From 08028b113ed1e1d04953d6656926318b42dd86b7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Thu, 27 Sep 2012 10:23:23 +0000 Subject: [PATCH] mx5 clocks: Fix get_uart_clk() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This function returned 66500000 instead of the correct lp_apm clock frequency if the CCM.CSCMR1.uart_clk_sel mux is set to 3. This patch fixes this issue by introducing the get_standard_pll_sel_clk() function that will be used by future patches to handle identical muxes used by many other clocks. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- arch/arm/cpu/armv7/mx5/clock.c | 36 ++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index c5a93a08ac..d7f6971a7e 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -331,28 +331,40 @@ static u32 get_ipg_per_clk(void) return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); } -/* - * Get the rate of uart clk. - */ -static u32 get_uart_clk(void) +/* Get the output clock rate of a standard PLL MUX for peripherals. */ +static u32 get_standard_pll_sel_clk(u32 clk_sel) { - unsigned int freq, reg, pred, podf; + u32 freq; - reg = readl(&mxc_ccm->cscmr1); - switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) { - case 0x0: + switch (clk_sel & 0x3) { + case 0: freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); break; - case 0x1: + case 1: freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); break; - case 0x2: + case 2: freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); break; - default: - return 66500000; + case 3: + freq = get_lp_apm(); + break; } + return freq; +} + +/* + * Get the rate of uart clk. + */ +static u32 get_uart_clk(void) +{ + unsigned int clk_sel, freq, reg, pred, podf; + + reg = readl(&mxc_ccm->cscmr1); + clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); + freq = get_standard_pll_sel_clk(clk_sel); + reg = readl(&mxc_ccm->cscdr1); pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg); podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg); -- 2.39.5