From 0991701a27e7f1de983ff2250dbdb88a7c8c60ec Mon Sep 17 00:00:00 2001
From: Anton Staaf <robotboy@chromium.org>
Date: Mon, 17 Oct 2011 16:46:06 -0700
Subject: [PATCH] powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer
 alignment

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
 arch/powerpc/include/asm/cache.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 53e8d05f50..e6b8f69b76 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -20,6 +20,12 @@
 
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+
 /*
  * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
  */
-- 
2.39.5