From 09d25782fdb2d095e573585012f400006858a78e Mon Sep 17 00:00:00 2001 From: richardbarry Date: Fri, 17 Oct 2008 14:07:17 +0000 Subject: [PATCH] Start of a new ColdFire/CodeWarrior demo. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@494 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../RTOSDemo.mcp | Bin 0 -> 53386 bytes .../RTOSDemo_Data/CWSettingsWindows.stg | Bin 0 -> 4506 bytes .../INTERNAL_FLASH/TargetDataWindows.tdt | Bin 0 -> 94264 bytes .../bin/MCF52221_INTERNAL_FLASH.elf | Bin 0 -> 99036 bytes .../bin/MCF52221_INTERNAL_FLASH.elf.S19 | 601 +++++++++++++++++ .../bin/MCF52221_INTERNAL_FLASH.elf.xMAP | 309 +++++++++ .../cfg/MCF52221_CONSOLE_INTERNAL_RAM.cfg | 14 + .../cfg/MCF52221_CONSOLE_INTERNAL_RAM.mem | 31 + .../cfg/MCF52221_INTERNAL_FLASH.cfg | 14 + .../cfg/MCF52221_INTERNAL_FLASH.mem | 31 + .../cfg/MCF52221_INTERNAL_RAM.cfg | 14 + .../cfg/MCF52221_INTERNAL_RAM.mem | 31 + .../cfg/MCF52221_INTFLASH.xml | 48 ++ .../headers/MCF52221.h | 89 +++ .../headers/MCF52221_ADC.h | 201 ++++++ .../headers/MCF52221_CCM.h | 46 ++ .../headers/MCF52221_CFM.h | 84 +++ .../headers/MCF52221_CLOCK.h | 84 +++ .../headers/MCF52221_DMA.h | 150 +++++ .../headers/MCF52221_DTIM.h | 99 +++ .../headers/MCF52221_EPORT.h | 123 ++++ .../headers/MCF52221_GPIO.h | 475 +++++++++++++ .../headers/MCF52221_GPTA.h | 206 ++++++ .../headers/MCF52221_I2C.h | 62 ++ .../headers/MCF52221_INTC.h | 331 +++++++++ .../headers/MCF52221_PAD.h | 92 +++ .../headers/MCF52221_PIT.h | 57 ++ .../headers/MCF52221_PMM.h | 44 ++ .../headers/MCF52221_PWM.h | 142 ++++ .../headers/MCF52221_QSPI.h | 86 +++ .../headers/MCF52221_RCM.h | 48 ++ .../headers/MCF52221_RTC.h | 83 +++ .../headers/MCF52221_SCM.h | 202 ++++++ .../headers/MCF52221_UART.h | 202 ++++++ .../headers/MCF52221_USB_OTG.h | 271 ++++++++ .../lcf/MCF52221_CONSOLE_INTERNAL_RAM.lcf | 133 ++++ .../lcf/MCF52221_INTERNAL_FLASH.lcf | 140 ++++ .../lcf/MCF52221_INTERNAL_RAM.lcf | 133 ++++ Demo/ColdFire_MCF52221_CodeWarrior/readme.txt | 160 +++++ .../sources/FreeRTOSConfig.h | 142 ++++ .../sources/FreeRTOS_Tick_Setup.c | 137 ++++ .../sources/MCF52221_sysinit.c | 86 +++ .../sources/MCF52221_sysinit.h | 55 ++ .../sources/ParTest/ParTest.c | 133 ++++ .../sources/cfm.c | 21 + .../sources/exceptions.c | 626 ++++++++++++++++++ .../sources/exceptions.h | 67 ++ .../sources/lwipopts.h | 238 +++++++ .../sources/main.c | 449 +++++++++++++ .../sources/printf-stdarg.c | 293 ++++++++ .../sources/startcf.c | 312 +++++++++ .../sources/startcf.h | 74 +++ .../sources/stdlib.c | 509 ++++++++++++++ .../sources/stdlib.h | 79 +++ .../sources/support_common.h | 35 + .../sources/uart_support.c | 298 +++++++++ .../sources/uart_support.h | 66 ++ 57 files changed, 8456 insertions(+) create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo.mcp create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo_Data/CWSettingsWindows.stg create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo_Data/INTERNAL_FLASH/TargetDataWindows.tdt create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.S19 create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.xMAP create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.cfg create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.mem create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.cfg create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.mem create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.cfg create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.mem create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTFLASH.xml create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_ADC.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CCM.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CFM.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CLOCK.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DMA.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DTIM.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_EPORT.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPIO.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPTA.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_I2C.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_INTC.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PAD.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PIT.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PMM.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PWM.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_QSPI.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RCM.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RTC.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_SCM.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_UART.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_USB_OTG.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_CONSOLE_INTERNAL_RAM.lcf create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_FLASH.lcf create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_RAM.lcf create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/readme.txt create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOSConfig.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOS_Tick_Setup.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/ParTest/ParTest.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/cfm.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/lwipopts.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/main.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/printf-stdarg.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/support_common.h create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.c create mode 100644 Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.h diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo.mcp b/Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo.mcp new file mode 100644 index 0000000000000000000000000000000000000000..28b292be25cd1959734489f4caa5b0f3d318ccba GIT binary patch literal 53386 zcmeHQdypGPnQwcX*s-0&36KQHLtZD2~Q9LGr<+gh#GR;=BXcgK$;PGqe#yDP6= zk+ja*c{$;LK)B=#p@vDB1at@73!+EI_m0xg5vcDb=;$l0t)W; z>-lD+(T+5mVr}lMY1ilesrys+^w-~`ce+PYtWRrf}3w{at3c;U6eu>~$k*^f|6XdG|FUJL}7JL)%rGobWUncl|;L8O+3A{$|3&2+h z{si!qg1-X%I>A2ze!XB0@C|~m0_K>RHUM93Lp2P1jo=yJHwu0h_)UU80{mvdF9TmI z_$qQyA4$dc!%I;f$tFfIpCdwzYlz;;47hEcM0AFe7E4^z`F#$8~7f< zp90=3_&dOR1YZf|+$(qoa7=I-ctG$8;JDytfCmM?1e_53Mc^U9-vr(#_c47Eg!CQbQ1Sf%Wf(yWT!Os9&f?ooj6#O#ql;CdzPYeDfa6$0Za4aVT-wiw? z_MPMhYyaRYv%3lJe4`up1 z@FO-*+j4S51Y`+}R$F`V{wJ?I7y zhM;3-1o>Lf7SKiz%uw6j66Exmv_0C~RuKJB473+SA6f#@7KTCeqh%1q0~OXbID(vh zs}HmebQ6fNhOuWmh_QgNfpLH_We14y(9y&&50D2P7sYS00YW6$)BDG+U%{t#|L`^a06ZvgE9-3WqtYk! z&Vc@y6OD;<`~yCD631~I#5qL!2Ic)m5OeB^p%DPmGAxET|KB-!{g=K*B??ndN`SgT z`(jQz{Soxx6&hq)Vttr;TLSPS#!?V;fqz9Ch)D)qlCc~Fw`5!bLR>IbfuKtUe4qip zW5C}Ua4`nrgMk=jAVwMRpT;#H_$LD~$v{jp5R(kVBLnfoKs+%bptT_QdIP@GfUh^; z!wtj~1HRLM?=-f6q9DW)V;ksJP(SE45aNM>IA|aS7>EVNP7q?F0l#M;Mi__{2I7PP zA8)`v8+$=eeFJg9h=T?}hl!Tuit3_xEEQ^ww;G8~~6`mqbSLu|>>{UN4{ry)MAq=opT< z(J`BL&iKSw#JEcPXMDgs>GcHWN&lUUdD3wX^E7Ymz;%NY_ane-L6DP<;gFLXpD}Mb zMz2TC7`y?*n20%a;~(ZwuP-o%`fp2)9doGTI_6NXWiW?2o?{O6`i8NKaUOH1V?EfAlR{9-yKFy zy`dhDf{ub706hr04+MXp*L-8h4}#zm^xwF9k;g$tKxaTpK$n14fG!2m&MpGI33M&! z1`utI%Pz;(Xp^+ht3XRZ7lSSbT?2YEi1zkI&@#{}(3PMoK+8e2LnZ@swMM_4|2Xbm zPn-j!HVa*sw%&={3Y zYtyn+VWQ6NSP2y~m_ucB4)xNxUpZBd>O~c#`jDuqR6D9IiKql!}4&HPnBnzW9I1ipjE2eHC~ym z<*bNVv#ffvG?vR*^?D?oZA`b64q6klQ&UzgGB#Uo6iQZ;-^|vgtVU$qYBUPvsg|z{ z6^d45I9siHiw9;4#e5_&*QjM%nBDg6=9dZbdzw^R)8*m)oltJkg4L=j(3XUkTx*=W2{%nuc6 z&@b$0?6bJpV)vcBicW%jW)gb65Bp;9fdfYxPyLoJMm9>(`M@Pm-Q;AG+#7vBh#8R2D z*s#~kd^tQO=gZ+vfn$EYTKf$tamU4t)ctDEp;Xmc6ec)aezm(%M?IYA>ug>d2JRDxv(O%Vb8SOQ; ztMHV%bL-{VsJT~fCrFhtUOx{!PX~r>i4@Wl>_b_%c z?V(g`e7|?S;(pJr^EYq1&YhHb25#4PG;zDSgOS^n{$}3RZ@Zz})&8b#*ZCT|RCP6X zo2R3}+tuAoUYcnC^P)}QUCiEYz{AkV@NL!r)0Ycs`Lm<#S~{7({YBqDLE2jA-~!y9 zeVl+>*X9Q7a#!cNIRcxtyDPAHf}DYHb#(_ePbY^UEp+_DrCnh2|9olV=p(SP;V$VN*yVj&ern$TYIuFHCxN_k4xNL2vaD5Py+v#CE(oQP`IsC z=Z(9ml2yijf!|*NYNS%Olqc$Y0*?Nh*Hh9Kf;@q{Jzl!r+gUNV1ro}=YXZ;x%8siE z+;UM~AE|H;GHMkk)$oys?Uxw|Rjgi$=nxIBj~l(X8CI%RYPb)jCJNkgmJ)6&Msun@Tcv<9xk{;2DMzQ3BbOGKsh_GB%7uns5n5NF0GiK#NAqaa_YzL&kT>JP>{pT z&q~qC6e<~9Le9N<|5+{Opf6qLJvTWOz)`YFT9@2*T)l*n+8XKf;HmNS?Wytf>8a`5 zmk#W@x7=i@b=>avZ4Uol?K=N{?K<{ctrg0R$u0Fp9{1#_Dvf-xFaa=x%>_D~j9JLd zWUxsvTWu+|7Y~^Cbhc(%^#-a2ij~~VK>%o3!!F8O*o#2PWHDQ3j=S&&g&VzExIvD> zbfsA2*AAvFYX*7E%9Umt)*K-2>`P1gO*74{4-^)$m_hdNtTk&PZ)EE;b>vj=Y`qj6 z*GLLV*<7uHt0WULXH0;)m1+B1*gZf=6%RXLN2(5Jw+&slO4aEa3dS4R+{`c=V|CrC z6|zNuSg|osX5lcNM$%FHWOd~}69tsG%bE3DHGYQasbl64Z%gX5{fb~#~~O+6Qs z1-^pM_MA*N=S0gyn5V65HPa7Chw1!Dz}Zgb{vh`TnYg{peMTm3jdL%NX$y$^iA?<< z?nyH30dYT)iCgyE=VU5@*e(-~CUDP@>75|%WimYv;(jL6$3Wb(WcoCS`;|A*vt{}NVD8&8y$H;`Tc*DTc8(0Z49vY+rhf*GXr$CnfY%CM0pWAs zmgzcR?%6W+1K(&vbtmvmg6{=hFZdAf&4QPw5-N2g!zYln`;Ew@w zj+s6K9JQhPd*H2t{{?uP;2!|rD)?u>)Cr~)P@dats5Sy`7n}mdQ8As$z&ixL3-}Jf z9|GPf_=~`I3jQYWU4nlOe79gK=Ptq50^cKeC-82;d|Zb*%9ID*s}b}QI41ZlzypHc z3mg~x0`Q>V4+AFz{|)ev;7ZdCB4z-hs60H(b$T?ag7Lv=IoxZo(TDflj69>rmb0Ux%ZN&z1cJPv$R@I%1& z2`&KNFZf~L2Lzu6J|_4X;0Fc22lyeu?*q;V{xI-y!5;_C3jRFsgy2_zbArDPoEQAB zz?R_e15XP6De#owUjR=FUUqTw(UjG|C#3u;;2FU;02c+{3{0QJ6a{wfV%!N_v5Qq4 zxGH!A_+i0Efop;%fa`)!0OL<8ooc|df=>gV6#Q1;M+Cnccuw%S&ftD{JX9@(?E-`N zznz*$#|0h@4djDa^7v>VA5_~|zW_c=r9rfE5Sz}8`Rz^@X`MU@vR0QeRB}srQoBV4B|r!>kfl)$8Q|1*M~I;k5vcqVZFkm*MWRk%kX%1AYTN0jB`QPw-$VifkAwI;A4CY z;)Ac^QSm@N_$nSH59EWdG8kur`i0Lh7+?MPQ0yl741=*Zhz~x)U|bI3gU>J+vxE5H zGYrP_AU>@1495B(KCA-`t^e^3#D{gK!F5Lv-|gT# zz5u=*;L9$6?+);BEfdu5PVjM^6U2u#u#sN?AJ)f)wE#ZE1Y>dme257K*HuB+hnQe+ z%@xFlm|zqZz=xP%oLB(gUhvH(6O7UV_z)8et__36iC z8N`Q}U~s(|#D|z*a4j0dhnQe+of^c4m|$=X8^nj0U~qjK#D|z*aP1q!hnQe+T^z)R zm|)Cx;A@S8Bj6ib03Tw9F}?sk#16ykz=vWt{kHhr3kX3dflvbTB(M}Et^Q#iLs$?> zAe2BTfgX{-8X4y$*!@`zd=YMyFL8H;dPE4}FuO|N*GRa}i@3Q|@hm`?LJ3d;)Qe@v zsTVvy5~ffBlmPVtaYXAyT|Z{bI}Ty$bqP=}E`|{3FL3Y&Pu7Nd(d#OBcKdVzBoj$S}D?1uw- zPa5Hf9SJykv9hTb;x7v2TyZwfJ<>4so&+4dScRc4#XskHn#{QUJj*fs*i$WAD_G%D zwC9wA>kI4$?e*1*QaxN^^qfXu&51EnFL1xpUoV`e6?;%Ny*y+`FL1weFYkqiDU?7c zflvaW1ng)0JkOKMgYThiLJ9PW1iX*a_sXc7E!-YQiGu!5OUw=%-|{89nz4u?Vjqnk(@U#dDsb`AXOMS%eEnvkm<-SzQ`iwD~zt zhb5!<6|OGB@&4>xH^zXvC?9z2k`_&F{Dr;qkfL*?Y}Wwvn_t5kHi3RFlszUp{+x&T z(edXz975Oq@W<^gjI`zwya@?^l7%UhKq!Gw0-*##34{^|CE$^OeFlGt`+J`}F&Cy# z0+hg#B})~52|SdBR|0&VX;nHgoQ#i+W)6)Hcx%H?p#*wE0()=J6Ay zv1BaO8)FYg*_1%9D*&HM3QBw@wZo%dE#iC#^H2hz1VRaf5(p&_N+6U#D1lG{p#(w+ zgcA6TBw*jy4sT}vMnVj~d_hQHDGz~!+d3D-T!w?_4GFvs?;LnNi0?$=`;Pc7qiaBX z2NB;d#CHery+C~D58vm5Tk%E&v=-C{S_hghsa<<;{4jD7Kf;H1x8KuuYjj)Rp4}^V z*>86Dyx6^!>9)SzD5k-^y5pr_Mj;cM$HUCSlrs>w3mZd@$tu{-_FuZd4vxf%AVhnXB1Hz9|3 zCUG?FxfE~3YrCBIbfM~8fb$Mwx5t4|j5^a=?8-d8Kbg*?lH+CslcPTj#fFoq`!a|7 z-IBxonejsdQZB6=Wo=u#!Bb?v$=kWk^!jY6dUqm%jnv4%;BaJkw%8~X3+1M$@DlEk zOgaGu)O%#bnnavB)Vz8RbMVEavgN7S?3CqPPTZAODmJn&qd&TG(nXG(q&~O{TNRuR z_=0t}4^e>3$f##rQcUT#a0K_X{|MB*hF2~-oej+vi;;l}>>(mQe&lw&|40T}KV}|E zXZ9aSjwDUb6*Oyk5zS8yZ}7E@rp>z5a4sZ~t)GhMx4pX;0ESE=Hh!O{Ulg)Kw+{X6 z+Unzfp)G9wb@v1lWA`r_jRVITl zKj$n6`- zJ#V8lONG;GJ)ZE)%&|@ebm2Vb(&LldW%!{D;05DdY~VaRQ`Tj6!m9Hx0Y=70@gu?2 zLeZ){j^C_m;KyLgjVEUqaNg#Y?e4a?cf=~iIDSUq%c9NE(J{A}Z~RQ8l0yg+ zM*7g$K2|VfEVp0IRp*m&tjC>rgZXO7d9sC{dAfx;Pq;AWDHo?5z6EaOpjE0w%xrz8 zeyKFYLoj6JK^W#d48xoUVwm$#409fgVa~%b%y~eDc|`KHlJl^P(F3Infe3#_+NWNS0J(BO0JSO>oqb9R=AaeE4l!-RWk@w@4n9e5>T!B)?Vi zG;*hX4q!#negjzD(NOIC>xS_z51pf2=ePi!h-X-Pg#t)o2vTQ*{

(-#VI)~D_tx{C0?O(}{4B_@;orc0MVGqw`LIdhDeN1A? zs@ZJLd|=;Mx5<-X&V_Jv%kVZU{iB&@VLb|#Rcm;E@^}L}I)jFbZRI~hi)YY!xvl&x zCP85YZ0Cm@nWVEY0fkYpo!0VKX{pjqYx#43r4;A4(5RH837x$PE!v>Vz3r^Q99)Zb zic<|w`dL%&Wtt?jQsJG>+u$nx}i1LX4}%d6h5!H*f7v})DuM@^N*cbWca zSgGxBZ!Ev$7E?{w#cKIflmFQ7m?|gbR~Iqum>2T@ZNgM}Dc@96>h~c#mVf*?Q(02} z*(Y&55D?4%YmccWrTklON52pN%fI)#rb2f*z3y4`EA2nF&s5V={tO07OCbLzo;OuN z%IDzKmtnjtA9%Z|PDuH?zz=V&%m4F(rkauRb?;H?y>gw`Y&8{zqtl1L-v`8Y-uaBF zoXPyu3osP_kgJ$ zmh$I5s?<)o{?y&3f*5uB+9#nW7%=&F-exLobf|d@?ISAb^5-W^)v(#sms{jBgYnKv z`Fp{SD$W1n7ff|h%3nk|^_J~_{T-%yM9Tjh<&NBbane+CQvOOyJ8wH|s#8+_lh2@i z8Q1hSQ=OLbuYXLbl#FXt-c*lD`E`Gx)I(DK+>54qOv)caR7OHLP&OAQ!0aKlk@|9m!>iw9nMm?2|{Gq9ylJb9i UNvW?w&c$l2dZ^!2PfPj#0z70sYybcN literal 0 HcmV?d00001 diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo_Data/CWSettingsWindows.stg b/Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo_Data/CWSettingsWindows.stg new file mode 100644 index 0000000000000000000000000000000000000000..9cfc047a1266ccb509b920c02d9efdb95f681988 GIT binary patch literal 4506 zcmeHLPixdb6n~p-wbXx$=&gqc3Y8wJ?a7nYxURysESsbv2okchZDcnSCJ8NKVJU*w z#Y54nAHTd}rR`tJ-}gxN&fWjD~u<7pJfQ(Gc2 z+d*9VjhnlX7xqNYY$=&WnUQoLJdu7n6k*BRN|j>ZWGdRUY>t*RqT!CUX`3A{6a%tl zs(fL4eSwe?{b{74`lgD3bIAaX|4eS;Y2^L8(3~e&EHs@Ny6Dd`2ziBeA?qQBKu_x# zmw)0^D(0B^XHJ=W&8OxY&_9)WwtA=Aa;{>X=NnG5yRp`O{j|MiKg$+2@-Q&yD}AG; zu~NSd+*-DlmiQ!(l=MX$OQi$n60Eayr?zkG8S^uTh>2ei#E*_LqJ<-#dGyf#0~Pyb z%V{##4g76S^&X$*P~jB=6$2FmXJkO{r{8Xdc%X)Y|b%QfI$`O^s z!!iR6lqw@IG?>80Nckf;h7&m7I6ML#r^&FC__N!GMc~1N|G4C@iwn5XVF@q)V;gfs zw_xuJ6}1kWqTYB3{Bn-}Sa*sF_W^J-$A6X<5WrV+eEqXqRKfRw^Ljl0yALi?lF29F n?=fKf`&+lDju);F-N3wzfBEPZ70x|ewHVj~$CeePaS}`B`_060V)+rrand|2%aWs*vSdACCs9Jv6lKxYDO)9N*kNxp}zjF`Ich7eo_nbrOa&}=M?KBKyr^7JLoOc+nTyPj) z-DDX15!dE~qQj}|{M5oz`OtVOcP>*19ZeNd)~O9~96T}JKYF4!ksL_$jy-tK*uqjS zoe7QSGMT(lajrL=&gAorTId3E>rnl?cT9Wp^%+Fx9aT! z+1X5JD7Cm)?c|ZA?Ceyi|572BTJ^?dyQYCkv!j{0g+eBzQdOSoT`DZ>E~si>b!t8} z`}8v?P2a-&d?sDUF3hj8+_#i3EX;+DXP$m)Avd+^^w7aW$3wmOd}i+KEHWBN&1YsS z&GaqIP7P#p8JL;M9LvmCoLq_8!%mkimW^}(udp&>aA6rq0bJbvh$%@b&SmWFQqfET_ppY9Gov?a=E3&LZxY( z8_nc1tKygIeq^w3*=lu9UpjQK%y{)Q{Rxyln@`oRGc?0Y4$UKEw#w@Dx~K29+fb=< zi)hxXJlQ{YHZwJqnF>jb)T^>SmCZ;lvzS|up0`jxtC8Hod9>9^@97>rfVPIVq5D{M z510l|rE>GC8*Yg4&n~3xfsO6~Op#RZ;k8Zchj5hnlZ4X{YsT~x^lKy%;Wfx+r5VOo zaonQyzs9j$>wkyiR;_P_p$@I@f_|;m2cdUreGd9{TK^dI_h|hq(686}kD+hV`fs4$ zpmjGc{zk3e1^p(iKL&lf)-OTt()w%AyS4r$=sUFjBj_%z|3Bz%t%uW4dQj{C3_YZET)y&;_)E$y$DIPKC^2UnU4fZ+2efr_a?qH zP92$DNMAS!1->tsQBxVr%Mmj@o65@(^U0GsHLPYZr9N=I5>lrg9m5O=oq)c2fU&v(_a?s7$Z1UlK zDlOi!lJH1h-{ii7N3w;Z!()>Jv-z2QhYqS#bE$N00c8^_I80{e)3ZxcnPrzCPF>H8 zX&*)rg9*|3smyd9s(F=YK$*G4nH(a<3aRvkA<0!v=QFu%Y8FcGY~jeP_)M$tpQ)NI zQL(1KW-RZ{7-z-Jm@6ZtcJ%%gRcTo5z_O@0)A6FsEG$UoW{u$Z^n7YAn?}qu=7WR7 zqNqxeJG1hHv#W%`iBvhnHU;IJVllTzOK zrCF)h%z_Lb7gI^yO4OT@sl_Z}#oft#A-81t-UKTzq(Ex4BPe1Fn(5^l8LpZsNM~8aLaiVv0yqpL3_m$(xv5~=Y9v!FCN5=;#bBsiE z{@93WOUuSbdXG|Wd})1*BSVyTUt+lLc=@~gM~3;@M+T`Vy+Vra*DE_7(0?2 z9zRxYpl?7@^z=;Pzqv+P87-<0EBjRfYrt4DwW03;%fsiSj!0S~m9{IbKn7&96+p8h z^qol!(&kAt2xBUHQ8f@WEG(1EcZr5~$w9Y0eO6_Gv1keHR~mKSJ(K;DM>7{Ets#H% z)I#n8-qyFU`1Jk;9kI_WyBdq9^e|UAKPMwe8tY_e8240!GH(ss=;O-+H;u>U4ZJzm zW>%7UpTHEu4z>qu5B#2cK-M4WUf9IiF>%aFyx7L3zL$}s{pM-9$|2_xZTK|0+y0!lM26Suv_dV#=`cKxK z*81;f(5>~~FQHrOKLdre)_*SO*81-NbZh-L0^M5w%|f@dPt@YM7p(4^pqxDyy@74Mz zpzqWA8_?zR6$xK}E^S4^pF@|nBH`abztdEWH=!TY`gftuK`cCMFwSEWmUaj8;{fO2dgx;t1QRqjt z{uuOrt;@Q9KWF{e;%P z4t-eb--14(_3uGHsrBzeAJzI#ppR+&e?lME`Y)kRXx)KM{jk=zLYKZOAqxGpsTzBs zKce-+&>z+M5cJ2i{si<%tv>_(ajm}y{Rypq7J5?a{}TEct;=U}DXo7U`dO{N2|ca# z??9i@`hSL=(fUuIPiy@b(9dc8H_&Iaz6FC-R_oV8moZ3!8~O!PHFiRu)%ro`b6W3* zKCkt0=nGn(g1)HrJoG2E{sQ!z);|S3ul3JEFKGQQpf73tE$A1u{(b0AY5k|rFKPXk z(4W@&Z=gS;_3JV4zEA5R=+A0>4|Ew@CEO4F1Ey-6fc`(@blS?gWUU(tFP`iHf?3wlZG`=NhC>-RwasMhr>EQ)%pVTPip;5=%3R1cc6b->wgXXHLd>$`X6ci=g?o*`rkwU zjMlGhH;gy5-s%IIs`9^#aWb~am?mSH^hN1w(w8vIt9y!!Ycifm+2vZdK?0D&5EAtCP)x+6e9H^e(Z;|LC!+1hjc;)AQ{LsBm_AI zc@T0VWFN!}@j${58SBO%5r~X+GREBk*$+YURdWPstJ2ns5NX@e-=yD2+m?PJ?N|C* z9?}izg6x1uzmYaCeM8!{^g-!APeP>sZiS%gRG*c$o`A^MC1aWNd#k^vpv!pWgUDDL zg~&L2JLC?Cw2xho9>_4n1vvnTK}H}uA$LNYkT~QdMEc4>$jy*Z$RUWdxlcjPK<>+Kqkd;sBGbC!J$ekHMmV(muTIpHbrw7o6rnR4XsCO@Xz5cbym)Z zv`IRpIaEzaT!*SR(VWUVW;*ec)Q3aGNlk23n%UmOlakInD?aqg^&LK?;zg7CHS>Ex zrIYJ>NokVvXCU12Wf;uoa^!ZWA*49(EWqO4`Bpfa!tXBH-SO z`(_(Hj+NPs9c&L6hO`Tr_er~u&(G~(dq6xO?ZTYJw;6f$#ba6V*omv*s5w+lU9OzQ7M+3wk(9*{j6X&176CF2FYP12{nk2pDm?;Xyi zW;du`HhQtGb|HJhx?L=P(P*RlW+Rv1Y8SE#%;Sai&C`wSosC;|t6j(^3vKvkeMc}k zW`4_Ez7(EI<+2%jD!SnsiOetLQ?07)0$&W?a1OBxZ2T5Jkai)THCAmG`pd?)t2UMg ztac%vH_KkQ9c&NS9gFYonK~K+1MVq z2Hyx>>z)vXi_Q*@4)$bo3un*Q_7^|PV0Ak6po7)X6f=Ihf4m2OzDSW3Ku<}iI49V! zophBqmqj(LJn7ryYr!=`^X$|wQ1k4_H@|C#CfccMsCjlSU8-Fgd`F$0(Xl#Z!|iQm z^?S=>nqX&}>OV6rZ*SVpVyo*%+i7|In0D|HM0tHw>P;ATOgoF|x-Fpz?VzaI0qoRk z2~D%J#-4l={AQ@~C2Km@>q*Hp=srjKkBLznr25mrK*mhCY|cJG?%J-1G;iM z+awFvxmrGBGVed@P(NzCUWYHCD?9RVud5?$JFzgIsaF*FoIHnz2h~f{q;rQWp0#Q| zE43_hS=1y(MtaMlTBR<|E-tQ%oeLiw?rT*c%JSWo&(E%lo$1{9hsx}>O5JuOu`X?L z+dyJuJ=*@ZqkX5=!_H#g=$QPua;w9lIUZk`nFiLm=KW=j{f@P+qH#M{Hr;I8&XvtF zF2l|h8EV*$JZZ1B!E6VaOIK8$1}@RGQ+GAJb}kM3ZKlxbiJ)1Y^Qnt#EJ5oQ>Y=sY zZrYioyDcK z@~U^f;qu5sMy?=?X5TeU(&7i@P+D^;Ajk;}MxbJj>*K|e6LW@~>+)b;) z$iO<;SxPUg$DY?>I+wq~R^5=x7thY(M_<+;+Zy|l&9hVQ)9WT!(T~OKc_w>>GoCfCWt;xRpH+J@);s0zC>mMwjr8qS zKP-el+B1JG$I3t-8@RV?JN4IM&9hVgGsouHssEW{)9kFVc4>kgHCL&q)>fd|m)BUh zH0?8nb^8pc{utP_@~kliHp|Xh72k~Zw$*Sr@W*|2usvXV!1jRc0owz%2W$_J2h8Wl zIMh>Q%@g*s49P(o7#xl^^&58^*acOKF3;q;cBFr3uy1rYiJx?;n#hi{J#dwK;IKS2 zACF`2J<>ZqI(#BI);~Jfo4CpgZ5MBq2R3>GkS!K_o5lQ{hTqB$P8gN1^7OH_f&;-y zqkcZu0{dut!1jRc0owz%2W$`694jirXRW@> z&juuc9c&M5Y!9@_4v*avHg+ShOOIZ#a-Y~_Sa%A`G0V3QD`LYP-2$jcpyie+ObcqzXvY&&L}H0k&Pb2Z|}4I zDCYh0Co=d2lKH~!`9e?TQr#!CTwR{4@WCwn(6=y^IhD%gvJ30+mycJMJMGe31s;&G zVf7ekj@wLNusv{D z9=Ngb)Yi>*`L2t%F2^;V&DE8%+<(`YAG;YLxaHSIGMO)=a)qTPJ+Q!$OkT{S3%4he z>FKNGnVgr^6!g5X;^q~_6W6lynNZ(w;^@HOXn*qI{mH)Jqy49PM@I*TM-BW4gTtt` zak<7{x?k4i{XQq&@V)f+xpM4lvpryY!1lm8d0_MMcZ19gk=15Hh!XMQmp+YlQ-`)H zm_Ia35Rj-ud;6$4?B#5!l!h)(+=Zi;YV;@j*mKw{pbJbE#onVu~T@` zVH~>drnih;4&$w-|M?xq<6wz@!eKnPW8d3G(qVk66X(z1eG;G2$K5*p4u{cxD)4QG z(_s`xaonVjXB|f86RCF`X@}7v$0^MjeVo?EbNV==(`7ZE*L*?qtUk`^_<79>niuu) zNgbcloY!2?$0dEdsLx;HFg`BVeY?Y$J&xm34rBXp;M>kyb@^`7#~yv$qmKt2#+%}= z`}Fa!J`U*PaeX|dk4N-zP#+)CN4;gYqfNeE)`qqq^9_fwnX#R*gRzsbi?N&0#pq`A zFnSq%jDE%dV~{b#7-ozxMj2y_amEB=vBWGr(J*$jp*NO0n6aI)gRzsbi?N&0#pq`A zFnSq%jDE%dV~{b#7-ozxMj2y_amEB=vBZ3hcCd_TWi6Poow0+lld+4jo6*JSX7n(6 z8GVd?#sFiGF~k^Vj4(zSV~lae1Y@zpEPr8dxc|^c*sXe`HKco@rL@b#09V>eC!;hm z!?Q)d=MTN?mmJ2?<3E1WVMxWI)SIu9*X7Z^ld(h6{K41vwN`yg#p0gUaXntk$}Eu~ zt5IAn6@9tWH$!S3;Rf@dcf@WoX}cUcp4KzE%gy>3%qV5XX3hNG=P=&*habLW7+sR> zAAIwA)?s|{)8F`}!|0ac++I0Rw7GUQHS4_5EihMm-eyI+7u+saU>pfWY zRP3Kx`=Lfas>L3x-lb~kvwDYmc%417dY7uf>K)dn1?n>-d$4-9?j2TjSReLSAKDmU z8LakHt_x0F=4W=+I-+v@VXZ4F*C88iong7%s)mQGK`J8dw{PL^(jZk?E!IbzMpUY$ z$6jx&&w9i9MB0dn+YhXl+lxhqagXdL7oXE#IVe7F#k}A!9+gv-1EV$2Sp(Zf8_0?; z>RGQ5m%6%l=w1Gjht*apH^M4!ICfpXMlYj}(a#uQ3^Ilo!;BHe7-O6|N7# z7uoYOh8V+)5k?s&@qLK+A}j*DTSOKr9@#yDU>7{qeKx#_4^Tfta;nzZZuTR^C~wSD(8Ln{N4Pr z!}1bqNY~NBx{d@LMx0R^lVNOclV3!aCLsYI1u|}D>}GT^x*0u;UPd3IpE1A~WDGHe z86%8Q#u#IqF~L|YF-zYPpFM)tGM_PSXY6KlF}fK&j9x|`qn|Or7-S4Fh8ZJ_QN|c! zoH4;zEHRI0pFPSxW8BWz&FEruGkO@kj6Oy`V}LQp7-9@FMi`@vF~&G!g0Wa)mT_6y z*<gxlxlM`B9%r91ZfERf zbTPUaJ&ayPAETc!z!+opAsS};!M2s^2NSmLbMBR)oMmM8}(aY##^fLw+gNz}@Fk^%< z${1seGbR{|C1x36#4B0$3ZskB&FEqDGWr<(i~+_VV~8=#7-5Vu#u(#_3C3cHS%y^c z%6aw*ql?ka=wb9S`WXF;0mdL>h%w9}y7~_ly#$t*2j5q~exq#P|dr3E=i_y*K zVe~Tk82yX^#vo&eG0YfYj55X;x%;_6nnm(aq>#^fLMw{fq&|AY+Iz z%ot&eGR7F=j0whKiCOL;@<*g|+A9tm@mIQx?Tj6aos3r(Z%Ry^e}oEeT;s_0Ar9b#299b zFh&_;jB&;UW3j|6lVox5lk8x|cE%3IPR1_AZblcQo6*DQW%M!n83T+##t>teF~S&S zj4{R;6O6?Yvn(*g!8vv?V>@F9V<%%5V>hFV(aq>#^fLMw{fq&|AY+Iz%ot&eGR7F= zj0whKiCNYv;@~_xn6aI)gRzsbi?N&0#pq`AFnSq%jDE%dV~{b#7-ozxMj2y_amEB= zvBWIP9&vDi9n9Fy*umJz*u~h*=wfs;dKkToK1M%dfHBAzVhl4z7^93a#yDewu~=f3 z6_hx5i5<+?&e*}&$=Jo%&FEruGkO@kj6Oy`V}LQp7-9@FMi`@vF~&G!g0Wa)mc^Jj z_#!))v7NDlv6Hcjv76Dw=w|dVdKrC;e#QV}kTJv%_sA*ujkL zj2(=fj9rY~j4nnuqleMU=wtLV1{i~kA;vIcgfYq(V~jH<7>gxlS=Wh!pJoR$wlj7x zb~1J`b~Cyd-HaYaFQbpq&lq3~GKLt#j1k5tV~jD*m|!fHm}Olj4t|Cm%-GJ@!Pv>z z#n{d0VstZl7`==>Mn7YKF~}HV3^PU;ql_`eIAembSYnoSojCY?>|n-r#tz0##xBNg zMi---(ZlFv^fCGw1B^k&5M!7z!Wdk%-GJ@!Pv>z#n{d0VstZl z7`==>Mn7YKF~}HV3^PU;ql_`eIAembSYnoSojCXd>|n-r#tz0##xBNgMi---(ZlFv z^fCGw1B^k&5M!7z!Wd=O;fcE%3IPR1_AZblcQo6*DQW%M!n z83T+##t>teF~S&Sj4{R;6O6?Yv#jgH!O!8f%)yN9j2(=fj9rY~j4nnuqleMU=wtLV z1{i~kA;vIcgfYq(V~jH<7>gxlS=Y%&!O!EhWBD_=ZblcQo6*DQW%M!n83T+##t>te zF~S&Sj4{R;6O6?Yvna@dcgg6P${%D4h!pJ@%?jWp;+5 zv?zq4)QA1d&sIP4UYz{<5m5bj1hnDYq%UXubpQAR2-elfPY+mny<@T7Nt{CuaEfe( zE=_L5j>FjGz*7z$X}}ILkp3g@uN9oIA+iMt*bd%|&}eze>}*qStayRH#AnWS#7oXA z+YhXiUD{NFNkNm_!#idonwaSBfk-Bkqtg>TzyCFLb)DP-K>c)BPDm$j%8nT1; zu2mk?i`0#?bCn&ly)|T~f%2eUq;8zot+LbH@}OR%Zk+E~Wv99IgL;v=abCa5PIJqH zdXc(uO6THs-Q4n^UZifEH?-Ie@)sMx3I&Lu3ci$QaiI zJ5|TGn_xr4)nYr_VMD|XJJs638^8U*J2+K8G|*4GU_-=%oGR_e{ileZ+No~@XB)7C z`j_M_IEwn0HsJIlBe~bDv^TS# zK0ELqn^GRszqA2o05;@aS7}Fn5(v@tLj(1L`jt%T5JdP zFLmSG2|F?;tsD>JC)E&LKeW+2v1(eefx2BQ{Vs&RsR^^xSac+T(QtS zX=omT_pN0|Y@kg$?`g3ev4J-2d~b{Ghz+!9=e;eqBR0^co%glaj@Uq(cHZA&J7NQE z+9?}ut!!^%18v%QxW#tF2HLc==4YX-zUyJRC4YX==4YX7A8)(zcaoCZ)|CM>K1JvNU5lhUnd9Qk3<%`&mxQ8LzAS-t8W(4(9 z?MkctB6|X5b|jls0sThVIgK;b?5LlDU-d4IXv7Zsjk5Dd4LjhPU1TsjQ#Be0}_F&UH04Vh8<3*?AmquU0?JDi8XNvhxJ& zR4dPSe|F27<(a{I*J^L*H_A@3MtKtQ6#q4X_^r5-rfR#M(00xsT{XYm`>X6*D_K<6 z8nJ`^smhb8Vdr3jIH2rg zYS`I-{+}9Z2W!<2#sOt#x`v&dO)Af%wsWqAokQ2%)RgjIyiw(mK3%Q<9BNW|Fy1IT z*&22p+_CR%oT?id>8BWPl%4a)saknH)!7`sozZqK)UdO^Nq)n4qslYeVmlabl$|-) zX@gYW=Q^KAy@TkwLE6w-{U@#M%p+|zI~`53gYia{XQ76jW|aryjk2@YVmlabl$|GA zYzO0wvXg7E9kdl?Ctt%(v)Td18)c_Z!%nl>0md6;XQ_srW|aryjk0sGhMi`W2jh*h z^HhuNV7yUwF4eHpEWcsAQFflLVW(Ms!+4|YJX6C?v&w_X88@{jk5EB8g`mh9*j52&Iem;2jh*hQ*5yvj5o^8b2aQVt9~%v$ex&d zR%_e{DW8Y5;d^P@hu8kxxgGCYYaW8}MwRD9q`j%a4$wGy{Ks#~v0i9ozJu{b+4&GM zsx}{O*18enjk5D{4Lc7tI3F#p6j&~IRls^LCh z?LaQ-i=Y0+H|1C_G*UkpZ$mWx7WkYJL_cUGY#6Yd{ggOHXc+>_LBDTr*XF0xYOwUw5)z4n^gh#YgL!8;Y>9< zjoweoGOlU|_iJV6kC3q1cyPMG`}SJpc}3fK9d@=ue%J9}Ejwl9wN={#wg+qv*dDMw zV0*y!fbD@l5D&<@Mb=_6F_rbrHIU7aEs%D|R!9frT8PXCWqtV`$n_AJd~ zP3D?ikZ#BhhzsI|cpzSg58{UeAVEk75{AhBEcP;tMMwk^g~T9n$jy*jAhHg=6|xH= z>(AREvOesA$o}D8$Uew^$Q_UakUJpmxUdVlr`ymfN4nuk&M<9KW zqmX{c0OT0tLC7HFA;@t^0x|@_df32P)fj=Cgp5MQAmfk;$it9RkkgPyAdf;GgG@pm zhdcpELe4-^kh739WD1gjOhe8=W*}L}dB_FGEMyKc4_Sab3CTh7kOJf)WC?;jRs;K= z2KFY^bAzy_XJEfgJpst_dlCE` z_9p$jvb|buRq_#8kM=hJJI5e$ozl0Zk4s;cJ}o|xYZw1Wzm~o$eO3Cb^j&Fl(wC)Q zpMpp~m;NsOUi!a`12QH^pO$_seOLOclv~Ow{ZZ;){33nw8Hn^#DZBVnd?tNad@TK2 z`nmLZ>H9JU$aruLG7XWjLdFakJI+94Jdt4aE$JhT^sn+ZU)k4M)dzOr+HQl~4%rRq zf$V|oh3tduhui@<0J#%#5ONpf5ae#i<&NjI+TaVwOX|8@fGrJ0F@pCgxYJC_!)_Z z>m)w*;)L3NmiXD{&Anua|J+|qsJWiRe+cofVe>-bzxm%M)M{DcJ+GSk$r3*dyRyF_ z;a

gx=@JfZfpCH}!rqxtCg+^;6o9=F7gyl$?*C7-+DpKTI}Fp2ov(Hk9iO_?1 zE1zF}ZbI$VOZ@#3ugmq(A5EzDO8kjG$DWuj*Jq0pYENI{Kl`t-H>Tr1^TP?X&oA-+ z_$70%M(pnW@`T#^m-szjUa8-&{&Yfp9w6~|d{noyq+Nc;o;cBLMDUzjjL z5{a-gZ0@CIEBf6bT+DlLK3maWMv(qjh)+)y=Kj_xIhbJp>F-BB%H|8ye^ao#6GE~^La6i83X#uR4Ox5p8o#>@-{ll literal 0 HcmV?d00001 diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf b/Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf new file mode 100644 index 0000000000000000000000000000000000000000..476843a0174e992b958daf4cd70680598b530a0d GIT binary patch literal 99036 zcmeFa4Sbcwl|MfB{Sq!AU|=ayyg&*8F$p0kFA?%i5<>_{1ay(yklY(m@^ZcR27{#- z5CN4czO1#@TGzF%?P{gewrZ`5Y*$^ERqOJzw6!hkT9>v|`MGQtUDo`+=giFW%yX0Y z(qi}b`~QT`&GXEhGiT16Ip@rodFGktn##H=m)j+*e{SK$Ju)&HaV-+AYi?&)kqCS9YF9_?RNf(q1p2%M=yrpjrp2*undGq-1xkU-r{_SfH)*P%Ds2zxTgU<*q zG3|BA@1V4cu*bb%rQMXCwbe@dDE;Y7EA6NBIp46-0ZQlWveKiTc$}ojb%h?I`=Gp^ zvxxF@>2I)hSBHCBVcaA8C-X_Pv5eYy+0AjU%v<&<(apTKetmr(L2Nlp@1cGnTH)Zg z4|ez^B<@PMQ=ZMaNm43Yj6cX5JdMs9z-?>&=R)3a zvHR670gUk?MA{ZSL3#!3ATS4!J}5?U`5-~Z_;n5G*Zffa=;@=r^>jxl;?DZXbkQ_W zyFK>%nJu|38Z$ps^A1HewYPUn4$l?A>Dkjur_UAMa4At9wXiW6JdE>F(cN z|D&hNzU2H5{1b`ua>Ng}zkWkUXnJ+&$+@EJOGG8%Ik-LYU0Gk%nOR~bWU%Z^xEPX{ z1}U-qj~Y+8Grg=ig6#1Uq`i|!UVd*m-{0~N;b2FIEprmL>NR;kGL$5OGVD=CJ-}tQ z^50bT)nZE7U(>x$G~8UjUfu^^TYGcunfg9-5%Z8AAnzZBKe(V_@btwSg?sRgiyH=C zPl&?2!Pn!VV}D7WQVbs2eL?BqiIgZpt{ave632EZ9M7SFo!c)c8$1~o1%SRjaBw$# z>G2CT3h&^l>3M@E;@$%T9ocao{$|Gg_#2D|@Yh{`C7{RS%MJ`|5Uzr_`@ld{xNR83eladgPl(7wM{dCs zF=JqgXxvVByO#_&SvQKuX!5lvTT(yhZlUWck?d&64>csy!!9);^tT zSNP)(X?)v1(6|8n5b(2VukXlZUUzhaBUy2gH7+5>XYJn}o7i}L737AH``+MtPwzu&f)KEnEO#BWZF3cNOOs!4$XPB`mIR=&?cfCQqe@w%<8xs5tvs; zhq=$s+!Jq~g&gUnW>uTmxz)M1mBAY`Z0c;lDCR?im6d-C^*^Xt+u zt1V0(PxANM+~p48E_aVrf0*jGac5S~yxrh@GI37a;g>a}&IYSagS%ndvDU&I!kr~M zpOj{r?4}QuUA%p^mh2QQJ?1Z6dXe;6M{LPP3sbeEj(geCr4Ww>Cvss8Wj%wZwh2%Q z<#%B@BZ#Q@6qml8dT7o*id8KO_HJ`UjuZr{55_XWU5G8R8V8`!d4s1K2QDrdJQaD2 zMmzYUW7ThE9TeF_pB%Y^`bnGm`DcjwY8`PO<#C2a7alu`^9E0%zC-EtHSUUhlj_M2 zAdVH0nAFLo1(QYfvwWXZME8fD+7WZd1&^pX5{L5V@0bkFhw*r-QDV-J5_2SuF44F> z=*$F4<EA);qw5Q%luXiGvC~!In7=xTh_Qc?s;mU`vvN$ zx#ta`c#5z}?wd>8mT;ezaL&=Nzj1(~E7yuT%tGTCbtUn@Yc~^&XQQXoZ1j|#jppql zSmu)>3>1DX~Gj!NB(~LJNxR~YAS)>P_KBaF7YYG z&EL=cx(>P7JW33mr{AedOny?>@cENB`u1H!?n9(9M_fH$Gx+WsFxf?WPFk%y3QIYR*uwB58_9WxKW$b_gJ1YM&9P4C^<4Qt^Rgdf8(w^j^Zykg!SwPhXNOBNEhqKx;68or|?9cJIHqK2Kw zg+74F&^Y7!R*8wSZ@AAXT2yhykf`BlUE;hAMv1Llf}bD^De;^xG1ch*v?zmTMbhs| zJ3>Dgo_AQk6Q5o@Zu5fq`J`&dXXUvw3RGZBkG>}&xcpU2I5h{h}2aCXQibth>_H%JHDrKm# zC?0uL`#5Osaca-(t9k5s6!UH&_OTaw$o4{Lk8=!qQTvqX&l_IoK`z0bZb*qEy2K3S z8-c-duOXN}(U>`tC2h@XeqhzjER#o>?29N~SOfMq4zNbtZh7ZD%;SD=bG76KvLBh3 z*O-@m7B4Sz={uRD2dM{?Jv?OG8$Hu;pK8NhR2Oq}x8kRPQ@68*-p%*-GGu>8iR7Fi z_wxPy47pRqU3W6%{Xp zZ=_?|YrBfudp`oViQ%~&I~dQv8Z7h6t9R+E(Ql@6fjZ?nUpnUR(=pRmGT>!s&D~lZ zC5bL5~EPr{1$Nvs%5fHRk%=fonEjVDfcb~d=4$2+Xn!n+i) zKRr}ba5YwF`Tns&x_|o7?bd3okw1U?)uM5C!u!tV~&e(+2Zto0U^A6*FT8#+KsuAAV_|2#jS&g?l zpGoJB#uF|sJ$+n!5YL1PN`EVY5pNhzKXdUraC`fy8Mq?V$yA7^AgFq0TmovhMf|8G zEApyIm3W+vGAM`s!(C8Pz+Kk2el5Hm+=8ZCB9tG*^!21}4YcSaud#b+6%+HPQ0=Z* zFfPI+5g~TP>txR?D`Fct9uCy`gLuAgU)oMjA7HHuXE%#rYH+&$y zg5ssy0SV2n62-HZi;~%8q5{9_(i1|h6wi7N_c?OSa@KRXHW4EbP+tnU8u7dcO~&b+*RN=VvP>{<&kvGzHlAvEh{ae=M@C9 zriH6HKLA)pZ>;O zL@)0=n>(j3fPRJ0o7vl3wciw3@WbDw8WwO&g6DjL`yUb&G3u!bzOUx{YUw57uBQfK zA6+b9$oYeSt{=tqI#hlI0ZxO zd8!j9lIct{KlfqZ#zOF0++LAiC4zVks8%8_IF8mmByy~1cBZXEi<>DniDeI|5o`Lg zm6+v*SvHeLXpwu{V0`eYfe!KBQ_x}dvRVVBtfw4=cEIX#(q;V;)$kEz{d$_Ln<49d zgEI{$SvS<)9^-j!$$fdyda7+H$8;q}tzJ;JboP1yl3oZs+5>+V%CFUZkhc@Qq5}HA z5IkiNCl|jhs~tbVDtwLga;4HyAq&}C9z3pZ>A;vL$D+->~djbJ$4|? zp%pV8yD`=h%`taTnI9pAYY@8ZjlN7CGIH3!WFH_gZ-IpaGqnHq_HW?o-3K2={xfnn ztUlzh`BQoqLhUUbbHcMx%hyqMHp+e-wRmT<_~n;-?eaZ@f~=#@uDg;If--8AK+N zJ#|cW_CTx-{aX!4bf7xpA2+E~9+;V(4xxj4~A{Q=!UKNZDc^3*@on0M-NL z_2}B0?e;i(1f>_QdA8=+irunodcT;x2Pv_S7#SZni}g74e~9e07<)G0cPGJ5PFc!N z$S!VIG2koYdu202eI!gIjT6sj-A*L&Khnu;~wXY6XmKD<`N zHo5zBI$RRoEpglBDgba`xje`7v1aEkj!e?n7KH62mv=q$_&1~_9M=Rb3DZ104^JgU z?e30^B$EZlf59AU$};Bq`1xwM*^ZCXY|`2j(BYRood?ZjjY#vG=$GR>H=*5JLBt}V zZ6fY}5<8Bz^3KMR`#xBMuv4?*z%GnBcRjhiEePGsfbaK1C*0dyu!jnG(z!7&qRP4W zRmA=KcEMgI!5$EC+Sc%`6CyiSVrt_bVoMwq4e3GIa*ht{e#GqHW3m*sy;)~utsiU~ z*yjb=$E7TSm<437dAjE5itX3~He{#Z#-uPPnoHto_@DOwFcoYUZn^6<%Kj zYse|gR!RS@Q7&>1udE%5+(#?qfW{c_#LzfSx7fvf=RF+GqME#iVFLvlCMV?6(!(!p z*Q1M!D*VUe*~sDdWy(Cny)2c7QY70<%)2@=FpodPeS9p3dgWLmJM5~%?tR+N=1bLn zD=0dSv80aG;RV2O>5u*as|Ma_SbGrO^5Y`-?cQMSkbfta zwfQYU-cHK%c^i1G)F;}zBwr|9!lfD8=M6tjTCx^@aleKCQcjl4i4-f#JQ*n*Sptyi z9GhRHE@wMFqwSQ|w`p~RVuOSlrIj4_kc@H{Gylf8&-1=|=h*w9Vt_(TN%xYkTGo&j z9Z=Mxe7SS1g-?HB8X4V;}hiT?rm60r^ z!&|jZJGGc(%>8+arEqjwiM?h+?W+FqqydW2Xl;V+p4K65>sZLxr}p2DncgDO2DVmu z5}qy7Idd@s+A;kcyo-^wO+~cWmzRSTz_%sFz8$v?%-o(!nxpDQ9N-1~`J5#o2&b9`TC z+{+%5`7)B0_fo%}<8eO1KB}7U>!iP0n-=4(x|wz9rI zdr`tHeU)QRE_>orJoZ4UgQsj6>7_JbR-+ zBowJLB_}CJh;8Q|enx0UP5B`!qPv`FVYc4UVAeLfOH_!t;1_W=@%zWum>-ZcoZJ$U z+X9Z2d?z|WwLHha(2bSfg`}l^FKg*(^5niV{Pz_9Jt?7BjmNVgz)ni5_MM14>C_yu zWa!D9ReNPk&<=iI%6B^Ap1vwPZtXz08&jy)`W~t++&lMcKWj#|NL& zoZ>w$$j6&aEzIPRrlcxvy$5rdwCL=PAX{>FWQrZ});^Bqq^yoN%9tpS47+Kx4N@qqbyusCW+zN5RGoCW=9WAXJHYB2(tyH45rz4uw$ylPbJE{|%J+WSW-__Y;<#+YA>Fn;- zHWMq}x1k3FKu*`0+|tc;Z;rO5dJ_P&#k%8(-V~C!?`;RsRJ0%W5&_kVyuM^K!8h%# zsaBD|{MiOt;o&8^8zqNT433eg-*rV7h@`+8E*gdl{bXsRz> z-I{2>sx=W6Et@rtETfb2WU^#l(IU};zYF>AMF!D%HqoxGmd>8elxS(|inb9>Jhmj!z)q-RORBep+A<6be3U_yn>u?sR`o^uqNKHbZNzc1t~Hs`FjDHi z?r4Im&Y530kGPu09L{47=PlqI@QM5jQCgSO1i55-ZJKOaZH_Xit&pe|78q1@K}EH% zpQM&-?Ca@4LrPOksn!Ifvbj7FZB0cPrrF!v)YsY8+1}cvp3&Hzl*s=v-RUjj7NObllI#XL#^g;I| zGf)zk`Y?dLuDagdIM+{9`zsTP-b6)|6c|nc`bK?apyXUw2!22gKBKd*dl-uSBe2ld zwY(218f{YKCb|O*(iG2s}j9E zsnVYIvevduWHpc&{8Lx7JxwF~DHr{l*7+u~27yb1M9#bdD6B5-&@N_WKL172z!1p= zJZO=TXO*4f5W~7KNH*Q(rP3?SY1Awsfy*mZV}hS<($s{4krtaIQ$H4&z4al9Cg&7!o%*Ok>Ew z466mZx&lkskXBQ)yEVSCHxZS}n&t>?7sw-mwj=aHvL1tsBUAZ3M_w|ga1m&ro|+^Z zKxKD4wS_Y-?IBmqnVc?%qp!g51Ow`}b5*gbzOF6@R&%e7Q`!Ye3&}BA*O^R#`F^;xm9dqZqls8o?^Tr1+}XBCxy1ek^e9SlDJlSP zQ`^R9dtX;Hp}aD6cR6WjPfB{nl`*EzJXS=z;LX4dVKw*0FHJ_nyBnyb{Y^eb@uipsdAE&C1I;6viUGijY3yF7WJv-QNN-895u*-w%p3g484_u z>u{~@ua34Nq)C=Vqdm6N+jADct@Jb3{c0#?O!QGjUw8MGs-Af&;=avu-rLw-FrKzl`iQ)n1aAUN)cQf25!nIa}amf@E zsEwmJQr)Yg2vb`&m&W5=kPWqoqsJNwCKG*eHb`>>mkeuxltLifY0IN2Wpad|Jv0W) zM5-zgMeVK0?%~B&)6j(G34)v$@!RsrQ$(BI$R za#aGtZcFq74IMU&hNX2`OLb*wgRD=m(AYE7G(j%hhc!KzB&1l+X-d%2N)4mVl>qi- z;19i!=JAHe3f-Sbk+fP`8cSEOj7PdmZ2)Km3BRJWrL43GI?tw6Q(w~zY1YUXnca?4h9qd# z6&<=Hop2SRn?X5o%Vth8F`Gu2b`P{*5~uoG+7gX|m76iVP!GT(w06QD%XVMYnQGfe z@e0lIbQkGCq9#StCMh_3XqRHcj4Da(mg4X4Oj*)bCeYlvNd`@pHbF8pjZ{_F^t2_S z-C&BmF4(miW^_ZGsjq+=z?@cctc4D%2R(8f(sOVRI_0TLbYZwy*<%VI+TDhED#jn} z188`Kf~{Q9QrfJFvF$)uz>OowV6V{_rMVtL1j1$$00VRn57^0C+9&OQMKqag#l&3= z4Is(<>5$8Ig&@ocsnR;NTnC(n>_}f6<Ma-q_9?D-`S&pS6@)%mAlClbqqtI6f$ub-1|MjRS zIhXQL!m@@nDkXVu?(OL4iedt*r7fd(Ru1MyYif-(I4b|FX+r94n{5M@m-H!TbkxtilmB7hlNY7OC zx8uaH*N~2@G|qh;^#IbvD*YgxD2DWOmBzaZbC4!}M&o)4^+#|GDt_KY z8a(PWaz$y0k@h3qV5CDxR~zZ^pg$F9Mc*|C^~aFjDC>8X0ggNiz5(So8s#?vPV1Ap z`~cFBG0Ow|y1t0>2gf6Qr=s^YlpjD^@$dQ@A;v$1bWFjY0KDITA4Hng1U3HOgZ@IK zN!~>NRivpu+$#M$q|ruBqyOE0q)Tjk_oqN_57MeX-DrC@$#1i)-+cj8Pa4l-`4M0PV%SXAII`Kw7oOa}LsXBCYh-^C^_4_9^OapRq@e>=`Z*z{h9TcF zMelW#PZ{O^9qG88_IiXkZv)bgN__7Wyw5ZdY1MyTw5Jp_wS2r6BmK0IE(g7Sq!oYO z%TazW>R+qqC4m2Zz?J+6xAZ$kdK=2`G0NYBH1xxwcQ4X+8|fdww4X=%kfQ%fz#lZ= zr;vWgPWwVg-)^L*A-&H?Uxf7iMjHJ!1N@7dBz+(0fBT<7eP@tX^76kF#%>s-`(cm7-@gKW z%79b<9<|c}0sI1_vn77u9Kc^U;MBe&MtUjgr?eVR0(F4DYQS4SuMTNVFM)K#NM8qe zzK68xzrc;Os~G7$vVDQS0=<`zR_zIV8|8yW`DXz?X~6#%(#MSSuW3I7(#pRFGf=+T zh6g{5G}Wi*2Ny#0&;jN*05xa?97zk_4*FRt4gVcXAx-_E%cH-R970<8rjr8B4{0m4ce-Zoz;8T!R@(Z3u+9*FN8)<4k=`Z?s)MTWoKAoN(7Jei( zf1_sOC`sxc4OIx-rrZjhFC^3Lh`VF#cwG4hXnT??6~{ z2L9@&3ja%CK5w1iATLJ!4e0O0jdz^n_aM?+jr1#c?}Ox*Q03neZlv%}mIq7XT<|Q` zOL)c%l-Kp6{TX@K`?L@6#R|RzbrSvHYs_!P8hWaX^jZa{{u@AA@sqI|X(YKls4U|) zdiw*(u)>GEExQNlr7Hb6x*9x-9F=~l1PS`5`28uJ^@?Pzg8y$iGY<0UlIhW2XMLlm zp#RYZu~Wed@$M}7#~W0-#3}#L=pR4nUxtErfu13c(Oc;BX273U@Ebtyex&PE`d%S$ zVlDp3{v7=+I)52SUH>c49~KDUA#~a6z$bms_;1rLcO;cONbSoC6dd>=^hxewq*u%O zLg4M9g-9!Th6;KB~=oi6fA`HoqH?N zHz_!97wkoPol1WX_=K+dC-e-;Q2&M$9DP|x@?5CWzc%CveF&YRlWS#pl1FHe&aXyV z(I11png$tZ{TqX}kFP^IBI%83aPm7QinJlmF)1{a$WMZO!10W^8l;+$eoB?UowJ4b zjY{7IRzcsT>|qS_bJhvqXDK-R$!EZ~>uQz8*f{10;CU+jFR1@0(lb^16!dc`(v32m znTdP+^9t|-#xf_M|JEYol!C*bl#sqmQE8N2R)q9tRT{j_4*rVxrNXnZE*kptF8MZkZ=B-X20y$!Ba3Q#hD{>$EICb~^O?dBFFpG<1LV z+ej<>8e2=}p(DLb!9UBCks+*~yUWpD zauTqwtc#5D;3umBLld>{go0n;?B6W(Z_!D>?^f`>FcS0+?F-@WwRD~YlKl#Phji82 zpJm+*{dy1Z0tJ7>*0FR_WivbxlV4 zL75&GGTH}v;{XGv_$TR&%ccE_NGg9nZV}{{LRyV4zuJ!{&K%3_?h6j$l2k_5u<%eM-%i~ zS03QwUAjyO%G_Hr$^{ASbmfT=K-al^b}gWb7qHEGIcN7U#fj`5*H}@LH5#7qde=0O zkLwL6OZ*mxh|-NNmuocm$3}S9MC4Q67tH#&RX4fL0T#h-c8w7WGpGcm_6^e>s`VDv z1ke)VR#2zwZ7daACbzpLaQJ~P!zj0o_?+1;%b}g5KVDo1)O9Ca^_Z^LPV|}xhN+2wqdjs>L&r+U)BjkG zbAG4!l5-EeMxoadATILRUAXSTmFm?0<`RGT7wGab_5sI)1N)J_QX}Ka_02EW_|muQ z7z)=jz*(weSX}oZz1S$9qWUhnSC^NufF9FyETCg59s6sau44;5r`L0TT%SQ5H|ezk zy#`>{>k3i5rC*WtLjH#VLqd+#dJNIAzmAD?Y^!53J-5(v0zFpim|2gNI%d+b2CfTH zUl>=?&r>=E)v=q7S#@lq=QKJt!SxWz!9U2kuAcMjxw>A{&}$2N4yMOyT&X(J(tT%vV zyns9C33`LRpg$N01Ouaj8Nt!PP;g8zGdMPo6&M#BA3P_R9h?xH82qz40vNK z9A6g74Bmvk#J?&0SB(WSzjCMlI^QnuZp_ZDeYSFpknq|Uzy`q-O*w8DG$#>Ik0UbQ zy+svLFgdoQ!4y3TYea@Y?`*Um^^zduSS4vU=yoU=@hrj;wjvEC<5dak(Xg|{*PR&M zD833x`lXsa@kOxI`@qN-rk6V#eC1#{u>f`N1pVoXuf3kq8@;vvSbEsvkoAXod;oaG z7T#qR3ha&G{Ew6d`o?srkK-18G96#eH-K|C+5$Pc$*0o4DYDK>w2Z?NCSwW3&u))L z9DmksB-%jbb(}#ygwrbCpuOmnmT`xqu|d;6OZHeJ2%^0rs}zYYgqfdO&x== z!O!IiZ?|7!wm<7YrI^%`W1+;YkeI6+hzd`}oesP!9C#-Gir(ts+NStluVKUStmW5k z3NNiM3M4O=YC4+FyMVXY!RMt8KBvfb%eYzMmG1R4ruUJIrzJd+RtIbQI!7HbM;&L$ zt^ycyWZW+6>ePHd?+C{K8YQf9Ah)a+z)>4MXl+6 z3bGFX#{ZfnKc%}prMtXs&y*Ujiu^0#$@K>dFKVHj4L-q3uuiW@DcMMC^oW0V+9Kh} zd5q$P{Rp*B(vWi-MMHWA*+vcLIgizjtIujXP{%0rv79eib!@WgfW0yNA+TioLCK$j z$>;c1S&MfnC)a2#Sf@qzEcL;tm-IT1RR{E8gHs=fPr_RZ);61XNS`G>GC*6d$0_>U z$L?OoU;#b|Pd-<-@GMypOztU2gF%i2lluiEj0-7xlV3(^Ls}UHlh14l*{~JJBC{WB8qcA=99hRoEej1h z0a%vePs7kgE_Vj7rHVJS@kZ}j=lnzA$>)70Ub_=d)g{+bB;HxoE$}fmg7A>^XTNHT zw0HMPGunmB2~R$Mu=u^oGCK`_8+7U{c&i0h^~mRC796qp2D9fmPNjO}b6?GmikUs) zVMo-5_>ge<-(HOy&{6H@pE1MQxe`}C9~gq`5kGZcTYNC>okQ@qIIvaQBRpb< zLnx}P^4YKAbGPRbt1C1d^3dyOn4{Qmqn$3L?^35dVyD?q15Z?$@>pkLv7M6a`QJ>5 zXRYalrL5#yu|>n(XWFUaSMFtyI3DqkmME_^6MeZiK+%BiHCPQs&8i-`U&5~Ea*ue{xs#3 zqmqN%11HO)->$Kmsp!Z(Z3@nG+?5VO3Qz70H1V!5(^%dJj&u zXT$$OrhoRB-rr)?0pHN$lqq;&ynDcx9WU8xcs6)J9g`|BZCr~w@+@8)>pBdl=VR&X z7w9X3@xS!-Y6X+eK_p#s4U=geMalI3*ZlDF62;GMPm`s$syYw8t4+7w?JoJu1NY^N z*Hx~oh;Cj-uO>D&uWVYkrZ+(cQ_yS9g@APTt}E~DYR4;K(UukERSOCW3+J_z ztqD3zVO_GfFVPlFuA^7K^4f#}3hRR5^8E7i&quO5-iddU&tj!wz=dyamtYPxMff~; z6z8>$0kKZ(NJj};DAq|KJ6ysW=<7*#cJxHs!(F|29hI zb1f8Jecg#PJz2tzf_=k-$v6izd8#0I?L*Gi|_;Qh@c?Vlkc zSZ#aFwP^^ULVl5xq>c_^Vkr&eAjnPTMMiw z8fVYeEJMWGTl6m1pWg0nfB?K-aJgDq)Jw~p@i1lR*R-))2slqrmU_L`Hl-T@0`RWu zU4w&US1#MG+VCzPwiX$1M}j4P0*iU$MW&bx8rPET=rehc{xumPJx0Xi!UBl_MRUCK zX1y&K0)9PyE%+s1lb<1`^39&h0QhY79KR0P7W<#+u)uoijI@{Ysh0wqj9#J)|MSSu zui4od`aNVThu-?6_dKl(`_)e?i*WcId@D!2tf&hHu#v2#Nxo5Ns|fj2|6{^S+TmxV zFmlqpHG_U7yf?W-sIj-ZhR(0L+2x*r?nLW~ns|)j9GpOkoZ{xzLej2 zI2W})kgl%k6-`w6_l&$1$UDU)26Ed-rx~EkJNu}Do%lT<8f6(+%+Ld?pyt8Lzu;0h z`>`t7jyJlkj6=e8Su)XPXFM-l4g5whdsf=JhJ9-r-lqcVL@W~b9jNU=3`*@>;OAsy z_wspS*cZr@Xs7MxEo$~rTL6v&Qw$1J*j!3nVycIRtN|(-s3W@H?uw@ply?o2qlGE) zqfXj2DR?_C9(jLXRz!kl1I7EwIdBKqpX*0V=Epv3|6=?=&VL1dar}1RhenKA3u>P8 zOqY@QWvb!qIeY7fhvc8$YYeztC1M)nbeGG=3*PcId$Qz=ZufZ@kOL+r@hkv?2aPK(&iW>=N!g?y|u+f}$D}FKxEKg9PN@={H@)IoFbG&YmoisrIhU4S#xZkiqN8k}+6kM&(fXf!D9H zV^Gs9@&TF1(O0K8(bKNXf0m(v?M$o~fk3*jAYa#d0AnAr2xq-PS^v_GELr&xG}w(94K@5tSvj4=g37N&a2lAS7RpGyMCoU?|EmNprU%@Q~=Hx1W5$OV9JAtaF~ z7$k)IIh+rP6J8LPUdiP+^KH&tfpd_6f(Z0WW@k*p`*k0-GrGHbd)BSMXx-h~wT{pB zS#?&0?VwLV3O;CsT`gX@3OC6*i5BNS*=N`i-e$&At94T?Jm>kK2s_6S-oz!6Ue3tp z;)15at(LfR9Jo%p7@*-=CXB-X?Ism)`(y-~oot@xU;686Mh^|@^NkY1VA|xoltL` z;VI9bve&bik=b&fn}Bz3G-Ds?igMI?d+d~AaFo@w(O8Fg90?xySuhkW!UkxQ+tu8~ zv&m)h1CM_3Pt}NME)wu_|nmmXd@OswKS( zZSXIL0WTo%=ehL14FfK+!EX%%o=@PdT>3wU0T(#EXT(ljB%!1S>BPjfrD1?@09}SGRWc@v84jOnDrYC{OZoEsi2f zSclTWx4g*ZunrYX>6qkVQ=}YQk zHZ6AFvf2IeFzlk4nt=P3cwdrEStbAYCR1hQczl>Pkmk`VVdLwRBe)cr_W?(mK~Y)% z9+EnkjbZLn_3$JUxT;Hqs{x0xruq^bUg%7;>aaYP6OBhAVmjyC3n}lzg%b|v*^bk) zH-5anxkEr9CqE$lV?p}a+7NpeBRnAyikxS1>w~?4_Rl7rP~XraxydRdlA^WHNekzD zTPWwcFm(zGZ?WUd#o^o%IT_nkvA02%FM64ZR}$ z|2Hze5s#*X-Ayi$RZhlgD@k|C0g!)1wG-sKwdJ8Myn1cgSRP*3|ATBS)`cVDKVBPa zAkXpXYorO4^z~b3&#RMw-&ctVDA$oGoTT?pu}^soQ^ae~Y8Z7M$A|5xe)O3{qM4_6 zz~~o<^fE4fH$lEiktRRk;aU2qj0@A&a{W?W#j30KI@tVlcg zAB{{gyk5eq@i5i+PyoPvCb-T4W+U!5;SEDi{~vI<&ofb)<>OjsEl!lRLr|zDh4VL( z(RFFZFxwwNNXLwf@TCGWBx*!#y`$+^&mdTf>-V0qBOri>|v9@zJ?zxs}VTRQ&&+J6j4$i_;Vim5lozNbA?8X0vtQvNLNAz^; z@{ms_P}Mc~;W@#yzeCls1WuR0@m&r_ikco~YFPJEH6iOE&Z_6wu8V>mRuVh6zmIdJ zOQ)9uCO_%A$z;m-Sb^QA*^;62;NeLoB%AX#V$=5`tf|P-H-bT*CyhbZKBjz|B^`cF zLa!Z6e%W=>tkrp@w_P#(2UR*fLET61C7fI2cAEvwGqjz>Ai(K}F%>#JNAXQh6h3r%NLJPlcYh_j-T zY(M5{_h-o$=PZ*3-mbs4p<{Nr_X8^CK-;L%^aR90>tSj&l3Ev|sSkqia<&|z$f|Qz zaisPB^JIlI>@<^Lq#yL|2;L2m6|b_)d&pVZP^uhsL(Xe3FNyr;q#dP(WwXuFdnPzP z;aYCUDjM4iQo6k~#LajYFAgL@O``S?wMd$-;Xx2dcQY&#(-CVLvrEYwC9aWU0|jD6 z?yddgs-?ZsVGekCw4H` z_cg^Xi;7;U!SPQ&kzi#rBOksTgv`Jq$!%sERO)AntUXl%$HIG^X*p$kDen&$=2y|l zc!g-e+3Qdq$0VnMRU*vDLTZJM{lsmgYHP52SU+VIJar`bXW}+$VD~6_aEt2!vp>- znnj_bq#2`n9`kcC44Bo^dt7*5>vys>cJ+EmN}s4t7RzYrShGbAVyf zY(1R}GwpTP3X=mPxUj0nG>)q`dUVcTgAFd2TTE;;rnAv7EE_ACjS8C$+Lb{szD=L1 zOzh{%GdUH?F_e>X)k$d(TXRl;0WTjegDY=#tpUY9$Pp!?ZQb;(u#eXl(M~mSff{%B zNMB^F;z3m%@Vz5_Nhuw1pS5^wes2j_eOz6WbZxf}_wA^3q&qRrnjf(u_f~9DxqF1K zT@69JS0d_#Q1z{vsmr8OL$62tyJi&{EQ{j$18 z)pX$__}U9%($~_J6q`;|!imqHXUWAZUuk`c!HS02VP1e$ySZ4qo_h$&agcm1ofeI^ zFaJW8m)^-)7!ig3+!zlGuv8**{+B=oPUHN?v15HIqLnYI&V!|1+1D>OL(zMkc!%@o z$kcVOG3iN)G)NNp^It=HtgI%lhgwVTgXZkQZeLRF*l^sc{&kQ88RizQjT%k@$ol~` zK4%xb>Z#POMtKEi>xq!_lM!&rb1?^`w$H`t5i|G|+=DvRl0O&vvXmLbJiuIe@{TtH znTALIK>v}9cH{F>AMXUT~clu0#x%=sWG2@4dP7-6MEI5^BF(I5ps;mo^0;vAA| zyYz8Y{X{BB+gl*Uf|YoBhBu<@r)Ri*|A|1sHS&QOzIs~PP`$Eo_-ADW|J`qW6~caA zHqRID>uSP|UE}MB)?>4Rc4@TyFpc+a7F=T!u^$!jzOsVLr7;$?t1Gyoxy*3+=}k3O z=jc>3yh+^4BE8(QVT*OvK?r2ttB4FFRy&gZoyJrJU2-Lthf2o5a9c0F2d6)9XRxjD z=3!Ke_w#3YhC}0U9z4+rYrOV=CaKj5^P_p_y!?0YJBrr`U*U-c_4ov0?ynr9HT=UP zN@D;!Bp=n#9LLE0Urse^?#0*R2<2f`qfZmj<3oE62;XGNERz4ihse~oTG3K2iO#`0 z4tV!KeWJ~Z)_6H&9yVy>>mb%6Ksm*t_qJy}rxbXxatxN7hWZ3jVlYT@m|uo{IHQCI)PS6H(IWj<(nBljM!>%#Yu&Q1`a2pU@$NQ>wHE8AFhe_c&e zv;6?NsJM?lB8cyzu8h$)my)(+6|Ic-*WjCw{hSq~5WQ%ypFS2tAJ<}Qn*Xny=E;BB z6Bw!!tGM(aT-MoA(_Fd2thk@*ll?~q%NwtYei`ql4>GDMy`b@L=uq{IJA3)%9Wd*JSR(S#-9IAF zllEmF92xi?>{=rHjP!Y0Ty`KojzU>FQ*q@;%z{#U&Akc%O}&#Te-~8;UAlvi z81;_nT&_UW^kJRLmGl+qv+G?*Q5Rmsc2mbwuZn1lH~&I7WX_mb;f>(c@iu&ovYm6- zz!&x66PK;{D4;b)FS;t;wgz8tj5f%3YGv z--so=woQy!t+JYB7MuOTi~4!f58L~q^}HDB@~ig;t&OMzAUT>>%U?2WDMfHSf{$MG z@7ffIIrh9d^DuO_C?c@VSMzW{~FmxFFH1yk6wIjy4zcPqv7_55$?mqw+->p zi?Lvt=A#$=7qiD6gk=GK%i*2A;CBs-n$B~uKxx!WMSA>NtYkP*X0plN6=F9K$z#@g=<;{>~(Qiaz#k)6o3mV{w5qO zLl+%GGMKGCM5t`Z30&I8D#i8$PxmGfmBltnvIME=;g9Z8xcECl;Ftb`pJNxzzDD|4 zIvZy8+paL9T$sifPnC(gQ;6WEGs;rp?xrDB-o}d1Qda|``asgd{yWfM(7<*EMP6hxtS$$R7rIiHSL>2)?4p>ui?PC}B)$5Q%Od zp<;|e=bv#smR7NP=*6BBZ@}LQ(h_AgY8-W*+CN3xsAcwg%3d1ZOa`hyR*k*h37V{o zx$ajXN-hO$##!=nA`;cKt?XY>_D-ihSU~FZjK{GQs5+c$rsIL~p7Gu=T+Q}J(oy%f zL5H!H{Eq1St5LVi{tsl2c3WL2sXv36TC?{~le+mycF_HI&}I0N|0V*6c?~B*hY#fs zc#l%~B{@PY)SJ&Ip%q9BSI z^6hxw+(0LafbTQL^r%Fk0R-q1^o@!bc5!S3*O=&R=ZwSSP{3vEB>}}lt19@M2$(*>UjT1 zD4MmpbPU>$BSoZ9BIzjeER@YE-%K) zBY#+(72(-F#HOf&||!X&0uSOFhRi(<|xpL6!GJSDuhqlV>k{=!w#)7#Pmp_ag@ zFTasxqscCpJ86d9BxB+Htz20`S|e!eH^9Wq$?^1GMa|5`%B>M zhp3o>vFWq;&BYHvVA(ej``nG|kD%ibAujnV%t&O(E?!aN&yLecQ#6l}fZJeNqqoJ| z*mqgEw1sf=SNiZw5bx?&MB`Zdu}D1vQsW)ZJ#;bH4~ji$cufsi{yl>H4B-$n&ch5m zzl%rN<H!-rTFc%8t5TXIj4`Xf2>%fO~|FoGff~hlkYE zy5-WI6qfL)wp&$=hlQy4Pt=CFi7J8TvLbYaZB}bqH%0k5oW@`&hPJXc*Yva{qTNv( znT68QR^IfpR(CsK)q9%D&>q;DYg%zeVE2Y9C=zV|84I*TKhIGd&1MMuO-HqbKKwv64O6 zeURm9wO!YTSCMJdqWZ{~$f)Y?K)n)u5cQ7vjH*}XvP{O{MGvgeYcj;t-&xHbv!$PV zrZIYDAC89O{xP6?t&ra=eu#=!2dKuc8tl{AqDA+6W;@weAtXI=Ce|yk-?RQ*ECMiE z^;jZuK(gK3t8p=VKcDOPGXlSA)^R`TIO%ETIyPwcQ*KoD79Nj`^oi5nxNix3GEsarnAy)T@c5y3@pgP8^#$ySQ znW>wm(9yC!uHqtsUSPD0PC;F8-19?cEpT{=R8!l=XnP->xJN=H#|m?9I1lVT!`K^) zEf2I|gFeo9q1$sRjZ|MUjsUzAFBL&;%dzdFVFh_AIx6*|NuD#3loqMvmyp8}nH{@w zpbn$+T^D^r&Is*_o383iwQZz%2tAjDrBM%4N0pzlD=vQm z=_6nU&&w)ct|YngEAVB_Lj|)0 zGF;F(wM)kPSX9d`e;^;x(V~@I3pitmC>18(K%6#x71eX`nik^hQj;^xyMIizW7)x4 zI08qnP+m<3p<{MxwJm*Ro8M6LM+c+bLW0g2qo ze1kIEtk6-Svf^azFk(PfXF40W_^|(ggFBqS*xB0EnPeVGos%Lg2V2q>iq=S%E7AF+ z*Ojmz((y~b38_6wgk)WRIixNiUEJ<}*{qBEj-82qNNTK{P{4+;kkpk!M7X5Yvrx%v zM4{$QYUZP|?E@}9DsZG-wja;4a; z#0v)?zZX(uyyage^3OU#ZB+fAOyfO*L1hq5u(DGZ(uu?uzZ7l@#k{8h9pj(G7H9Z@ncz~^kY#l_c*#!oG-@livj&UYYL)InqKCknpMcqwJ;9Y# z5pbJAK?=CX3)2gv%6%gS*a&DOf1E4pq)w0lKsPsh5A(bjlN;aOd19#RLU0OBjO z9rLnmxr%n8ANvd9)vd|0Xtc++a6YE(w~Tm+L_FCq7b@|jl8UR`)3n5eBj!L>=D)_+ ze!*mUUz7b((`A_dVh!j0_cDSq&*@8B`1lX(CaS;0Ui!EUaV@Pp&|yIKnjSysy{te! z*5gN`yaaLCB{HY3vu6`8cMxrwP!l7LtIpTg7n#xYLsPNT;O(a~oLj0ZOB)QP3h)A9 zUw8Kw&VoS*arvM1(Z&q~2AHVh-(@fI8GB?4^!3hV_o!Z&3R}Pw8LF@XM@;s%(Nt>f z1Ni+net1;0_C?To2#!+|B)KS`kdNb3-BcuXBf#Q)tXP7;V|$`R`vc@UN*H zp53W47ud$ZgIM;e>b99=lf(uUrf`cY|MOCQ_DtRV2oX3O-wdl0XPD&oDCf7v)*W#2 zCPV&~IANLd^JgmlEFr%a?`yNmQ&Yx|GrJ5K;$CGvl&aljbpLx^R!nNu49B` zcV3gAmL+kJXVgA6yRxn-T#8|`8)le5?GOhaI^G}sqD!=taGzH7%rhXkbssP-zMow0 zN45C(WA@{*|B-4W!(B?pSFQUA8?HASTSnoFJ0Ylg?5n1SAj7OMlkuPg8S8KPjECUM2NvLIdUC0!b_N)Wl1?7|7D#Lx*c4Lk}>q-?jOhs7(t&*!ER z+9}~$3wLZU=0j&CfitLdd=3T7ypAPvuRs|wzTB}a#c$xEUiv`pMymUY1*n^=X76TC z^I#b3z6<#8DDI+Tgq`Y)pk?2Nd`a}YES|4O8g`m^U?`~~N^djlODxdyrfTJd#>7ARmh6#>Ro^b|>>n?-y2y1FDv8;)~D9fU3KWVU7pDO3$e zXKzbuyi)>W_`n9vuuk-~rKejkSZ-jrM^Hua;AaudYo3F>h!(LFlTef687oRPzyMF%U#+|)XbGm6b-cSY$s~w zN+)XOC?{%WNhfONNGEFMXeVmsX(wvtNhfONNGEFMNGEFMNGEFMC?{%WDJN=XDJN=X zNhfONC?{%WNhfONC?{%WNhfONNGEFKps$b`;zZ4!(*4&)y(&#Sc)~l`=Qal7?kQF}7iuxze!A9A#K$mNYCg zM;exyqYcZ<(}rc{Ny9R8q+yvk(y+`NX;@~CGAuJo8J3x)49m=thGpg`!!om^VVOC~ zu*@uJSZ0niEF%Yoh13wkB4eWkE__i&MFTR?M!GMJYgEd6F0AM8ge#C|8r4?L{>Sv} zot*tLvVHD)SR_mfrsi|454gR0AR6@mBfZ8*Y@<^)c9%xM)<5joOBjLR^;7CmY?Cv?&|nv*%(IhwiBIhr}jIhtA0Ihr}rIhr}z zIhuLeIhuLWIhr}rIhr}rIhr}rIhr}jIht9@Iht9@IhtA0Ihr}jIhtA0Ihr}jIhtA0 zIhr}rIT|_eeMs4k5FO_TAD!to@}$x?W}NX(gXh{oF2uVnkhe7NsrR-m^JV-8lGEV$ zFu$mG!4ZtX%~;&z!z<_?+!%ZXyp|27g#FWCJI93D_n$#2&p5XW^gW;E3rM^62i!jG zZ$qzuO|R!+1payIKY2IuSZ-`Wl@p%OyFhY#p7)|HzC3s~CwPpXoBDGCyO+bAeidyb zv_Vv+qb=dNh=ZnqVf@_xiT(l8M*7~#CldsGlk@-f34-cNV_Gn#f#d#XdA|EXAj}hE z?~~A7gafXy5s-|zi!mRj8Lyi#X&&!|Wx66J))B^flCi!TIM3%<2`m_!hcFwA&?3{# znEynW-hD81%*Zp&1JS7*40#90=C5|UT|QTi4iS74$#lG!oqwd&>rYmqqyIOqM61O! zgd)ZwFj8s}SmomHjk&&tjIgz#(fswElfpM=EfpMo7fpMD_=c;HJOS5(~JQPbWN82l~z)6pWkp=gQ zwPp;ZxYuo!1FKFsKWt>hP?^=<3lKy73r+NV^8)od>IZJZswmGGdFfL4enOtnm;8vH z@ssCzBYbiD|98*z&fa1fj)tPs;n%@7&1Zd|JhC$epidszkvnpFYdFy~Z*4vC`a>Vt z4ezbb-t#i)t-+@D&+yi0m$CqC)4}dRIm^ww*PEwS0DZpvKn0fA?R9c`#FqIaBfQ0H zbrHnEn2vhz=C|icOh@y5-eo=?#nU(Wd|?F32!375{Q9wy|MTqJuldBeN99h7KXRV@ z|EP0!d=d%UUTJ6i&}|r>`0-EtxEXc-Dg3w<7!Pr^?VX$T1`dkS5$gXb_DRSEFEFEQ z#BlUuv%H0H-Z(WK%ODR1uDrK25}!721GY*`aCrjw({oQ=OV8A$Ei%WCoIuY#OYJNa zCR}6baa@o|9>xmkO@Vx$X9mUrJn6~C=rGmiosN)y8FDtDz7~5aa$JlH{T7App=B1k zkZ%A)@My<}l75u*QOU4T@&zt=3zmFJ0GY{4J>Iu4>YNwY?^8GbUwh{Q99MN7;JbVG z?iI$CE!oD;*zyBg7U(TMu<))V8}o=C!WIS`Y9UK&TUc6&)dN9@V;-S|5@Vakq%<*v z@nnc6B`!%AN*O}kgi=ZkNeFdQmn4*=qz&Lwnjskv^!xv__wK!m+=LDtNU~S6y660_ z^Pk5(|M|~3_gp9XP;R=$imy-ulqndXf&r54iQY=QziaTf^DgoXP+&`7!RQo>PQmEN zDho!(`&y;%T$HYf)nYb&r8ehAcgt)$h6Nc^2g6^$D*dVw?bD_D8|lsK+=Xr;v8SDr zgxuCv_VwXxT!pg{n1i2KsyvS=&kfAH+Z){Wq}lctm2H2~T{*ik@sJXKA7ZRZl%;~N zahvb{CdGC9|Bq@-_R(XrSDUFQEDB4l>)dGE+wCyvG9`RP35OtT zYI35<B{~mthsPL*#{<}Mc&c4vu>#DLp zU*$hB!T$betRC-Sw+`~}bnj)K-Q>t-Gd&fFPNUN&JPo(N@AxM_rW}Wa!?q_!-N+kG z>|0_0n1_0odkc5Q`*;iH-s=9yiG4aiAcR4JONp-sfAnesLb%>d9Ig6^3AX|hsd9gV z`z72F;4lX^fep+OYzMT_-QqaVc>rYWCML;jauY^G(hGKRmbx3bu@-P>Xn->#n8rwW$5V97r?OCESzIAF#LvwnqHzrw6v zcGk~4A_2QSW52pzudDlYgZs2j%c-%R8eBb^S*Bz+VXP0hRrgFA=4?oJ#jE>emTBFMqU zuv~;O4NCb~v8wV zhvVEwEGgbwOhPRj)wC`&Gdb^e6?aUB<(o;DlvL~&Y7Hli!weg)-YO!;G4LMrO(}m zf$YX~U17XJbXfqzzeVf`x>3cv+Z4Y^?b+uF_N-vfJ~(?8I<>H1&I;!2BVx`zvU}mZ z2PR`^p;i9obxBcEO9~%3`bCU0Yh%9;+77 zUwvF~vkH~D$S+|O*ldzWuo1DPR`~IT9J|cz#0I^I9TQtLk2?p3IPq#Cv&A;5-DJK} z_RYuJf!>4h*&{kRju^SU0sFh~dQI&XjFm`dC%uSy0|o?yHo-gpsb*-#`!qv^!v}sB z4TTLkH#xst~9SH&3=~`m{z*@FwuS&;#wibv)E}o3wbGb z5<%Xj&GGM5{(Hnninh92I%-;&msGA#DpzC!@q{wK3paaz5BmrH7T$*_&wg z>~dou1TQDhWGVGDnh)88823A1L&~3tEvDy|w_Ba)5!YTM=YZMv#T@%NKkK9_ z@mBmdDdB#f-5k4;$p4OE|RO{~)NdxI8r?`k!NzIvW=PO@Tnpc$O z3B;3>Q{y@%Td0buv?v*SZ~&!LFA}OHL$V(;$~)L)8j)0QWGvtpR@Kca^0w0?**(f+ zc=WiuuLVXqRZl79=arK7U^nS;mu$bei%7jXo5?0zS|>JJ>t}xs>_phAV{aC<(33-a zBcBM4U#iQS&qy$$$?niBjBRA>`+Iko?;rBm#vCR>E7y@w?)xr8L*I7^#l5e#7`EK^T_7^w zcOhWD=HgL`cmt8p|F=)xEnh<-9dSJdIG)P)$*T{?RxqCWsn|T3jvXIqH+xg=W>i%Y zEsFd#0}9p$uXI~rJS62(b` zylPQ#U+kg*~Dg(cGABoHh z939YL>hr%e5tei11r{gi#BXxbS>0UpiivK?z}(B?+esi|e_M7eF*`(i($`My8N7i? zf_5K+p7wRkPUL)V3dUiPe6f^t#C}V;I8a+gdkIEKf$`RosFIw71WlszX-N#NC^x5_ z4b1V`ZaU4LEM9YR+&ciycKM*ul!$5Nvvq4Um^Lu97KYKYNMS$2&`=v*I#ts+ssqYq z)S#+KMQHqQBJo9ZQT1PxrYWmxKFwuH^NbG8I-qHH6FYfc?Ag&IOD8(=OQfA~JYvmp zv@T)#3ape-JU15Q`{t6;i817fX{?mXdI~wR$ruYTw1}U`+3LLCB}X#UMc5}WC+_|@ z-Vm49rXq=8`JQt~MeR9VMBU>aaqRt0>;gC0Cxdt=c2vI7KvGkqV@179)Df`?V)5Lp z+VVD)@q)_u6Zdsl4O&lAl~;?WAQxBaF{B^1yI?0jY;Hry6o$8fJT;c8kekNB;H;xs zB3lA=+*qa9+XNe>Va8S(UxTLy*Q|)gCH7@7W$-5Lln(G?vy9V~-XkQD1%am6_^?X* zrb?qx$-B?~BxU0fMSe$+b^}7mt{sWwHaRpNRf1c_i7wB%Pt<5PC~4a@PP8_CbfJ`Pv~v>IVpbmo`;^{;W!7J zSeg!mP9ZJ}X>2x3(|=2Al*vo~fnL$2QvO?0)fKur_dX}K+U02N@zN%iAer{-ufDB# z0fwmk!(vIcpH81Il;kRT#jh3nbH&oSIkr%qGjXN;Cm>-7$9`z;clSBYG1tC^ zeTx0kAc~~#$_Y(KSx42R-3h@YnYT-IlC4yw~z7Wb^(p(@tWu#mFb3j9YVEb@G5Rn|av|EJUr#7?EkLH!vfN^VA4f z*4@%iTU~rLB|e7JM7YcK+bys7Pjukhxw$XphCb&lLSyF3EXm_GZ!FB4KXpp=)OpoY ztEWtzH*d;}bEnwu89S?OcX(J1HL;v8i(;|k1q1R2U_c6!R|P}xhw}Xh=`@+|kzUsl zhq>u8{a}Ro#NYw9thuZS@24g(N^iPFDPGl06g6&Blkrh~2dL=*#lNHYgv*9(S%*kq zAcim$?v@R7{_CAcS`{IdC`!#uY;x(K)e6W@AWYHw69v$X~(SyUqkS&F_SE7OpS7kSx#`Z27PR? z!ES&L(PJztLU2r-AtdNsr?Yx{dY2Ws49rP_@o>W9W?9y_CM$BWM^E%hetWIRC%Cn0 zG`eqW0NrKKa45P9ffEAg9JdD?w*%7sR%EjWAbN=3vnGvuH5yLiA%m7Q1pQE68aZxH zPFGU;q(H+{q%AIeb7<3c^px?_y|9WP=b&1JDR5rl;fEN2sF|0 z)b)fd3K~z15e?~ILW3*WrfslOT1~D8C&>PXjjn zaYaLA5e;!qKW0Z>x+RpqnfF`P$BK;*(jXcZau66h`Y4f^#|&klaAtnlfC5R(s<5otTUFjH zlp-3EH@k;7ZpjilLuC;Sq03+?yIs*xSwzF=dn{|tD+YZ#=zGHGxo=w5ytYsqI1?!g zMig`=Pd3qzzy)M^;q@wT!Oc+a&qI@*pf_3mwcvmO1+u*0Q3Imy_O1o*0HR3;9+!p4 zUw9;>+`?x8Va4h07Cz07cYlM`zwiXGxAh@d_zQw3!szmtWtG>d?h8*6jOC%}P6RE& z1ziMstfwDw!h#McUETudRt1$WC)koFaJ4}rP|>UN1YQIjn-|D(`Bwow6*8gaWMmOk zlxR8ashrA`;4}Pwk(XSSl7cQjZYU+_QKG(gm6N?iaVtW{=w0Q%1k|r(D8>l5ybcf z8rj)rAh1=nsiY(;9}Ov1N%dC#SQV?p)DjITR{4TK2Ohpks;KHZ!|^KEH^UrN7lGcS z&rsD&f@f>6lIBqrGeMXj3T03!%d{z1{@PH|sw;(33=vJmyQ*#nM*q$;QN{C3G^B48 z6({J+vgo~e=^VAJY7EpBpr7KGH=3vhUQPRv8wE);B)pn>t$xs;cN4rd5B-E?)l}#J zu=+6QC&FphJP7({+I|F0G?cMw^r?A4>qfbs0zK8sHPWc38jL#?t7xewir2fUUo>bm z_pU&C9;lXPR-0BKH579#&m8h2dk>&v3aX_bh=w`t1$I*P zSMJAhW|>Z|yzGr=-~c|A*g9k6ex`t^dY3+JwW39w&>li6W70=;wn z7C>)>3bkRGWi{NU$u`UR~djrNmC<8Uza0t+GeHI!H5&xrAIUd0KP1Av0X<`|ln>ER zGd<@K%UW)!0_O-?2FZbD8bEsjms4xYX(S}KoKAsgNFXR{`P-^U}KjF(kvkgrRXuyY8$gm5=qo{N;H)J6}y1ZN+~JtT5%i@78lS8EEdraM)?tV>jrP$opn zhl~ePy`sQenZY62nYpeNsi%==dp3aM?Zc@~(Jr#R zw{u&2YNRvOFF8S(bXQL*115Sy$3XAsn8WZa9vK;Fzb4Z@yj6*h1v2DI6HWA*B8iW^ zp5$W0zuVrqP4b{uqoBs!j9w$4AK)c~bZ7syprW&SQ@z>XpAj5LiN4Wy1={Opt4i2Q zKt$&7?~PEcq{#k->A_ScGt@um>!Jyko(aci`NfB`A8))cTOk8d50N?#+}5{!drxZ3 zd8>fxwN4V8NDu7%Dcbz`Fm<09)X#$P8pXv!si9PxY_@~eSvb<1Nrg}Y8wb04dNvHD z)AG(m_Sz&8r>&<1t|aAiMpkB09fPSZ5d%f!v0($)IMm(Q-PO_KiMQR63kM8JK%+@s zAd+W(9U)I4>A#GwFx|=Dt3ir>OGjz zQvbNfoL51L6oglTqZZRX5x1ZV6+eTx(?>4o-oAs+&bDT{ z`!d~w*LuZOtB8DP+sN8fSNBkFKKz8yO7&??rFMFS5?d)cg~6lcQBSO_cnziK{i1go zX&X|VLwuBaIJI_YFg4@3{7oG><#5(-S$EME`C`Wq6J8eC^rB zE>|KCxX}QArNE6t1N|mfH4hfE`yFO$V0uJo94tnD5cNOfJ_o$8UYntYa* zIj?Fd%nQ`=3HFmlw`|99VR{F>pr|(a=OM(Z?tyL}2O4i)TF#|!@sM1^b5_$o+{!ZC zTC8+mC)ntt8eg4B`Ok?SWb}!jfy1CgF7F=^hTM}$?z9jiKTw34nqXZFb-#7pW`kx6ZrjcHXP?JK`J9=g66+Ogm!QC4xNA;skEv5yvw8e z0sx_h&XJ(d1uu{80e}HI=XS>3qseKEC`*@hHJNTPtVeElWW^<#9yUB^H0)}-?Z%AK&|a3DDNk; z5xIGE<=Jo+)k_)R*xu)6TA%70(8UZSM*9g-Twgp6vPJr literal 0 HcmV?d00001 diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.S19 b/Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.S19 new file mode 100644 index 000000000..22a1b55d4 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.S19 @@ -0,0 +1,601 @@ +S0030000FC +S3210000000020003FFC00000A5200000CD600000CD600000CD600000CD600000CD6BD +S3210000001C00000CD600000CD600000CD600000CD600000CD600000CD600000CD694 +S3210000003800000CD600000CD600000CD600000CD600000CD600000CD600000CD678 +S3210000005400000CD600000CD600000CD600000CD600000CD600000CD600000CD65C +S3210000007000000CD600000CD600000CD600000CD600000CD600000CD600000CD640 +S3210000008C00000CD600000CD600000CD600000CD600000CD600000CD600000CD624 +S321000000A800000CD600000CD600000CD600000CD600000CD600000CD600000CD608 +S321000000C400000CD600000CD600000CD600000CD600000CD600000CD600000CD6EC +S321000000E000000CD600000CD600000CD600000CD600000CD600000CD600000CD6D0 +S321000000FC00000CD600000CD600000CD600000CD600000CD600000CD600000CD6B4 +S3210000011800000CD600000CD600000CD600000CD600000CD600000CD600000CD697 +S3210000013400000CD600000CD600000CD600000CD600000CD600000CD600000CD67B +S3210000015000000CD600000CD600000CD600000CD600000CD600000CD600000CD65F +S3210000016C00000CD600000CD600000CD600000CD600000CD600000CD600000CD643 +S3210000018800000CD600000CD600000CD600000CD600000CD600000CD600000CD627 +S321000001A400000CD600000CD600000CD600000CD600000CD600000CD600000CD60B +S321000001C000000CD600000CD600000CD600000CD600000CD600000CD600000CD6EF +S321000001DC00000CD600000CD600000CD600000CD600000CD600000CD600000CD6D3 +S321000001F800000CD600000CD600000CD600000CD600000CD600000CD600000CD6B7 +S3210000021400000CD600000CD600000CD600000CD600000CD600000CD600000CD69A +S3210000023000000CD600000CD600000CD600000CD600000CD600000CD600000CD67E +S3210000024C00000CD600000CD600000CD600000CD600000CD600000CD600000CD662 +S3210000026800000CD600000CD600000CD600000CD600000CD600000CD600000CD646 +S3210000028400000CD600000CD600000CD600000CD600000CD600000CD600000CD62A +S321000002A000000CD600000CD600000CD600000CD600000CD600000CD600000CD60E +S321000002BC00000CD600000CD600000CD600000CD600000CD600000CD600000CD6F2 +S321000002D800000CD600000CD600000CD600000CD600000CD600000CD600000CD6D6 +S321000002F400000CD600000CD600000CD600000CD600000CD600000CD600000CD6BA +S3210000031000000CD600000CD600000CD600000CD600000CD600000CD600000CD69D +S3210000032C00000CD600000CD600000CD600000CD600000CD600000CD600000CD681 +S3210000034800000CD600000CD600000CD600000CD600000CD600000CD600000CD665 +S3210000036400000CD600000CD600000CD600000CD600000CD600000CD600000CD649 +S3210000038000000CD600000CD600000CD600000CD600000CD600000CD600000CD62D +S3210000039C00000CD600000CD600000CD600000CD600000CD600000CD600000CD611 +S321000003B800000CD600000CD600000CD600000CD600000CD600000CD600000CD6F5 +S321000003D400000CD600000CD600000CD600000CD600000CD600000CD600000CD6D9 +S315000003F000000CD600000CD600000CD600000CD66F +S31D00000400000000000000000000000000000000000000000000000000DE +S321000005004E5600004FEFFFE84EB9000006CE42974EB90000140670012E804EB915 +S3210000051C0000250A70022E804EB900001B9242974EB9000014CE4EB900001D3A9A +S321000005384EB90000221E70022E804EB900000F1042AF001442AF001041F92000B4 +S3210000055404042F48000A303C00A03F40000841F9000041302F4800042EBC000059 +S3210000057006F24EB900002FB042AF001442AF001041F9200004082F48000A303C32 +S3210000058C00A03F40000841F9000041352F4800042EBC000007EA4EB900002FB03A +S321000005A842AF001470032F40001042AF000A303C00A03F40000841F90000413AF7 +S321000005C42F4800042EBC000005EA4EB900002FB070022E804EB90000124C4EB94F +S321000005E00000358C51FC6000FFFC4E5600004FEFFFE448EF00F0000C2E3C00002E +S321000005FC01F47C007A0078004EB9000037182D40FFEC2F47000441EEFFEC2E8882 +S321000006184EB9000031884EB900001B347201B08157C049C044804A80660408C620 +S3210000063400004EB9000021E47201B081670408C600014EB9000011CE7201B08130 +S32100000650670408C600024EB90000277C7201B081670408C600054EB900001D0E8F +S3210000066C7201B081670408C600064EB9000013AA7201B081670408C600074EB9DA +S32100000688000024867201B081670408C60009BAB920000404660408C6000CB8B970 +S321000006A420000408660408C6000C2A39200004042839200004084A8667027E32C3 +S321000006C070032E804EB900000EBC6000FF424E560000598F70042E804EB90000D0 +S321000006DC3FDC4EB900000EA04E5E4E754E56000051FC6000FFFC4E560000226E3D +S321000006F8000841F9200004042008B3C0670651FC6000FFFC7001720274037604F0 +S3210000071478057A067C077E08207C00000009227C0000000A247C0000000B267C23 +S321000007300000000C287C0000000D2A7C0000000E2C7C0000000F0C8000000001F2 +S3210000074C660000960C81000000026600008C0C8200000003660000820C83000006 +S32100000768000466780C840000000566700C850000000666680C860000000766605E +S321000007840C8700000008665820080C8000000009664E20090C800000000A664420 +S321000007A0200A0C800000000B663A200B0C800000000C6630200C0C800000000DB8 +S321000007BC6626200D0C800000000E661C200E0C800000000F661220392000040484 +S321000007D8528023C0200004046000FF2A60FE4E5E4E754E560000226E000841F956 +S321000007F4200004082008B3C0670651FC6000FFFC700A7214741E762878327A3C77 +S321000008107C467E50207C0000005A227C00000064247C0000006E267C0000007816 +S3210000082C287C000000822A7C0000008C2C7C000000960C800000000A6600009682 +S321000008480C81000000146600008C0C820000001E660000820C83000000286678D2 +S321000008640C840000003266700C850000003C66680C860000004666600C8700000E +S321000008800050665820080C800000005A664E20090C80000000646644200A0C800D +S3210000089C0000006E663A200B0C80000000786630200C0C80000000826626200D74 +S321000008B80C800000008C661C200E0C80000000966612203920000404528023C086 +S321000008D4200004086000FF2A60FE4E5E4E754E56000051FC6000FFFC4E56000090 +S321000008F0700513C040120008303C300733C04012000010394012000208000003B4 +S3210000090C67F44E5E4E754E560000203C400000000280C0000000528023C0400088 +S321000009280000203C000000000280FFF800000680000000614E7B0C04203C02DCDE +S321000009446C0023C04012000C4EB9000008EC41F92000000020080280FFFF0000E7 +S3210000096008C0000923C0400000084EB900000D064E5E4E754E5600004E5E4E75DD +S3210000097C4E5600004E5E4E754E5600002F0C2F0B2209B1C1670C600210D92200B0 +S3210000099853804A8166F6265F285F4E5E4E754E5600002F0C49F9000042304A9457 +S321000009B4671A202C000822142241222C000420414EB900000984508C588C60E26A +S321000009D04AAC000466E04AAC000866DA285F4E5E4E754E5600002F0C7220B081EF +S321000009EC6514240844827203C481671690824218538266FA600C4A806746421869 +S32100000A08538066FA603E2400EA8A671C22482202EB89D1C14299429942994299E0 +S32100000A244299429942994299538266EC721F2400C481E48A670C224841F02C007B +S32100000A404299538266FA7203C08160B6285F4E5E4E7546FC27004FF920003FFCB6 +S32100000A5C203C200000214E7B0C054EB9000009124FF9200026042C7C00000000A5 +S32100000A784E5600004BF92000041841F92000060443F92000041891C92008670C67 +S32100000A9441F9200004184EB9000009E241F92000041843F92000041891C9200868 +S32100000AB0670C41F9200004184EB9000009E241F900004230200867064EB9000001 +S32100000ACC09A64EB90000097C4EB900000974487A001C42A74EB900000500508F97 +S32100000AE84E5E42A74EB9000008E2588F4AFC4E75000000004E5600002F074FEF5E +S32100000B04FFE8206E00082D50FFF83D680002FFE63D50FFE47200322EFFE4700CB1 +S32100000B20E0A12E3C000000FFC2872D41FFEC7400342EFFE4028200000C00E0827C +S32100000B3C7200322EFFE47003C28084812D42FFF07000302EFFE4E480C0872D4001 +S32100000B58FFE82D680004FFF4222EFFEC7004B28067147005B280670E7006B280E8 +S32100000B7467087007B28067024E71222EFFE8703FB280620001307002B28065006B +S32100000B9001285581323B1A0848C14EFB1A00003F005C0076008C008C008C00781C +S32100000BAC007A007C007E0080008C00820084008C008C008C008C008C008C008CCD +S32100000BC8008C00860088008800880088008800880088008A008A008A008A008A8F +S32100000BE4008A008A008A008A008A008A008A008A008A008A008A008C008C008C5D +S32100000C00008C008C008C008C008C008C008C008C008C008C008C008C008C4E71F7 +S32100000C1C222EFFF07004B28067147008B28067147009B2806714700CB2806714E2 +S32100000C3860164E716000008E4E71600000884E71600000824E71607C4E716078FD +S32100000C544E71222EFFF07004B28067147008B28067127009B2806710700CB2806C +S32100000C70670E60104E7160544E7160504E71604C4E7160484E7160444E71604007 +S32100000C8C4E71603C4E7160384E7160344E7160304E71602C4E7160284E7160241D +S32100000CA84E7160204E71601C4E7160184E716014222EFFE87040B28065080C8133 +S32100000CC4000000C063024E714FEF00182E1F4E5E4E754E5600004FEFFFEC48D72C +S32100000CE00307486F00184EB900000AFC4CEF030700044FEF00184E5E4E73202FB1 +S32100000CFC00044E7B08014E714E754E560000598F43F92000000041F9000000005C +S32100000D182008B3C067227200601643F92000000041F90000000020301C00238008 +S32100000D341C0052810C810000010065E22EBC200000004EB900000CFA4E5E4E7553 +S32100000D504E5600004FEFFFF448D71C00206E0008266E000C222E001024484A889D +S32100000D6C67244A8B67204A816F1C101349C057C049C044804A80660C20015381E7 +S32100000D884A806F0414DB60E642124CD71C004E5E4E754E5600004FEFFFF448D7E1 +S32100000DA41C00206E0008266E000C222E001024484A8867144A8B67104A81670C38 +S32100000DC0600214DB200153814A8066F64CD71C004E5E4E754E5600002F0C206E8A +S32100000DDC0008242E000C222E001022484A8867104A81670C600212C22001538113 +S32100000DF84A8066F6285F4E5E4E754E560000226E0008206E000C242E00104A89B2 +S32100000E1467284A8867244A82672060107000101172001210B08166165289528886 +S32100000E3053827200121170001010B28067E27000600290814E5E4E754E56000035 +S32100000E4C700913C040000C77207C40000C08203CFF7FFFFFC190700813C04000D1 +S32100000E680C50207C40000C0C203CFFFEFFFEC190207C401500007000301008C008 +S32100000E8400023080303C050B33C040150000303C30D433C0401500024E5E4E75AD +S32100000EA04E56000042394010006F700F13C04010002742394010000F4E5E4E7540 +S32100000EBC4E5600002F07222E00087004B2806502603C7E01E3AF4EB9000040A23F +S32100000ED8700010394010000FC0876712207C4010000F700010104687C0871080F1 +S32100000EF4600E207C4010000F70001010808710804EB9000040D82E1F4E5E4E7571 +S32100000F104E5600004FEFFFDC48EF188000182E2E0008700C2E804EB900003F3413 +S32100000F2C264870022F40000470012E804EB9000028CA268870642740000441F911 +S32100000F482000041827480008700C2E804EB900003F342848289342AC000441F9D9 +S32100000F642000041E2948000842AF00142F4700102F4B000A303C00A03F4000080E +S32100000F8041F9000041402F4800042EBC000011664EB900002FB042AF001442AFDC +S32100000F9C00102F4C000A303C00A03F40000841F9000041482F4800042EBC0000E3 +S32100000FB811084EB900002FB0700C2E804EB900003F34284870022F4000047001AE +S32100000FD42E804EB9000028CA288842AC000441F92000042029480008700C2E8091 +S32100000FF04EB900003F342648269470642740000441F92000041A2748000842AF1E +S3210000100C001442AF00102F4C000A303C00A03F40000841F9000041502F4800044F +S321000010282EBC000011664EB900002FB042AF00142F4700102F4B000A303C00A044 +S321000010443F40000841F9000041582F4800042EBC000011084EB900002FB0700C50 +S321000010602E804EB900003F34264870022F40000470052E804EB9000028CA268829 +S3210000107C70642740000441F92000042227480008700C2E804EB900003F34284808 +S32100001098289370642940000441F92000041C2948000842AF001442AF00102F4BC7 +S321000010B4000A303C00A03F40000841F9000041602F4800042EBC000011084EB91D +S321000010D000002FB042AF001442AF00102F4C000A303C00A03F40000841F90000C7 +S321000010EC41682F4800042EBC000011664EB900002FB04CEF188000184E5E4E751D +S321000011084E5600002F0C2F074FEFFFEC286E0008426EFFF47E0042AF000C2F6C30 +S321000011240004000841EEFFF42F4800042E944EB900002A907201B08157C049C0B9 +S3210000114044804A8066047E0160D4300748C0660A206C0008301052803080302E7F +S3210000115CFFF452803D40FFF460B84E5600004FEFFFE048EF10C00014286E0008AA +S321000011787C007E0042AF000C2F6C0004000841EEFFF02F4800042E944EB9000055 +S321000011942BFC7201B08156C049C044804A8066D87200322EFFF070003006B280EA +S321000011B067083C2EFFF07E0160C2300748C0660A206C00083010528030805286D7 +S321000011CC60AE4E5600002F0770017200606641F9200004183E301A0048C741F929 +S321000011E82000042434301A0048C2BE826602700043F92000042441F92000041803 +S3210000120434301A0033821A0041F92000041E3E301A0048C741F92000042A34307C +S321000012201A0048C2BE826602700043F92000042A41F92000041E34301A00338237 +S3210000123C1A0052817403B2826D942E1F4E5E4E754E5600002F074FEFFFE82E2EE0 +S32100001258000870042E804EB900003F34208742AF00142F4700102F48000A303CB1 +S3210000127400DC3F40000841F9000041702F4800042EBC000013124EB900002FB09A +S321000012904EB90000373823C02000043452B9200004344FEF00182E1F4E5E4E7516 +S321000012AC4E5600002F0C4FEFFFF4206E00084A88674E285070022D40FFF87059DC +S321000012C82D40FFF4222EFFF4202EFFF84C0108002D40FFF470142E804EB900002E +S321000012E432524A8C57C049C044804A8066CE42974EB9000032522E8C4EB9000087 +S3210000130030F042974EB9000030F060B47000284060AE4E5600002F074FEFFFE8B2 +S3210000131C206E00082E102E884EB900003F9E70642E804EB90000325242B9200019 +S32100001338043C41F92000043C2F4800142F47001042AF000A303C00A03F4000081A +S3210000135441F9000041782F4800042EBC000012AC4EB900002FB042AF00142F4700 +S32100001370001041F92000043C2F48000A303C00A03F40000841F9000041802F482B +S3210000138C00042EBC000012AC4EB900002FB0303920000430528033C020000430D7 +S321000013A860804E5600002F077E01720032392000040C7000303920000430B2807E +S321000013C466287E004EB90000373823C020000438B0B920000434652090B9200097 +S321000013E004347202B08163027E002007601230392000043033C02000040C60CC86 +S321000013FC7E0060EA2E1F4E5E4E754E5600002F072F064FEFFFE82C2E00087E0037 +S32100001418602C42AF00142F46001042AF000A303C00A03F40000841F9000041880B +S321000014342F4800042EBC000014584EB900002FB052877003BE806DCE4FEF0018C4 +S321000014502C1F2E1F4E5E4E754E5600002F072F064FEFFFF44EB9000040A22C39E5 +S3210000146C2000044052B9200004404EB9000040D8200652802E3C0000014D4C0070 +S321000014887800700A4C407007E28F4EB9000037182D40FFF42F47000441EEFFF48A +S321000014A42E884EB9000031882E864EB900000EBC2F47000441EEFFF42E884EB9D2 +S321000014C0000031882E864EB900000EBC60CE4E5600002F0C2F074FEFFFE82E2E08 +S321000014DC000870042F40000470052E804EB9000028CA42AF00142F4700102F48E1 +S321000014F8000A303C00A03F40000841F90000418D2F4800042EBC000015BA4EB9F2 +S3210000151400002FB04EB90000297A284842AF001442AF00102F4C000A303C00A025 +S321000015303F40000841F9000041922F4800042EBC000019B04EB900002FB041F9B7 +S3210000154C2000045C2F48001470022F40001042AF000A303C00A03F40000841F9B9 +S32100001568000041982F4800042EBC00001ABC4EB900002FB041F9200004602F4832 +S32100001584001470032F4000102F4C000A303C00A03F40000841F90000419E2F4897 +S321000015A000042EBC00001AD24EB900002FB04FEF00182E1F285F4E5E4E754E562C +S321000015BC00002F0C4FEFFFE8286E000870012F40000C42AF000841F92000044884 +S321000015D82F4800042E8C4EB900002A902E8C4EB900002DC27201B08157C049C087 +S321000015F444804A80660623C12000044442AF000C42AF000841EEFFF82F480004F8 +S321000016102E8C4EB900002BFC7201B081670623C120000444202EFFF8B0B92000A5 +S3210000162C04486708700123C0200004442E8C4EB900002DC24A806708700123C0E8 +S321000016482000044442AF000C42AF000841F9200004482F4800042E8C4EB9000040 +S321000016642A902E8C4EB900002DC27201B081670623C12000044442AF000C42AFAF +S32100001680000841EEFFF82F4800042E8C4EB900002BFC7201B081670623C12000A2 +S3210000169C04442E8C4EB900002DC24A806708700123C020000444202EFFF8B0B991 +S321000016B8200004486708700123C02000044470022D40FFF8601C42AF000C42AF39 +S321000016D4000841EEFFF82F4800042E8C4EB900002A9052AEFFF87205B2AEFFF80B +S321000016F062DC2E8C4EB900002DC27203B0816708700123C02000044470012D403B +S3210000170CFFF82F40000C42AF000841EEFFF82F4800042E8C4EB900002A9042AE44 +S32100001728FFF870012F40000C42AF000841EEFFF82F4800042E8C4EB900002A90A7 +S321000017442E8C4EB900002DC27205B0816708700123C02000044470012F40000C14 +S3210000176042AF000841EEFFF82F4800042E8C4EB900002A904A806708700123C0C5 +S3210000177C2000044442AF000C42AF000841EEFFF82F4800042E8C4EB900002A90D1 +S321000017984A806708700123C02000044442AEFFF8607C70012F40000C42AF000892 +S321000017B441EEFFF42F4800042E8C4EB900002BFC7201B081670623C12000044431 +S321000017D0222EFFF8B2AEFFF46708700123C020000444202EFFF446802D40FFF4CB +S321000017EC42AF000C42AF000841EEFFF42F4800042E8C4EB900002BFC7201B081BC +S32100001808670623C120000444222EFFF8B2AEFFF46708700123C02000044452AE40 +S32100001824FFF87205B2AEFFF86200FF7C2E8C4EB900002DC24A806708700123C0C3 +S3210000184020000444700A2D40FFF842AF000C42AF000841EEFFF82F4800042E8CEF +S3210000185C4EB900002A907201B081670623C120000444700B2D40FFF842AF000C70 +S3210000187842AF000841EEFFF82F4800042E8C4EB900002A907201B081670623C144 +S32100001894200004442E8C4EB900002DC27202B0816708700123C0200004447009D1 +S321000018B02D40FFF8602A70012F40000C42AF000841EEFFF82F4800042E8C4EB9E1 +S321000018CC00002A907201B081670623C12000044453AEFFF87207B2AEFFF863CEEA +S321000018E82E8C4EB900002DC27205B0816708700123C02000044470012F40000C6F +S3210000190442AF000841EEFFF82F4800042E8C4EB900002A904A806708700123C01F +S321000019202000044442AF000C42AF000841EEFFF82F4800042E8C4EB900002A902B +S3210000193C4A806708700123C02000044470072D40FFF8603A42AF000C42AF000829 +S3210000195841EEFFF42F4800042E8C4EB900002BFC7201B081670623C1200004448B +S32100001974222EFFF8B2AEFFF46708700123C02000044452AEFFF8720CB2AEFFF8C0 +S3210000199062BE2E8C4EB900002DC24A806708700123C02000044452B920000448F9 +S321000019AC6000FC1A4E5600002F0C4FEFFFF0286E000842AF000C42AF000842AF12 +S321000019C800042E8C4EB900002BFC7201B08157C049C044804A80660623C120004F +S321000019E4044442B92000045042974EB9000032E84A806708700123C0200004443B +S32100001A002EB9200004604EB9000034F042974EB9000032E87203B08167087001AE +S32100001A1C23C02000044470012F40000442974EB90000332042974EB9000032E84C +S32100001A387203B0816708700123C0200004442EB92000045C4EB9000034F04AB926 +S32100001A54200004506708700123C02000044442AF000C42AF000842AF00042E8C2C +S32100001A704EB900002A907201B081670623C1200004447001B0B92000045067067B +S32100001A8C23C02000044442974EB9000032E87201B081670623C12000044442AFA5 +S32100001AA8000442974EB90000332052B92000044C6000FF044E560000598F4297A2 +S32100001AC44EB90000341A52B92000045060F04E5600002F0C4FEFFFF0286E000832 +S32100001AE042974EB90000341A42AF000C70FF2F40000842AF00042E8C4EB900001D +S32100001AFC2BFC7201B08157C049C044804A80660623C12000044442AF000C42AFA9 +S32100001B18000842AF00042E8C4EB900002A907201B08167B423C12000044460AC1C +S32100001B344E560000203920000454B0B9200004486734203920000458B0B920004C +S32100001B50044C673020392000044823C02000045420392000044C23C02000045844 +S32100001B6C4AB92000044457C049C044806014700123C02000044460C2700123C062 +S32100001B882000044460C64E5E4E754E5600002F074FEFFFE82E2E000870022F40FA +S32100001BA40004700A2E804EB9000028CA23C82000046C42AF00142F47001041F9BA +S32100001BC02000046C2F48000A303C00A03F40000841F9000041A52F4800042EBCDA +S32100001BDC00001C924EB900002FB042AF00142F47001041F92000046C2F48000A7D +S32100001BF8303C00A03F40000841F9000041AD2F4800042EBC00001C204EB9000068 +S32100001C142FB04FEF00182E1F4E5E4E754E5600004FEFFFE048EF10C00014286E4B +S32100001C300008426EFFF07E007C00604442AF000C42AF000841EEFFF02F480004BE +S32100001C4C2E944EB900002A907201B08167047E0160204A8766124EB9000040A2B3 +S32100001C6852B9200004684EB9000040D8302EFFF052803D40FFF052867003BC8092 +S32100001C846DB670142E804EB90000325260A64E5600004FEFFFE048EF10C000147C +S32100001CA0286E00087C007E00604C42AF000C42AF000841EEFFF02F4800042E948D +S32100001CBC4EB900002BFC7201B081662E7200322EFFF070003006B28067087E0119 +S32100001CD83C2EFFF060164A8766124EB9000040A252B9200004644EB9000040D837 +S32100001CF452862E944EB900002DC24A8066A870122E804EB90000325260E84E56BF +S32100001D1000004AB92000046467184AB9200004686710700142B92000046442B9B2 +S32100001D2C200004686004700060EE4E5E4E754E5600002F0C4FEFFFE870042F4091 +S32100001D48000470052E804EB9000028CA284842AF001442AF00102F4C000A303CF2 +S32100001D6400A03F40000841F9000041B52F4800042EBC0000208C4EB900002FB00F +S32100001D8041F9200004842F48001470012F4000102F4C000A303C00A03F400008CC +S32100001D9C41F9000041BB2F4800042EBC000020164EB900002FB041F92000048090 +S32100001DB82F48001470022F4000102F4C000A303C00A03F40000841F9000041C139 +S32100001DD42F4800042EBC00001F624EB900002FB041F92000047C2F480014700349 +S32100001DF02F4000102F4C000A303C00A03F40000841F9000041C82F4800042EBC92 +S32100001E0C00001E204EB900002FB04FEF0018285F4E5E4E754E5600002F0C4FEF27 +S32100001E28FFEC286E000870012F40000C70FF2F40000841EEFFF82F4800042E8CE2 +S32100001E444EB900002BFC7201B08157C049C044804A80660623C120000470223CBA +S32100001E6011223344B2AEFFF86708700123C0200004702E8C4EB900002DC27201E5 +S32100001E7CB081670623C12000047042AEFFF842AF000C42AF000841EEFFF82F48B4 +S32100001E9800042E8C4EB900002BFC7201B081670623C120000470223C11223344AB +S32100001EB4B2AEFFF86708700123C02000047070012F40000C70FF2F40000841EE5D +S32100001ED0FFF82F4800042E8C4EB900002BFC7201B081670623C120000470223CAF +S32100001EEC01234567B2AEFFF86708700123C0200004702E8C4EB900002DC2720133 +S32100001F08B081670623C12000047042974EB90000341A70012F40000C70FF2F40A9 +S32100001F24000841EEFFF82F4800042E8C4EB900002BFC7201B081670623C12000F5 +S32100001F400470223CAABBAABBB2AEFFF86708700123C02000047042974EB9000055 +S32100001F5C341A6000FECE4E5600002F0C4FEFFFEC286E000870012F40000C70FFE8 +S32100001F782F40000841EEFFF82F4800042E8C4EB900002BFC7201B08157C049C083 +S32100001F9444804A80660623C120000470223C01234567B2AEFFF86708700123C071 +S32100001FB0200004702E8C4EB900002DC27201B081670623C12000047042974EB962 +S32100001FCC0000341A42AF000C70FF2F40000841EEFFF82F4800042E8C4EB9000060 +S32100001FE82BFC7201B081670623C120000470223CAABBAABBB2AEFFF867087001C8 +S3210000200423C02000047042974EB90000341A6000FF5C4E5600002F0C4FEFFFEC52 +S32100002020286E000870012F40000C70FF2F40000841EEFFF82F4800042E8C4EB9CC +S3210000203C00002BFC7201B08157C049C044804A80660623C120000470223C0123A3 +S321000020584567B2AEFFF86708700123C0200004702E8C4EB900002DC27201B081B8 +S32100002074670623C12000047052B92000047442974EB90000341A60984E560000F8 +S321000020902F0C4FEFFFEC286E0008203C112233442D40FFF842AF000C42AF0008CC +S321000020AC41EEFFF82F4800042E8C4EB900002A907201B08157C049C044804A80A4 +S321000020C8660623C1200004702E8C4EB900002DC24A806708700123C02000047041 +S321000020E4203C012345672D40FFF842AF000C42AF000841EEFFF82F4800042E8CF9 +S321000021004EB900002A907201B081670623C12000047042AEFFF842AF000C42AF9E +S3210000211C000841EEFFF82F4800042E8C4EB900002BFC7201B081670623C12000FB +S321000021380470700A2E804EB9000032522EB9200004844EB9000034F02EB920009D +S3210000215404804EB9000034F02EB92000047C4EB9000034F0203CAABBAABB2D4075 +S32100002170FFF870012F40000C42AF000841EEFFF82F4800042E8C4EB900002A9055 +S3210000218C7201B081670623C12000047070012F40000C42AF000841EEFFF82F4826 +S321000021A800042E8C4EB900002BFC4A806708700123C0200004702EB9200004807D +S321000021C44EB9000034F02EB92000047C4EB9000034F0700A2E804EB90000325269 +S321000021E06000FEB84E560000203920000478B0B920000474671A203920000474BB +S321000021FC23C0200004784AB92000047057C049C04480600A700123C02000047075 +S3210000221860DC4E5E4E754E5600004FEFFFE84EB90000297A23C8200004B44A88F1 +S321000022346700009041F9200004AC2F48001470022F40001042AF000A303C00A004 +S321000022503F40000841F9000041CF2F4800042EBC000022CA4EB900002FB041F92A +S3210000226C200004A82F48001470012F40001042AF000A303C00A03F40000841F941 +S32100002288000041D42F4800042EBC0000238C4EB900002FB042AF001442AF00101F +S321000022A442AF000A303C00A03F40000841F9000041D92F4800042EBC0000241A93 +S321000022C04EB900002FB04E5E4E754E5600002F07518F2EB9200004B44EB9000027 +S321000022DC29F27201B08156C049C044804A80660623C1200004887E00602A7002FE +S321000022F82F4000042EB9200004B44EB900002A3E7201B081670623C12000048882 +S3210000231470022E804EB9000032525287700ABE8065D07E00602470022E804EB90D +S32100002330000032522EB9200004B44EB9000029F27201B081670623C12000048885 +S3210000234C5287700ABE8065D62EB9200004B44EB9000029F27201B081660623C1CE +S321000023682000048852B920000494700123C02000048C42974EB90000341A42B9B7 +S321000023842000048C6000FF484E560000518F70FF2F4000042EB9200004B44EB9B4 +S321000023A000002A3E7201B08156C049C044804A806640B2B92000048C670823C14E +S321000023BC2000048860362EB9200004B44EB9000029F27201B081670623C12000C7 +S321000023D80488700123C02000049042974EB90000341A42B920000490600623C128 +S321000023F4200004882039200004B05280B0B9200004946708700123C0200004888C +S3210000241052B9200004B06000FF7A4E560000518F42AF00042EB9200004B44EB9B3 +S3210000242C00002A3E7201B08156C049C044804A8066E2B2B920000490670823C11B +S321000024482000048860D252B9200004982EB9200004A84EB9000034F02EB92000E8 +S3210000246404AC4EB9000034F02EB9200004B44EB9000029F27201B08167A223C109 +S3210000248020000488609A4E56000020392000049CB0B92000049467502039200086 +S3210000249C049423C02000049C2039200004A0B0B9200004B067402039200004B0B5 +S321000024B823C0200004A02039200004A4B0B920000498673020392000049823C086 +S321000024D4200004A47001B0B92000048856C049C04480601E700123C02000048837 +S321000024F060B2700123C02000048860C2700123C02000048860D24E5E4E754E5651 +S3210000250C00002F0C2F074FEFFFE82E2E0008700C2E804EB900003F3428484A8CC9 +S321000025286700009E42AF000470012E804EB9000028CA28882014671442AF000C23 +S3210000254442AF000842AF00042E804EB900002A904A94677070042E804EB900003A +S321000025603F3429480004206C000420BC000000FF42AC000842AF001442AF00100A +S3210000257C2F4C000A303C00A03F40000841F9000041DE2F4800042EBC00002684BD +S321000025984EB900002FB042AF001442AF00102F4C000A303C00A03F40000841F9E3 +S321000025B4000041E62F4800042EBC000026844EB900002FB0700C2E804EB90000B8 +S321000025D03F3428484A8C670000A042AF000470012E804EB9000028CA2888201438 +S321000025EC671442AF000C42AF000842AF00042E804EB900002A904A9467727004CD +S321000026082E804EB900003F3429480004206C000420BC00000FFF700A29400008AE +S3210000262442AF00142F4700102F4C000A303C00A03F40000841F9000041EE2F4811 +S3210000264000042EBC000026844EB900002FB042AF00142F4700102F4C000A303C7E +S3210000265C00A03F40000841F9000041F62F4800042EBC000026844EB900002FB0CF +S321000026784FEF00182E1F285F4E5E4E754E5600004FEFFFDC48EF18C00014286E31 +S3210000269400087C004EB9000040A23E39200004C03039200004C0528033C020002A +S321000026B004C04EB9000040D8266C00044AAC0008670C203C00000FFF2D40FFEC5C +S321000026CC600A203C000000FF2D40FFEC42AF000C2F6C0008000842AF00042E9470 +S321000026E84EB900002BFC7201B081666C202EFFECB09367027C017200600A268147 +S32100002704B29367027C015281B2AEFFEC63F042AF000C42AF000842AF00042E946A +S321000027204EB900002A904A8066027C01300648C0661A320748C17004B2806C1005 +S3210000273C41F9200004B841F01A00301052803080700A4C2C080000082E804EB9A1 +S32100002758000032526000FF7A4AAC00086600FF72203C0001000023C040000C148D +S321000027744E714E716000FF5E4E5600002F0770017E00603441F9200004C2343027 +S321000027907A0048C241F9200004B832307A0048C1B4816602700043F9200004C279 +S321000027AC41F9200004B832307A0033817A0052877204BE816DC62E1F4E5E4E756E +S321000027C84E560000226E000841E900082348000470FF234000082348000C234856 +S321000027E4001042914E5E4E754E560000206E000842A800104E5E4E754E5600003A +S321000028002F0C2F0B286E0008226E000C266C0004236B00040004236C0004000840 +S3210000281C206B0004214900082749000429490004234C00105294265F285F4E5E92 +S321000028384E754E5600002F0C2F0B266E0008226E000C221170FFB280673041EBD3 +S32100002854000860042068000428680004B29464F42368000400042869000429499E +S3210000287000082348000821490004234B001052936006206B001060DC265F285FB1 +S3210000288C4E5E4E754E560000206E0008226800042368000800082268000823683B +S321000028A80004000422680010B1E90004670842A800105391600823680008000482 +S321000028C460F04E5E4E754E5600004FEFFFF048EF10C000042C2E00082E2E000C8D +S321000028E04A8666087000204060000086704C2E804EB900003F3428484A8C67E869 +S321000028FC20074C06080052802E804EB900003F3428882214675220074C0608001F +S32100002918D0812940000442AC00382954000874FF2206D28220074C010800D09465 +S321000029342940000C2946003C29470040294200442942004841EC00102E884EB955 +S32100002950000027C841EC00242E884EB9000027C8204C600C2E8C4EB900003F9E03 +S3210000296C6000FF764CEF10C000044E5E4E754E5600002F0C4FEFFFF0704C2E8080 +S321000029884EB900003F3428484A8C675242AC0004429442AC000842AC000C42AC0E +S321000029A4003870012940003C42AC004070FF294000442940004841EC00102E88D5 +S321000029C04EB9000027C841EC00242E884EB9000027C842AF000C42AF000842AF1B +S321000029DC00042E8C4EB900002A90204C4FEF0010285F4E5E4E754E5600002F0CCB +S321000029F84FEFFFF0286E00084EB900003DFAB1EC000467047000602453AC000CA9 +S32100002A144AAC000C67047001601642AF000C42AF000842AF00042E8C4EB90000A0 +S32100002A302A9060E64FEF0010285F4E5E4E754E5600002F0C2F074FEFFFF0286E68 +S32100002A4C00082E2E000C4EB900003DFAB1EC0004672042AF000C2F47000842AF26 +S32100002A6800042E8C4EB900002BFC7201B081660C52AC000C600652AC000C70015F +S32100002A844FEF00102E1F285F4E5E4E754E5600004FEFFFDC48EF18C00014286E29 +S32100002AA00008266E000C2C2E00147E014AAE0010670000B64EB9000035E84EB92F +S32100002ABC000040A270FFB0AC0044660442AC004470FFB0AC0048660442AC0048B8 +S32100002AD84EB9000040D87001BE80660C41EEFFE82E884EB900003B122E8C4EB9BB +S32100002AF400002F804A80675E41EE00102F48000441EEFFE82E884EB900003B2E8C +S32100002B104A8066362F6E0010000441EC00102E884EB9000039AA2E8C4EB90000EE +S32100002B2C2EC64EB9000036024A806630203C0001000023C040000C144E714E71D6 +S32100002B48601E2E8C4EB900002EC64EB900003602600E2E8C4EB900002EC64EB9CF +S32100002B64000036024EB9000040A2202C0038B0AC003C64442F4600082F4B00046F +S32100002B802E8C4EB900002DE87E014AAC002457C049C044804A80662641EC002439 +S32100002B9C2E884EB900003A547201B0816614203C0001000023C040000C144E714F +S32100002BB84E7160027E004EB9000040D84A8766204AAE0010671A41EE00102F48A7 +S32100002BD4000441EEFFE82E884EB900003B2E4A8066027EFF70FFBE806700FEBE20 +S32100002BF020074CEF18C000144E5E4E754E5600004FEFFFDC48EF1CC00010286E90 +S32100002C0C0008246E000C2C2E00147E014AAE0010670000D04EB9000035E84EB9A9 +S32100002C28000040A270FFB0AC0044660442AC004470FFB0AC0048660442AC00484A +S32100002C444EB9000040D87001BE80660C41EEFFE42E884EB900003B122E8C4EB951 +S32100002C6000002F544A80677841EE00102F48000441EEFFE42E884EB900003B2E34 +S32100002C7C4A8066504A9466164EB9000040A22EAC00044EB900003E1A4EB900002F +S32100002C9840D82F6E0010000441EC00242E884EB9000039AA2E8C4EB900002EC6AB +S32100002CB44EB9000036024A806630203C0001000023C040000C144E714E71601EC3 +S32100002CD02E8C4EB900002EC64EB900003602600E2E8C4EB900002EC64EB90000C4 +S32100002CEC36024EB9000040A24AAC003867000088266C000C2F4A00042E8C4EB9AC +S32100002D0800002E844A86664453AC00384A94660A4EB900003DFA294800044AAC4F +S32100002D24001057C049C044804A80664E41EC00102E884EB900003A547201B081EF +S32100002D40663C203C0001000023C040000C144E714E71602A294B000C4AAC00248D +S32100002D5C672041EC00242E884EB900003A544A806710203C0001000023C0400071 +S32100002D780C144E714E717E0160027E004EB9000040D84A8766204AAE0010671A3D +S32100002D9441EE00102F48000441EEFFE42E884EB900003B2E4A8066027EFF70FF0D +S32100002DB0BE806700FE6420074CEF1CC000104E5E4E754E5600002F0C2F07286E92 +S32100002DCC00084EB9000040A22E2C00384EB9000040D820072E1F285F4E5E4E75D9 +S32100002DE84E5600002F0C4FEFFFF4286E0008206E000C222E0010202C0040661817 +S32100002E044A94660E2EAC00044EB900003EC242AC000452AC0038605E4A81662A34 +S32100002E202F4000082F4800042EAC00084EB900000D9A202C0040D1AC0008202CB1 +S32100002E3C0008B0AC000465D22954000860CC2F4000082F4800042EAC000C4EB945 +S32100002E5800000D9A202C004091AC000C202C000CB09464AA202C000490AC004066 +S32100002E742940000C609C4FEF000C285F4E5E4E754E5600004FEFFFF4226E00081E +S32100002E90206E000C4A91672A20290040D1A9000C2029000CB0A90004650423517C +S32100002EAC000C2F69004000082F69000C00042E884EB900000D9A4E5E4E754E56F9 +S32100002EC800002F0C598F286E00084EB9000040A2601A4AAC0024671A41EC0024D8 +S32100002EE42E884EB900003A544A80664C53AC00484AAC00486EE070FF2940004812 +S32100002F004EB9000040D84EB9000040A2601A4AAC0010671A41EC00102E884EB9AC +S32100002F1C00003A544A80662053AC00444AAC00446EE070FF294000444EB90000C7 +S32100002F3840D860104EB900003BB260AC4EB900003BB260D8588F285F4E5E4E75E6 +S32100002F544E5600002F0C2F07286E00084EB9000040A24AAC003857C749C7448798 +S32100002F704EB9000040D820072E1F285F4E5E4E754E5600002F0C2F07286E000803 +S32100002F8C4EB9000040A2202C0038B0AC003C57C749C744874EB9000040D82007DF +S32100002FA82E1F285F4E5E4E754E5600004FEFFFE048EF1CC0000C246E000C3C2EDC +S32100002FC400102E2E0018266E001C3E864EB900003D6428484A8C670000D62F4752 +S32100002FE000082F4A00042E8C4EB900003BCE206C00307200320670FFD28041F028 +S32100002FFC1C002F6E001200082F6E000800042E884EB90000405828884EB900002B +S3210000301840A252B9200004D47001B0B9200004D4660E23CC200004CC4EB9000085 +S321000030343C44601A4AB9200004E466122079200004CCBEA8002C650623CC200068 +S3210000305004CC202C002CB0B9200004DC630623C0200004DC2039200004F8294083 +S3210000306C004052B9200004F8202C002CB0B9200004E0630623C0200004E041EC79 +S3210000308800042F48000470144C2C0800002C41F92000057441F008002E884EB9AE +S321000030A4000027FC7C014EB9000040D860027CFF7001BC80662A4A8B6702268C41 +S321000030C04AB9200004E4671C2079200004CCBEA8002C6310203C0001000023C092 +S321000030DC40000C144E714E7120064CEF1CC0000C4E5E4E754E5600002F0C2F0B23 +S321000030F8518F266E00084EB9000040A2B7F9200004CC6604700026404A8B57C085 +S3210000311449C044804A8067082879200004CC6002284B41EC00042E884EB900003F +S3210000313028904AAC0028670C41EC00182E884EB900002890588C2F4C00042EBC2D +S3210000314C2000051C4EB9000027FC52B9200004D04EB9000040D84AB9200004E4CD +S3210000316867144A8B6610203C0001000023C040000C144E714E71508F265F285F76 +S321000031844E5E4E754E5600004FEFFFEC48EF10C00008286E00082E2E000C7C005C +S321000031A04EB9000035E82214DE812039200004D8B0816410BE81641ABEB9200006 +S321000031BC04D863127C01600EBE816508BEB9200004D863027C0128874A86675678 +S321000031D82039200004CC58802E804EB9000028902039200004CC5880204020871F +S321000031F4BEB9200004D8641A2039200004CC58802F4000042EB9200005444EB9DD +S321000032100000283A60182039200004CC58802F4000042EB9200005484EB90000D3 +S3210000322C283A4EB9000036024A806610203C0001000023C040000C144E714E7181 +S321000032484CEF10C000084E5E4E754E5600002F07518F2E2E000870004A876768B4 +S321000032644EB9000035E8DEB9200004D82039200004CC58802E804EB90000289003 +S321000032802039200004CC588020402087BEB9200004D8641A2039200004CC5880F2 +S3210000329C2F4000042EB9200005444EB90000283A60182039200004CC58802F40DC +S321000032B800042EB9200005484EB90000283A4EB9000036024A806610203C000157 +S321000032D4000023C040000C144E714E71508F2E1F4E5E4E754E5600002F0C2F0767 +S321000032F0286E00084EB9000040A24A8C57C049C044804A8067062879200004CCB3 +S3210000330C2E2C002C4EB9000040D820072E1F285F4E5E4E754E5600004FEFFFE8C7 +S3210000332848EF18C00008266E00082C2E000C7E007006BC8065027C054EB900004B +S3210000334440A2B7F9200004CC6604700026404A8B57C049C044804A806708287912 +S32100003360200004CC6002284B222C0044B2866700009ABC8163084A8B670A7E014E +S3210000337C60064A8B66027E01202C0044B0AC002C66042946002C294600447006C7 +S3210000339890862940001870144C01080041F92000057441F00800B1EC0014664040 +S321000033B441EC00042E884EB900002890202C002CB0B9200004E0630623C0200000 +S321000033D004E041EC00042F48000470144C2C0800002C41F92000057441F008000F +S321000033EC2E884EB9000027FC7001BE806610203C0001000023C040000C144E715B +S321000034084E714EB9000040D84CEF18C000084E5E4E754E5600002F0C2F0B518F41 +S32100003424266E00084EB9000040A2B7F9200004CC6604700026404A8B57C049C02C +S3210000344044804A8067082879200004CC6002284B41EC00042E884EB90000289061 +S3210000345C4AAC0028670C41EC00182E884EB900002890588C2F4C00042EBC200096 +S3210000347805084EB9000027FC4EB9000040D84A8B6610203C0001000023C0400011 +S321000034940C144E714E71508F265F285F4E5E4E754E5600002F07226E000870003C +S321000034B041F920000508B1E9001457C149C144814A81672641F9200005302E29C0 +S321000034CC0028B1C757C149C144817401B282670E4A8757C149C14481B2826602E5 +S321000034E870012E1F4E5E4E754E5600002F0C518F286E00084A8C67000084B9F9C5 +S32100003504200004CC677A4EB9000040A22E8C4EB9000034A47201B081666041ECBB +S3210000352000042E884EB900002890202C002CB0B9200004E0630623C0200004E0DB +S3210000353C41EC00042F48000470144C2C0800002C41F92000057441F008002E88CF +S321000035584EB9000027FC202C002C2079200004CCB0A8002C6510203C00010000D0 +S3210000357423C040000C144E714E714EB9000040D8508F285F4E5E4E754E560000DC +S321000035904FEFFFE842AF001442AF001042AF000A303C00A03F40000841F9000026 +S321000035AC41FE2F4800042EBC00003BC24EB900002FB07201B0816702601E700477 +S321000035C82E804EB900003FDC700123C0200004E442B9200004D84EB900004086F1 +S321000035E44E5E4E754E5600004EB9000040A252B9200004E84EB9000040D84E5EE7 +S321000036004E754E5600004FEFFFE448EF18C0000C7E004EB9000040A253B9200072 +S3210000361C04E84AB9200004E8660000E04AB9200004D4670000D67C00605C41ECAE +S3210000363800182E884EB90000289041EB00042E884EB900002890202C002CB0B95D +S32100003654200004E0630623C0200004E0588B2F4B000470144C2C0800002C41F935 +S321000036702000057441F008002E884EB9000027FC202C002C2079200004CCB0A82D +S3210000368C002C65027C014AB92000053056C049C044804A80670E20792000053C98 +S321000036A82D68000CFFEC600442AEFFEC286EFFEC264C4A8C6600FF784AB920006C +S321000036C404EC6718600C4EB90000375853B9200004EC4AB9200004EC66EC7C0175 +S321000036E07001BC806708B0B9200004F066187E0142B9200004F0203C00010000C6 +S321000036FC23C040000C144E714E714EB9000040D820074CEF18C0000C4E5E4E7517 +S321000037184E5600002F074EB9000040A22E39200004D84EB9000040D820072E1FD6 +S321000037344E5E4E754E5600002F074EB9000040A22E39200004D44EB9000040D8C3 +S3210000375020072E1F4E5E4E754E5600002F0C4FEFFFF44AB9200004E8660000D21D +S3210000376C52B9200004D84AB9200004D8670000822079200005484A9057C049C04C +S3210000378844804A80660000A62079200005482068000C2D68000CFFF8286EFFF8C6 +S321000037A44A8C6700009A2039200004D8B0AC00046500008C41EC00042E884EB998 +S321000037C0000028904AAC00286654202C002CB0B9200004E0625641EC00042F4812 +S321000037DC000470144C2C0800002C41F92000057441F008002E884EB9000027FCAB +S321000037F86082604620792000054820392000054423C02000054823C820000544BB +S3210000381452B9200004F46000FF6041EC00182E884EB900002890609E23C02000F5 +S3210000383004E060A242AEFFF86000FF6652B9200004EC4FEF000C285F4E5E4E7589 +S3210000384C4E5600004FEFFFF44AB9200004E86600010E2079200004CC20102079AF +S32100003868200004CCB0A80030621A72342039200004CCD0812F4000042EB9200090 +S3210000388404CC4EB9000006E870142F40000841F9000042032F48000420792000AF +S321000038A004CC2EA800304EB900000E024A80670A600000C253B9200004E024394F +S321000038BC200004E0721420014C02080043F9200005744AB1080067E02039200051 +S321000038D804E04C0018002041D1C92268000421690004000443E80008B3E8000499 +S321000038F46700009C206800042028000C23C0200004CC4AB9200004FC67000098DA +S321000039102039200004102079200004CCB0A80040670000842039200005045080AA +S3210000392CB0B920000500646C2079200004CC2028004023C020000410207920003A +S32100003948050420B9200004D858B92000050420792000050420B92000041058B965 +S3210000396420000504603C700123C0200004F0603272342039200004CCD0812F40D3 +S3210000398000042EB9200004CC4EB9000006E86000FF2A22680004216900040004AC +S3210000399C6000FF5A42B9200004FC4E5E4E754E5600002F07518F206E00082E2E1A +S321000039B8000C72182039200004CCD0812F4000042E884EB90000283A20392000B2 +S321000039D404CC58802E804EB90000289070FFBE80674EDEB9200004D8203920004E +S321000039F004CC588020402087BEB9200004D8641A2039200004CC58802F40000481 +S32100003A0C2EB9200005444EB90000283A60322039200004CC58802F4000042EB9D2 +S32100003A28200005484EB90000283A60182039200004CC58802F4000042EBC200090 +S32100003A4405084EB9000027FC508F2E1F4E5E4E754E5600002F0C4FEFFFF4206EF0 +S32100003A6000084A9056C049C044804A806700008A2068000C2D68000CFFF8286E02 +S32100003A7CFFF841EC00182E884EB9000028904AB9200004E8663C41EC00042E88DF +S32100003A984EB900002890202C002CB0B9200004E0625641EC00042F480004701480 +S32100003AB44C2C0800002C41F92000057441F008002E884EB9000027FC601441ECB7 +S32100003AD000182F4800042EBC200005304EB9000027FC202C002C2079200004CCD7 +S32100003AECB0A8002C54C049C04480601042AEFFF86000FF7C23C0200004E060A238 +S32100003B084FEF000C285F4E5E4E754E560000206E000820B9200004F420392000B7 +S32100003B2404D8214000044E5E4E754E5600004FEFFFF448D71880286E0008266E11 +S32100003B40000C4EB9000040A270FFB09367382039200004F4B09467102039200078 +S32100003B5C04D8B0AC000465047E0160142039200004D8242C000490822213B0818E +S32100003B7865107E014EB9000040D8200760247E0060F22039200004D89082928024 +S32100003B94268128B9200004F42039200004D8294000047E0060D24CD718804E5E96 +S32100003BB04E754E560000700123C0200004F04E5E4E754E5600004EB900003CCC02 +S32100003BCC60F84E5600002F0C2F074FEFFFF4286E0008206E000C2E2E0010700C19 +S32100003BE82F4000082F48000441EC00342E884EB900000D50422C003F7006BE80ED +S32100003C0465027E052947002C2947004441EC00042E884EB9000027EC41EC00181E +S32100003C202E884EB9000027EC294C00107006908729400018294C00244FEF000C3C +S32100003C3C2E1F285F4E5E4E754E5600002F07598F7E00601A70144C07080041F950 +S32100003C582000057441F008002E884EB9000027C852877006BE8065E02EBC2000F0 +S32100003C7405604EB9000027C82EBC2000054C4EB9000027C82EBC200005304EB93C +S32100003C90000027C82EBC2000051C4EB9000027C82EBC200005084EB9000027C8F5 +S32100003CAC41F92000056023C82000054841F92000054C23C820000544588F2E1FAC +S32100003CC84E5E4E754E5600002F0C2F07518F4AB9200004D06602607A4EB9000036 +S32100003CE440A252B9200004E84EB9000040D84AB92000051C57C749C744874EB962 +S32100003D00000036024A8766524EB9000040A24AB92000051C56C049C044804A8006 +S32100003D1C670E2079200005282D68000CFFF4600442AEFFF4286EFFF441EC000495 +S32100003D382E884EB90000289053B9200004D453B9200004D04EB9000040D82E8C17 +S32100003D544EB900003DD4508F2E1F285F4E5E4E754E5600002F0C2F074FEFFFF4CD +S32100003D703E2E000870482E804EB900003F3428484A8C674270003007E5882E802C +S32100003D8C4EB900003F3429480030222C0030671E70003007E5882F400008203C10 +S32100003DA8000000A52F4000042E814EB900000DD4600C2E8C4EB900003F9E7000D0 +S32100003DC42840204C4FEF000C2E1F285F4E5E4E754E5600002F0C598F286E000817 +S32100003DE02EAC00304EB900003F9E2E8C4EB900003F9E588F285F4E5E4E754E56B4 +S32100003DFC00002F0C4EB9000040A22879200004CC4EB9000040D8204C285F4E5E32 +S32100003E184E754E5600002F0C518F286E0008202C002C2079200004CCB0A8002CE3 +S32100003E34640000842079200004CC700690A8002C2940001870144C2C0800002C70 +S32100003E5041F92000057441F00800B1EC0014670E2079200004CC2968002C002CAC +S32100003E6C604C41EC00042E884EB9000028902079200004CC2968002C002C202C24 +S32100003E88002CB0B9200004E0630623C0200004E041EC00042F48000470144C2C87 +S32100003EA40800002C41F92000057441F008002E884EB9000027FC508F285F4E5ECA +S32100003EC04E754E5600002F0C518F286E00084A8C675A202C002CB0AC004467505A +S32100003EDC41EC00042E884EB900002890296C0044002C700690AC002C29400018BA +S32100003EF8202C002CB0B9200004E0630623C0200004E041EC00042F480004701443 +S32100003F144C2C0800002C41F92000057441F008002E884EB9000027FC508F285F8D +S32100003F304E5E4E754E5600002F0C2F072E2E0008700028404EB9000035E84AB988 +S32100003F4C200005EC670C4A874EB900003602204C603841F92000060423C820004C +S32100003F6805F842B9200005FC42B9200005F442B9200005F041F92000060442A8AC +S32100003F84000420BC200005F0700123C0200005EC60BC2E1F285F4E5E4E754E56BE +S32100003FA000002F0C286E00084A8C672A518C4EB9000035E8222C000443F9200010 +S32100003FBC05F860022251201158802040B29062F42891228C4EB900003602285FE3 +S32100003FD84E5E4E754E56FFF848D700C040C72007028000000700E0882C2E00085D +S32100003FF4028600000007E18E02870000F8FF8E8646C74CD700C04FEF00084E5E37 +S321000040104E75202F00044E7B00024E714E754FEFFFC448D77FFF2079200004CC04 +S3210000402C208F4EB9000040FE2079200004CC2E504CD77FFF4FEF003C4E73207902 +S32100004048200004CC2E504CD77FFF4FEF003C4E734E5600002F0C206E0008286E01 +S32100004064000C226E00102089213CDEADBEEF210C213C4000200042A041E8FFC894 +S32100004080285F4E5E4E754E56000042B9200004144EB900000E484EB90000404667 +S3210000409C70004E5E4E754E560000598F4AB920000414670852B920000414601C2E +S321000040B870042E804EB900003FDC4AB940000C1067E642974EB900003FDC60E4B7 +S321000040D44E5E4E754E560000598F203920000414538023C0200004144A8067021D +S321000040F0600842974EB900003FDC4E5E4E754E5600002F07598F70042E804EB9F1 +S3210000410C00003FDC2E0042B940000C144EB90000384C2E874EB900003FDC588FA4 +S321000041282E1F4E5E4E75000052656731005265673200436865636B0051436F6ECB +S32100004144734231005150726F644232005150726F6442330051436F6E7342340064 +S321000041605150726F6442350051436F6E7342360043524541544F52005355494340 +S3210000417C4944310053554943494432004C4544780047656E51004D754C6F7700C4 +S321000041984D754D6564004D75486967680051436F6E734E42005150726F644E4201 +S321000041B4005065656B4C005065656B4D005065656B4831005065656B48320052F7 +S321000041D06563310052656332005265633300506F6C53454D3100506F6C53454DEA +S321000041EC3200426C6B53454D3100426C6B53454D320049444C4500A5A5A5A5A5C9 +S31500004208A5A5A5A5A5A5A5A5A5A5A5A5A5A5A500F5 +S31D000042180000000011111111222222220FFF0000000000FF000099997D +S31D00004230000042182000040000000018000000000000000000000000DA +S70500000A529E diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.xMAP b/Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.xMAP new file mode 100644 index 000000000..c581e9047 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.xMAP @@ -0,0 +1,309 @@ + + +#>00001000 ___heap_size (linker command file) +#>00001000 ___stack_size (linker command file) +#>40000000 ___IPSBAR (linker command file) +#>20000000 ___RAMBAR (linker command file) +#>00004000 ___RAMBAR_SIZE (linker command file) +#>00000000 ___FLASHBAR (linker command file) +#>00020000 ___FLASHBAR_SIZE (linker command file) +#>20003FFC ___SP_AFTER_RESET (linker command file) + +# .userram + +# .code + +# .vectorram + +# .vectors + 00000000 00000400 .vectortable _vect (exceptions.c) + +# .cfmprotect + 00000400 00000018 .cfmconfig _cfm (cfm.c) + +# .text + 00000500 000000EA .text main (main.c) + 000005EA 000000E4 .text prvCheckTask (main.c) + 000006CE 0000001A .text prvSetupHardware (main.c) + 000006E8 0000000A .text vApplicationStackOverflowHook (main.c) + 000006F2 000000F8 .text vRegTest1Task (main.c) + 000007EA 000000F8 .text vRegTest2Task (main.c) + 000008E2 0000000A .text exit (main.c) + 000008EC 00000026 .text pll_init (MCF52221_sysinit.c) + 00000912 00000062 .text __initialize_hardware (MCF52221_sysinit.c) + 00000974 00000008 .text __initialize_system (startcf.c) + 0000097C 00000008 .text __call_static_initializers (startcf.c) + 00000984 00000022 .text __copy_rom_section (startcf.c) + 000009A6 0000003C .text __copy_rom_sections_to_ram (startcf.c) + 000009E2 00000070 .text clear_mem (startcf.c) + 00000A52 000000AA .text _startup (startcf.c) + 00000AFC 000001DA .text mcf_exception_handler (exceptions.c) + 00000CD6 00000024 .text asm_exception_handler (exceptions.c) + 00000CFA 0000000C .text mcf5xxx_wr_vbr (exceptions.c) + 00000D06 0000004A .text initialize_exceptions (exceptions.c) + 00000D50 0000004A .text strncpy (stdlib.c) + 00000D9A 0000003A .text memcpy (stdlib.c) + 00000DD4 0000002E .text memset (stdlib.c) + 00000E02 00000046 .text memcmp (stdlib.c) + 00000E48 00000058 .text vApplicationSetupInterrupts (FreeRTOS_Tick_Setup.c) + 00000EA0 0000001C .text vParTestInitialise (ParTest.c) + 00000EBC 00000054 .text vParTestToggleLED (ParTest.c) + 00000F10 000001F8 .text vStartBlockingQueueTasks (BlockQ.c) + 00001108 0000005E .text vBlockingQueueProducer (BlockQ.c) + 00001166 00000068 .text vBlockingQueueConsumer (BlockQ.c) + 000011CE 0000007E .text xAreBlockingQueuesStillRunning (BlockQ.c) + 0000124C 00000060 .text vCreateSuicidalTasks (death.c) + 000012AC 00000066 .text vSuicidalTask (death.c) + 00001312 00000098 .text vCreateTasks (death.c) + 000013AA 0000005C .text xIsCreateTaskStillRunning (death.c) + 00001406 00000052 .text vStartLEDFlashTasks (flash.c) + 00001458 00000076 .text vLEDFlashTask (flash.c) + 000014CE 000000EC .text vStartGenericQueueTasks (GenQTest.c) + 000015BA 000003F6 .text prvSendFrontAndBackTest (GenQTest.c) + 000019B0 0000010C .text prvLowPriorityMutexTask (GenQTest.c) + 00001ABC 00000016 .text prvMediumPriorityMutexTask (GenQTest.c) + 00001AD2 00000062 .text prvHighPriorityMutexTask (GenQTest.c) + 00001B34 0000005E .text xAreGenericQueueTasksStillRunning (GenQTest.c) + 00001B92 0000008E .text vStartPolledQueueTasks (PollQ.c) + 00001C20 00000072 .text vPolledQueueProducer (PollQ.c) + 00001C92 0000007C .text vPolledQueueConsumer (PollQ.c) + 00001D0E 0000002C .text xArePollingQueuesStillRunning (PollQ.c) + 00001D3A 000000E6 .text vStartQueuePeekTasks (QPeek.c) + 00001E20 00000142 .text prvHighestPriorityPeekTask (QPeek.c) + 00001F62 000000B4 .text prvHighPriorityPeekTask (QPeek.c) + 00002016 00000076 .text prvMediumPriorityPeekTask (QPeek.c) + 0000208C 00000158 .text prvLowPriorityPeekTask (QPeek.c) + 000021E4 0000003A .text xAreQueuePeekTasksStillRunning (QPeek.c) + 0000221E 000000AC .text vStartRecursiveMutexTasks (recmutex.c) + 000022CA 000000C2 .text prvRecursiveMutexControllingTask (recmutex.c) + 0000238C 0000008E .text prvRecursiveMutexBlockingTask (recmutex.c) + 0000241A 0000006C .text prvRecursiveMutexPollingTask (recmutex.c) + 00002486 00000084 .text xAreRecursiveMutexTasksStillRunning (recmutex.c) + 0000250A 0000017A .text vStartSemaphoreTasks (semtest.c) + 00002684 000000F8 .text prvSemaphoreTest (semtest.c) + 0000277C 0000004C .text xAreSemaphoreTasksStillRunning (semtest.c) + 000027C8 00000024 .text vListInitialise (list.c) + 000027EC 00000010 .text vListInitialiseItem (list.c) + 000027FC 0000003E .text vListInsertEnd (list.c) + 0000283A 00000056 .text vListInsert (list.c) + 00002890 0000003A .text vListRemove (list.c) + 000028CA 000000B0 .text xQueueCreate (queue.c) + 0000297A 00000078 .text xQueueCreateMutex (queue.c) + 000029F2 0000004C .text xQueueGiveMutexRecursive (queue.c) + 00002A3E 00000052 .text xQueueTakeMutexRecursive (queue.c) + 00002A90 0000016C .text xQueueGenericSend (queue.c) + 00002BFC 000001C6 .text xQueueGenericReceive (queue.c) + 00002DC2 00000026 .text uxQueueMessagesWaiting (queue.c) + 00002DE8 0000009C .text prvCopyDataToQueue (queue.c) + 00002E84 00000042 .text prvCopyDataFromQueue (queue.c) + 00002EC6 0000008E .text prvUnlockQueue (queue.c) + 00002F54 0000002C .text prvIsQueueEmpty (queue.c) + 00002F80 00000030 .text prvIsQueueFull (queue.c) + 00002FB0 00000140 .text xTaskCreate (tasks.c) + 000030F0 00000098 .text vTaskDelete (tasks.c) + 00003188 000000CA .text vTaskDelayUntil (tasks.c) + 00003252 00000096 .text vTaskDelay (tasks.c) + 000032E8 00000038 .text uxTaskPriorityGet (tasks.c) + 00003320 000000FA .text vTaskPrioritySet (tasks.c) + 0000341A 0000008A .text vTaskSuspend (tasks.c) + 000034A4 0000004C .text xTaskIsTaskSuspended (tasks.c) + 000034F0 0000009C .text vTaskResume (tasks.c) + 0000358C 0000005C .text vTaskStartScheduler (tasks.c) + 000035E8 0000001A .text vTaskSuspendAll (tasks.c) + 00003602 00000116 .text xTaskResumeAll (tasks.c) + 00003718 00000020 .text xTaskGetTickCount (tasks.c) + 00003738 00000020 .text uxTaskGetNumberOfTasks (tasks.c) + 00003758 000000F4 .text vTaskIncrementTick (tasks.c) + 0000384C 0000015E .text vTaskSwitchContext (tasks.c) + 000039AA 000000AA .text vTaskPlaceOnEventList (tasks.c) + 00003A54 000000BE .text xTaskRemoveFromEventList (tasks.c) + 00003B12 0000001C .text vTaskSetTimeOutState (tasks.c) + 00003B2E 00000084 .text xTaskCheckForTimeOut (tasks.c) + 00003BB2 00000010 .text vTaskMissedYield (tasks.c) + 00003BC2 0000000C .text prvIdleTask (tasks.c) + 00003BCE 00000076 .text prvInitialiseTCBVariables (tasks.c) + 00003C44 00000088 .text prvInitialiseTaskLists (tasks.c) + 00003CCC 00000098 .text prvCheckTasksWaitingTermination (tasks.c) + 00003D64 00000070 .text prvAllocateTCBAndStack (tasks.c) + 00003DD4 00000026 .text prvDeleteTCB (tasks.c) + 00003DFA 00000020 .text xTaskGetCurrentTaskHandle (tasks.c) + 00003E1A 000000A8 .text vTaskPriorityInherit (tasks.c) + 00003EC2 00000072 .text vTaskPriorityDisinherit (tasks.c) + 00003F34 0000006A .text pvPortMalloc (heap_2.c) + 00003F9E 0000003E .text vPortFree (heap_2.c) + 00003FDC 00000000 .text ulPortSetIPL (portasm.S) + 00003FDC 0000007C .text @DummyFn1 (portasm.S) + 00003FDC 0000007C .text .text (portasm.S) + 00003FDC 00000000 .text ulPortSetIPL (portasm.S) + 00004012 00000000 .text mcf5xxx_wr_cacrx (portasm.S) + 00004012 00000000 .text mcf5xxx_wr_cacrx (portasm.S) + 0000401E 00000000 .text vPortYieldISR (portasm.S) + 0000401E 00000000 .text vPortYieldISR (portasm.S) + 00004046 00000000 .text vPortStartFirstTask (portasm.S) + 00004046 00000000 .text vPortStartFirstTask (portasm.S) + 00004058 0000002E .text pxPortInitialiseStack (port.c) + 00004086 0000001C .text xPortStartScheduler (port.c) + 000040A2 00000036 .text vPortEnterCritical (port.c) + 000040D8 00000026 .text vPortExitCritical (port.c) + 000040FE 00000030 .text vPortYieldHandler (port.c) + 00004130 00000005 .rodata @147 (main.c) + 00004135 00000005 .rodata @148 (main.c) + 0000413A 00000006 .rodata @149 (main.c) + 00004140 00000008 .rodata @115 (BlockQ.c) + 00004148 00000008 .rodata @116 (BlockQ.c) + 00004150 00000008 .rodata @117 (BlockQ.c) + 00004158 00000008 .rodata @118 (BlockQ.c) + 00004160 00000008 .rodata @119 (BlockQ.c) + 00004168 00000008 .rodata @120 (BlockQ.c) + 00004170 00000008 .rodata @55 (death.c) + 00004178 00000008 .rodata @116 (death.c) + 00004180 00000008 .rodata @117 (death.c) + 00004188 00000005 .rodata @62 (flash.c) + 0000418D 00000005 .rodata @105 (GenQTest.c) + 00004192 00000006 .rodata @106 (GenQTest.c) + 00004198 00000006 .rodata @107 (GenQTest.c) + 0000419E 00000007 .rodata @108 (GenQTest.c) + 000041A5 00000008 .rodata @102 (PollQ.c) + 000041AD 00000008 .rodata @103 (PollQ.c) + 000041B5 00000006 .rodata @102 (QPeek.c) + 000041BB 00000006 .rodata @103 (QPeek.c) + 000041C1 00000007 .rodata @104 (QPeek.c) + 000041C8 00000007 .rodata @105 (QPeek.c) + 000041CF 00000005 .rodata @101 (recmutex.c) + 000041D4 00000005 .rodata @102 (recmutex.c) + 000041D9 00000005 .rodata @103 (recmutex.c) + 000041DE 00000008 .rodata @116 (semtest.c) + 000041E6 00000008 .rodata @117 (semtest.c) + 000041EE 00000008 .rodata @118 (semtest.c) + 000041F6 00000008 .rodata @119 (semtest.c) + 000041FE 00000005 .rodata @410 (tasks.c) + 00004203 00000014 .rodata ucExpectedStackBytes$615 (tasks.c) +#>00004218 ___ROM_AT (linker command file) +#>00004218 ___DATA_ROM (linker command file) + +# .data +#>20000400 ___DATA_RAM (linker command file) +#>20000400 __exception_table_start__ (linker command file) +# Exception index + 20000400 00000000 Exception Table Index () +#>20000400 __exception_table_end__ (linker command file) +#>20000400 ___sinit__ (linker command file) +# Linker generated symbols + 20000400 00000004 static initializer (linker generated) +#>20000404 __START_DATA (linker command file) + 20000404 00000004 .data ulRegTest1Counter (main.c) + 20000408 00000004 .data ulRegTest2Counter (main.c) + 2000040C 00000002 .data usLastCreationCount$155 (death.c) + 20000410 00000004 .data uxPreviousTask (tasks.c) + 20000414 00000004 .data ulCriticalNesting (port.c) +#>20000418 __END_DATA (linker command file) +#>20000418 __START_SDATA (linker command file) +#>20000418 __END_SDATA (linker command file) +#>20000418 ___DATA_END (linker command file) +#>20000418 __SDA_BASE (linker command file) + +# .bss +#>20000418 ___BSS_START (linker command file) +#>20000418 __START_SBSS (linker command file) +#>20000418 __END_SBSS (linker command file) +#>20000418 __START_BSS (linker command file) + 20000418 00000006 .bss sBlockingConsumerCount (BlockQ.c) + 2000041E 00000006 .bss sBlockingProducerCount (BlockQ.c) + 20000424 00000006 .bss sLastBlockingConsumerCount$321 (BlockQ.c) + 2000042A 00000006 .bss sLastBlockingProducerCount$322 (BlockQ.c) + 20000430 00000002 .bss usCreationCount (death.c) + 20000434 00000004 .bss uxTasksRunningAtStart (death.c) + 20000438 00000004 .bss uxTasksRunningNow$157 (death.c) + 2000043C 00000004 .bss xCreatedTask (death.c) + 20000440 00000004 .bss uxFlashTaskNumber (flash.c) + 20000444 00000004 .bss xErrorDetected (GenQTest.c) + 20000448 00000004 .bss ulLoopCounter (GenQTest.c) + 2000044C 00000004 .bss ulLoopCounter2 (GenQTest.c) + 20000450 00000004 .bss ulGuardedVariable (GenQTest.c) + 20000454 00000004 .bss ulLastLoopCounter$625 (GenQTest.c) + 20000458 00000004 .bss ulLastLoopCounter2$626 (GenQTest.c) + 2000045C 00000004 .bss xMediumPriorityMutexTask (GenQTest.c) + 20000460 00000004 .bss xHighPriorityMutexTask (GenQTest.c) + 20000464 00000004 .bss xPollingConsumerCount (PollQ.c) + 20000468 00000004 .bss xPollingProducerCount (PollQ.c) + 2000046C 00000004 .bss xPolledQueue$101 (PollQ.c) + 20000470 00000004 .bss xErrorDetected (QPeek.c) + 20000474 00000004 .bss ulLoopCounter (QPeek.c) + 20000478 00000004 .bss ulLastLoopCounter$438 (QPeek.c) + 2000047C 00000004 .bss xHighestPriorityTask (QPeek.c) + 20000480 00000004 .bss xHighPriorityTask (QPeek.c) + 20000484 00000004 .bss xMediumPriorityTask (QPeek.c) + 20000488 00000004 .bss xErrorOccurred (recmutex.c) + 2000048C 00000004 .bss xControllingIsSuspended (recmutex.c) + 20000490 00000004 .bss xBlockingIsSuspended (recmutex.c) + 20000494 00000004 .bss uxControllingCycles (recmutex.c) + 20000498 00000004 .bss uxPollingCycles (recmutex.c) + 2000049C 00000004 .bss uxLastControllingCycles$264 (recmutex.c) + 200004A0 00000004 .bss uxLastBlockingCycles$265 (recmutex.c) + 200004A4 00000004 .bss uxLastPollingCycles$266 (recmutex.c) + 200004A8 00000004 .bss xBlockingTaskHandle (recmutex.c) + 200004AC 00000004 .bss xControllingTaskHandle (recmutex.c) + 200004B0 00000004 .bss uxBlockingCycles (recmutex.c) + 200004B4 00000004 .bss xMutex (recmutex.c) + 200004B8 00000008 .bss sCheckVariables (semtest.c) + 200004C0 00000002 .bss sNextCheckVariable (semtest.c) + 200004C2 00000008 .bss sLastCheckVariables$297 (semtest.c) + 200004CC 00000004 .bss pxCurrentTCB (tasks.c) + 200004D0 00000004 .bss uxTasksDeleted (tasks.c) + 200004D4 00000004 .bss uxCurrentNumberOfTasks (tasks.c) + 200004D8 00000004 .bss xTickCount (tasks.c) + 200004DC 00000004 .bss uxTopUsedPriority (tasks.c) + 200004E0 00000004 .bss uxTopReadyPriority (tasks.c) + 200004E4 00000004 .bss xSchedulerRunning (tasks.c) + 200004E8 00000004 .bss uxSchedulerSuspended (tasks.c) + 200004EC 00000004 .bss uxMissedTicks (tasks.c) + 200004F0 00000004 .bss xMissedYield (tasks.c) + 200004F4 00000004 .bss xNumOfOverflows (tasks.c) + 200004F8 00000004 .bss uxTaskNumber (tasks.c) + 200004FC 00000004 .bss xTracing (tasks.c) + 20000500 00000004 .bss pcTraceBufferEnd (tasks.c) + 20000504 00000004 .bss pcTraceBuffer (tasks.c) + 20000508 00000014 .bss xSuspendedTaskList (tasks.c) + 2000051C 00000014 .bss xTasksWaitingTermination (tasks.c) + 20000530 00000014 .bss xPendingReadyList (tasks.c) + 20000544 00000004 .bss pxOverflowDelayedTaskList (tasks.c) + 20000548 00000004 .bss pxDelayedTaskList (tasks.c) + 2000054C 00000014 .bss xDelayedTaskList2 (tasks.c) + 20000560 00000014 .bss xDelayedTaskList1 (tasks.c) + 20000574 00000078 .bss pxReadyTasksLists (tasks.c) + 200005EC 00000004 .bss xHeapHasBeenInitialised$54 (heap_2.c) + 200005F0 00000008 .bss xEnd (heap_2.c) + 200005F8 00000008 .bss xStart (heap_2.c) + 20000600 00000004 .bss xHeap (heap_2.c) +#>20000604 __END_BSS (linker command file) +#>20000604 ___BSS_END (linker command file) + +# .custom +#>20000604 ___HEAP_START (linker command file) +#>20000604 ___heap_addr (linker command file) +#>20001604 ___HEAP_END (linker command file) +#>20001604 ___SP_END (linker command file) +#>20002604 ___SP_INIT (linker command file) +#>20000000 ___VECTOR_RAM (linker command file) +#>20002604 __SP_INIT (linker command file) +#>00004230 _romp_at (linker command file) + +# .romp +#>00004230 __S_romp (linker command file) + + +# Memory map: + v_addr p_addr size name + 00000000 00000000 00000400 .vectors vectorrom + 00000400 00000400 00000018 .cfmprotect cfmprotrom + 00000500 00000500 00000000 .code code + 00000500 00000500 00003D18 .text code + 20000000 20000000 00000000 .vectorram vectorram + 20000400 20000400 00000000 .userram userram + 20000400 00004218 00000018 .data userram + 20000418 20000418 000001EC .bss userram + 20000604 20000604 00000000 .custom userram + 20000604 00004230 00000018 .romp userram + +# Link start time: Fri Oct 17 15:01:49 2008 +# Link end time: Fri Oct 17 15:01:49 2008 diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.cfg b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.cfg new file mode 100644 index 000000000..b4c1de164 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.cfg @@ -0,0 +1,14 @@ +ResetHalt + +; Set VBR to the beginning of what will be SRAM +; VBR is an absolute CPU register +writecontrolreg 0x0801 0x20000000 + +; Set RAMBAR1 (SRAM) +writecontrolreg 0x0C05 0x20000021 + +; Set FLASHBAR (Flash) +writecontrolreg 0x0C04 0x00000061 + +; Enable PST[3:0] signals +writemem.b 0x40100074 0x0F diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.mem b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.mem new file mode 100644 index 000000000..bbd427adc --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.mem @@ -0,0 +1,31 @@ +// Memory Configuration File +// +// Description: +// A memory configuration file contains commands that define the legally accessible +// areas of memory for your specific board. Useful for example when the debugger +// tries to display the content of a "char *" variable, that has not yet been initialized. +// In this case the debugger may try to read from a bogus address, which could cause a +// bus error. +// +// Board: +// Freescale M52221DEMO +// +// Reference: +// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7 + + +// All reserved ranges read back 0xBABA... +reservedchar 0xBA + +address IPSBAR_BASE 0x40000000 + +usederivative "MCF52221" + +// Memory Map: +// ---------------------------------------------------------------------- +range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory +reserved 0x00020000 0x1FFFFFFF +range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM +reserved 0x20004000 0x40000007 +// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers +reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.cfg b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.cfg new file mode 100644 index 000000000..b4c1de164 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.cfg @@ -0,0 +1,14 @@ +ResetHalt + +; Set VBR to the beginning of what will be SRAM +; VBR is an absolute CPU register +writecontrolreg 0x0801 0x20000000 + +; Set RAMBAR1 (SRAM) +writecontrolreg 0x0C05 0x20000021 + +; Set FLASHBAR (Flash) +writecontrolreg 0x0C04 0x00000061 + +; Enable PST[3:0] signals +writemem.b 0x40100074 0x0F diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.mem b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.mem new file mode 100644 index 000000000..bbd427adc --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.mem @@ -0,0 +1,31 @@ +// Memory Configuration File +// +// Description: +// A memory configuration file contains commands that define the legally accessible +// areas of memory for your specific board. Useful for example when the debugger +// tries to display the content of a "char *" variable, that has not yet been initialized. +// In this case the debugger may try to read from a bogus address, which could cause a +// bus error. +// +// Board: +// Freescale M52221DEMO +// +// Reference: +// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7 + + +// All reserved ranges read back 0xBABA... +reservedchar 0xBA + +address IPSBAR_BASE 0x40000000 + +usederivative "MCF52221" + +// Memory Map: +// ---------------------------------------------------------------------- +range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory +reserved 0x00020000 0x1FFFFFFF +range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM +reserved 0x20004000 0x40000007 +// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers +reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.cfg b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.cfg new file mode 100644 index 000000000..b4c1de164 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.cfg @@ -0,0 +1,14 @@ +ResetHalt + +; Set VBR to the beginning of what will be SRAM +; VBR is an absolute CPU register +writecontrolreg 0x0801 0x20000000 + +; Set RAMBAR1 (SRAM) +writecontrolreg 0x0C05 0x20000021 + +; Set FLASHBAR (Flash) +writecontrolreg 0x0C04 0x00000061 + +; Enable PST[3:0] signals +writemem.b 0x40100074 0x0F diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.mem b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.mem new file mode 100644 index 000000000..bbd427adc --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.mem @@ -0,0 +1,31 @@ +// Memory Configuration File +// +// Description: +// A memory configuration file contains commands that define the legally accessible +// areas of memory for your specific board. Useful for example when the debugger +// tries to display the content of a "char *" variable, that has not yet been initialized. +// In this case the debugger may try to read from a bogus address, which could cause a +// bus error. +// +// Board: +// Freescale M52221DEMO +// +// Reference: +// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7 + + +// All reserved ranges read back 0xBABA... +reservedchar 0xBA + +address IPSBAR_BASE 0x40000000 + +usederivative "MCF52221" + +// Memory Map: +// ---------------------------------------------------------------------- +range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory +reserved 0x00020000 0x1FFFFFFF +range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM +reserved 0x20004000 0x40000007 +// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers +reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTFLASH.xml b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTFLASH.xml new file mode 100644 index 000000000..c3c1cb8e5 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTFLASH.xml @@ -0,0 +1,48 @@ + + + + + + false + 52221 + + true + {CodeWarrior}\ColdFire_Support\Initialization_Files\M52221DEMO.cfg + 0x20000000 + 0x00004000 + true + false + + + + 0x00000000 + CFM_MCF52221 + 4Kx32x1 + 0x00000000 + 0x0001FFFF + + + + false + nofile + Auto Detect + false + 0x00000000 + 0x0001FFFF + false + 0x00000000 + + + + true + + false + + + + FileOnTarg + 0x00000000 + 0x0000FFFF + + + diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221.h new file mode 100644 index 000000000..e133909d8 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221.h @@ -0,0 +1,89 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_H__ +#define __MCF52221_H__ + + +/********************************************************************/ +/* + * The basic data types + */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +typedef volatile uint8 vuint8; /* 8 bits */ +typedef volatile uint16 vuint16; /* 16 bits */ +typedef volatile uint32 vuint32; /* 32 bits */ + +#ifdef __cplusplus +extern "C" { +#endif + +#pragma define_section system ".system" far_absolute RW + +/*** + * MCF52221 Derivative Memory map definitions from linker command files: + * __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker + * symbols must be defined in the linker command file. + */ + +extern __declspec(system) uint8 __IPSBAR[]; +extern __declspec(system) uint8 __RAMBAR[]; +extern __declspec(system) uint8 __RAMBAR_SIZE[]; +extern __declspec(system) uint8 __FLASHBAR[]; +extern __declspec(system) uint8 __FLASHBAR_SIZE[]; + +#define IPSBAR_ADDRESS (uint32)__IPSBAR +#define RAMBAR_ADDRESS (uint32)__RAMBAR +#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE +#define FLASHBAR_ADDRESS (uint32)__FLASHBAR +#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE + + +#include "MCF52221_SCM.h" +#include "MCF52221_DMA.h" +#include "MCF52221_UART.h" +#include "MCF52221_I2C.h" +#include "MCF52221_QSPI.h" +#include "MCF52221_RTC.h" +#include "MCF52221_DTIM.h" +#include "MCF52221_INTC.h" +#include "MCF52221_GPIO.h" +#include "MCF52221_PAD.h" +#include "MCF52221_RCM.h" +#include "MCF52221_CCM.h" +#include "MCF52221_PMM.h" +#include "MCF52221_CLOCK.h" +#include "MCF52221_EPORT.h" +#include "MCF52221_PIT.h" +#include "MCF52221_ADC.h" +#include "MCF52221_GPTA.h" +#include "MCF52221_PWM.h" +#include "MCF52221_USB_OTG.h" +#include "MCF52221_CFM.h" + +#ifdef __cplusplus +} +#endif + + +#endif /* __MCF52221_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_ADC.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_ADC.h new file mode 100644 index 000000000..37fa3bda0 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_ADC.h @@ -0,0 +1,201 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_ADC_H__ +#define __MCF52221_ADC_H__ + + +/********************************************************************* +* +* Analog-to-Digital Converter (ADC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_ADC_CTRL1 (*(vuint16*)(0x40190000)) +#define MCF_ADC_CTRL2 (*(vuint16*)(0x40190002)) +#define MCF_ADC_ADZCC (*(vuint16*)(0x40190004)) +#define MCF_ADC_ADLST1 (*(vuint16*)(0x40190006)) +#define MCF_ADC_ADLST2 (*(vuint16*)(0x40190008)) +#define MCF_ADC_ADSDIS (*(vuint16*)(0x4019000A)) +#define MCF_ADC_ADSTAT (*(vuint16*)(0x4019000C)) +#define MCF_ADC_ADLSTAT (*(vuint16*)(0x4019000E)) +#define MCF_ADC_ADZCSTAT (*(vuint16*)(0x40190010)) +#define MCF_ADC_ADRSLT0 (*(vuint16*)(0x40190012)) +#define MCF_ADC_ADRSLT1 (*(vuint16*)(0x40190014)) +#define MCF_ADC_ADRSLT2 (*(vuint16*)(0x40190016)) +#define MCF_ADC_ADRSLT3 (*(vuint16*)(0x40190018)) +#define MCF_ADC_ADRSLT4 (*(vuint16*)(0x4019001A)) +#define MCF_ADC_ADRSLT5 (*(vuint16*)(0x4019001C)) +#define MCF_ADC_ADRSLT6 (*(vuint16*)(0x4019001E)) +#define MCF_ADC_ADRSLT7 (*(vuint16*)(0x40190020)) +#define MCF_ADC_ADLLMT0 (*(vuint16*)(0x40190022)) +#define MCF_ADC_ADLLMT1 (*(vuint16*)(0x40190024)) +#define MCF_ADC_ADLLMT2 (*(vuint16*)(0x40190026)) +#define MCF_ADC_ADLLMT3 (*(vuint16*)(0x40190028)) +#define MCF_ADC_ADLLMT4 (*(vuint16*)(0x4019002A)) +#define MCF_ADC_ADLLMT5 (*(vuint16*)(0x4019002C)) +#define MCF_ADC_ADLLMT6 (*(vuint16*)(0x4019002E)) +#define MCF_ADC_ADLLMT7 (*(vuint16*)(0x40190030)) +#define MCF_ADC_ADHLMT0 (*(vuint16*)(0x40190032)) +#define MCF_ADC_ADHLMT1 (*(vuint16*)(0x40190034)) +#define MCF_ADC_ADHLMT2 (*(vuint16*)(0x40190036)) +#define MCF_ADC_ADHLMT3 (*(vuint16*)(0x40190038)) +#define MCF_ADC_ADHLMT4 (*(vuint16*)(0x4019003A)) +#define MCF_ADC_ADHLMT5 (*(vuint16*)(0x4019003C)) +#define MCF_ADC_ADHLMT6 (*(vuint16*)(0x4019003E)) +#define MCF_ADC_ADHLMT7 (*(vuint16*)(0x40190040)) +#define MCF_ADC_ADOFS0 (*(vuint16*)(0x40190042)) +#define MCF_ADC_ADOFS1 (*(vuint16*)(0x40190044)) +#define MCF_ADC_ADOFS2 (*(vuint16*)(0x40190046)) +#define MCF_ADC_ADOFS3 (*(vuint16*)(0x40190048)) +#define MCF_ADC_ADOFS4 (*(vuint16*)(0x4019004A)) +#define MCF_ADC_ADOFS5 (*(vuint16*)(0x4019004C)) +#define MCF_ADC_ADOFS6 (*(vuint16*)(0x4019004E)) +#define MCF_ADC_ADOFS7 (*(vuint16*)(0x40190050)) +#define MCF_ADC_POWER (*(vuint16*)(0x40190052)) +#define MCF_ADC_CAL (*(vuint16*)(0x40190054)) +#define MCF_ADC_ADRSLT(x) (*(vuint16*)(0x40190012 + ((x)*0x2))) +#define MCF_ADC_ADLLMT(x) (*(vuint16*)(0x40190022 + ((x)*0x2))) +#define MCF_ADC_ADHLMT(x) (*(vuint16*)(0x40190032 + ((x)*0x2))) +#define MCF_ADC_ADOFS(x) (*(vuint16*)(0x40190042 + ((x)*0x2))) + + +/* Bit definitions and macros for MCF_ADC_CTRL1 */ +#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x7)<<0) +#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0xF)<<0x4) +#define MCF_ADC_CTRL1_HLMTIE (0x100) +#define MCF_ADC_CTRL1_LLMTIE (0x200) +#define MCF_ADC_CTRL1_ZCIE (0x400) +#define MCF_ADC_CTRL1_EOSIE0 (0x800) +#define MCF_ADC_CTRL1_SYNC0 (0x1000) +#define MCF_ADC_CTRL1_START0 (0x2000) +#define MCF_ADC_CTRL1_STOP0 (0x4000) + +/* Bit definitions and macros for MCF_ADC_CTRL2 */ +#define MCF_ADC_CTRL2_DIV(x) (((x)&0x1F)<<0) +#define MCF_ADC_CTRL2_SIMULT (0x20) +#define MCF_ADC_CTRL2_EOSIE1 (0x800) +#define MCF_ADC_CTRL2_SYNC1 (0x1000) +#define MCF_ADC_CTRL2_START1 (0x2000) +#define MCF_ADC_CTRL2_STOP1 (0x4000) + +/* Bit definitions and macros for MCF_ADC_ADZCC */ +#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x3)<<0) +#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x3)<<0x2) +#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x3)<<0x4) +#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x3)<<0x6) +#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x3)<<0x8) +#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x3)<<0xA) +#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x3)<<0xC) +#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x3)<<0xE) + +/* Bit definitions and macros for MCF_ADC_ADLST1 */ +#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x7)<<0) +#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x7)<<0x4) +#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x7)<<0x8) +#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x7)<<0xC) + +/* Bit definitions and macros for MCF_ADC_ADLST2 */ +#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x7)<<0) +#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x7)<<0x4) +#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x7)<<0x8) +#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x7)<<0xC) + +/* Bit definitions and macros for MCF_ADC_ADSDIS */ +#define MCF_ADC_ADSDIS_DS0 (0x1) +#define MCF_ADC_ADSDIS_DS1 (0x2) +#define MCF_ADC_ADSDIS_DS2 (0x4) +#define MCF_ADC_ADSDIS_DS3 (0x8) +#define MCF_ADC_ADSDIS_DS4 (0x10) +#define MCF_ADC_ADSDIS_DS5 (0x20) +#define MCF_ADC_ADSDIS_DS6 (0x40) +#define MCF_ADC_ADSDIS_DS7 (0x80) + +/* Bit definitions and macros for MCF_ADC_ADSTAT */ +#define MCF_ADC_ADSTAT_RDY0 (0x1) +#define MCF_ADC_ADSTAT_RDY1 (0x2) +#define MCF_ADC_ADSTAT_RDY2 (0x4) +#define MCF_ADC_ADSTAT_RDY3 (0x8) +#define MCF_ADC_ADSTAT_RDY4 (0x10) +#define MCF_ADC_ADSTAT_RDY5 (0x20) +#define MCF_ADC_ADSTAT_RDY6 (0x40) +#define MCF_ADC_ADSTAT_RDY7 (0x80) +#define MCF_ADC_ADSTAT_HLMTI (0x100) +#define MCF_ADC_ADSTAT_LLMTI (0x200) +#define MCF_ADC_ADSTAT_ZCI (0x400) +#define MCF_ADC_ADSTAT_EOSI0 (0x800) +#define MCF_ADC_ADSTAT_EOSI1 (0x1000) +#define MCF_ADC_ADSTAT_CIP1 (0x4000) +#define MCF_ADC_ADSTAT_CIP0 (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLSTAT */ +#define MCF_ADC_ADLSTAT_LLS0 (0x1) +#define MCF_ADC_ADLSTAT_LLS1 (0x2) +#define MCF_ADC_ADLSTAT_LLS2 (0x4) +#define MCF_ADC_ADLSTAT_LLS3 (0x8) +#define MCF_ADC_ADLSTAT_LLS4 (0x10) +#define MCF_ADC_ADLSTAT_LLS5 (0x20) +#define MCF_ADC_ADLSTAT_LLS6 (0x40) +#define MCF_ADC_ADLSTAT_LLS7 (0x80) +#define MCF_ADC_ADLSTAT_HLS0 (0x100) +#define MCF_ADC_ADLSTAT_HLS1 (0x200) +#define MCF_ADC_ADLSTAT_HLS2 (0x400) +#define MCF_ADC_ADLSTAT_HLS3 (0x800) +#define MCF_ADC_ADLSTAT_HLS4 (0x1000) +#define MCF_ADC_ADLSTAT_HLS5 (0x2000) +#define MCF_ADC_ADLSTAT_HLS6 (0x4000) +#define MCF_ADC_ADLSTAT_HLS7 (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADZCSTAT */ +#define MCF_ADC_ADZCSTAT_ZCS0 (0x1) +#define MCF_ADC_ADZCSTAT_ZCS1 (0x2) +#define MCF_ADC_ADZCSTAT_ZCS2 (0x4) +#define MCF_ADC_ADZCSTAT_ZCS3 (0x8) +#define MCF_ADC_ADZCSTAT_ZCS4 (0x10) +#define MCF_ADC_ADZCSTAT_ZCS5 (0x20) +#define MCF_ADC_ADZCSTAT_ZCS6 (0x40) +#define MCF_ADC_ADZCSTAT_ZCS7 (0x80) + +/* Bit definitions and macros for MCF_ADC_ADRSLT */ +#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0xFFF)<<0x3) +#define MCF_ADC_ADRSLT_SEXT (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLLMT */ +#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0xFFF)<<0x3) + +/* Bit definitions and macros for MCF_ADC_ADHLMT */ +#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0xFFF)<<0x3) + +/* Bit definitions and macros for MCF_ADC_ADOFS */ +#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0xFFF)<<0x3) + +/* Bit definitions and macros for MCF_ADC_POWER */ +#define MCF_ADC_POWER_PD0 (0x1) +#define MCF_ADC_POWER_PD1 (0x2) +#define MCF_ADC_POWER_PD2 (0x4) +#define MCF_ADC_POWER_APD (0x8) +#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x3F)<<0x4) +#define MCF_ADC_POWER_PSTS0 (0x400) +#define MCF_ADC_POWER_PSTS1 (0x800) +#define MCF_ADC_POWER_PSTS2 (0x1000) +#define MCF_ADC_POWER_ASB (0x8000) + +/* Bit definitions and macros for MCF_ADC_CAL */ +#define MCF_ADC_CAL_SEL_VREFL (0x4000) +#define MCF_ADC_CAL_SEL_VREFH (0x8000) + + +#endif /* __MCF52221_ADC_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CCM.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CCM.h new file mode 100644 index 000000000..08a52235a --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CCM.h @@ -0,0 +1,46 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_CCM_H__ +#define __MCF52221_CCM_H__ + + +/********************************************************************* +* +* Chip Configuration Module (CCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CCM_CCR (*(vuint16*)(0x40110004)) +#define MCF_CCM_RCON (*(vuint16*)(0x40110008)) +#define MCF_CCM_CIR (*(vuint16*)(0x4011000A)) + + +/* Bit definitions and macros for MCF_CCM_CCR */ +#define MCF_CCM_CCR_Mode(x) (((x)&0x7)<<0x8) +#define MCF_CCM_CCR_MODE_SINGLECHIP (0x600) +#define MCF_CCM_CCR_MODE_EZPORT (0x500) + +/* Bit definitions and macros for MCF_CCM_RCON */ +#define MCF_CCM_RCON_MODE (0x1) +#define MCF_CCM_RCON_RLOAD (0x20) + +/* Bit definitions and macros for MCF_CCM_CIR */ +#define MCF_CCM_CIR_PRN(x) (((x)&0x3F)<<0) +#define MCF_CCM_CIR_PIN(x) (((x)&0x3FF)<<0x6) + + +#endif /* __MCF52221_CCM_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CFM.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CFM.h new file mode 100644 index 000000000..398e1c963 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CFM.h @@ -0,0 +1,84 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_CFM_H__ +#define __MCF52221_CFM_H__ + + +/********************************************************************* +* +* ColdFire Flash Module (CFM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CFM_CFMMCR (*(vuint16*)(0x401D0000)) +#define MCF_CFM_CFMCLKD (*(vuint8 *)(0x401D0002)) +#define MCF_CFM_CFMSEC (*(vuint32*)(0x401D0008)) +#define MCF_CFM_CFMPROT (*(vuint32*)(0x401D0010)) +#define MCF_CFM_CFMSACC (*(vuint32*)(0x401D0014)) +#define MCF_CFM_CFMDACC (*(vuint32*)(0x401D0018)) +#define MCF_CFM_CFMUSTAT (*(vuint8 *)(0x401D0020)) +#define MCF_CFM_CFMCMD (*(vuint8 *)(0x401D0024)) +#define MCF_CFM_CFMCLKSEL (*(vuint16*)(0x401D004A)) + + +/* Bit definitions and macros for MCF_CFM_CFMMCR */ +#define MCF_CFM_CFMMCR_KEYACC (0x20) +#define MCF_CFM_CFMMCR_CCIE (0x40) +#define MCF_CFM_CFMMCR_CBEIE (0x80) +#define MCF_CFM_CFMMCR_AEIE (0x100) +#define MCF_CFM_CFMMCR_PVIE (0x200) +#define MCF_CFM_CFMMCR_LOCK (0x400) + +/* Bit definitions and macros for MCF_CFM_CFMCLKD */ +#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0) +#define MCF_CFM_CFMCLKD_PRDIV8 (0x40) +#define MCF_CFM_CFMCLKD_DIVLD (0x80) + +/* Bit definitions and macros for MCF_CFM_CFMSEC */ +#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0) +#define MCF_CFM_CFMSEC_SECSTAT (0x40000000) +#define MCF_CFM_CFMSEC_KEYEN (0x80000000) + +/* Bit definitions and macros for MCF_CFM_CFMPROT */ +#define MCF_CFM_CFMPROT_PROTECT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CFM_CFMSACC */ +#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CFM_CFMDACC */ +#define MCF_CFM_CFMDACC_DACC(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CFM_CFMUSTAT */ +#define MCF_CFM_CFMUSTAT_BLANK (0x4) +#define MCF_CFM_CFMUSTAT_ACCERR (0x10) +#define MCF_CFM_CFMUSTAT_PVIOL (0x20) +#define MCF_CFM_CFMUSTAT_CCIF (0x40) +#define MCF_CFM_CFMUSTAT_CBEIF (0x80) + +/* Bit definitions and macros for MCF_CFM_CFMCMD */ +#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0) +#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5) +#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6) +#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20) +#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40) +#define MCF_CFM_CFMCMD_MASS_ERASE (0x41) + +/* Bit definitions and macros for MCF_CFM_CFMCLKSEL */ +#define MCF_CFM_CFMCLKSEL_CLKSEL(x) (((x)&0x3)<<0) + + +#endif /* __MCF52221_CFM_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CLOCK.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CLOCK.h new file mode 100644 index 000000000..bbd9b3191 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CLOCK.h @@ -0,0 +1,84 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_CLOCK_H__ +#define __MCF52221_CLOCK_H__ + + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SYNCR (*(vuint16*)(0x40120000)) +#define MCF_CLOCK_SYNSR (*(vuint8 *)(0x40120002)) +#define MCF_CLOCK_ROCR (*(vuint16*)(0x40120004)) +#define MCF_CLOCK_LPDR (*(vuint8 *)(0x40120007)) +#define MCF_CLOCK_CCHR (*(vuint8 *)(0x40120008)) +#define MCF_CLOCK_CCLR (*(vuint8 *)(0x40120009)) +#define MCF_CLOCK_OCHR (*(vuint8 *)(0x4012000A)) +#define MCF_CLOCK_OCLR (*(vuint8 *)(0x4012000B)) +#define MCF_CLOCK_RTCDR (*(vuint32*)(0x4012000C)) + + +/* Bit definitions and macros for MCF_CLOCK_SYNCR */ +#define MCF_CLOCK_SYNCR_PLLEN (0x1) +#define MCF_CLOCK_SYNCR_PLLMODE (0x2) +#define MCF_CLOCK_SYNCR_CLKSRC (0x4) +#define MCF_CLOCK_SYNCR_FWKUP (0x20) +#define MCF_CLOCK_SYNCR_DISCLK (0x40) +#define MCF_CLOCK_SYNCR_LOCEN (0x80) +#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8) +#define MCF_CLOCK_SYNCR_LOCRE (0x800) +#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC) +#define MCF_CLOCK_SYNCR_LOLRE (0x8000) + +/* Bit definitions and macros for MCF_CLOCK_SYNSR */ +#define MCF_CLOCK_SYNSR_LOCS (0x4) +#define MCF_CLOCK_SYNSR_LOCK (0x8) +#define MCF_CLOCK_SYNSR_LOCKS (0x10) +#define MCF_CLOCK_SYNSR_CRYOSC (0x20) +#define MCF_CLOCK_SYNSR_OCOSC (0x40) +#define MCF_CLOCK_SYNSR_EXTOSC (0x80) + +/* Bit definitions and macros for MCF_CLOCK_ROCR */ +#define MCF_CLOCK_ROCR_TRIM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_CLOCK_LPDR */ +#define MCF_CLOCK_LPDR_LPD(x) (((x)&0xF)<<0) + +/* Bit definitions and macros for MCF_CLOCK_CCHR */ +#define MCF_CLOCK_CCHR_CCHR(x) (((x)&0x7)<<0) + +/* Bit definitions and macros for MCF_CLOCK_CCLR */ +#define MCF_CLOCK_CCLR_OSCSEL (0x1) + +/* Bit definitions and macros for MCF_CLOCK_OCHR */ +#define MCF_CLOCK_OCHR_STBY (0x40) +#define MCF_CLOCK_OCHR_OCOEN (0x80) + +/* Bit definitions and macros for MCF_CLOCK_OCLR */ +#define MCF_CLOCK_OCLR_RANGE (0x10) +#define MCF_CLOCK_OCLR_LPEN (0x20) +#define MCF_CLOCK_OCLR_REFS (0x40) +#define MCF_CLOCK_OCLR_OSCEN (0x80) + +/* Bit definitions and macros for MCF_CLOCK_RTCDR */ +#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF52221_CLOCK_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DMA.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DMA.h new file mode 100644 index 000000000..1f297b1e8 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DMA.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_DMA_H__ +#define __MCF52221_DMA_H__ + + +/********************************************************************* +* +* DMA Controller (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA0_SAR (*(vuint32*)(0x40000100)) +#define MCF_DMA0_DAR (*(vuint32*)(0x40000104)) +#define MCF_DMA0_DSR (*(vuint8 *)(0x40000108)) +#define MCF_DMA0_BCR (*(vuint32*)(0x40000108)) +#define MCF_DMA0_DCR (*(vuint32*)(0x4000010C)) + +#define MCF_DMA1_SAR (*(vuint32*)(0x40000110)) +#define MCF_DMA1_DAR (*(vuint32*)(0x40000114)) +#define MCF_DMA1_DSR (*(vuint8 *)(0x40000118)) +#define MCF_DMA1_BCR (*(vuint32*)(0x40000118)) +#define MCF_DMA1_DCR (*(vuint32*)(0x4000011C)) + +#define MCF_DMA2_SAR (*(vuint32*)(0x40000120)) +#define MCF_DMA2_DAR (*(vuint32*)(0x40000124)) +#define MCF_DMA2_DSR (*(vuint8 *)(0x40000128)) +#define MCF_DMA2_BCR (*(vuint32*)(0x40000128)) +#define MCF_DMA2_DCR (*(vuint32*)(0x4000012C)) + +#define MCF_DMA3_SAR (*(vuint32*)(0x40000130)) +#define MCF_DMA3_DAR (*(vuint32*)(0x40000134)) +#define MCF_DMA3_DSR (*(vuint8 *)(0x40000138)) +#define MCF_DMA3_BCR (*(vuint32*)(0x40000138)) +#define MCF_DMA3_DCR (*(vuint32*)(0x4000013C)) + +#define MCF_DMA_SAR(x) (*(vuint32*)(0x40000100 + ((x)*0x10))) +#define MCF_DMA_DAR(x) (*(vuint32*)(0x40000104 + ((x)*0x10))) +#define MCF_DMA_DSR(x) (*(vuint8 *)(0x40000108 + ((x)*0x10))) +#define MCF_DMA_BCR(x) (*(vuint32*)(0x40000108 + ((x)*0x10))) +#define MCF_DMA_DCR(x) (*(vuint32*)(0x4000010C + ((x)*0x10))) + + +/* Bit definitions and macros for MCF_DMA_SAR */ +#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DAR */ +#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DSR */ +#define MCF_DMA_DSR_DONE (0x1) +#define MCF_DMA_DSR_BSY (0x2) +#define MCF_DMA_DSR_REQ (0x4) +#define MCF_DMA_DSR_BED (0x10) +#define MCF_DMA_DSR_BES (0x20) +#define MCF_DMA_DSR_CE (0x40) + +/* Bit definitions and macros for MCF_DMA_BCR */ +#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFF)<<0) +#define MCF_DMA_BCR_DSR(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_DMA_DCR */ +#define MCF_DMA_DCR_LCH2(x) (((x)&0x3)<<0) +#define MCF_DMA_DCR_LCH2_CH0 (0) +#define MCF_DMA_DCR_LCH2_CH1 (0x1) +#define MCF_DMA_DCR_LCH2_CH2 (0x2) +#define MCF_DMA_DCR_LCH2_CH3 (0x3) +#define MCF_DMA_DCR_LCH1(x) (((x)&0x3)<<0x2) +#define MCF_DMA_DCR_LCH1_CH0 (0) +#define MCF_DMA_DCR_LCH1_CH1 (0x1) +#define MCF_DMA_DCR_LCH1_CH2 (0x2) +#define MCF_DMA_DCR_LCH1_CH3 (0x3) +#define MCF_DMA_DCR_LINKCC(x) (((x)&0x3)<<0x4) +#define MCF_DMA_DCR_D_REQ (0x80) +#define MCF_DMA_DCR_DMOD(x) (((x)&0xF)<<0x8) +#define MCF_DMA_DCR_DMOD_DIS (0) +#define MCF_DMA_DCR_DMOD_16 (0x1) +#define MCF_DMA_DCR_DMOD_32 (0x2) +#define MCF_DMA_DCR_DMOD_64 (0x3) +#define MCF_DMA_DCR_DMOD_128 (0x4) +#define MCF_DMA_DCR_DMOD_256 (0x5) +#define MCF_DMA_DCR_DMOD_512 (0x6) +#define MCF_DMA_DCR_DMOD_1K (0x7) +#define MCF_DMA_DCR_DMOD_2K (0x8) +#define MCF_DMA_DCR_DMOD_4K (0x9) +#define MCF_DMA_DCR_DMOD_8K (0xA) +#define MCF_DMA_DCR_DMOD_16K (0xB) +#define MCF_DMA_DCR_DMOD_32K (0xC) +#define MCF_DMA_DCR_DMOD_64K (0xD) +#define MCF_DMA_DCR_DMOD_128K (0xE) +#define MCF_DMA_DCR_DMOD_256K (0xF) +#define MCF_DMA_DCR_SMOD(x) (((x)&0xF)<<0xC) +#define MCF_DMA_DCR_SMOD_DIS (0) +#define MCF_DMA_DCR_SMOD_16 (0x1) +#define MCF_DMA_DCR_SMOD_32 (0x2) +#define MCF_DMA_DCR_SMOD_64 (0x3) +#define MCF_DMA_DCR_SMOD_128 (0x4) +#define MCF_DMA_DCR_SMOD_256 (0x5) +#define MCF_DMA_DCR_SMOD_512 (0x6) +#define MCF_DMA_DCR_SMOD_1K (0x7) +#define MCF_DMA_DCR_SMOD_2K (0x8) +#define MCF_DMA_DCR_SMOD_4K (0x9) +#define MCF_DMA_DCR_SMOD_8K (0xA) +#define MCF_DMA_DCR_SMOD_16K (0xB) +#define MCF_DMA_DCR_SMOD_32K (0xC) +#define MCF_DMA_DCR_SMOD_64K (0xD) +#define MCF_DMA_DCR_SMOD_128K (0xE) +#define MCF_DMA_DCR_SMOD_256K (0xF) +#define MCF_DMA_DCR_START (0x10000) +#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11) +#define MCF_DMA_DCR_DSIZE_LONG (0) +#define MCF_DMA_DCR_DSIZE_BYTE (0x1) +#define MCF_DMA_DCR_DSIZE_WORD (0x2) +#define MCF_DMA_DCR_DSIZE_LINE (0x3) +#define MCF_DMA_DCR_DINC (0x80000) +#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14) +#define MCF_DMA_DCR_SSIZE_LONG (0) +#define MCF_DMA_DCR_SSIZE_BYTE (0x1) +#define MCF_DMA_DCR_SSIZE_WORD (0x2) +#define MCF_DMA_DCR_SSIZE_LINE (0x3) +#define MCF_DMA_DCR_SINC (0x400000) +#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19) +#define MCF_DMA_DCR_BWC_16K (0x1) +#define MCF_DMA_DCR_BWC_32K (0x2) +#define MCF_DMA_DCR_BWC_64K (0x3) +#define MCF_DMA_DCR_BWC_128K (0x4) +#define MCF_DMA_DCR_BWC_256K (0x5) +#define MCF_DMA_DCR_BWC_512K (0x6) +#define MCF_DMA_DCR_BWC_1024K (0x7) +#define MCF_DMA_DCR_AA (0x10000000) +#define MCF_DMA_DCR_CS (0x20000000) +#define MCF_DMA_DCR_EEXT (0x40000000) +#define MCF_DMA_DCR_INT (0x80000000) + + +#endif /* __MCF52221_DMA_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DTIM.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DTIM.h new file mode 100644 index 000000000..0de7dd361 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DTIM.h @@ -0,0 +1,99 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_DTIM_H__ +#define __MCF52221_DTIM_H__ + + +/********************************************************************* +* +* DMA Timers (DTIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DTIM0_DTMR (*(vuint16*)(0x40000400)) +#define MCF_DTIM0_DTXMR (*(vuint8 *)(0x40000402)) +#define MCF_DTIM0_DTER (*(vuint8 *)(0x40000403)) +#define MCF_DTIM0_DTRR (*(vuint32*)(0x40000404)) +#define MCF_DTIM0_DTCR (*(vuint32*)(0x40000408)) +#define MCF_DTIM0_DTCN (*(vuint32*)(0x4000040C)) + +#define MCF_DTIM1_DTMR (*(vuint16*)(0x40000440)) +#define MCF_DTIM1_DTXMR (*(vuint8 *)(0x40000442)) +#define MCF_DTIM1_DTER (*(vuint8 *)(0x40000443)) +#define MCF_DTIM1_DTRR (*(vuint32*)(0x40000444)) +#define MCF_DTIM1_DTCR (*(vuint32*)(0x40000448)) +#define MCF_DTIM1_DTCN (*(vuint32*)(0x4000044C)) + +#define MCF_DTIM2_DTMR (*(vuint16*)(0x40000480)) +#define MCF_DTIM2_DTXMR (*(vuint8 *)(0x40000482)) +#define MCF_DTIM2_DTER (*(vuint8 *)(0x40000483)) +#define MCF_DTIM2_DTRR (*(vuint32*)(0x40000484)) +#define MCF_DTIM2_DTCR (*(vuint32*)(0x40000488)) +#define MCF_DTIM2_DTCN (*(vuint32*)(0x4000048C)) + +#define MCF_DTIM3_DTMR (*(vuint16*)(0x400004C0)) +#define MCF_DTIM3_DTXMR (*(vuint8 *)(0x400004C2)) +#define MCF_DTIM3_DTER (*(vuint8 *)(0x400004C3)) +#define MCF_DTIM3_DTRR (*(vuint32*)(0x400004C4)) +#define MCF_DTIM3_DTCR (*(vuint32*)(0x400004C8)) +#define MCF_DTIM3_DTCN (*(vuint32*)(0x400004CC)) + +#define MCF_DTIM_DTMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40))) +#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0x40000402 + ((x)*0x40))) +#define MCF_DTIM_DTER(x) (*(vuint8 *)(0x40000403 + ((x)*0x40))) +#define MCF_DTIM_DTRR(x) (*(vuint32*)(0x40000404 + ((x)*0x40))) +#define MCF_DTIM_DTCR(x) (*(vuint32*)(0x40000408 + ((x)*0x40))) +#define MCF_DTIM_DTCN(x) (*(vuint32*)(0x4000040C + ((x)*0x40))) + + +/* Bit definitions and macros for MCF_DTIM_DTMR */ +#define MCF_DTIM_DTMR_RST (0x1) +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1) +#define MCF_DTIM_DTMR_CLK_STOP (0) +#define MCF_DTIM_DTMR_CLK_DIV1 (0x2) +#define MCF_DTIM_DTMR_CLK_DIV16 (0x4) +#define MCF_DTIM_DTMR_CLK_DTIN (0x6) +#define MCF_DTIM_DTMR_FRR (0x8) +#define MCF_DTIM_DTMR_ORRI (0x10) +#define MCF_DTIM_DTMR_OM (0x20) +#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6) +#define MCF_DTIM_DTMR_CE_NONE (0) +#define MCF_DTIM_DTMR_CE_RISE (0x40) +#define MCF_DTIM_DTMR_CE_FALL (0x80) +#define MCF_DTIM_DTMR_CE_ANY (0xC0) +#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_DTIM_DTXMR */ +#define MCF_DTIM_DTXMR_MODE16 (0x1) +#define MCF_DTIM_DTXMR_HALTED (0x40) +#define MCF_DTIM_DTXMR_DMAEN (0x80) + +/* Bit definitions and macros for MCF_DTIM_DTER */ +#define MCF_DTIM_DTER_CAP (0x1) +#define MCF_DTIM_DTER_REF (0x2) + +/* Bit definitions and macros for MCF_DTIM_DTRR */ +#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCR */ +#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCN */ +#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF52221_DTIM_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_EPORT.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_EPORT.h new file mode 100644 index 000000000..030cd0c29 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_EPORT.h @@ -0,0 +1,123 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_EPORT_H__ +#define __MCF52221_EPORT_H__ + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(vuint16*)(0x40130000)) +#define MCF_EPORT_EPDDR (*(vuint8 *)(0x40130002)) +#define MCF_EPORT_EPIER (*(vuint8 *)(0x40130003)) +#define MCF_EPORT_EPDR (*(vuint8 *)(0x40130004)) +#define MCF_EPORT_EPPDR (*(vuint8 *)(0x40130005)) +#define MCF_EPORT_EPFR (*(vuint8 *)(0x40130006)) + + + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (0x1) +#define MCF_EPORT_EPPAR_FALLING (0x2) +#define MCF_EPORT_EPPAR_BOTH (0x3) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x2) +#define MCF_EPORT_EPDDR_EPDD2 (0x4) +#define MCF_EPORT_EPDDR_EPDD3 (0x8) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x2) +#define MCF_EPORT_EPIER_EPIE2 (0x4) +#define MCF_EPORT_EPIER_EPIE3 (0x8) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x2) +#define MCF_EPORT_EPDR_EPD2 (0x4) +#define MCF_EPORT_EPDR_EPD3 (0x8) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x2) +#define MCF_EPORT_EPPDR_EPPD2 (0x4) +#define MCF_EPORT_EPPDR_EPPD3 (0x8) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x2) +#define MCF_EPORT_EPFR_EPF2 (0x4) +#define MCF_EPORT_EPFR_EPF3 (0x8) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + + +#endif /* __MCF52221_EPORT_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPIO.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPIO.h new file mode 100644 index 000000000..e88e37a97 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPIO.h @@ -0,0 +1,475 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_GPIO_H__ +#define __MCF52221_GPIO_H__ + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PORTNQ (*(vuint8 *)(0x40100008)) +#define MCF_GPIO_DDRNQ (*(vuint8 *)(0x40100020)) +#define MCF_GPIO_SETNQ (*(vuint8 *)(0x40100038)) +#define MCF_GPIO_CLRNQ (*(vuint8 *)(0x40100050)) +#define MCF_GPIO_PNQPAR (*(vuint16*)(0x40100068)) + +#define MCF_GPIO_PORTAN (*(vuint8 *)(0x4010000A)) +#define MCF_GPIO_DDRAN (*(vuint8 *)(0x40100022)) +#define MCF_GPIO_SETAN (*(vuint8 *)(0x4010003A)) +#define MCF_GPIO_CLRAN (*(vuint8 *)(0x40100052)) +#define MCF_GPIO_PANPAR (*(vuint8 *)(0x4010006A)) + +#define MCF_GPIO_PORTAS (*(vuint8 *)(0x4010000B)) +#define MCF_GPIO_DDRAS (*(vuint8 *)(0x40100023)) +#define MCF_GPIO_SETAS (*(vuint8 *)(0x4010003B)) +#define MCF_GPIO_CLRAS (*(vuint8 *)(0x40100053)) +#define MCF_GPIO_PASPAR (*(vuint8 *)(0x4010006B)) + +#define MCF_GPIO_PORTQS (*(vuint8 *)(0x4010000C)) +#define MCF_GPIO_DDRQS (*(vuint8 *)(0x40100024)) +#define MCF_GPIO_SETQS (*(vuint8 *)(0x4010003C)) +#define MCF_GPIO_CLRQS (*(vuint8 *)(0x40100054)) +#define MCF_GPIO_PQSPAR (*(vuint16*)(0x4010006C)) + +#define MCF_GPIO_PORTTA (*(vuint8 *)(0x4010000E)) +#define MCF_GPIO_DDRTA (*(vuint8 *)(0x40100026)) +#define MCF_GPIO_SETTA (*(vuint8 *)(0x4010003E)) +#define MCF_GPIO_CLRTA (*(vuint8 *)(0x40100056)) +#define MCF_GPIO_PTAPAR (*(vuint8 *)(0x4010006E)) + +#define MCF_GPIO_PORTTC (*(vuint8 *)(0x4010000F)) +#define MCF_GPIO_DDRTC (*(vuint8 *)(0x40100027)) +#define MCF_GPIO_SETTC (*(vuint8 *)(0x4010003F)) +#define MCF_GPIO_CLRTC (*(vuint8 *)(0x40100057)) +#define MCF_GPIO_PTCPAR (*(vuint8 *)(0x4010006F)) + +#define MCF_GPIO_PORTUA (*(vuint8 *)(0x40100011)) +#define MCF_GPIO_DDRUA (*(vuint8 *)(0x40100029)) +#define MCF_GPIO_SETUA (*(vuint8 *)(0x40100041)) +#define MCF_GPIO_CLRUA (*(vuint8 *)(0x40100059)) +#define MCF_GPIO_PUAPAR (*(vuint8 *)(0x40100071)) + +#define MCF_GPIO_PORTUB (*(vuint8 *)(0x40100012)) +#define MCF_GPIO_DDRUB (*(vuint8 *)(0x4010002A)) +#define MCF_GPIO_SETUB (*(vuint8 *)(0x40100042)) +#define MCF_GPIO_CLRUB (*(vuint8 *)(0x4010005A)) +#define MCF_GPIO_PUBPAR (*(vuint8 *)(0x40100072)) + + + +/* Bit definitions and macros for MCF_GPIO_PORTNQ */ +#define MCF_GPIO_PORTNQ_PORTNQ1 (0x2) +#define MCF_GPIO_PORTNQ_PORTNQ2 (0x4) +#define MCF_GPIO_PORTNQ_PORTNQ3 (0x8) +#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10) +#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20) +#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40) +#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRNQ */ +#define MCF_GPIO_DDRNQ_DDRNQ1 (0x2) +#define MCF_GPIO_DDRNQ_DDRNQ2 (0x4) +#define MCF_GPIO_DDRNQ_DDRNQ3 (0x8) +#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10) +#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20) +#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40) +#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETNQ */ +#define MCF_GPIO_SETNQ_SETNQ1 (0x2) +#define MCF_GPIO_SETNQ_SETNQ2 (0x4) +#define MCF_GPIO_SETNQ_SETNQ3 (0x8) +#define MCF_GPIO_SETNQ_SETNQ4 (0x10) +#define MCF_GPIO_SETNQ_SETNQ5 (0x20) +#define MCF_GPIO_SETNQ_SETNQ6 (0x40) +#define MCF_GPIO_SETNQ_SETNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRNQ */ +#define MCF_GPIO_CLRNQ_CLRNQ1 (0x2) +#define MCF_GPIO_CLRNQ_CLRNQ2 (0x4) +#define MCF_GPIO_CLRNQ_CLRNQ3 (0x8) +#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10) +#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20) +#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40) +#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PNQPAR */ +#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x3)<<0x2) +#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0) +#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x4) +#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x8) +#define MCF_GPIO_PNQPAR_IRQ1_USB_ALT_CLK (0xC) +#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x3)<<0x4) +#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0) +#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x10) +#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x3)<<0x6) +#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0) +#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x40) +#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x3)<<0x8) +#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0) +#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x100) +#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x3)<<0xA) +#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0) +#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x400) +#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x3)<<0xC) +#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0) +#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000) +#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x3)<<0xE) +#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0) +#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000) + +/* Bit definitions and macros for MCF_GPIO_PORTAN */ +#define MCF_GPIO_PORTAN_PORTAN0 (0x1) +#define MCF_GPIO_PORTAN_PORTAN1 (0x2) +#define MCF_GPIO_PORTAN_PORTAN2 (0x4) +#define MCF_GPIO_PORTAN_PORTAN3 (0x8) +#define MCF_GPIO_PORTAN_PORTAN4 (0x10) +#define MCF_GPIO_PORTAN_PORTAN5 (0x20) +#define MCF_GPIO_PORTAN_PORTAN6 (0x40) +#define MCF_GPIO_PORTAN_PORTAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRAN */ +#define MCF_GPIO_DDRAN_DDRAN0 (0x1) +#define MCF_GPIO_DDRAN_DDRAN1 (0x2) +#define MCF_GPIO_DDRAN_DDRAN2 (0x4) +#define MCF_GPIO_DDRAN_DDRAN3 (0x8) +#define MCF_GPIO_DDRAN_DDRAN4 (0x10) +#define MCF_GPIO_DDRAN_DDRAN5 (0x20) +#define MCF_GPIO_DDRAN_DDRAN6 (0x40) +#define MCF_GPIO_DDRAN_DDRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETAN */ +#define MCF_GPIO_SETAN_SETAN0 (0x1) +#define MCF_GPIO_SETAN_SETAN1 (0x2) +#define MCF_GPIO_SETAN_SETAN2 (0x4) +#define MCF_GPIO_SETAN_SETAN3 (0x8) +#define MCF_GPIO_SETAN_SETAN4 (0x10) +#define MCF_GPIO_SETAN_SETAN5 (0x20) +#define MCF_GPIO_SETAN_SETAN6 (0x40) +#define MCF_GPIO_SETAN_SETAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRAN */ +#define MCF_GPIO_CLRAN_CLRAN0 (0x1) +#define MCF_GPIO_CLRAN_CLRAN1 (0x2) +#define MCF_GPIO_CLRAN_CLRAN2 (0x4) +#define MCF_GPIO_CLRAN_CLRAN3 (0x8) +#define MCF_GPIO_CLRAN_CLRAN4 (0x10) +#define MCF_GPIO_CLRAN_CLRAN5 (0x20) +#define MCF_GPIO_CLRAN_CLRAN6 (0x40) +#define MCF_GPIO_CLRAN_CLRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PANPAR */ +#define MCF_GPIO_PANPAR_PANPAR0 (0x1) +#define MCF_GPIO_PANPAR_AN0_GPIO (0) +#define MCF_GPIO_PANPAR_AN0_AN0 (0x1) +#define MCF_GPIO_PANPAR_PANPAR1 (0x2) +#define MCF_GPIO_PANPAR_AN1_GPIO (0) +#define MCF_GPIO_PANPAR_AN1_AN1 (0x2) +#define MCF_GPIO_PANPAR_PANPAR2 (0x4) +#define MCF_GPIO_PANPAR_AN2_GPIO (0) +#define MCF_GPIO_PANPAR_AN2_AN2 (0x4) +#define MCF_GPIO_PANPAR_PANPAR3 (0x8) +#define MCF_GPIO_PANPAR_AN3_GPIO (0) +#define MCF_GPIO_PANPAR_AN3_AN3 (0x8) +#define MCF_GPIO_PANPAR_PANPAR4 (0x10) +#define MCF_GPIO_PANPAR_AN4_GPIO (0) +#define MCF_GPIO_PANPAR_AN4_AN4 (0x10) +#define MCF_GPIO_PANPAR_PANPAR5 (0x20) +#define MCF_GPIO_PANPAR_AN5_GPIO (0) +#define MCF_GPIO_PANPAR_AN5_AN5 (0x20) +#define MCF_GPIO_PANPAR_PANPAR6 (0x40) +#define MCF_GPIO_PANPAR_AN6_GPIO (0) +#define MCF_GPIO_PANPAR_AN6_AN6 (0x40) +#define MCF_GPIO_PANPAR_PANPAR7 (0x80) +#define MCF_GPIO_PANPAR_AN7_GPIO (0) +#define MCF_GPIO_PANPAR_AN7_AN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTAS */ +#define MCF_GPIO_PORTAS_PORTAS0 (0x1) +#define MCF_GPIO_PORTAS_PORTAS1 (0x2) + +/* Bit definitions and macros for MCF_GPIO_DDRAS */ +#define MCF_GPIO_DDRAS_DDRAS0 (0x1) +#define MCF_GPIO_DDRAS_DDRAS1 (0x2) + +/* Bit definitions and macros for MCF_GPIO_SETAS */ +#define MCF_GPIO_SETAS_SETAS0 (0x1) +#define MCF_GPIO_SETAS_SETAS1 (0x2) + +/* Bit definitions and macros for MCF_GPIO_CLRAS */ +#define MCF_GPIO_CLRAS_CLRAS0 (0x1) +#define MCF_GPIO_CLRAS_CLRAS1 (0x2) + +/* Bit definitions and macros for MCF_GPIO_PASPAR */ +#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x3)<<0) +#define MCF_GPIO_PASPAR_SCL_GPIO (0) +#define MCF_GPIO_PASPAR_SCL_SCL (0x1) +#define MCF_GPIO_PASPAR_SCL_USB_DMI (0x2) +#define MCF_GPIO_PASPAR_SCL_UTXD2 (0x3) +#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x3)<<0x2) +#define MCF_GPIO_PASPAR_SDA_GPIO (0) +#define MCF_GPIO_PASPAR_SDA_SDA (0x4) +#define MCF_GPIO_PASPAR_SDA_USB_DPI (0x8) +#define MCF_GPIO_PASPAR_SDA_URXD2 (0xC) + +/* Bit definitions and macros for MCF_GPIO_PORTQS */ +#define MCF_GPIO_PORTQS_PORTQS0 (0x1) +#define MCF_GPIO_PORTQS_PORTQS1 (0x2) +#define MCF_GPIO_PORTQS_PORTQS2 (0x4) +#define MCF_GPIO_PORTQS_PORTQS3 (0x8) +#define MCF_GPIO_PORTQS_PORTQS4 (0x10) +#define MCF_GPIO_PORTQS_PORTQS5 (0x20) +#define MCF_GPIO_PORTQS_PORTQS6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_DDRQS */ +#define MCF_GPIO_DDRQS_DDRQS0 (0x1) +#define MCF_GPIO_DDRQS_DDRQS1 (0x2) +#define MCF_GPIO_DDRQS_DDRQS2 (0x4) +#define MCF_GPIO_DDRQS_DDRQS3 (0x8) +#define MCF_GPIO_DDRQS_DDRQS4 (0x10) +#define MCF_GPIO_DDRQS_DDRQS5 (0x20) +#define MCF_GPIO_DDRQS_DDRQS6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_SETQS */ +#define MCF_GPIO_SETQS_SETQS0 (0x1) +#define MCF_GPIO_SETQS_SETQS1 (0x2) +#define MCF_GPIO_SETQS_SETQS2 (0x4) +#define MCF_GPIO_SETQS_SETQS3 (0x8) +#define MCF_GPIO_SETQS_SETQS4 (0x10) +#define MCF_GPIO_SETQS_SETQS5 (0x20) +#define MCF_GPIO_SETQS_SETQS6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_CLRQS */ +#define MCF_GPIO_CLRQS_CLRQS0 (0x1) +#define MCF_GPIO_CLRQS_CLRQS1 (0x2) +#define MCF_GPIO_CLRQS_CLRQS2 (0x4) +#define MCF_GPIO_CLRQS_CLRQS3 (0x8) +#define MCF_GPIO_CLRQS_CLRQS4 (0x10) +#define MCF_GPIO_CLRQS_CLRQS5 (0x20) +#define MCF_GPIO_CLRQS_CLRQS6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PQSPAR */ +#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x3)<<0) +#define MCF_GPIO_PQSPAR_QSPI_DOUT_GPIO (0) +#define MCF_GPIO_PQSPAR_QSPI_DOUT_DOUT (0x1) +#define MCF_GPIO_PQSPAR_QSPI_DOUT_UTXD1 (0x3) +#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x3)<<0x2) +#define MCF_GPIO_PQSPAR_QSPI_DIN_GPIO (0) +#define MCF_GPIO_PQSPAR_QSPI_DIN_DIN (0x4) +#define MCF_GPIO_PQSPAR_QSPI_DIN_URXD1 (0xC) +#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x3)<<0x4) +#define MCF_GPIO_PQSPAR_QSPI_CLK_GPIO (0) +#define MCF_GPIO_PQSPAR_QSPI_CLK_CLK (0x10) +#define MCF_GPIO_PQSPAR_QSPI_CLK_SCL (0x20) +#define MCF_GPIO_PQSPAR_QSPI_CLK_URTS1 (0x30) +#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x3)<<0x6) +#define MCF_GPIO_PQSPAR_QSPI_CS0_GPIO (0) +#define MCF_GPIO_PQSPAR_QSPI_CS0_CS0 (0x40) +#define MCF_GPIO_PQSPAR_QSPI_CS0_UCTS1 (0xC0) +#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x3)<<0x8) +#define MCF_GPIO_PQSPAR_QSPI_CS1_GPIO (0) +#define MCF_GPIO_PQSPAR_QSPI_CS1_CS1 (0x100) +#define MCF_GPIO_PQSPAR_QSPI_CS1_USB_PULLUP (0x300) +#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x3)<<0xA) +#define MCF_GPIO_PQSPAR_QSPI_CS2_GPIO (0) +#define MCF_GPIO_PQSPAR_QSPI_CS2_CS2 (0x400) +#define MCF_GPIO_PQSPAR_QSPI_CS2_USB_DM_PD (0xC00) +#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x3)<<0xC) +#define MCF_GPIO_PQSPAR_QSPI_CS3_GPIO (0) +#define MCF_GPIO_PQSPAR_QSPI_CS3_CS3 (0x1000) +#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCA (0x2000) +#define MCF_GPIO_PQSPAR_QSPI_CS3_USB_DP_PD (0x3000) + +/* Bit definitions and macros for MCF_GPIO_PORTTA */ +#define MCF_GPIO_PORTTA_PORTTA0 (0x1) +#define MCF_GPIO_PORTTA_PORTTA1 (0x2) +#define MCF_GPIO_PORTTA_PORTTA2 (0x4) +#define MCF_GPIO_PORTTA_PORTTA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_DDRTA */ +#define MCF_GPIO_DDRTA_DDRTA0 (0x1) +#define MCF_GPIO_DDRTA_DDRTA1 (0x2) +#define MCF_GPIO_DDRTA_DDRTA2 (0x4) +#define MCF_GPIO_DDRTA_DDRTA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_SETTA */ +#define MCF_GPIO_SETTA_SETTA0 (0x1) +#define MCF_GPIO_SETTA_SETTA1 (0x2) +#define MCF_GPIO_SETTA_SETTA2 (0x4) +#define MCF_GPIO_SETTA_SETTA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_CLRTA */ +#define MCF_GPIO_CLRTA_CLRTA0 (0x1) +#define MCF_GPIO_CLRTA_CLRTA1 (0x2) +#define MCF_GPIO_CLRTA_CLRTA2 (0x4) +#define MCF_GPIO_CLRTA_CLRTA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PTAPAR */ +#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x3)<<0) +#define MCF_GPIO_PTAPAR_GPT0_GPIO (0) +#define MCF_GPIO_PTAPAR_GPT0_GPT0 (0x1) +#define MCF_GPIO_PTAPAR_GPT0_PWM1 (0x3) +#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x3)<<0x2) +#define MCF_GPIO_PTAPAR_GPT1_GPIO (0) +#define MCF_GPIO_PTAPAR_GPT1_GPT1 (0x4) +#define MCF_GPIO_PTAPAR_GPT1_PWM3 (0xC) +#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x3)<<0x4) +#define MCF_GPIO_PTAPAR_GPT2_GPIO (0) +#define MCF_GPIO_PTAPAR_GPT2_GPT2 (0x10) +#define MCF_GPIO_PTAPAR_GPT2_PWM5 (0x30) +#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x3)<<0x6) +#define MCF_GPIO_PTAPAR_GPT3_GPIO (0) +#define MCF_GPIO_PTAPAR_GPT3_GPT3 (0x40) +#define MCF_GPIO_PTAPAR_GPT3_PWM7 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PORTTC */ +#define MCF_GPIO_PORTTC_PORTTC0 (0x1) +#define MCF_GPIO_PORTTC_PORTTC1 (0x2) +#define MCF_GPIO_PORTTC_PORTTC2 (0x4) +#define MCF_GPIO_PORTTC_PORTTC3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_DDRTC */ +#define MCF_GPIO_DDRTC_DDRTC0 (0x1) +#define MCF_GPIO_DDRTC_DDRTC1 (0x2) +#define MCF_GPIO_DDRTC_DDRTC2 (0x4) +#define MCF_GPIO_DDRTC_DDRTC3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_SETTC */ +#define MCF_GPIO_SETTC_SETTC0 (0x1) +#define MCF_GPIO_SETTC_SETTC1 (0x2) +#define MCF_GPIO_SETTC_SETTC2 (0x4) +#define MCF_GPIO_SETTC_SETTC3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_CLRTC */ +#define MCF_GPIO_CLRTC_CLRTC0 (0x1) +#define MCF_GPIO_CLRTC_CLRTC1 (0x2) +#define MCF_GPIO_CLRTC_CLRTC2 (0x4) +#define MCF_GPIO_CLRTC_CLRTC3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PTCPAR */ +#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x3)<<0) +#define MCF_GPIO_PTCPAR_DTIN0_GPIO (0) +#define MCF_GPIO_PTCPAR_DTIN0_DTIN0 (0x1) +#define MCF_GPIO_PTCPAR_DTIN0_DTOUT0 (0x2) +#define MCF_GPIO_PTCPAR_DTIN0_PWM0 (0x3) +#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x3)<<0x2) +#define MCF_GPIO_PTCPAR_DTIN1_GPIO (0) +#define MCF_GPIO_PTCPAR_DTIN1_DTIN1 (0x4) +#define MCF_GPIO_PTCPAR_DTIN1_DTOUT1 (0x8) +#define MCF_GPIO_PTCPAR_DTIN1_PWM2 (0xC) +#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x3)<<0x4) +#define MCF_GPIO_PTCPAR_DTIN2_GPIO (0) +#define MCF_GPIO_PTCPAR_DTIN2_DTIN2 (0x10) +#define MCF_GPIO_PTCPAR_DTIN2_DTOUT2 (0x20) +#define MCF_GPIO_PTCPAR_DTIN2_PWM4 (0x30) +#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x3)<<0x6) +#define MCF_GPIO_PTCPAR_DTIN3_GPIO (0) +#define MCF_GPIO_PTCPAR_DTIN3_DTIN3 (0x40) +#define MCF_GPIO_PTCPAR_DTIN3_DTOUT3 (0x80) +#define MCF_GPIO_PTCPAR_DTIN3_PWM6 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PORTUA */ +#define MCF_GPIO_PORTUA_PORTUA0 (0x1) +#define MCF_GPIO_PORTUA_PORTUA1 (0x2) +#define MCF_GPIO_PORTUA_PORTUA2 (0x4) +#define MCF_GPIO_PORTUA_PORTUA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_DDRUA */ +#define MCF_GPIO_DDRUA_DDRUA0 (0x1) +#define MCF_GPIO_DDRUA_DDRUA1 (0x2) +#define MCF_GPIO_DDRUA_DDRUA2 (0x4) +#define MCF_GPIO_DDRUA_DDRUA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_SETUA */ +#define MCF_GPIO_SETUA_SETUA0 (0x1) +#define MCF_GPIO_SETUA_SETUA1 (0x2) +#define MCF_GPIO_SETUA_SETUA2 (0x4) +#define MCF_GPIO_SETUA_SETUA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_CLRUA */ +#define MCF_GPIO_CLRUA_CLRUA0 (0x1) +#define MCF_GPIO_CLRUA_CLRUA1 (0x2) +#define MCF_GPIO_CLRUA_CLRUA2 (0x4) +#define MCF_GPIO_CLRUA_CLRUA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PUAPAR */ +#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x3)<<0) +#define MCF_GPIO_PUAPAR_UTXD0_GPIO (0) +#define MCF_GPIO_PUAPAR_UTXD0_UTXD0 (0x1) +#define MCF_GPIO_PUAPAR_UTXD0_USB_SUSPEND (0x3) +#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x3)<<0x2) +#define MCF_GPIO_PUAPAR_URXD0_GPIO (0) +#define MCF_GPIO_PUAPAR_URXD0_URXD0 (0x4) +#define MCF_GPIO_PUAPAR_URXD0_USB_RCV (0xC) +#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x3)<<0x4) +#define MCF_GPIO_PUAPAR_URTS0_GPIO (0) +#define MCF_GPIO_PUAPAR_URTS0_URTS0 (0x10) +#define MCF_GPIO_PUAPAR_URTS0_USB_VBUSD (0x30) +#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x3)<<0x6) +#define MCF_GPIO_PUAPAR_UCTS0_GPIO (0) +#define MCF_GPIO_PUAPAR_UCTS0_UCTS0 (0x40) +#define MCF_GPIO_PUAPAR_UCTS0_USB_VBUSE (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PORTUB */ +#define MCF_GPIO_PORTUB_PORTUB0 (0x1) +#define MCF_GPIO_PORTUB_PORTUB1 (0x2) +#define MCF_GPIO_PORTUB_PORTUB2 (0x4) +#define MCF_GPIO_PORTUB_PORTUB3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_DDRUB */ +#define MCF_GPIO_DDRUB_DDRUB0 (0x1) +#define MCF_GPIO_DDRUB_DDRUB1 (0x2) +#define MCF_GPIO_DDRUB_DDRUB2 (0x4) +#define MCF_GPIO_DDRUB_DDRUB3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_SETUB */ +#define MCF_GPIO_SETUB_SETUB0 (0x1) +#define MCF_GPIO_SETUB_SETUB1 (0x2) +#define MCF_GPIO_SETUB_SETUB2 (0x4) +#define MCF_GPIO_SETUB_SETUB3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_CLRUB */ +#define MCF_GPIO_CLRUB_CLRUB0 (0x1) +#define MCF_GPIO_CLRUB_CLRUB1 (0x2) +#define MCF_GPIO_CLRUB_CLRUB2 (0x4) +#define MCF_GPIO_CLRUB_CLRUB3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PUBPAR */ +#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x3)<<0) +#define MCF_GPIO_PUBPAR_UTXD1_GPIO (0) +#define MCF_GPIO_PUBPAR_UTXD1_UTXD1 (0x1) +#define MCF_GPIO_PUBPAR_UTXD1_USB_SPEED (0x3) +#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x3)<<0x2) +#define MCF_GPIO_PUBPAR_URXD1_GPIO (0) +#define MCF_GPIO_PUBPAR_URXD1_URXD1 (0x4) +#define MCF_GPIO_PUBPAR_URXD1_USB_OE (0xC) +#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x3)<<0x4) +#define MCF_GPIO_PUBPAR_URTS1_GPIO (0) +#define MCF_GPIO_PUBPAR_URTS1_URTS1 (0x10) +#define MCF_GPIO_PUBPAR_URTS1_SYNCB (0x20) +#define MCF_GPIO_PUBPAR_URTS1_UTXD2 (0x30) +#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x3)<<0x6) +#define MCF_GPIO_PUBPAR_UCTS1_GPIO (0) +#define MCF_GPIO_PUBPAR_UCTS1_UCTS1 (0x40) +#define MCF_GPIO_PUBPAR_UCTS1_SYNCA (0x80) +#define MCF_GPIO_PUBPAR_UCTS1_URXD2 (0xC0) + + +#endif /* __MCF52221_GPIO_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPTA.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPTA.h new file mode 100644 index 000000000..376186156 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPTA.h @@ -0,0 +1,206 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_GPTA_H__ +#define __MCF52221_GPTA_H__ + + +/********************************************************************* +* +* General Purpose Timer Module (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPTA_GPTIOS (*(vuint8 *)(0x401A0000)) +#define MCF_GPTA_GPTCFORC (*(vuint8 *)(0x401A0001)) +#define MCF_GPTA_GPTOC3M (*(vuint8 *)(0x401A0002)) +#define MCF_GPTA_GPTOC3D (*(vuint8 *)(0x401A0003)) +#define MCF_GPTA_GPTCNT (*(vuint16*)(0x401A0004)) +#define MCF_GPTA_GPTSCR1 (*(vuint8 *)(0x401A0006)) +#define MCF_GPTA_GPTTOV (*(vuint8 *)(0x401A0008)) +#define MCF_GPTA_GPTCTL1 (*(vuint8 *)(0x401A0009)) +#define MCF_GPTA_GPTCTL2 (*(vuint8 *)(0x401A000B)) +#define MCF_GPTA_GPTIE (*(vuint8 *)(0x401A000C)) +#define MCF_GPTA_GPTSCR2 (*(vuint8 *)(0x401A000D)) +#define MCF_GPTA_GPTFLG1 (*(vuint8 *)(0x401A000E)) +#define MCF_GPTA_GPTFLG2 (*(vuint8 *)(0x401A000F)) +#define MCF_GPTA_GPTC0 (*(vuint16*)(0x401A0010)) +#define MCF_GPTA_GPTC1 (*(vuint16*)(0x401A0012)) +#define MCF_GPTA_GPTC2 (*(vuint16*)(0x401A0014)) +#define MCF_GPTA_GPTC3 (*(vuint16*)(0x401A0016)) +#define MCF_GPTA_GPTPACTL (*(vuint8 *)(0x401A0018)) +#define MCF_GPTA_GPTPAFLG (*(vuint8 *)(0x401A0019)) +#define MCF_GPTA_GPTPACNT (*(vuint16*)(0x401A001A)) +#define MCF_GPTA_GPTPORT (*(vuint8 *)(0x401A001D)) +#define MCF_GPTA_GPTDDR (*(vuint8 *)(0x401A001E)) +#define MCF_GPTA_GPTC(x) (*(vuint16*)(0x401A0010 + ((x)*0x2))) + + +/* Bit definitions and macros for MCF_GPTA_GPTIOS */ +#define MCF_GPTA_GPTIOS_IOS0 (0x1) +#define MCF_GPTA_GPTIOS_IOS1 (0x2) +#define MCF_GPTA_GPTIOS_IOS2 (0x4) +#define MCF_GPTA_GPTIOS_IOS3 (0x8) + +/* Bit definitions and macros for MCF_GPTA_GPTCFORC */ +#define MCF_GPTA_GPTCFORC_FOC0 (0x1) +#define MCF_GPTA_GPTCFORC_FOC1 (0x2) +#define MCF_GPTA_GPTCFORC_FOC2 (0x4) +#define MCF_GPTA_GPTCFORC_FOC3 (0x8) + +/* Bit definitions and macros for MCF_GPTA_GPTOC3M */ +#define MCF_GPTA_GPTOC3M_OC3M0 (0x1) +#define MCF_GPTA_GPTOC3M_OC3M1 (0x2) +#define MCF_GPTA_GPTOC3M_OC3M2 (0x4) +#define MCF_GPTA_GPTOC3M_OC3M3 (0x8) + +/* Bit definitions and macros for MCF_GPTA_GPTOC3D */ +#define MCF_GPTA_GPTOC3D_OC3D0 (0x1) +#define MCF_GPTA_GPTOC3D_OC3D1 (0x2) +#define MCF_GPTA_GPTOC3D_OC3D2 (0x4) +#define MCF_GPTA_GPTOC3D_OC3D3 (0x8) + +/* Bit definitions and macros for MCF_GPTA_GPTCNT */ +#define MCF_GPTA_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPTA_GPTSCR1 */ +#define MCF_GPTA_GPTSCR1_TFFCA (0x10) +#define MCF_GPTA_GPTSCR1_GPTEN (0x80) + +/* Bit definitions and macros for MCF_GPTA_GPTTOV */ +#define MCF_GPTA_GPTTOV_TOV0 (0x1) +#define MCF_GPTA_GPTTOV_TOV1 (0x2) +#define MCF_GPTA_GPTTOV_TOV2 (0x4) +#define MCF_GPTA_GPTTOV_TOV3 (0x8) + +/* Bit definitions and macros for MCF_GPTA_GPTCTL1 */ +#define MCF_GPTA_GPTCTL1_OL0 (0x1) +#define MCF_GPTA_GPTCTL1_OM0 (0x2) +#define MCF_GPTA_GPTCTL1_OL1 (0x4) +#define MCF_GPTA_GPTCTL1_OM1 (0x8) +#define MCF_GPTA_GPTCTL1_OL2 (0x10) +#define MCF_GPTA_GPTCTL1_OM2 (0x20) +#define MCF_GPTA_GPTCTL1_OL3 (0x40) +#define MCF_GPTA_GPTCTL1_OM3 (0x80) +#define MCF_GPTA_GPTCTL1_OUTPUT0_NOTHING (0) +#define MCF_GPTA_GPTCTL1_OUTPUT0_TOGGLE (0x1) +#define MCF_GPTA_GPTCTL1_OUTPUT0_CLEAR (0x2) +#define MCF_GPTA_GPTCTL1_OUTPUT0_SET (0x3) +#define MCF_GPTA_GPTCTL1_OUTPUT1_NOTHING (0) +#define MCF_GPTA_GPTCTL1_OUTPUT1_TOGGLE (0x4) +#define MCF_GPTA_GPTCTL1_OUTPUT1_CLEAR (0x8) +#define MCF_GPTA_GPTCTL1_OUTPUT1_SET (0xC) +#define MCF_GPTA_GPTCTL1_OUTPUT2_NOTHING (0) +#define MCF_GPTA_GPTCTL1_OUTPUT2_TOGGLE (0x10) +#define MCF_GPTA_GPTCTL1_OUTPUT2_CLEAR (0x20) +#define MCF_GPTA_GPTCTL1_OUTPUT2_SET (0x30) +#define MCF_GPTA_GPTCTL1_OUTPUT3_NOTHING (0) +#define MCF_GPTA_GPTCTL1_OUTPUT3_TOGGLE (0x40) +#define MCF_GPTA_GPTCTL1_OUTPUT3_CLEAR (0x80) +#define MCF_GPTA_GPTCTL1_OUTPUT3_SET (0xC0) + +/* Bit definitions and macros for MCF_GPTA_GPTCTL2 */ +#define MCF_GPTA_GPTCTL2_EDG0A (0x1) +#define MCF_GPTA_GPTCTL2_EDG0B (0x2) +#define MCF_GPTA_GPTCTL2_EDG1A (0x4) +#define MCF_GPTA_GPTCTL2_EDG1B (0x8) +#define MCF_GPTA_GPTCTL2_EDG2A (0x10) +#define MCF_GPTA_GPTCTL2_EDG2B (0x20) +#define MCF_GPTA_GPTCTL2_EDG3A (0x40) +#define MCF_GPTA_GPTCTL2_EDG3B (0x80) +#define MCF_GPTA_GPTCTL2_INPUT0_DISABLED (0) +#define MCF_GPTA_GPTCTL2_INPUT0_RISING (0x1) +#define MCF_GPTA_GPTCTL2_INPUT0_FALLING (0x2) +#define MCF_GPTA_GPTCTL2_INPUT0_ANY (0x3) +#define MCF_GPTA_GPTCTL2_INPUT1_DISABLED (0) +#define MCF_GPTA_GPTCTL2_INPUT1_RISING (0x4) +#define MCF_GPTA_GPTCTL2_INPUT1_FALLING (0x8) +#define MCF_GPTA_GPTCTL2_INPUT1_ANY (0xC) +#define MCF_GPTA_GPTCTL2_INPUT2_DISABLED (0) +#define MCF_GPTA_GPTCTL2_INPUT2_RISING (0x10) +#define MCF_GPTA_GPTCTL2_INPUT2_FALLING (0x20) +#define MCF_GPTA_GPTCTL2_INPUT2_ANY (0x30) +#define MCF_GPTA_GPTCTL2_INPUT3_DISABLED (0) +#define MCF_GPTA_GPTCTL2_INPUT3_RISING (0x40) +#define MCF_GPTA_GPTCTL2_INPUT3_FALLING (0x80) +#define MCF_GPTA_GPTCTL2_INPUT3_ANY (0xC0) + +/* Bit definitions and macros for MCF_GPTA_GPTIE */ +#define MCF_GPTA_GPTIE_CI0 (0x1) +#define MCF_GPTA_GPTIE_CI1 (0x2) +#define MCF_GPTA_GPTIE_CI2 (0x4) +#define MCF_GPTA_GPTIE_CI3 (0x8) + +/* Bit definitions and macros for MCF_GPTA_GPTSCR2 */ +#define MCF_GPTA_GPTSCR2_PR(x) (((x)&0x7)<<0) +#define MCF_GPTA_GPTSCR2_PR_1 (0) +#define MCF_GPTA_GPTSCR2_PR_2 (0x1) +#define MCF_GPTA_GPTSCR2_PR_4 (0x2) +#define MCF_GPTA_GPTSCR2_PR_8 (0x3) +#define MCF_GPTA_GPTSCR2_PR_16 (0x4) +#define MCF_GPTA_GPTSCR2_PR_32 (0x5) +#define MCF_GPTA_GPTSCR2_PR_64 (0x6) +#define MCF_GPTA_GPTSCR2_PR_128 (0x7) +#define MCF_GPTA_GPTSCR2_TCRE (0x8) +#define MCF_GPTA_GPTSCR2_RDPT (0x10) +#define MCF_GPTA_GPTSCR2_PUPT (0x20) +#define MCF_GPTA_GPTSCR2_TOI (0x80) + +/* Bit definitions and macros for MCF_GPTA_GPTFLG1 */ +#define MCF_GPTA_GPTFLG1_CF0 (0x1) +#define MCF_GPTA_GPTFLG1_CF1 (0x2) +#define MCF_GPTA_GPTFLG1_CF2 (0x4) +#define MCF_GPTA_GPTFLG1_CF3 (0x8) + +/* Bit definitions and macros for MCF_GPTA_GPTFLG2 */ +#define MCF_GPTA_GPTFLG2_TOF (0x80) + +/* Bit definitions and macros for MCF_GPTA_GPTC */ +#define MCF_GPTA_GPTC_CCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPTA_GPTPACTL */ +#define MCF_GPTA_GPTPACTL_PAI (0x1) +#define MCF_GPTA_GPTPACTL_PAOVI (0x2) +#define MCF_GPTA_GPTPACTL_CLK(x) (((x)&0x3)<<0x2) +#define MCF_GPTA_GPTPACTL_CLK_GPTPR (0) +#define MCF_GPTA_GPTPACTL_CLK_PACLK (0x1) +#define MCF_GPTA_GPTPACTL_CLK_PACLK_256 (0x2) +#define MCF_GPTA_GPTPACTL_CLK_PACLK_65536 (0x3) +#define MCF_GPTA_GPTPACTL_PEDGE (0x10) +#define MCF_GPTA_GPTPACTL_PAMOD (0x20) +#define MCF_GPTA_GPTPACTL_PAE (0x40) + +/* Bit definitions and macros for MCF_GPTA_GPTPAFLG */ +#define MCF_GPTA_GPTPAFLG_PAIF (0x1) +#define MCF_GPTA_GPTPAFLG_PAOVF (0x2) + +/* Bit definitions and macros for MCF_GPTA_GPTPACNT */ +#define MCF_GPTA_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPTA_GPTPORT */ +#define MCF_GPTA_GPTPORT_PORTT0 (0x1) +#define MCF_GPTA_GPTPORT_PORTT1 (0x2) +#define MCF_GPTA_GPTPORT_PORTT2 (0x4) +#define MCF_GPTA_GPTPORT_PORTT3 (0x8) + +/* Bit definitions and macros for MCF_GPTA_GPTDDR */ +#define MCF_GPTA_GPTDDR_DDRT0 (0x1) +#define MCF_GPTA_GPTDDR_DDRT1 (0x2) +#define MCF_GPTA_GPTDDR_DDRT2 (0x4) +#define MCF_GPTA_GPTDDR_DDRT3 (0x8) + + +#endif /* __MCF52221_GPTA_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_I2C.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_I2C.h new file mode 100644 index 000000000..064c413e9 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_I2C.h @@ -0,0 +1,62 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_I2C_H__ +#define __MCF52221_I2C_H__ + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2ADR (*(vuint8 *)(0x40000300)) +#define MCF_I2C_I2FDR (*(vuint8 *)(0x40000304)) +#define MCF_I2C_I2CR (*(vuint8 *)(0x40000308)) +#define MCF_I2C_I2SR (*(vuint8 *)(0x4000030C)) +#define MCF_I2C_I2DR (*(vuint8 *)(0x40000310)) + + + +/* Bit definitions and macros for MCF_I2C_I2ADR */ +#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x4) +#define MCF_I2C_I2CR_TXAK (0x8) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x1) +#define MCF_I2C_I2SR_IIF (0x2) +#define MCF_I2C_I2SR_SRW (0x4) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + + +#endif /* __MCF52221_I2C_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_INTC.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_INTC.h new file mode 100644 index 000000000..d03a30b39 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_INTC.h @@ -0,0 +1,331 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_INTC_H__ +#define __MCF52221_INTC_H__ + + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC0_IPRH (*(vuint32*)(0x40000C00)) +#define MCF_INTC0_IPRL (*(vuint32*)(0x40000C04)) +#define MCF_INTC0_IMRH (*(vuint32*)(0x40000C08)) +#define MCF_INTC0_IMRL (*(vuint32*)(0x40000C0C)) +#define MCF_INTC0_INTFRCH (*(vuint32*)(0x40000C10)) +#define MCF_INTC0_INTFRCL (*(vuint32*)(0x40000C14)) +#define MCF_INTC0_IRLR (*(vuint8 *)(0x40000C18)) +#define MCF_INTC0_IACKLPR (*(vuint8 *)(0x40000C19)) +#define MCF_INTC0_ICR01 (*(vuint8 *)(0x40000C41)) +#define MCF_INTC0_ICR02 (*(vuint8 *)(0x40000C42)) +#define MCF_INTC0_ICR03 (*(vuint8 *)(0x40000C43)) +#define MCF_INTC0_ICR04 (*(vuint8 *)(0x40000C44)) +#define MCF_INTC0_ICR05 (*(vuint8 *)(0x40000C45)) +#define MCF_INTC0_ICR06 (*(vuint8 *)(0x40000C46)) +#define MCF_INTC0_ICR07 (*(vuint8 *)(0x40000C47)) +#define MCF_INTC0_ICR08 (*(vuint8 *)(0x40000C48)) +#define MCF_INTC0_ICR09 (*(vuint8 *)(0x40000C49)) +#define MCF_INTC0_ICR10 (*(vuint8 *)(0x40000C4A)) +#define MCF_INTC0_ICR11 (*(vuint8 *)(0x40000C4B)) +#define MCF_INTC0_ICR12 (*(vuint8 *)(0x40000C4C)) +#define MCF_INTC0_ICR13 (*(vuint8 *)(0x40000C4D)) +#define MCF_INTC0_ICR14 (*(vuint8 *)(0x40000C4E)) +#define MCF_INTC0_ICR15 (*(vuint8 *)(0x40000C4F)) +#define MCF_INTC0_ICR16 (*(vuint8 *)(0x40000C50)) +#define MCF_INTC0_ICR17 (*(vuint8 *)(0x40000C51)) +#define MCF_INTC0_ICR18 (*(vuint8 *)(0x40000C52)) +#define MCF_INTC0_ICR19 (*(vuint8 *)(0x40000C53)) +#define MCF_INTC0_ICR20 (*(vuint8 *)(0x40000C54)) +#define MCF_INTC0_ICR21 (*(vuint8 *)(0x40000C55)) +#define MCF_INTC0_ICR22 (*(vuint8 *)(0x40000C56)) +#define MCF_INTC0_ICR23 (*(vuint8 *)(0x40000C57)) +#define MCF_INTC0_ICR24 (*(vuint8 *)(0x40000C58)) +#define MCF_INTC0_ICR25 (*(vuint8 *)(0x40000C59)) +#define MCF_INTC0_ICR26 (*(vuint8 *)(0x40000C5A)) +#define MCF_INTC0_ICR27 (*(vuint8 *)(0x40000C5B)) +#define MCF_INTC0_ICR28 (*(vuint8 *)(0x40000C5C)) +#define MCF_INTC0_ICR29 (*(vuint8 *)(0x40000C5D)) +#define MCF_INTC0_ICR30 (*(vuint8 *)(0x40000C5E)) +#define MCF_INTC0_ICR31 (*(vuint8 *)(0x40000C5F)) +#define MCF_INTC0_ICR32 (*(vuint8 *)(0x40000C60)) +#define MCF_INTC0_ICR33 (*(vuint8 *)(0x40000C61)) +#define MCF_INTC0_ICR34 (*(vuint8 *)(0x40000C62)) +#define MCF_INTC0_ICR35 (*(vuint8 *)(0x40000C63)) +#define MCF_INTC0_ICR36 (*(vuint8 *)(0x40000C64)) +#define MCF_INTC0_ICR37 (*(vuint8 *)(0x40000C65)) +#define MCF_INTC0_ICR38 (*(vuint8 *)(0x40000C66)) +#define MCF_INTC0_ICR39 (*(vuint8 *)(0x40000C67)) +#define MCF_INTC0_ICR40 (*(vuint8 *)(0x40000C68)) +#define MCF_INTC0_ICR41 (*(vuint8 *)(0x40000C69)) +#define MCF_INTC0_ICR42 (*(vuint8 *)(0x40000C6A)) +#define MCF_INTC0_ICR43 (*(vuint8 *)(0x40000C6B)) +#define MCF_INTC0_ICR44 (*(vuint8 *)(0x40000C6C)) +#define MCF_INTC0_ICR45 (*(vuint8 *)(0x40000C6D)) +#define MCF_INTC0_ICR46 (*(vuint8 *)(0x40000C6E)) +#define MCF_INTC0_ICR47 (*(vuint8 *)(0x40000C6F)) +#define MCF_INTC0_ICR48 (*(vuint8 *)(0x40000C70)) +#define MCF_INTC0_ICR49 (*(vuint8 *)(0x40000C71)) +#define MCF_INTC0_ICR50 (*(vuint8 *)(0x40000C72)) +#define MCF_INTC0_ICR51 (*(vuint8 *)(0x40000C73)) +#define MCF_INTC0_ICR52 (*(vuint8 *)(0x40000C74)) +#define MCF_INTC0_ICR53 (*(vuint8 *)(0x40000C75)) +#define MCF_INTC0_ICR54 (*(vuint8 *)(0x40000C76)) +#define MCF_INTC0_ICR55 (*(vuint8 *)(0x40000C77)) +#define MCF_INTC0_ICR56 (*(vuint8 *)(0x40000C78)) +#define MCF_INTC0_ICR57 (*(vuint8 *)(0x40000C79)) +#define MCF_INTC0_ICR58 (*(vuint8 *)(0x40000C7A)) +#define MCF_INTC0_ICR59 (*(vuint8 *)(0x40000C7B)) +#define MCF_INTC0_ICR60 (*(vuint8 *)(0x40000C7C)) +#define MCF_INTC0_ICR61 (*(vuint8 *)(0x40000C7D)) +#define MCF_INTC0_ICR62 (*(vuint8 *)(0x40000C7E)) +#define MCF_INTC0_ICR63 (*(vuint8 *)(0x40000C7F)) +#define MCF_INTC0_SWIACK (*(vuint8 *)(0x40000CE0)) +#define MCF_INTC0_L1IACK (*(vuint8 *)(0x40000CE4)) +#define MCF_INTC0_L2IACK (*(vuint8 *)(0x40000CE8)) +#define MCF_INTC0_L3IACK (*(vuint8 *)(0x40000CEC)) +#define MCF_INTC0_L4IACK (*(vuint8 *)(0x40000CF0)) +#define MCF_INTC0_L5IACK (*(vuint8 *)(0x40000CF4)) +#define MCF_INTC0_L6IACK (*(vuint8 *)(0x40000CF8)) +#define MCF_INTC0_L7IACK (*(vuint8 *)(0x40000CFC)) +#define MCF_INTC0_ICR(x) (*(vuint8 *)(0x40000C41 + ((x-1)*0x1))) +#define MCF_INTC0_LIACK(x) (*(vuint8 *)(0x40000CE4 + ((x-1)*0x4))) + + + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x1) +#define MCF_INTC_IPRH_INT33 (0x2) +#define MCF_INTC_IPRH_INT34 (0x4) +#define MCF_INTC_IPRH_INT35 (0x8) +#define MCF_INTC_IPRH_INT36 (0x10) +#define MCF_INTC_IPRH_INT37 (0x20) +#define MCF_INTC_IPRH_INT38 (0x40) +#define MCF_INTC_IPRH_INT39 (0x80) +#define MCF_INTC_IPRH_INT40 (0x100) +#define MCF_INTC_IPRH_INT41 (0x200) +#define MCF_INTC_IPRH_INT42 (0x400) +#define MCF_INTC_IPRH_INT43 (0x800) +#define MCF_INTC_IPRH_INT44 (0x1000) +#define MCF_INTC_IPRH_INT45 (0x2000) +#define MCF_INTC_IPRH_INT46 (0x4000) +#define MCF_INTC_IPRH_INT47 (0x8000) +#define MCF_INTC_IPRH_INT48 (0x10000) +#define MCF_INTC_IPRH_INT49 (0x20000) +#define MCF_INTC_IPRH_INT50 (0x40000) +#define MCF_INTC_IPRH_INT51 (0x80000) +#define MCF_INTC_IPRH_INT52 (0x100000) +#define MCF_INTC_IPRH_INT53 (0x200000) +#define MCF_INTC_IPRH_INT54 (0x400000) +#define MCF_INTC_IPRH_INT55 (0x800000) +#define MCF_INTC_IPRH_INT56 (0x1000000) +#define MCF_INTC_IPRH_INT57 (0x2000000) +#define MCF_INTC_IPRH_INT58 (0x4000000) +#define MCF_INTC_IPRH_INT59 (0x8000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x2) +#define MCF_INTC_IPRL_INT2 (0x4) +#define MCF_INTC_IPRL_INT3 (0x8) +#define MCF_INTC_IPRL_INT4 (0x10) +#define MCF_INTC_IPRL_INT5 (0x20) +#define MCF_INTC_IPRL_INT6 (0x40) +#define MCF_INTC_IPRL_INT7 (0x80) +#define MCF_INTC_IPRL_INT8 (0x100) +#define MCF_INTC_IPRL_INT9 (0x200) +#define MCF_INTC_IPRL_INT10 (0x400) +#define MCF_INTC_IPRL_INT11 (0x800) +#define MCF_INTC_IPRL_INT12 (0x1000) +#define MCF_INTC_IPRL_INT13 (0x2000) +#define MCF_INTC_IPRL_INT14 (0x4000) +#define MCF_INTC_IPRL_INT15 (0x8000) +#define MCF_INTC_IPRL_INT16 (0x10000) +#define MCF_INTC_IPRL_INT17 (0x20000) +#define MCF_INTC_IPRL_INT18 (0x40000) +#define MCF_INTC_IPRL_INT19 (0x80000) +#define MCF_INTC_IPRL_INT20 (0x100000) +#define MCF_INTC_IPRL_INT21 (0x200000) +#define MCF_INTC_IPRL_INT22 (0x400000) +#define MCF_INTC_IPRL_INT23 (0x800000) +#define MCF_INTC_IPRL_INT24 (0x1000000) +#define MCF_INTC_IPRL_INT25 (0x2000000) +#define MCF_INTC_IPRL_INT26 (0x4000000) +#define MCF_INTC_IPRL_INT27 (0x8000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x1) +#define MCF_INTC_IMRH_INT_MASK33 (0x2) +#define MCF_INTC_IMRH_INT_MASK34 (0x4) +#define MCF_INTC_IMRH_INT_MASK35 (0x8) +#define MCF_INTC_IMRH_INT_MASK36 (0x10) +#define MCF_INTC_IMRH_INT_MASK37 (0x20) +#define MCF_INTC_IMRH_INT_MASK38 (0x40) +#define MCF_INTC_IMRH_INT_MASK39 (0x80) +#define MCF_INTC_IMRH_INT_MASK40 (0x100) +#define MCF_INTC_IMRH_INT_MASK41 (0x200) +#define MCF_INTC_IMRH_INT_MASK42 (0x400) +#define MCF_INTC_IMRH_INT_MASK43 (0x800) +#define MCF_INTC_IMRH_INT_MASK44 (0x1000) +#define MCF_INTC_IMRH_INT_MASK45 (0x2000) +#define MCF_INTC_IMRH_INT_MASK46 (0x4000) +#define MCF_INTC_IMRH_INT_MASK47 (0x8000) +#define MCF_INTC_IMRH_INT_MASK48 (0x10000) +#define MCF_INTC_IMRH_INT_MASK49 (0x20000) +#define MCF_INTC_IMRH_INT_MASK50 (0x40000) +#define MCF_INTC_IMRH_INT_MASK51 (0x80000) +#define MCF_INTC_IMRH_INT_MASK52 (0x100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x1000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x2000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x4000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x8000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x1) +#define MCF_INTC_IMRL_INT_MASK1 (0x2) +#define MCF_INTC_IMRL_INT_MASK2 (0x4) +#define MCF_INTC_IMRL_INT_MASK3 (0x8) +#define MCF_INTC_IMRL_INT_MASK4 (0x10) +#define MCF_INTC_IMRL_INT_MASK5 (0x20) +#define MCF_INTC_IMRL_INT_MASK6 (0x40) +#define MCF_INTC_IMRL_INT_MASK7 (0x80) +#define MCF_INTC_IMRL_INT_MASK8 (0x100) +#define MCF_INTC_IMRL_INT_MASK9 (0x200) +#define MCF_INTC_IMRL_INT_MASK10 (0x400) +#define MCF_INTC_IMRL_INT_MASK11 (0x800) +#define MCF_INTC_IMRL_INT_MASK12 (0x1000) +#define MCF_INTC_IMRL_INT_MASK13 (0x2000) +#define MCF_INTC_IMRL_INT_MASK14 (0x4000) +#define MCF_INTC_IMRL_INT_MASK15 (0x8000) +#define MCF_INTC_IMRL_INT_MASK16 (0x10000) +#define MCF_INTC_IMRL_INT_MASK17 (0x20000) +#define MCF_INTC_IMRL_INT_MASK18 (0x40000) +#define MCF_INTC_IMRL_INT_MASK19 (0x80000) +#define MCF_INTC_IMRL_INT_MASK20 (0x100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x1000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x2000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x4000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x8000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x1) +#define MCF_INTC_INTFRCH_INTFRC33 (0x2) +#define MCF_INTC_INTFRCH_INTFRC34 (0x4) +#define MCF_INTC_INTFRCH_INTFRC35 (0x8) +#define MCF_INTC_INTFRCH_INTFRC36 (0x10) +#define MCF_INTC_INTFRCH_INTFRC37 (0x20) +#define MCF_INTC_INTFRCH_INTFRC38 (0x40) +#define MCF_INTC_INTFRCH_INTFRC39 (0x80) +#define MCF_INTC_INTFRCH_INTFRC40 (0x100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x1000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x2000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x4000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x8000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x10000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x20000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x40000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x80000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x2) +#define MCF_INTC_INTFRCL_INTFRC2 (0x4) +#define MCF_INTC_INTFRCL_INTFRC3 (0x8) +#define MCF_INTC_INTFRCL_INTFRC4 (0x10) +#define MCF_INTC_INTFRCL_INTFRC5 (0x20) +#define MCF_INTC_INTFRCL_INTFRC6 (0x40) +#define MCF_INTC_INTFRCL_INTFRC7 (0x80) +#define MCF_INTC_INTFRCL_INTFRC8 (0x100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x1000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x2000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x4000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x8000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x10000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x20000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x40000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x80000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + + +#endif /* __MCF52221_INTC_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PAD.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PAD.h new file mode 100644 index 000000000..21c1e92c4 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PAD.h @@ -0,0 +1,92 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_PAD_H__ +#define __MCF52221_PAD_H__ + + +/********************************************************************* +* +* Common GPIO +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PAD_PSRR (*(vuint32*)(0x40100078)) +#define MCF_PAD_PDSR (*(vuint32*)(0x4010007C)) + + +/* Bit definitions and macros for MCF_PAD_PSRR */ +#define MCF_PAD_PSRR_PSRR0 (0x1) +#define MCF_PAD_PSRR_PSRR1 (0x2) +#define MCF_PAD_PSRR_PSRR2 (0x4) +#define MCF_PAD_PSRR_PSRR3 (0x8) +#define MCF_PAD_PSRR_PSRR4 (0x10) +#define MCF_PAD_PSRR_PSRR5 (0x20) +#define MCF_PAD_PSRR_PSRR6 (0x40) +#define MCF_PAD_PSRR_PSRR7 (0x80) +#define MCF_PAD_PSRR_PSRR8 (0x100) +#define MCF_PAD_PSRR_PSRR9 (0x200) +#define MCF_PAD_PSRR_PSRR10 (0x400) +#define MCF_PAD_PSRR_PSRR11 (0x800) +#define MCF_PAD_PSRR_PSRR12 (0x1000) +#define MCF_PAD_PSRR_PSRR13 (0x2000) +#define MCF_PAD_PSRR_PSRR14 (0x4000) +#define MCF_PAD_PSRR_PSRR15 (0x8000) +#define MCF_PAD_PSRR_PSRR16 (0x10000) +#define MCF_PAD_PSRR_PSRR17 (0x20000) +#define MCF_PAD_PSRR_PSRR18 (0x40000) +#define MCF_PAD_PSRR_PSRR19 (0x80000) +#define MCF_PAD_PSRR_PSRR20 (0x100000) +#define MCF_PAD_PSRR_PSRR21 (0x200000) +#define MCF_PAD_PSRR_PSRR22 (0x400000) +#define MCF_PAD_PSRR_PSRR23 (0x800000) +#define MCF_PAD_PSRR_PSRR24 (0x1000000) +#define MCF_PAD_PSRR_PSRR25 (0x2000000) +#define MCF_PAD_PSRR_PSRR26 (0x4000000) +#define MCF_PAD_PSRR_PSRR27 (0x8000000) + +/* Bit definitions and macros for MCF_PAD_PDSR */ +#define MCF_PAD_PDSR_PDSR0 (0x1) +#define MCF_PAD_PDSR_PDSR1 (0x2) +#define MCF_PAD_PDSR_PDSR2 (0x4) +#define MCF_PAD_PDSR_PDSR3 (0x8) +#define MCF_PAD_PDSR_PDSR4 (0x10) +#define MCF_PAD_PDSR_PDSR5 (0x20) +#define MCF_PAD_PDSR_PDSR6 (0x40) +#define MCF_PAD_PDSR_PDSR7 (0x80) +#define MCF_PAD_PDSR_PDSR8 (0x100) +#define MCF_PAD_PDSR_PDSR9 (0x200) +#define MCF_PAD_PDSR_PDSR10 (0x400) +#define MCF_PAD_PDSR_PDSR11 (0x800) +#define MCF_PAD_PDSR_PDSR12 (0x1000) +#define MCF_PAD_PDSR_PDSR13 (0x2000) +#define MCF_PAD_PDSR_PDSR14 (0x4000) +#define MCF_PAD_PDSR_PDSR15 (0x8000) +#define MCF_PAD_PDSR_PDSR16 (0x10000) +#define MCF_PAD_PDSR_PDSR17 (0x20000) +#define MCF_PAD_PDSR_PDSR18 (0x40000) +#define MCF_PAD_PDSR_PDSR19 (0x80000) +#define MCF_PAD_PDSR_PDSR20 (0x100000) +#define MCF_PAD_PDSR_PDSR21 (0x200000) +#define MCF_PAD_PDSR_PDSR22 (0x400000) +#define MCF_PAD_PDSR_PDSR23 (0x800000) +#define MCF_PAD_PDSR_PDSR24 (0x1000000) +#define MCF_PAD_PDSR_PDSR25 (0x2000000) +#define MCF_PAD_PDSR_PDSR26 (0x4000000) +#define MCF_PAD_PDSR_PDSR27 (0x8000000) + + +#endif /* __MCF52221_PAD_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PIT.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PIT.h new file mode 100644 index 000000000..7878cb1eb --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PIT.h @@ -0,0 +1,57 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_PIT_H__ +#define __MCF52221_PIT_H__ + + +/********************************************************************* +* +* Programmable Interrupt Timer (PIT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PIT0_PCSR (*(vuint16*)(0x40150000)) +#define MCF_PIT0_PMR (*(vuint16*)(0x40150002)) +#define MCF_PIT0_PCNTR (*(vuint16*)(0x40150004)) + +#define MCF_PIT1_PCSR (*(vuint16*)(0x40160000)) +#define MCF_PIT1_PMR (*(vuint16*)(0x40160002)) +#define MCF_PIT1_PCNTR (*(vuint16*)(0x40160004)) + +#define MCF_PIT_PCSR(x) (*(vuint16*)(0x40150000 + ((x)*0x10000))) +#define MCF_PIT_PMR(x) (*(vuint16*)(0x40150002 + ((x)*0x10000))) +#define MCF_PIT_PCNTR(x) (*(vuint16*)(0x40150004 + ((x)*0x10000))) + + +/* Bit definitions and macros for MCF_PIT_PCSR */ +#define MCF_PIT_PCSR_EN (0x1) +#define MCF_PIT_PCSR_RLD (0x2) +#define MCF_PIT_PCSR_PIF (0x4) +#define MCF_PIT_PCSR_PIE (0x8) +#define MCF_PIT_PCSR_OVW (0x10) +#define MCF_PIT_PCSR_DBG (0x20) +#define MCF_PIT_PCSR_DOZE (0x40) +#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8) + +/* Bit definitions and macros for MCF_PIT_PMR */ +#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PIT_PCNTR */ +#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF52221_PIT_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PMM.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PMM.h new file mode 100644 index 000000000..f61773a86 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PMM.h @@ -0,0 +1,44 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_PMM_H__ +#define __MCF52221_PMM_H__ + + +/********************************************************************* +* +* Power Management (PMM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PMM_LPICR (*(vuint8 *)(0x40000012)) +#define MCF_PMM_LPCR (*(vuint8 *)(0x40110007)) + + +/* Bit definitions and macros for MCF_PMM_LPICR */ +#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4) +#define MCF_PMM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_PMM_LPCR */ +#define MCF_PMM_LPCR_STPMD (0x8) +#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6) +#define MCF_PMM_LPCR_LPMD_RUN (0) +#define MCF_PMM_LPCR_LPMD_DOZE (0x40) +#define MCF_PMM_LPCR_LPMD_WAIT (0x80) +#define MCF_PMM_LPCR_LPMD_STOP (0xC0) + + +#endif /* __MCF52221_PMM_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PWM.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PWM.h new file mode 100644 index 000000000..46ec3c9f8 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PWM.h @@ -0,0 +1,142 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_PWM_H__ +#define __MCF52221_PWM_H__ + + +/********************************************************************* +* +* Pulse Width Modulation (PWM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PWM_PWME (*(vuint8 *)(0x401B0000)) +#define MCF_PWM_PWMPOL (*(vuint8 *)(0x401B0001)) +#define MCF_PWM_PWMCLK (*(vuint8 *)(0x401B0002)) +#define MCF_PWM_PWMPRCLK (*(vuint8 *)(0x401B0003)) +#define MCF_PWM_PWMCAE (*(vuint8 *)(0x401B0004)) +#define MCF_PWM_PWMCTL (*(vuint8 *)(0x401B0005)) +#define MCF_PWM_PWMSCLA (*(vuint8 *)(0x401B0008)) +#define MCF_PWM_PWMSCLB (*(vuint8 *)(0x401B0009)) +#define MCF_PWM_PWMCNT0 (*(vuint8 *)(0x401B000C)) +#define MCF_PWM_PWMCNT1 (*(vuint8 *)(0x401B000D)) +#define MCF_PWM_PWMCNT2 (*(vuint8 *)(0x401B000E)) +#define MCF_PWM_PWMCNT3 (*(vuint8 *)(0x401B000F)) +#define MCF_PWM_PWMCNT4 (*(vuint8 *)(0x401B0010)) +#define MCF_PWM_PWMCNT5 (*(vuint8 *)(0x401B0011)) +#define MCF_PWM_PWMCNT6 (*(vuint8 *)(0x401B0012)) +#define MCF_PWM_PWMCNT7 (*(vuint8 *)(0x401B0013)) +#define MCF_PWM_PWMPER0 (*(vuint8 *)(0x401B0014)) +#define MCF_PWM_PWMPER1 (*(vuint8 *)(0x401B0015)) +#define MCF_PWM_PWMPER2 (*(vuint8 *)(0x401B0016)) +#define MCF_PWM_PWMPER3 (*(vuint8 *)(0x401B0017)) +#define MCF_PWM_PWMPER4 (*(vuint8 *)(0x401B0018)) +#define MCF_PWM_PWMPER5 (*(vuint8 *)(0x401B0019)) +#define MCF_PWM_PWMPER6 (*(vuint8 *)(0x401B001A)) +#define MCF_PWM_PWMPER7 (*(vuint8 *)(0x401B001B)) +#define MCF_PWM_PWMDTY0 (*(vuint8 *)(0x401B001C)) +#define MCF_PWM_PWMDTY1 (*(vuint8 *)(0x401B001D)) +#define MCF_PWM_PWMDTY2 (*(vuint8 *)(0x401B001E)) +#define MCF_PWM_PWMDTY3 (*(vuint8 *)(0x401B001F)) +#define MCF_PWM_PWMDTY4 (*(vuint8 *)(0x401B0020)) +#define MCF_PWM_PWMDTY5 (*(vuint8 *)(0x401B0021)) +#define MCF_PWM_PWMDTY6 (*(vuint8 *)(0x401B0022)) +#define MCF_PWM_PWMDTY7 (*(vuint8 *)(0x401B0023)) +#define MCF_PWM_PWMSDN (*(vuint8 *)(0x401B0024)) +#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0x401B000C + ((x)*0x1))) +#define MCF_PWM_PWMPER(x) (*(vuint8 *)(0x401B0014 + ((x)*0x1))) +#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0x401B001C + ((x)*0x1))) + + +/* Bit definitions and macros for MCF_PWM_PWME */ +#define MCF_PWM_PWME_PWME0 (0x1) +#define MCF_PWM_PWME_PWME1 (0x2) +#define MCF_PWM_PWME_PWME2 (0x4) +#define MCF_PWM_PWME_PWME3 (0x8) +#define MCF_PWM_PWME_PWME4 (0x10) +#define MCF_PWM_PWME_PWME5 (0x20) +#define MCF_PWM_PWME_PWME6 (0x40) +#define MCF_PWM_PWME_PWME7 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMPOL */ +#define MCF_PWM_PWMPOL_PPOL0 (0x1) +#define MCF_PWM_PWMPOL_PPOL1 (0x2) +#define MCF_PWM_PWMPOL_PPOL2 (0x4) +#define MCF_PWM_PWMPOL_PPOL3 (0x8) +#define MCF_PWM_PWMPOL_PPOL4 (0x10) +#define MCF_PWM_PWMPOL_PPOL5 (0x20) +#define MCF_PWM_PWMPOL_PPOL6 (0x40) +#define MCF_PWM_PWMPOL_PPOL7 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMCLK */ +#define MCF_PWM_PWMCLK_PCLK0 (0x1) +#define MCF_PWM_PWMCLK_PCLK1 (0x2) +#define MCF_PWM_PWMCLK_PCLK2 (0x4) +#define MCF_PWM_PWMCLK_PCLK3 (0x8) +#define MCF_PWM_PWMCLK_PCLK4 (0x10) +#define MCF_PWM_PWMCLK_PCLK5 (0x20) +#define MCF_PWM_PWMCLK_PCLK6 (0x40) +#define MCF_PWM_PWMCLK_PCLK7 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ +#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x7)<<0) +#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_PWM_PWMCAE */ +#define MCF_PWM_PWMCAE_CAE0 (0x1) +#define MCF_PWM_PWMCAE_CAE1 (0x2) +#define MCF_PWM_PWMCAE_CAE2 (0x4) +#define MCF_PWM_PWMCAE_CAE3 (0x8) +#define MCF_PWM_PWMCAE_CAE4 (0x10) +#define MCF_PWM_PWMCAE_CAE5 (0x20) +#define MCF_PWM_PWMCAE_CAE6 (0x40) +#define MCF_PWM_PWMCAE_CAE7 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMCTL */ +#define MCF_PWM_PWMCTL_PFRZ (0x4) +#define MCF_PWM_PWMCTL_PSWAI (0x8) +#define MCF_PWM_PWMCTL_CON01 (0x10) +#define MCF_PWM_PWMCTL_CON23 (0x20) +#define MCF_PWM_PWMCTL_CON45 (0x40) +#define MCF_PWM_PWMCTL_CON67 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMSCLA */ +#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSCLB */ +#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMCNT */ +#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMPER */ +#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMDTY */ +#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSDN */ +#define MCF_PWM_PWMSDN_SDNEN (0x1) +#define MCF_PWM_PWMSDN_PWM7IL (0x2) +#define MCF_PWM_PWMSDN_PWM7IN (0x4) +#define MCF_PWM_PWMSDN_LVL (0x10) +#define MCF_PWM_PWMSDN_RESTART (0x20) +#define MCF_PWM_PWMSDN_IE (0x40) +#define MCF_PWM_PWMSDN_IF (0x80) + + +#endif /* __MCF52221_PWM_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_QSPI.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_QSPI.h new file mode 100644 index 000000000..c0ee0986f --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_QSPI.h @@ -0,0 +1,86 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_QSPI_H__ +#define __MCF52221_QSPI_H__ + + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_QSPI_QMR (*(vuint16*)(0x40000340)) +#define MCF_QSPI_QDLYR (*(vuint16*)(0x40000344)) +#define MCF_QSPI_QWR (*(vuint16*)(0x40000348)) +#define MCF_QSPI_QIR (*(vuint16*)(0x4000034C)) +#define MCF_QSPI_QAR (*(vuint16*)(0x40000350)) +#define MCF_QSPI_QDR (*(vuint16*)(0x40000354)) + + +/* Bit definitions and macros for MCF_QSPI_QMR */ +#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0) +#define MCF_QSPI_QMR_CPHA (0x100) +#define MCF_QSPI_QMR_CPOL (0x200) +#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA) +#define MCF_QSPI_QMR_DOHIE (0x4000) +#define MCF_QSPI_QMR_MSTR (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QDLYR */ +#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0) +#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8) +#define MCF_QSPI_QDLYR_SPE (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QWR */ +#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0) +#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4) +#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8) +#define MCF_QSPI_QWR_CSIV (0x1000) +#define MCF_QSPI_QWR_WRTO (0x2000) +#define MCF_QSPI_QWR_WREN (0x4000) +#define MCF_QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QIR */ +#define MCF_QSPI_QIR_SPIF (0x1) +#define MCF_QSPI_QIR_ABRT (0x4) +#define MCF_QSPI_QIR_WCEF (0x8) +#define MCF_QSPI_QIR_SPIFE (0x100) +#define MCF_QSPI_QIR_ABRTE (0x400) +#define MCF_QSPI_QIR_WCEFE (0x800) +#define MCF_QSPI_QIR_ABRTL (0x1000) +#define MCF_QSPI_QIR_ABRTB (0x4000) +#define MCF_QSPI_QIR_WCEFB (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QAR */ +#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0) +#define MCF_QSPI_QAR_TRANS (0) +#define MCF_QSPI_QAR_RECV (0x10) +#define MCF_QSPI_QAR_CMD (0x20) + +/* Bit definitions and macros for MCF_QSPI_QDR */ +#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) +#define MCF_QSPI_QDR_CONT (0x8000) +#define MCF_QSPI_QDR_BITSE (0x4000) +#define MCF_QSPI_QDR_DT (0x2000) +#define MCF_QSPI_QDR_DSCK (0x1000) +#define MCF_QSPI_QDR_QSPI_CS3 (0x800) +#define MCF_QSPI_QDR_QSPI_CS2 (0x400) +#define MCF_QSPI_QDR_QSPI_CS1 (0x200) +#define MCF_QSPI_QDR_QSPI_CS0 (0x100) + + +#endif /* __MCF52221_QSPI_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RCM.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RCM.h new file mode 100644 index 000000000..36f163ba1 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RCM.h @@ -0,0 +1,48 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_RCM_H__ +#define __MCF52221_RCM_H__ + + +/********************************************************************* +* +* Reset Controller Module (RCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RCM_RCR (*(vuint8 *)(0x40110000)) +#define MCF_RCM_RSR (*(vuint8 *)(0x40110001)) + + +/* Bit definitions and macros for MCF_RCM_RCR */ +#define MCF_RCM_RCR_LVDE (0x1) +#define MCF_RCM_RCR_LVDRE (0x4) +#define MCF_RCM_RCR_LVDIE (0x8) +#define MCF_RCM_RCR_LVDF (0x10) +#define MCF_RCM_RCR_FRCRSTOUT (0x40) +#define MCF_RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for MCF_RCM_RSR */ +#define MCF_RCM_RSR_LOL (0x1) +#define MCF_RCM_RSR_LOC (0x2) +#define MCF_RCM_RSR_EXT (0x4) +#define MCF_RCM_RSR_POR (0x8) +#define MCF_RCM_RSR_SOFT (0x20) +#define MCF_RCM_RSR_LVD (0x40) + + +#endif /* __MCF52221_RCM_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RTC.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RTC.h new file mode 100644 index 000000000..256f6cc20 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RTC.h @@ -0,0 +1,83 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_RTC_H__ +#define __MCF52221_RTC_H__ + + +/********************************************************************* +* +* Real-Time Clock (RTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RTC_HOURMIN (*(vuint32*)(0x400003C0)) +#define MCF_RTC_SECONDS (*(vuint32*)(0x400003C4)) +#define MCF_RTC_ALRM_HM (*(vuint32*)(0x400003C8)) +#define MCF_RTC_ALRM_SEC (*(vuint32*)(0x400003CC)) +#define MCF_RTC_RTCCTL (*(vuint32*)(0x400003D0)) +#define MCF_RTC_RTCISR (*(vuint32*)(0x400003D4)) +#define MCF_RTC_RTCIENR (*(vuint32*)(0x400003D8)) +#define MCF_RTC_STPWCH (*(vuint32*)(0x400003DC)) +#define MCF_RTC_DAYS (*(vuint32*)(0x400003E0)) +#define MCF_RTC_ALRM_DAY (*(vuint32*)(0x400003E4)) + + +/* Bit definitions and macros for MCF_RTC_HOURMIN */ +#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x3F)<<0) +#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x1F)<<0x8) + +/* Bit definitions and macros for MCF_RTC_SECONDS */ +#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_RTC_ALRM_HM */ +#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x3F)<<0) +#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x1F)<<0x8) + +/* Bit definitions and macros for MCF_RTC_ALRM_SEC */ +#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_RTC_RTCCTL */ +#define MCF_RTC_RTCCTL_SWR (0x1) +#define MCF_RTC_RTCCTL_EN (0x80) + +/* Bit definitions and macros for MCF_RTC_RTCISR */ +#define MCF_RTC_RTCISR_SW (0x1) +#define MCF_RTC_RTCISR_MIN (0x2) +#define MCF_RTC_RTCISR_ALM (0x4) +#define MCF_RTC_RTCISR_DAY (0x8) +#define MCF_RTC_RTCISR_1HZ (0x10) +#define MCF_RTC_RTCISR_HR (0x20) + +/* Bit definitions and macros for MCF_RTC_RTCIENR */ +#define MCF_RTC_RTCIENR_SW (0x1) +#define MCF_RTC_RTCIENR_MIN (0x2) +#define MCF_RTC_RTCIENR_ALM (0x4) +#define MCF_RTC_RTCIENR_DAY (0x8) +#define MCF_RTC_RTCIENR_1HZ (0x10) +#define MCF_RTC_RTCIENR_HR (0x20) + +/* Bit definitions and macros for MCF_RTC_STPWCH */ +#define MCF_RTC_STPWCH_CNT(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_RTC_DAYS */ +#define MCF_RTC_DAYS_DAYS(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_RTC_ALRM_DAY */ +#define MCF_RTC_ALRM_DAY_DAYSAL(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF52221_RTC_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_SCM.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_SCM.h new file mode 100644 index 000000000..1eca68c04 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_SCM.h @@ -0,0 +1,202 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_SCM_H__ +#define __MCF52221_SCM_H__ + + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SCM_RAMBAR (*(vuint32*)(0x40000008)) +#define MCF_SCM_PPMRH (*(vuint32*)(0x4000000C)) +#define MCF_SCM_CRSR (*(vuint8 *)(0x40000010)) +#define MCF_SCM_CWCR (*(vuint8 *)(0x40000011)) +#define MCF_SCM_CWSR (*(vuint8 *)(0x40000013)) +#define MCF_SCM_DMAREQC (*(vuint32*)(0x40000014)) +#define MCF_SCM_PPMRL (*(vuint32*)(0x40000018)) +#define MCF_SCM_MPARK (*(vuint32*)(0x4000001C)) +#define MCF_SCM_MPR (*(vuint8 *)(0x40000020)) +#define MCF_SCM_PPMRS (*(vuint8 *)(0x40000021)) +#define MCF_SCM_PPMRC (*(vuint8 *)(0x40000022)) +#define MCF_SCM_IPSBMT (*(vuint8 *)(0x40000023)) +#define MCF_SCM_PACR0 (*(vuint8 *)(0x40000024)) +#define MCF_SCM_PACR1 (*(vuint8 *)(0x40000025)) +#define MCF_SCM_PACR2 (*(vuint8 *)(0x40000026)) +#define MCF_SCM_PACR3 (*(vuint8 *)(0x40000027)) +#define MCF_SCM_PACR4 (*(vuint8 *)(0x40000028)) +#define MCF_SCM_PACR5 (*(vuint8 *)(0x40000029)) +#define MCF_SCM_PACR6 (*(vuint8 *)(0x4000002A)) +#define MCF_SCM_PACR7 (*(vuint8 *)(0x4000002B)) +#define MCF_SCM_PACR8 (*(vuint8 *)(0x4000002C)) +#define MCF_SCM_GPACR0 (*(vuint8 *)(0x40000030)) +#define MCF_SCM_GPACR1 (*(vuint8 *)(0x40000031)) +#define MCF_SCM_PACR(x) (*(vuint8 *)(0x40000024 + ((x)*0x1))) +#define MCF_SCM_GPACR(x) (*(vuint8 *)(0x40000030 + ((x)*0x1))) + +/* Other macros */ +#define MCF_SCM_IPSBAR (*(vuint32*)(0x40000000)) +#define MCF_SCM_IPSBAR_V (0x1) +#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000) + + +/* Bit definitions and macros for MCF_SCM_RAMBAR */ +#define MCF_SCM_RAMBAR_BDE (0x200) +#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_SCM_PPMRH */ +#define MCF_SCM_PPMRH_CDPORTS (0x1) +#define MCF_SCM_PPMRH_CDEPORT (0x2) +#define MCF_SCM_PPMRH_CDPIT0 (0x8) +#define MCF_SCM_PPMRH_CDPIT1 (0x10) +#define MCF_SCM_PPMRH_CDADC (0x80) +#define MCF_SCM_PPMRH_CDGPT (0x100) +#define MCF_SCM_PPMRH_CDPWM (0x200) +#define MCF_SCM_PPMRH_CDFCAN (0x400) +#define MCF_SCM_PPMRH_CDCFM (0x800) + +/* Bit definitions and macros for MCF_SCM_CRSR */ +#define MCF_SCM_CRSR_EXT (0x80) + +/* Bit definitions and macros for MCF_SCM_CWCR */ +#define MCF_SCM_CWCR_CWTIF (0x1) +#define MCF_SCM_CWCR_CWTAVAL (0x2) +#define MCF_SCM_CWCR_CWTA (0x4) +#define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3) +#define MCF_SCM_CWCR_CWT_2_9 (0) +#define MCF_SCM_CWCR_CWT_2_11 (0x8) +#define MCF_SCM_CWCR_CWT_2_13 (0x10) +#define MCF_SCM_CWCR_CWT_2_15 (0x18) +#define MCF_SCM_CWCR_CWT_2_19 (0x20) +#define MCF_SCM_CWCR_CWT_2_23 (0x28) +#define MCF_SCM_CWCR_CWT_2_27 (0x30) +#define MCF_SCM_CWCR_CWT_2_31 (0x38) +#define MCF_SCM_CWCR_CWRI (0x40) +#define MCF_SCM_CWCR_CWE (0x80) + +/* Bit definitions and macros for MCF_SCM_CWSR */ +#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SCM_DMAREQC */ +#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0) +#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4) +#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8) +#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC) + +/* Bit definitions and macros for MCF_SCM_PPMRL */ +#define MCF_SCM_PPMRL_CDG (0x2) +#define MCF_SCM_PPMRL_CDDMA (0x10) +#define MCF_SCM_PPMRL_CDUART0 (0x20) +#define MCF_SCM_PPMRL_CDUART1 (0x40) +#define MCF_SCM_PPMRL_CDUART2 (0x80) +#define MCF_SCM_PPMRL_CDI2C (0x200) +#define MCF_SCM_PPMRL_CDQSPI (0x400) +#define MCF_SCM_PPMRL_CDTMR0 (0x2000) +#define MCF_SCM_PPMRL_CDTMR1 (0x4000) +#define MCF_SCM_PPMRL_CDTMR2 (0x8000) +#define MCF_SCM_PPMRL_CDTMR3 (0x10000) +#define MCF_SCM_PPMRL_CDINTC0 (0x20000) + +/* Bit definitions and macros for MCF_SCM_MPARK */ +#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8) +#define MCF_SCM_MPARK_PRKLAST (0x1000) +#define MCF_SCM_MPARK_TIMEOUT (0x2000) +#define MCF_SCM_MPARK_FIXED (0x4000) +#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12) +#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14) +#define MCF_SCM_MPARK_BCR24BIT (0x1000000) +#define MCF_SCM_MPARK_M2_P_EN (0x2000000) + +/* Bit definitions and macros for MCF_SCM_MPR */ +#define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0) + +/* Bit definitions and macros for MCF_SCM_PPMRS */ +#define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0) +#define MCF_SCM_PPMRS_DISABLE_ALL (0x40) +#define MCF_SCM_PPMRS_DISABLE_CFM (0x2B) +#define MCF_SCM_PPMRS_DISABLE_CAN (0x2A) +#define MCF_SCM_PPMRS_DISABLE_PWM (0x29) +#define MCF_SCM_PPMRS_DISABLE_GPT (0x28) +#define MCF_SCM_PPMRS_DISABLE_ADC (0x27) +#define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24) +#define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23) +#define MCF_SCM_PPMRS_DISABLE_EPORT (0x21) +#define MCF_SCM_PPMRS_DISABLE_PORTS (0x20) +#define MCF_SCM_PPMRS_DISABLE_INTC (0x11) +#define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10) +#define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF) +#define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE) +#define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD) +#define MCF_SCM_PPMRS_DISABLE_QSPI (0xA) +#define MCF_SCM_PPMRS_DISABLE_I2C (0x9) +#define MCF_SCM_PPMRS_DISABLE_UART2 (0x7) +#define MCF_SCM_PPMRS_DISABLE_UART1 (0x6) +#define MCF_SCM_PPMRS_DISABLE_UART0 (0x5) +#define MCF_SCM_PPMRS_DISABLE_DMA (0x4) +#define MCF_SCM_PPMRS_SET_CDG (0x1) + +/* Bit definitions and macros for MCF_SCM_PPMRC */ +#define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0) +#define MCF_SCM_PPMRC_ENABLE_ALL (0x40) +#define MCF_SCM_PPMRC_ENABLE_CFM (0x2B) +#define MCF_SCM_PPMRC_ENABLE_CAN (0x2A) +#define MCF_SCM_PPMRC_ENABLE_PWM (0x29) +#define MCF_SCM_PPMRC_ENABLE_GPT (0x28) +#define MCF_SCM_PPMRC_ENABLE_ADC (0x27) +#define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24) +#define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23) +#define MCF_SCM_PPMRC_ENABLE_EPORT (0x21) +#define MCF_SCM_PPMRC_ENABLE_PORTS (0x20) +#define MCF_SCM_PPMRC_ENABLE_INTC (0x11) +#define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10) +#define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF) +#define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE) +#define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD) +#define MCF_SCM_PPMRC_ENABLE_QSPI (0xA) +#define MCF_SCM_PPMRC_ENABLE_I2C (0x9) +#define MCF_SCM_PPMRC_ENABLE_UART2 (0x7) +#define MCF_SCM_PPMRC_ENABLE_UART1 (0x6) +#define MCF_SCM_PPMRC_ENABLE_UART0 (0x5) +#define MCF_SCM_PPMRC_ENABLE_DMA (0x4) +#define MCF_SCM_PPMRC_CLEAR_CDG (0x1) + +/* Bit definitions and macros for MCF_SCM_IPSBMT */ +#define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0) +#define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0) +#define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1) +#define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2) +#define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3) +#define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4) +#define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5) +#define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6) +#define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7) +#define MCF_SCM_IPSBMT_BME (0x8) + +/* Bit definitions and macros for MCF_SCM_PACR */ +#define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0) +#define MCF_SCM_PACR_LOCK0 (0x8) +#define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4) +#define MCF_SCM_PACR_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_GPACR */ +#define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0) +#define MCF_SCM_GPACR_LOCK (0x80) + + +#endif /* __MCF52221_SCM_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_UART.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_UART.h new file mode 100644 index 000000000..c925ac402 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_UART.h @@ -0,0 +1,202 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_UART_H__ +#define __MCF52221_UART_H__ + + +/********************************************************************* +* +* Universal Asynchronous Receiver Transmitter (UART) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_UART0_UMR1 (*(vuint8 *)(0x40000200)) +#define MCF_UART0_UMR2 (*(vuint8 *)(0x40000200)) +#define MCF_UART0_USR (*(vuint8 *)(0x40000204)) +#define MCF_UART0_UCSR (*(vuint8 *)(0x40000204)) +#define MCF_UART0_UCR (*(vuint8 *)(0x40000208)) +#define MCF_UART0_URB (*(vuint8 *)(0x4000020C)) +#define MCF_UART0_UTB (*(vuint8 *)(0x4000020C)) +#define MCF_UART0_UIPCR (*(vuint8 *)(0x40000210)) +#define MCF_UART0_UACR (*(vuint8 *)(0x40000210)) +#define MCF_UART0_UIMR (*(vuint8 *)(0x40000214)) +#define MCF_UART0_UISR (*(vuint8 *)(0x40000214)) +#define MCF_UART0_UBG1 (*(vuint8 *)(0x40000218)) +#define MCF_UART0_UBG2 (*(vuint8 *)(0x4000021C)) +#define MCF_UART0_UIP (*(vuint8 *)(0x40000234)) +#define MCF_UART0_UOP1 (*(vuint8 *)(0x40000238)) +#define MCF_UART0_UOP0 (*(vuint8 *)(0x4000023C)) + +#define MCF_UART1_UMR1 (*(vuint8 *)(0x40000240)) +#define MCF_UART1_UMR2 (*(vuint8 *)(0x40000240)) +#define MCF_UART1_USR (*(vuint8 *)(0x40000244)) +#define MCF_UART1_UCSR (*(vuint8 *)(0x40000244)) +#define MCF_UART1_UCR (*(vuint8 *)(0x40000248)) +#define MCF_UART1_URB (*(vuint8 *)(0x4000024C)) +#define MCF_UART1_UTB (*(vuint8 *)(0x4000024C)) +#define MCF_UART1_UIPCR (*(vuint8 *)(0x40000250)) +#define MCF_UART1_UACR (*(vuint8 *)(0x40000250)) +#define MCF_UART1_UIMR (*(vuint8 *)(0x40000254)) +#define MCF_UART1_UISR (*(vuint8 *)(0x40000254)) +#define MCF_UART1_UBG1 (*(vuint8 *)(0x40000258)) +#define MCF_UART1_UBG2 (*(vuint8 *)(0x4000025C)) +#define MCF_UART1_UIP (*(vuint8 *)(0x40000274)) +#define MCF_UART1_UOP1 (*(vuint8 *)(0x40000278)) +#define MCF_UART1_UOP0 (*(vuint8 *)(0x4000027C)) + +#define MCF_UART2_UMR1 (*(vuint8 *)(0x40000280)) +#define MCF_UART2_UMR2 (*(vuint8 *)(0x40000280)) +#define MCF_UART2_USR (*(vuint8 *)(0x40000284)) +#define MCF_UART2_UCSR (*(vuint8 *)(0x40000284)) +#define MCF_UART2_UCR (*(vuint8 *)(0x40000288)) +#define MCF_UART2_URB (*(vuint8 *)(0x4000028C)) +#define MCF_UART2_UTB (*(vuint8 *)(0x4000028C)) +#define MCF_UART2_UIPCR (*(vuint8 *)(0x40000290)) +#define MCF_UART2_UACR (*(vuint8 *)(0x40000290)) +#define MCF_UART2_UIMR (*(vuint8 *)(0x40000294)) +#define MCF_UART2_UISR (*(vuint8 *)(0x40000294)) +#define MCF_UART2_UBG1 (*(vuint8 *)(0x40000298)) +#define MCF_UART2_UBG2 (*(vuint8 *)(0x4000029C)) +#define MCF_UART2_UIP (*(vuint8 *)(0x400002B4)) +#define MCF_UART2_UOP1 (*(vuint8 *)(0x400002B8)) +#define MCF_UART2_UOP0 (*(vuint8 *)(0x400002BC)) + +#define MCF_UART_UMR(x) (*(vuint8 *)(0x40000200 + ((x)*0x40))) +#define MCF_UART_USR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40))) +#define MCF_UART_UCSR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40))) +#define MCF_UART_UCR(x) (*(vuint8 *)(0x40000208 + ((x)*0x40))) +#define MCF_UART_URB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40))) +#define MCF_UART_UTB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40))) +#define MCF_UART_UIPCR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40))) +#define MCF_UART_UACR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40))) +#define MCF_UART_UIMR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40))) +#define MCF_UART_UISR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40))) +#define MCF_UART_UBG1(x) (*(vuint8 *)(0x40000218 + ((x)*0x40))) +#define MCF_UART_UBG2(x) (*(vuint8 *)(0x4000021C + ((x)*0x40))) +#define MCF_UART_UIP(x) (*(vuint8 *)(0x40000234 + ((x)*0x40))) +#define MCF_UART_UOP1(x) (*(vuint8 *)(0x40000238 + ((x)*0x40))) +#define MCF_UART_UOP0(x) (*(vuint8 *)(0x4000023C + ((x)*0x40))) + +/* Bit definitions and macros for MCF_UART_UMR */ +#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0) +#define MCF_UART_UMR_BC_5 (0) +#define MCF_UART_UMR_BC_6 (0x1) +#define MCF_UART_UMR_BC_7 (0x2) +#define MCF_UART_UMR_BC_8 (0x3) +#define MCF_UART_UMR_PT (0x4) +#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3) +#define MCF_UART_UMR_ERR (0x20) +#define MCF_UART_UMR_RXIRQ (0x40) +#define MCF_UART_UMR_RXRTS (0x80) +#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) +#define MCF_UART_UMR_PM_MULTI_DATA (0x18) +#define MCF_UART_UMR_PM_NONE (0x10) +#define MCF_UART_UMR_PM_FORCE_HI (0xC) +#define MCF_UART_UMR_PM_FORCE_LO (0x8) +#define MCF_UART_UMR_PM_ODD (0x4) +#define MCF_UART_UMR_PM_EVEN (0) +#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0) +#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7) +#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8) +#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF) +#define MCF_UART_UMR_TXCTS (0x10) +#define MCF_UART_UMR_TXRTS (0x20) +#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6) +#define MCF_UART_UMR_CM_NORMAL (0) +#define MCF_UART_UMR_CM_ECHO (0x40) +#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) +#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) + +/* Bit definitions and macros for MCF_UART_USR */ +#define MCF_UART_USR_RXRDY (0x1) +#define MCF_UART_USR_FFULL (0x2) +#define MCF_UART_USR_TXRDY (0x4) +#define MCF_UART_USR_TXEMP (0x8) +#define MCF_UART_USR_OE (0x10) +#define MCF_UART_USR_PE (0x20) +#define MCF_UART_USR_FE (0x40) +#define MCF_UART_USR_RB (0x80) + +/* Bit definitions and macros for MCF_UART_UCSR */ +#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0) +#define MCF_UART_UCSR_TCS_SYS_CLK (0xD) +#define MCF_UART_UCSR_TCS_CTM16 (0xE) +#define MCF_UART_UCSR_TCS_CTM (0xF) +#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4) +#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF_UART_UCSR_RCS_CTM16 (0xE0) +#define MCF_UART_UCSR_RCS_CTM (0xF0) + +/* Bit definitions and macros for MCF_UART_UCR */ +#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0) +#define MCF_UART_UCR_RX_ENABLED (0x1) +#define MCF_UART_UCR_RX_DISABLED (0x2) +#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2) +#define MCF_UART_UCR_TX_ENABLED (0x4) +#define MCF_UART_UCR_TX_DISABLED (0x8) +#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4) +#define MCF_UART_UCR_NONE (0) +#define MCF_UART_UCR_RESET_MR (0x10) +#define MCF_UART_UCR_RESET_RX (0x20) +#define MCF_UART_UCR_RESET_TX (0x30) +#define MCF_UART_UCR_RESET_ERROR (0x40) +#define MCF_UART_UCR_RESET_BKCHGINT (0x50) +#define MCF_UART_UCR_START_BREAK (0x60) +#define MCF_UART_UCR_STOP_BREAK (0x70) + +/* Bit definitions and macros for MCF_UART_URB */ +#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_UART_UTB */ +#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_UART_UIPCR */ +#define MCF_UART_UIPCR_CTS (0x1) +#define MCF_UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for MCF_UART_UACR */ +#define MCF_UART_UACR_IEC (0x1) + +/* Bit definitions and macros for MCF_UART_UIMR */ +#define MCF_UART_UIMR_TXRDY (0x1) +#define MCF_UART_UIMR_FFULL_RXRDY (0x2) +#define MCF_UART_UIMR_DB (0x4) +#define MCF_UART_UIMR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UISR */ +#define MCF_UART_UISR_TXRDY (0x1) +#define MCF_UART_UISR_FFULL_RXRDY (0x2) +#define MCF_UART_UISR_DB (0x4) +#define MCF_UART_UISR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UBG1 */ +#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_UART_UBG2 */ +#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_UART_UIP */ +#define MCF_UART_UIP_CTS (0x1) + +/* Bit definitions and macros for MCF_UART_UOP1 */ +#define MCF_UART_UOP1_RTS (0x1) + +/* Bit definitions and macros for MCF_UART_UOP0 */ +#define MCF_UART_UOP0_RTS (0x1) + + +#endif /* __MCF52221_UART_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_USB_OTG.h b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_USB_OTG.h new file mode 100644 index 000000000..ab0bbaf57 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_USB_OTG.h @@ -0,0 +1,271 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.95 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF52221_USB_OTG_H__ +#define __MCF52221_USB_OTG_H__ + + +/********************************************************************* +* +* Universal Serial Bus - OTG Controller (USB_OTG) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_USB_OTG_PER_ID (*(vuint8 *)(0x401C0000)) +#define MCF_USB_OTG_ID_COMP (*(vuint8 *)(0x401C0004)) +#define MCF_USB_OTG_REV (*(vuint8 *)(0x401C0008)) +#define MCF_USB_OTG_ADD_INFO (*(vuint8 *)(0x401C000C)) +#define MCF_USB_OTG_OTG_INT_STAT (*(vuint8 *)(0x401C0010)) +#define MCF_USB_OTG_OTG_INT_EN (*(vuint8 *)(0x401C0014)) +#define MCF_USB_OTG_OTG_STAT (*(vuint8 *)(0x401C0018)) +#define MCF_USB_OTG_OTG_CTRL (*(vuint8 *)(0x401C001C)) +#define MCF_USB_OTG_INT_STAT (*(vuint8 *)(0x401C0080)) +#define MCF_USB_OTG_INT_ENB (*(vuint8 *)(0x401C0084)) +#define MCF_USB_OTG_ERR_STAT (*(vuint8 *)(0x401C0088)) +#define MCF_USB_OTG_ERR_ENB (*(vuint8 *)(0x401C008C)) +#define MCF_USB_OTG_STAT (*(vuint8 *)(0x401C0090)) +#define MCF_USB_OTG_CTL (*(vuint8 *)(0x401C0094)) +#define MCF_USB_OTG_ADDR (*(vuint8 *)(0x401C0098)) +#define MCF_USB_OTG_BDT_PAGE_01 (*(vuint8 *)(0x401C009C)) +#define MCF_USB_OTG_FRM_NUML (*(vuint8 *)(0x401C00A0)) +#define MCF_USB_OTG_FRM_NUMH (*(vuint8 *)(0x401C00A4)) +#define MCF_USB_OTG_TOKEN (*(vuint8 *)(0x401C00A8)) +#define MCF_USB_OTG_SOF_THLD (*(vuint8 *)(0x401C00AC)) +#define MCF_USB_OTG_BDT_PAGE_02 (*(vuint8 *)(0x401C00B0)) +#define MCF_USB_OTG_BDT_PAGE_03 (*(vuint8 *)(0x401C00B4)) +#define MCF_USB_OTG_ENDPT0 (*(vuint8 *)(0x401C00C0)) +#define MCF_USB_OTG_ENDPT1 (*(vuint8 *)(0x401C00C4)) +#define MCF_USB_OTG_ENDPT2 (*(vuint8 *)(0x401C00C8)) +#define MCF_USB_OTG_ENDPT3 (*(vuint8 *)(0x401C00CC)) +#define MCF_USB_OTG_ENDPT4 (*(vuint8 *)(0x401C00D0)) +#define MCF_USB_OTG_ENDPT5 (*(vuint8 *)(0x401C00D4)) +#define MCF_USB_OTG_ENDPT6 (*(vuint8 *)(0x401C00D8)) +#define MCF_USB_OTG_ENDPT7 (*(vuint8 *)(0x401C00DC)) +#define MCF_USB_OTG_ENDPT8 (*(vuint8 *)(0x401C00E0)) +#define MCF_USB_OTG_ENDPT9 (*(vuint8 *)(0x401C00E4)) +#define MCF_USB_OTG_ENDPT10 (*(vuint8 *)(0x401C00E8)) +#define MCF_USB_OTG_ENDPT11 (*(vuint8 *)(0x401C00EC)) +#define MCF_USB_OTG_ENDPT12 (*(vuint8 *)(0x401C00F0)) +#define MCF_USB_OTG_ENDPT13 (*(vuint8 *)(0x401C00F4)) +#define MCF_USB_OTG_ENDPT14 (*(vuint8 *)(0x401C00F8)) +#define MCF_USB_OTG_ENDPT15 (*(vuint8 *)(0x401C00FC)) +#define MCF_USB_OTG_USB_CTRL (*(vuint8 *)(0x401C0100)) +#define MCF_USB_OTG_USB_OTG_OBSERVE (*(vuint8 *)(0x401C0104)) +#define MCF_USB_OTG_USB_OTG_CONTROL (*(vuint8 *)(0x401C0108)) +#define MCF_USB_OTG_ENDPT(x) (*(vuint8 *)(0x401C00C0 + ((x)*0x4))) + +/* Other macros */ +#define MCF_USB_OTG_FRM_NUM (MCF_USB_OTG_INT_STAT=MCF_USB_OTG_INT_STAT_SOF_TOK ,MCF_USB_OTG_FRM_NUML | (((vuint16)MCF_USB_OTG_FRM_NUMH)<<8)) + + +/* Bit definitions and macros for MCF_USB_OTG_PER_ID */ +#define MCF_USB_OTG_PER_ID_ID(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_USB_OTG_ID_COMP */ +#define MCF_USB_OTG_ID_COMP_NID(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_USB_OTG_REV */ +#define MCF_USB_OTG_REV_REV(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_OTG_ADD_INFO */ +#define MCF_USB_OTG_ADD_INFO_IEHOST (0x1) +#define MCF_USB_OTG_ADD_INFO_IRQ_NUM(x) (((x)&0x1F)<<0x3) + +/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_STAT */ +#define MCF_USB_OTG_OTG_INT_STAT_A_VBUS_CHG (0x1) +#define MCF_USB_OTG_OTG_INT_STAT_B_SESS_CHG (0x4) +#define MCF_USB_OTG_OTG_INT_STAT_SESS_VLD_CHG (0x8) +#define MCF_USB_OTG_OTG_INT_STAT_LINE_STATE_CHG (0x20) +#define MCF_USB_OTG_OTG_INT_STAT_1_MSEC (0x40) +#define MCF_USB_OTG_OTG_INT_STAT_ID_CHG (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_EN */ +#define MCF_USB_OTG_OTG_INT_EN_A_VBUS_EN (0x1) +#define MCF_USB_OTG_OTG_INT_EN_B_SESS_EN (0x4) +#define MCF_USB_OTG_OTG_INT_EN_SESS_VLD_EN (0x8) +#define MCF_USB_OTG_OTG_INT_EN_LINE_STATE_EN (0x20) +#define MCF_USB_OTG_OTG_INT_EN_1_MSEC_EN (0x40) +#define MCF_USB_OTG_OTG_INT_EN_ID_EN (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_OTG_STAT */ +#define MCF_USB_OTG_OTG_STAT_A_VBUS_VLD (0x1) +#define MCF_USB_OTG_OTG_STAT_B_SESS_END (0x4) +#define MCF_USB_OTG_OTG_STAT_SESS_VLD (0x8) +#define MCF_USB_OTG_OTG_STAT_LINE_STATE_STABLE (0x20) +#define MCF_USB_OTG_OTG_STAT_1_MSEC_EN (0x40) +#define MCF_USB_OTG_OTG_STAT_ID (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_OTG_CTRL */ +#define MCF_USB_OTG_OTG_CTRL_VBUS_DSCHG (0x1) +#define MCF_USB_OTG_OTG_CTRL_VBUS_CHG (0x2) +#define MCF_USB_OTG_OTG_CTRL_OTG_EN (0x4) +#define MCF_USB_OTG_OTG_CTRL_VBUS_ON (0x8) +#define MCF_USB_OTG_OTG_CTRL_DM_LOW (0x10) +#define MCF_USB_OTG_OTG_CTRL_DP_LOW (0x20) +#define MCF_USB_OTG_OTG_CTRL_DP_HIGH (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_INT_STAT */ +#define MCF_USB_OTG_INT_STAT_USB_RST (0x1) +#define MCF_USB_OTG_INT_STAT_ERROR (0x2) +#define MCF_USB_OTG_INT_STAT_SOF_TOK (0x4) +#define MCF_USB_OTG_INT_STAT_TOK_DNE (0x8) +#define MCF_USB_OTG_INT_STAT_SLEEP (0x10) +#define MCF_USB_OTG_INT_STAT_RESUME (0x20) +#define MCF_USB_OTG_INT_STAT_ATTACH (0x40) +#define MCF_USB_OTG_INT_STAT_STALL (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_INT_ENB */ +#define MCF_USB_OTG_INT_ENB_USB_RST_EN (0x1) +#define MCF_USB_OTG_INT_ENB_ERROR_EN (0x2) +#define MCF_USB_OTG_INT_ENB_SOF_TOK_EN (0x4) +#define MCF_USB_OTG_INT_ENB_TOK_DNE_EN (0x8) +#define MCF_USB_OTG_INT_ENB_SLEEP_EN (0x10) +#define MCF_USB_OTG_INT_ENB_RESUME_EN (0x20) +#define MCF_USB_OTG_INT_ENB_ATTACH_EN (0x40) +#define MCF_USB_OTG_INT_ENB_STALL_EN (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_ERR_STAT */ +#define MCF_USB_OTG_ERR_STAT_PID_ERR (0x1) +#define MCF_USB_OTG_ERR_STAT_CRC5_EOF (0x2) +#define MCF_USB_OTG_ERR_STAT_CRC16 (0x4) +#define MCF_USB_OTG_ERR_STAT_DFN8 (0x8) +#define MCF_USB_OTG_ERR_STAT_BTO_ERR (0x10) +#define MCF_USB_OTG_ERR_STAT_DMA_ERR (0x20) +#define MCF_USB_OTG_ERR_STAT_BTS_ERR (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_ERR_ENB */ +#define MCF_USB_OTG_ERR_ENB_PID_ERR_EN (0x1) +#define MCF_USB_OTG_ERR_ENB_CRC5_EOF_EN (0x2) +#define MCF_USB_OTG_ERR_ENB_CRC16_EN (0x4) +#define MCF_USB_OTG_ERR_ENB_DFN8_EN (0x8) +#define MCF_USB_OTG_ERR_ENB_BTO_ERR_EN (0x10) +#define MCF_USB_OTG_ERR_ENB_DMA_ERR_EN (0x20) +#define MCF_USB_OTG_ERR_ENB_BTS_ERR_EN (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_STAT */ +#define MCF_USB_OTG_STAT_ODD (0x4) +#define MCF_USB_OTG_STAT_TX (0x8) +#define MCF_USB_OTG_STAT_ENDP(x) (((x)&0xF)<<0x4) + +/* Bit definitions and macros for MCF_USB_OTG_CTL */ +#define MCF_USB_OTG_CTL_USB_EN_SOF_EN (0x1) +#define MCF_USB_OTG_CTL_ODD_RST (0x2) +#define MCF_USB_OTG_CTL_RESUME (0x4) +#define MCF_USB_OTG_CTL_HOST_MODE_EN (0x8) +#define MCF_USB_OTG_CTL_RESET (0x10) +#define MCF_USB_OTG_CTL_TXSUSPEND_TOKENBUSY (0x20) +#define MCF_USB_OTG_CTL_SE0 (0x40) +#define MCF_USB_OTG_CTL_JSTATE (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_ADDR */ +#define MCF_USB_OTG_ADDR_ADDR(x) (((x)&0x7F)<<0) +#define MCF_USB_OTG_ADDR_LS_EN (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_01 */ +#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA9 (0x2) +#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA10 (0x4) +#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA11 (0x8) +#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA12 (0x10) +#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA13 (0x20) +#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA14 (0x40) +#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA15 (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_FRM_NUML */ +#define MCF_USB_OTG_FRM_NUML_FRM0 (0x1) +#define MCF_USB_OTG_FRM_NUML_FRM1 (0x2) +#define MCF_USB_OTG_FRM_NUML_FRM2 (0x4) +#define MCF_USB_OTG_FRM_NUML_FRM3 (0x8) +#define MCF_USB_OTG_FRM_NUML_FRM4 (0x10) +#define MCF_USB_OTG_FRM_NUML_FRM5 (0x20) +#define MCF_USB_OTG_FRM_NUML_FRM6 (0x40) +#define MCF_USB_OTG_FRM_NUML_FRM7 (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_FRM_NUMH */ +#define MCF_USB_OTG_FRM_NUMH_FRM8 (0x1) +#define MCF_USB_OTG_FRM_NUMH_FRM9 (0x2) +#define MCF_USB_OTG_FRM_NUMH_FRM10 (0x4) + +/* Bit definitions and macros for MCF_USB_OTG_TOKEN */ +#define MCF_USB_OTG_TOKEN_TOKEN_ENDPT(x) (((x)&0xF)<<0) +#define MCF_USB_OTG_TOKEN_TOKEN_PID(x) (((x)&0xF)<<0x4) +#define MCF_USB_OTG_TOKEN_TOKEN_PID_OUT (0x10) +#define MCF_USB_OTG_TOKEN_TOKEN_PID_IN (0x90) +#define MCF_USB_OTG_TOKEN_TOKEN_PID_SETUP (0xD0) + +/* Bit definitions and macros for MCF_USB_OTG_SOF_THLD */ +#define MCF_USB_OTG_SOF_THLD_CNT0 (0x1) +#define MCF_USB_OTG_SOF_THLD_CNT1 (0x2) +#define MCF_USB_OTG_SOF_THLD_CNT2 (0x4) +#define MCF_USB_OTG_SOF_THLD_CNT3 (0x8) +#define MCF_USB_OTG_SOF_THLD_CNT4 (0x10) +#define MCF_USB_OTG_SOF_THLD_CNT5 (0x20) +#define MCF_USB_OTG_SOF_THLD_CNT6 (0x40) +#define MCF_USB_OTG_SOF_THLD_CNT7 (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_02 */ +#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA16 (0x1) +#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA17 (0x2) +#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA18 (0x4) +#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA19 (0x8) +#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA20 (0x10) +#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA21 (0x20) +#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA22 (0x40) +#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA23 (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_03 */ +#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA24 (0x1) +#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA25 (0x2) +#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA26 (0x4) +#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA27 (0x8) +#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA28 (0x10) +#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA29 (0x20) +#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA30 (0x40) +#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA31 (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_ENDPT */ +#define MCF_USB_OTG_ENDPT_EP_HSHK (0x1) +#define MCF_USB_OTG_ENDPT_EP_STALL (0x2) +#define MCF_USB_OTG_ENDPT_EP_TX_EN (0x4) +#define MCF_USB_OTG_ENDPT_EP_RX_EN (0x8) +#define MCF_USB_OTG_ENDPT_EP_CTL_DIS (0x10) +#define MCF_USB_OTG_ENDPT_RETRY_DIS (0x40) +#define MCF_USB_OTG_ENDPT_HOST_WO_HUB (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_USB_CTRL */ +#define MCF_USB_OTG_USB_CTRL_CLK_SRC(x) (((x)&0x3)<<0) +#define MCF_USB_OTG_USB_CTRL_CLK_SRC_ALTCLK (0) +#define MCF_USB_OTG_USB_CTRL_CLK_SRC_OSCCLK (0x1) +#define MCF_USB_OTG_USB_CTRL_CLK_SRC_SYSCLK (0x3) +#define MCF_USB_OTG_USB_CTRL_PDE (0x40) +#define MCF_USB_OTG_USB_CTRL_SUSP (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_OBSERVE */ +#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSDIS (0x2) +#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSCHG (0x4) +#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSE (0x8) +#define MCF_USB_OTG_USB_OTG_OBSERVE_DM_PD (0x10) +#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PD (0x40) +#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PU (0x80) + +/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_CONTROL */ +#define MCF_USB_OTG_USB_OTG_CONTROL_SESSEND (0x1) +#define MCF_USB_OTG_USB_OTG_CONTROL_SESSVLD (0x2) +#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSVLD (0x4) +#define MCF_USB_OTG_USB_OTG_CONTROL_ID (0x8) +#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSD (0x10) + + +#endif /* __MCF52221_USB_OTG_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_CONSOLE_INTERNAL_RAM.lcf b/Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_CONSOLE_INTERNAL_RAM.lcf new file mode 100644 index 000000000..b6ecc52fa --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_CONSOLE_INTERNAL_RAM.lcf @@ -0,0 +1,133 @@ +# Sample Linker Command File for CodeWarrior for ColdFire + +KEEP_SECTION {.vectortable} + +# Memory ranges + +MEMORY { + vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000500 + code (RX) : ORIGIN = 0x20000500, LENGTH = 0x00002B00 + userram (RWX) : ORIGIN = 0x20003000, LENGTH = 0x00001000 +} + +SECTIONS { + +# Heap and Stack sizes definition + ___heap_size = 0x400; + ___stack_size = 0x400; + + + +# MCF52221 Derivative Memory map definitions from linker command files: +# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker +# symbols must be defined in the linker command file. + +# Memory Mapped Registers (IPSBAR= 0x40000000) + ___IPSBAR = 0x40000000; + +# 16 Kbytes Internal SRAM + ___RAMBAR = 0x20000000; + ___RAMBAR_SIZE = 0x00004000; + +# 128 KByte Internal Flash Memory + ___FLASHBAR = 0x00000000; + ___FLASHBAR_SIZE = 0x00020000; + + ___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4; + + .userram : {} > userram + .code : {} > code + .vectorram : {} > vectorram + + .vectors : + { + exceptions.c(.vectortable) + . = ALIGN (0x4); + } >> code + + + .text : + { + *(.text) + . = ALIGN (0x4); + *(.rodata) + . = ALIGN (0x4); + ___ROM_AT = .; + ___DATA_ROM = .; + } >> code + + .data : AT(___ROM_AT) + { + ___DATA_RAM = .; + . = ALIGN(0x4); + *(.exception) + . = ALIGN(0x4); + __exception_table_start__ = .; + EXCEPTION + __exception_table_end__ = .; + + ___sinit__ = .; + STATICINIT + __START_DATA = .; + + *(.data) + . = ALIGN (0x4); + __END_DATA = .; + + __START_SDATA = .; + *(.sdata) + . = ALIGN (0x4); + __END_SDATA = .; + + ___DATA_END = .; + __SDA_BASE = .; + . = ALIGN (0x4); + } >> userram + + .bss : + { + ___BSS_START = .; + __START_SBSS = .; + *(.sbss) + . = ALIGN (0x4); + *(SCOMMON) + __END_SBSS = .; + + __START_BSS = .; + *(.bss) + . = ALIGN (0x4); + *(COMMON) + __END_BSS = .; + ___BSS_END = .; + + . = ALIGN(0x4); + } >> userram + + .custom : + { + ___HEAP_START = .; + ___heap_addr = ___HEAP_START; + ___HEAP_END = ___HEAP_START + ___heap_size; + ___SP_END = ___HEAP_END; + ___SP_INIT = ___SP_END + ___stack_size; + + . = ALIGN (0x4); + } >> userram + + ___VECTOR_RAM = ADDR(.vectorram); + + __SP_INIT = ___SP_INIT; + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + WRITEW(___ROM_AT); + WRITEW(ADDR(.data)); + WRITEW(SIZEOF(.data)); + WRITEW(0); + WRITEW(0); + WRITEW(0); + } + +} \ No newline at end of file diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_FLASH.lcf b/Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_FLASH.lcf new file mode 100644 index 000000000..a7cacb026 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_FLASH.lcf @@ -0,0 +1,140 @@ +# Sample Linker Command File for CodeWarrior for ColdFire + +KEEP_SECTION {.vectortable} + +# Memory ranges + +MEMORY { + vectorrom (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + cfmprotrom (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000020 + code (RX) : ORIGIN = 0x00000500, LENGTH = 0x0001FB00 + vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000400 + userram (RWX) : ORIGIN = 0x20000400, LENGTH = 0x00003C00 +} + +SECTIONS { + +# Heap and Stack sizes definition + ___heap_size = 0x1000; + ___stack_size = 0x1000; + + + +# MCF52221 Derivative Memory map definitions from linker command files: +# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker +# symbols must be defined in the linker command file. + +# Memory Mapped Registers (IPSBAR= 0x40000000) + ___IPSBAR = 0x40000000; + +# 16 Kbytes Internal SRAM + ___RAMBAR = 0x20000000; + ___RAMBAR_SIZE = 0x00004000; + +# 128 KByte Internal Flash Memory + ___FLASHBAR = 0x00000000; + ___FLASHBAR_SIZE = 0x00020000; + + ___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4; + + .userram : {} > userram + .code : {} > code + .vectorram : {} > vectorram + + .vectors : + { + exceptions.c(.vectortable) + . = ALIGN (0x4); + } > vectorrom + + .cfmprotect : + { + *(.cfmconfig) + . = ALIGN (0x4); + } > cfmprotrom + + .text : + { + *(.text) + . = ALIGN (0x4); + *(.rodata) + . = ALIGN (0x4); + ___ROM_AT = .; + ___DATA_ROM = .; + } >> code + + .data : AT(___ROM_AT) + { + ___DATA_RAM = .; + . = ALIGN(0x4); + *(.exception) + . = ALIGN(0x4); + __exception_table_start__ = .; + EXCEPTION + __exception_table_end__ = .; + + ___sinit__ = .; + STATICINIT + __START_DATA = .; + + *(.data) + . = ALIGN (0x4); + __END_DATA = .; + + __START_SDATA = .; + *(.sdata) + . = ALIGN (0x4); + __END_SDATA = .; + + ___DATA_END = .; + __SDA_BASE = .; + . = ALIGN (0x4); + } >> userram + + .bss : + { + ___BSS_START = .; + __START_SBSS = .; + *(.sbss) + . = ALIGN (0x4); + *(SCOMMON) + __END_SBSS = .; + + __START_BSS = .; + *(.bss) + . = ALIGN (0x4); + *(COMMON) + __END_BSS = .; + ___BSS_END = .; + + . = ALIGN(0x4); + } >> userram + + .custom : + { + ___HEAP_START = .; + ___heap_addr = ___HEAP_START; + ___HEAP_END = ___HEAP_START + ___heap_size; + ___SP_END = ___HEAP_END; + ___SP_INIT = ___SP_END + ___stack_size; + + . = ALIGN (0x4); + } >> userram + + ___VECTOR_RAM = ADDR(.vectorram); + + __SP_INIT = ___SP_INIT; + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + WRITEW(___ROM_AT); + WRITEW(ADDR(.data)); + WRITEW(SIZEOF(.data)); + WRITEW(0); + WRITEW(0); + WRITEW(0); + } + +} \ No newline at end of file diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_RAM.lcf b/Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_RAM.lcf new file mode 100644 index 000000000..b6ecc52fa --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_RAM.lcf @@ -0,0 +1,133 @@ +# Sample Linker Command File for CodeWarrior for ColdFire + +KEEP_SECTION {.vectortable} + +# Memory ranges + +MEMORY { + vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000500 + code (RX) : ORIGIN = 0x20000500, LENGTH = 0x00002B00 + userram (RWX) : ORIGIN = 0x20003000, LENGTH = 0x00001000 +} + +SECTIONS { + +# Heap and Stack sizes definition + ___heap_size = 0x400; + ___stack_size = 0x400; + + + +# MCF52221 Derivative Memory map definitions from linker command files: +# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker +# symbols must be defined in the linker command file. + +# Memory Mapped Registers (IPSBAR= 0x40000000) + ___IPSBAR = 0x40000000; + +# 16 Kbytes Internal SRAM + ___RAMBAR = 0x20000000; + ___RAMBAR_SIZE = 0x00004000; + +# 128 KByte Internal Flash Memory + ___FLASHBAR = 0x00000000; + ___FLASHBAR_SIZE = 0x00020000; + + ___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4; + + .userram : {} > userram + .code : {} > code + .vectorram : {} > vectorram + + .vectors : + { + exceptions.c(.vectortable) + . = ALIGN (0x4); + } >> code + + + .text : + { + *(.text) + . = ALIGN (0x4); + *(.rodata) + . = ALIGN (0x4); + ___ROM_AT = .; + ___DATA_ROM = .; + } >> code + + .data : AT(___ROM_AT) + { + ___DATA_RAM = .; + . = ALIGN(0x4); + *(.exception) + . = ALIGN(0x4); + __exception_table_start__ = .; + EXCEPTION + __exception_table_end__ = .; + + ___sinit__ = .; + STATICINIT + __START_DATA = .; + + *(.data) + . = ALIGN (0x4); + __END_DATA = .; + + __START_SDATA = .; + *(.sdata) + . = ALIGN (0x4); + __END_SDATA = .; + + ___DATA_END = .; + __SDA_BASE = .; + . = ALIGN (0x4); + } >> userram + + .bss : + { + ___BSS_START = .; + __START_SBSS = .; + *(.sbss) + . = ALIGN (0x4); + *(SCOMMON) + __END_SBSS = .; + + __START_BSS = .; + *(.bss) + . = ALIGN (0x4); + *(COMMON) + __END_BSS = .; + ___BSS_END = .; + + . = ALIGN(0x4); + } >> userram + + .custom : + { + ___HEAP_START = .; + ___heap_addr = ___HEAP_START; + ___HEAP_END = ___HEAP_START + ___heap_size; + ___SP_END = ___HEAP_END; + ___SP_INIT = ___SP_END + ___stack_size; + + . = ALIGN (0x4); + } >> userram + + ___VECTOR_RAM = ADDR(.vectorram); + + __SP_INIT = ___SP_INIT; + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + WRITEW(___ROM_AT); + WRITEW(ADDR(.data)); + WRITEW(SIZEOF(.data)); + WRITEW(0); + WRITEW(0); + WRITEW(0); + } + +} \ No newline at end of file diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/readme.txt b/Demo/ColdFire_MCF52221_CodeWarrior/readme.txt new file mode 100644 index 000000000..09e133b70 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/readme.txt @@ -0,0 +1,160 @@ +//------------------------------------------------------------------------ +// Readme.txt +//------------------------------------------------------------------------ +This project is configure to get you up and running quickly using +CodeWarrior with the Freescale MCF52221 board. + +This project provides full support for the selected board. +The created project provides Standard IO Support through console and terminal window. + +Sample code for the following language: +- C + + +//------------------------------------------------------------------------ +// Memory Maps +//------------------------------------------------------------------------ +The Hardware has the following memory map: + +# MCF52221 Derivative Memory map definitions from linker command files: +# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker +# symbols must be defined in the linker command file. + +# Memory Mapped Registers (IPSBAR= 0x40000000) + ___IPSBAR = 0x40000000; + +# 16 Kbytes Internal SRAM + ___RAMBAR = 0x20000000; + ___RAMBAR_SIZE = 0x00004000; + +# 128 KByte Internal Flash Memory + ___FLASHBAR = 0x00000000; + ___FLASHBAR_SIZE = 0x00020000; + + + +//------------------------------------------------------------------------ +// Project Structure +//------------------------------------------------------------------------ +The project generated contains various files/groups: +- readme.txt: information for this project +- Sources: application source codes, user customizable startup + code, uart library, exception table +- Includes: derivative and board header files, ... +- Libs: runtime and libs +- Project Settings: linker command files for the different build + targets, the initialization and memory configuration files for + the hardware debugging, the common startup code, etc... + +//------------------------------------------------------------------------ +// Build Targets +//------------------------------------------------------------------------ +- CONSOLE_INTERNAL_RAM: +This project target is setup to load and debug code from internal RAM. +It should be used during your application development. +The application outputs to the CodeWarrior's console window. + +- INTERNAL_RAM: +This project target is setup to load and debug code from internal RAM. +It should be used during your application development. +This is the very basic project that outputs to the UART. +You needs to connect a Terminal Program to see the output. + +- INTERNAL_FLASH: +This project target is setup to load and debug code in Internal FLASH. +This is the very basic project that outputs to the UART. User needs +to connect the terminal to see the output. + + + +=================================================================== +WARNING regarding debugging new project wizard code with CCS-SIM +=================================================================== +The CCS-SIM is an instruction set simulator, it does not implement +any peripherals. +The new project generated by the wizard are using startup code +performing some hardware peripheral initializations. +When debugging with the CCS-SIM it might happen that the simulation +stuck on loop using non implemented peripheral register flag as +condition (PLL initialization as example). +In this case, you should either: +- move the PC to next statement +- use a skip point +- define a simulator specific macro which used when define allos you +to comment out the unwanted code in order to debug with CCS-SIM + + +=================================================================== +WARNING regarding code located in RAM +=================================================================== +Many possible ColdFire target processors have an external bus, so +you can use large external RAM devices for debugging applications +during development. But some processors do not have an external +bus, so you must accommodate applications in on-chip memory. +Although this on-chip RAM accommodates this CodeWarrior project, +it probably is too small for full development of your application. +Accordingly, for a processor without external bus, you should locate +your applications in flash memory. + +//------------------------------------------------------------------------ +// Flashing the code +//------------------------------------------------------------------------ +1. Select the appropriate project target and build it +2. Make sure the correct remote connection is selected in the Remote + Connection debugger panel +3. In the CodeWarrior IDE menu, select Project > Set Default Project + and select your project +4. In the CodeWarrior IDE menu, select Project > Set Default Target + and select the project target that has the code you want to flash +5. In the CodeWarrior IDE menu, select Tools > Flash Programmer +6. Go to the flash programmer Target Configuration panel, click Load + Settings +7. Browse to the \cfg sub folder and + select the flash settings xml file matching your build target +8. Check that Use Custom Settings checkbox is not selected +9. Go to the Erase/Blank Check panel, select the All Sectors option and + click Erase +10. Go to Program/Verify panel, click Program +11. Your code should now be flashed + +//------------------------------------------------------------------------ +// Terminal Settings +//------------------------------------------------------------------------ +In case the UART is supported, the terminal should be setup with: +- 19200 bauds, +- 8 data bits, +- no parity, +- 1 stop bit, +- no flow control. + +Please check this file in the project. + +//------------------------------------------------------------------------ +// Getting Started +//------------------------------------------------------------------------ +To build/debug your project, use the CodeWarrior IDE menu Project > Debug +or press F5. This will launch the debugger. Press again F5 in the +debugger (or the CodeWarrior IDE menu Project > Run) to start the +application. The CodeWarrior IDE menu Project > Break stops the +application. + +//------------------------------------------------------------------------ +// Adding your own code +//------------------------------------------------------------------------ +Once everything is working as expected, you can begin adding your own code +to the project. Keep in mind that we provide this as an example of how to +get up and running quickly with CodeWarrior. There are certainly other +ways to handle interrupts and set up your linker command file. Feel free +to modify any of the source files provided. + +//------------------------------------------------------------------------ +// Additional documentation +//------------------------------------------------------------------------ +Read the online documentation provided. In CodeWarrior IDE menu, select +Help > CodeWarrior Help. + +//------------------------------------------------------------------------ +// Contacting Freescale +//------------------------------------------------------------------------ +For bug reports, technical questions, and suggestions, please use the +forms installed in the Release_Notes folder. diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOSConfig.h b/Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOSConfig.h new file mode 100644 index 000000000..876be9ae5 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOSConfig.h @@ -0,0 +1,142 @@ +/* + FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "support_common.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 80000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 100 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 160 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 0 ) ) /* The heap size is worked out from the linker script, so this constant is not used. */ +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_COUNTING_SEMAPHORES 0 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 + +#define configYIELD_INTERRUPT_VECTOR 16UL +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +void vApplicationSetupInterrupts( void ); + +/* Ethernet configuration. */ +#define configMAC_0 0x00 +#define configMAC_1 0x04 +#define configMAC_2 0x9F +#define configMAC_3 0x00 +#define configMAC_4 0xAB +#define configMAC_5 0x2B + +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 11 + +#define configGW_ADDR0 172 +#define configGW_ADDR1 25 +#define configGW_ADDR2 218 +#define configGW_ADDR3 3 + +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#define configNUM_FEC_TX_BUFFERS 2 +#define configNUM_FEC_RX_BUFFERS 4 +#define configFEC_BUFFER_SIZE 1520 +#define configUSE_PROMISCUOUS_MODE 0 +#define configETHERNET_INPUT_TASK_STACK_SIZE ( 320 ) +#define configETHERNET_INPUT_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) + +#define configPHY_ADDRESS 1 + +#if ( configFEC_BUFFER_SIZE & 0x0F ) != 0 + #error configFEC_BUFFER_SIZE must be a multiple of 16. +#endif + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOS_Tick_Setup.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOS_Tick_Setup.c new file mode 100644 index 000000000..b9eb5eb76 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOS_Tick_Setup.c @@ -0,0 +1,137 @@ +/* + FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#include "FreeRTOS.h" +#include "task.h" + +__declspec(interrupt:0) void vPIT0InterruptHandler( void ); +extern unsigned portLONG __VECTOR_RAM[]; + +/* Constants used to configure the interrupts. */ +#define portPRESCALE_VALUE 64 +#define portPRESCALE_REG_SETTING ( 5 << 8 ) +#define portPIT_INTERRUPT_ENABLED ( 0x08 ) +#define configPIT0_INTERRUPT_VECTOR ( 55 ) + +/* + * FreeRTOS.org requires two interrupts - a tick interrupt generated from a + * timer source, and a spare interrupt vector used for context switching. + * The configuration below uses PIT0 for the former, and vector 63 for the + * latter. **IF YOUR APPLICATION HAS BOTH OF THESE INTERRUPTS FREE THEN YOU DO + * NOT NEED TO CHANGE ANY OF THIS CODE** - otherwise instructions are provided + * here for using alternative interrupt sources. + * + * To change the tick interrupt source: + * + * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever + * peripheral is to be used to generate the tick interrupt. + * + * 2) Change the name of the function __cs3_isr_interrupt_119() defined within + * this file to be correct for the interrupt vector used by the timer peripheral. + * The name of the function should contain the vector number, so by default vector + * number 119 is being used. + * + * 3) Make sure the tick interrupt is cleared within the interrupt handler function. + * Currently __cs3_isr_interrupt_119() clears the PIT0 interrupt. + * + * To change the spare interrupt source: + * + * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever + * interrupt vector is to be used. Make sure you use a spare interrupt on interrupt + * controller 0, otherwise the register used to request context switches will also + * require modification. + * + * 2) Change the definition of configYIELD_INTERRUPT_VECTOR within FreeRTOSConfig.h + * to be correct for your chosen interrupt vector. + * + * 3) Change the name of the function __cs3_isr_interrupt_127() within portasm.S + * to be correct for whichever vector number is being used. By default interrupt + * controller 0 number 63 is used, which corresponds to vector number 127. + */ +void vApplicationSetupInterrupts( void ) +{ +const unsigned portSHORT usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ ); + + /* Configure interrupt priority and level and unmask interrupt for PIT0. */ + MCF_INTC0_ICR55 = ( 1 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) ); + MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 ); + + /* Do the same for vector 63 (interrupt controller 0. I don't think the + write to MCF_INTC0_IMRH is actually required here but is included for + completeness. */ + MCF_INTC0_ICR16 = ( 0 | configKERNEL_INTERRUPT_PRIORITY << 3 ); + MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK16 | 0x01 ); + + /* Configure PIT0 to generate the RTOS tick. */ + MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF; + MCF_PIT0_PCSR = ( portPRESCALE_REG_SETTING | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN ); + MCF_PIT0_PMR = usCompareMatchValue; +} +/*-----------------------------------------------------------*/ + +__declspec(interrupt:0) void vPIT0InterruptHandler( void ) +{ +unsigned portLONG ulSavedInterruptMask; + + /* Clear the PIT0 interrupt. */ + MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF; + + /* Increment the RTOS tick. */ + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + vTaskIncrementTick(); + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); + + /* If we are using the pre-emptive scheduler then also request a + context switch as incrementing the tick could have unblocked a task. */ + #if configUSE_PREEMPTION == 1 + { + taskYIELD(); + } + #endif +} diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.c new file mode 100644 index 000000000..40046e943 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.c @@ -0,0 +1,86 @@ +/* + * File: mcf52221_sysinit.c + * Purpose: Power-on Reset configuration of the MCF52221. + * + * Notes: + * + */ +#include "support_common.h" +#include "exceptions.h" + + + +/********************************************************************/ +static void pll_init(void) +{ + + MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 48MHz / 6 = 8MHz + + /* The PLL pre-divider affects this!!! + * Multiply 8Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz + */ + + MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ; + + while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK)) + { + } +} +/********************************************************************/ +static void scm_init(void) +{ + /* + * Enable on-chip modules to access internal SRAM + */ + MCF_SCM_RAMBAR = (0 + | MCF_SCM_RAMBAR_BA(RAMBAR_ADDRESS) + | MCF_SCM_RAMBAR_BDE); +} + +/********************************************************************/ + + /* + * Out of reset, the low-level assembly code calls this routine to + * initialize the mcf5206e for this board. A temporary stack has been + * setup in the internal SRAM, and the stack pointer will be changed + * to point to DRAM once this routine returns. + */ +void __initialize_hardware(void) +{ + /******************************************************* + * Out of reset, the low-level assembly code calls this + * routine to initialize the MCF52221 modules for the + * M522223EVB board. + ********************************************************/ + + + asm + { + /* Initialize IPSBAR */ + move.l #__IPSBAR,d0 + andi.l #0xC0000000,d0 // need to mask + add.l #0x1,d0 + move.l d0,0x40000000 + + + + /* Initialize FLASHBAR */ + move.l #__FLASHBAR,d0 + andi.l #0xFFF80000,d0 // need to mask + add.l #0x61,d0 + movec d0,FLASHBAR + + } + + + /* Set real time clock freq */ + MCF_CLOCK_RTCDR = 48000000; + + pll_init(); + scm_init(); + + initialize_exceptions(); +} + + + diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.h b/Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.h new file mode 100644 index 000000000..43fb84a7b --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.h @@ -0,0 +1,55 @@ +/* + * File: mcf52221demo_sysinit.h + * Purpose: Power-on Reset configuration of the MCF52221. + * + * Notes: + * + */ + +#ifndef __MCF52221DEMO_SYSINIT_H__ +#define __MCF52221DEMO_SYSINIT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + + +#if ENABLE_UART_SUPPORT==1 + +#define TERMINAL_PORT 0 +#define TERMINAL_BAUD kBaud19200 + +#endif /* ENABLE_UART_SUPPORT==1 */ + +#define SYSTEM_CLOCK_KHZ 80000 /* system bus frequency in kHz */ + + +/********************************************************************/ +/* __initialize_hardware Startup code routine + * + * __initialize_hardware is called by the startup code right after reset, + * with interrupt disabled and SP pre-set to a valid memory area. + * Here you should initialize memory and some peripherics; + * at this point global variables are not initialized yet. + * The startup code will initialize SP on return of this function. + */ +void __initialize_hardware(void); + +/********************************************************************/ +/* __initialize_system Startup code routine + * + * __initialize_system is called by the startup code when all languages + * specific initialization are done to allow additional hardware setup. + */ +void __initialize_system(void); + + + +#ifdef __cplusplus +} +#endif + +#endif /* __MCF52221DEMO_SYSINIT_H__ */ + + diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/ParTest/ParTest.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/ParTest/ParTest.c new file mode 100644 index 000000000..b775273fa --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/ParTest/ParTest.c @@ -0,0 +1,133 @@ +/* + FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + Changes from V2.5.2 + + + All LED's are turned off to start. +*/ + + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#define partstNUM_LEDs 4 + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Enable signals as GPIO */ + MCF_GPIO_PTCPAR = 0 + | MCF_GPIO_PTCPAR_DTIN3_GPIO + | MCF_GPIO_PTCPAR_DTIN2_GPIO + | MCF_GPIO_PTCPAR_DTIN1_GPIO + | MCF_GPIO_PTCPAR_DTIN0_GPIO; + + /* Enable signals as digital outputs */ + MCF_GPIO_DDRTC = 0 + | MCF_GPIO_DDRTC_DDRTC3 + | MCF_GPIO_DDRTC_DDRTC2 + | MCF_GPIO_DDRTC_DDRTC1 + | MCF_GPIO_DDRTC_DDRTC0; + + MCF_GPIO_PORTTC = 0x00; // TURN LEDS OFF +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portBASE_TYPE uxLEDMask; + + if( uxLED < partstNUM_LEDs ) + { + uxLEDMask = 1UL << uxLED; + + taskENTER_CRITICAL(); + { + if( xValue ) + { + MCF_GPIO_PORTTC |= uxLEDMask; + } + else + { + MCF_GPIO_PORTTC &= ~uxLEDMask; + } + } + taskEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portBASE_TYPE uxLEDMask; + + if( uxLED < partstNUM_LEDs ) + { + uxLEDMask = 1UL << uxLED; + + taskENTER_CRITICAL(); + { + if( MCF_GPIO_PORTTC & uxLEDMask ) + { + MCF_GPIO_PORTTC &= ~uxLEDMask; + } + else + { + MCF_GPIO_PORTTC |= uxLEDMask; + } + } + taskEXIT_CRITICAL(); + } +} + diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/cfm.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/cfm.c new file mode 100644 index 000000000..b1cbcb5ec --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/cfm.c @@ -0,0 +1,21 @@ + +/* CFM init */ + +#define KEY_UPPER 0 +#define KEY_LOWER 0 +#define CFMPROT 0 +#define CFMSACC 0 +#define CFMDACC 0 +#define CFMSEC 0 + +#pragma define_section cfmconfig ".cfmconfig" far_absolute R +#pragma explicit_zero_data on + +__declspec(cfmconfig) unsigned long _cfm[6] = { + KEY_UPPER, /* 0x00000400 */ + KEY_LOWER, /* 0x00000404 */ + CFMPROT, /* 0x00000408 */ + CFMSACC, /* 0x0000040C */ + CFMDACC, /* 0x00000410 */ + CFMSEC, /* 0x00000414 */ +}; diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.c new file mode 100644 index 000000000..a6a41edf2 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.c @@ -0,0 +1,626 @@ +/* + * File: exceptions.c + * Purpose: Generic exception handling for ColdFire processors + * + */ +#include "exceptions.h" +#include "startcf.h" +#include "support_common.h" +#include + +#define REGISTER_ABI __REGABI__ + +extern __declspec(system) unsigned long __VECTOR_RAM[]; +#define VECTOR_RAM_ADDRESS (uint32)__VECTOR_RAM + +/***********************************************************************/ +/* + * Set NO_PRINTF to 0 in order the exceptions.c interrupt handler + * to output messages to the standard io. + * + */ +#define NO_PRINTF 1 + +#if NO_PRINTF +#define VECTORDISPLAY(MESSAGE) asm { nop; }; +#define VECTORDISPLAY2(MESSAGE,MESSAGE2) asm { nop; }; +#define VECTORDISPLAY3(MESSAGE,MESSAGE2,MESSAGE3) asm { nop; }; +#else +#include +#define VECTORDISPLAY(MESSAGE1) printf(MESSAGE1); +#define VECTORDISPLAY2(MESSAGE1,MESSAGE2) printf(MESSAGE1,MESSAGE2); +#define VECTORDISPLAY3(MESSAGE1,MESSAGE2,MESSAGE3) printf(MESSAGE1,MESSAGE2,MESSAGE3); +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +extern unsigned long far _SP_INIT[]; + +/***********************************************************************/ +/* + * Handling of the TRK ColdFire libs (printf support in Debugger Terminal) + * + * To enable this support (setup by default in CONSOLE_RAM build target + * if available): + * - Set CONSOLE_IO_SUPPORT to 1 in this file; this will enable + * TrapHandler_printf for the trap #14 exception. + * (this is set by default to 1 in the ColdFire Pre-Processor panel for + * the CONSOLE_RAM build target) + * + * - Make sure the file: + * {Compiler}ColdFire_Support\msl\MSL_C\MSL_ColdFire\Src\console_io_cf.c + * is referenced from your project. + * + * - Make sure that in the CF Exceptions panel the check box + * "46 TRAP #14 for Console I/O", in the "User Application Exceptions" + * area is set. + * + */ +#ifndef CONSOLE_IO_SUPPORT +#define CONSOLE_IO_SUPPORT 0 +#endif + +#if CONSOLE_IO_SUPPORT +asm void TrapHandler_printf(void) { + HALT + RTE +} +#endif + +/***********************************************************************/ +/* + * This is the handler for all exceptions which are not common to all + * ColdFire Chips. + * + * Called by mcf_exception_handler + * + */ +void derivative_interrupt(unsigned long vector) +{ + if (vector < 64 || vector > 192) { + VECTORDISPLAY2("User Defined Vector #%d\n",vector); + } +} + +/*********************************************************************** + * + * This is the exception handler for all exceptions common to all + * chips ColdFire. Most exceptions do nothing, but some of the more + * important ones are handled to some extent. + * + * Called by asm_exception_handler + * + * The ColdFire family of processors has a simplified exception stack + * frame that looks like the following: + * + * 3322222222221111 111111 + * 1098765432109876 5432109876543210 + * 8 +----------------+----------------+ + * | Program Counter | + * 4 +----------------+----------------+ + * |FS/Fmt/Vector/FS| SR | + * SP --> 0 +----------------+----------------+ + * + * The stack self-aligns to a 4-byte boundary at an exception, with + * the FS/Fmt/Vector/FS field indicating the size of the adjustment + * (SP += 0,1,2,3 bytes). + * 31 28 27 26 25 18 17 16 15 0 + * 4 +---------------------------------------+------------------------------------+ + * | Format | FS[3..2] | Vector | FS[1..0] | SR | + * SP --> 0 +---------------------------------------+------------------------------------+ + */ +#define MCF5XXX_RD_SF_FORMAT(PTR) \ + ((*((unsigned short *)(PTR)) >> 12) & 0x00FF) + +#define MCF5XXX_RD_SF_VECTOR(PTR) \ + ((*((unsigned short *)(PTR)) >> 2) & 0x00FF) + +#define MCF5XXX_RD_SF_FS(PTR) \ + ( ((*((unsigned short *)(PTR)) & 0x0C00) >> 8) | (*((unsigned short *)(PTR)) & 0x0003) ) + +#define MCF5XXX_SF_SR(PTR) *(((unsigned short *)(PTR))+1) + +#define MCF5XXX_SF_PC(PTR) *((unsigned long *)(PTR)+1) + +#define MCF5XXX_EXCEPTFMT "%s -- PC = %#08X\n" + + +void mcf_exception_handler(void *framepointer) +{ + volatile unsigned long exceptionStackFrame = (*(unsigned long *)(framepointer)); + volatile unsigned short stackFrameSR = MCF5XXX_SF_SR(framepointer); + volatile unsigned short stackFrameWord = (*(unsigned short *)(framepointer)); + volatile unsigned long stackFrameFormat = (unsigned long)MCF5XXX_RD_SF_FORMAT(&stackFrameWord); + volatile unsigned long stackFrameFS = (unsigned long)MCF5XXX_RD_SF_FS(&stackFrameWord); + volatile unsigned long stackFrameVector = (unsigned long)MCF5XXX_RD_SF_VECTOR(&stackFrameWord); + volatile unsigned long stackFramePC = MCF5XXX_SF_PC(framepointer); + + switch (stackFrameFormat) + { + case 4: + case 5: + case 6: + case 7: + break; + default: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT,"Illegal stack type", stackFramePC); + break; + } + + switch (stackFrameVector) + { + case 2: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Access Error", stackFramePC); + switch (stackFrameFS) + { + case 4: + VECTORDISPLAY("Error on instruction fetch\n"); + break; + case 8: + VECTORDISPLAY("Error on operand write\n"); + break; + case 9: + VECTORDISPLAY("Attempted write to write-protected space\n"); + break; + case 12: + VECTORDISPLAY("Error on operand read\n"); + break; + default: + VECTORDISPLAY("Reserved Fault Status Encoding\n"); + break; + } + break; + case 3: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Address Error", stackFramePC); + switch (stackFrameFS) + { + case 4: + VECTORDISPLAY("Error on instruction fetch\n"); + break; + case 8: + VECTORDISPLAY("Error on operand write\n"); + break; + case 9: + VECTORDISPLAY("Attempted write to write-protected space\n"); + break; + case 12: + VECTORDISPLAY("Error on operand read\n"); + break; + default: + VECTORDISPLAY("Reserved Fault Status Encoding\n"); + break; + } + break; + case 4: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Illegal instruction", stackFramePC); + break; + case 8: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Privilege violation", stackFramePC); + break; + case 9: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Trace Exception", stackFramePC); + break; + case 10: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Unimplemented A-Line Instruction", stackFramePC); + break; + case 11: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Unimplemented F-Line Instruction", stackFramePC); + break; + case 12: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Debug Interrupt", stackFramePC); + break; + case 14: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Format Error", stackFramePC); + break; + case 15: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Unitialized Interrupt", stackFramePC); + break; + case 24: + VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Spurious Interrupt", stackFramePC); + break; + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + VECTORDISPLAY2("Autovector interrupt level %d\n", stackFrameVector - 24); + break; + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + VECTORDISPLAY2("TRAP #%d\n", stackFrameVector - 32); + break; + case 5: + case 6: + case 7: + case 13: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + VECTORDISPLAY2("Reserved: #%d\n", stackFrameVector); + break; + default: + derivative_interrupt(stackFrameVector); + break; + } +} + +#if REGISTER_ABI +asm void asm_exception_handler(void) +{ + link a6,#0 + lea -20(sp), sp + movem.l d0-d2/a0-a1, (sp) + lea 24(sp),a0 /* A0 point to exception stack frame on the stack */ + jsr mcf_exception_handler + movem.l (sp), d0-d2/a0-a1 + lea 20(sp), sp + unlk a6 + rte +} +#else +asm void asm_exception_handler(void) +{ + link a6,#0 + lea -20(sp), sp + movem.l d0-d2/a0-a1, (sp) + pea 24(sp) /* push exception frame address */ + jsr mcf_exception_handler + movem.l 4(sp), d0-d2/a0-a1 + lea 24(sp), sp + unlk a6 + rte +} +#endif + +typedef void (* vectorTableEntryType)(void); + +#pragma define_section vectortable ".vectortable" far_absolute R + +/* CF have 255 vector + SP_INIT in the vector table (256 entries) +*/ +__declspec(vectortable) vectorTableEntryType _vect[256] = { /* Interrupt vector table */ + (vectorTableEntryType)__SP_AFTER_RESET, /* 0 (0x000) Initial supervisor SP */ + _startup, /* 1 (0x004) Initial PC */ + asm_exception_handler, /* 2 (0x008) Access Error */ + asm_exception_handler, /* 3 (0x00C) Address Error */ + asm_exception_handler, /* 4 (0x010) Illegal Instruction */ + asm_exception_handler, /* 5 (0x014) Reserved */ + asm_exception_handler, /* 6 (0x018) Reserved */ + asm_exception_handler, /* 7 (0x01C) Reserved */ + asm_exception_handler, /* 8 (0x020) Privilege Violation */ + asm_exception_handler, /* 9 (0x024) Trace */ + asm_exception_handler, /* 10 (0x028) Unimplemented A-Line */ + asm_exception_handler, /* 11 (0x02C) Unimplemented F-Line */ + asm_exception_handler, /* 12 (0x030) Debug Interrupt */ + asm_exception_handler, /* 13 (0x034) Reserved */ + asm_exception_handler, /* 14 (0x038) Format Error */ + asm_exception_handler, /* 15 (0x03C) Unitialized Int */ + asm_exception_handler, /* 16 (0x040) Reserved */ + asm_exception_handler, /* 17 (0x044) Reserved */ + asm_exception_handler, /* 18 (0x048) Reserved */ + asm_exception_handler, /* 19 (0x04C) Reserved */ + asm_exception_handler, /* 20 (0x050) Reserved */ + asm_exception_handler, /* 21 (0x054) Reserved */ + asm_exception_handler, /* 22 (0x058) Reserved */ + asm_exception_handler, /* 23 (0x05C) Reserved */ + asm_exception_handler, /* 24 (0x060) Spurious Interrupt */ + asm_exception_handler, /* 25 (0x064) Autovector Level 1 */ + asm_exception_handler, /* 26 (0x068) Autovector Level 2 */ + asm_exception_handler, /* 27 (0x06C) Autovector Level 3 */ + asm_exception_handler, /* 28 (0x070) Autovector Level 4 */ + asm_exception_handler, /* 29 (0x074) Autovector Level 5 */ + asm_exception_handler, /* 30 (0x078) Autovector Level 6 */ + asm_exception_handler, /* 31 (0x07C) Autovector Level 7 */ + asm_exception_handler, /* 32 (0x080) TRAP #0 */ + asm_exception_handler, /* 33 (0x084) TRAP #1 */ + asm_exception_handler, /* 34 (0x088) TRAP #2 */ + asm_exception_handler, /* 35 (0x08C) TRAP #3 */ + asm_exception_handler, /* 36 (0x090) TRAP #4 */ + asm_exception_handler, /* 37 (0x094) TRAP #5 */ + asm_exception_handler, /* 38 (0x098) TRAP #6 */ + asm_exception_handler, /* 39 (0x09C) TRAP #7 */ + asm_exception_handler, /* 40 (0x0A0) TRAP #8 */ + asm_exception_handler, /* 41 (0x0A4) TRAP #9 */ + asm_exception_handler, /* 42 (0x0A8) TRAP #10 */ + asm_exception_handler, /* 43 (0x0AC) TRAP #11 */ + asm_exception_handler, /* 44 (0x0B0) TRAP #12 */ + asm_exception_handler, /* 45 (0x0B4) TRAP #13 */ +#if CONSOLE_IO_SUPPORT + TrapHandler_printf, /* 46 (0x0B8) TRAP #14 */ +#else + asm_exception_handler, /* 46 (0x0B8) TRAP #14 */ +#endif + asm_exception_handler, /* 47 (0x0BC) TRAP #15 */ + asm_exception_handler, /* 48 (0x0C0) Reserved */ + asm_exception_handler, /* 49 (0x0C4) Reserved */ + asm_exception_handler, /* 50 (0x0C8) Reserved */ + asm_exception_handler, /* 51 (0x0CC) Reserved */ + asm_exception_handler, /* 52 (0x0D0) Reserved */ + asm_exception_handler, /* 53 (0x0D4) Reserved */ + asm_exception_handler, /* 54 (0x0D8) Reserved */ + asm_exception_handler, /* 55 (0x0DC) Reserved */ + asm_exception_handler, /* 56 (0x0E0) Reserved */ + asm_exception_handler, /* 57 (0x0E4) Reserved */ + asm_exception_handler, /* 58 (0x0E8) Reserved */ + asm_exception_handler, /* 59 (0x0EC) Reserved */ + asm_exception_handler, /* 60 (0x0F0) Reserved */ + asm_exception_handler, /* 61 (0x0F4) Reserved */ + asm_exception_handler, /* 62 (0x0F8) Reserved */ + asm_exception_handler, /* 63 (0x0FC) Reserved */ + asm_exception_handler, /* 64 (0x100) Device-specific interrupts */ + asm_exception_handler, /* 65 (0x104) Device-specific interrupts */ + asm_exception_handler, /* 66 (0x108) Device-specific interrupts */ + asm_exception_handler, /* 67 (0x10C) Device-specific interrupts */ + asm_exception_handler, /* 68 (0x110) Device-specific interrupts */ + asm_exception_handler, /* 69 (0x114) Device-specific interrupts */ + asm_exception_handler, /* 70 (0x118) Device-specific interrupts */ + asm_exception_handler, /* 71 (0x11C) Device-specific interrupts */ + asm_exception_handler, /* 72 (0x120) Device-specific interrupts */ + asm_exception_handler, /* 73 (0x124) Device-specific interrupts */ + asm_exception_handler, /* 74 (0x128) Device-specific interrupts */ + asm_exception_handler, /* 75 (0x12C) Device-specific interrupts */ + asm_exception_handler, /* 76 (0x130) Device-specific interrupts */ + asm_exception_handler, /* 77 (0x134) Device-specific interrupts */ + asm_exception_handler, /* 78 (0x138) Device-specific interrupts */ + asm_exception_handler, /* 79 (0x13C) Device-specific interrupts */ + asm_exception_handler, /* 80 (0x140) Device-specific interrupts */ + asm_exception_handler, /* 81 (0x144) Device-specific interrupts */ + asm_exception_handler, /* 82 (0x148) Device-specific interrupts */ + asm_exception_handler, /* 83 (0x14C) Device-specific interrupts */ + asm_exception_handler, /* 84 (0x150) Device-specific interrupts */ + asm_exception_handler, /* 85 (0x154) Device-specific interrupts */ + asm_exception_handler, /* 86 (0x158) Device-specific interrupts */ + asm_exception_handler, /* 87 (0x15C) Device-specific interrupts */ + asm_exception_handler, /* 88 (0x160) Device-specific interrupts */ + asm_exception_handler, /* 89 (0x164) Device-specific interrupts */ + asm_exception_handler, /* 90 (0x168) Device-specific interrupts */ + asm_exception_handler, /* 91 (0x16C) Device-specific interrupts */ + asm_exception_handler, /* 92 (0x170) Device-specific interrupts */ + asm_exception_handler, /* 93 (0x174) Device-specific interrupts */ + asm_exception_handler, /* 94 (0x178) Device-specific interrupts */ + asm_exception_handler, /* 95 (0x17C) Device-specific interrupts */ + asm_exception_handler, /* 96 (0x180) Level 1 software interrupt */ + asm_exception_handler, /* 97 (0x184) Level 2 software interrupt */ + asm_exception_handler, /* 98 (0x188) Level 3 software interrupt */ + asm_exception_handler, /* 99 (0x18C) Level 4 software interrupt */ + asm_exception_handler, /* 100 (0x190) Level 5 software interrupt */ + asm_exception_handler, /* 101 (0x194) Level 6 software interrupt */ + asm_exception_handler, /* 102 (0x198) Level 7 software interrupt */ + asm_exception_handler, /* 103 (0x19C) Reserved */ + asm_exception_handler, /* 104 (0x1A0) Reserved */ + asm_exception_handler, /* 105 (0x1A4) Reserved */ + asm_exception_handler, /* 106 (0x1A8) Reserved */ + asm_exception_handler, /* 107 (0x___) Reserved */ + asm_exception_handler, /* 108 (0x___) Reserved */ + asm_exception_handler, /* 109 (0x___) Reserved */ + asm_exception_handler, /* 110 (0x___) Reserved */ + asm_exception_handler, /* 111 (0x___) Reserved */ + asm_exception_handler, /* 112 (0x___) Reserved */ + asm_exception_handler, /* 113 (0x___) Reserved */ + asm_exception_handler, /* 114 (0x___) Reserved */ + asm_exception_handler, /* 115 (0x___) Reserved */ + asm_exception_handler, /* 116 (0x___) Reserved */ + asm_exception_handler, /* 117 (0x___) Reserved */ + asm_exception_handler, /* 118 (0x___) Reserved */ + asm_exception_handler, /* 119 (0x___) Reserved */ + asm_exception_handler, /* 120 (0x___) Reserved */ + asm_exception_handler, /* 121 (0x___) Reserved */ + asm_exception_handler, /* 122 (0x___) Reserved */ + asm_exception_handler, /* 123 (0x___) Reserved */ + asm_exception_handler, /* 124 (0x___) Reserved */ + asm_exception_handler, /* 125 (0x___) Reserved */ + asm_exception_handler, /* 126 (0x___) Reserved */ + asm_exception_handler, /* 127 (0x___) Reserved */ + asm_exception_handler, /* 128 (0x___) Reserved */ + asm_exception_handler, /* 129 (0x___) Reserved */ + asm_exception_handler, /* 130 (0x___) Reserved */ + asm_exception_handler, /* 131 (0x___) Reserved */ + asm_exception_handler, /* 132 (0x___) Reserved */ + asm_exception_handler, /* 133 (0x___) Reserved */ + asm_exception_handler, /* 134 (0x___) Reserved */ + asm_exception_handler, /* 135 (0x___) Reserved */ + asm_exception_handler, /* 136 (0x___) Reserved */ + asm_exception_handler, /* 137 (0x___) Reserved */ + asm_exception_handler, /* 138 (0x___) Reserved */ + asm_exception_handler, /* 139 (0x___) Reserved */ + asm_exception_handler, /* 140 (0x___) Reserved */ + asm_exception_handler, /* 141 (0x___) Reserved */ + asm_exception_handler, /* 142 (0x___) Reserved */ + asm_exception_handler, /* 143 (0x___) Reserved */ + asm_exception_handler, /* 144 (0x___) Reserved */ + asm_exception_handler, /* 145 (0x___) Reserved */ + asm_exception_handler, /* 146 (0x___) Reserved */ + asm_exception_handler, /* 147 (0x___) Reserved */ + asm_exception_handler, /* 148 (0x___) Reserved */ + asm_exception_handler, /* 149 (0x___) Reserved */ + asm_exception_handler, /* 150 (0x___) Reserved */ + asm_exception_handler, /* 151 (0x___) Reserved */ + asm_exception_handler, /* 152 (0x___) Reserved */ + asm_exception_handler, /* 153 (0x___) Reserved */ + asm_exception_handler, /* 154 (0x___) Reserved */ + asm_exception_handler, /* 155 (0x___) Reserved */ + asm_exception_handler, /* 156 (0x___) Reserved */ + asm_exception_handler, /* 157 (0x___) Reserved */ + asm_exception_handler, /* 158 (0x___) Reserved */ + asm_exception_handler, /* 159 (0x___) Reserved */ + asm_exception_handler, /* 160 (0x___) Reserved */ + asm_exception_handler, /* 161 (0x___) Reserved */ + asm_exception_handler, /* 162 (0x___) Reserved */ + asm_exception_handler, /* 163 (0x___) Reserved */ + asm_exception_handler, /* 164 (0x___) Reserved */ + asm_exception_handler, /* 165 (0x___) Reserved */ + asm_exception_handler, /* 166 (0x___) Reserved */ + asm_exception_handler, /* 167 (0x___) Reserved */ + asm_exception_handler, /* 168 (0x___) Reserved */ + asm_exception_handler, /* 169 (0x___) Reserved */ + asm_exception_handler, /* 170 (0x___) Reserved */ + asm_exception_handler, /* 171 (0x___) Reserved */ + asm_exception_handler, /* 172 (0x___) Reserved */ + asm_exception_handler, /* 173 (0x___) Reserved */ + asm_exception_handler, /* 174 (0x___) Reserved */ + asm_exception_handler, /* 175 (0x___) Reserved */ + asm_exception_handler, /* 176 (0x___) Reserved */ + asm_exception_handler, /* 177 (0x___) Reserved */ + asm_exception_handler, /* 178 (0x___) Reserved */ + asm_exception_handler, /* 179 (0x___) Reserved */ + asm_exception_handler, /* 180 (0x___) Reserved */ + asm_exception_handler, /* 181 (0x___) Reserved */ + asm_exception_handler, /* 182 (0x___) Reserved */ + asm_exception_handler, /* 183 (0x___) Reserved */ + asm_exception_handler, /* 184 (0x___) Reserved */ + asm_exception_handler, /* 185 (0x___) Reserved */ + asm_exception_handler, /* 186 (0x___) Reserved */ + asm_exception_handler, /* 187 (0x___) Reserved */ + asm_exception_handler, /* 188 (0x___) Reserved */ + asm_exception_handler, /* 189 (0x___) Reserved */ + asm_exception_handler, /* 190 (0x___) Reserved */ + asm_exception_handler, /* 191 (0x___) Reserved */ + asm_exception_handler, /* 192 (0x___) Reserved */ + asm_exception_handler, /* 193 (0x___) Reserved */ + asm_exception_handler, /* 194 (0x___) Reserved */ + asm_exception_handler, /* 195 (0x___) Reserved */ + asm_exception_handler, /* 196 (0x___) Reserved */ + asm_exception_handler, /* 197 (0x___) Reserved */ + asm_exception_handler, /* 198 (0x___) Reserved */ + asm_exception_handler, /* 199 (0x___) Reserved */ + asm_exception_handler, /* 200 (0x___) Reserved */ + asm_exception_handler, /* 201 (0x___) Reserved */ + asm_exception_handler, /* 202 (0x___) Reserved */ + asm_exception_handler, /* 203 (0x___) Reserved */ + asm_exception_handler, /* 204 (0x___) Reserved */ + asm_exception_handler, /* 205 (0x___) Reserved */ + asm_exception_handler, /* 206 (0x___) Reserved */ + asm_exception_handler, /* 207 (0x___) Reserved */ + asm_exception_handler, /* 208 (0x___) Reserved */ + asm_exception_handler, /* 209 (0x___) Reserved */ + asm_exception_handler, /* 210 (0x___) Reserved */ + asm_exception_handler, /* 211 (0x___) Reserved */ + asm_exception_handler, /* 212 (0x___) Reserved */ + asm_exception_handler, /* 213 (0x___) Reserved */ + asm_exception_handler, /* 214 (0x___) Reserved */ + asm_exception_handler, /* 215 (0x___) Reserved */ + asm_exception_handler, /* 216 (0x___) Reserved */ + asm_exception_handler, /* 217 (0x___) Reserved */ + asm_exception_handler, /* 218 (0x___) Reserved */ + asm_exception_handler, /* 219 (0x___) Reserved */ + asm_exception_handler, /* 220 (0x___) Reserved */ + asm_exception_handler, /* 221 (0x___) Reserved */ + asm_exception_handler, /* 222 (0x___) Reserved */ + asm_exception_handler, /* 223 (0x___) Reserved */ + asm_exception_handler, /* 224 (0x___) Reserved */ + asm_exception_handler, /* 225 (0x___) Reserved */ + asm_exception_handler, /* 226 (0x___) Reserved */ + asm_exception_handler, /* 227 (0x___) Reserved */ + asm_exception_handler, /* 228 (0x___) Reserved */ + asm_exception_handler, /* 229 (0x___) Reserved */ + asm_exception_handler, /* 230 (0x___) Reserved */ + asm_exception_handler, /* 231 (0x___) Reserved */ + asm_exception_handler, /* 232 (0x___) Reserved */ + asm_exception_handler, /* 233 (0x___) Reserved */ + asm_exception_handler, /* 234 (0x___) Reserved */ + asm_exception_handler, /* 235 (0x___) Reserved */ + asm_exception_handler, /* 236 (0x___) Reserved */ + asm_exception_handler, /* 237 (0x___) Reserved */ + asm_exception_handler, /* 238 (0x___) Reserved */ + asm_exception_handler, /* 239 (0x___) Reserved */ + asm_exception_handler, /* 240 (0x___) Reserved */ + asm_exception_handler, /* 241 (0x___) Reserved */ + asm_exception_handler, /* 242 (0x___) Reserved */ + asm_exception_handler, /* 243 (0x___) Reserved */ + asm_exception_handler, /* 244 (0x___) Reserved */ + asm_exception_handler, /* 245 (0x___) Reserved */ + asm_exception_handler, /* 246 (0x___) Reserved */ + asm_exception_handler, /* 247 (0x___) Reserved */ + asm_exception_handler, /* 248 (0x___) Reserved */ + asm_exception_handler, /* 249 (0x___) Reserved */ + asm_exception_handler, /* 250 (0x___) Reserved */ + asm_exception_handler, /* 251 (0x___) Reserved */ + asm_exception_handler, /* 252 (0x___) Reserved */ + asm_exception_handler, /* 253 (0x___) Reserved */ + asm_exception_handler, /* 254 (0x___) Reserved */ + asm_exception_handler, /* 255 (0x___) Reserved */ +}; + +/******************************************************************** + * MCF5xxx ASM utility functions + */ +asm void mcf5xxx_wr_vbr(unsigned long) { /* Set VBR */ + move.l 4(SP),D0 + movec d0,VBR + nop + rts +} + +/******************************************************************** + * MCF5xxx startup copy functions: + * + * Set VBR and performs RAM vector table initializatiom. + * The following symbol should be defined in the lcf: + * __VECTOR_RAM + * + * _vect is the start of the exception table in the code + * In case _vect address is different from __VECTOR_RAM, + * the vector table is copied from _vect to __VECTOR_RAM. + * In any case VBR is set to __VECTOR_RAM. + */ +void initialize_exceptions(void) +{ + /* + * Memory map definitions from linker command files used by mcf5xxx_startup + */ + + register uint32 n; + + /* + * Copy the vector table to RAM + */ + if (__VECTOR_RAM != (unsigned long*)_vect) + { + for (n = 0; n < 256; n++) + __VECTOR_RAM[n] = (unsigned long)_vect[n]; + } + mcf5xxx_wr_vbr((unsigned long)__VECTOR_RAM); +} + +#ifdef __cplusplus +} +#endif diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.h b/Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.h new file mode 100644 index 000000000..9eac95184 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.h @@ -0,0 +1,67 @@ +/* + * File: exceptions.h + * Purpose: Generic exception handling for ColdFire processors + * + * Notes: + */ + +#ifndef _MCF_EXCEPTIONS_H +#define _MCF_EXCEPTIONS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***********************************************************************/ +/* + * This is the handler for all exceptions which are not common to all + * ColdFire Chips. + * + * Called by mcf_exception_handler + * + */ +void derivative_interrupt(unsigned long vector); + +/***********************************************************************/ +/* + * This is the exception handler for all exceptions common to all + * chips ColdFire. Most exceptions do nothing, but some of the more + * important ones are handled to some extent. + * + * Called by asm_exception_handler + */ +void mcf_exception_handler(void *framepointer); + + +/***********************************************************************/ +/* + * This is the assembly exception handler defined in the vector table. + * This function is in assembler so that the frame pointer can be read + * from the stack. + * Note that the way to give the stack frame as argument to the c handler + * depends on the used ABI (Register, Compact or Standard). + * + */ +asm void asm_exception_handler(void); + +/***********************************************************************/ +/* MCF5xxx exceptions table initialization: + * + * Set VBR and performs RAM vector table initialization. + * The following symbol should be defined in the lcf: + * __VECTOR_RAM + * + * _vect is the start of the exception table in the code + * In case _vect address is different from __VECTOR_RAM, + * the vector table is copied from _vect to __VECTOR_RAM. + * In any case VBR is set to __VECTOR_RAM. + */ +void initialize_exceptions(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* _MCF_EXCEPTIONS_H */ + diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/lwipopts.h b/Demo/ColdFire_MCF52221_CodeWarrior/sources/lwipopts.h new file mode 100644 index 000000000..3849907de --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/lwipopts.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +#define TCPIP_THREAD_NAME "tcp/ip" +#define TCPIP_THREAD_STACKSIZE 350 +#define TCPIP_THREAD_PRIO 2 + +#define DEFAULT_THREAD_STACKSIZE 200 +#define DEFAULT_THREAD_PRIO 1 + +#define ETH_PAD_SIZE 2 + +#define NOT_LWIP_DEBUG 0 +#define DBG_TYPES_ON 0x00 +#define LWIP_DBG_TYPES_ON LWIP_DBG_OFF + +#define ETHARP_DEBUG LWIP_DBG_OFF +#define NETIF_DEBUG LWIP_DBG_OFF +#define PBUF_DEBUG LWIP_DBG_OFF +#define API_LIB_DEBUG LWIP_DBG_OFF +#define API_MSG_DEBUG LWIP_DBG_OFF +#define SOCKETS_DEBUG LWIP_DBG_OFF +#define ICMP_DEBUG LWIP_DBG_OFF +#define IGMP_DEBUG LWIP_DBG_OFF +#define INET_DEBUG LWIP_DBG_OFF +#define IP_DEBUG LWIP_DBG_OFF +#define IP_REASS_DEBUG LWIP_DBG_OFF +#define RAW_DEBUG LWIP_DBG_OFF +#define MEM_DEBUG LWIP_DBG_OFF +#define MEMP_DEBUG LWIP_DBG_OFF +#define SYS_DEBUG LWIP_DBG_OFF +#define TCP_DEBUG LWIP_DBG_OFF +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#define TCP_FR_DEBUG LWIP_DBG_OFF +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#define TCP_WND_DEBUG LWIP_DBG_OFF +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#define TCP_RST_DEBUG LWIP_DBG_OFF +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#define UDP_DEBUG LWIP_DBG_OFF +#define TCPIP_DEBUG LWIP_DBG_OFF +#define PPP_DEBUG LWIP_DBG_OFF +#define SLIP_DEBUG LWIP_DBG_OFF +#define DHCP_DEBUG LWIP_DBG_OFF +#define AUTOIP_DEBUG LWIP_DBG_OFF +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#define DNS_DEBUG LWIP_DBG_OFF +#define LWIP_NOASSERT 0 + +#define ETHARP_TRUST_IP_MAC 0 +#define LWIP_UDP 0 + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#define SYS_LIGHTWEIGHT_PROT 1 + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#define MEM_ALIGNMENT 4 + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#define MEM_SIZE (8*1024) + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#define MEMP_NUM_PBUF 20 + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_PCB 10 + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_SEG 8 + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + */ +#define MEMP_NUM_SYS_TIMEOUT 5 + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#define MEMP_NUM_NETBUF 4 + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#define PBUF_POOL_SIZE 4 + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#define PBUF_POOL_BUFSIZE 1500 + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#define LWIP_TCP 1 + +/* TCP Maximum segment size. */ +#define TCP_MSS 1500 + +/* TCP sender buffer space (bytes). */ +#define TCP_SND_BUF 1500 + +/** + * TCP_WND: The size of a TCP window. + */ +#define TCP_WND 1500 + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#define TCP_SYNMAXRTX 4 + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#define LWIP_RAW 0 + + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#define LWIP_SOCKET 0 + + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#define LWIP_STATS 0 + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#define LWIP_DHCP 0 + + +#define LWIP_PROVIDE_ERRNO 0 + +#endif /* __LWIPOPTS_H__ */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/main.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/main.c new file mode 100644 index 000000000..0dba35c71 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/main.c @@ -0,0 +1,449 @@ +/* + FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Check" task - This only executes every five seconds but has a high priority + * to ensure it gets processor time. Its main function is to check that all the + * standard demo tasks are still operational. While no errors have been + * discovered the check task will toggle an LED every 5 seconds - the toggle + * rate increasing to 500ms being a visual indication that at least one task has + * reported unexpected behaviour. + * + * "Reg test" tasks - These fill the registers with known values, then check + * that each register still contains its expected value. Each task uses + * different values. The tasks run with very low priority so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "death.h" +#include "flash.h" +#include "partest.h" +#include "semtest.h" +#include "PollQ.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "recmutex.h" + +/*-----------------------------------------------------------*/ + +/* The time between cycles of the 'check' functionality - as described at the +top of this file. */ +#define mainNO_ERROR_PERIOD ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* The rate at which the LED controlled by the 'check' task will flash should an +error have been detected. */ +#define mainERROR_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* The LED controlled by the 'check' task. */ +#define mainCHECK_LED ( 3 ) + +/* ComTest constants - there is no free LED for the comtest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 ) +#define mainCOM_TEST_LED ( 5 ) + +/* Task priorities. */ +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainWEB_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* + * Configure the hardware for the demo. + */ +static void prvSetupHardware( void ); + +/* + * Implements the 'check' task functionality as described at the top of this + * file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Implement the 'Reg test' functionality as described at the top of this file. + */ +static void vRegTest1Task( void *pvParameters ); +static void vRegTest2Task( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Counters used to detect errors within the reg test tasks. */ +static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Setup the hardware ready for this demo. */ + prvSetupHardware(); + + /* Start the standard demo tasks. */ + vStartLEDFlashTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the reg test tasks - defined in this file. */ + xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL ); + + /* Create the check task. */ + xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + for( ;; ) + { + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0; +portTickType xLastExecutionTime; + + ( void ) pvParameters; + + /* Initialise the variable used to control our iteration rate prior to + its first use. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Wait until it is time to run the tests again. */ + vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait ); + + /* Has an error been found in any task? */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulError |= 0x01UL; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + ulError |= 0x02UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulError |= 0x04UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulError |= 0x20UL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + ulError |= 0x40UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulError |= 0x80UL; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulError |= 0x200UL; + } + + if( ulLastRegTest1Count == ulRegTest1Counter ) + { + ulError |= 0x1000UL; + } + + if( ulLastRegTest2Count == ulRegTest2Counter ) + { + ulError |= 0x1000UL; + } + + ulLastRegTest1Count = ulRegTest1Counter; + ulLastRegTest2Count = ulRegTest2Counter; + + /* If an error has been found then increase our cycle rate, and in so + going increase the rate at which the check task LED toggles. */ + if( ulError != 0 ) + { + ulTicksToWait = mainERROR_PERIOD; + } + + /* Toggle the LED each itteration. */ + vParTestToggleLED( mainCHECK_LED ); + } +} +/*-----------------------------------------------------------*/ + +void prvSetupHardware( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Setup the port used to toggle LEDs. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName ) +{ + /* This will get called if a stack overflow is detected during the context + switch. Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack + problems within nested interrupts, but only do this for debug purposes as + it will increase the context switch time. */ + + ( void ) pxTask; + ( void ) pcTaskName; + + for( ;; ) + { + } +} +/*-----------------------------------------------------------*/ + +static void vRegTest1Task( void *pvParameters ) +{ + /* Sanity check - did we receive the parameter expected? */ + if( pvParameters != &ulRegTest1Counter ) + { + /* Change here so the check task can detect that an error occurred. */ + for( ;; ) + { + } + } + + /* Set all the registers to known values, then check that each retains its + expected value - as described at the top of this file. If an error is + found then the loop counter will no longer be incremented allowing the check + task to recognise the error. */ + asm volatile ( "reg_test_1_start: \n\t" + " moveq #1, d0 \n\t" + " moveq #2, d1 \n\t" + " moveq #3, d2 \n\t" + " moveq #4, d3 \n\t" + " moveq #5, d4 \n\t" + " moveq #6, d5 \n\t" + " moveq #7, d6 \n\t" + " moveq #8, d7 \n\t" + " move #9, a0 \n\t" + " move #10, a1 \n\t" + " move #11, a2 \n\t" + " move #12, a3 \n\t" + " move #13, a4 \n\t" + " move #14, a5 \n\t" + " move #15, a6 \n\t" + " \n\t" + " cmpi.l #1, d0 \n\t" + " bne reg_test_1_error \n\t" + " cmpi.l #2, d1 \n\t" + " bne reg_test_1_error \n\t" + " cmpi.l #3, d2 \n\t" + " bne reg_test_1_error \n\t" + " cmpi.l #4, d3 \n\t" + " bne reg_test_1_error \n\t" + " cmpi.l #5, d4 \n\t" + " bne reg_test_1_error \n\t" + " cmpi.l #6, d5 \n\t" + " bne reg_test_1_error \n\t" + " cmpi.l #7, d6 \n\t" + " bne reg_test_1_error \n\t" + " cmpi.l #8, d7 \n\t" + " bne reg_test_1_error \n\t" + " move a0, d0 \n\t" + " cmpi.l #9, d0 \n\t" + " bne reg_test_1_error \n\t" + " move a1, d0 \n\t" + " cmpi.l #10, d0 \n\t" + " bne reg_test_1_error \n\t" + " move a2, d0 \n\t" + " cmpi.l #11, d0 \n\t" + " bne reg_test_1_error \n\t" + " move a3, d0 \n\t" + " cmpi.l #12, d0 \n\t" + " bne reg_test_1_error \n\t" + " move a4, d0 \n\t" + " cmpi.l #13, d0 \n\t" + " bne reg_test_1_error \n\t" + " move a5, d0 \n\t" + " cmpi.l #14, d0 \n\t" + " bne reg_test_1_error \n\t" + " move a6, d0 \n\t" + " cmpi.l #15, d0 \n\t" + " bne reg_test_1_error \n\t" + " move ulRegTest1Counter, d0 \n\t" + " addq #1, d0 \n\t" + " move d0, ulRegTest1Counter \n\t" + " bra reg_test_1_start \n\t" + "reg_test_1_error: \n\t" + " bra reg_test_1_error \n\t" + ); +} +/*-----------------------------------------------------------*/ + +static void vRegTest2Task( void *pvParameters ) +{ + /* Sanity check - did we receive the parameter expected? */ + if( pvParameters != &ulRegTest2Counter ) + { + /* Change here so the check task can detect that an error occurred. */ + for( ;; ) + { + } + } + + /* Set all the registers to known values, then check that each retains its + expected value - as described at the top of this file. If an error is + found then the loop counter will no longer be incremented allowing the check + task to recognise the error. */ + asm volatile ( "reg_test_2_start: \n\t" + " moveq #10, d0 \n\t" + " moveq #20, d1 \n\t" + " moveq #30, d2 \n\t" + " moveq #40, d3 \n\t" + " moveq #50, d4 \n\t" + " moveq #60, d5 \n\t" + " moveq #70, d6 \n\t" + " moveq #80, d7 \n\t" + " move #90, a0 \n\t" + " move #100, a1 \n\t" + " move #110, a2 \n\t" + " move #120, a3 \n\t" + " move #130, a4 \n\t" + " move #140, a5 \n\t" + " move #150, a6 \n\t" + " \n\t" + " cmpi.l #10, d0 \n\t" + " bne reg_test_2_error \n\t" + " cmpi.l #20, d1 \n\t" + " bne reg_test_2_error \n\t" + " cmpi.l #30, d2 \n\t" + " bne reg_test_2_error \n\t" + " cmpi.l #40, d3 \n\t" + " bne reg_test_2_error \n\t" + " cmpi.l #50, d4 \n\t" + " bne reg_test_2_error \n\t" + " cmpi.l #60, d5 \n\t" + " bne reg_test_2_error \n\t" + " cmpi.l #70, d6 \n\t" + " bne reg_test_2_error \n\t" + " cmpi.l #80, d7 \n\t" + " bne reg_test_2_error \n\t" + " move a0, d0 \n\t" + " cmpi.l #90, d0 \n\t" + " bne reg_test_2_error \n\t" + " move a1, d0 \n\t" + " cmpi.l #100, d0 \n\t" + " bne reg_test_2_error \n\t" + " move a2, d0 \n\t" + " cmpi.l #110, d0 \n\t" + " bne reg_test_2_error \n\t" + " move a3, d0 \n\t" + " cmpi.l #120, d0 \n\t" + " bne reg_test_2_error \n\t" + " move a4, d0 \n\t" + " cmpi.l #130, d0 \n\t" + " bne reg_test_2_error \n\t" + " move a5, d0 \n\t" + " cmpi.l #140, d0 \n\t" + " bne reg_test_2_error \n\t" + " move a6, d0 \n\t" + " cmpi.l #150, d0 \n\t" + " bne reg_test_2_error \n\t" + " move ulRegTest1Counter, d0 \n\t" + " addq #1, d0 \n\t" + " move d0, ulRegTest2Counter \n\t" + " bra reg_test_2_start \n\t" + "reg_test_2_error: \n\t" + " bra reg_test_2_error \n\t" + ); +} +/*-----------------------------------------------------------*/ + +/* To keep the linker happy. */ +void exit( int n ) +{ + ( void ) n; + for( ;; ) {} +} + + diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/printf-stdarg.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/printf-stdarg.c new file mode 100644 index 000000000..f6139dc80 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/printf-stdarg.c @@ -0,0 +1,293 @@ +/* + Copyright 2001, 2002 Georges Menie (www.menie.org) + stdarg version contributed by Christian Ettinger + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +/* + putchar is the only external dependency for this file, + if you have a working putchar, leave it commented out. + If not, uncomment the define below and + replace outbyte(c) by your own function call. + +*/ + +#define putchar(c) c + +#include + +static void printchar(char **str, int c) +{ + //extern int putchar(int c); + + if (str) { + **str = (char)c; + ++(*str); + } + else + { + (void)putchar(c); + } +} + +#define PAD_RIGHT 1 +#define PAD_ZERO 2 + +static int prints(char **out, const char *string, int width, int pad) +{ + register int pc = 0, padchar = ' '; + + if (width > 0) { + register int len = 0; + register const char *ptr; + for (ptr = string; *ptr; ++ptr) ++len; + if (len >= width) width = 0; + else width -= len; + if (pad & PAD_ZERO) padchar = '0'; + } + if (!(pad & PAD_RIGHT)) { + for ( ; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + } + for ( ; *string ; ++string) { + printchar (out, *string); + ++pc; + } + for ( ; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + + return pc; +} + +/* the following should be enough for 32 bit int */ +#define PRINT_BUF_LEN 12 + +static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase) +{ + char print_buf[PRINT_BUF_LEN]; + register char *s; + register int t, neg = 0, pc = 0; + register unsigned int u = (unsigned int)i; + + if (i == 0) { + print_buf[0] = '0'; + print_buf[1] = '\0'; + return prints (out, print_buf, width, pad); + } + + if (sg && b == 10 && i < 0) { + neg = 1; + u = (unsigned int)-i; + } + + s = print_buf + PRINT_BUF_LEN-1; + *s = '\0'; + + while (u) { + t = (int)u % b; + if( t >= 10 ) + t += letbase - '0' - 10; + *--s = (char)(t + '0'); + u /= b; + } + + if (neg) { + if( width && (pad & PAD_ZERO) ) { + printchar (out, '-'); + ++pc; + --width; + } + else { + *--s = '-'; + } + } + + return pc + prints (out, s, width, pad); +} + +static int print( char **out, const char *format, va_list args ) +{ + register int width, pad; + register int pc = 0; + char scr[2]; + + for (; *format != 0; ++format) { + if (*format == '%') { + ++format; + width = pad = 0; + if (*format == '\0') break; + if (*format == '%') goto out; + if (*format == '-') { + ++format; + pad = PAD_RIGHT; + } + while (*format == '0') { + ++format; + pad |= PAD_ZERO; + } + for ( ; *format >= '0' && *format <= '9'; ++format) { + width *= 10; + width += *format - '0'; + } + if( *format == 's' ) { + register char *s = (char *)va_arg( args, int ); + pc += prints (out, s?s:"(null)", width, pad); + continue; + } + if( *format == 'd' ) { + pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a'); + continue; + } + if( *format == 'x' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a'); + continue; + } + if( *format == 'X' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A'); + continue; + } + if( *format == 'u' ) { + pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a'); + continue; + } + if( *format == 'c' ) { + /* char are converted to int then pushed on the stack */ + scr[0] = (char)va_arg( args, int ); + scr[1] = '\0'; + pc += prints (out, scr, width, pad); + continue; + } + } + else { + out: + printchar (out, *format); + ++pc; + } + } + if (out) **out = '\0'; + va_end( args ); + return pc; +} + +int printf(const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return print( 0, format, args ); +} + +int sprintf(char *out, const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return print( &out, format, args ); +} + + +int snprintf( char *buf, unsigned int count, const char *format, ... ) +{ + va_list args; + + ( void ) count; + + va_start( args, format ); + return print( &buf, format, args ); +} + + +#ifdef TEST_PRINTF +int main(void) +{ + char *ptr = "Hello world!"; + char *np = 0; + int i = 5; + unsigned int bs = sizeof(int)*8; + int mi; + char buf[80]; + + mi = (1 << (bs-1)) + 1; + printf("%s\n", ptr); + printf("printf test\n"); + printf("%s is null pointer\n", np); + printf("%d = 5\n", i); + printf("%d = - max int\n", mi); + printf("char %c = 'a'\n", 'a'); + printf("hex %x = ff\n", 0xff); + printf("hex %02x = 00\n", 0); + printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3); + printf("%d %s(s)%", 0, "message"); + printf("\n"); + printf("%d %s(s) with %%\n", 0, "message"); + sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf); + sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf); + sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf); + sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf); + sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf); + sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf); + sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf); + sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf); + + return 0; +} + +/* + * if you compile this file with + * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c + * you will get a normal warning: + * printf.c:214: warning: spurious trailing `%' in format + * this line is testing an invalid % at the end of the format string. + * + * this should display (on 32bit int machine) : + * + * Hello world! + * printf test + * (null) is null pointer + * 5 = 5 + * -2147483647 = - max int + * char a = 'a' + * hex ff = ff + * hex 00 = 00 + * signed -3 = unsigned 4294967293 = hex fffffffd + * 0 message(s) + * 0 message(s) with % + * justif: "left " + * justif: " right" + * 3: 0003 zero padded + * 3: 3 left justif. + * 3: 3 right justif. + * -3: -003 zero padded + * -3: -3 left justif. + * -3: -3 right justif. + */ + +#endif + + +/* To keep linker happy. */ +int write( int i, char* c, int n) +{ + (void)i; + (void)n; + (void)c; + return 0; +} + diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.c new file mode 100644 index 000000000..dabac672d --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.c @@ -0,0 +1,312 @@ +/* + * CF_Startup.c - Default init/startup/termination routines for + * Embedded Metrowerks C++ + * + * Copyright © 1993-1998 Metrowerks, Inc. All Rights Reserved. + * Copyright © 2005 Freescale semiConductor Inc. All Rights Reserved. + * + * + * THEORY OF OPERATION + * + * This version of thestartup code is intended for linker relocated + * executables. The startup code will assign the stack pointer to + * __SP_INIT, assign the address of the data relative base address + * to a5, initialize the .bss/.sbss sections to zero, call any + * static C++ initializers and then call main. Upon returning from + * main it will call C++ destructors and call exit to terminate. + */ + +#ifdef __cplusplus +#pragma cplusplus off +#endif +#pragma PID off +#pragma PIC off + +#include "startcf.h" +#include "RuntimeConfig.h" + + /* imported data */ + +extern unsigned long far _SP_INIT, _SDA_BASE; +extern unsigned long far _START_BSS, _END_BSS; +extern unsigned long far _START_SBSS, _END_SBSS; +extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END; + + /* imported routines */ + +extern void __call_static_initializers(void); +extern int main(int, char **); +extern void exit(int); + + /* exported routines */ + +extern void _ExitProcess(void); +extern asm void _startup(void); +extern void __initialize_hardware(void); +extern void __initialize_system(void); + + +/* + * Dummy routine for initializing hardware. For user's custom systems, you + * can create your own routine of the same name that will perform HW + * initialization. The linker will do the right thing to ignore this + * definition and use the version in your file. + */ +#pragma overload void __initialize_hardware(void); +void __initialize_hardware(void) +{ +} + +/* + * Dummy routine for initializing systems. For user's custom systems, + * you can create your own routine of the same name that will perform + * initialization. The linker will do the right thing to ignore this + * definition and use the version in your file. + */ +#pragma overload void __initialize_system(void); +void __initialize_system(void) +{ +} + +/* + * Dummy routine for initializing C++. This routine will get overloaded by the C++ runtime. + */ +#pragma overload void __call_static_initializers(void); +void __call_static_initializers(void) +{ +} + +/* + * Routine to copy a single section from ROM to RAM ... + */ +static __declspec(register_abi) void __copy_rom_section(char* dst, const char* src, unsigned long size) +{ + if (dst != src) + while (size--) + *dst++ = *src++; +} + +/* + * Routine that copies all sections the user marked as ROM into + * their target RAM addresses ... + * + * __S_romp is automatically generated by the linker if it + * is referenced by the program. It is a table of RomInfo + * structures. The final entry in the table has all-zero + * fields. + */ +static void __copy_rom_sections_to_ram(void) +{ + RomInfo *info; + + /* + * Go through the entire table, copying sections from ROM to RAM. + */ + for (info = _S_romp; info->Source != 0L || info->Target != 0L || info->Size != 0; ++info) + __copy_rom_section( (char *)info->Target,(char *)info->Source, info->Size); + +} + +/* + * Exit handler called from the exit routine, if your OS needs + * to do something special for exit handling just replace this + * routines with what the OS needs to do ... + */ +asm void _ExitProcess(void) +{ + illegal + rts +} + +/* + * Routine to clear out blocks of memory should give good + * performance regardless of 68k or ColdFire part. + */ +static __declspec(register_abi) void clear_mem(char *dst, unsigned long n) +{ + unsigned long i; + long *lptr; + + if (n >= 32) + { + /* align start address to a 4 byte boundary */ + i = (- (unsigned long) dst) & 3; + + if (i) + { + n -= i; + do + *dst++ = 0; + while (--i); + } + + /* use an unrolled loop to zero out 32byte blocks */ + i = n >> 5; + if (i) + { + lptr = (long *)dst; + dst += i * 32; + do + { + *lptr++ = 0; + *lptr++ = 0; + *lptr++ = 0; + *lptr++ = 0; + *lptr++ = 0; + *lptr++ = 0; + *lptr++ = 0; + *lptr++ = 0; + } + while (--i); + } + i = (n & 31) >> 2; + + /* handle any 4 byte blocks left */ + if (i) + { + lptr = (long *)dst; + dst += i * 4; + do + *lptr++ = 0; + while (--i); + } + n &= 3; + } + + /* handle any byte blocks left */ + if (n) + do + *dst++ = 0; + while (--n); +} + +/* + * Startup routine for embedded application ... + */ + +asm void _startup(void) +{ + /* disable interrupts */ + move.w #0x2700,sr + + /* Pre-init SP, in case memory for stack is not valid it should be setup using + MEMORY_INIT before __initialize_hardware is called + */ + lea __SP_AFTER_RESET,a7; + + /* initialize memory */ + MEMORY_INIT + + /* initialize any hardware specific issues */ + jsr __initialize_hardware + + /* setup the stack pointer */ + lea _SP_INIT,a7 + + /* setup A6 dummy stackframe */ + movea.l #0,a6 + link a6,#0 + + /* setup A5 */ + lea _SDA_BASE,a5 + + + /* zero initialize the .bss section */ + + lea _END_BSS, a0 + lea _START_BSS, a1 + suba.l a1, a0 + move.l a0, d0 + + beq __skip_bss__ + + lea _START_BSS, a0 + + /* call clear_mem with base pointer in a0 and size in d0 */ + jsr clear_mem + +__skip_bss__: + + /* zero initialize the .sbss section */ + + lea _END_SBSS, a0 + lea _START_SBSS, a1 + suba.l a1, a0 + move.l a0, d0 + + beq __skip_sbss__ + + lea _START_SBSS, a0 + + /* call clear_mem with base pointer in a0 and size in d0 */ + jsr clear_mem + +__skip_sbss__: + + /* copy all ROM sections to their RAM locations ... */ +#if SUPPORT_ROM_TO_RAM + + /* + * _S_romp is a null terminated array of + * typedef struct RomInfo { + * unsigned long Source; + * unsigned long Target; + * unsigned long Size; + * } RomInfo; + * + * Watch out if you're rebasing using _PICPID_DELTA + */ + + lea _S_romp, a0 + move.l a0, d0 + beq __skip_rom_copy__ + jsr __copy_rom_sections_to_ram + +#else + + /* + * There's a single block to copy from ROM to RAM, perform + * the copy directly without using the __S_romp structure + */ + + lea __DATA_RAM, a0 + lea __DATA_ROM, a1 + + cmpa a0,a1 + beq __skip_rom_copy__ + + move.l #__DATA_END, d0 + sub.l a0, d0 + + jsr __copy_rom_section + +#endif +__skip_rom_copy__: + + /* call C++ static initializers (__sinit__(void)) */ + jsr __call_static_initializers + + jsr __initialize_system + + /* call main(int, char **) */ + pea __argv + clr.l -(sp) /* clearing a long is ok since it's caller cleanup */ + jsr main + addq.l #8, sp + + unlk a6 + + /* now call exit(0) to terminate the application */ + clr.l -(sp) + jsr exit + addq.l #4, sp + + /* should never reach here but just in case */ + illegal + rts + + /* exit will never return */ +__argv: + dc.l 0 +} + diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.h b/Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.h new file mode 100644 index 000000000..135ab92ff --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.h @@ -0,0 +1,74 @@ +/****************************************************************************** + FILE : startcf.h + PURPOSE : startup code for ColdFire + LANGUAGE: C + + + Notes: + 1) Default entry point is _startup. + . disable interrupts + . the SP is set to __SP_AFTER_RESET + . SP must be initialized to valid memory + in case the memory it points to is not valid using MEMORY_INIT macro + 2) __initialize_hardware is called. Here you can initialize memory and some peripherics + at this point global variables are not initialized yet + 3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform + needed initialisations for the language (clear memory, data rom copy). + 4) void __initialize_system(void); is called + to allow additional hardware initialization (UART, GPIOs, etc...) + 5) Jump to main + +*/ +/********************************************************************************/ + +#ifndef STARTCF_H +#define STARTCF_H + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "support_common.h" + +extern unsigned long far __SP_INIT[]; +extern unsigned long far __SP_AFTER_RESET[]; + + +#ifndef MEMORY_INIT +/* If MEMORY_INIT is set then it performs + minimal memory initialization (to preset SP to __SP_AFTER_RESET, etc...) +*/ +#define MEMORY_INIT +#endif + + +void _startup(void); + +#ifndef SUPPORT_ROM_TO_RAM + /* + * If SUPPORT_ROM_TO_RAM is set, _S_romp is used to define the copy to be performed. + * If it is not set, there's a single block to copy, performed directly without + * using the __S_romp structure, based on __DATA_RAM, __DATA_ROM and + * __DATA_END symbols. + * + * Set to 0 for more aggressive dead stripping ... + */ +#define SUPPORT_ROM_TO_RAM 1 +#endif + +/* format of the ROM table info entry ... */ +typedef struct RomInfo { + void *Source; + void *Target; + unsigned long Size; +} RomInfo; + +/* imported data */ +extern far RomInfo _S_romp[]; /* linker defined symbol */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.c new file mode 100644 index 000000000..3bfa519d0 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.c @@ -0,0 +1,509 @@ +/* FILENAME: stdlib.c + * + * Functions normally found in a standard C lib. + * + * 12/28/2005 - added memcmp and memmove + * + * Notes: These functions support ASCII only!!! + */ + +#include "support_common.h" +#include "stdlib.h" + +/***********************************************************************/ +/* + * Misc. Defines + */ +#ifdef FALSE +#undef FALSE +#endif +#define FALSE (0) + +#ifdef TRUE +#undef TRUE +#endif +#define TRUE (1) + +#ifdef NULL +#undef NULL +#endif +#define NULL (0) + +#ifdef ON +#undef ON +#endif +#define ON (1) + +#ifdef OFF +#undef OFF +#endif +#define OFF (0) + + +/****************************************************************/ +int +isspace (int ch) +{ + if ((ch == ' ') || (ch == '\t')) /* \n ??? */ + return TRUE; + else + return FALSE; +} + +/****************************************************************/ +int +isalnum (int ch) +{ + /* ASCII only */ + if (((ch >= '0') && (ch <= '9')) || + ((ch >= 'A') && (ch <= 'Z')) || + ((ch >= 'a') && (ch <= 'z'))) + return TRUE; + else + return FALSE; +} + +/****************************************************************/ +int +isdigit (int ch) +{ + /* ASCII only */ + if ((ch >= '0') && (ch <= '9')) + return TRUE; + else + return FALSE; +} + +/****************************************************************/ +int +isupper (int ch) +{ + /* ASCII only */ + if ((ch >= 'A') && (ch <= 'Z')) + return TRUE; + else + return FALSE; +} + +/****************************************************************/ +int +strcasecmp (const char *s1, const char *s2) +{ + char c1, c2; + int result = 0; + + while (result == 0) + { + c1 = *s1++; + c2 = *s2++; + if ((c1 >= 'a') && (c1 <= 'z')) + c1 = (char)(c1 - ' '); + if ((c2 >= 'a') && (c2 <= 'z')) + c2 = (char)(c2 - ' '); + if ((result = (c1 - c2)) != 0) + break; + if ((c1 == 0) || (c2 == 0)) + break; + } + return result; +} + + +/****************************************************************/ +int +stricmp (const char *s1, const char *s2) +{ + return (strcasecmp(s1, s2)); +} + +/****************************************************************/ +int +strncasecmp (const char *s1, const char *s2, int n) +{ + char c1, c2; + int k = 0; + int result = 0; + + while ( k++ < n ) + { + c1 = *s1++; + c2 = *s2++; + if ((c1 >= 'a') && (c1 <= 'z')) + c1 = (char)(c1 - ' '); + if ((c2 >= 'a') && (c2 <= 'z')) + c2 = (char)(c2 - ' '); + if ((result = (c1 - c2)) != 0) + break; + if ((c1 == 0) || (c2 == 0)) + break; + } + return result; +} + +/****************************************************************/ +int +strnicmp (const char *s1, const char *s2, int n) +{ + return (strncasecmp(s1, s2, n)); +} + +/****************************************************************/ +uint32 +strtoul (char *str, char **ptr, int base) +{ + unsigned long rvalue = 0; + int neg = 0; + int c; + + /* Validate parameters */ + if ((str != NULL) && (base >= 0) && (base <= 36)) + { + /* Skip leading white spaces */ + while (isspace(*str)) + { + ++str; + } + + /* Check for notations */ + switch (str[0]) + { + case '0': + if (base == 0) + { + if ((str[1] == 'x') || (str[1] == 'X')) + { + base = 16; + str += 2; + } + else + { + base = 8; + str++; + } + } + break; + + case '-': + neg = 1; + str++; + break; + + case '+': + str++; + break; + + default: + break; + } + + if (base == 0) + base = 10; + + /* Valid "digits" are 0..9, A..Z, a..z */ + while (isalnum(c = *str)) + { + /* Convert char to num in 0..36 */ + if ((c -= ('a' - 10)) < 10) /* 'a'..'z' */ + { + if ((c += ('a' - 'A')) < 10) /* 'A'..'Z' */ + { + c += ('A' - '0' - 10); /* '0'..'9' */ + } + } + + /* check c against base */ + if (c >= base) + { + break; + } + + if (neg) + { + rvalue = (rvalue * base) - c; + } + else + { + rvalue = (rvalue * base) + c; + } + + ++str; + } + } + + /* Upon exit, 'str' points to the character at which valid info */ + /* STOPS. No chars including and beyond 'str' are used. */ + + if (ptr != NULL) + *ptr = str; + + return rvalue; + } + +/****************************************************************/ +int +atoi (const char *str) +{ + char *s = (char *)str; + + return ((int)strtoul(s, NULL, 10)); +} + +/****************************************************************/ +int +strlen (const char *str) +{ + char *s = (char *)str; + int len = 0; + + if (s == NULL) + return 0; + + while (*s++ != '\0') + ++len; + + return len; +} + +/****************************************************************/ +char * +strcat (char *dest, const char *src) +{ + char *dp; + char *sp = (char *)src; + + if ((dest != NULL) && (src != NULL)) + { + dp = &dest[strlen(dest)]; + + while (*sp != '\0') + { + *dp++ = *sp++; + } + *dp = '\0'; + } + return dest; +} + +/****************************************************************/ +char * +strncat (char *dest, const char *src, int n) +{ + char *dp; + char *sp = (char *)src; + + if ((dest != NULL) && (src != NULL) && (n > 0)) + { + dp = &dest[strlen(dest)]; + + while ((*sp != '\0') && (n-- > 0)) + { + *dp++ = *sp++; + } + *dp = '\0'; + } + return dest; +} + +/****************************************************************/ +char * +strcpy (char *dest, const char *src) +{ + char *dp = (char *)dest; + char *sp = (char *)src; + + if ((dest != NULL) && (src != NULL)) + { + while (*sp != '\0') + { + *dp++ = *sp++; + } + *dp = '\0'; + } + return dest; +} + +/****************************************************************/ +char * +strncpy (char *dest, const char *src, int n) +{ + char *dp = (char *)dest; + char *sp = (char *)src; + + if ((dest != NULL) && (src != NULL) && (n > 0)) + { + while ((*sp != '\0') && (n-- > 0)) + { + *dp++ = *sp++; + } + *dp = '\0'; + } + return dest; +} + +/****************************************************************/ +int +strcmp (const char *s1, const char *s2) +{ + /* No checks for NULL */ + char *s1p = (char *)s1; + char *s2p = (char *)s2; + + while (*s2p != '\0') + { + if (*s1p != *s2p) + break; + + ++s1p; + ++s2p; + } + return (*s1p - *s2p); +} + +/****************************************************************/ +int +strncmp (const char *s1, const char *s2, int n) +{ + /* No checks for NULL */ + char *s1p = (char *)s1; + char *s2p = (char *)s2; + + if (n <= 0) + return 0; + + while (*s2p != '\0') + { + if (*s1p != *s2p) + break; + + if (--n == 0) + break; + + ++s1p; + ++s2p; + } + return (*s1p - *s2p); +} + +/****************************************************************/ +char * +strstr(const char *s1, const char *s2) +{ + char *sp = (char *)s1; + int len1 = strlen(s1); + int len2 = strlen(s2); + + while (len1 >= len2) + { + if (strncmp(sp, s2, len2) == 0) + { + return (sp); + } + ++sp; + --len1; + } + + return (NULL); +} + +/****************************************************************/ +char * +strchr(const char *str, int c) +{ + char *sp = (char *)str; + char ch = (char)(c & 0xff); + + while (*sp != '\0') + { + if (*sp == ch) + { + return (sp); + } + ++sp; + } + + return (NULL); +} + +/****************************************************************/ +void * +memcpy (void *dest, const void *src, unsigned n) +{ + unsigned char *dbp = (unsigned char *)dest; + unsigned char *sbp = (unsigned char *)src; + + if ((dest != NULL) && (src != NULL) && (n > 0)) + { + while (n--) + *dbp++ = *sbp++; + } + return dest; +} + +/****************************************************************/ +void * +memset (void *s, int c, unsigned n) +{ + /* Not optimized, but very portable */ + unsigned char *sp = (unsigned char *)s; + + if ((s != NULL) && (n > 0)) + { + while (n--) + { + *sp++ = (unsigned char)c; + } + } + return s; +} + +/****************************************************************/ +int +memcmp (const void *s1, const void *s2, unsigned n) +{ + unsigned char *s1p, *s2p; + + if (s1 && s2 && (n > 0)) + { + s1p = (unsigned char *)s1; + s2p = (unsigned char *)s2; + + while ((--n >= 0) && (*s1p == *s2p)) + { + if (*s1p != *s2p) + return (*s1p - *s2p); + ++s1p; + ++s2p; + } + } + + return (0); +} + +/****************************************************************/ +void * +memmove (void *dest, const void *src, unsigned n) +{ + unsigned char *dbp = (unsigned char *)dest; + unsigned char *sbp = (unsigned char *)src; + unsigned char *dend = dbp + n; + unsigned char *send = sbp + n; + + if ((dest != NULL) && (src != NULL) && (n > 0)) + { + /* see if a memcpy would overwrite source buffer */ + if ((sbp < dbp) && (dbp < send)) + { + while (n--) + *(--dend) = *(--send); + } + else + { + while (n--) + *dbp++ = *sbp++; + } + } + + return dest; +} + +/****************************************************************/ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.h b/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.h new file mode 100644 index 000000000..7a9865d94 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.h @@ -0,0 +1,79 @@ +/* + * File: stdlib.h + * Purpose: Function prototypes for standard library functions + * + * Notes: + */ + +#ifndef _STDLIB_H +#define _STDLIB_H + +/******************************************************************** + * Standard library functions + ********************************************************************/ + +int +isspace (int); + +int +isalnum (int); + +int +isdigit (int); + +int +isupper (int); + +int +strcasecmp (const char *, const char *); + +int +strncasecmp (const char *, const char *, int); + +unsigned long +strtoul (char *, char **, int); + +int +strlen (const char *); + +char * +strcat (char *, const char *); + +char * +strncat (char *, const char *, int); + +char * +strcpy (char *, const char *); + +char * +strncpy (char *, const char *, int); + +int +strcmp (const char *, const char *); + +int +strncmp (const char *, const char *, int); + +void * +memcpy (void *, const void *, unsigned); + +void * +memset (void *, int, unsigned); + +void +free (void *); + +void * +malloc (unsigned); + +#define RAND_MAX 32767 + +int +rand (void); + +void +srand (int); + +/********************************************************************/ + +#endif diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/support_common.h b/Demo/ColdFire_MCF52221_CodeWarrior/sources/support_common.h new file mode 100644 index 000000000..db1d80497 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/support_common.h @@ -0,0 +1,35 @@ +/* +* File: support_common.h + * Purpose: Various project configurations. + * + * Notes: + */ + +#ifndef _SUPPORT_COMMON_H_ +#define _SUPPORT_COMMON_H_ + +/* Enable UART Support. */ +#define ENABLE_UART_SUPPORT 0 + + +#define MEMORY_INIT \ + /* Initialize RAMBAR: locate SRAM and validate it */ \ + move.l %#__RAMBAR + 0x21,d0; \ + movec d0,RAMBAR; + +#define SUPPORT_ROM_TO_RAM 1 + +/* + * Include the derivative header files + */ +#include "MCF52221.h" + +/* + * Include the board specific header files + */ +#include "MCF52221_sysinit.h" + +/********************************************************************/ + +#endif /* _SUPPORT_COMMON_H_ */ + diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.c b/Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.c new file mode 100644 index 000000000..8dfbdf433 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.c @@ -0,0 +1,298 @@ +/* + * File: uart_support.c + * Purpose: Implements UART basic support, Derivative Specific Interrupt handler and need function needed + * for MSL Support (printf\cout to terminal), defined in + * + * Notes: + * + */ +#include "support_common.h" +#include "uart_support.h" + +#if ENABLE_UART_SUPPORT==1 + + +#if UART_SUPPORT_TYPE==UART_PSC +/* 5475 & 5485 boards have different names for uart access registers */ +void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate) +{ + register uint16 ubgs; + + /* + * On Verdi, only PSC 0 & 1 are brought out to RS232 transceivers + */ + + /* Put PSC in UART mode */ + MCF_PSC_PSCSICR(channel) = MCF_PSC_PSCSICR_SIM_UART; + + /* Rx and Tx baud rate from timers */ + MCF_PSC_PSCCSR(channel) = (0 + | MCF_PSC_PSCCSR_RCSEL_SYS_CLK + | MCF_PSC_PSCCSR_TCSEL_SYS_CLK); + + /* + * Calculate baud settings + */ + ubgs = (uint16)((systemClockKHz * 1000)/(baudRate * 32)); + + MCF_PSC_PSCCTUR(channel) = (uint8) ((ubgs >> 8) & 0xFF); + MCF_PSC_PSCCTLR(channel) = (uint8) (ubgs & 0xFF); + + /* Reset transmitter, receiver, mode register, and error conditions */ + MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_RX; + MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_TX; + MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_ERROR; + MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_BKCHGINT; + MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_MR; + + /* 8-bit data, no parity */ + MCF_PSC_PSCMR(channel) = (0 +#ifdef UART_HARDWARE_FLOW_CONTROL + | MCF_PSC_PSCMR_RXRTS +#endif + | MCF_PSC_PSCMR_PM_NONE + | MCF_PSC_PSCMR_BC_8); + + /* No echo or loopback, 1 stop bit */ + MCF_PSC_PSCMR(channel) = (0 +#ifdef UART_HARDWARE_FLOW_CONTROL + | MCF_PSC_PSCMR_TXCTS +#endif + | MCF_PSC_PSCMR_CM_NORMAL + | MCF_PSC_PSCMR_SB_STOP_BITS_1); + + /* Mask all UART interrupts */ + MCF_PSC_PSCIMR(channel) = 0x0000; + + /* Enable RTS to send */ + MCF_PSC_PSCOPSET(channel) = MCF_PSC_PSCOPSET_RTS; + + /* Setup FIFO Alarms */ + MCF_PSC_PSCRFAR(channel) = MCF_PSC_PSCRFAR_ALARM(248); + MCF_PSC_PSCTFAR(channel) = MCF_PSC_PSCTFAR_ALARM(248); + + /* Enable receiver and transmitter */ + MCF_PSC_PSCCR(channel) =(0 + | MCF_PSC_PSCCR_RX_ENABLED + | MCF_PSC_PSCCR_TX_ENABLED); +} + +/********************************************************************/ +/* + * Wait for a character to be received on the specified UART + * + * Return Values: + * the received character + */ +char uart_getchar (int channel) +{ + /* Wait until character has been received */ + while (!(MCF_PSC_PSCSR(channel) & MCF_PSC_PSCSR_RXRDY)) + { + + } + return (char)(*((uint8 *) &MCF_PSC_PSCRB_8BIT(channel))); +} + +/********************************************************************/ +/* + * Wait for space in the UART Tx FIFO and then send a character + */ +void uart_putchar (int channel, char ch) +{ + /* Wait until space is available in the FIFO */ + while (!(MCF_PSC_PSCSR(channel) & MCF_PSC_PSCSR_TXRDY)) + ; + *((uint8 *) &MCF_PSC_PSCTB_8BIT(channel)) = (uint8)ch; +} + + +#else /* UART_SUPPORT_TYPE==UART_PSC */ + +#if UART_SUPPORT_TYPE == UART_5407 +/********************************************************************/ +/* + * 5407 derivative doesn't have macros to access URB/UTB by channel number + * because they have different sizes for UART0 & UART1 + * But in UART mode only 8 bits of UART1 URB/UTB is used, so define these macros here + * if they doesn't defined before + */ +#ifndef MCF_UART_URB +#define MCF_UART_URB(x) (*(vuint8 *)(&__MBAR[0x1CC + ((x)*0x40)])) +#endif /* MCF_UART_URB */ + +#ifndef MCF_UART_UTB +#define MCF_UART_UTB(x) (*(vuint8 *)(&__MBAR[0x1CC + ((x)*0x40)])) +#endif /* MCF_UART_UTB */ + +#endif /* UART_SUPPORT_TYPE == UART_5407 */ + +void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate) +{ + /* + * Initialize UART for serial communications + */ + + register uint16 ubgs; + +#if UART_SUPPORT_TYPE==UART_54451 + uint32 vco; + uint32 divider; + uint32 bus_clk; + + divider = ((MCF_CLOCK_PCR & 0x000000F0) >> 4) + 1; + vco = ((MCF_CLOCK_PCR >> 24) * systemClockKHz * 1000); + bus_clk = (vco / divider); +#endif + /* + * Reset Transmitter + */ + MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_TX; + + /* + * Reset Receiver + */ + MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_RX; + + /* + * Reset Mode Register + */ + MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_MR; + + /* + * No parity, 8-bits per character + */ + MCF_UART_UMR(channel) = (0 + | MCF_UART_UMR_PM_NONE + | MCF_UART_UMR_BC_8 ); + + /* + * No echo or loopback, 1 stop bit + */ + MCF_UART_UMR(channel) = (0 + | MCF_UART_UMR_CM_NORMAL + | MCF_UART_UMR_SB_STOP_BITS_1); + + /* + * Set Rx and Tx baud by SYSTEM CLOCK + */ + MCF_UART_UCSR(channel) = (0 + | MCF_UART_UCSR_RCS_SYS_CLK + | MCF_UART_UCSR_TCS_SYS_CLK); + + /* + * Mask all UART interrupts + */ + MCF_UART_UIMR(channel) = 0; + + /* + * Calculate baud settings + */ +#if UART_SUPPORT_TYPE==UART_54451 + ubgs = (uint16)(((bus_clk >> 5) + (baudRate >> 1)) / baudRate); +#else + ubgs = (uint16)((systemClockKHz * 1000)/(baudRate * 32)); +#endif + +#if UART_SUPPORT_TYPE==UART_DIVIDER || UART_SUPPORT_TYPE == UART_5407 + MCF_UART_UDU(channel) = (uint8)((ubgs & 0xFF00) >> 8); + MCF_UART_UDL(channel) = (uint8)(ubgs & 0x00FF); +#else /* UART_SUPPORT_TYPE!=UART_DIVIDER */ + MCF_UART_UBG1(channel) = (uint8)((ubgs & 0xFF00) >> 8); + MCF_UART_UBG2(channel) = (uint8)(ubgs & 0x00FF); +#endif /* UART_SUPPORT_TYPE==UART_DIVIDER */ + + /* + * Enable receiver and transmitter + */ + MCF_UART_UCR(channel) = (0 + | MCF_UART_UCR_TX_ENABLED + | MCF_UART_UCR_RX_ENABLED); +} + +/********************************************************************/ +/* + * Wait for a character to be received on the specified UART + * + * Return Values: + * the received character + */ +char uart_getchar (int channel) +{ + /* Wait until character has been received */ + while (!(MCF_UART_USR(channel) & MCF_UART_USR_RXRDY)) + { + + }; + + return (char)MCF_UART_URB(channel); +} + +/********************************************************************/ +/* + * Wait for space in the UART Tx FIFO and then send a character + */ +void uart_putchar (int channel, char ch) +{ + /* Wait until space is available in the FIFO */ + while (!(MCF_UART_USR(channel) & MCF_UART_USR_TXRDY)) + { + + }; + + /* Send the character */ + MCF_UART_UTB(channel) = (uint8)ch; +} + +#endif /* UART_SUPPORT_TYPE==UART_PSC */ +/********************************************************************/ + +/********************************************************************/ +/** Neeeded functions **/ +/********************************************************************/ + +/****************************************************************************/ +/* + * Implementation for CodeWarror MSL interface to serial device (UART.h). + * Needed for printf, etc... + * Only InitializeUART, ReadUARTN, and WriteUARTN are implemented. + * + */ +UARTError InitializeUART(UARTBaudRate baudRate) +{ +#if UART_SUPPORT_TYPE==UART_54451 + baudRate = kBaud115200; +#endif + uart_init(TERMINAL_PORT, SYSTEM_CLOCK_KHZ, baudRate); + return kUARTNoError; +} + +/****************************************************************************/ +/* + ReadUARTN + + Read N bytes from the UART. + + bytes pointer to result buffer + limit size of buffer and # of bytes to read +*/ +/****************************************************************************/ +UARTError ReadUARTN(void* bytes, unsigned long limit) +{ + int count; + for (count = 0; count < limit; count++) { + *( (char *)bytes + count ) = uart_getchar(TERMINAL_PORT); + } + return kUARTNoError; +} + +/****************************************************************************/ +UARTError WriteUARTN(const void* bytes, unsigned long length) +{ + int count; + for (count = 0; count < length; count++) { + uart_putchar(TERMINAL_PORT, *( ((char *)bytes) + count)); + } + return kUARTNoError; +} +#endif /* ENABLE_UART_SUPPORT */ diff --git a/Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.h b/Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.h new file mode 100644 index 000000000..cceeeb7f1 --- /dev/null +++ b/Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.h @@ -0,0 +1,66 @@ +/* + * File: uart_support.h + * Purpose: Implements UART basic support, Derivative Specific Interrupt handler and need function needed + * for MSL Support (printf\cout to terminal), defined in + * + * Notes: + * + */ + +#ifndef __UART_SUPPORT_H__ +#define __UART_SUPPORT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "support_common.h" + +#if ENABLE_UART_SUPPORT==1 + +/* + * Include the Freescale UART specific header file for printf/cout/scanf support + */ +#include +#ifdef __cplusplus +extern "C" { +#endif +#include +#ifdef __cplusplus +} +#endif + +#define UART_STANDARD 0 +#define UART_DIVIDER 1 +#define UART_5407 2 +#define UART_PSC 3 +#define UART_54451 4 + +#define UART_SUPPORT_TYPE UART_STANDARD + +void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate); + +/********************************************************************/ +/* + * Wait for a character to be received on the specified UART + * + * Return Values: + * the received character + */ +char uart_getchar (int channel); + +/********************************************************************/ +/* + * Wait for space in the UART Tx FIFO and then send a character + */ +void uart_putchar (int channel, char ch); + + +#endif /* ENABLE_UART_SUPPORT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UART_SUPPORT_H__ */ -- 2.39.2