From 13ac3d556c8cae37807801b64c289a3e9bfde359 Mon Sep 17 00:00:00 2001 From: Paul Fertser Date: Sat, 14 Mar 2015 08:15:12 +0300 Subject: [PATCH] target/cortex_a: emit a clear error message when dbgbase can't be detected In some cases (the most obvious are TI's SoCs) ROM table lacks entries for the cores, so OpenOCD has no way to determine what debug base to use. Due to an error fixed in ec9ccaa28849 it wasn't handled properly, and OpenOCD would continue to try using dbgbase = 0, which happened to work for e.g. AM437x. This patch adds a clear indication to the user that to access such a target, dbgbase must be set manually in the config. Reported by Felipe Balbi on IRC. Change-Id: Id8533e708f44b76550eb8b659564f5f45717c298 Signed-off-by: Paul Fertser Reviewed-on: http://openocd.zylin.com/2603 Tested-by: jenkins --- src/target/cortex_a.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index ab52dd75..7ecf428d 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -2871,8 +2871,11 @@ static int cortex_a_examine_first(struct target *target) /* Lookup 0x15 -- Processor DAP */ retval = dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15, &armv7a->debug_base, &coreidx); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.", + target->cmd_name); return retval; + } LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32, coreidx, armv7a->debug_base); } else -- 2.39.5