From 1733646f4d3c8d71ad1501e15744e4aa6517ab45 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Mon, 23 Jan 2012 12:02:57 +0000 Subject: [PATCH] Add XMC4500 project. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1676 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../Dbg_Flash.ini | 2 + .../Dbg_RAM TraceETM.ini | 36 ++ .../Dbg_RAM.ini | 32 + .../FreeRTOSConfig.h | 149 +++++ .../RTOSDemo.uvopt | 577 ++++++++++++++++++ .../RTOSDemo.uvproj | 530 ++++++++++++++++ .../RegTest.c | 502 +++++++++++++++ .../System_XMC4500.c | 356 +++++++++++ .../Template.sct | 15 + Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c | 421 +++++++++++++ .../startup_XMC4500.s | 541 ++++++++++++++++ 11 files changed, 3161 insertions(+) create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_Flash.ini create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM TraceETM.ini create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM.ini create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvproj create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Template.sct create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c create mode 100644 Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_Flash.ini b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_Flash.ini new file mode 100644 index 000000000..307511920 --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_Flash.ini @@ -0,0 +1,2 @@ +_WDWORD(0xE0002008, 0x00000000); // Clear FPB 0 (FP_COMP0) + diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM TraceETM.ini b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM TraceETM.ini new file mode 100644 index 000000000..4c624d397 --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM TraceETM.ini @@ -0,0 +1,36 @@ +/*---------------------------------------------------------------------------- + * Name: Dbg_RAM.ini + * Purpose: RAM Debug Initialization File + * Note(s): + *---------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2008-2011 Keil - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Setup() configure PC & SP for RAM Debug + *----------------------------------------------------------------------------*/ +FUNC void Setup (void) { + SP = _RDWORD(0x10000000); // Setup Stack Pointer + PC = _RDWORD(0x10000004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x10000000); // Setup Vector Table Offset Register +} + +_WDWORD(0x5000413C, 0x001F3700); // Enable RAM + +_WDWORD(0x48028674, 0x00001405); // Enable ETM Pins P6 + +_WDWORD(0x48028274, 0x00401405); // Enable ETM Pins P2 + +LOAD %L INCREMENTAL // load the application + +Setup(); // Setup for Running + +/*g, main*/ + \ No newline at end of file diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM.ini b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM.ini new file mode 100644 index 000000000..832a6eb0c --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM.ini @@ -0,0 +1,32 @@ +/*---------------------------------------------------------------------------- + * Name: Dbg_RAM.ini + * Purpose: RAM Debug Initialization File + * Note(s): + *---------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2008-2011 Keil - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Setup() configure PC & SP for RAM Debug + *----------------------------------------------------------------------------*/ +FUNC void Setup (void) { + SP = _RDWORD(0x10000000); // Setup Stack Pointer + PC = _RDWORD(0x10000004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x10000000); // Setup Vector Table Offset Register +} + +_WDWORD(0x5000413C, 0x001F3700); // Enable RAM + +LOAD %L INCREMENTAL // load the application + +Setup(); // Setup for Running + +/*g, main*/ + \ No newline at end of file diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h new file mode 100644 index 000000000..65b233fc0 --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#include +extern uint32_t SystemCoreClock; + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 6 /* 63 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt new file mode 100644 index 000000000..4129a7056 --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt @@ -0,0 +1,577 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + RTOSDemo + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + + 0 + Data Sheet + DATASHTS\Infineon\comming.pdf + + + 1 + User Manual + DATASHTS\Infineon\comming.pdf + + + + SARMCM3.DLL + -MPU + DARMP1.DLL + -pLPC1785 + SARMCM3.DLL + -MPU + TARMP1.DLL + -pLPC1785 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(314=-1,-1,-1,-1,0)(292=-1,-1,-1,-1,0)(303=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(410=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(362=-1,-1,-1,-1,0)(363=-1,-1,-1,-1,0)(364=-1,-1,-1,-1,0)(365=-1,-1,-1,-1,0)(366=-1,-1,-1,-1,0)(367=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(337=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(390=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(385=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(199=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(263=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(314=-1,-1,-1,-1,0)(292=-1,-1,-1,-1,0)(303=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(410=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(362=-1,-1,-1,-1,0)(363=-1,-1,-1,-1,0)(364=-1,-1,-1,-1,0)(365=-1,-1,-1,-1,0)(366=-1,-1,-1,-1,0)(367=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(337=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(390=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(385=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(263=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + ULP2CM3 + -UP1048084 -O143 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO18 -TC10000000 -TP28 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000 + + + 0 + UL2CM3 + -UM1129BUE -O142 -S9 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO16 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000 + + + + + 1 + 5 + 0x0C000000 + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Startup + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + 0 + 213 + 213 + 0 + .\startup_XMC4500.s + startup_XMC4500.s + + + 1 + 2 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + 0 + .\System_XMC4500.c + System_XMC4500.c + + + + + Demo_Source + 1 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 161 + 174 + 0 + .\main.c + main.c + + + 2 + 4 + 5 + 0 + 0 + 47 + 0 + 0 + 0 + 0 + .\FreeRTOSConfig.h + FreeRTOSConfig.h + + + 2 + 5 + 1 + 0 + 0 + 0 + 0 + 297 + 309 + 0 + .\RegTest.c + RegTest.c + + + + + FreeRTOS_Source + 1 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\timers.c + timers.c + + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\list.c + list.c + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 1215 + 1228 + 0 + ..\..\Source\queue.c + queue.c + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\tasks.c + tasks.c + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\portable\MemMang\heap_2.c + heap_2.c + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\portable\RVDS\ARM_CM4F\port.c + port.c + + + + + Other + 0 + 0 + 0 + + 4 + 12 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\readme.txt + readme.txt + + + + + Common_Demo_Source + 0 + 0 + 0 + + 5 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\semtest.c + semtest.c + + + 5 + 14 + 1 + 0 + 0 + 0 + 0 + 283 + 296 + 0 + ..\Common\Minimal\sp_flop.c + sp_flop.c + + + 5 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\BlockQ.c + BlockQ.c + + + 5 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\blocktim.c + blocktim.c + + + 5 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\countsem.c + countsem.c + + + 5 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\death.c + death.c + + + 5 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\dynamic.c + dynamic.c + + + 5 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\GenQTest.c + GenQTest.c + + + 5 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\integer.c + integer.c + + + 5 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\PollQ.c + PollQ.c + + + 5 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\recmutex.c + recmutex.c + + + + + 1 + 0 + + 100 + 0 + + + .\main.c + 0 + 161 + 174 + + + + + +
diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvproj b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvproj new file mode 100644 index 000000000..c77a412e2 --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvproj @@ -0,0 +1,530 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + RTOSDemo + 0x4 + ARM-ADS + + + XMC4500 + Infineon + IRAM(0x10000000-0x1000FFFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x0C000000-0x0C0FFFFF) IROM2(0x08000000-0x080FFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") + + "STARTUP\Infineon\XMC4500\startup_XMC4500.s" ("Infineon XMC4500 Startup Code") + UL2CM3(-FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000) + 0 + XMC4500.H + + + + + + + + + + SFD\Infineon\XMC4500\xmc4500.sfr + 0 + + + + Infineon\XMC4500\ + Infineon\XMC4500\ + + 0 + 0 + 0 + 0 + 1 + + .\Flash\ + RTOSDemo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DARMP1.DLL + -pLPC1785 + SARMCM3.DLL + -MPU + TARMP1.DLL + -pLPC1785 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 1 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x10000 + + + 1 + 0xc000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0xc000000 + 0x100000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x10000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata + rvkdm PART_XMC4500 + + ..\CORTEX_M4F_Infineon_XMC4500_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;..\Common\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x0C000000 + 0x10000000 + + + + --entry=Reset_Handler + + + + + + + + Startup + + + startup_XMC4500.s + 2 + .\startup_XMC4500.s + + + System_XMC4500.c + 1 + .\System_XMC4500.c + + + + + Demo_Source + + + main.c + 1 + .\main.c + + + FreeRTOSConfig.h + 5 + .\FreeRTOSConfig.h + + + RegTest.c + 1 + .\RegTest.c + + + + + FreeRTOS_Source + + + timers.c + 1 + ..\..\Source\timers.c + + + list.c + 1 + ..\..\Source\list.c + + + queue.c + 1 + ..\..\Source\queue.c + + + tasks.c + 1 + ..\..\Source\tasks.c + + + heap_2.c + 1 + ..\..\Source\portable\MemMang\heap_2.c + + + port.c + 1 + ..\..\Source\portable\RVDS\ARM_CM4F\port.c + + + + + Other + + + readme.txt + 5 + .\readme.txt + + + + + Common_Demo_Source + + + semtest.c + 1 + ..\Common\Minimal\semtest.c + + + sp_flop.c + 1 + ..\Common\Minimal\sp_flop.c + + + BlockQ.c + 1 + ..\Common\Minimal\BlockQ.c + + + blocktim.c + 1 + ..\Common\Minimal\blocktim.c + + + countsem.c + 1 + ..\Common\Minimal\countsem.c + + + death.c + 1 + ..\Common\Minimal\death.c + + + dynamic.c + 1 + ..\Common\Minimal\dynamic.c + + + GenQTest.c + 1 + ..\Common\Minimal\GenQTest.c + + + integer.c + 1 + ..\Common\Minimal\integer.c + + + PollQ.c + 1 + ..\Common\Minimal\PollQ.c + + + recmutex.c + 1 + ..\Common\Minimal\recmutex.c + + + + + + + +
diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c new file mode 100644 index 000000000..52130081b --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c @@ -0,0 +1,502 @@ +/* + FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +__asm vRegTest1Task( void ) +{ + PRESERVE8 + IMPORT ulRegTest1LoopCounter + + /* Fill the core registers with known values. */ + mov r0, #100 + mov r1, #101 + mov r2, #102 + mov r3, #103 + mov r4, #104 + mov r5, #105 + mov r6, #106 + mov r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the VFP registers with known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg1_loop + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d1 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d2 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d3 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d4 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d5 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d6 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d7 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d8 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d9 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d10 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d11 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d12 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d13 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d14 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d15 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg1_loopf_pass + +reg1_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg1_error_loopf + +reg1_loopf_pass + + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop +} +/*-----------------------------------------------------------*/ + +__asm vRegTest2Task( void ) +{ + PRESERVE8 + IMPORT ulRegTest2LoopCounter + + /* Set all the core registers to known values. */ + mov r0, #-1 + mov r1, #1 + mov r2, #2 + mov r3, #3 + mov r4, #4 + mov r5, #5 + mov r6, #6 + mov r7, #7 + mov r8, #8 + mov r9, #9 + mov r10, #10 + mov r11, #11 + mov r12, #12 + + /* Set all the VFP to known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg2_loop + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d1 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d2 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d3 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d4 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d5 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d6 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d7 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d8 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d9 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d10 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d11 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d12 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d13 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d14 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d15 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg2_loopf_pass + +reg2_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg2_error_loopf + +reg2_loopf_pass + + cmp r0, #-1 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + /* Increment the loop counter to indicate this test is still functioning + correctly. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop + /* If this line is hit then there was an error in a core register value. + This loop ensures the loop counter variable stops incrementing. */ + b reg2_error_loop + nop +} +/*-----------------------------------------------------------*/ + +__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue ) +{ + PRESERVE8 + + /* Clobber the auto saved registers. */ + vmov d0, r0, r0 + vmov d1, r0, r0 + vmov d2, r0, r0 + vmov d3, r0, r0 + vmov d4, r0, r0 + vmov d5, r0, r0 + vmov d6, r0, r0 + vmov d7, r0, r0 + bx lr +} +/*-----------------------------------------------------------*/ + +__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue ) +{ + PRESERVE8 + + vmov r1, s0 + cmp r0, r1 + bne return_error + vmov r1, s1 + cmp r0, r1 + bne return_error + vmov r1, s2 + cmp r0, r1 + bne return_error + vmov r1, s3 + cmp r0, r1 + bne return_error + vmov r1, s4 + cmp r0, r1 + bne return_error + vmov r1, s5 + cmp r0, r1 + bne return_error + vmov r1, s6 + cmp r0, r1 + bne return_error + vmov r1, s7 + cmp r0, r1 + bne return_error + vmov r1, s8 + cmp r0, r1 + bne return_error + vmov r1, s9 + cmp r0, r1 + bne return_error + vmov r1, s10 + cmp r0, r1 + bne return_error + vmov r1, s11 + cmp r0, r1 + bne return_error + vmov r1, s12 + cmp r0, r1 + bne return_error + vmov r1, s13 + cmp r0, r1 + bne return_error + vmov r1, s14 + cmp r0, r1 + bne return_error + vmov r1, s15 + cmp r0, r1 + bne return_error + +return_pass + mov r0, #1 + bx lr + +return_error + mov r0, #0 + bx lr +} + + diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c new file mode 100644 index 000000000..d11f5918e --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c @@ -0,0 +1,356 @@ +/**************************************************************************//** + * @file system_XMC4500.h + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4500 Device Series + * @version V2.1 + * @date 20. December 2011 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "System_XMC4500.h" +#include + +/*---------------------------------------------------------------------------- + Define clocks is located in System_XMC4500.h + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = CLOCK_OSC_HP;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +static int SystemClockSetup(void); +static void USBClockSetup(void); + +/*---------------------------------------------------------------------------- + Keil pragma to prevent warnings + *----------------------------------------------------------------------------*/ +#pragma diag_suppress 177 + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 + + + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> USB Clock +// <3=> Divided value of PLL Clock +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000000 +#define SCU_CLOCKOUT_PIN 0x00000000 + + + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +/* Setup the WDT */ + #if WDT_SETUP + WDT->CTR &= ~WDTENB_nVal; + #endif + +/* enable coprocessor FPU */ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + +/* Disable branch prediction - PCON.PBS = 1 */ + PREF->PCON |= (PREF_PCON_PBS_Msk << PREF_PCON_PBS_Pos); + +/* Setup the clockout */ + #if SCU_CLOCKOUT_SETUP + SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; + if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + } + else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + #endif + +/* Setup the System clock */ + #if SCU_CLOCK_SETUP + SystemClockSetup(); + #endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ + SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/ + +/* Setup the USB PL */ + #if SCU_USB_CLOCK_SETUP + USBClockSetup(); + #endif + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ + SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/ + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +static int SystemClockSetup(void) +{ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +/* Enable OSC_HP */ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + + SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + do + { + ; /* here a timeout need to be added */ + }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); + + } + +/* Setup Main PLL */ + /* select FOFI as system clock */ + if(SCU_CLK->SYSCLKCR != 0X000000)SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/ + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)); + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /********************************************************* + here the ramp up of the system clock starts + *********************************************************/ + /* Delay for next K2 step ~50µs */ + /********************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24)); + + /* Delay for next K2 step ~50µs */ + /********************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24)); + + /* Delay for next K2 step ~50µs */ + /********************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) | (PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + + return(1); + +} + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +static void USBClockSetup(void) +{ +/* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); + +/* check and if not already running enable OSC_HP */ + if(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))) + { + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + + SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + do + { + ; /* here a timeout need to be added */ + }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); + + } + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + +} + + diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Template.sct b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Template.sct new file mode 100644 index 000000000..785967479 --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Template.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x0C000000 0x00100000 { ; load region size_region + ER_IROM1 0x0C000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x10000000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c new file mode 100644 index 000000000..738438f0f --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c @@ -0,0 +1,421 @@ +/* + FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * main() creates all the demo application tasks and a software timer, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" timer - The check software timer period is initially set to three + * seconds. The callback function associated with the check software timer + * checks that all the standard demo tasks, and the register check tasks, are + * not only still executing, but are executing without reporting any errors. If + * the check software timer discovers that a task has either stalled, or + * reported an error, then it changes its own execution period from the initial + * three seconds, to just 200ms. The check software timer callback function + * also toggles the single LED each time it is called. This provides a visual + * indication of the system status: If the LED toggles every three seconds, + * then no issues have been discovered. If the LED toggles every 200ms, then + * an issue has been discovered with at least one task. + * + * + * Additional code: + * + * This demo does not contain a non-kernel interrupt service routine that + * can be used as an example for application writers to use as a reference. + * Therefore, the framework of a dummy (not installed) handler is provided + * in this file. The dummy function is called Dummy_IRQHandler(). Please + * ensure to read the comments in the function itself, but more importantly, + * the notes on the function contained on the documentation page for this demo + * that is found on the FreeRTOS.org web site. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "integer.h" +#include "PollQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" + +/* Hardware includes. */ +#include "XMC4500.h" +#include "System_XMC4500.h" + +/* Priorities for the demo application tasks. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* To toggle the single LED */ +#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_RATE_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_RATE_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS ) + +/*-----------------------------------------------------------*/ + +/* + * Set up the hardware ready to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * The check timer callback function, as described at the top of this file. + */ +static void prvCheckTimerCallback( xTimerHandle xTimer ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file. + */ +extern void vRegTest1Task( void *pvParameters ); +extern void vRegTest2Task( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check software timer. If the variables keep +incrementing, then the register check tasks has not discovered any errors. If +a variable stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ +xTimerHandle xCheckTimer = NULL; + + /* Configure the hardware ready to run the test. */ + prvSetupHardware(); + + /* Start all the other standard demo/test tasks. The have not particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* Create the register check tasks, as described at the top of this + file */ + xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + + /* Create the software timer that performs the 'check' functionality, + as described at the top of this file. */ + xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xCheckTimer != NULL ) + { + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + } + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + will never be reached. If the following line does execute, then there was + insufficient FreeRTOS heap memory available for the idle and/or timer tasks + to be created. See the memory management section on the FreeRTOS web site + for more details. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTimerCallback( xTimerHandle xTimer ) +{ +static long lChangedTimerPeriodAlready = pdFALSE; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = pdTRUE; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = pdTRUE; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + everything is ok. A faster toggle indicates an error. */ + mainTOGGLE_LED(); + + /* Have any errors been latch in ulErrorFound? If so, shorten the + period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + This will result in an increase in the rate at which mainCHECK_LED + toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + Functions called from inside of a timer callback function must + *never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +extern void SystemCoreClockUpdate( void ); + + /* Ensure SystemCoreClock variable is set. */ + SystemCoreClockUpdate(); + + /* Configure pin P3.9 for the LED. */ + PORT3->IOCR8 = 0x00008000; + + /* Ensure all priority bits are assigned as preemption priority bits. */ + NVIC_SetPriorityGrouping( 0 ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* vApplicationMallocFailedHook() will only be called if + configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + function that will get called if a call to pvPortMalloc() fails. + pvPortMalloc() is called internally by the kernel whenever a task, queue, + timer or semaphore is created. It is also called by various parts of the + demo application. If heap_1.c or heap_2.c are used, then the size of the + heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + to query the size of free heap space that remains (although it does not + provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + task. It is essential that code added to this hook function never attempts + to block in any way (for example, call xQueueReceive() with a block time + specified, or call vTaskDelay()). If the application makes use of the + vTaskDelete() API function (as this demo application does) then it is also + important that vApplicationIdleHook() is permitted to return to its calling + function, because it is the responsibility of the idle task to clean up + memory allocated by the kernel to any task that has since been deleted. */ +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + /* This function will be called by each tick interrupt if + configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + added here, but the tick hook is called from an interrupt context, so + code must not attempt to block, and only the interrupt safe FreeRTOS API + functions can be used (those that end in FromISR()). */ +} +/*-----------------------------------------------------------*/ + +#ifdef JUST_AN_EXAMPLE_ISR + +void Dummy_IRQHandler(void) +{ +long lHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt if necessary. */ + Dummy_ClearITPendingBit(); + + /* This interrupt does nothing more than demonstrate how to synchronise a + task with an interrupt. A semaphore is used for this purpose. Note + lHigherPriorityTaskWoken is initialised to zero. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + semaphore caused the task to unblock, and the unblocked task has a priority + higher than the current Running state task (the task that this interrupt + interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE + internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the + portEND_SWITCHING_ISR() macro will result in a context switch being pended to + ensure this interrupt returns directly to the unblocked, higher priority, + task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); +} + +#endif /* JUST_AN_EXAMPLE_ISR */ diff --git a/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s new file mode 100644 index 000000000..0db35b283 --- /dev/null +++ b/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s @@ -0,0 +1,541 @@ +;*****************************************************************************/ +; * @file startup_XMC4500.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Infineon XMC4500 Device Series +; * @version V1.02 +; * @date 6. December 2011 +; * +; * @note +; * Copyright (C) 2009-2011 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + + +;* <<< Use Configuration Wizard in Context Menu >>> + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +;* ================== START OF VECTOR TABLE DEFINITION ====================== */ +;* Vector Table - This gets programed into VTOR register */ + AREA RESET, DATA, READONLY + EXPORT __cs3_interrupt_vector_cortex_m + EXPORT __cs3_interrupt_vector_cortex_m_End + EXPORT __cs3_interrupt_vector_cortex_m_Size + + + +__cs3_interrupt_vector_cortex_m + DCD __initial_sp ;* Top of Stack */ + DCD Reset_Handler ;* Reset Handler */ + DCD NMI_Handler ;* NMI Handler */ + DCD HardFault_Handler ;* Hard Fault Handler */ + DCD MemManage_Handler ;* MPU Fault Handler */ + DCD BusFault_Handler ;* Bus Fault Handler */ + DCD UsageFault_Handler ;* Usage Fault Handler */ + DCD 0 ;* Reserved */ + DCD 0 ;* Reserved */ + DCD 0 ;* Reserved */ + DCD 0 ;* Reserved */ + DCD SVC_Handler ;* SVCall Handler */ + DCD DebugMon_Handler ;* Debug Monitor Handler */ + DCD 0 ;* Reserved */ + DCD PendSV_Handler ;* PendSV Handler */ + DCD SysTick_Handler ;* SysTick Handler */ + + ;* Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals */ + DCD SCU_0_IRQHandler ;* Handler name for SR SCU_0 */ + DCD ERU0_0_IRQHandler ;* Handler name for SR ERU0_0 */ + DCD ERU0_1_IRQHandler ;* Handler name for SR ERU0_1 */ + DCD ERU0_2_IRQHandler ;* Handler name for SR ERU0_2 */ + DCD ERU0_3_IRQHandler ;* Handler name for SR ERU0_3 */ + DCD ERU1_0_IRQHandler ;* Handler name for SR ERU1_0 */ + DCD ERU1_1_IRQHandler ;* Handler name for SR ERU1_1 */ + DCD ERU1_2_IRQHandler ;* Handler name for SR ERU1_2 */ + DCD ERU1_3_IRQHandler ;* Handler name for SR ERU1_3 */ + DCD 0 ;* Not Available */ + DCD 0 ;* Not Available */ + DCD 0 ;* Not Available */ + DCD PMU0_0_IRQHandler ;* Handler name for SR PMU0_0 */ + DCD 0 ;* Not Available */ + DCD VADC0_C0_0_IRQHandler ;* Handler name for SR VADC0_C0_0 */ + DCD VADC0_C0_1_IRQHandler ;* Handler name for SR VADC0_C0_1 */ + DCD VADC0_C0_2_IRQHandler ;* Handler name for SR VADC0_C0_1 */ + DCD VADC0_C0_3_IRQHandler ;* Handler name for SR VADC0_C0_3 */ + DCD VADC0_G0_0_IRQHandler ;* Handler name for SR VADC0_G0_0 */ + DCD VADC0_G0_1_IRQHandler ;* Handler name for SR VADC0_G0_1 */ + DCD VADC0_G0_2_IRQHandler ;* Handler name for SR VADC0_G0_2 */ + DCD VADC0_G0_3_IRQHandler ;* Handler name for SR VADC0_G0_3 */ + DCD VADC0_G1_0_IRQHandler ;* Handler name for SR VADC0_G1_0 */ + DCD VADC0_G1_1_IRQHandler ;* Handler name for SR VADC0_G1_1 */ + DCD VADC0_G1_2_IRQHandler ;* Handler name for SR VADC0_G1_2 */ + DCD VADC0_G1_3_IRQHandler ;* Handler name for SR VADC0_G1_3 */ + DCD VADC0_G2_0_IRQHandler ;* Handler name for SR VADC0_G2_0 */ + DCD VADC0_G2_1_IRQHandler ;* Handler name for SR VADC0_G2_1 */ + DCD VADC0_G2_2_IRQHandler ;* Handler name for SR VADC0_G2_2 */ + DCD VADC0_G2_3_IRQHandler ;* Handler name for SR VADC0_G2_3 */ + DCD VADC0_G3_0_IRQHandler ;* Handler name for SR VADC0_G3_0 */ + DCD VADC0_G3_1_IRQHandler ;* Handler name for SR VADC0_G3_1 */ + DCD VADC0_G3_2_IRQHandler ;* Handler name for SR VADC0_G3_2 */ + DCD VADC0_G3_3_IRQHandler ;* Handler name for SR VADC0_G3_3 */ + DCD DSD0_0_IRQHandler ;* Handler name for SR DSD0_0 */ + DCD DSD0_1_IRQHandler ;* Handler name for SR DSD0_1 */ + DCD DSD0_2_IRQHandler ;* Handler name for SR DSD0_2 */ + DCD DSD0_3_IRQHandler ;* Handler name for SR DSD0_3 */ + DCD DSD0_4_IRQHandler ;* Handler name for SR DSD0_4 */ + DCD DSD0_5_IRQHandler ;* Handler name for SR DSD0_5 */ + DCD DSD0_6_IRQHandler ;* Handler name for SR DSD0_6 */ + DCD DSD0_7_IRQHandler ;* Handler name for SR DSD0_7 */ + DCD DAC0_0_IRQHandler ;* Handler name for SR DAC0_0 */ + DCD DAC0_1_IRQHandler ;* Handler name for SR DAC0_0 */ + DCD CCU40_0_IRQHandler ;* Handler name for SR CCU40_0 */ + DCD CCU40_1_IRQHandler ;* Handler name for SR CCU40_1 */ + DCD CCU40_2_IRQHandler ;* Handler name for SR CCU40_2 */ + DCD CCU40_3_IRQHandler ;* Handler name for SR CCU40_3 */ + DCD CCU41_0_IRQHandler ;* Handler name for SR CCU41_0 */ + DCD CCU41_1_IRQHandler ;* Handler name for SR CCU41_1 */ + DCD CCU41_2_IRQHandler ;* Handler name for SR CCU41_2 */ + DCD CCU41_3_IRQHandler ;* Handler name for SR CCU41_3 */ + DCD CCU42_0_IRQHandler ;* Handler name for SR CCU42_0 */ + DCD CCU42_1_IRQHandler ;* Handler name for SR CCU42_1 */ + DCD CCU42_2_IRQHandler ;* Handler name for SR CCU42_2 */ + DCD CCU42_3_IRQHandler ;* Handler name for SR CCU42_3 */ + DCD CCU43_0_IRQHandler ;* Handler name for SR CCU43_0 */ + DCD CCU43_1_IRQHandler ;* Handler name for SR CCU43_1 */ + DCD CCU43_2_IRQHandler ;* Handler name for SR CCU43_2 */ + DCD CCU43_3_IRQHandler ;* Handler name for SR CCU43_3 */ + DCD CCU80_0_IRQHandler ;* Handler name for SR CCU80_0 */ + DCD CCU80_1_IRQHandler ;* Handler name for SR CCU80_1 */ + DCD CCU80_2_IRQHandler ;* Handler name for SR CCU80_2 */ + DCD CCU80_3_IRQHandler ;* Handler name for SR CCU80_3 */ + DCD CCU81_0_IRQHandler ;* Handler name for SR CCU81_0 */ + DCD CCU81_1_IRQHandler ;* Handler name for SR CCU81_1 */ + DCD CCU81_2_IRQHandler ;* Handler name for SR CCU81_2 */ + DCD CCU81_3_IRQHandler ;* Handler name for SR CCU81_3 */ + DCD POSIF0_0_IRQHandler ;* Handler name for SR POSIF0_0 */ + DCD POSIF0_1_IRQHandler ;* Handler name for SR POSIF0_1 */ + DCD POSIF1_0_IRQHandler ;* Handler name for SR POSIF1_0 */ + DCD POSIF1_1_IRQHandler ;* Handler name for SR POSIF1_1 */ + DCD 0 ;* Not Available */ + DCD 0 ;* Not Available */ + DCD 0 ;* Not Available */ + DCD 0 ;* Not Available */ + DCD CAN0_0_IRQHandler ;* Handler name for SR CAN0_0 */ + DCD CAN0_1_IRQHandler ;* Handler name for SR CAN0_1 */ + DCD CAN0_2_IRQHandler ;* Handler name for SR CAN0_2 */ + DCD CAN0_3_IRQHandler ;* Handler name for SR CAN0_3 */ + DCD CAN0_4_IRQHandler ;* Handler name for SR CAN0_4 */ + DCD CAN0_5_IRQHandler ;* Handler name for SR CAN0_5 */ + DCD CAN0_6_IRQHandler ;* Handler name for SR CAN0_6 */ + DCD CAN0_7_IRQHandler ;* Handler name for SR CAN0_7 */ + DCD USIC0_0_IRQHandler ;* Handler name for SR USIC0_0 */ + DCD USIC0_1_IRQHandler ;* Handler name for SR USIC0_1 */ + DCD USIC0_2_IRQHandler ;* Handler name for SR USIC0_2 */ + DCD USIC0_3_IRQHandler ;* Handler name for SR USIC0_3 */ + DCD USIC0_4_IRQHandler ;* Handler name for SR USIC0_4 */ + DCD USIC0_5_IRQHandler ;* Handler name for SR USIC0_5 */ + DCD USIC1_0_IRQHandler ;* Handler name for SR USIC1_0 */ + DCD USIC1_1_IRQHandler ;* Handler name for SR USIC1_1 */ + DCD USIC1_2_IRQHandler ;* Handler name for SR USIC1_2 */ + DCD USIC1_3_IRQHandler ;* Handler name for SR USIC1_3 */ + DCD USIC1_4_IRQHandler ;* Handler name for SR USIC1_4 */ + DCD USIC1_5_IRQHandler ;* Handler name for SR USIC1_5 */ + DCD USIC2_0_IRQHandler ;* Handler name for SR USIC2_0 */ + DCD USIC2_1_IRQHandler ;* Handler name for SR USIC2_1 */ + DCD USIC2_2_IRQHandler ;* Handler name for SR USIC2_2 */ + DCD USIC2_3_IRQHandler ;* Handler name for SR USIC2_3 */ + DCD USIC2_4_IRQHandler ;* Handler name for SR USIC2_4 */ + DCD USIC2_5_IRQHandler ;* Handler name for SR USIC2_5 */ + DCD LEDTS0_0_IRQHandler ;* Handler name for SR LEDTS0_0 */ + DCD 0 ;* Not Available */ + DCD FCE0_0_IRQHandler ;* Handler name for SR FCE0_0 */ + DCD GPDMA0_0_IRQHandler ;* Handler name for SR GPDMA0_0 */ + DCD SDMMC0_0_IRQHandler ;* Handler name for SR SDMMC0_0 */ + DCD USB0_0_IRQHandler ;* Handler name for SR USB0_0 */ + DCD ETH0_0_IRQHandler ;* Handler name for SR ETH0_0 */ + DCD 0 ;* Not Available */ + DCD GPDMA1_0_IRQHandler ;* Handler name for SR GPDMA1_0 */ + DCD 0 ;* Not Available */ +__cs3_interrupt_vector_cortex_m_End + +__cs3_interrupt_vector_cortex_m_Size EQU __cs3_interrupt_vector_cortex_m_End - __cs3_interrupt_vector_cortex_m + +;* ================== END OF VECTOR TABLE DEFINITION ======================= */ + +;* ================== START OF VECTOR ROUTINES ============================= */ + + AREA |.text|, CODE, READONLY + +;* Reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ;* Remap vector table + LDR R0, =__cs3_interrupt_vector_cortex_m + LDR R1, =0xE000ED08 ;*VTOR register + STR R0,[R1] + + ;enable un-aligned memory access + LDR R1, =0xE000ED14 + LDR.W R0,[R1,#0x0] + BIC R0,R0,#0x8 + STR.W R0,[R1,#0x0] + + + ;* C routines are likely to be called. Setup the stack now + LDR SP,=__initial_sp + + + LDR R0, = SystemInit + BLX R0 + + + ;* Reset stack pointer before zipping off to user application + LDR SP,=__initial_sp + + LDR R0, =__main + BX R0 + + ENDP + + + + +;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ + +;* Default exception Handlers - Users may override this default functionality by + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ + +;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ + +;* IRQ Handlers */ + EXPORT SCU_0_IRQHandler [WEAK] + EXPORT ERU0_0_IRQHandler [WEAK] + EXPORT ERU0_1_IRQHandler [WEAK] + EXPORT ERU0_2_IRQHandler [WEAK] + EXPORT ERU0_3_IRQHandler [WEAK] + EXPORT ERU1_0_IRQHandler [WEAK] + EXPORT ERU1_1_IRQHandler [WEAK] + EXPORT ERU1_2_IRQHandler [WEAK] + EXPORT ERU1_3_IRQHandler [WEAK] + EXPORT PMU0_0_IRQHandler [WEAK] + EXPORT VADC0_C0_0_IRQHandler [WEAK] + EXPORT VADC0_C0_1_IRQHandler [WEAK] + EXPORT VADC0_C0_2_IRQHandler [WEAK] + EXPORT VADC0_C0_3_IRQHandler [WEAK] + EXPORT VADC0_G0_0_IRQHandler [WEAK] + EXPORT VADC0_G0_1_IRQHandler [WEAK] + EXPORT VADC0_G0_2_IRQHandler [WEAK] + EXPORT VADC0_G0_3_IRQHandler [WEAK] + EXPORT VADC0_G1_0_IRQHandler [WEAK] + EXPORT VADC0_G1_1_IRQHandler [WEAK] + EXPORT VADC0_G1_2_IRQHandler [WEAK] + EXPORT VADC0_G1_3_IRQHandler [WEAK] + EXPORT VADC0_G2_0_IRQHandler [WEAK] + EXPORT VADC0_G2_1_IRQHandler [WEAK] + EXPORT VADC0_G2_2_IRQHandler [WEAK] + EXPORT VADC0_G2_3_IRQHandler [WEAK] + EXPORT VADC0_G3_0_IRQHandler [WEAK] + EXPORT VADC0_G3_1_IRQHandler [WEAK] + EXPORT VADC0_G3_2_IRQHandler [WEAK] + EXPORT VADC0_G3_3_IRQHandler [WEAK] + EXPORT DSD0_0_IRQHandler [WEAK] + EXPORT DSD0_1_IRQHandler [WEAK] + EXPORT DSD0_2_IRQHandler [WEAK] + EXPORT DSD0_3_IRQHandler [WEAK] + EXPORT DSD0_4_IRQHandler [WEAK] + EXPORT DSD0_5_IRQHandler [WEAK] + EXPORT DSD0_6_IRQHandler [WEAK] + EXPORT DSD0_7_IRQHandler [WEAK] + EXPORT DAC0_0_IRQHandler [WEAK] + EXPORT DAC0_1_IRQHandler [WEAK] + EXPORT CCU40_0_IRQHandler [WEAK] + EXPORT CCU40_1_IRQHandler [WEAK] + EXPORT CCU40_2_IRQHandler [WEAK] + EXPORT CCU40_3_IRQHandler [WEAK] + EXPORT CCU41_0_IRQHandler [WEAK] + EXPORT CCU41_1_IRQHandler [WEAK] + EXPORT CCU41_2_IRQHandler [WEAK] + EXPORT CCU41_3_IRQHandler [WEAK] + EXPORT CCU42_0_IRQHandler [WEAK] + EXPORT CCU42_1_IRQHandler [WEAK] + EXPORT CCU42_2_IRQHandler [WEAK] + EXPORT CCU42_3_IRQHandler [WEAK] + EXPORT CCU43_0_IRQHandler [WEAK] + EXPORT CCU43_1_IRQHandler [WEAK] + EXPORT CCU43_2_IRQHandler [WEAK] + EXPORT CCU43_3_IRQHandler [WEAK] + EXPORT CCU80_0_IRQHandler [WEAK] + EXPORT CCU80_1_IRQHandler [WEAK] + EXPORT CCU80_2_IRQHandler [WEAK] + EXPORT CCU80_3_IRQHandler [WEAK] + EXPORT CCU81_0_IRQHandler [WEAK] + EXPORT CCU81_1_IRQHandler [WEAK] + EXPORT CCU81_2_IRQHandler [WEAK] + EXPORT CCU81_3_IRQHandler [WEAK] + EXPORT POSIF0_0_IRQHandler [WEAK] + EXPORT POSIF0_1_IRQHandler [WEAK] + EXPORT POSIF1_0_IRQHandler [WEAK] + EXPORT POSIF1_1_IRQHandler [WEAK] + EXPORT CAN0_0_IRQHandler [WEAK] + EXPORT CAN0_1_IRQHandler [WEAK] + EXPORT CAN0_2_IRQHandler [WEAK] + EXPORT CAN0_3_IRQHandler [WEAK] + EXPORT CAN0_4_IRQHandler [WEAK] + EXPORT CAN0_5_IRQHandler [WEAK] + EXPORT CAN0_6_IRQHandler [WEAK] + EXPORT CAN0_7_IRQHandler [WEAK] + EXPORT USIC0_0_IRQHandler [WEAK] + EXPORT USIC0_1_IRQHandler [WEAK] + EXPORT USIC0_2_IRQHandler [WEAK] + EXPORT USIC0_3_IRQHandler [WEAK] + EXPORT USIC0_4_IRQHandler [WEAK] + EXPORT USIC0_5_IRQHandler [WEAK] + EXPORT USIC1_0_IRQHandler [WEAK] + EXPORT USIC1_1_IRQHandler [WEAK] + EXPORT USIC1_2_IRQHandler [WEAK] + EXPORT USIC1_3_IRQHandler [WEAK] + EXPORT USIC1_4_IRQHandler [WEAK] + EXPORT USIC1_5_IRQHandler [WEAK] + EXPORT USIC2_0_IRQHandler [WEAK] + EXPORT USIC2_1_IRQHandler [WEAK] + EXPORT USIC2_2_IRQHandler [WEAK] + EXPORT USIC2_3_IRQHandler [WEAK] + EXPORT USIC2_4_IRQHandler [WEAK] + EXPORT USIC2_5_IRQHandler [WEAK] + EXPORT LEDTS0_0_IRQHandler [WEAK] + EXPORT FCE0_0_IRQHandler [WEAK] + EXPORT GPDMA0_0_IRQHandler [WEAK] + EXPORT SDMMC0_0_IRQHandler [WEAK] + EXPORT USB0_0_IRQHandler [WEAK] + EXPORT ETH0_0_IRQHandler [WEAK] + EXPORT GPDMA1_0_IRQHandler [WEAK] + + +SCU_0_IRQHandler +ERU0_0_IRQHandler +ERU0_1_IRQHandler +ERU0_2_IRQHandler +ERU0_3_IRQHandler +ERU1_0_IRQHandler +ERU1_1_IRQHandler +ERU1_2_IRQHandler +ERU1_3_IRQHandler +PMU0_0_IRQHandler +VADC0_C0_0_IRQHandler +VADC0_C0_1_IRQHandler +VADC0_C0_2_IRQHandler +VADC0_C0_3_IRQHandler +VADC0_G0_0_IRQHandler +VADC0_G0_1_IRQHandler +VADC0_G0_2_IRQHandler +VADC0_G0_3_IRQHandler +VADC0_G1_0_IRQHandler +VADC0_G1_1_IRQHandler +VADC0_G1_2_IRQHandler +VADC0_G1_3_IRQHandler +VADC0_G2_0_IRQHandler +VADC0_G2_1_IRQHandler +VADC0_G2_2_IRQHandler +VADC0_G2_3_IRQHandler +VADC0_G3_0_IRQHandler +VADC0_G3_1_IRQHandler +VADC0_G3_2_IRQHandler +VADC0_G3_3_IRQHandler +DSD0_0_IRQHandler +DSD0_1_IRQHandler +DSD0_2_IRQHandler +DSD0_3_IRQHandler +DSD0_4_IRQHandler +DSD0_5_IRQHandler +DSD0_6_IRQHandler +DSD0_7_IRQHandler +DAC0_0_IRQHandler +DAC0_1_IRQHandler +CCU40_0_IRQHandler +CCU40_1_IRQHandler +CCU40_2_IRQHandler +CCU40_3_IRQHandler +CCU41_0_IRQHandler +CCU41_1_IRQHandler +CCU41_2_IRQHandler +CCU41_3_IRQHandler +CCU42_0_IRQHandler +CCU42_1_IRQHandler +CCU42_2_IRQHandler +CCU42_3_IRQHandler +CCU43_0_IRQHandler +CCU43_1_IRQHandler +CCU43_2_IRQHandler +CCU43_3_IRQHandler +CCU80_0_IRQHandler +CCU80_1_IRQHandler +CCU80_2_IRQHandler +CCU80_3_IRQHandler +CCU81_0_IRQHandler +CCU81_1_IRQHandler +CCU81_2_IRQHandler +CCU81_3_IRQHandler +POSIF0_0_IRQHandler +POSIF0_1_IRQHandler +POSIF1_0_IRQHandler +POSIF1_1_IRQHandler +CAN0_0_IRQHandler +CAN0_1_IRQHandler +CAN0_2_IRQHandler +CAN0_3_IRQHandler +CAN0_4_IRQHandler +CAN0_5_IRQHandler +CAN0_6_IRQHandler +CAN0_7_IRQHandler +USIC0_0_IRQHandler +USIC0_1_IRQHandler +USIC0_2_IRQHandler +USIC0_3_IRQHandler +USIC0_4_IRQHandler +USIC0_5_IRQHandler +USIC1_0_IRQHandler +USIC1_1_IRQHandler +USIC1_2_IRQHandler +USIC1_3_IRQHandler +USIC1_4_IRQHandler +USIC1_5_IRQHandler +USIC2_0_IRQHandler +USIC2_1_IRQHandler +USIC2_2_IRQHandler +USIC2_3_IRQHandler +USIC2_4_IRQHandler +USIC2_5_IRQHandler +LEDTS0_0_IRQHandler +FCE0_0_IRQHandler +GPDMA0_0_IRQHandler +SDMMC0_0_IRQHandler +USB0_0_IRQHandler +ETH0_0_IRQHandler +GPDMA1_0_IRQHandler + + +;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ + +;* Definition of the default weak SystemInit_DAVE3 function. +;* This function will be called by the CMSIS SystemInit function. +;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 +;* which will overule this weak definition + +;*SystemInit_DAVE3 +;* NOP +;* BX LR + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + + ENDIF + + ALIGN + END + +;******************* (C) COPYRIGHT 2011 Infineon Techonlogies *****END OF FILE***** + + -- 2.39.5