From 20d18d415da304c65ce4dd0da7d555f5160ff92b Mon Sep 17 00:00:00 2001 From: Tomas Vanek Date: Mon, 12 Mar 2018 23:42:23 +0100 Subject: [PATCH] tcl/target/stm32f7x: configure faster system clock in reset-init STM32F7xx devices need faster clock for flash programming over JTAG transport. Using reset default 16 MHz clock resulted in lot of DAP WAITs and substantial decrease of flashing performance. Adapted to the restructured dap support (see 2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f). Change-Id: Ida6915331dd924c9c0d08822fd94c04ad408cdc5 Signed-off-by: Tomas Vanek Reviewed-on: http://openocd.zylin.com/4464 Tested-by: jenkins Reviewed-by: Christopher Head --- tcl/target/stm32f7x.cfg | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg index dc310da4..98f3eea3 100755 --- a/tcl/target/stm32f7x.cfg +++ b/tcl/target/stm32f7x.cfg @@ -82,3 +82,27 @@ $_TARGETNAME configure -event trace-config { # assignment mmw 0xE0042004 0x00000020 0 } + +$_TARGETNAME configure -event reset-init { + # Configure PLL to boost clock to HSI x 10 (160 MHz) + mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P) + mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency) + mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON + sleep 10 ;# Wait for PLL to lock + mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2) + mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL + + # Boost SWD frequency + # Do not boost JTAG frequency and slow down JTAG memory access or flash write algo + # suffers from DAP WAITs + if {[using_jtag]} { + [[target current] cget -dap] memaccess 16 + } { + adapter_khz 8000 + } +} + +$_TARGETNAME configure -event reset-start { + # Reduce speed since CPU speed will slow down to 16MHz with the reset + adapter_khz 2000 +} -- 2.39.5