From 27cd0da41e7c2f10d754efba0d178a5715d12bc2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 May 2016 18:35:56 +0800 Subject: [PATCH] imx-common: use simpler runtime cpu dection macros MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Bhuvanchandra DV Cc: "Benoît Thébaudeau" --- arch/arm/imx-common/hab.c | 48 +++++++++------------------------- arch/arm/imx-common/init.c | 5 ++-- arch/arm/imx-common/iomux-v3.c | 2 +- arch/arm/imx-common/sata.c | 2 +- arch/arm/imx-common/timer.c | 11 +++----- 5 files changed, 20 insertions(+), 48 deletions(-) diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c index 1e4ed7ecd8..a980688338 100644 --- a/arch/arm/imx-common/hab.c +++ b/arch/arm/imx-common/hab.c @@ -17,65 +17,45 @@ #define hab_rvt_report_event_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ - ((is_cpu_type(MXC_CPU_MX6DL) || \ - is_cpu_type(MXC_CPU_MX6SOLO)) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \ ) #define hab_rvt_report_status_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ - ((is_cpu_type(MXC_CPU_MX6DL) || \ - is_cpu_type(MXC_CPU_MX6SOLO)) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \ ) #define hab_rvt_authenticate_image_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ - ((is_cpu_type(MXC_CPU_MX6DL) || \ - is_cpu_type(MXC_CPU_MX6SOLO)) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \ ) #define hab_rvt_entry_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ - ((is_cpu_type(MXC_CPU_MX6DL) || \ - is_cpu_type(MXC_CPU_MX6SOLO)) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \ ) #define hab_rvt_exit_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ - ((is_cpu_type(MXC_CPU_MX6DL) || \ - is_cpu_type(MXC_CPU_MX6SOLO)) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ ((hab_rvt_exit_t *)HAB_RVT_EXIT) \ ) @@ -429,8 +409,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) */ /* Check MMU enabled */ if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) { - if (is_cpu_type(MXC_CPU_MX6Q) || - is_cpu_type(MXC_CPU_MX6D)) { + if (is_mx6dq()) { /* * This won't work on Rev 1.0.0 of * i.MX6Q/D, since their ROM doesn't @@ -439,10 +418,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) */ if (!is_mx6dqp()) writel(1, MX6DQ_PU_IROM_MMU_EN_VAR); - } else if (is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO)) { + } else if (is_mx6sdl()) { writel(1, MX6DLS_PU_IROM_MMU_EN_VAR); - } else if (is_cpu_type(MXC_CPU_MX6SL)) { + } else if (is_mx6sl()) { writel(1, MX6SL_PU_IROM_MMU_EN_VAR); } } diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index 15dab1d904..3d2ce3a82e 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -44,7 +44,7 @@ void init_aips(void) writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4); - if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) { + if (is_mx6sx() || is_mx7()) { /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. @@ -78,8 +78,7 @@ void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog1->wmcr); writew(enable, &wdog2->wmcr); - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || - is_soc_type(MXC_SOC_MX7)) + if (is_mx6sx() || is_mx6ul() || is_mx7()) writew(enable, &wdog3->wmcr); #ifdef CONFIG_MX7D writew(enable, &wdog4->wmcr); diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 228d5f8f1c..66137d148a 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -83,7 +83,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, #if defined(CONFIG_MX6QDL) stride = 2; - if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + if (!is_mx6dq()) p += 1; #else stride = 1; diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c index d174a463f8..dd9698d3cd 100644 --- a/arch/arm/imx-common/sata.c +++ b/arch/arm/imx-common/sata.c @@ -15,7 +15,7 @@ int setup_sata(void) struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; - if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + if (!is_mx6dq()) return 1; ret = enable_sata_clock(); diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index 92c7218e69..bea17f2c6b 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -43,10 +43,8 @@ DECLARE_GLOBAL_DATA_PTR; static inline int gpt_has_clk_source_osc(void) { #if defined(CONFIG_MX6) - if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && - (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) || - is_cpu_type(MXC_CPU_MX6UL)) + if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || + is_mx6sdl() || is_mx6sx() || is_mx6ul()) return 1; return 0; @@ -86,10 +84,7 @@ int timer_init(void) i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */ - if (is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO) || - is_cpu_type(MXC_CPU_MX6SX) || - is_cpu_type(MXC_CPU_MX6UL)) { + if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) { i |= GPTCR_24MEN; /* Produce 3Mhz clock */ -- 2.39.5