From 312cc39e270170b37a992b2d57773c828dcb9c6b Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 10 Mar 2015 18:31:20 +0800 Subject: [PATCH] x86: quark: MRC codes clean up This patch cleans up the quark MRC codes coding style by: - Remove BIT0/1../31 defines from mrc_util.h - Create names for the documented BITs and use them - For undocumented single BITs, use (1 << n) directly - For undocumented ORed BITs, use the hex number directly - Remove redundancy parenthesis all over the codes - Replace to use lower case hex numbers Signed-off-by: Bin Meng --- arch/x86/cpu/quark/hte.c | 74 +- arch/x86/cpu/quark/hte.h | 4 +- arch/x86/cpu/quark/mrc.c | 12 +- arch/x86/cpu/quark/mrc_util.c | 326 +++++---- arch/x86/cpu/quark/mrc_util.h | 34 - arch/x86/cpu/quark/smc.c | 1205 +++++++++++++++------------------ arch/x86/cpu/quark/smc.h | 349 ++++++---- 7 files changed, 955 insertions(+), 1049 deletions(-) diff --git a/arch/x86/cpu/quark/hte.c b/arch/x86/cpu/quark/hte.c index 372815d8c1..db601e4efb 100644 --- a/arch/x86/cpu/quark/hte.c +++ b/arch/x86/cpu/quark/hte.c @@ -20,9 +20,9 @@ */ static void hte_enable_all_errors(void) { - msg_port_write(HTE, 0x000200A2, 0xFFFFFFFF); - msg_port_write(HTE, 0x000200A3, 0x000000FF); - msg_port_write(HTE, 0x000200A4, 0x00000000); + msg_port_write(HTE, 0x000200a2, 0xffffffff); + msg_port_write(HTE, 0x000200a3, 0x000000ff); + msg_port_write(HTE, 0x000200a4, 0x00000000); } /** @@ -32,7 +32,7 @@ static void hte_enable_all_errors(void) */ static u32 hte_check_errors(void) { - return msg_port_read(HTE, 0x000200A7); + return msg_port_read(HTE, 0x000200a7); } /** @@ -44,11 +44,11 @@ static void hte_wait_for_complete(void) ENTERFN(); - do {} while ((msg_port_read(HTE, 0x00020012) & BIT30) != 0); + do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0); tmp = msg_port_read(HTE, 0x00020011); - tmp |= BIT9; - tmp &= ~(BIT12 | BIT13); + tmp |= (1 << 9); + tmp &= ~((1 << 12) | (1 << 13)); msg_port_write(HTE, 0x00020011, tmp); LEAVEFN(); @@ -65,9 +65,9 @@ static void hte_clear_error_regs(void) * Clear all HTE errors and enable error checking * for burst and chunk. */ - tmp = msg_port_read(HTE, 0x000200A1); - tmp |= BIT8; - msg_port_write(HTE, 0x000200A1, tmp); + tmp = msg_port_read(HTE, 0x000200a1); + tmp |= (1 << 8); + msg_port_write(HTE, 0x000200a1, tmp); } /** @@ -91,25 +91,25 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr, u32 offset; if (first_run) { - msg_port_write(HTE, 0x00020020, 0x01B10021); + msg_port_write(HTE, 0x00020020, 0x01b10021); msg_port_write(HTE, 0x00020021, 0x06000000); msg_port_write(HTE, 0x00020022, addr >> 6); msg_port_write(HTE, 0x00020062, 0x00800015); - msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); - msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); - msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); + msg_port_write(HTE, 0x00020063, 0xaaaaaaaa); + msg_port_write(HTE, 0x00020064, 0xcccccccc); + msg_port_write(HTE, 0x00020065, 0xf0f0f0f0); msg_port_write(HTE, 0x00020061, 0x00030008); if (mode == WRITE_TRAIN) - pattern = 0xC33C0000; + pattern = 0xc33c0000; else /* READ_TRAIN */ - pattern = 0xAA5555AA; + pattern = 0xaa5555aa; - for (offset = 0x80; offset <= 0x8F; offset++) + for (offset = 0x80; offset <= 0x8f; offset++) msg_port_write(HTE, offset, pattern); } - msg_port_write(HTE, 0x000200A1, 0xFFFF1000); + msg_port_write(HTE, 0x000200a1, 0xffff1000); msg_port_write(HTE, 0x00020011, 0x00011000); msg_port_write(HTE, 0x00020011, 0x00011100); @@ -119,7 +119,7 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr, * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for * any bytelane errors. */ - return (hte_check_errors() >> 8) & 0xFF; + return (hte_check_errors() >> 8) & 0xff; } /** @@ -153,7 +153,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, msg_port_write(HTE, 0x00020024, 0x06070000); msg_port_write(HTE, 0x00020022, addr >> 6); msg_port_write(HTE, 0x00020025, addr >> 6); - msg_port_write(HTE, 0x00020062, 0x0000002A); + msg_port_write(HTE, 0x00020062, 0x0000002a); msg_port_write(HTE, 0x00020063, seed_victim); msg_port_write(HTE, 0x00020064, seed_aggressor); msg_port_write(HTE, 0x00020065, seed_victim); @@ -163,21 +163,21 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, * * Start with bit0 */ - for (offset = 0x80; offset <= 0x8F; offset++) { + for (offset = 0x80; offset <= 0x8f; offset++) { if ((offset % 8) == victim_bit) msg_port_write(HTE, offset, 0x55555555); else - msg_port_write(HTE, offset, 0xCCCCCCCC); + msg_port_write(HTE, offset, 0xcccccccc); } msg_port_write(HTE, 0x00020061, 0x00000000); msg_port_write(HTE, 0x00020066, 0x03440000); - msg_port_write(HTE, 0x000200A1, 0xFFFF1000); + msg_port_write(HTE, 0x000200a1, 0xffff1000); } tmp = 0x10001000 | (loop_cnt << 16); msg_port_write(HTE, 0x00020011, tmp); - msg_port_write(HTE, 0x00020011, tmp | BIT8); + msg_port_write(HTE, 0x00020011, tmp | (1 << 8)); hte_wait_for_complete(); @@ -185,7 +185,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for * any bytelane errors. */ - return (hte_check_errors() >> 8) & 0xFF; + return (hte_check_errors() >> 8) & 0xff; } /** @@ -219,14 +219,14 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag) msg_port_write(HTE, 0x00020062, 0x00000015); - for (offset = 0x80; offset <= 0x8F; offset++) - msg_port_write(HTE, offset, ((offset & 1) ? 0xA55A : 0x5AA5)); + for (offset = 0x80; offset <= 0x8f; offset++) + msg_port_write(HTE, offset, ((offset & 1) ? 0xa55a : 0x5aa5)); msg_port_write(HTE, 0x00020021, 0x00000000); msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1); - msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); - msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); - msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); + msg_port_write(HTE, 0x00020063, 0xaaaaaaaa); + msg_port_write(HTE, 0x00020064, 0xcccccccc); + msg_port_write(HTE, 0x00020065, 0xf0f0f0f0); msg_port_write(HTE, 0x00020066, 0x03000000); switch (flag) { @@ -243,7 +243,7 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag) break; default: DPF(D_INFO, "Unknown parameter for flag: %d\n", flag); - return 0xFFFFFFFF; + return 0xffffffff; } DPF(D_INFO, "hte_mem_init"); @@ -379,16 +379,16 @@ void hte_mem_op(u32 addr, u8 first_run, u8 is_write) msg_port_write(HTE, 0x00020021, 0x06000000); msg_port_write(HTE, 0x00020022, addr >> 6); msg_port_write(HTE, 0x00020062, 0x00800015); - msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); - msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); - msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); + msg_port_write(HTE, 0x00020063, 0xaaaaaaaa); + msg_port_write(HTE, 0x00020064, 0xcccccccc); + msg_port_write(HTE, 0x00020065, 0xf0f0f0f0); msg_port_write(HTE, 0x00020061, 0x00030008); - for (offset = 0x80; offset <= 0x8F; offset++) - msg_port_write(HTE, offset, 0xC33C0000); + for (offset = 0x80; offset <= 0x8f; offset++) + msg_port_write(HTE, offset, 0xc33c0000); } - msg_port_write(HTE, 0x000200A1, 0xFFFF1000); + msg_port_write(HTE, 0x000200a1, 0xffff1000); msg_port_write(HTE, 0x00020011, 0x00011000); msg_port_write(HTE, 0x00020011, 0x00011100); diff --git a/arch/x86/cpu/quark/hte.h b/arch/x86/cpu/quark/hte.h index 6577796fd6..e98c7ef41d 100644 --- a/arch/x86/cpu/quark/hte.h +++ b/arch/x86/cpu/quark/hte.h @@ -29,10 +29,10 @@ enum { #define HTE_LOOP_CNT 5 /* random seed for victim */ -#define HTE_LFSR_VICTIM_SEED 0xF294BA21 +#define HTE_LFSR_VICTIM_SEED 0xf294ba21 /* random seed for aggressor */ -#define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D +#define HTE_LFSR_AGRESSOR_SEED 0xeba7492d u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag); u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr, diff --git a/arch/x86/cpu/quark/mrc.c b/arch/x86/cpu/quark/mrc.c index 7eb34c5302..65734e9456 100644 --- a/arch/x86/cpu/quark/mrc.c +++ b/arch/x86/cpu/quark/mrc.c @@ -105,8 +105,8 @@ static void mrc_adjust_params(struct mrc_params *mrc_params) * Column: 11 for 8Gbx8, else 10 */ mrc_params->column_bits[0] = - ((dram_params[0].density == 4) && - (dram_width == X8)) ? (11) : (10); + (dram_params[0].density == 4) && + (dram_width == X8) ? 11 : 10; /* * Determine row bits: @@ -117,9 +117,9 @@ static void mrc_adjust_params(struct mrc_params *mrc_params) * 4Gbx16=15 4Gbx8=16 * 8Gbx16=16 8Gbx8=16 */ - mrc_params->row_bits[0] = 12 + (dram_params[0].density) + - (((dram_params[0].density < 4) && - (dram_width == X8)) ? (1) : (0)); + mrc_params->row_bits[0] = 12 + dram_params[0].density + + (dram_params[0].density < 4) && + (dram_width == X8) ? 1 : 0; /* * Determine per-channel memory size: @@ -137,7 +137,7 @@ static void mrc_adjust_params(struct mrc_params *mrc_params) * 4Gb x16 0x040000000 (1024MB) * 4Gb x8 0x080000000 (2048MB) */ - mrc_params->channel_size[0] = (1 << dram_params[0].density); + mrc_params->channel_size[0] = 1 << dram_params[0].density; mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1; mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1; mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2; diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index 3a79ae551b..49d803d794 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -18,14 +18,14 @@ static const uint8_t vref_codes[64] = { /* lowest to highest */ - 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, 0x38, + 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, - 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, 0x28, + 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f }; void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask) @@ -80,7 +80,7 @@ void select_mem_mgr(void) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT28; + dco &= ~DCO_PMICTL; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -94,7 +94,7 @@ void select_hte(void) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco |= BIT28; + dco |= DCO_PMICTL; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -151,26 +151,25 @@ void set_rcvn(uint8_t channel, uint8_t rank, * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); - msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) : - (BIT11 | BIT10 | BIT9 | BIT8); - temp = (byte_lane & BIT0) ? ((pi_count / HALF_CLK) << 20) : - ((pi_count / HALF_CLK) << 8); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; + msk = (byte_lane & 1) ? 0xf00000 : 0xf00; + temp = (byte_lane & 1) ? (pi_count / HALF_CLK) << 20 : + (pi_count / HALF_CLK) << 8; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x3f000000; temp = pi_count << 24; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -179,25 +178,25 @@ void set_rcvn(uint8_t channel, uint8_t rank, * BL0/1 -> B01DBCTL1[08/11] (+1 select) * BL0/1 -> B01DBCTL1[02/05] (enable) */ - reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (byte_lane & BIT0) ? BIT5 : BIT2; + msk |= (byte_lane & 1) ? (1 << 5) : (1 << 2); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & BIT0) ? BIT11 : BIT8; + msk |= (byte_lane & 1) ? (1 << 11) : (1 << 8); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) { + if (pi_count > 0x3f) { training_message(channel, rank, byte_lane); mrc_post_code(0xee, 0xe0); } @@ -224,11 +223,11 @@ uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); - temp >>= (byte_lane & BIT0) ? 20 : 8; - temp &= 0xF; + temp >>= (byte_lane & 1) ? 20 : 8; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -238,12 +237,12 @@ uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= 24; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -275,10 +274,10 @@ void set_rdqs(uint8_t channel, uint8_t rank, * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) */ - reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x7f; temp = pi_count << 0; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -310,13 +309,13 @@ uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) */ - reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); /* Adjust PI_COUNT */ - pi_count = temp & 0x7F; + pi_count = temp & 0x7f; LEAVEFN(); @@ -346,26 +345,25 @@ void set_wdqs(uint8_t channel, uint8_t rank, * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); - msk = (byte_lane & BIT0) ? (BIT19 | BIT18 | BIT17 | BIT16) : - (BIT7 | BIT6 | BIT5 | BIT4); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; + msk = (byte_lane & 1) ? 0xf0000 : 0xf0; temp = pi_count / HALF_CLK; - temp <<= (byte_lane & BIT0) ? 16 : 4; + temp <<= (byte_lane & 1) ? 16 : 4; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x3f0000; temp = pi_count << 16; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -374,25 +372,25 @@ void set_wdqs(uint8_t channel, uint8_t rank, * BL0/1 -> B01DBCTL1[07/10] (+1 select) * BL0/1 -> B01DBCTL1[01/04] (enable) */ - reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (byte_lane & BIT0) ? BIT4 : BIT1; + msk |= (byte_lane & 1) ? (1 << 4) : (1 << 1); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & BIT0) ? BIT10 : BIT7; + msk |= (byte_lane & 1) ? (1 << 10) : (1 << 7); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) { + if (pi_count > 0x3f) { training_message(channel, rank, byte_lane); mrc_post_code(0xee, 0xe2); } @@ -419,11 +417,11 @@ uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); - temp >>= (byte_lane & BIT0) ? 16 : 4; - temp &= 0xF; + temp >>= (byte_lane & 1) ? 16 : 4; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = (temp * HALF_CLK); @@ -433,12 +431,12 @@ uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= 16; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -471,26 +469,25 @@ void set_wdq(uint8_t channel, uint8_t rank, * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); - msk = (byte_lane & BIT0) ? (BIT15 | BIT14 | BIT13 | BIT12) : - (BIT3 | BIT2 | BIT1 | BIT0); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; + msk = (byte_lane & 1) ? 0xf000 : 0xf; temp = pi_count / HALF_CLK; - temp <<= (byte_lane & BIT0) ? 12 : 0; + temp <<= (byte_lane & 1) ? 12 : 0; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x3f00; temp = pi_count << 8; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -499,25 +496,25 @@ void set_wdq(uint8_t channel, uint8_t rank, * BL0/1 -> B01DBCTL1[06/09] (+1 select) * BL0/1 -> B01DBCTL1[00/03] (enable) */ - reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (byte_lane & BIT0) ? BIT3 : BIT0; + msk |= (byte_lane & 1) ? (1 << 3) : (1 << 0); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & BIT0) ? BIT9 : BIT6; + msk |= (byte_lane & 1) ? (1 << 9) : (1 << 6); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) { + if (pi_count > 0x3f) { training_message(channel, rank, byte_lane); mrc_post_code(0xee, 0xe3); } @@ -544,11 +541,11 @@ uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); - temp >>= (byte_lane & BIT0) ? (12) : (0); - temp &= 0xF; + temp >>= (byte_lane & 1) ? 12 : 0; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -558,12 +555,12 @@ uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= 8; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -589,14 +586,14 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) * RDPTR (1/2 MCLK, 64 PIs) * CMDPTRREG[11:08] (0x0-0xF) */ - reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT11 | BIT10 | BIT9 | BIT8); + reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET; + msk = 0xf00; temp = pi_count / HALF_CLK; temp <<= 8; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) @@ -609,18 +606,13 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) */ - reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); - - msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); - + reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; + msk = 0x3f3f3f3f; temp = (pi_count << 24) | (pi_count << 16) | (pi_count << 8) | (pi_count << 0); mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = CMDDLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); /* PO */ + reg = CMDDLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; /* PO */ mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* @@ -628,24 +620,24 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) * CMDCFGREG0[17] (+1 select) * CMDCFGREG0[16] (enable) */ - reg = CMDCFGREG0 + (channel * DDRIOCCC_CH_OFFSET); + reg = CMDCFGREG0 + channel * DDRIOCCC_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= BIT16; + msk |= (1 << 16); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= BIT17; + msk |= (1 << 17); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) + if (pi_count > 0x3f) mrc_post_code(0xee, 0xe4); LEAVEFN(); @@ -667,10 +659,10 @@ uint32_t get_wcmd(uint8_t channel) * RDPTR (1/2 MCLK, 64 PIs) * CMDPTRREG[11:08] (0x0-0xF) */ - reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET); + reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 8; - temp &= 0xF; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -686,10 +678,10 @@ uint32_t get_wcmd(uint8_t channel) * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) */ - reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); + reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 16; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -716,13 +708,13 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCPTRREG[15:12] -> CLK1 (0x0-0xF) * CCPTRREG[11:08] -> CLK0 (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; + msk = 0xff00; temp = ((pi_count / HALF_CLK) << 12) | ((pi_count / HALF_CLK) << 8); mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) @@ -731,16 +723,18 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) */ reg = rank ? ECCB1DLLPICODER0 : ECCB1DLLPICODER0; reg += (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); + msk = 0x3f3f00; temp = (pi_count << 16) | (pi_count << 8); mrc_alt_write_mask(DDRPHY, reg, temp, msk); + reg = rank ? ECCB1DLLPICODER1 : ECCB1DLLPICODER1; reg += (channel * DDRIOCCC_CH_OFFSET); mrc_alt_write_mask(DDRPHY, reg, temp, msk); + reg = rank ? ECCB1DLLPICODER2 : ECCB1DLLPICODER2; reg += (channel * DDRIOCCC_CH_OFFSET); mrc_alt_write_mask(DDRPHY, reg, temp, msk); + reg = rank ? ECCB1DLLPICODER3 : ECCB1DLLPICODER3; reg += (channel * DDRIOCCC_CH_OFFSET); mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -750,24 +744,24 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCCFGREG1[11:08] (+1 select) * CCCFGREG1[03:00] (enable) */ - reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET); + reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (BIT3 | BIT2 | BIT1 | BIT0); + msk |= 0xf; if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (BIT11 | BIT10 | BIT9 | BIT8); + msk |= 0xf00; if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) + if (pi_count > 0x3f) mrc_post_code(0xee, 0xe5); LEAVEFN(); @@ -790,10 +784,10 @@ uint32_t get_wclk(uint8_t channel, uint8_t rank) * CCPTRREG[15:12] -> CLK1 (0x0-0xF) * CCPTRREG[11:08] -> CLK0 (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= rank ? 12 : 8; - temp &= 0xF; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -807,7 +801,7 @@ uint32_t get_wclk(uint8_t channel, uint8_t rank) reg += (channel * DDRIOCCC_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= rank ? 16 : 8; - temp &= 0x3F; + temp &= 0x3f; pi_count += temp; @@ -835,28 +829,31 @@ void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCPTRREG[31:28] (0x0-0xF) * CCPTRREG[27:24] (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; + msk = 0xff000000; temp = ((pi_count / HALF_CLK) << 28) | ((pi_count / HALF_CLK) << 24); mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) */ - reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; + msk = 0x3f000000; temp = (pi_count << 24); mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = ECCB1DLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); + + reg = ECCB1DLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = ECCB1DLLPICODER2 + (channel * DDRIOCCC_CH_OFFSET); + + reg = ECCB1DLLPICODER2 + channel * DDRIOCCC_CH_OFFSET; mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = ECCB1DLLPICODER3 + (channel * DDRIOCCC_CH_OFFSET); + + reg = ECCB1DLLPICODER3 + channel * DDRIOCCC_CH_OFFSET; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* @@ -864,24 +861,24 @@ void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCCFGREG1[13:12] (+1 select) * CCCFGREG1[05:04] (enable) */ - reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET); + reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (BIT5 | BIT4); + msk |= 0x30; if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (BIT13 | BIT12); + msk |= 0x3000; if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) + if (pi_count > 0x3f) mrc_post_code(0xee, 0xe6); LEAVEFN(); @@ -906,10 +903,10 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank) * CCPTRREG[31:28] (0x0-0xF) * CCPTRREG[27:24] (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 24; - temp &= 0xF; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -919,10 +916,10 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) */ - reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); + reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 24; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -938,17 +935,16 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank) */ void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting) { - uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL); + uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL; ENTERFN(); DPF(D_TRN, "Vref ch%d ln%d : val=%03X\n", channel, byte_lane, setting); - mrc_alt_write_mask(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) + - ((byte_lane >> 1) * DDRIODQ_BL_OFFSET)), - (vref_codes[setting] << 2), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + mrc_alt_write_mask(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET + + (byte_lane >> 1) * DDRIODQ_BL_OFFSET, + vref_codes[setting] << 2, 0xfc); /* * need to wait ~300ns for Vref to settle @@ -969,15 +965,15 @@ uint32_t get_vref(uint8_t channel, uint8_t byte_lane) { uint8_t j; uint32_t ret_val = sizeof(vref_codes) / 2; - uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL); + uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL; uint32_t temp; ENTERFN(); - temp = msg_port_alt_read(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) + - ((byte_lane >> 1) * DDRIODQ_BL_OFFSET))); + temp = msg_port_alt_read(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET + + (byte_lane >> 1) * DDRIODQ_BL_OFFSET); temp >>= 2; - temp &= 0x3F; + temp &= 0x3f; for (j = 0; j < sizeof(vref_codes); j++) { if (vref_codes[j] == temp) { @@ -997,7 +993,7 @@ uint32_t get_vref(uint8_t channel, uint8_t byte_lane) */ uint32_t get_addr(uint8_t channel, uint8_t rank) { - uint32_t offset = 0x02000000; /* 32MB */ + uint32_t offset = 32 * 1024 * 1024; /* 32MB */ /* Begin product specific code */ if (channel > 0) { @@ -1040,8 +1036,8 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, uint32_t address = get_addr(channel, rank); /* initialise msk[] */ - msk[0] = rcvn ? BIT1 : BIT9; /* BL0 */ - msk[1] = rcvn ? BIT0 : BIT8; /* BL1 */ + msk[0] = rcvn ? (1 << 1) : (1 << 9); /* BL0 */ + msk[1] = rcvn ? (1 << 0) : (1 << 8); /* BL1 */ /* cycle through each byte lane group */ for (bl_grp = 0; bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { @@ -1056,9 +1052,9 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, * DQTRAINSTS register */ sampled_val[j] = msg_port_alt_read(DDRPHY, - (DQTRAINSTS + - (bl_grp * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET))); + DQTRAINSTS + + bl_grp * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); } /* @@ -1076,7 +1072,7 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, num_0s++; } if (num_1s > num_0s) - ret_val |= (1 << (bl + (bl_grp * 2))); + ret_val |= (1 << (bl + bl_grp * 2)); } } @@ -1116,10 +1112,10 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], /* increase sample delay by 26 PI (0.2 CLK) */ if (rcvn) { set_rcvn(channel, rank, bl, - delay[bl] + (sample * SAMPLE_DLY)); + delay[bl] + sample * SAMPLE_DLY); } else { set_wdqs(channel, rank, bl, - delay[bl] + (sample * SAMPLE_DLY)); + delay[bl] + sample * SAMPLE_DLY); } } @@ -1129,7 +1125,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], DPF(D_TRN, "Find rising edge %s ch%d rnk%d: #%d dly=%d dqs=%02X\n", - (rcvn ? "RCVN" : "WDQS"), channel, rank, sample, + rcvn ? "RCVN" : "WDQS", channel, rank, sample, sample * SAMPLE_DLY, sample_result[sample]); } @@ -1137,7 +1133,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], * This pattern will help determine where we landed and ultimately * how to place RCVEN/WDQS. */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* build transition_pattern (MSB is 1st sample) */ transition_pattern = 0; for (sample = 0; sample < SAMPLE_CNT; sample++) { @@ -1202,7 +1198,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], /* take a sample */ temp = sample_dqs(mrc_params, channel, rank, rcvn); /* check all each byte lane for proper edge */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (temp & (1 << bl)) { /* sampled "1" */ if (direction[bl] == BACKWARD) { @@ -1340,10 +1336,10 @@ void lfsr32(uint32_t *lfsr_ptr) lfsr = *lfsr_ptr; for (i = 0; i < 32; i++) { - bit = 1 ^ (lfsr & BIT0); - bit = bit ^ ((lfsr & BIT1) >> 1); - bit = bit ^ ((lfsr & BIT2) >> 2); - bit = bit ^ ((lfsr & BIT22) >> 22); + bit = 1 ^ (lfsr & 1); + bit = bit ^ ((lfsr & 2) >> 1); + bit = bit ^ ((lfsr & 4) >> 2); + bit = bit ^ ((lfsr & 0x400000) >> 22); lfsr = ((lfsr >> 1) | (bit << 31)); } @@ -1362,16 +1358,16 @@ void clear_pointers(void) for (channel = 0; channel < NUM_CHANNELS; channel++) { for (bl = 0; bl < NUM_BYTE_LANES; bl++) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (channel * DDRIODQ_CH_OFFSET) + - ((bl >> 1) * DDRIODQ_BL_OFFSET)), - ~BIT8, BIT8); + B01PTRCTL1 + + channel * DDRIODQ_CH_OFFSET + + (bl >> 1) * DDRIODQ_BL_OFFSET, + ~(1 << 8), (1 << 8)); mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (channel * DDRIODQ_CH_OFFSET) + - ((bl >> 1) * DDRIODQ_BL_OFFSET)), - BIT8, BIT8); + B01PTRCTL1 + + channel * DDRIODQ_CH_OFFSET + + (bl >> 1) * DDRIODQ_BL_OFFSET, + (1 << 8), (1 << 8)); } } @@ -1412,7 +1408,7 @@ static void print_timings_internal(uint8_t algo, uint8_t channel, uint8_t rank, break; } - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { switch (algo) { case RCVN: DPF(D_INFO, " %03d", get_rcvn(channel, rank, bl)); diff --git a/arch/x86/cpu/quark/mrc_util.h b/arch/x86/cpu/quark/mrc_util.h index f0ddbce3c5..a63d1f91e9 100644 --- a/arch/x86/cpu/quark/mrc_util.h +++ b/arch/x86/cpu/quark/mrc_util.h @@ -41,40 +41,6 @@ #define LEAVEFN(...) debug_cond(D_FCALL, "\n", __func__) #define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__) -/* Generic Register Bits */ -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - /* Message Bus Port */ #define MEM_CTLR 0x01 #define HOST_BRIDGE 0x03 diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c index e34bec4c80..3ffe92b67b 100644 --- a/arch/x86/cpu/quark/smc.c +++ b/arch/x86/cpu/quark/smc.c @@ -60,7 +60,7 @@ void clear_self_refresh(struct mrc_params *mrc_params) ENTERFN(); /* clear the PMSTS Channel Self Refresh bits */ - mrc_write_mask(MEM_CTLR, PMSTS, BIT0, BIT0); + mrc_write_mask(MEM_CTLR, PMSTS, PMSTS_DISR, PMSTS_DISR); LEAVEFN(); } @@ -101,47 +101,47 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) wl = 5 + mrc_params->ddr_speed; - dtr0 &= ~(BIT0 | BIT1); + dtr0 &= ~DTR0_DFREQ_MASK; dtr0 |= mrc_params->ddr_speed; - dtr0 &= ~(BIT12 | BIT13 | BIT14); + dtr0 &= ~DTR0_TCL_MASK; tmp1 = tcl - 5; dtr0 |= ((tcl - 5) << 12); - dtr0 &= ~(BIT4 | BIT5 | BIT6 | BIT7); + dtr0 &= ~DTR0_TRP_MASK; dtr0 |= ((trp - 5) << 4); /* 5 bit DRAM Clock */ - dtr0 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr0 &= ~DTR0_TRCD_MASK; dtr0 |= ((trcd - 5) << 8); /* 5 bit DRAM Clock */ - dtr1 &= ~(BIT0 | BIT1 | BIT2); + dtr1 &= ~DTR1_TWCL_MASK; tmp2 = wl - 3; dtr1 |= (wl - 3); - dtr1 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr1 &= ~DTR1_TWTP_MASK; dtr1 |= ((wl + 4 + twr - 14) << 8); /* Change to tWTP */ - dtr1 &= ~(BIT28 | BIT29 | BIT30); + dtr1 &= ~DTR1_TRTP_MASK; dtr1 |= ((MMAX(trtp, 4) - 3) << 28); /* 4 bit DRAM Clock */ - dtr1 &= ~(BIT24 | BIT25); + dtr1 &= ~DTR1_TRRD_MASK; dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */ - dtr1 &= ~(BIT4 | BIT5); + dtr1 &= ~DTR1_TCMD_MASK; dtr1 |= (1 << 4); - dtr1 &= ~(BIT20 | BIT21 | BIT22 | BIT23); + dtr1 &= ~DTR1_TRAS_MASK; dtr1 |= ((tras - 14) << 20); /* 6 bit DRAM Clock */ - dtr1 &= ~(BIT16 | BIT17 | BIT18 | BIT19); + dtr1 &= ~DTR1_TFAW_MASK; dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */ /* Set 4 Clock CAS to CAS delay (multi-burst) */ - dtr1 &= ~(BIT12 | BIT13); + dtr1 &= ~DTR1_TCCD_MASK; - dtr2 &= ~(BIT0 | BIT1 | BIT2); + dtr2 &= ~DTR2_TRRDR_MASK; dtr2 |= 1; - dtr2 &= ~(BIT8 | BIT9 | BIT10); + dtr2 &= ~DTR2_TWWDR_MASK; dtr2 |= (2 << 8); - dtr2 &= ~(BIT16 | BIT17 | BIT18 | BIT19); + dtr2 &= ~DTR2_TRWDR_MASK; dtr2 |= (2 << 16); - dtr3 &= ~(BIT0 | BIT1 | BIT2); + dtr3 &= ~DTR3_TWRDR_MASK; dtr3 |= 2; - dtr3 &= ~(BIT4 | BIT5 | BIT6); + dtr3 &= ~DTR3_TXXXX_MASK; dtr3 |= (2 << 4); - dtr3 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr3 &= ~DTR3_TRWSR_MASK; if (mrc_params->ddr_speed == DDRFREQ_800) { /* Extended RW delay (+1) */ dtr3 |= ((tcl - 5 + 1) << 8); @@ -150,24 +150,24 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) dtr3 |= ((tcl - 5 + 1) << 8); } - dtr3 &= ~(BIT13 | BIT14 | BIT15 | BIT16); + dtr3 &= ~DTR3_TWRSR_MASK; dtr3 |= ((4 + wl + twtr - 11) << 13); - dtr3 &= ~(BIT22 | BIT23); + dtr3 &= ~DTR3_TXP_MASK; if (mrc_params->ddr_speed == DDRFREQ_800) dtr3 |= ((MMAX(0, 1 - 1)) << 22); else dtr3 |= ((MMAX(0, 2 - 1)) << 22); - dtr4 &= ~(BIT0 | BIT1); + dtr4 &= ~DTR4_WRODTSTRT_MASK; dtr4 |= 1; - dtr4 &= ~(BIT4 | BIT5 | BIT6); + dtr4 &= ~DTR4_WRODTSTOP_MASK; dtr4 |= (1 << 4); - dtr4 &= ~(BIT8 | BIT9 | BIT10); + dtr4 &= ~DTR4_XXXX1_MASK; dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8); - dtr4 &= ~(BIT12 | BIT13 | BIT14); + dtr4 &= ~DTR4_XXXX2_MASK; dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12); - dtr4 &= ~(BIT15 | BIT16); + dtr4 &= ~(DTR4_ODTDIS | DTR4_TRGSTRDIS); msg_port_write(MEM_CTLR, DTR0, dtr0); msg_port_write(MEM_CTLR, DTR1, dtr1); @@ -191,25 +191,25 @@ void prog_decode_before_jedec(struct mrc_params *mrc_params) /* Disable power saving features */ dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 |= (BIT24 | BIT25); - dpmc0 &= ~(BIT16 | BIT17 | BIT18); - dpmc0 &= ~BIT23; + dpmc0 |= (DPMC0_CLKGTDIS | DPMC0_DISPWRDN); + dpmc0 &= ~DPMC0_PCLSTO_MASK; + dpmc0 &= ~DPMC0_DYNSREN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); /* Disable out of order transactions */ dsch = msg_port_read(MEM_CTLR, DSCH); - dsch |= (BIT8 | BIT12); + dsch |= (DSCH_OOODIS | DSCH_NEWBYPDIS); msg_port_write(MEM_CTLR, DSCH, dsch); /* Disable issuing the REF command */ drfc = msg_port_read(MEM_CTLR, DRFC); - drfc &= ~(BIT12 | BIT13 | BIT14); + drfc &= ~DRFC_TREFI_MASK; msg_port_write(MEM_CTLR, DRFC, drfc); /* Disable ZQ calibration short */ dcal = msg_port_read(MEM_CTLR, DCAL); - dcal &= ~(BIT8 | BIT9 | BIT10); - dcal &= ~(BIT12 | BIT13); + dcal &= ~DCAL_ZQCINT_MASK; + dcal &= ~DCAL_SRXZQCL_MASK; msg_port_write(MEM_CTLR, DCAL, dcal); /* @@ -218,9 +218,9 @@ void prog_decode_before_jedec(struct mrc_params *mrc_params) */ drp = 0; if (mrc_params->rank_enables & 1) - drp |= BIT0; + drp |= DRP_RKEN0; if (mrc_params->rank_enables & 2) - drp |= BIT1; + drp |= DRP_RKEN1; msg_port_write(MEM_CTLR, DRP, drp); LEAVEFN(); @@ -238,14 +238,14 @@ void perform_ddr_reset(struct mrc_params *mrc_params) ENTERFN(); /* Set COLDWAKE bit before sending the WAKE message */ - mrc_write_mask(MEM_CTLR, DRMC, BIT16, BIT16); + mrc_write_mask(MEM_CTLR, DRMC, DRMC_COLDWAKE, DRMC_COLDWAKE); /* Send wake command to DUNIT (MUST be done before JEDEC) */ dram_wake_command(); /* Set default value */ msg_port_write(MEM_CTLR, DRMC, - (mrc_params->rd_odt_value == 0 ? BIT12 : 0)); + mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0); LEAVEFN(); } @@ -263,7 +263,7 @@ void ddrphy_init(struct mrc_params *mrc_params) uint8_t bl_grp; /* byte lane group counter (2 BLs per module) */ uint8_t bl_divisor = 1; /* byte lane divisor */ /* For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333 */ - uint8_t speed = mrc_params->ddr_speed & (BIT1 | BIT0); + uint8_t speed = mrc_params->ddr_speed & 3; uint8_t cas; uint8_t cwl; @@ -286,21 +286,21 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* Deassert DDRPHY Initialization Complete */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT20, BIT20); /* SPID_INIT_COMPLETE=0 */ + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 20), 1 << 20); /* SPID_INIT_COMPLETE=0 */ /* Deassert IOBUFACT */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT2, BIT2); /* IOBUFACTRST_N=0 */ + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 2), 1 << 2); /* IOBUFACTRST_N=0 */ /* Disable WRPTR */ mrc_alt_write_mask(DDRPHY, - (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT0, BIT0); /* WRPTRENABLE=0 */ + CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 0), 1 << 0); /* WRPTRENABLE=0 */ } } /* Put PHY in reset */ - mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, BIT0); + mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, 1); /* Initialize DQ01, DQ23, CMD, CLK-CTL, COMP modules */ @@ -310,14 +310,14 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { /* Analog MUX select - IO2xCLKSEL */ mrc_alt_write_mask(DDRPHY, - (DQOBSCKEBBCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((bl_grp) ? (0x00) : (BIT22)), (BIT22)); + DQOBSCKEBBCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + bl_grp ? 0 : (1 << 22), 1 << 22); /* ODT Strength */ switch (mrc_params->rd_odt_value) { @@ -337,20 +337,20 @@ void ddrphy_init(struct mrc_params *mrc_params) /* ODT strength */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (temp << 5), (BIT6 | BIT5)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp << 5, 0x60); /* ODT strength */ mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (temp << 5), (BIT6 | BIT5)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp << 5, 0x60); /* Dynamic ODT/DIFFAMP */ - temp = (((cas) << 24) | ((cas) << 16) | - ((cas) << 8) | ((cas) << 0)); + temp = (cas << 24) | (cas << 16) | + (cas << 8) | (cas << 0); switch (speed) { case 0: temp -= 0x01010101; @@ -368,247 +368,199 @@ void ddrphy_init(struct mrc_params *mrc_params) /* Launch Time: ODT, DIFFAMP, ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B01LATCTL1 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + B01LATCTL1 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x1f1f1f1f); switch (speed) { /* HSD#234715 */ case 0: - temp = ((0x06 << 16) | (0x07 << 8)); + temp = (0x06 << 16) | (0x07 << 8); break; /* 800 */ case 1: - temp = ((0x07 << 16) | (0x08 << 8)); + temp = (0x07 << 16) | (0x08 << 8); break; /* 1066 */ case 2: - temp = ((0x09 << 16) | (0x0A << 8)); + temp = (0x09 << 16) | (0x0a << 8); break; /* 1333 */ case 3: - temp = ((0x0A << 16) | (0x0B << 8)); + temp = (0x0a << 16) | (0x0b << 8); break; /* 1600 */ } /* On Duration: ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B0ONDURCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8)); + B0ONDURCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003f3f00); /* On Duration: ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B1ONDURCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8)); + B1ONDURCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003f3f00); switch (mrc_params->rd_odt_value) { case 0: /* override DIFFAMP=on, ODT=off */ - temp = ((0x3F << 16) | (0x3f << 10)); + temp = (0x3f << 16) | (0x3f << 10); break; default: /* override DIFFAMP=on, ODT=on */ - temp = ((0x3F << 16) | (0x2A << 10)); + temp = (0x3f << 16) | (0x2a << 10); break; } /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | - BIT11 | BIT10)); + B0OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003ffc00); /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B1OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | - BIT11 | BIT10)); + B1OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003ffc00); /* DLL Setup */ /* 1xCLK Domain Timings: tEDP,RCVEN,WDQS (PO) */ mrc_alt_write_mask(DDRPHY, - (B0LATCTL0 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (((cas + 7) << 16) | ((cas - 4) << 8) | - ((cwl - 2) << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT12 | BIT11 | BIT10 | BIT9 | - BIT8 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + B0LATCTL0 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + ((cas + 7) << 16) | ((cas - 4) << 8) | + ((cwl - 2) << 0), 0x003f1f1f); mrc_alt_write_mask(DDRPHY, - (B1LATCTL0 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (((cas + 7) << 16) | ((cas - 4) << 8) | - ((cwl - 2) << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT12 | BIT11 | BIT10 | BIT9 | - BIT8 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + B1LATCTL0 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + ((cas + 7) << 16) | ((cas - 4) << 8) | + ((cwl - 2) << 0), 0x003f1f1f); /* RCVEN Bypass (PO) */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x0 << 7) | (0x0 << 0)), - (BIT7 | BIT0)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x81); mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x0 << 7) | (0x0 << 0)), - (BIT7 | BIT0)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x81); /* TX */ mrc_alt_write_mask(DDRPHY, - (DQCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT16), (BIT16)); + DQCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 16, 1 << 16); mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT8), (BIT8)); + B01PTRCTL1 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 8, 1 << 8); /* RX (PO) */ /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ mrc_alt_write_mask(DDRPHY, - (B0VREFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + B0VREFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + (0x03 << 2) | (0x0 << 1) | (0x0 << 0), + 0xff); /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ mrc_alt_write_mask(DDRPHY, - (B1VREFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + B1VREFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + (0x03 << 2) | (0x0 << 1) | (0x0 << 0), + 0xff); /* Per-Bit De-Skew Enable */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (0), (BIT4)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x10); /* Per-Bit De-Skew Enable */ mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (0), (BIT4)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x10); } /* CLKEBB */ mrc_alt_write_mask(DDRPHY, - (CMDOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)), - 0, (BIT23)); + CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, + 0, 1 << 23); /* Enable tristate control of cmd/address bus */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - 0, (BIT1 | BIT0)); + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 0, 0x03); /* ODT RCOMP */ mrc_alt_write_mask(DDRPHY, - (CMDRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)), - ((0x03 << 5) | (0x03 << 0)), - (BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET, + (0x03 << 5) | (0x03 << 0), 0x3ff); /* CMDPM* registers must be programmed in this order */ /* Turn On Delays: SFR (regulator), MPLL */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG4 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFFFU << 16) | (0xFFFF << 0)), - 0xFFFFFFFF); + CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* * Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, * VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT * for_PM_MSG_gt0, MDLL Turn On */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG3 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFU << 28) | (0xFFF << 16) | (0xF << 12) | - (0x616 << 0)), 0xFFFFFFFF); + CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET, + 0xfffff616, 0xffffffff); /* MPLL Divider Reset Delays */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG2 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Turn Off Delays: VREG, Staggered MDLL, MDLL, PI */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG1 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG0 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Allow PUnit signals */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x6 << 8) | BIT6 | (0x4 << 0)), - (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | - BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT11 | - BIT10 | BIT9 | BIT8 | BIT6 | BIT3 | BIT2 | - BIT1 | BIT0)); + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + (0x6 << 8) | (0x1 << 6) | (0x4 << 0), + 0xffe00f4f); /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - ((0x3 << 4) | (0x7 << 0)), - (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + (0x3 << 4) | (0x7 << 0), 0x7f); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)), - 0, BIT24); /* CLKEBB */ + CCOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, + 0, 1 << 24); /* CLKEBB */ /* Buffer Enable: CS,CKE,ODT,CLK */ mrc_alt_write_mask(DDRPHY, - (CCCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x0 << 16) | (0x0 << 12) | (0x0 << 8) | - (0xF << 4) | BIT0), - (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT7 | BIT6 | BIT5 | BIT4 | BIT0)); + CCCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 0x1f, 0x000ffff1); /* ODT RCOMP */ mrc_alt_write_mask(DDRPHY, - (CCRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)), - ((0x03 << 8) | (0x03 << 0)), - (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + CCRCOMPODT + ch * DDRIOCCC_CH_OFFSET, + (0x03 << 8) | (0x03 << 0), 0x00001f1f); /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - ((0x3 << 4) | (0x7 << 0)), - (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + (0x3 << 4) | (0x7 << 0), 0x7f); /* * COMP (RON channel specific) @@ -618,66 +570,43 @@ void ddrphy_init(struct mrc_params *mrc_params) */ /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x08 << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x08 << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CMDVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0C << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CMDVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0C << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0F << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0F << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x08 << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x08 << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CTLVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0C << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CTLVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0C << 24) | (0x03 << 16), 0x3f3f0000); /* DQS Swapped Input Enable */ mrc_alt_write_mask(DDRPHY, - (COMPEN1CH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT19 | BIT17), - (BIT31 | BIT30 | BIT19 | BIT17 | - BIT15 | BIT14)); + COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 19) | (1 << 17), 0xc00ac000); /* ODT VREF = 1.5 x 274/360+274 = 0.65V (code of ~50) */ /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x32 << 8) | (0x03 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x32 << 8) | (0x03 << 0), 0x00003f3f); /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x32 << 8) | (0x03 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x32 << 8) | (0x03 << 0), 0x00003f3f); /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0E << 8) | (0x05 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0E << 8) | (0x05 << 0), 0x00003f3f); /* * Slew rate settings are frequency specific, @@ -685,273 +614,227 @@ void ddrphy_init(struct mrc_params *mrc_params) * - DQ/DQS/DM/CLK SR: 4V/ns, * - CTRL/CMD SR: 1.5V/ns */ - temp = (0x0E << 16) | (0x0E << 12) | (0x08 << 8) | - (0x0B << 4) | (0x0B << 0); + temp = (0x0e << 16) | (0x0e << 12) | (0x08 << 8) | + (0x0b << 4) | (0x0b << 0); /* DCOMP Delay Select: CTL,CMD,CLK,DQS,DQ */ mrc_alt_write_mask(DDRPHY, - (DLYSELCH0 + (ch * DDRCOMP_CH_OFFSET)), - temp, - (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | - BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + DLYSELCH0 + ch * DDRCOMP_CH_OFFSET, + temp, 0x000fffff); /* TCO Vref CLK,DQS,DQ */ mrc_alt_write_mask(DDRPHY, - (TCOVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x05 << 16) | (0x05 << 8) | (0x05 << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT5 | BIT4 | BIT3 | BIT2 | - BIT1 | BIT0)); + TCOVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x05 << 16) | (0x05 << 8) | (0x05 << 0), + 0x003f3f3f); /* ODTCOMP CMD/CTL PU/PD */ mrc_alt_write_mask(DDRPHY, - (CCBUFODTCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x03 << 8) | (0x03 << 0)), - (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + CCBUFODTCH0 + ch * DDRCOMP_CH_OFFSET, + (0x03 << 8) | (0x03 << 0), + 0x00001f1f); /* COMP */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - 0, (BIT31 | BIT30 | BIT8)); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + 0, 0xc0000100); #ifdef BACKUP_COMPS /* DQ COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* DQS COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* CLK COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0C << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0c << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0C << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0c << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x07 << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x07 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x07 << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x07 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* CMD COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CMDDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CMDDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CMDDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CMDDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* CTL COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CTLDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CTLDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CTLDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CTLDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); #else /* DQ TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* DQS TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* CLK TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); #endif /* program STATIC delays */ @@ -962,7 +845,7 @@ void ddrphy_init(struct mrc_params *mrc_params) #endif for (rk = 0; rk < NUM_RANKS; rk++) { - if (mrc_params->rank_enables & (1<rank_enables & (1 << rk)) { set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]); #ifdef BACKUP_WCTL set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]); @@ -976,86 +859,80 @@ void ddrphy_init(struct mrc_params *mrc_params) /* COMP (non channel specific) */ /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADRVPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANAODTPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANAODTPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANAODTPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADLYPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANATCOPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANATCOPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANATCOPDCTL, 1 << 30, 1 << 30); /* TCOCOMP: Pulse Count */ - mrc_alt_write_mask(DDRPHY, (TCOCNTCTRL), (0x1 << 0), (BIT1 | BIT0)); + mrc_alt_write_mask(DDRPHY, TCOCNTCTRL, 1, 3); /* ODT: CMD/CTL PD/PU */ - mrc_alt_write_mask(DDRPHY, - (CHNLBUFSTATIC), ((0x03 << 24) | (0x03 << 16)), - (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT20 | BIT19 | BIT18 | BIT17 | BIT16)); + mrc_alt_write_mask(DDRPHY, CHNLBUFSTATIC, + (0x03 << 24) | (0x03 << 16), 0x1f1f0000); /* Set 1us counter */ - mrc_alt_write_mask(DDRPHY, - (MSCNTR), (0x64 << 0), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); - mrc_alt_write_mask(DDRPHY, - (LATCH1CTL), (0x1 << 28), - (BIT30 | BIT29 | BIT28)); + mrc_alt_write_mask(DDRPHY, MSCNTR, 0x64, 0xff); + mrc_alt_write_mask(DDRPHY, LATCH1CTL, 0x1 << 28, 0x70000000); /* Release PHY from reset */ - mrc_alt_write_mask(DDRPHY, MASTERRSTN, BIT0, BIT0); + mrc_alt_write_mask(DDRPHY, MASTERRSTN, 1, 1); /* STEP1 */ mrc_post_code(0x03, 0x11); @@ -1064,30 +941,30 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { mrc_alt_write_mask(DDRPHY, - (DQMDLLCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT13), - (BIT13)); /* Enable VREG */ + DQMDLLCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 13, + 1 << 13); /* Enable VREG */ delay_n(3); } /* ECC */ - mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL), - (BIT13), (BIT13)); /* Enable VREG */ + mrc_alt_write_mask(DDRPHY, ECCMDLLCTL, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); /* CMD */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT13), (BIT13)); /* Enable VREG */ + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT13), (BIT13)); /* Enable VREG */ + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); } } @@ -1100,30 +977,30 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { mrc_alt_write_mask(DDRPHY, - (DQMDLLCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT17), - (BIT17)); /* Enable MCDLL */ + DQMDLLCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 17, + 1 << 17); /* Enable MCDLL */ delay_n(50); } /* ECC */ - mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL), - (BIT17), (BIT17)); /* Enable MCDLL */ + mrc_alt_write_mask(DDRPHY, ECCMDLLCTL, + 1 << 17, 1 << 17); /* Enable MCDLL */ delay_n(50); /* CMD */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT18), (BIT18)); /* Enable MCDLL */ + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 18, 1 << 18); /* Enable MCDLL */ delay_n(50); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT18), (BIT18)); /* Enable MCDLL */ + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 18, 1 << 18); /* Enable MCDLL */ delay_n(50); } } @@ -1136,54 +1013,47 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { #ifdef FORCE_16BIT_DDRIO - temp = ((bl_grp) && + temp = (bl_grp && (mrc_params->channel_width == X16)) ? - ((0x1 << 12) | (0x1 << 8) | - (0xF << 4) | (0xF << 0)) : - ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); + 0x11ff : 0xffff; #else - temp = ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); + temp = 0xffff; #endif /* Enable TXDLL */ mrc_alt_write_mask(DDRPHY, - (DQDLLTXCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, 0xFFFF); + DQDLLTXCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0xffff); delay_n(3); /* Enable RXDLL */ mrc_alt_write_mask(DDRPHY, - (DQDLLRXCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT3 | BIT2 | BIT1 | BIT0), - (BIT3 | BIT2 | BIT1 | BIT0)); + DQDLLRXCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0xf, 0xf); delay_n(3); /* Enable RXDLL Overrides BL0 */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT3 | BIT2 | BIT1 | BIT0), - (BIT3 | BIT2 | BIT1 | BIT0)); + B0OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0xf, 0xf); } /* ECC */ - temp = ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); - mrc_alt_write_mask(DDRPHY, (ECCDLLTXCTL), - temp, 0xFFFF); + temp = 0xffff; + mrc_alt_write_mask(DDRPHY, ECCDLLTXCTL, + temp, 0xffff); delay_n(3); /* CMD (PO) */ mrc_alt_write_mask(DDRPHY, - (CMDDLLTXCTL + (ch * DDRIOCCC_CH_OFFSET)), - temp, 0xFFFF); + CMDDLLTXCTL + ch * DDRIOCCC_CH_OFFSET, + temp, 0xffff); delay_n(3); } } @@ -1195,94 +1065,85 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* Host To Memory Clock Alignment (HMC) for 800/1066 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { /* CLK_ALIGN_MOD_ID */ mrc_alt_write_mask(DDRPHY, - (DQCLKALIGNREG2 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (bl_grp) ? (0x3) : (0x1), - (BIT3 | BIT2 | BIT1 | BIT0)); + DQCLKALIGNREG2 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + bl_grp ? 3 : 1, + 0xf); } mrc_alt_write_mask(DDRPHY, - (ECCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x2, - (BIT3 | BIT2 | BIT1 | BIT0)); + ECCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x2, 0xf); mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x0, - (BIT3 | BIT2 | BIT1 | BIT0)); + CMDCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x0, 0xf); mrc_alt_write_mask(DDRPHY, - (CCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x2, - (BIT3 | BIT2 | BIT1 | BIT0)); + CCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x2, 0xf); mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)), - (0x2 << 4), (BIT5 | BIT4)); + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, + 0x20, 0x30); /* * NUM_SAMPLES, MAX_SAMPLES, * MACRO_PI_STEP, MICRO_PI_STEP */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG1 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x18 << 16) | (0x10 << 8) | - (0x8 << 2) | (0x1 << 0)), - (BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + CMDCLKALIGNREG1 + ch * DDRIOCCC_CH_OFFSET, + (0x18 << 16) | (0x10 << 8) | + (0x8 << 2) | (0x1 << 0), + 0x007f7fff); /* TOTAL_NUM_MODULES, FIRST_U_PARTITION */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG2 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x10 << 16) | (0x4 << 8) | (0x2 << 4)), - (BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | - BIT5 | BIT4)); + CMDCLKALIGNREG2 + ch * DDRIOCCC_CH_OFFSET, + (0x10 << 16) | (0x4 << 8) | (0x2 << 4), + 0x001f0ff0); #ifdef HMC_TEST /* START_CLK_ALIGN=1 */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT24, BIT24); + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 24, 1 << 24); while (msg_port_alt_read(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET))) & - BIT24) + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) & + (1 << 24)) ; /* wait for START_CLK_ALIGN=0 */ #endif /* Set RD/WR Pointer Seperation & COUNTEN & FIFOPTREN */ mrc_alt_write_mask(DDRPHY, - (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)), - BIT0, BIT0); /* WRPTRENABLE=1 */ + CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, + 1, 1); /* WRPTRENABLE=1 */ /* COMP initial */ /* enable bypass for CLK buffer (PO) */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - BIT5, BIT5); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 5, 1 << 5); /* Initial COMP Enable */ - mrc_alt_write_mask(DDRPHY, (CMPCTRL), - (BIT0), (BIT0)); + mrc_alt_write_mask(DDRPHY, CMPCTRL, 1, 1); /* wait for Initial COMP Enable = 0 */ - while (msg_port_alt_read(DDRPHY, (CMPCTRL)) & BIT0) + while (msg_port_alt_read(DDRPHY, CMPCTRL) & 1) ; /* disable bypass for CLK buffer (PO) */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - ~BIT5, BIT5); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + ~(1 << 5), 1 << 5); /* IOBUFACT */ /* STEP4a */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT2, BIT2); /* IOBUFACTRST_N=1 */ + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 2, 1 << 2); /* IOBUFACTRST_N=1 */ /* DDRPHY initialization complete */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT20, BIT20); /* SPID_INIT_COMPLETE=1 */ + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 20, 1 << 20); /* SPID_INIT_COMPLETE=1 */ } } @@ -1308,13 +1169,13 @@ void perform_jedec_init(struct mrc_params *mrc_params) mrc_post_code(0x04, 0x00); /* DDR3_RESET_SET=0, DDR3_RESET_RESET=1 */ - mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT1, (BIT8 | BIT1)); + mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 2, 0x102); /* Assert RESET# for 200us */ delay_u(200); /* DDR3_RESET_SET=1, DDR3_RESET_RESET=0 */ - mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT8, (BIT8 | BIT1)); + mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 0x100, 0x102); dtr0 = msg_port_read(MEM_CTLR, DTR0); @@ -1327,8 +1188,8 @@ void perform_jedec_init(struct mrc_params *mrc_params) drp &= 0x3; drmc = msg_port_read(MEM_CTLR, DRMC); - drmc &= 0xFFFFFFFC; - drmc |= (BIT4 | drp); + drmc &= 0xfffffffc; + drmc |= (DRMC_CKEMODE | drp); msg_port_write(MEM_CTLR, DRMC, drmc); @@ -1341,7 +1202,7 @@ void perform_jedec_init(struct mrc_params *mrc_params) } msg_port_write(MEM_CTLR, DRMC, - (mrc_params->rd_odt_value == 0 ? BIT12 : 0)); + (mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0)); /* * setup for emrs 2 @@ -1392,12 +1253,12 @@ void perform_jedec_init(struct mrc_params *mrc_params) * 1** --> RESERVED */ emrs1_cmd |= (1 << 3); - emrs1_cmd &= ~BIT6; + emrs1_cmd &= ~(1 << 6); if (mrc_params->ron_value == 0) - emrs1_cmd |= BIT7; + emrs1_cmd |= (1 << 7); else - emrs1_cmd &= ~BIT7; + emrs1_cmd &= ~(1 << 7); if (mrc_params->rtt_nom_value == 0) emrs1_cmd |= (DDR3_EMRS1_RTTNOM_40 << 6); @@ -1432,8 +1293,8 @@ void perform_jedec_init(struct mrc_params *mrc_params) * BIT[02:02] "0" if oem_tCAS <= 11 (1866?) * BIT[06:04] use oem_tCAS-4 */ - mrs0_cmd |= BIT14; - mrs0_cmd |= BIT18; + mrs0_cmd |= (1 << 14); + mrs0_cmd |= (1 << 18); mrs0_cmd |= ((((dtr0 >> 12) & 7) + 1) << 10); tck = t_ck[mrc_params->ddr_speed]; @@ -1480,8 +1341,8 @@ void set_ddr_init_complete(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT28; - dco |= BIT31; + dco &= ~DCO_PMICTL; + dco |= DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -1577,7 +1438,7 @@ void rcvn_cal(struct mrc_params *mrc_params) /* need separate burst to sample DQS preamble */ dtr1 = msg_port_read(MEM_CTLR, DTR1); dtr1_save = dtr1; - dtr1 |= BIT12; + dtr1 |= DTR1_TCCD_12CLK; msg_port_write(MEM_CTLR, DTR1, dtr1); #endif @@ -1596,7 +1457,7 @@ void rcvn_cal(struct mrc_params *mrc_params) * POST_CODE here indicates the current * channel and rank being calibrated */ - mrc_post_code(0x05, (0x10 + ((ch << 4) | rk))); + mrc_post_code(0x05, 0x10 + ((ch << 4) | rk)); #ifdef BACKUP_RCVN /* et hard-coded timing values */ @@ -1606,10 +1467,10 @@ void rcvn_cal(struct mrc_params *mrc_params) /* enable FIFORST */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - ((bl >> 1) * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - 0, BIT8); + B01PTRCTL1 + + (bl >> 1) * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 1 << 8); } /* initialize the starting delay to 128 PI (cas +1 CLK) */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { @@ -1638,11 +1499,11 @@ void rcvn_cal(struct mrc_params *mrc_params) } else { /* not enough delay */ training_message(ch, rk, bl); - mrc_post_code(0xEE, 0x50); + mrc_post_code(0xee, 0x50); } } } - } while (temp & 0xFF); + } while (temp & 0xff); #ifdef R2R_SHARING /* increment "num_ranks_enabled" */ @@ -1653,7 +1514,7 @@ void rcvn_cal(struct mrc_params *mrc_params) /* add "delay[]" values to "final_delay[][]" for rolling average */ final_delay[ch][bl] += delay[bl]; /* set timing based on rolling average values */ - set_rcvn(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); } #else /* Finally increment delay by 32 PI (1/4 CLK) to place in center of preamble */ @@ -1666,10 +1527,10 @@ void rcvn_cal(struct mrc_params *mrc_params) /* disable FIFORST */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - ((bl >> 1) * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - BIT8, BIT8); + B01PTRCTL1 + + (bl >> 1) * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 8, 1 << 8); } #endif } @@ -1742,12 +1603,12 @@ void wr_level(struct mrc_params *mrc_params) * POST_CODE here indicates the current * rank and channel being calibrated */ - mrc_post_code(0x06, (0x10 + ((ch << 4) | rk))); + mrc_post_code(0x06, 0x10 + ((ch << 4) | rk)); #ifdef BACKUP_WDQS for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]); - set_wdq(ch, rk, bl, (ddr_wdqs[PLATFORM_ID] - QRTR_CLK)); + set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK); } #else /* @@ -1760,7 +1621,7 @@ void wr_level(struct mrc_params *mrc_params) * enable Write Levelling Mode * (EMRS1 w/ Write Levelling Mode Enable) */ - dram_init_command(DCMD_MRS1(rk, 0x0082)); + dram_init_command(DCMD_MRS1(rk, 0x82)); /* * set ODT DRAM Full Time Termination @@ -1769,24 +1630,24 @@ void wr_level(struct mrc_params *mrc_params) dtr4 = msg_port_read(MEM_CTLR, DTR4); dtr4_save = dtr4; - dtr4 |= BIT15; + dtr4 |= DTR4_ODTDIS; msg_port_write(MEM_CTLR, DTR4, dtr4); - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* * Enable Sandy Bridge Mode (WDQ Tri-State) & * Ensure 5 WDQS pulses during Write Leveling */ mrc_alt_write_mask(DDRPHY, - DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch), - (BIT28 | BIT8 | BIT6 | BIT4 | BIT2), - (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, + 0x10000154, + 0x100003fc); } /* Write Leveling Mode enabled in IO */ mrc_alt_write_mask(DDRPHY, - CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch), - BIT16, BIT16); + CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, + 1 << 16, 1 << 16); /* Initialize the starting delay to WCLK */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { @@ -1804,15 +1665,15 @@ void wr_level(struct mrc_params *mrc_params) /* disable Write Levelling Mode */ mrc_alt_write_mask(DDRPHY, - CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch), - 0, BIT16); + CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, + 0, 1 << 16); - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* Disable Sandy Bridge Mode & Ensure 4 WDQS pulses during normal operation */ mrc_alt_write_mask(DDRPHY, - DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch), - (BIT8 | BIT6 | BIT4 | BIT2), - (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, + 0x00000154, + 0x100003fc); } /* restore original DTR4 */ @@ -1830,7 +1691,7 @@ void wr_level(struct mrc_params *mrc_params) */ dram_init_command(DCMD_PREA(rk)); - mrc_post_code(0x06, (0x30 + ((ch << 4) | rk))); + mrc_post_code(0x06, 0x30 + ((ch << 4) | rk)); /* * COARSE WRITE LEVEL: @@ -1863,13 +1724,13 @@ void wr_level(struct mrc_params *mrc_params) coarse_result = check_rw_coarse(mrc_params, address); /* check for failures and margin the byte lane back 128 PI (1 CLK) */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (coarse_result & (coarse_result_mask << bl)) { all_edges_found = false; delay[bl] -= FULL_CLK; set_wdqs(ch, rk, bl, delay[bl]); /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ - set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK)); + set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK); } } } while (!all_edges_found); @@ -1878,11 +1739,11 @@ void wr_level(struct mrc_params *mrc_params) /* increment "num_ranks_enabled" */ num_ranks_enabled++; /* accumulate "final_delay[][]" values from "delay[]" values for rolling average */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { final_delay[ch][bl] += delay[bl]; - set_wdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ - set_wdq(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled) - QRTR_CLK); + set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); } #endif #endif @@ -1901,9 +1762,9 @@ void prog_page_ctrl(struct mrc_params *mrc_params) ENTERFN(); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 &= ~(BIT16 | BIT17 | BIT18); + dpmc0 &= ~DPMC0_PCLSTO_MASK; dpmc0 |= (4 << 16); - dpmc0 |= BIT21; + dpmc0 |= DPMC0_PREAPWDEN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); } @@ -1966,7 +1827,7 @@ void rd_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]); } @@ -1981,7 +1842,7 @@ void rd_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* x_coordinate */ x_coordinate[L][B][ch][rk][bl] = RDQS_MIN; @@ -2011,7 +1872,7 @@ void rd_train(struct mrc_params *mrc_params) /* look for passing coordinates */ for (side_y = B; side_y <= T; side_y++) { for (side_x = L; side_x <= R; side_x++) { - mrc_post_code(0x07, (0x10 + (side_y * 2) + (side_x))); + mrc_post_code(0x07, 0x10 + side_y * 2 + side_x); /* find passing values */ for (ch = 0; ch < NUM_CHANNELS; ch++) { @@ -2021,7 +1882,7 @@ void rd_train(struct mrc_params *mrc_params) (0x1 << rk)) { /* set x/y_coordinate search starting settings */ for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]); @@ -2041,9 +1902,9 @@ void rd_train(struct mrc_params *mrc_params) result = check_bls_ex(mrc_params, address); /* check for failures */ - if (result & 0xFF) { + if (result & 0xff) { /* at least 1 byte lane failed */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (result & (bl_mask << bl)) { /* adjust the RDQS values accordingly */ @@ -2072,13 +1933,13 @@ void rd_train(struct mrc_params *mrc_params) (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) { /* VREF_EYE collapsed below MIN_VREF_EYE */ training_message(ch, rk, bl); - mrc_post_code(0xEE, (0x70 + (side_y * 2) + (side_x))); + mrc_post_code(0xEE, 0x70 + side_y * 2 + side_x); } else { /* update the VREF setting */ set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]); /* reset the X coordinate to begin the search at the new VREF */ x_coordinate[side_x][side_y][ch][rk][bl] = - (side_x == L) ? (RDQS_MIN) : (RDQS_MAX); + (side_x == L) ? RDQS_MIN : RDQS_MAX; } } @@ -2087,7 +1948,7 @@ void rd_train(struct mrc_params *mrc_params) } } } - } while (result & 0xFF); + } while (result & 0xff); } } } @@ -2147,23 +2008,23 @@ void rd_train(struct mrc_params *mrc_params) /* perform an eye check */ for (side_y = B; side_y <= T; side_y++) { for (side_x = L; side_x <= R; side_x++) { - mrc_post_code(0x07, (0x30 + (side_y * 2) + (side_x))); + mrc_post_code(0x07, 0x30 + side_y * 2 + side_x); /* update the settings for the eye check */ for (ch = 0; ch < NUM_CHANNELS; ch++) { if (mrc_params->channel_enables & (1 << ch)) { for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (side_x == L) - set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2))); + set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)); else - set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2))); + set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)); if (side_y == B) - set_vref(ch, bl, (y_center[ch][bl] - (MIN_VREF_EYE / 2))); + set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2)); else - set_vref(ch, bl, (y_center[ch][bl] + (MIN_VREF_EYE / 2))); + set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2)); } } } @@ -2174,9 +2035,9 @@ void rd_train(struct mrc_params *mrc_params) mrc_params->hte_setup = 1; /* check the eye */ - if (check_bls_ex(mrc_params, address) & 0xFF) { + if (check_bls_ex(mrc_params, address) & 0xff) { /* one or more byte lanes failed */ - mrc_post_code(0xEE, (0x74 + (side_x * 2) + (side_y))); + mrc_post_code(0xee, 0x74 + side_x * 2 + side_y); } } } @@ -2197,7 +2058,7 @@ void rd_train(struct mrc_params *mrc_params) /* x_coordinate */ #ifdef R2R_SHARING final_delay[ch][bl] += x_center[ch][rk][bl]; - set_rdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); #else set_rdqs(ch, rk, bl, x_center[ch][rk][bl]); #endif @@ -2258,7 +2119,7 @@ void wr_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]); } @@ -2273,7 +2134,7 @@ void wr_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* * want to start with @@ -2303,7 +2164,7 @@ void wr_train(struct mrc_params *mrc_params) * until no failures are observed, then repeat for the RIGHT side. */ for (side = L; side <= R; side++) { - mrc_post_code(0x08, (0x10 + (side))); + mrc_post_code(0x08, 0x10 + side); /* set starting values */ for (ch = 0; ch < NUM_CHANNELS; ch++) { @@ -2312,7 +2173,7 @@ void wr_train(struct mrc_params *mrc_params) if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_wdq(ch, rk, bl, delay[side][ch][rk][bl]); } @@ -2338,9 +2199,9 @@ void wr_train(struct mrc_params *mrc_params) /* result[07:00] == failing byte lane (MAX 8) */ result = check_bls_ex(mrc_params, address); /* check for failures */ - if (result & 0xFF) { + if (result & 0xff) { /* at least 1 byte lane failed */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (result & (bl_mask << bl)) { if (side == L) @@ -2362,13 +2223,13 @@ void wr_train(struct mrc_params *mrc_params) * notify the user and halt */ training_message(ch, rk, bl); - mrc_post_code(0xEE, (0x80 + side)); + mrc_post_code(0xee, 0x80 + side); } } } } /* stop when all byte lanes pass */ - } while (result & 0xFF); + } while (result & 0xff); } } } @@ -2384,7 +2245,7 @@ void wr_train(struct mrc_params *mrc_params) /* increment "num_ranks_enabled" */ num_ranks_enabled++; #endif - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { DPF(D_INFO, "WDQ eye rank%d lane%d : %d-%d\n", rk, bl, @@ -2396,7 +2257,7 @@ void wr_train(struct mrc_params *mrc_params) #ifdef R2R_SHARING final_delay[ch][bl] += temp; set_wdq(ch, rk, bl, - ((final_delay[ch][bl]) / num_ranks_enabled)); + final_delay[ch][bl] / num_ranks_enabled); #else set_wdq(ch, rk, bl, temp); #endif @@ -2470,7 +2331,7 @@ void enable_scrambling(struct mrc_params *mrc_params) * get seed from system clock * and make sure it is not all 1's */ - lfsr = rdtsc() & 0x0FFFFFFF; + lfsr = rdtsc() & 0x0fffffff; } else { /* * Need to replace scrambler @@ -2491,10 +2352,10 @@ void enable_scrambling(struct mrc_params *mrc_params) * In cold boot, we have the last 32bit LFSR which is the new seed. */ lfsr32(&lfsr); /* shift to next value */ - msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003FFFF)); + msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003ffff)); for (i = 0; i < 2; i++) - msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xAAAAAAAA)); + msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xaaaaaaaa)); LEAVEFN(); } @@ -2511,20 +2372,20 @@ void prog_ddr_control(struct mrc_params *mrc_params) ENTERFN(); dsch = msg_port_read(MEM_CTLR, DSCH); - dsch &= ~(BIT8 | BIT9 | BIT12); + dsch &= ~(DSCH_OOODIS | DSCH_OOOST3DIS | DSCH_NEWBYPDIS); msg_port_write(MEM_CTLR, DSCH, dsch); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 &= ~BIT25; + dpmc0 &= ~DPMC0_DISPWRDN; dpmc0 |= (mrc_params->power_down_disable << 25); - dpmc0 &= ~BIT24; - dpmc0 &= ~(BIT16 | BIT17 | BIT18); + dpmc0 &= ~DPMC0_CLKGTDIS; + dpmc0 &= ~DPMC0_PCLSTO_MASK; dpmc0 |= (4 << 16); - dpmc0 |= BIT21; + dpmc0 |= DPMC0_PREAPWDEN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); /* CMDTRIST = 2h - CMD/ADDR are tristated when no valid command */ - mrc_write_mask(MEM_CTLR, DPMC1, 2 << 4, BIT4 | BIT5); + mrc_write_mask(MEM_CTLR, DPMC1, 0x20, 0x30); LEAVEFN(); } @@ -2542,14 +2403,14 @@ void prog_dra_drb(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT31; + dco &= ~DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); drp = 0; if (mrc_params->rank_enables & 1) - drp |= BIT0; + drp |= DRP_RKEN0; if (mrc_params->rank_enables & 2) - drp |= BIT1; + drp |= DRP_RKEN1; if (mrc_params->dram_width == X16) { drp |= (1 << 4); drp |= (1 << 9); @@ -2570,8 +2431,8 @@ void prog_dra_drb(struct mrc_params *mrc_params) msg_port_write(MEM_CTLR, DRP, drp); - dco &= ~BIT28; - dco |= BIT31; + dco &= ~DCO_PMICTL; + dco |= DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -2600,18 +2461,18 @@ void change_refresh_period(struct mrc_params *mrc_params) ENTERFN(); drfc = msg_port_read(MEM_CTLR, DRFC); - drfc &= ~(BIT12 | BIT13 | BIT14); + drfc &= ~DRFC_TREFI_MASK; drfc |= (mrc_params->refresh_rate << 12); - drfc |= BIT21; + drfc |= DRFC_REFDBTCLR; msg_port_write(MEM_CTLR, DRFC, drfc); dcal = msg_port_read(MEM_CTLR, DCAL); - dcal &= ~(BIT8 | BIT9 | BIT10); + dcal &= ~DCAL_ZQCINT_MASK; dcal |= (3 << 8); /* 63ms */ msg_port_write(MEM_CTLR, DCAL, dcal); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 |= (BIT23 | BIT29); + dpmc0 |= (DPMC0_DYNSREN | DPMC0_ENPHYCLKGATE); msg_port_write(MEM_CTLR, DPMC0, dpmc0); LEAVEFN(); @@ -2638,36 +2499,32 @@ void set_auto_refresh(struct mrc_params *mrc_params) for (channel = 0; channel < NUM_CHANNELS; channel++) { if (mrc_params->channel_enables & (1 << channel)) { /* Enable Periodic RCOMPS */ - mrc_alt_write_mask(DDRPHY, CMPCTRL, BIT1, BIT1); + mrc_alt_write_mask(DDRPHY, CMPCTRL, 2, 2); /* Enable Dynamic DiffAmp & Set Read ODT Value */ switch (mrc_params->rd_odt_value) { case 0: - temp = 0x3F; /* OFF */ + temp = 0x3f; /* OFF */ break; default: temp = 0x00; /* Auto */ break; } - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + (bl * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)), - (0x00 << 16) | (temp << 10), - (BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10)); + B0OVRCTL + bl * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET, + temp << 10, + 0x003ffc00); /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B1OVRCTL + (bl * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)), - (0x00 << 16) | (temp << 10), - (BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10)); + B1OVRCTL + bl * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET, + temp << 10, + 0x003ffc00); } /* Issue ZQCS command */ @@ -2702,18 +2559,18 @@ void ecc_enable(struct mrc_params *mrc_params) /* Configuration required in ECC mode */ drp = msg_port_read(MEM_CTLR, DRP); - drp &= ~(BIT14 | BIT15); - drp |= BIT15; - drp |= BIT13; + drp &= ~DRP_ADDRMAP_MASK; + drp |= DRP_ADDRMAP_MAP1; + drp |= DRP_PRI64BSPLITEN; msg_port_write(MEM_CTLR, DRP, drp); /* Disable new request bypass */ dsch = msg_port_read(MEM_CTLR, DSCH); - dsch |= BIT12; + dsch |= DSCH_NEWBYPDIS; msg_port_write(MEM_CTLR, DSCH, dsch); /* Enable ECC */ - ecc_ctrl = (BIT0 | BIT1 | BIT17); + ecc_ctrl = (DECCCTRL_SBEEN | DECCCTRL_DBEEN | DECCCTRL_ENCBGEN); msg_port_write(MEM_CTLR, DECCCTRL, ecc_ctrl); /* Assume 8 bank memory, one bank is gone for ECC */ @@ -2756,8 +2613,8 @@ void lock_registers(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~(BIT28 | BIT29); - dco |= (BIT0 | BIT8); + dco &= ~(DCO_PMICTL | DCO_PMIDIS); + dco |= (DCO_DRPLOCK | DCO_CPGCLOCK); msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); diff --git a/arch/x86/cpu/quark/smc.h b/arch/x86/cpu/quark/smc.h index 46017a1ccb..1582b87e10 100644 --- a/arch/x86/cpu/quark/smc.h +++ b/arch/x86/cpu/quark/smc.h @@ -24,46 +24,133 @@ #define DPMC1 0x07 #define DRFC 0x08 #define DSCH 0x09 -#define DCAL 0x0A -#define DRMC 0x0B -#define PMSTS 0x0C -#define DCO 0x0F +#define DCAL 0x0a +#define DRMC 0x0b +#define PMSTS 0x0c +#define DCO 0x0f #define DSTAT 0x20 -#define SSKPD0 0x4A -#define SSKPD1 0x4B +#define SSKPD0 0x4a +#define SSKPD1 0x4b #define DECCCTRL 0x60 #define DECCSTAT 0x61 #define DECCSBECNT 0x62 #define DECCSBECA 0x68 #define DECCSBECS 0x69 -#define DECCDBECA 0x6A -#define DECCDBECS 0x6B +#define DECCDBECA 0x6a +#define DECCDBECS 0x6b #define DFUSESTAT 0x70 #define SCRMSEED 0x80 #define SCRMLO 0x81 #define SCRMHI 0x82 +/* DRP register defines */ +#define DRP_RKEN0 (1 << 0) +#define DRP_RKEN1 (1 << 1) +#define DRP_PRI64BSPLITEN (1 << 13) +#define DRP_ADDRMAP_MAP0 (1 << 14) +#define DRP_ADDRMAP_MAP1 (1 << 15) +#define DRP_ADDRMAP_MASK 0x0000c000 + +/* DTR0 register defines */ +#define DTR0_DFREQ_MASK 0x00000003 +#define DTR0_TRP_MASK 0x000000f0 +#define DTR0_TRCD_MASK 0x00000f00 +#define DTR0_TCL_MASK 0x00007000 + +/* DTR1 register defines */ +#define DTR1_TWCL_MASK 0x00000007 +#define DTR1_TCMD_MASK 0x00000030 +#define DTR1_TWTP_MASK 0x00000f00 +#define DTR1_TCCD_12CLK (1 << 12) +#define DTR1_TCCD_18CLK (1 << 13) +#define DTR1_TCCD_MASK 0x00003000 +#define DTR1_TFAW_MASK 0x000f0000 +#define DTR1_TRAS_MASK 0x00f00000 +#define DTR1_TRRD_MASK 0x03000000 +#define DTR1_TRTP_MASK 0x70000000 + +/* DTR2 register defines */ +#define DTR2_TRRDR_MASK 0x00000007 +#define DTR2_TWWDR_MASK 0x00000700 +#define DTR2_TRWDR_MASK 0x000f0000 + +/* DTR3 register defines */ +#define DTR3_TWRDR_MASK 0x00000007 +#define DTR3_TXXXX_MASK 0x00000070 +#define DTR3_TRWSR_MASK 0x00000f00 +#define DTR3_TWRSR_MASK 0x0001e000 +#define DTR3_TXP_MASK 0x00c00000 + +/* DTR4 register defines */ +#define DTR4_WRODTSTRT_MASK 0x00000003 +#define DTR4_WRODTSTOP_MASK 0x00000070 +#define DTR4_XXXX1_MASK 0x00000700 +#define DTR4_XXXX2_MASK 0x00007000 +#define DTR4_ODTDIS (1 << 15) +#define DTR4_TRGSTRDIS (1 << 16) + +/* DPMC0 register defines */ +#define DPMC0_PCLSTO_MASK 0x00070000 +#define DPMC0_PREAPWDEN (1 << 21) +#define DPMC0_DYNSREN (1 << 23) +#define DPMC0_CLKGTDIS (1 << 24) +#define DPMC0_DISPWRDN (1 << 25) +#define DPMC0_ENPHYCLKGATE (1 << 29) + +/* DRFC register defines */ +#define DRFC_TREFI_MASK 0x00007000 +#define DRFC_REFDBTCLR (1 << 21) + +/* DSCH register defines */ +#define DSCH_OOODIS (1 << 8) +#define DSCH_OOOST3DIS (1 << 9) +#define DSCH_NEWBYPDIS (1 << 12) + +/* DCAL register defines */ +#define DCAL_ZQCINT_MASK 0x00000700 +#define DCAL_SRXZQCL_MASK 0x00003000 + +/* DRMC register defines */ +#define DRMC_CKEMODE (1 << 4) +#define DRMC_ODTMODE (1 << 12) +#define DRMC_COLDWAKE (1 << 16) + +/* PMSTS register defines */ +#define PMSTS_DISR (1 << 0) + +/* DCO register defines */ +#define DCO_DRPLOCK (1 << 0) +#define DCO_CPGCLOCK (1 << 8) +#define DCO_PMICTL (1 << 28) +#define DCO_PMIDIS (1 << 29) +#define DCO_IC (1 << 31) + +/* DECCCTRL register defines */ +#define DECCCTRL_SBEEN (1 << 0) +#define DECCCTRL_DBEEN (1 << 1) +#define DECCCTRL_ENCBGEN (1 << 17) + /* DRAM init command */ #define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6)) #define DCMD_REF(rnk) (1 | ((rnk) << 22)) #define DCMD_PRE(rnk) (2 | ((rnk) << 22)) -#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (BIT10 << 6)) +#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (0x400 << 6)) #define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6)) #define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6)) #define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6)) #define DCMD_ZQCS(rnk) (6 | ((rnk) << 22)) -#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (BIT10 << 6)) +#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (0x400 << 6)) #define DCMD_NOP(rnk) (7 | ((rnk) << 22)) -#define DDR3_EMRS1_DIC_40 (0) -#define DDR3_EMRS1_DIC_34 (1) +#define DDR3_EMRS1_DIC_40 0 +#define DDR3_EMRS1_DIC_34 1 -#define DDR3_EMRS1_RTTNOM_0 (0) -#define DDR3_EMRS1_RTTNOM_60 (0x04) -#define DDR3_EMRS1_RTTNOM_120 (0x40) -#define DDR3_EMRS1_RTTNOM_40 (0x44) -#define DDR3_EMRS1_RTTNOM_20 (0x200) -#define DDR3_EMRS1_RTTNOM_30 (0x204) +#define DDR3_EMRS1_RTTNOM_0 0 +#define DDR3_EMRS1_RTTNOM_60 0x04 +#define DDR3_EMRS1_RTTNOM_120 0x40 +#define DDR3_EMRS1_RTTNOM_40 0x44 +#define DDR3_EMRS1_RTTNOM_20 0x200 +#define DDR3_EMRS1_RTTNOM_30 0x204 #define DDR3_EMRS2_RTTWR_60 (1 << 9) #define DDR3_EMRS2_RTTWR_120 (1 << 10) @@ -80,87 +167,87 @@ #define DQOBSCKEBBCTL 0x0000 #define DQDLLTXCTL 0x0004 #define DQDLLRXCTL 0x0008 -#define DQMDLLCTL 0x000C +#define DQMDLLCTL 0x000c #define B0RXIOBUFCTL 0x0010 #define B0VREFCTL 0x0014 #define B0RXOFFSET1 0x0018 -#define B0RXOFFSET0 0x001C +#define B0RXOFFSET0 0x001c #define B1RXIOBUFCTL 0x0020 #define B1VREFCTL 0x0024 #define B1RXOFFSET1 0x0028 -#define B1RXOFFSET0 0x002C +#define B1RXOFFSET0 0x002c #define DQDFTCTL 0x0030 #define DQTRAINSTS 0x0034 #define B1DLLPICODER0 0x0038 -#define B0DLLPICODER0 0x003C +#define B0DLLPICODER0 0x003c #define B1DLLPICODER1 0x0040 #define B0DLLPICODER1 0x0044 #define B1DLLPICODER2 0x0048 -#define B0DLLPICODER2 0x004C +#define B0DLLPICODER2 0x004c #define B1DLLPICODER3 0x0050 #define B0DLLPICODER3 0x0054 #define B1RXDQSPICODE 0x0058 -#define B0RXDQSPICODE 0x005C +#define B0RXDQSPICODE 0x005c #define B1RXDQPICODER32 0x0060 #define B1RXDQPICODER10 0x0064 #define B0RXDQPICODER32 0x0068 -#define B0RXDQPICODER10 0x006C +#define B0RXDQPICODER10 0x006c #define B01PTRCTL0 0x0070 #define B01PTRCTL1 0x0074 #define B01DBCTL0 0x0078 -#define B01DBCTL1 0x007C +#define B01DBCTL1 0x007c #define B0LATCTL0 0x0080 #define B1LATCTL0 0x0084 #define B01LATCTL1 0x0088 -#define B0ONDURCTL 0x008C +#define B0ONDURCTL 0x008c #define B1ONDURCTL 0x0090 #define B0OVRCTL 0x0094 #define B1OVRCTL 0x0098 -#define DQCTL 0x009C -#define B0RK2RKCHGPTRCTRL 0x00A0 -#define B1RK2RKCHGPTRCTRL 0x00A4 -#define DQRK2RKCTL 0x00A8 -#define DQRK2RKPTRCTL 0x00AC -#define B0RK2RKLAT 0x00B0 -#define B1RK2RKLAT 0x00B4 -#define DQCLKALIGNREG0 0x00B8 -#define DQCLKALIGNREG1 0x00BC -#define DQCLKALIGNREG2 0x00C0 -#define DQCLKALIGNSTS0 0x00C4 -#define DQCLKALIGNSTS1 0x00C8 -#define DQCLKGATE 0x00CC -#define B0COMPSLV1 0x00D0 -#define B1COMPSLV1 0x00D4 -#define B0COMPSLV2 0x00D8 -#define B1COMPSLV2 0x00DC -#define B0COMPSLV3 0x00E0 -#define B1COMPSLV3 0x00E4 -#define DQVISALANECR0TOP 0x00E8 -#define DQVISALANECR1TOP 0x00EC -#define DQVISACONTROLCRTOP 0x00F0 -#define DQVISALANECR0BL 0x00F4 -#define DQVISALANECR1BL 0x00F8 -#define DQVISACONTROLCRBL 0x00FC -#define DQTIMINGCTRL 0x010C +#define DQCTL 0x009c +#define B0RK2RKCHGPTRCTRL 0x00a0 +#define B1RK2RKCHGPTRCTRL 0x00a4 +#define DQRK2RKCTL 0x00a8 +#define DQRK2RKPTRCTL 0x00ac +#define B0RK2RKLAT 0x00b0 +#define B1RK2RKLAT 0x00b4 +#define DQCLKALIGNREG0 0x00b8 +#define DQCLKALIGNREG1 0x00bc +#define DQCLKALIGNREG2 0x00c0 +#define DQCLKALIGNSTS0 0x00c4 +#define DQCLKALIGNSTS1 0x00c8 +#define DQCLKGATE 0x00cc +#define B0COMPSLV1 0x00d0 +#define B1COMPSLV1 0x00d4 +#define B0COMPSLV2 0x00d8 +#define B1COMPSLV2 0x00dc +#define B0COMPSLV3 0x00e0 +#define B1COMPSLV3 0x00e4 +#define DQVISALANECR0TOP 0x00e8 +#define DQVISALANECR1TOP 0x00ec +#define DQVISACONTROLCRTOP 0x00f0 +#define DQVISALANECR0BL 0x00f4 +#define DQVISALANECR1BL 0x00f8 +#define DQVISACONTROLCRBL 0x00fc +#define DQTIMINGCTRL 0x010c /* CH0-ECC */ #define ECCDLLTXCTL 0x2004 #define ECCDLLRXCTL 0x2008 -#define ECCMDLLCTL 0x200C +#define ECCMDLLCTL 0x200c #define ECCB1DLLPICODER0 0x2038 #define ECCB1DLLPICODER1 0x2040 #define ECCB1DLLPICODER2 0x2048 #define ECCB1DLLPICODER3 0x2050 #define ECCB01DBCTL0 0x2078 -#define ECCB01DBCTL1 0x207C -#define ECCCLKALIGNREG0 0x20B8 -#define ECCCLKALIGNREG1 0x20BC -#define ECCCLKALIGNREG2 0x20C0 +#define ECCB01DBCTL1 0x207c +#define ECCCLKALIGNREG0 0x20b8 +#define ECCCLKALIGNREG1 0x20bc +#define ECCCLKALIGNREG2 0x20c0 /* CH0-CMD */ #define CMDOBSCKEBBCTL 0x4800 #define CMDDLLTXCTL 0x4808 -#define CMDDLLRXCTL 0x480C +#define CMDDLLRXCTL 0x480c #define CMDMDLLCTL 0x4810 #define CMDRCOMPODT 0x4814 #define CMDDLLPICODER0 0x4820 @@ -170,30 +257,30 @@ #define CMDCLKALIGNREG0 0x4850 #define CMDCLKALIGNREG1 0x4854 #define CMDCLKALIGNREG2 0x4858 -#define CMDPMCONFIG0 0x485C +#define CMDPMCONFIG0 0x485c #define CMDPMDLYREG0 0x4860 #define CMDPMDLYREG1 0x4864 #define CMDPMDLYREG2 0x4868 -#define CMDPMDLYREG3 0x486C +#define CMDPMDLYREG3 0x486c #define CMDPMDLYREG4 0x4870 #define CMDCLKALIGNSTS0 0x4874 #define CMDCLKALIGNSTS1 0x4878 -#define CMDPMSTS0 0x487C +#define CMDPMSTS0 0x487c #define CMDPMSTS1 0x4880 #define CMDCOMPSLV 0x4884 -#define CMDBONUS0 0x488C +#define CMDBONUS0 0x488c #define CMDBONUS1 0x4890 #define CMDVISALANECR0 0x4894 #define CMDVISALANECR1 0x4898 -#define CMDVISACONTROLCR 0x489C -#define CMDCLKGATE 0x48A0 -#define CMDTIMINGCTRL 0x48A4 +#define CMDVISACONTROLCR 0x489c +#define CMDCLKGATE 0x48a0 +#define CMDTIMINGCTRL 0x48a4 /* CH0-CLK-CTL */ #define CCOBSCKEBBCTL 0x5800 #define CCRCOMPIO 0x5804 #define CCDLLTXCTL 0x5808 -#define CCDLLRXCTL 0x580C +#define CCDLLRXCTL 0x580c #define CCMDLLCTL 0x5810 #define CCRCOMPODT 0x5814 #define CCDLLPICODER0 0x5820 @@ -205,123 +292,123 @@ #define CCCLKALIGNREG0 0x5850 #define CCCLKALIGNREG1 0x5854 #define CCCLKALIGNREG2 0x5858 -#define CCPMCONFIG0 0x585C +#define CCPMCONFIG0 0x585c #define CCPMDLYREG0 0x5860 #define CCPMDLYREG1 0x5864 #define CCPMDLYREG2 0x5868 -#define CCPMDLYREG3 0x586C +#define CCPMDLYREG3 0x586c #define CCPMDLYREG4 0x5870 #define CCCLKALIGNSTS0 0x5874 #define CCCLKALIGNSTS1 0x5878 -#define CCPMSTS0 0x587C +#define CCPMSTS0 0x587c #define CCPMSTS1 0x5880 #define CCCOMPSLV1 0x5884 #define CCCOMPSLV2 0x5888 -#define CCCOMPSLV3 0x588C +#define CCCOMPSLV3 0x588c #define CCBONUS0 0x5894 #define CCBONUS1 0x5898 -#define CCVISALANECR0 0x589C -#define CCVISALANECR1 0x58A0 -#define CCVISACONTROLCR 0x58A4 -#define CCCLKGATE 0x58A8 -#define CCTIMINGCTL 0x58AC +#define CCVISALANECR0 0x589c +#define CCVISALANECR1 0x58a0 +#define CCVISACONTROLCR 0x58a4 +#define CCCLKGATE 0x58a8 +#define CCTIMINGCTL 0x58ac /* COMP */ #define CMPCTRL 0x6800 #define SOFTRSTCNTL 0x6804 #define MSCNTR 0x6808 -#define NMSCNTRL 0x680C +#define NMSCNTRL 0x680c #define LATCH1CTL 0x6814 -#define COMPVISALANECR0 0x681C +#define COMPVISALANECR0 0x681c #define COMPVISALANECR1 0x6820 #define COMPVISACONTROLCR 0x6824 #define COMPBONUS0 0x6830 -#define TCOCNTCTRL 0x683C +#define TCOCNTCTRL 0x683c #define DQANAODTPUCTL 0x6840 #define DQANAODTPDCTL 0x6844 #define DQANADRVPUCTL 0x6848 -#define DQANADRVPDCTL 0x684C +#define DQANADRVPDCTL 0x684c #define DQANADLYPUCTL 0x6850 #define DQANADLYPDCTL 0x6854 #define DQANATCOPUCTL 0x6858 -#define DQANATCOPDCTL 0x685C +#define DQANATCOPDCTL 0x685c #define CMDANADRVPUCTL 0x6868 -#define CMDANADRVPDCTL 0x686C +#define CMDANADRVPDCTL 0x686c #define CMDANADLYPUCTL 0x6870 #define CMDANADLYPDCTL 0x6874 #define CLKANAODTPUCTL 0x6880 #define CLKANAODTPDCTL 0x6884 #define CLKANADRVPUCTL 0x6888 -#define CLKANADRVPDCTL 0x688C +#define CLKANADRVPDCTL 0x688c #define CLKANADLYPUCTL 0x6890 #define CLKANADLYPDCTL 0x6894 #define CLKANATCOPUCTL 0x6898 -#define CLKANATCOPDCTL 0x689C -#define DQSANAODTPUCTL 0x68A0 -#define DQSANAODTPDCTL 0x68A4 -#define DQSANADRVPUCTL 0x68A8 -#define DQSANADRVPDCTL 0x68AC -#define DQSANADLYPUCTL 0x68B0 -#define DQSANADLYPDCTL 0x68B4 -#define DQSANATCOPUCTL 0x68B8 -#define DQSANATCOPDCTL 0x68BC -#define CTLANADRVPUCTL 0x68C8 -#define CTLANADRVPDCTL 0x68CC -#define CTLANADLYPUCTL 0x68D0 -#define CTLANADLYPDCTL 0x68D4 -#define CHNLBUFSTATIC 0x68F0 -#define COMPOBSCNTRL 0x68F4 -#define COMPBUFFDBG0 0x68F8 -#define COMPBUFFDBG1 0x68FC +#define CLKANATCOPDCTL 0x689c +#define DQSANAODTPUCTL 0x68a0 +#define DQSANAODTPDCTL 0x68a4 +#define DQSANADRVPUCTL 0x68a8 +#define DQSANADRVPDCTL 0x68ac +#define DQSANADLYPUCTL 0x68b0 +#define DQSANADLYPDCTL 0x68b4 +#define DQSANATCOPUCTL 0x68b8 +#define DQSANATCOPDCTL 0x68bc +#define CTLANADRVPUCTL 0x68c8 +#define CTLANADRVPDCTL 0x68cc +#define CTLANADLYPUCTL 0x68d0 +#define CTLANADLYPDCTL 0x68d4 +#define CHNLBUFSTATIC 0x68f0 +#define COMPOBSCNTRL 0x68f4 +#define COMPBUFFDBG0 0x68f8 +#define COMPBUFFDBG1 0x68fc #define CFGMISCCH0 0x6900 #define COMPEN0CH0 0x6904 #define COMPEN1CH0 0x6908 -#define COMPEN2CH0 0x690C +#define COMPEN2CH0 0x690c #define STATLEGEN0CH0 0x6910 #define STATLEGEN1CH0 0x6914 #define DQVREFCH0 0x6918 -#define CMDVREFCH0 0x691C +#define CMDVREFCH0 0x691c #define CLKVREFCH0 0x6920 #define DQSVREFCH0 0x6924 #define CTLVREFCH0 0x6928 -#define TCOVREFCH0 0x692C +#define TCOVREFCH0 0x692c #define DLYSELCH0 0x6930 #define TCODRAMBUFODTCH0 0x6934 #define CCBUFODTCH0 0x6938 -#define RXOFFSETCH0 0x693C +#define RXOFFSETCH0 0x693c #define DQODTPUCTLCH0 0x6940 #define DQODTPDCTLCH0 0x6944 #define DQDRVPUCTLCH0 0x6948 -#define DQDRVPDCTLCH0 0x694C +#define DQDRVPDCTLCH0 0x694c #define DQDLYPUCTLCH0 0x6950 #define DQDLYPDCTLCH0 0x6954 #define DQTCOPUCTLCH0 0x6958 -#define DQTCOPDCTLCH0 0x695C +#define DQTCOPDCTLCH0 0x695c #define CMDDRVPUCTLCH0 0x6968 -#define CMDDRVPDCTLCH0 0x696C +#define CMDDRVPDCTLCH0 0x696c #define CMDDLYPUCTLCH0 0x6970 #define CMDDLYPDCTLCH0 0x6974 #define CLKODTPUCTLCH0 0x6980 #define CLKODTPDCTLCH0 0x6984 #define CLKDRVPUCTLCH0 0x6988 -#define CLKDRVPDCTLCH0 0x698C +#define CLKDRVPDCTLCH0 0x698c #define CLKDLYPUCTLCH0 0x6990 #define CLKDLYPDCTLCH0 0x6994 #define CLKTCOPUCTLCH0 0x6998 -#define CLKTCOPDCTLCH0 0x699C -#define DQSODTPUCTLCH0 0x69A0 -#define DQSODTPDCTLCH0 0x69A4 -#define DQSDRVPUCTLCH0 0x69A8 -#define DQSDRVPDCTLCH0 0x69AC -#define DQSDLYPUCTLCH0 0x69B0 -#define DQSDLYPDCTLCH0 0x69B4 -#define DQSTCOPUCTLCH0 0x69B8 -#define DQSTCOPDCTLCH0 0x69BC -#define CTLDRVPUCTLCH0 0x69C8 -#define CTLDRVPDCTLCH0 0x69CC -#define CTLDLYPUCTLCH0 0x69D0 -#define CTLDLYPDCTLCH0 0x69D4 -#define FNLUPDTCTLCH0 0x69F0 +#define CLKTCOPDCTLCH0 0x699c +#define DQSODTPUCTLCH0 0x69a0 +#define DQSODTPDCTLCH0 0x69a4 +#define DQSDRVPUCTLCH0 0x69a8 +#define DQSDRVPDCTLCH0 0x69ac +#define DQSDLYPUCTLCH0 0x69b0 +#define DQSDLYPDCTLCH0 0x69b4 +#define DQSTCOPUCTLCH0 0x69b8 +#define DQSTCOPDCTLCH0 0x69bc +#define CTLDRVPUCTLCH0 0x69c8 +#define CTLDRVPDCTLCH0 0x69cc +#define CTLDLYPUCTLCH0 0x69d0 +#define CTLDLYPDCTLCH0 0x69d4 +#define FNLUPDTCTLCH0 0x69f0 /* PLL */ #define MPLLCTRL0 0x7800 @@ -332,17 +419,17 @@ #define MPLLDFT 0x7828 #define MPLLMON0CTL 0x7830 #define MPLLMON1CTL 0x7838 -#define MPLLMON2CTL 0x783C +#define MPLLMON2CTL 0x783c #define SFRTRIM 0x7850 #define MPLLDFTOUT0 0x7858 -#define MPLLDFTOUT1 0x785C +#define MPLLDFTOUT1 0x785c #define MASTERRSTN 0x7880 #define PLLLOCKDEL 0x7884 #define SFRDEL 0x7888 -#define CRUVISALANECR0 0x78F0 -#define CRUVISALANECR1 0x78F4 -#define CRUVISACONTROLCR 0x78F8 -#define IOSFVISALANECR0 0x78FC +#define CRUVISALANECR0 0x78f0 +#define CRUVISALANECR1 0x78f4 +#define CRUVISACONTROLCR 0x78f8 +#define IOSFVISALANECR0 0x78fc #define IOSFVISALANECR1 0x7900 #define IOSFVISACONTROLCR 0x7904 @@ -350,7 +437,7 @@ /* DRAM Specific Message Bus OpCodes */ #define MSG_OP_DRAM_INIT 0x68 -#define MSG_OP_DRAM_WAKE 0xCA +#define MSG_OP_DRAM_WAKE 0xca #define SAMPLE_SIZE 6 @@ -377,9 +464,9 @@ /* offset into "vref_codes[]" for minimum allowed VREF setting */ #define VREF_MIN 0x00 /* offset into "vref_codes[]" for maximum allowed VREF setting */ -#define VREF_MAX 0x3F +#define VREF_MAX 0x3f #define RDQS_MIN 0x00 /* minimum RDQS delay value */ -#define RDQS_MAX 0x3F /* maximum RDQS delay value */ +#define RDQS_MAX 0x3f /* maximum RDQS delay value */ /* how many WDQ codes to jump while margining */ #define WDQ_STEP 1 -- 2.39.5