From 3630066843b7ca6b2cd12911d3e2fe3314cd4549 Mon Sep 17 00:00:00 2001 From: Howard Chu Date: Sat, 26 Jul 2014 18:16:02 -0700 Subject: [PATCH] Fix MIPS cache coherency on Linux MIPS chips require manual control of on-chip caches. The cacheflush syscall being used here only exists on MIPS Linux, other OSs will require revisiting. --- libraries/liblmdb/mdb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/libraries/liblmdb/mdb.c b/libraries/liblmdb/mdb.c index 84477c4285..e1d774887b 100644 --- a/libraries/liblmdb/mdb.c +++ b/libraries/liblmdb/mdb.c @@ -70,6 +70,15 @@ #include #endif +#if defined(__mips) && defined(__linux) +/* MIPS has cache coherency issues, requires explicit cache control */ +#include +extern int cacheflush(char *addr, int nbytes, int cache); +#define CACHEFLUSH(addr, bytes, cache) cacheflush(addr, bytes, cache) +#else +#define CACHEFLUSH(addr, bytes, cache) +#endif + #include #include #include @@ -3581,6 +3590,11 @@ done: if (env->me_txns) env->me_txns->mti_txnid = txn->mt_txnid; + /* MIPS has cache coherency issues, this is a no-op everywhere else */ + if (!(env->me_flags & MDB_WRITEMAP)) { + CACHEFLUSH(env->me_map, txn->mt_next_pgno * env->me_psize, DCACHE); + } + return MDB_SUCCESS; } -- 2.39.5