From 3776f9b79f83f36d91cdf959b90c3c82d087f912 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Wed, 22 Sep 2010 12:48:21 +0000 Subject: [PATCH] Starting point for the RX RDK version of the demo app. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1121 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../RTOSDemo/DefaultSession.hsf | 965 ++ .../RTOSDemo/DefaultSession.ini | 30 + .../RTOSDemo/FreeRTOSConfig.h | 153 + .../RTOSDemo/GNU-Files/hwinit.c | 55 + .../RTOSDemo/GNU-Files/inthandler.c | 431 + .../RTOSDemo/GNU-Files/start.asm | 94 + .../RTOSDemo/HighFrequencyTimerTest.c | 178 + .../RTOSDemo/IntQueueTimer.c | 170 + Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/ParTest.c | 254 + .../RTOSDemo/RTOSDemo.hwp | 477 + .../RTOSDemo/RTOSDemo.nav | Bin 0 -> 126816 bytes .../RTOSDemo/RTOSDemo.tps | 48 + .../RTOSDemo/Renesas-Files/hwsetup.c | 230 + .../RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf | 267 + .../RTOSDemo/include/IntQueueTimer.h | 62 + .../RTOSDemo/include/inthandler.h | 714 + .../RTOSDemo/include/iodefine.h | 14211 ++++++++++++++++ .../RTOSDemo/include/typedefine.h | 23 + .../RTOSDemo/include/yrdkrx62ndef.h | 104 + .../RTOSDemo/main-blinky.c | 227 + .../RTOSDemo/main-full.c | 671 + .../RX600_RX62N-RDK_GNURX/RTOSDemo/uIP_Task.c | 270 + Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/vects.c | 614 + .../RTOSDemo/webserver/EMAC.c | 572 + .../RTOSDemo/webserver/httpd-cgi.c | 277 + .../RTOSDemo/webserver/httpd-fs/404.html | 8 + .../RTOSDemo/webserver/httpd-fs/index.html | 13 + .../RTOSDemo/webserver/httpd-fs/index.shtml | 20 + .../RTOSDemo/webserver/httpd-fs/io.shtml | 28 + .../RTOSDemo/webserver/httpd-fs/logo.jpg | Bin 0 -> 32592 bytes .../RTOSDemo/webserver/httpd-fs/runtime.shtml | 20 + .../RTOSDemo/webserver/httpd-fs/stats.shtml | 47 + .../RTOSDemo/webserver/httpd-fs/tcp.shtml | 21 + .../RTOSDemo/webserver/httpd-fsdata.c | 3871 +++++ .../RTOSDemo/webserver/makefsdata | 79 + .../RTOSDemo/webserver/phy.c | 474 + .../RTOSDemo/webserver/phy.h | 84 + .../RTOSDemo/webserver/r_ether.h | 185 + .../RTOSDemo/webserver/uip-conf.h | 167 + .../RTOSDemo/webserver/webserver.h | 47 + .../RX600_RX62N_RSK_GNURX.Hbp | 2 + .../RX600_RX62N_RSK_GNURX.hws | 40 + .../RX600_RX62N_RSK_GNURX.tws | 15 + 43 files changed, 26218 insertions(+) create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/DefaultSession.hsf create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/DefaultSession.ini create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/FreeRTOSConfig.h create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/hwinit.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/inthandler.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/start.asm create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/HighFrequencyTimerTest.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/IntQueueTimer.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/ParTest.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/RTOSDemo.hwp create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/RTOSDemo.nav create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/RTOSDemo.tps create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/Renesas-Files/hwsetup.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/IntQueueTimer.h create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/inthandler.h create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/iodefine.h create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/typedefine.h create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/yrdkrx62ndef.h create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/main-blinky.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/main-full.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/uIP_Task.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/vects.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/EMAC.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-cgi.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/404.html create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/index.html create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/index.shtml create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/io.shtml create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/logo.jpg create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/runtime.shtml create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/stats.shtml create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/tcp.shtml create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fsdata.c create mode 100644 Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/makefsdata create mode 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+"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000013_SYMBOL}" "TOOLBAR 0" 59419 2 5 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000014_CODE}" "TOOLBAR 0" 59419 2 9 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000015_PERFORMANCE}" "TOOLBAR 0" 59419 2 10 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000016_GRAPHIC}" "TOOLBAR 0" 59419 2 8 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000023_RTOS}" "TOOLBAR 0" 59419 2 11 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000025_HELPSYSTEMTOOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000027_EVENT}" "TOOLBAR 0" 59419 2 7 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\GCC\RX600\port_asm.asm" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-MDK_GNURX\RTOSDemo\GNU-Files\start.asm" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-MDK_GNURX\RTOSDemo\main-full.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\GCC\RX600\port.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-MDK_GNURX\RTOSDemo\RegTest.asm" +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\GCC\RX600\portmacro.h" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-MDK_GNURX\RTOSDemo\FreeRTOSConfig.h" +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" +[TARGET_NAME] +"RX600 E1/E20 SYSTEM" "" 0 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +"SBK_TAR_EMUE100|Exception" 1 +"SBK_TAR_EMUE100|BreakCondition" 1 +"SBK_TAR_EMUE100|TaskID" 1 +"SBK_TAR_EMUE100|PC" 1 +"SBK_TAR_EMUE100|ExecutionTime" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"" +[DOWNLOAD_MODULES] +"$(CONFIGDIR)\$(PROJECTNAME).x" 0 "Elf/Dwarf2_KPIT" 0 1 1 0 +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"FALSE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"Elf/Dwarf2_KPIT" +[FLASH_DETAILS] +"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +"c:\e\dev\freertos\workingcopy\demo\rx600_rx62n-mdk_gnurx\rtosdemo\main-full.c" 298 -510103 1 "{00000000-0000-0000-C000-000000000046}" "" +"c:\e\dev\freertos\workingcopy\demo\rx600_rx62n-mdk_gnurx\rtosdemo\main-full.c" 581 33414224 1 "{00000000-0000-0000-C000-000000000046}" "" +"c:\e\dev\freertos\workingcopy\demo\rx600_rx62n-mdk_gnurx\rtosdemo\regtest.asm" 144 -524093 1 "{00000000-0000-0000-C000-000000000046}" "" +"c:\e\dev\freertos\workingcopy\demo\rx600_rx62n-mdk_gnurx\rtosdemo\regtest.asm" 222 -523943 1 "{00000000-0000-0000-C000-000000000046}" "" +"c:\e\dev\freertos\workingcopy\source\portable\gcc\rx600\port.c" 255 -511337 1 "{00000000-0000-0000-C000-000000000046}" "" +"" -1 -523932 1 "{110BABEB-6DCB-4265-8236-8888EECAB6AB}" "" +"" -1 -509967 1 "{110BABEB-6DCB-4265-8236-8888EECAB6AB}" "" +[END] diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/DefaultSession.ini b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/DefaultSession.ini new file mode 100644 index 000000000..5e7c5edd5 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/DefaultSession.ini @@ -0,0 +1,30 @@ +[Init_DeviceSetting] +DebugMode=0 +PowerOut=0 +ResetRelease=0 +EmulatorSerial= +McuGroup=RX62N Group +Device=R5F562N8 +McuFileDir=RX62NGr +SupplyVoltage=-1 +[Init_CommunicationClock] +JtagClock=16.5 +JtagClockValue=10 +[Init_EmulatorSetting] +FirstStartUp=0 +HideNext=0 +ConnectionDlgAutoClose=1 +[CFG_MCU] +PrevDevice=R5F562N8 +ProcessorMode=0 +EXTAL=12.0000 +WorkRam=0x17000 +[CFG_SYSTEM] +CpuReWrite=0 +PerfCounterUser=0 +TraceDebugAs=0 +[CFG_FLASHCLEAR_R5F562N8_00] +BlockCount=54 +BlockData=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +[Config_Property] +HideNext=0 diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/FreeRTOSConfig.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..b8e32de58 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,153 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Board specifics. */ +#include "yrdkrx62ndef.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ICLK_FREQUENCY ) /* Set in rskrx62ndef.h. */ +#define configPERIPHERAL_CLOCK_HZ ( PCLK_FREQUENCY ) /* Set in rskrx62ndef.h. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 + +extern volatile unsigned long ulHighFrequencyTickCount; +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() portNOP() /* Run time stats use the same timer as the high frequency timer test. */ +#define portGET_RUN_TIME_COUNTER_VALUE() ulHighFrequencyTickCount + + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure flase positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 2 ) +#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 3 ) + + +/*----------------------------------------------------------- + * Ethernet configuration. + *-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x12 +#define configMAC_ADDR2 0x13 +#define configMAC_ADDR3 0x10 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 200 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/hwinit.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/hwinit.c new file mode 100644 index 000000000..b6660aaa0 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/hwinit.c @@ -0,0 +1,55 @@ +/***********************************************************************/ +/* */ +/* FILE :hwinit.c */ +/* DATE :Wed, Aug 25, 2010 */ +/* DESCRIPTION :Hardware Setup file */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by KPIT GNU Project Generator. */ +/* */ +/***********************************************************************/ + + + +#include "iodefine.h" +#ifdef __cplusplus +extern "C" { +#endif +extern void hw_initialise(void); +#ifdef __cplusplus +} +#endif + +void hw_initialise(void) +{ +/* + SCI.SMR.BYTE = 0; + SCI.SMR.BIT.CA = 1; + SCI.SMR.BIT.CHR = 1; + SCI.SMR.BIT.OE = 1; + SCI.SMR.BIT.STOP = 1; + SCI.SMR.BIT.MP = 1; + SCI.SMR.BIT.CKS = 3; + SCI.BRR = 0; + SCI.SCR.BYTE = 0; + SCI.SCR.BIT.TIE = 1; + SCI.SCR.BIT.RIE = 1; + SCI.SCR.BIT.TE = 1; + SCI.SCR.BIT.RE = 1; + SCI.SCR.BIT.MPIE = 1; + SCI.SCR.BIT.TEIE = 1; + SCI.SCR.BIT.CKE = 3; + SCI.TDR = 0; + SCI.SSR.BYTE = 0; + SCI.SSR.BIT.TDRE = 1; + SCI.SSR.BIT.RDRF = 1; + SCI.SSR.BIT.ORER = 1; + SCI.SSR.BIT.FER = 1; + SCI.SSR.BIT.PER = 1; + SCI.SSR.BIT.TEND = 1; + SCI.SSR.BIT.MPB = 1; + SCI.SSR.BIT.MPBT = 1; + SCI.RDR = 0; + +*/ +} diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/inthandler.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/inthandler.c new file mode 100644 index 000000000..7334d3e9c --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/inthandler.c @@ -0,0 +1,431 @@ +/***********************************************************************/ +/* */ +/* FILE :inthandler.c */ +/* DATE :Wed, Aug 25, 2010 */ +/* DESCRIPTION :Interrupt Handler */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by KPIT GNU Project Generator. */ +/* */ +/***********************************************************************/ + + + + +#include "inthandler.h" + +// Exception(Supervisor Instruction) +void INT_Excep_SuperVisorInst(void){/* brk(); */} + +// Exception(Undefined Instruction) +void INT_Excep_UndefinedInst(void){ __asm volatile ("brk"); } + +// Exception(Floating Point) +void INT_Excep_FloatingPoint(void){/* brk(); */} + +// NMI +void INT_NonMaskableInterrupt(void){/* brk(); */} + +// Dummy +void Dummy(void){/* brk(); */} + +// BRK +void INT_Excep_BRK(void){ /*wait(); */} + +// BUSERR +void INT_Excep_BUSERR(void){ } + +// FCU_FCUERR +void INT_Excep_FCU_FCUERR(void){ } + +// FCU_FRDYI +void INT_Excep_FCU_FRDYI(void){ } + +// CMTU0_CMT0 - (RB) NOTE This has been replaced in the vector table with vTickISR(). +void INT_Excep_CMTU0_CMT0(void){ } + +// CMTU0_CMT1 +void INT_Excep_CMTU0_CMT1(void){ } + +// CMTU1_CMT2 +void INT_Excep_CMTU1_CMT2(void){ } + +// CMTU1_CMT3 +void INT_Excep_CMTU1_CMT3(void){ } + +// IRQ0 +void INT_Excep_IRQ0(void){ } + +// IRQ1 +void INT_Excep_IRQ1(void){ } + +// IRQ2 +void INT_Excep_IRQ2(void){ } + +// IRQ3 +void INT_Excep_IRQ3(void){ } + +// IRQ4 +void INT_Excep_IRQ4(void){ } + +// IRQ5 +void INT_Excep_IRQ5(void){ } + +// IRQ6 +void INT_Excep_IRQ6(void){ } + +// IRQ7 +void INT_Excep_IRQ7(void){ } + +// IRQ8 +void INT_Excep_IRQ8(void){ } + +// IRQ9 +void INT_Excep_IRQ9(void){ } + +// IRQ10 +void INT_Excep_IRQ10(void){ } + +// IRQ11 +void INT_Excep_IRQ11(void){ } + +// IRQ12 +void INT_Excep_IRQ12(void){ } + +// IRQ13 +void INT_Excep_IRQ13(void){ } + +// IRQ14 +void INT_Excep_IRQ14(void){ } + +// IRQ15 +void INT_Excep_IRQ15(void){ } + +// WDT_WOVI +void INT_Excep_WDT_WOVI(void){ } + +// AD0_ADI0 +void INT_Excep_AD0_ADI0(void){ } + +// AD1_ADI1 +void INT_Excep_AD1_ADI1(void){ } + +// AD2_ADI2 +void INT_Excep_AD2_ADI2(void){ } + +// AD3_ADI3 +void INT_Excep_AD3_ADI3(void){ } + +// TPU0_TGI0A +void INT_Excep_TPU0_TGI0A(void){ } + +// TPU0_TGI0B +void INT_Excep_TPU0_TGI0B(void){ } + +// TPU0_TGI0C +void INT_Excep_TPU0_TGI0C(void){ } + +// TPU0_TGI0D +void INT_Excep_TPU0_TGI0D(void){ } + +// TPU0_TCI0V +void INT_Excep_TPU0_TCI0V(void){ } + +// TPU1_TGI1A +void INT_Excep_TPU1_TGI1A(void){ } + +// TPU1_TGI1B +void INT_Excep_TPU1_TGI1B(void){ } + +// TPU1_TCI1V +void INT_Excep_TPU1_TCI1V(void){ } + +// TPU1_TCI1U +void INT_Excep_TPU1_TCI1U(void){ } + +// TPU2_TGI2A +void INT_Excep_TPU2_TGI2A(void){ } + +// TPU2_TGI2B +void INT_Excep_TPU2_TGI2B(void){ } + +// TPU2_TCI2V +void INT_Excep_TPU2_TCI2V(void){ } + +// TPU2_TCI2U +void INT_Excep_TPU2_TCI2U(void){ } + +// TPU3_TGI3A +void INT_Excep_TPU3_TGI3A(void){ } + +// TPU3_TGI3B +void INT_Excep_TPU3_TGI3B(void){ } + +// TPU3_TGI3C +void INT_Excep_TPU3_TGI3C(void){ } + +// TPU3_TGI3D +void INT_Excep_TPU3_TGI3D(void){ } + +// TPU3_TCI3V +void INT_Excep_TPU3_TCI3V(void){ } + +// TPU4_TGI4A +void INT_Excep_TPU4_TGI4A(void){ } + +// TPU4_TGI4B +void INT_Excep_TPU4_TGI4B(void){ } + +// TPU4_TCI4V +void INT_Excep_TPU4_TCI4V(void){ } + +// TPU4_TCI4U +void INT_Excep_TPU4_TCI4U(void){ } + +// TPU5_TGI5A +void INT_Excep_TPU5_TGI5A(void){ } + +// TPU5_TGI5B +void INT_Excep_TPU5_TGI5B(void){ } + +// TPU5_TCI5V +void INT_Excep_TPU5_TCI5V(void){ } + +// TPU5_TCI5U +void INT_Excep_TPU5_TCI5U(void){ } + +// TPU6_TGI6A +void INT_Excep_TPU6_TGI6A(void){ } + +// TPU6_TGI6B +void INT_Excep_TPU6_TGI6B(void){ } + +// TPU6_TGI6C +void INT_Excep_TPU6_TGI6C(void){ } + +// TPU6_TGI6D +void INT_Excep_TPU6_TGI6D(void){ } + +// TPU6_TCI6V +void INT_Excep_TPU6_TCI6V(void){ } + +// TPU7_TGI7A +void INT_Excep_TPU7_TGI7A(void){ } + +// TPU7_TGI7B +void INT_Excep_TPU7_TGI7B(void){ } + +// TPU7_TCI7V +void INT_Excep_TPU7_TCI7V(void){ } + +// TPU7_TCI7U +void INT_Excep_TPU7_TCI7U(void){ } + +// TPU8_TGI8A +void INT_Excep_TPU8_TGI8A(void){ } + +// TPU8_TGI8B +void INT_Excep_TPU8_TGI8B(void){ } + +// TPU8_TCI8V +void INT_Excep_TPU8_TCI8V(void){ } + +// TPU8_TCI8U +void INT_Excep_TPU8_TCI8U(void){ } + +// TPU9_TGI9A +void INT_Excep_TPU9_TGI9A(void){ } + +// TPU9_TGI9B +void INT_Excep_TPU9_TGI9B(void){ } + +// TPU9_TGI9C +void INT_Excep_TPU9_TGI9C(void){ } + +// TPU9_TGI9D +void INT_Excep_TPU9_TGI9D(void){ } + +// TPU9_TCI9V +void INT_Excep_TPU9_TCI9V(void){ } + +// TPU10_TGI10A +void INT_Excep_TPU10_TGI10A(void){ } + +// TPU10_TGI10B +void INT_Excep_TPU10_TGI10B(void){ } + +// TPU10_TCI10V +void INT_Excep_TPU10_TCI10V(void){ } + +// TPU10_TCI10U +void INT_Excep_TPU10_TCI10U(void){ } + +// TPU11_TGI11A +void INT_Excep_TPU11_TGI11A(void){ } + +// TPU11_TGI11B +void INT_Excep_TPU11_TGI11B(void){ } + +// TPU11_TCI11V +void INT_Excep_TPU11_TCI11V(void){ } + +// TPU11_TCI11U +void INT_Excep_TPU11_TCI11U(void){ } + +// TMR0_CMI0A +void INT_Excep_TMR0_CMI0A(void){ } + +// TMR0_CMI0B +void INT_Excep_TMR0_CMI0B(void){ } + +// TMR0_OV0I +void INT_Excep_TMR0_OV0I(void){ } + +// TMR1_CMI1A +void INT_Excep_TMR1_CMI1A(void){ } + +// TMR1_CMI1B +void INT_Excep_TMR1_CMI1B(void){ } + +// TMR1_OV1I +void INT_Excep_TMR1_OV1I(void){ } + +// TMR2_CMI2A +void INT_Excep_TMR2_CMI2A(void){ } + +// TMR2_CMI2B +void INT_Excep_TMR2_CMI2B(void){ } + +// TMR2_OV2I +void INT_Excep_TMR2_OV2I(void){ } + +// TMR3_CMI3A +void INT_Excep_TMR3_CMI3A(void){ } + +// TMR3_CMI3B +void INT_Excep_TMR3_CMI3B(void){ } + +// TMR3_OV3I +void INT_Excep_TMR3_OV3I(void){ } + +// DMAC_DMTEND0 +void INT_Excep_DMAC_DMTEND0(void){ } + +// DMAC_DMTEND1 +void INT_Excep_DMAC_DMTEND1(void){ } + +// DMAC_DMTEND2 +void INT_Excep_DMAC_DMTEND2(void){ } + +// DMAC_DMTEND3 +void INT_Excep_DMAC_DMTEND3(void){ } + +// SCI0_ERI0 +void INT_Excep_SCI0_ERI0(void){ } + +// SCI0_RXI0 +void INT_Excep_SCI0_RXI0(void){ } + +// SCI0_TXI0 +void INT_Excep_SCI0_TXI0(void){ } + +// SCI0_TEI0 +void INT_Excep_SCI0_TEI0(void){ } + +// SCI1_ERI1 +void INT_Excep_SCI1_ERI1(void){ } + +// SCI1_RXI1 +void INT_Excep_SCI1_RXI1(void){ } + +// SCI1_TXI1 +void INT_Excep_SCI1_TXI1(void){ } + +// SCI1_TEI1 +void INT_Excep_SCI1_TEI1(void){ } + +// SCI2_ERI2 +void INT_Excep_SCI2_ERI2(void){ } + +// SCI2_RXI2 +void INT_Excep_SCI2_RXI2(void){ } + +// SCI2_TXI2 +void INT_Excep_SCI2_TXI2(void){ } + +// SCI2_TEI2 +void INT_Excep_SCI2_TEI2(void){ } + +// SCI3_ERI3 +void INT_Excep_SCI3_ERI3(void){ } + +// SCI3_RXI3 +void INT_Excep_SCI3_RXI3(void){ } + +// SCI3_TXI3 +void INT_Excep_SCI3_TXI3(void){ } + +// SCI3_TEI3 +void INT_Excep_SCI3_TEI3(void){ } + +// SCI4_ERI4 +void INT_Excep_SCI4_ERI4(void){ } + +// SCI4_RXI4 +void INT_Excep_SCI4_RXI4(void){ } + +// SCI4_TXI4 +void INT_Excep_SCI4_TXI4(void){ } + +// SCI4_TEI4 +void INT_Excep_SCI4_TEI4(void){ } + +// SCI5_ERI5 +void INT_Excep_SCI5_ERI5(void){ } + +// SCI5_RXI5 +void INT_Excep_SCI5_RXI5(void){ } + +// SCI5_TXI5 +void INT_Excep_SCI5_TXI5(void){ } + +// SCI5_TEI5 +void INT_Excep_SCI5_TEI5(void){ } + +// SCI6_ERI6 +void INT_Excep_SCI6_ERI6(void){ } + +// SCI6_RXI6 +void INT_Excep_SCI6_RXI6(void){ } + +// SCI6_TXI6 +void INT_Excep_SCI6_TXI6(void){ } + +// SCI6_TEI6 +void INT_Excep_SCI6_TEI6(void){ } + +// RIIC0_EEI0 +void INT_Excep_RIIC0_EEI0(void){ } + +// RIIC0_RXI0 +void INT_Excep_RIIC0_RXI0(void){ } + +// RIIC0_TXI0 +void INT_Excep_RIIC0_TXI0(void){ } + +// RIIC0_TEI0 +void INT_Excep_RIIC0_TEI0(void){ } + +// RIIC1_EEI1 +void INT_Excep_RIIC1_EEI1(void){ } + +// RIIC1_RXI1 +void INT_Excep_RIIC1_RXI1(void){ } + +// RIIC1_TXI1 +void INT_Excep_RIIC1_TXI1(void){ } + +// RIIC1_TEI1 +void INT_Excep_RIIC1_TEI1(void){ } + + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/start.asm b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/start.asm new file mode 100644 index 000000000..677b81f41 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/GNU-Files/start.asm @@ -0,0 +1,94 @@ +/*------------------------------------------------------------------------ + | + FILE : start.asm | + DATE : Wed, Aug 25, 2010 | + DESCRIPTION : Reset Program | + CPU TYPE : Other | + | + This file is generated by KPIT GNU Project Generator (Ver.4.5). | + | +------------------------------------------------------------------------*/ + + + + /*Start.asm*/ + + .list + .section .text + .global _start /*global Start routine */ + +#ifdef CPPAPP +___dso_handle: + .global ___dso_handle +#endif + + .extern _hw_initialise /*external Sub-routine to initialise Hardware*/ + .extern _data + .extern _mdata + .extern _ebss + .extern _bss + .extern _edata + .extern _main + .extern _ustack + .extern _istack + .extern _rvectors +#if DEBUG + .extern _exit +#endif + + +_start: +/* initialise user stack pointer */ + mvtc #_ustack,USP + +/* initialise interrupt stack pointer */ + mvtc #_istack,ISP + +/* setup intb */ + mvtc #_rvectors_start, intb /* INTERRUPT VECTOR ADDRESS definition */ + +/* setup FPSW */ + mvtc #100h, fpsw + +/* load data section from ROM to RAM */ + + mov #_mdata,r2 /* src ROM address of data section in R2 */ + mov #_data,r1 /* dest start RAM address of data section in R1 */ + mov #_edata,r3 /* end RAM address of data section in R3 */ + sub r1,r3 /* size of data section in R3 (R3=R3-R1) */ + smovf /* block copy R3 bytes from R2 to R1 */ + +/* bss initialisation : zero out bss */ + + mov #00h,r2 /* load R2 reg with zero */ + mov #_ebss, r3 /* store the end address of bss in R3 */ + mov #_bss, r1 /* store the start address of bss in R1 */ + sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */ + sstr.b + +/* call the hardware initialiser */ + bsr.a _hw_initialise + nop + +/* setup PSW */ +// mvtc #10000h, psw /* Set Ubit & Ibit for PSW */ + +/* change PSW PM to user-mode */ +// MVFC PSW,R1 +// OR #00100000h,R1 +// PUSH.L R1 +// MVFC PC,R1 +// ADD #10,R1 +// PUSH.L R1 +// RTE +// NOP +// NOP + +/* start user program */ + bsr.a _main + +/* call to exit*/ +_exit: + bsr.a _exit + + .end diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/HighFrequencyTimerTest.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/HighFrequencyTimerTest.c new file mode 100644 index 000000000..6c66a6db5 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/HighFrequencyTimerTest.c @@ -0,0 +1,178 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * High frequency timer test as described in main.c. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +/* The set frequency of the interrupt. Deviations from this are measured as +the jitter. */ +#define timerINTERRUPT_FREQUENCY ( 20000UL ) + +/* The expected time between each of the timer interrupts - if the jitter was +zero. */ +#define timerEXPECTED_DIFFERENCE_VALUE ( ( unsigned short ) ( ( configPERIPHERAL_CLOCK_HZ / 8UL ) / timerINTERRUPT_FREQUENCY ) ) + +/* The highest available interrupt priority. */ +#define timerHIGHEST_PRIORITY ( 15 ) + +/* Misc defines. */ +#define timerTIMER_3_COUNT_VALUE ( *( ( unsigned short * ) 0x8801a ) ) /*( CMT3.CMCNT )*/ + +/*-----------------------------------------------------------*/ + +/* Interrupt wrapper and handler in which the jitter is measured. */ +void vTimer2_ISR_Wrapper( void ) __attribute__((naked)); +static void prvTimer2_ISR_Handler( void ) __attribute__((noinline)); + +/* Stores the value of the maximum recorded jitter between interrupts. This is +displayed on one of the served web pages. */ +volatile unsigned short usMaxJitter = 0; + +/* Counts the number of high frequency interrupts - used to generate the run +time stats. */ +volatile unsigned long ulHighFrequencyTickCount = 0UL; + +/*-----------------------------------------------------------*/ + +void vSetupHighFrequencyTimer( void ) +{ + /* Timer CMT2 is used to generate the interrupts, and CMT3 is used + to measure the jitter. */ + + /* Enable compare match timer 2 and 3. */ + MSTP( CMT2 ) = 0; + MSTP( CMT3 ) = 0; + + /* Interrupt on compare match. */ + CMT2.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT2.CMCR.BIT.CKS = 0; + CMT3.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT2_CMI2 ) = 1; + + /* ...and set its priority to the maximum possible, this is above the priority + set by configMAX_SYSCALL_INTERRUPT_PRIORITY so will nest. */ + _IPR( _CMT2_CMI2 ) = timerHIGHEST_PRIORITY; + + /* Start the timers. */ + CMT.CMSTR1.BIT.STR2 = 1; + CMT.CMSTR1.BIT.STR3 = 1; +} +/*-----------------------------------------------------------*/ + +void vTimer2_ISR_Wrapper( void ) +{ + portENTER_INTERRUPT(); + prvTimer2_ISR_Handler(); + portEXIT_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +static void prvTimer2_ISR_Handler( void ) +{ +volatile unsigned short usCurrentCount; +static unsigned short usMaxCount = 0; +static unsigned long ulErrorCount = 0UL; + + /* We use the timer 1 counter value to measure the clock cycles between + the timer 0 interrupts. First stop the clock. */ + CMT.CMSTR1.BIT.STR3 = 0; + portNOP(); + portNOP(); + usCurrentCount = timerTIMER_3_COUNT_VALUE; + + /* Is this the largest count we have measured yet? */ + if( usCurrentCount > usMaxCount ) + { + if( usCurrentCount > timerEXPECTED_DIFFERENCE_VALUE ) + { + usMaxJitter = usCurrentCount - timerEXPECTED_DIFFERENCE_VALUE; + } + else + { + /* This should not happen! */ + ulErrorCount++; + } + + usMaxCount = usCurrentCount; + } + + /* Used to generate the run time stats. */ + ulHighFrequencyTickCount++; + + /* Clear the timer. */ + timerTIMER_3_COUNT_VALUE = 0; + + /* Then start the clock again. */ + CMT.CMSTR1.BIT.STR3 = 1; +} + + + + + + + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/IntQueueTimer.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/IntQueueTimer.c new file mode 100644 index 000000000..31538a17c --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/IntQueueTimer.c @@ -0,0 +1,170 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2001UL ) + +/* Wrappers and handlers for the two timers used. See the documentation page +for this port on http://www.FreeRTOS.org for more information on writing +interrupt handlers. */ +void vT0_1_ISR_Wrapper( void ) __attribute((naked)); +void vT2_3_ISR_Wrapper( void ) __attribute((naked)); + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + IEN( TMR0, CMIA0 ) = 1; + IEN( TMR2, CMIA2 ) = 1; + + /* Set the timer interrupts to be above the kernel. The interrupts are + assigned different priorities so they nest with each other. */ + IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 ); + } + portEXIT_CRITICAL(); + + /* Ensure the interrupts are clear as they are edge detected. */ + IR( TMR0, CMIA0 ) = 0; + IR( TMR2, CMIA2 ) = 0; +} +/*-----------------------------------------------------------*/ + +void vT0_1_ISR_Wrapper( void ) +{ + /* This is a naked function. This macro saves registers then re-enables + interrupts. See the documentation for htis port on http://www.FreeRTOS.org + for more information on writing interrupts. */ + portENTER_INTERRUPT(); + + /* Call the handler that is part of the common code - this is where the + non-portable code ends and the actual test is performed. */ + portYIELD_FROM_ISR( xFirstTimerHandler() ); + + /* Restore registers, then return. */ + portEXIT_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vT2_3_ISR_Wrapper( void ) +{ + /* This is a naked function. This macro saves registers then re-enables + interrupts. See the documentation for htis port on http://www.FreeRTOS.org + for more information on writing interrupts. */ + portENTER_INTERRUPT(); + + /* Call the handler that is part of the common code - this is where the + non-portable code ends and the actual test is performed. */ + portYIELD_FROM_ISR( xSecondTimerHandler() ); + + /* Restore registers, then return. */ + portEXIT_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/ParTest.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/ParTest.c new file mode 100644 index 000000000..06caecdb5 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/ParTest.c @@ -0,0 +1,254 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/*----------------------------------------------------------- + * Simple IO routines to control the LEDs. + *-----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* Hardware specifics. */ +#include + +#define partestNUM_LEDS ( 12 ) + +long lParTestGetLEDState( unsigned long ulLED ); + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Port pin configuration is done by the low level set up prior to this + function being called. */ +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned long ulLED, signed long xValue ) +{ + if( ulLED < partestNUM_LEDS ) + { + if( xValue != 0 ) + { + /* Turn the LED on. */ + taskENTER_CRITICAL(); + { + switch( ulLED ) + { + case 0: LED4 = LED_ON; + break; + case 1: LED5 = LED_ON; + break; + case 2: LED6 = LED_ON; + break; + case 3: LED7 = LED_ON; + break; + case 4: LED8 = LED_ON; + break; + case 5: LED9 = LED_ON; + break; + case 6: LED10 = LED_ON; + break; + case 7: LED11 = LED_ON; + break; + case 8: LED12 = LED_ON; + break; + case 9: LED13 = LED_ON; + break; + case 10:LED14 = LED_ON; + break; + case 11:LED15 = LED_ON; + break; + } + } + taskEXIT_CRITICAL(); + } + else + { + /* Turn the LED off. */ + taskENTER_CRITICAL(); + { + switch( ulLED ) + { + case 0: LED4 = LED_OFF; + break; + case 1: LED5 = LED_OFF; + break; + case 2: LED6 = LED_OFF; + break; + case 3: LED7 = LED_OFF; + break; + case 4: LED8 = LED_OFF; + break; + case 5: LED9 = LED_OFF; + break; + case 6: LED10 = LED_OFF; + break; + case 7: LED11 = LED_OFF; + break; + case 8: LED12 = LED_OFF; + break; + case 9: LED13 = LED_OFF; + break; + case 10:LED14 = LED_OFF; + break; + case 11:LED15 = LED_OFF; + break; + } + + } + taskEXIT_CRITICAL(); + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned long ulLED ) +{ + if( ulLED < partestNUM_LEDS ) + { + taskENTER_CRITICAL(); + { + if( lParTestGetLEDState( ulLED ) != 0x00 ) + { + vParTestSetLED( ulLED, 0 ); + } + else + { + vParTestSetLED( ulLED, 1 ); + } + } + taskEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +long lParTestGetLEDState( unsigned long ulLED ) +{ +long lReturn = pdFALSE; + + if( ulLED < partestNUM_LEDS ) + { + switch( ulLED ) + { + case 0 : if( LED4 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 1 : if( LED5 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 2 : if( LED6 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 3 : if( LED7 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 4 : if( LED8 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 5 : if( LED9 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 6 : if( LED10 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 7 : if( LED11 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 8 : if( LED12 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 9 : if( LED13 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 10 : if( LED14 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 11 : if( LED15 != 0 ) + { + lReturn = pdTRUE; + } + break; + } + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + diff --git 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+[GENERAL_DATA_CONFIGURATION_Blinky] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Blinky] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +[GENERAL_DATA_CONFIGURATION_Debug] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Debug] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +[GENERAL_DATA_CONFIGURATION_Debug_RX600_E1_E20_SYSTEM] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug_RX600_E1_E20_SYSTEM] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +[GENERAL_DATA_CONFIGURATION_Debug_with_optimisation] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug_with_optimisation] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +[GENERAL_DATA_SESSION_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_SESSION_SessionRX600_E1_E20_SYSTEM] +[END] diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/Renesas-Files/hwsetup.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/Renesas-Files/hwsetup.c new file mode 100644 index 000000000..46d03858a --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/Renesas-Files/hwsetup.c @@ -0,0 +1,230 @@ +/****************************************************************************** +* DISCLAIMER + +* This software is supplied by Renesas Technology Corp. and is only +* intended for use with Renesas products. No other uses are authorized. + +* This software is owned by Renesas Technology Corp. and is protected under +* all applicable laws, including copyright laws. + +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES +* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, +* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY +* DISCLAIMED. + +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES +* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS +* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +* Renesas reserves the right, without notice, to make changes to this +* software and to discontinue the availability of this software. +* By using this software, you agree to the additional terms and +* conditions found by accessing the following link: +* http://www.renesas.com/disclaimer +****************************************************************************** +* Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved. +******************************************************************************* +* File Name : hwsetup.c +* Version : 1.00 +* Description : Power up hardware initializations +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.02.2010 1.00 First Release +******************************************************************************/ + + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include +#include "rskrx62ndef.h" +// #include "lcd.h" Uncomment this if an LCD is present. +#include "r_ether.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ +void io_set_cpg(void); +void ConfigurePortPins(void); +void EnablePeripheralModules(void); + +/****************************************************************************** +* Function Name: HardwareSetup +* Description : This function does initial setting for CPG port pins used in +* : the Demo including the MII pins of the Ethernet PHY connection. +* Arguments : none +* Return Value : none +******************************************************************************/ +void HardwareSetup(void) +{ + /* CPG setting */ + io_set_cpg(); + + /* Setup the port pins */ + ConfigurePortPins(); + + /* Enables peripherals */ + EnablePeripheralModules(); + +#if INCLUDE_LCD == 1 + /* Initialize display */ + InitialiseDisplay(); +#endif +} + +/****************************************************************************** +* Function Name: EnablePeripheralModules +* Description : Enables Peripheral Modules before use +* Arguments : none +* Return Value : none +******************************************************************************/ +void EnablePeripheralModules(void) +{ + /* Module standby clear */ + SYSTEM.MSTPCRB.BIT.MSTPB15 = 0; /* EtherC, EDMAC */ + SYSTEM.MSTPCRA.BIT.MSTPA15 = 0; /* CMT0 */ +} + +/****************************************************************************** +* Function Name: ConfigurePortPins +* Description : Configures port pins. +* Arguments : none +* Return Value : none +******************************************************************************/ +void ConfigurePortPins(void) +{ +/* Port pins default to inputs. To ensure safe initialisation set the pin states +before changing the data direction registers. This will avoid any unintentional +state changes on the external ports. +Many peripheral modules will override the setting of the port registers. Ensure +that the state is safe for external devices if the internal peripheral module is +disabled or powered down. */ + + /* ==== MII/RMII Pins setting ==== */ + /*--------------------------------------*/ + /* Port Function Control Register */ + /*--------------------------------------*/ +#if ETH_MODE_SEL == ETH_MII_MODE + /* EE=1, PHYMODE=1, ENETE3=1, ENETE2=0, ENETE1=1, ENETE0=0 (Ethernet) */ + IOPORT.PFENET.BYTE = 0x9A; +#endif /* ETH_MODE_SEL */ +#if ETH_MODE_SEL == ETH_RMII_MODE + /* EE=1, PHYMODE=0, ENETE3=0, ENETE2=0, ENETE1=1, ENETE0=0 (Ethernet) */ + IOPORT.PFENET.BYTE = 0x82; +#endif /* ETH_MODE_SEL */ + /*-------------------------------------------*/ + /* Input Buffer Control Register (ICR) */ + /*-------------------------------------------*/ +#if ETH_MODE_SEL == ETH_MII_MODE + /* P54=1 Set ET_LINKSTA input */ + PORT5.ICR.BIT.B4 = 1; + /* P71=1 Set ET_MDIO input */ + PORT7.ICR.BIT.B1 = 1; + /* P74=1 Set ET_ERXD1 input */ + PORT7.ICR.BIT.B4 = 1; + /* P75=1 Set ET_ERXD0 input */ + PORT7.ICR.BIT.B5 = 1; + /* P76=1 Set ET_RX_CLK input */ + PORT7.ICR.BIT.B6 = 1; + /* P77=1 Set ET_RX_ER input */ + PORT7.ICR.BIT.B7 = 1; + /* P83=1 Set ET_CRS input */ + PORT8.ICR.BIT.B3 = 1; + /* PC0=1 Set ET_ERXD3 input */ + PORTC.ICR.BIT.B0 = 1; + /* PC1=1 Set ET_ERXD2 input */ + PORTC.ICR.BIT.B1 = 1; + /* PC2=1 Set ET_RX_DV input */ + PORTC.ICR.BIT.B2 = 1; + /* PC4=1 Set EX_TX_CLK input */ + PORTC.ICR.BIT.B4 = 1; + /* PC7=1 Set ET_COL input */ + PORTC.ICR.BIT.B7 = 1; +#endif /* ETH_MODE_SEL */ +#if ETH_MODE_SEL == ETH_RMII_MODE + /* P54=1 Set ET_LINKSTA input */ + PORT5.ICR.BIT.B4 = 1; + /* P71=1 Set ET_MDIO input */ + PORT7.ICR.BIT.B1 = 1; + /* P74=1 Set RMII_RXD1 input */ + PORT7.ICR.BIT.B4 = 1; + /* P75=1 Set RMII_RXD0 input */ + PORT7.ICR.BIT.B5 = 1; + /* P76=1 Set REF50CLK input */ + PORT7.ICR.BIT.B6 = 1; + /* P77=1 Set RMII_RX_ER input */ + PORT7.ICR.BIT.B7 = 1; + /* P83=1 Set RMII_CRS_DV input */ + PORT8.ICR.BIT.B3 = 1; +#endif /* ETH_MODE_SEL */ + + /* Configure LED 0-5 pin settings */ + PORT0.DR.BIT.B2 = 1; + PORT0.DR.BIT.B3 = 1; + PORT0.DR.BIT.B5 = 1; + PORT3.DR.BIT.B4 = 1; + PORT6.DR.BIT.B0 = 1; + PORT7.DR.BIT.B3 = 1; + PORT0.DDR.BIT.B2 = 1; + PORT0.DDR.BIT.B3 = 1; + PORT0.DDR.BIT.B5 = 1; + PORT3.DDR.BIT.B4 = 1; + PORT6.DDR.BIT.B0 = 1; + PORT7.DDR.BIT.B3 = 1; + + /* Configure SW 1-3 pin settings */ + PORT0.DDR.BIT.B0 = 0; + PORT0.DDR.BIT.B1 = 0; + PORT0.DDR.BIT.B7 = 0; + PORT0.ICR.BIT.B0 = 1; + PORT0.ICR.BIT.B1 = 1; + PORT0.ICR.BIT.B7 = 1; + +#if INCLUDE_LCD == 1 + /* Set LCD pins as outputs */ + /* LCD-RS */ + PORT8.DDR.BIT.B4 = 1; + /* LCD-EN */ + PORT8.DDR.BIT.B5 = 1; + /*LCD-data */ + PORT9.DDR.BYTE = 0xF0; +#endif +} + +/****************************************************************************** +* Function Name: io_set_cpg +* Description : Sets up operating speed +* Arguments : none +* Return Value : none +******************************************************************************/ +void io_set_cpg(void) +{ +/* Set CPU PLL operating frequencies. Changes to the peripheral clock will require +changes to the debugger and flash kernel BRR settings. */ + + /* ==== CPG setting ==== */ + SYSTEM.SCKCR.LONG = 0x00020100; /* Clockin = 12MHz */ + /* I Clock = 96MHz, B Clock = 24MHz, */ + /* P Clock = 48MHz */ + +} + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf new file mode 100644 index 000000000..675ac306f --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf @@ -0,0 +1,267 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"FIRST_CONNECTION_TAG" "NO" +"RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_TRUE_STORE_TAG" +"{228DB593-0AB2-4EBE-A098-A2CABF094E46}RamMonitorCtrlViews" "0" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" 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"0000000000000000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_23" "0000000000000000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_24" "0000000040000140" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_25" "00008A613AE30000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_3" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_4" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_5" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_6" "000000000000ABB0" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_7" "0000000000000000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_8" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_9" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_COUNT" "26" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" +"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" +"{855C64C3-E49C-4450-9BCA-C9822566D214}OSObjectCtrlViews" "0" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_ADDRESS_NAME" "" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,," +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_SAMPLING_RATE" "1000" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ColumnWidth" "47,153,48" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_COUNT" "33" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideFLAGs" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideRadix" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0LastFileName" "" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16," +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEM" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ColumnWidth" "47,153,35" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_COUNT" "33" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideFLAGs" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideRadix" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0LastFileName" "" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16," +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewBInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEMViewB" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_ADDRESS_NAME" "" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_PALETTE_NAME" "" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_REDRAW_CONTINUOUSLY" "0,2" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_SAMPLEING_RATE" "1000" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "4" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "247" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth12" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEMCnt" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth12" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH_ITEMCnt" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth12" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH_ITEMCnt" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth12" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH_ITEMCnt" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInitial_Radix" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}RTOSDemoSessionRX600_E1_E20_SYSTEM" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndRecentFile_WatchRecord" "" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndRecentFile_WatchSave" "" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndUpdate_Interval" "100" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlDCEnable" "1" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlLocalEchoEnable" "1" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlLogFileName" "" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlPortBaudIndex" "0" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlPortName" "" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlSendDataTimeout" "50" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlViews" "1" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleWndInstanceKey0" "{WK_00000001_DEBUGCONSOLE}RTOSDemoSessionRX600_E1_E20_SYSTEM" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}StartStopCheckAfter" "0" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}StartStopCheckBefore" "0" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}StartStopExpAfter" "" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}StartStopExpBefore" "" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}T_SESSION_IS_SAVED" "YES" +"{CBEBB610-1516-11D4-8F2D-00409545B67B}ElfDwarf2Objects" "1" +"{CBEBB610-1516-11D4-8F2D-00409545B67B}LoadModule0OBJ_ELFDWARF2_ARRAY_EXPAND_LIMIT" "-1" +"{CBEBB610-1516-11D4-8F2D-00409545B67B}LoadModule0OBJ_ELFDWARF2_STATIC_MEM_EXPAND" "1" +"{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0" +"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlIOFile" "" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlSaveFileDir" "$(CONFIGDIR)" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlSaveFileName" "" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlViews" "0" +"{F923CED3-3318-4B43-B931-0AE76B289176}TaskTraceCtrlAnalyzeViews" "0" +"{F923CED3-3318-4B43-B931-0AE76B289176}TaskTraceCtrlFileSaveDirectory" "" +"{F923CED3-3318-4B43-B931-0AE76B289176}TaskTraceCtrlTraceViews" "0" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"Help" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_00000001_CmdLine}" "WINDOW" 59422 0 1 "0.07" 252 0 0 100 100 17 0 "32771|32772|32778|<>|32773|32774|<>" "0.0" +"{WK_00000001_DEBUGCONSOLE}RTOSDemoSessionRX600_E1_E20_SYSTEM" "WINDOW" 59422 5 0 "1.00" 146 0 0 350 200 17 0 "57634|57637|57633|<>|32781|32782|<>|32780|32785|32787" "0.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 252 560 340 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" +"{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEM" "WINDOW" 59421 0 0 "1.00" 413 0 0 350 200 2065 0 "" "0.0" +"{WK_00000001_WATCH}RTOSDemoSessionRX600_E1_E20_SYSTEM" "WINDOW" 59421 0 0 "1.00" 441 0 0 853 610 17 0 "32781|32783|<>|32771|32829|32772|32827|32773|<>|32786|<>|32810|32811" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 342 560 340 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 2 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 2 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000011_CPU}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000013_SYMBOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000014_CODE}" "TOOLBAR 0" 59419 2 9 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000015_PERFORMANCE}" "TOOLBAR 0" 59419 2 10 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000016_GRAPHIC}" "TOOLBAR 0" 59419 2 8 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000023_RTOS}" "TOOLBAR 0" 59419 2 11 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000025_HELPSYSTEMTOOL}" "TOOLBAR 0" 59419 2 5 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000027_EVENT}" "TOOLBAR 0" 59419 2 7 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RSK_GNURX\RTOSDemo\main-full.c" +[TARGET_NAME] +"RX600 E1/E20 SYSTEM" "" 0 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +"SBK_TAR_EMUE100|Exception" 1 +"SBK_TAR_EMUE100|BreakCondition" 1 +"SBK_TAR_EMUE100|TaskID" 1 +"SBK_TAR_EMUE100|PC" 1 +"SBK_TAR_EMUE100|ExecutionTime" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"Unknown Options" +[DOWNLOAD_MODULES] +"$(CONFIGDIR)\$(PROJECTNAME).x" 0 "Elf/Dwarf2_KPIT" 0 0 1 0 +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"TRUE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"Elf/Dwarf2_KPIT" +[FLASH_DETAILS] +"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/IntQueueTimer.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/IntQueueTimer.h new file mode 100644 index 000000000..ce40d7e29 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/IntQueueTimer.h @@ -0,0 +1,62 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/inthandler.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/inthandler.h new file mode 100644 index 000000000..f55efcaf6 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/inthandler.h @@ -0,0 +1,714 @@ +/***********************************************************************/ +/* */ +/* FILE :inthandler.h */ +/* DATE :Wed, Aug 25, 2010 */ +/* DESCRIPTION :Interrupt Handler Declarations */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by KPIT GNU Project Generator. */ +/* */ +/***********************************************************************/ + + + +#ifndef INTHANDLER_H +#define INTHANDLER_H + +// Exception(Supervisor Instruction) +void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt)); + +// Exception(Undefined Instruction) +void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt)); + +// Exception(Floating Point) +void INT_Excep_FloatingPoint(void) __attribute__ ((interrupt)); + +// NMI +void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt)); + +// Dummy +void Dummy (void) __attribute__ ((interrupt)); + +// BRK +void INT_Excep_BRK(void) __attribute__ ((interrupt)); + +// vector 1 reserved +// vector 2 reserved +// vector 3 reserved +// vector 4 reserved +// vector 5 reserved +// vector 6 reserved +// vector 7 reserved +// vector 8 reserved +// vector 9 reserved +// vector 10 reserved +// vector 11 reserved +// vector 12 reserved +// vector 13 reserved +// vector 14 reserved +// vector 15 reserved + +// BUSERR + +void INT_Excep_BUSERR(void) __attribute__ ((interrupt)); + +// vector 17 reserved +// vector 18 reserved +// vector 19 reserved +// vector 20 reserved + +// FCU_FCUERR + +void INT_Excep_FCU_FCUERR(void) __attribute__ ((interrupt)); + +// vector 22 reserved + +// FCU_FRDYI + +void INT_Excep_FCU_FRDYI(void) __attribute__ ((interrupt)); + +// vector 24 reserved +// vector 25 reserved +// vector 26 reserved +// vector 27 reserved + +// CMTU0_CMT0 + +void INT_Excep_CMTU0_CMT0(void) __attribute__ ((interrupt)); + +// CMTU0_CMT1 + +void INT_Excep_CMTU0_CMT1(void) __attribute__ ((interrupt)); + +// CMTU1_CMT2 + +void INT_Excep_CMTU1_CMT2(void) __attribute__ ((interrupt)); + +// CMTU1_CMT3 + +void INT_Excep_CMTU1_CMT3(void) __attribute__ ((interrupt)); + +// vector 32 reserved +// vector 33 reserved +// vector 34 reserved +// vector 35 reserved +// vector 36 reserved +// vector 37 reserved +// vector 38 reserved +// vector 39 reserved +// vector 40 reserved +// vector 41 reserved +// vector 42 reserved +// vector 43 reserved +// vector 44 reserved +// vector 45 reserved +// vector 46 reserved +// vector 47 reserved +// vector 48 reserved +// vector 49 reserved +// vector 50 reserved +// vector 51 reserved +// vector 52 reserved +// vector 53 reserved +// vector 54 reserved +// vector 55 reserved +// vector 56 reserved +// vector 57 reserved +// vector 58 reserved +// vector 59 reserved +// vector 60 reserved +// vector 61 reserved +// vector 62 reserved +// vector 63 reserved + +// IRQ0 + +void INT_Excep_IRQ0(void) __attribute__ ((interrupt)); + +// IRQ1 + +void INT_Excep_IRQ1(void) __attribute__ ((interrupt)); + +// IRQ2 + +void INT_Excep_IRQ2(void) __attribute__ ((interrupt)); + +// IRQ3 + +void INT_Excep_IRQ3(void) __attribute__ ((interrupt)); + +// IRQ4 + +void INT_Excep_IRQ4(void) __attribute__ ((interrupt)); + +// IRQ5 + +void INT_Excep_IRQ5(void) __attribute__ ((interrupt)); + +// IRQ6 + +void INT_Excep_IRQ6(void) __attribute__ ((interrupt)); + +// IRQ7 + +void INT_Excep_IRQ7(void) __attribute__ ((interrupt)); + +// IRQ8 + +void INT_Excep_IRQ8(void) __attribute__ ((interrupt)); + +// IRQ9 + +void INT_Excep_IRQ9(void) __attribute__ ((interrupt)); + +// IRQ10 + +void INT_Excep_IRQ10(void) __attribute__ ((interrupt)); + +// IRQ11 + +void INT_Excep_IRQ11(void) __attribute__ ((interrupt)); + +// IRQ12 + +void INT_Excep_IRQ12(void) __attribute__ ((interrupt)); + +// IRQ13 + +void INT_Excep_IRQ13(void) __attribute__ ((interrupt)); + +// IRQ14 + +void INT_Excep_IRQ14(void) __attribute__ ((interrupt)); + +// IRQ15 + +void INT_Excep_IRQ15(void) __attribute__ ((interrupt)); + +// vector 80 reserved +// vector 81 reserved +// vector 82 reserved +// vector 83 reserved +// vector 84 reserved +// vector 85 reserved +// vector 86 reserved +// vector 87 reserved +// vector 88 reserved +// vector 89 reserved +// vector 90 reserved +// vector 91 reserved +// vector 92 reserved +// vector 93 reserved +// vector 94 reserved +// vector 95 reserved + +// WDT_WOVI + +void INT_Excep_WDT_WOVI(void) __attribute__ ((interrupt)); + +// vector 97 reserved + +// AD0_ADI0 + +void INT_Excep_AD0_ADI0(void) __attribute__ ((interrupt)); + +// AD1_ADI1 + +void INT_Excep_AD1_ADI1(void) __attribute__ ((interrupt)); + +// AD2_ADI2 + +void INT_Excep_AD2_ADI2(void) __attribute__ ((interrupt)); + +// AD3_ADI3 + +void INT_Excep_AD3_ADI3(void) __attribute__ ((interrupt)); + +// vector 102 reserved +// vector 103 reserved + +// TPU0_TGI0A + +void INT_Excep_TPU0_TGI0A(void) __attribute__ ((interrupt)); + +// TPU0_TGI0B + +void INT_Excep_TPU0_TGI0B(void) __attribute__ ((interrupt)); + +// TPU0_TGI0C + +void INT_Excep_TPU0_TGI0C(void) __attribute__ ((interrupt)); + +// TPU0_TGI0D + +void INT_Excep_TPU0_TGI0D(void) __attribute__ ((interrupt)); + +// TPU0_TCI0V + +void INT_Excep_TPU0_TCI0V(void) __attribute__ ((interrupt)); + +// vector 109 reserved +// vector 110 reserved + +// TPU1_TGI1A + +void INT_Excep_TPU1_TGI1A(void) __attribute__ ((interrupt)); + +// TPU1_TGI1B + +void INT_Excep_TPU1_TGI1B(void) __attribute__ ((interrupt)); + +// vector 113 reserved +// vector 114 reserved + +// TPU1_TCI1V + +void INT_Excep_TPU1_TCI1V(void) __attribute__ ((interrupt)); + +// TPU1_TCI1U + +void INT_Excep_TPU1_TCI1U(void) __attribute__ ((interrupt)); + +// TPU2_TGI2A + +void INT_Excep_TPU2_TGI2A(void) __attribute__ ((interrupt)); + +// TPU2_TGI2B + +void INT_Excep_TPU2_TGI2B(void) __attribute__ ((interrupt)); + +// vector 119 reserved + +// TPU2_TCI2V + +void INT_Excep_TPU2_TCI2V(void) __attribute__ ((interrupt)); + +// TPU2_TCI2U + +void INT_Excep_TPU2_TCI2U(void) __attribute__ ((interrupt)); + +// TPU3_TGI3A + +void INT_Excep_TPU3_TGI3A(void) __attribute__ ((interrupt)); + +// TPU3_TGI3B + +void INT_Excep_TPU3_TGI3B(void) __attribute__ ((interrupt)); + +// TPU3_TGI3C + +void INT_Excep_TPU3_TGI3C(void) __attribute__ ((interrupt)); + +// TPU3_TGI3D + +void INT_Excep_TPU3_TGI3D(void) __attribute__ ((interrupt)); + +// TPU3_TCI3V + +void INT_Excep_TPU3_TCI3V(void) __attribute__ ((interrupt)); + +// TPU4_TGI4A + +void INT_Excep_TPU4_TGI4A(void) __attribute__ ((interrupt)); + +// TPU4_TGI4B + +void INT_Excep_TPU4_TGI4B(void) __attribute__ ((interrupt)); + +// vector 129 reserved +// vector 130 reserved + +// TPU4_TCI4V + +void INT_Excep_TPU4_TCI4V(void) __attribute__ ((interrupt)); + +// TPU4_TCI4U + +void INT_Excep_TPU4_TCI4U(void) __attribute__ ((interrupt)); + +// TPU5_TGI5A + +void INT_Excep_TPU5_TGI5A(void) __attribute__ ((interrupt)); + +// TPU5_TGI5B + +void INT_Excep_TPU5_TGI5B(void) __attribute__ ((interrupt)); + +// vector 135 reserved + +// TPU5_TCI5V + +void INT_Excep_TPU5_TCI5V(void) __attribute__ ((interrupt)); + +// TPU5_TCI5U + +void INT_Excep_TPU5_TCI5U(void) __attribute__ ((interrupt)); + +// TPU6_TGI6A + +void INT_Excep_TPU6_TGI6A(void) __attribute__ ((interrupt)); + +// TPU6_TGI6B + +void INT_Excep_TPU6_TGI6B(void) __attribute__ ((interrupt)); + +// TPU6_TGI6C + +void INT_Excep_TPU6_TGI6C(void) __attribute__ ((interrupt)); + +// TPU6_TGI6D + +void INT_Excep_TPU6_TGI6D(void) __attribute__ ((interrupt)); + +// TPU6_TCI6V + +void INT_Excep_TPU6_TCI6V(void) __attribute__ ((interrupt)); + +// vector 143 reserved +// vector 144 reserved + +// TPU7_TGI7A + +void INT_Excep_TPU7_TGI7A(void) __attribute__ ((interrupt)); + +// TPU7_TGI7B + +void INT_Excep_TPU7_TGI7B(void) __attribute__ ((interrupt)); + +// vector 147 reserved +// vector 148 reserved + +// TPU7_TCI7V + +void INT_Excep_TPU7_TCI7V(void) __attribute__ ((interrupt)); + +// TPU7_TCI7U + +void INT_Excep_TPU7_TCI7U(void) __attribute__ ((interrupt)); + +// TPU8_TGI8A + +void INT_Excep_TPU8_TGI8A(void) __attribute__ ((interrupt)); + +// TPU8_TGI8B + +void INT_Excep_TPU8_TGI8B(void) __attribute__ ((interrupt)); + +// vector 153 reserved + +// TPU8_TCI8V + +void INT_Excep_TPU8_TCI8V(void) __attribute__ ((interrupt)); + +// TPU8_TCI8U + +void INT_Excep_TPU8_TCI8U(void) __attribute__ ((interrupt)); + +// TPU9_TGI9A + +void INT_Excep_TPU9_TGI9A(void) __attribute__ ((interrupt)); + +// TPU9_TGI9B + +void INT_Excep_TPU9_TGI9B(void) __attribute__ ((interrupt)); + +// TPU9_TGI9C + +void INT_Excep_TPU9_TGI9C(void) __attribute__ ((interrupt)); + +// TPU9_TGI9D + +void INT_Excep_TPU9_TGI9D(void) __attribute__ ((interrupt)); + +// TPU9_TCI9V + +void INT_Excep_TPU9_TCI9V(void) __attribute__ ((interrupt)); + +// TPU10_TGI10A + +void INT_Excep_TPU10_TGI10A(void) __attribute__ ((interrupt)); + +// TPU10_TGI10B + +void INT_Excep_TPU10_TGI10B(void) __attribute__ ((interrupt)); + +// vector 163 reserved +// vector 164 reserved + +// TPU10_TCI10V + +void INT_Excep_TPU10_TCI10V(void) __attribute__ ((interrupt)); + +// TPU10_TCI10U + +void INT_Excep_TPU10_TCI10U(void) __attribute__ ((interrupt)); + +// TPU11_TGI11A + +void INT_Excep_TPU11_TGI11A(void) __attribute__ ((interrupt)); + +// TPU11_TGI11B + +void INT_Excep_TPU11_TGI11B(void) __attribute__ ((interrupt)); + +// vector 169 reserved + +// TPU11_TCI11V + +void INT_Excep_TPU11_TCI11V(void) __attribute__ ((interrupt)); + +// TPU11_TCI11U + +void INT_Excep_TPU11_TCI11U(void) __attribute__ ((interrupt)); + +// vector 172 reserved +// vector 173 reserved + +// TMR0_CMI0A + +void INT_Excep_TMR0_CMI0A(void) __attribute__ ((interrupt)); + +// TMR0_CMI0B + +void INT_Excep_TMR0_CMI0B(void) __attribute__ ((interrupt)); + +// TMR0_OV0I + +void INT_Excep_TMR0_OV0I(void) __attribute__ ((interrupt)); + +// TMR1_CMI1A + +void INT_Excep_TMR1_CMI1A(void) __attribute__ ((interrupt)); + +// TMR1_CMI1B + +void INT_Excep_TMR1_CMI1B(void) __attribute__ ((interrupt)); + +// TMR1_OV1I + +void INT_Excep_TMR1_OV1I(void) __attribute__ ((interrupt)); + +// TMR2_CMI2A + +void INT_Excep_TMR2_CMI2A(void) __attribute__ ((interrupt)); + +// TMR2_CMI2B + +void INT_Excep_TMR2_CMI2B(void) __attribute__ ((interrupt)); + +// TMR2_OV2I + +void INT_Excep_TMR2_OV2I(void) __attribute__ ((interrupt)); + +// TMR3_CMI3A + +void INT_Excep_TMR3_CMI3A(void) __attribute__ ((interrupt)); + +// TMR3_CMI3B + +void INT_Excep_TMR3_CMI3B(void) __attribute__ ((interrupt)); + +// TMR3_OV3I + +void INT_Excep_TMR3_OV3I(void) __attribute__ ((interrupt)); + +// vector 186 reserved +// vector 187 reserved +// vector 188 reserved +// vector 189 reserved +// vector 190 reserved +// vector 191 reserved +// vector 192 reserved +// vector 193 reserved +// vector 194 reserved +// vector 195 reserved +// vector 196 reserved +// vector 197 reserved + +// DMAC_DMTEND0 + +void INT_Excep_DMAC_DMTEND0(void); + +// DMAC_DMTEND1 + +void INT_Excep_DMAC_DMTEND1(void) __attribute__ ((interrupt)); + +// DMAC_DMTEND2 + +void INT_Excep_DMAC_DMTEND2(void) __attribute__ ((interrupt)); + +// DMAC_DMTEND3 + +void INT_Excep_DMAC_DMTEND3(void) __attribute__ ((interrupt)); + +// vector 202 reserved +// vector 203 reserved +// vector 204 reserved +// vector 205 reserved +// vector 206 reserved +// vector 207 reserved +// vector 208 reserved +// vector 209 reserved +// vector 210 reserved +// vector 211 reserved +// vector 212 reserved +// vector 213 reserved + +// SCI0_ERI0 + +void INT_Excep_SCI0_ERI0(void) __attribute__ ((interrupt)); + +// SCI0_RXI0 + +void INT_Excep_SCI0_RXI0(void) __attribute__ ((interrupt)); + +// SCI0_TXI0 + +void INT_Excep_SCI0_TXI0(void) __attribute__ ((interrupt)); + +// SCI0_TEI0 + +void INT_Excep_SCI0_TEI0(void) __attribute__ ((interrupt)); + +// SCI1_ERI1 + +void INT_Excep_SCI1_ERI1(void) __attribute__ ((interrupt)); + +// SCI1_RXI1 + +void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt)); + +// SCI1_TXI1 + +void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt)); + +// SCI1_TEI1 + +void INT_Excep_SCI1_TEI1(void) __attribute__ ((interrupt)); + +// SCI2_ERI2 + +void INT_Excep_SCI2_ERI2(void) __attribute__ ((interrupt)); + +// SCI2_RXI2 + +void INT_Excep_SCI2_RXI2(void) __attribute__ ((interrupt)); + +// SCI2_TXI2 + +void INT_Excep_SCI2_TXI2(void) __attribute__ ((interrupt)); + +// SCI2_TEI2 + +void INT_Excep_SCI2_TEI2(void) __attribute__ ((interrupt)); + +// SCI3_ERI3 + +void INT_Excep_SCI3_ERI3(void) __attribute__ ((interrupt)); + +// SCI3_RXI3 + +void INT_Excep_SCI3_RXI3(void) __attribute__ ((interrupt)); + +// SCI3_TXI3 + +void INT_Excep_SCI3_TXI3(void) __attribute__ ((interrupt)); + +// SCI3_TEI3 + +void INT_Excep_SCI3_TEI3(void) __attribute__ ((interrupt)); + +// SCI4_ERI4 + +void INT_Excep_SCI4_ERI4(void) __attribute__ ((interrupt)); + +// SCI4_RXI4 + +void INT_Excep_SCI4_RXI4(void) __attribute__ ((interrupt)); + +// SCI4_TXI4 + +void INT_Excep_SCI4_TXI4(void) __attribute__ ((interrupt)); + +// SCI4_TEI4 + +void INT_Excep_SCI4_TEI4(void) __attribute__ ((interrupt)); + +// SCI5_ERI5 + +void INT_Excep_SCI5_ERI5(void) __attribute__ ((interrupt)); + +// SCI5_RXI5 + +void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt)); + +// SCI5_TXI5 + +void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt)); + +// SCI5_TEI5 + +void INT_Excep_SCI5_TEI5(void) __attribute__ ((interrupt)); + +// SCI6_ERI6 + +void INT_Excep_SCI6_ERI6(void) __attribute__ ((interrupt)); + +// SCI6_RXI6 + +void INT_Excep_SCI6_RXI6(void) __attribute__ ((interrupt)); + +// SCI6_TXI6 + +void INT_Excep_SCI6_TXI6(void) __attribute__ ((interrupt)); + +// SCI6_TEI6 + +void INT_Excep_SCI6_TEI6(void) __attribute__ ((interrupt)); + +// vector 242 reserved +// vector 243 reserved +// vector 244 reserved +// vector 245 reserved + +// RIIC0_EEI0 + +void INT_Excep_RIIC0_EEI0(void) __attribute__ ((interrupt)); + +// RIIC0_RXI0 + +void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt)); + +// RIIC0_TXI0 + +void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt)); + +// RIIC0_TEI0 + +void INT_Excep_RIIC0_TEI0(void) __attribute__ ((interrupt)); + +// RIIC1_EEI1 + +void INT_Excep_RIIC1_EEI1(void) __attribute__ ((interrupt)); + +// RIIC1_RXI1 + +void INT_Excep_RIIC1_RXI1(void) __attribute__ ((interrupt)); + +// RIIC1_TXI1 + +void INT_Excep_RIIC1_TXI1(void) __attribute__ ((interrupt)); + +// RIIC1_TEI1 + +void INT_Excep_RIIC1_TEI1(void) __attribute__ ((interrupt)); + +// vector 254 reserved +// vector 255 reserved + +//;<> +//;Power On Reset PC +extern void PowerON_Reset_PC(void) __attribute__ ((interrupt)); +//;<> + +#endif \ No newline at end of file diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/iodefine.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/iodefine.h new file mode 100644 index 000000000..bdff17965 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/iodefine.h @@ -0,0 +1,14211 @@ +/********************************************************************************/ +/* */ +/* Summary : Definition of I/O Register. */ +/* Version : V1.1 (2010-04-21) [Hardware Manual Revision : 0.50] */ +/* File Name : iodefine.h for KPIT GNURX */ +/* Device : RX/RX600/RX62N */ +/* */ +/* Copyright(c) 2010 Renesas Electronics Corp. */ +/* And Renesas Solutions Corp. ,All Rights Reserved. */ +/* */ +/********************************************************************************/ +/* */ +/* CPU TYPE : RX62N */ +/* DESCRIPTION : Definition of ICU Register */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* for example : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(MTU1,TGIA1) = 2; expands to : */ +/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */ +/* ICU.IPR[0x53].BIT.IPR = 2; */ +/* */ +/* IPR(SCI0,ERI0) = 3; expands to : */ +/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */ +/* ICU.IPR[0x80].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* for example : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* for example : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTUA,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/********************************************************************************/ + +#ifndef IODEFINE_H +#define IODEFINE_H + +#ifdef __RX_LITTLE_ENDIAN__ /*Little endian*/ + +struct st_system { + union { + unsigned short WORD; + struct { + unsigned short MD0:1; + unsigned short MD1:1; + unsigned short :5; + unsigned short MDE:1; + unsigned short :8; + } BIT; + } MDMONR; + union { + unsigned short WORD; + struct { + unsigned short IROM:1; + unsigned short EXB:1; + unsigned short BSW:2; + unsigned short BOTS:1; + unsigned short :1; + unsigned short UBTS:1; + unsigned short :9; + } BIT; + } MDSR; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short ROME:1; + unsigned short EXBE:1; + unsigned short :6; + unsigned short KEY:8; + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + unsigned short RAME:1; + unsigned short :15; + } BIT; + } SYSCR1; + unsigned char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short STS:5; + unsigned short :1; + unsigned short OPE:1; + unsigned short SSBY:1; + } BIT; + } SBYCR; + unsigned char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long MSTPA4:1; + unsigned long MSTPA5:1; + unsigned long :2; + unsigned long MSTPA8:1; + unsigned long MSTPA9:1; + unsigned long MSTPA10:1; + unsigned long MSTPA11:1; + unsigned long :2; + unsigned long MSTPA14:1; + unsigned long MSTPA15:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long :1; + unsigned long MSTPA19:1; + unsigned long :2; + unsigned long MSTPA22:1; + unsigned long MSTPA23:1; + unsigned long :4; + unsigned long MSTPA28:1; + unsigned long MSTPA29:1; + unsigned long :1; + unsigned long ACSE:1; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB0:1; + unsigned long :14; + unsigned long MSTPB15:1; + unsigned long MSTPB16:1; + unsigned long MSTPB17:1; + unsigned long MSTPB18:1; + unsigned long MSTPB19:1; + unsigned long MSTPB20:1; + unsigned long MSTPB21:1; + unsigned long :1; + unsigned long MSTPB23:1; + unsigned long :1; + unsigned long MSTPB25:1; + unsigned long MSTPB26:1; + unsigned long :1; + unsigned long MSTPB28:1; + unsigned long MSTPB29:1; + unsigned long MSTPB30:1; + unsigned long MSTPB31:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long MSTPC0:1; + unsigned long MSTPC1:1; + unsigned long :30; + } BIT; + } MSTPCRC; + unsigned char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long PCK:4; + unsigned long :4; + unsigned long BCK:4; + unsigned long :2; + unsigned long PSTOP0:1; + unsigned long PSTOP1:1; + unsigned long ICK:4; + unsigned long :4; + } BIT; + } SCKCR; + unsigned char wk4[12]; + union { + unsigned char BYTE; + struct { + unsigned char BCLKDIV:1; + unsigned char :7; + } BIT; + } BCKCR; + unsigned char wk5[15]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short OSTDF:1; + unsigned short OSTDE:1; + unsigned short KEY:8; + } BIT; + } OSTDCR; + unsigned char wk6[49726]; + union { + unsigned char BYTE; + struct { + unsigned char RAMCUT0:1; + unsigned char :3; + unsigned char RAMCUT1:1; + unsigned char RAMCUT2:1; + unsigned char IOKEEP:1; + unsigned char DPSBY:1; + } BIT; + } DPSBYCR; + union { + unsigned char BYTE; + struct { + unsigned char WTSTS:6; + unsigned char :2; + } BIT; + } DPSWCR; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ0E:1; + unsigned char DIRQ1E:1; + unsigned char DIRQ2E:1; + unsigned char DIRQ3E:1; + unsigned char DLVDE:1; + unsigned char DRTCE:1; + unsigned char DUSBE:1; + unsigned char DNMIE:1; + } BIT; + } DPSIER; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ0F:1; + unsigned char DIRQ1F:1; + unsigned char DIRQ2F:1; + unsigned char DIRQ3F:1; + unsigned char DLVDF:1; + unsigned char DRTCFF:1; + unsigned char DUSBF:1; + unsigned char DNMIF:1; + } BIT; + } DPSIFR; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ0EG:1; + unsigned char DIRQ1EG:1; + unsigned char DIRQ2EG:1; + unsigned char DIRQ3EG:1; + unsigned char :3; + unsigned char DNMIEG:1; + } BIT; + } DPSIEGR; + union { + unsigned char BYTE; + struct { + unsigned char PORF:1; + unsigned char LVD1F:1; + unsigned char LVD2F:1; + unsigned char :4; + unsigned char DPSRSTF:1; + } BIT; + } RSTSR; + unsigned char wk7[4]; + union { + unsigned char BYTE; + struct { + unsigned char SUBSTOP:1; + unsigned char :7; + } BIT; + } SUBOSCCR; + unsigned char wk8[1]; + unsigned char LVDKEYR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD1RI:1; + unsigned char LVD1E:1; + unsigned char :2; + unsigned char LVD2RI:1; + unsigned char LVD2E:1; + } BIT; + } LVDCR; + unsigned char wk9[2]; + unsigned char DPSBKR[32]; +}; + +struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char STSCLR:1; + unsigned char :7; + } BIT; + } BERCLR; + unsigned char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char IGAEN:1; + unsigned char TOEN:1; + unsigned char :6; + } BIT; + } BEREN; + unsigned char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char IA:1; + unsigned char TO:1; + unsigned char :2; + unsigned char MST:3; + unsigned char :1; + } BIT; + } BERSR1; + unsigned char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short ADDR:13; + } BIT; + } BERSR2; + unsigned char wk3[7414]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS0WCR2; + unsigned char wk4[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS1WCR2; + unsigned char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS2WCR2; + unsigned char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS3WCR2; + unsigned char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS4WCR2; + unsigned char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS5WCR2; + unsigned char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS6WCR2; + unsigned char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS7WCR2; + unsigned char wk11[1926]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS0CR; + unsigned char wk12[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS0REC; + unsigned char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS1CR; + unsigned char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS1REC; + unsigned char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS2CR; + unsigned char wk16[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS2REC; + unsigned char wk17[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS3CR; + unsigned char wk18[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS3REC; + unsigned char wk19[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS4CR; + unsigned char wk20[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS4REC; + unsigned char wk21[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS5CR; + unsigned char wk22[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS5REC; + unsigned char wk23[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS6CR; + unsigned char wk24[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS6REC; + unsigned char wk25[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS7CR; + unsigned char wk26[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS7REC; + unsigned char wk27[900]; + union { + unsigned char BYTE; + struct { + unsigned char EXENB:1; + unsigned char :3; + unsigned char BSIZE:2; + unsigned char :2; + } BIT; + } SDCCR; + union { + unsigned char BYTE; + struct { + unsigned char EMODE:1; + unsigned char :7; + } BIT; + } SDCMOD; + union { + unsigned char BYTE; + struct { + unsigned char BE:1; + unsigned char :7; + } BIT; + } SDAMOD; + unsigned char wk28[13]; + union { + unsigned char BYTE; + struct { + unsigned char SFEN:1; + unsigned char :7; + } BIT; + } SDSELF; + unsigned char wk29[3]; + union { + unsigned short WORD; + struct { + unsigned short RFC:12; + unsigned short REFW:4; + } BIT; + } SDRFCR; + union { + unsigned char BYTE; + struct { + unsigned char RFEN:1; + unsigned char :7; + } BIT; + } SDRFEN; + unsigned char wk30[9]; + union { + unsigned char BYTE; + struct { + unsigned char INIRQ:1; + unsigned char :7; + } BIT; + } SDICR; + unsigned char wk31[3]; + union { + unsigned short WORD; + struct { + unsigned short ARFI:4; + unsigned short ARFC:4; + unsigned short PRC:3; + unsigned short :5; + } BIT; + } SDIR; + unsigned char wk32[26]; + union { + unsigned char BYTE; + struct { + unsigned char MXC:2; + unsigned char :6; + } BIT; + } SDADR; + unsigned char wk33[3]; + union { + unsigned long LONG; + struct { + unsigned long CL:3; + unsigned long :5; + unsigned long WR:1; + unsigned long RP:3; + unsigned long RCD:2; + unsigned long :2; + unsigned long RAS:3; + unsigned long :13; + } BIT; + } SDTR; + union { + unsigned short WORD; + struct { + unsigned short MR:15; + unsigned short :1; + } BIT; + } SDMOD; + unsigned char wk34[6]; + union { + unsigned char BYTE; + struct { + unsigned char MRSST:1; + unsigned char :2; + unsigned char INIST:1; + unsigned char SRFST:1; + unsigned char :3; + } BIT; + } SDSR; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short DCTG:2; + unsigned short :6; + unsigned short SZ:2; + unsigned short :2; + unsigned short DTS:2; + unsigned short MD:2; + } BIT; + } DMTMD; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char DARIE:1; + unsigned char SARIE:1; + unsigned char RPTIE:1; + unsigned char ESIE:1; + unsigned char DTIE:1; + unsigned char :3; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short DARA:5; + unsigned short :1; + unsigned short DM:2; + unsigned short SARA:5; + unsigned short :1; + unsigned short SM:2; + } BIT; + } DMAMD; + unsigned char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char DTE:1; + unsigned char :7; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char SWREQ:1; + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ESIF:1; + unsigned char :3; + unsigned char DTIF:1; + unsigned char :2; + unsigned char ACT:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char DISEL:1; + unsigned char :7; + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short DCTG:2; + unsigned short :6; + unsigned short SZ:2; + unsigned short :2; + unsigned short DTS:2; + unsigned short MD:2; + } BIT; + } DMTMD; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char DARIE:1; + unsigned char SARIE:1; + unsigned char RPTIE:1; + unsigned char ESIE:1; + unsigned char DTIE:1; + unsigned char :3; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short DARA:5; + unsigned short :1; + unsigned short DM:2; + unsigned short SARA:5; + unsigned short :1; + unsigned short SM:2; + } BIT; + } DMAMD; + unsigned char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char DTE:1; + unsigned char :7; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char SWREQ:1; + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ESIF:1; + unsigned char :3; + unsigned char DTIF:1; + unsigned char :2; + unsigned char ACT:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char DISEL:1; + unsigned char :7; + } BIT; + } DMCSL; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char DMST:1; + unsigned char :7; + } BIT; + } DMAST; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RRS:1; + unsigned char :3; + } BIT; + } DTCCR; + unsigned char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char SHORT:1; + unsigned char :7; + } BIT; + } DTCADMOD; + unsigned char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char DTCST:1; + unsigned char :7; + } BIT; + } DTCST; + unsigned char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short VECN:8; + unsigned short :7; + unsigned short ACT:1; + } BIT; + } DTCSTS; +}; + +struct st_exdmac0 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short DCTG:2; + unsigned short :6; + unsigned short SZ:2; + unsigned short :2; + unsigned short DTS:2; + unsigned short MD:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DACKW:1; + unsigned char DACKE:1; + unsigned char DACKS:1; + unsigned char :4; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char DARIE:1; + unsigned char SARIE:1; + unsigned char RPTIE:1; + unsigned char ESIE:1; + unsigned char DTIE:1; + unsigned char :3; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long DARA:5; + unsigned long :1; + unsigned long DM:2; + unsigned long SARA:5; + unsigned long :1; + unsigned long SM:2; + unsigned long DIR:1; + unsigned long AMS:1; + unsigned long :14; + } BIT; + } EDMAMD; + unsigned long EDMOFR; + union { + unsigned char BYTE; + struct { + unsigned char DTE:1; + unsigned char :7; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char SWREQ:1; + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ESIF:1; + unsigned char :3; + unsigned char DTIF:1; + unsigned char :2; + unsigned char ACT:1; + } BIT; + } EDMSTS; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char DREQS:2; + unsigned char :6; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char EREQ:1; + unsigned char :7; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char PREQ:1; + unsigned char :7; + } BIT; + } EDMPRF; +}; + +struct st_exdmac { + union { + unsigned char BYTE; + struct { + unsigned char DMST:1; + unsigned char :7; + } BIT; + } EDMAST; + unsigned char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char IR:1; + unsigned char :7; + } BIT; + } IR[254]; + unsigned char wk17[2]; + union { + unsigned char BYTE; + struct { + unsigned char DTCE:1; + unsigned char :7; + } BIT; + } DTCER[254]; + unsigned char wk47[2]; + union { + unsigned char BYTE; + struct { + unsigned char IEN0:1; + unsigned char IEN1:1; + unsigned char IEN2:1; + unsigned char IEN3:1; + unsigned char IEN4:1; + unsigned char IEN5:1; + unsigned char IEN6:1; + unsigned char IEN7:1; + } BIT; + } IER[32]; + unsigned char wk50[192]; + union { + unsigned char BYTE; + struct { + unsigned char SWINT:1; + unsigned char :7; + } BIT; + } SWINTR; + unsigned char wk51[15]; + union { + unsigned short WORD; + struct { + unsigned short FVCT:8; + unsigned short :7; + unsigned short FIEN:1; + } BIT; + } FIR; + unsigned char wk52[14]; + union { + unsigned char BYTE; + struct { + unsigned char IPR:4; + unsigned char :4; + } BIT; + } IPR[144]; + unsigned char wk67[112]; + unsigned char DMRSR0; + unsigned char wk68[3]; + unsigned char DMRSR1; + unsigned char wk69[3]; + unsigned char DMRSR2; + unsigned char wk70[3]; + unsigned char DMRSR3; + unsigned char wk71[243]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IRQMD:2; + unsigned char :4; + } BIT; + } IRQCR[16]; + unsigned char wk72[112]; + union { + unsigned char BYTE; + struct { + unsigned char NMIST:1; + unsigned char LVDST:1; + unsigned char OSTST:1; + unsigned char :5; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char NMIEN:1; + unsigned char LVDEN:1; + unsigned char OSTEN:1; + unsigned char :5; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char NMICLR:1; + unsigned char :1; + unsigned char OSTCLR:1; + unsigned char :5; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char NMIMD:1; + unsigned char :4; + } BIT; + } NMICR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short STR0:1; + unsigned short STR1:1; + unsigned short :14; + } BIT; + } CMSTR0; + unsigned char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short STR2:1; + unsigned short STR3:1; + unsigned short :14; + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short CKS:2; + unsigned short :4; + unsigned short CMIE:1; + unsigned short :9; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +union un_wdt { + struct { + union { + unsigned char BYTE; + struct { + unsigned char CKS:3; + unsigned char :2; + unsigned char TME:1; + unsigned char TMS:1; + unsigned char :1; + } BIT; + } TCSR; + unsigned char TCNT; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RSTE:1; + unsigned char WOVF:1; + } BIT; + } RSTCSR; + } READ; + struct { + unsigned short WINA; + unsigned short WINB; + } WRITE; +}; + +struct st_iwdt { + unsigned char IWDTRR; + unsigned char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short TOPS:2; + unsigned short :2; + unsigned short CKS:4; + unsigned short :8; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short CNTVAL:14; + unsigned short UNDFF:1; + unsigned short :1; + } BIT; + } IWDTSR; +}; + +struct st_ad { + unsigned short ADDRA; + unsigned short ADDRB; + unsigned short ADDRC; + unsigned short ADDRD; + unsigned char wk0[8]; + union { + unsigned char BYTE; + struct { + unsigned char CH:4; + unsigned char :1; + unsigned char ADST:1; + unsigned char ADIE:1; + unsigned char :1; + } BIT; + } ADCSR; + union { + unsigned char BYTE; + struct { + unsigned char MODE:2; + unsigned char CKS:2; + unsigned char :1; + unsigned char TRGS:3; + } BIT; + } ADCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DPSEL:1; + } BIT; + } ADDPR; + unsigned char ADSSTR; + unsigned char wk1[11]; + union { + unsigned char BYTE; + struct { + unsigned char DIAG:2; + unsigned char :6; + } BIT; + } ADDIAGR; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAE:1; + unsigned char DAOE0:1; + unsigned char DAOE1:1; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DPSEL:1; + } BIT; + } DADPR; +}; + +struct st_ppg0 { + union { + unsigned char BYTE; + struct { + unsigned char G0CMS:2; + unsigned char G1CMS:2; + unsigned char G2CMS:2; + unsigned char G3CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G0NOV:1; + unsigned char G1NOV:1; + unsigned char G2NOV:1; + unsigned char G3NOV:1; + unsigned char G0INV:1; + unsigned char G1INV:1; + unsigned char G2INV:1; + unsigned char G3INV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER8:1; + unsigned char NDER9:1; + unsigned char NDER10:1; + unsigned char NDER11:1; + unsigned char NDER12:1; + unsigned char NDER13:1; + unsigned char NDER14:1; + unsigned char NDER15:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER0:1; + unsigned char NDER1:1; + unsigned char NDER2:1; + unsigned char NDER3:1; + unsigned char NDER4:1; + unsigned char NDER5:1; + unsigned char NDER6:1; + unsigned char NDER7:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD8:1; + unsigned char POD9:1; + unsigned char POD10:1; + unsigned char POD11:1; + unsigned char POD12:1; + unsigned char POD13:1; + unsigned char POD14:1; + unsigned char POD15:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD0:1; + unsigned char POD1:1; + unsigned char POD2:1; + unsigned char POD3:1; + unsigned char POD4:1; + unsigned char POD5:1; + unsigned char POD6:1; + unsigned char POD7:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR8:1; + unsigned char NDR9:1; + unsigned char NDR10:1; + unsigned char NDR11:1; + unsigned char NDR12:1; + unsigned char NDR13:1; + unsigned char NDR14:1; + unsigned char NDR15:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR0:1; + unsigned char NDR1:1; + unsigned char NDR2:1; + unsigned char NDR3:1; + unsigned char NDR4:1; + unsigned char NDR5:1; + unsigned char NDR6:1; + unsigned char NDR7:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR8:1; + unsigned char NDR9:1; + unsigned char NDR10:1; + unsigned char NDR11:1; + unsigned char :4; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char NDR0:1; + unsigned char NDR1:1; + unsigned char NDR2:1; + unsigned char NDR3:1; + unsigned char :4; + } BIT; + } NDRL2; +}; + +struct st_ppg1 { + union { + unsigned char BYTE; + struct { + unsigned char PTRSL:1; + unsigned char :7; + } BIT; + } PTRSLR; + unsigned char wk0[5]; + union { + unsigned char BYTE; + struct { + unsigned char G0CMS:2; + unsigned char G1CMS:2; + unsigned char G2CMS:2; + unsigned char G3CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G0NOV:1; + unsigned char G1NOV:1; + unsigned char G2NOV:1; + unsigned char G3NOV:1; + unsigned char G0INV:1; + unsigned char G1INV:1; + unsigned char G2INV:1; + unsigned char G3INV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER24:1; + unsigned char NDER25:1; + unsigned char NDER26:1; + unsigned char NDER27:1; + unsigned char NDER28:1; + unsigned char NDER29:1; + unsigned char NDER30:1; + unsigned char NDER31:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER16:1; + unsigned char NDER17:1; + unsigned char NDER18:1; + unsigned char NDER19:1; + unsigned char NDER20:1; + unsigned char NDER21:1; + unsigned char NDER22:1; + unsigned char NDER23:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD24:1; + unsigned char POD25:1; + unsigned char POD26:1; + unsigned char POD27:1; + unsigned char POD28:1; + unsigned char POD29:1; + unsigned char POD30:1; + unsigned char POD31:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD16:1; + unsigned char POD17:1; + unsigned char POD18:1; + unsigned char POD19:1; + unsigned char POD20:1; + unsigned char POD21:1; + unsigned char POD22:1; + unsigned char POD23:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR24:1; + unsigned char NDR25:1; + unsigned char NDR26:1; + unsigned char NDR27:1; + unsigned char NDR28:1; + unsigned char NDR29:1; + unsigned char NDR30:1; + unsigned char NDR31:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR16:1; + unsigned char NDR17:1; + unsigned char NDR18:1; + unsigned char NDR19:1; + unsigned char NDR20:1; + unsigned char NDR21:1; + unsigned char NDR22:1; + unsigned char NDR23:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR24:1; + unsigned char NDR25:1; + unsigned char NDR26:1; + unsigned char NDR27:1; + unsigned char :4; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char NDR16:1; + unsigned char NDR17:1; + unsigned char NDR18:1; + unsigned char NDR19:1; + unsigned char :4; + } BIT; + } NDRL2; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CCLR:2; + unsigned char OVIE:1; + unsigned char CMIEA:1; + unsigned char CMIEB:1; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char OSA:2; + unsigned char OSB:2; + unsigned char ADTE:1; + unsigned char :3; + } BIT; + } TCSR; + unsigned char wk1[1]; + unsigned char TCORA; + unsigned char wk2[1]; + unsigned char TCORB; + unsigned char wk3[1]; + unsigned char TCNT; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char CKS:3; + unsigned char CSS:2; + unsigned char :2; + unsigned char TMRIS:1; + } BIT; + } TCCR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CCLR:2; + unsigned char OVIE:1; + unsigned char CMIEA:1; + unsigned char CMIEB:1; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char OSA:2; + unsigned char OSB:2; + unsigned char :4; + } BIT; + } TCSR; + unsigned char wk1[1]; + unsigned char TCORA; + unsigned char wk2[1]; + unsigned char TCORB; + unsigned char wk3[1]; + unsigned char TCNT; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char CKS:3; + unsigned char CSS:2; + unsigned char :2; + unsigned char TMRIS:1; + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_sci { + union { + unsigned char BYTE; + struct { + unsigned char CKS:2; + unsigned char MP:1; + unsigned char STOP:1; + unsigned char PM:1; + unsigned char PE:1; + unsigned char CHR:1; + unsigned char CM:1; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char CKE:2; + unsigned char TEIE:1; + unsigned char MPIE:1; + unsigned char RE:1; + unsigned char TE:1; + unsigned char RIE:1; + unsigned char TIE:1; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char MPBT:1; + unsigned char MPB:1; + unsigned char TEND:1; + unsigned char PER:1; + unsigned char FER:1; + unsigned char ORER:1; + unsigned char :2; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char SMIF:1; + unsigned char :1; + unsigned char SINV:1; + unsigned char SDIR:1; + unsigned char :4; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char ACS0:1; + unsigned char :3; + unsigned char ABCS:1; + unsigned char :3; + } BIT; + } SEMR; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + unsigned char CKS:2; + unsigned char BCP:2; + unsigned char PM:1; + unsigned char PE:1; + unsigned char BLK:1; + unsigned char GM:1; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char CKE:2; + unsigned char TEIE:1; + unsigned char :1; + unsigned char RE:1; + unsigned char TE:1; + unsigned char RIE:1; + unsigned char TIE:1; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char TEND:1; + unsigned char PER:1; + unsigned char ERS:1; + unsigned char ORER:1; + unsigned char :2; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char SMIF:1; + unsigned char :1; + unsigned char SINV:1; + unsigned char SDIR:1; + unsigned char :3; + unsigned char BCP2:1; + } BIT; + } SCMR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char GPS:2; + unsigned char LMS:1; + unsigned char :4; + unsigned char DORCLR:1; + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char SDAI:1; + unsigned char SCLI:1; + unsigned char SDAO:1; + unsigned char SCLO:1; + unsigned char SOWP:1; + unsigned char CLO:1; + unsigned char IICRST:1; + unsigned char ICE:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ST:1; + unsigned char RS:1; + unsigned char SP:1; + unsigned char :1; + unsigned char TRS:1; + unsigned char MST:1; + unsigned char BBSY:1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char BC:3; + unsigned char BCWP:1; + unsigned char CKS:3; + unsigned char MTWP:1; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char TMOS:1; + unsigned char TMOL:1; + unsigned char TMOH:1; + unsigned char :1; + unsigned char SDDL:3; + unsigned char DLCS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char NF:2; + unsigned char ACKBR:1; + unsigned char ACKBT:1; + unsigned char ACKWP:1; + unsigned char RDRFS:1; + unsigned char WAIT:1; + unsigned char SMBS:1; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char TMOE:1; + unsigned char MALE:1; + unsigned char NALE:1; + unsigned char SALE:1; + unsigned char NACKE:1; + unsigned char NFE:1; + unsigned char SCLE:1; + unsigned char FMPE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char SAR0E:1; + unsigned char SAR1E:1; + unsigned char SAR2E:1; + unsigned char GCAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char HOAE:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TMOIE:1; + unsigned char ALIE:1; + unsigned char STIE:1; + unsigned char SPIE:1; + unsigned char NAKIE:1; + unsigned char RIE:1; + unsigned char TEIE:1; + unsigned char TIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char AAS0:1; + unsigned char AAS1:1; + unsigned char AAS2:1; + unsigned char GCA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char HOA:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TMOF:1; + unsigned char AL:1; + unsigned char START:1; + unsigned char STOP:1; + unsigned char NACKF:1; + unsigned char RDRF:1; + unsigned char TEND:1; + unsigned char TDRE:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA0:1; + unsigned char SVA:7; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char FS:1; + unsigned char SVA:2; + unsigned char :5; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA0:1; + unsigned char SVA:7; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char FS:1; + unsigned char SVA:2; + unsigned char :5; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA0:1; + unsigned char SVA:7; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char FS:1; + unsigned char SVA:2; + unsigned char :5; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char BRL:5; + unsigned char :3; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char BRH:5; + unsigned char :3; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPMS:1; + unsigned char TXMD:1; + unsigned char MODFEN:1; + unsigned char MSTR:1; + unsigned char SPEIE:1; + unsigned char SPTIE:1; + unsigned char SPE:1; + unsigned char SPRIE:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char SSLP0:1; + unsigned char SSLP1:1; + unsigned char SSLP2:1; + unsigned char SSLP3:1; + unsigned char :4; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char SPLP:1; + unsigned char SPLP2:1; + unsigned char SPOM:1; + unsigned char :1; + unsigned char MOIFV:1; + unsigned char MOIFE:1; + unsigned char :2; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char OVRF:1; + unsigned char IDLNF:1; + unsigned char MODF:1; + unsigned char PERF:1; + unsigned char :4; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char SPSLN:3; + unsigned char :5; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char SPCP:3; + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + unsigned char SPR0:1; + unsigned char SPR1:1; + unsigned char SPR2:1; + unsigned char SPR3:1; + unsigned char SPR4:1; + unsigned char SPR5:1; + unsigned char SPR6:1; + unsigned char SPR7:1; + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + unsigned char SPFC:2; + unsigned char SLSEL:2; + unsigned char SPRDTD:1; + unsigned char SPLW:1; + unsigned char :2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char SCKDL:3; + unsigned char :5; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char SLNDL:3; + unsigned char :5; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char SPNDL:3; + unsigned char :5; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char SPPE:1; + unsigned char SPOE:1; + unsigned char SPIIE:1; + unsigned char PTE:1; + unsigned char :4; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD7; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char OE3B:1; + unsigned char OE4A:1; + unsigned char OE4B:1; + unsigned char OE3D:1; + unsigned char OE4C:1; + unsigned char OE4D:1; + unsigned char :2; + } BIT; + } TOER; + unsigned char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char UF:1; + unsigned char VF:1; + unsigned char WF:1; + unsigned char FB:1; + unsigned char P:1; + unsigned char N:1; + unsigned char BCD:1; + unsigned char :1; + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + unsigned char OLSP:1; + unsigned char OLSN:1; + unsigned char TOCS:1; + unsigned char TOCL:1; + unsigned char :2; + unsigned char PSYE:1; + unsigned char :1; + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char BF:2; + } BIT; + } TOCR2; + unsigned char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + unsigned char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + unsigned char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T4VCOR:3; + unsigned char T4VEN:1; + unsigned char T3ACOR:3; + unsigned char T3AEN:1; + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + unsigned char T4VCNT:3; + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + unsigned char BTE:2; + unsigned char :6; + } BIT; + } TBTER; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char :7; + } BIT; + } TDER; + unsigned char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char :2; + } BIT; + } TOLBR; + unsigned char wk6[41]; + union { + unsigned char BYTE; + struct { + unsigned char WRE:1; + unsigned char :6; + unsigned char CCE:1; + } BIT; + } TWCR; + unsigned char wk7[31]; + union { + unsigned char BYTE; + struct { + unsigned char CST0:1; + unsigned char CST1:1; + unsigned char CST2:1; + unsigned char :3; + unsigned char CST3:1; + unsigned char CST4:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char SYNC0:1; + unsigned char SYNC1:1; + unsigned char SYNC2:1; + unsigned char :3; + unsigned char SYNC3:1; + unsigned char SYNC4:1; + } BIT; + } TSYR; + unsigned char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char RWE:1; + unsigned char :7; + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char BFE:1; + unsigned char :1; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TTGE:1; + } BIT; + } TIER; + unsigned char TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + unsigned char wk0[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char TGIEE:1; + unsigned char TGIEF:1; + unsigned char :6; + } BIT; + } TIER2; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char TTSE:1; + unsigned char :5; + } BIT; + } TBTM; +}; + +struct st_mtu1 { + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char :4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char I1AE:1; + unsigned char I1BE:1; + unsigned char I2AE:1; + unsigned char I2BE:1; + unsigned char :4; + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char :4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char BFE:1; + unsigned char :1; + } BIT; + } TMDR; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + unsigned char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char TTGE2:1; + unsigned char TTGE:1; + } BIT; + } TIER; + unsigned char wk3[7]; + unsigned short TCNT; + unsigned char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + unsigned char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + unsigned char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char TTSE:1; + unsigned char :5; + } BIT; + } TBTM; +}; + +struct st_mtu4 { + unsigned char DMMY; + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char BFE:1; + unsigned char :1; + } BIT; + } TMDR; + unsigned char wk1[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + unsigned char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char TTGE2:1; + unsigned char TTGE:1; + } BIT; + } TIER; + unsigned char wk3[8]; + unsigned short TCNT; + unsigned char wk4[8]; + unsigned short TGRA; + unsigned short TGRB; + unsigned char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + unsigned char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char TTSE:1; + unsigned char :5; + } BIT; + } TBTM; + unsigned char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short ITB4VE:1; + unsigned short ITB3AE:1; + unsigned short ITA4VE:1; + unsigned short ITA3AE:1; + unsigned short DT4BE:1; + unsigned short UT4BE:1; + unsigned short DT4AE:1; + unsigned short UT4AE:1; + unsigned short :6; + unsigned short BF:2; + } BIT; + } TADCR; + unsigned char wk9[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; +}; + +struct st_mtu5 { + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCRU; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORU; + unsigned char wk1[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCRV; + union { + unsigned char BYTE; + struct { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORV; + unsigned char wk2[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCRW; + unsigned char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORW; + unsigned char wk4[11]; + union { + unsigned char BYTE; + struct { + unsigned char TGIE5W:1; + unsigned char TGIE5V:1; + unsigned char TGIE5U:1; + unsigned char :5; + } BIT; + } TIER; + unsigned char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char CSTW5:1; + unsigned char CSTV5:1; + unsigned char CSTU5:1; + unsigned char :5; + } BIT; + } TSTR; + unsigned char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char CMPCLR5W:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5U:1; + unsigned char :5; + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned short POE0M:2; + unsigned short POE1M:2; + unsigned short POE2M:2; + unsigned short POE3M:2; + unsigned short PIE1:1; + unsigned short :3; + unsigned short POE0F:1; + unsigned short POE1F:1; + unsigned short POE2F:1; + unsigned short POE3F:1; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short OIE1:1; + unsigned short OCE1:1; + unsigned short :5; + unsigned short OSF1:1; + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + unsigned short POE4M:2; + unsigned short POE5M:2; + unsigned short POE6M:2; + unsigned short POE7M:2; + unsigned short PIE2:1; + unsigned short :3; + unsigned short POE4F:1; + unsigned short POE5F:1; + unsigned short POE6F:1; + unsigned short POE7F:1; + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short OIE2:1; + unsigned short OCE2:1; + unsigned short :5; + unsigned short OSF2:1; + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + unsigned short POE8M:2; + unsigned short :6; + unsigned short PIE3:1; + unsigned short POE8E:1; + unsigned short :2; + unsigned short POE8F:1; + unsigned short :3; + } BIT; + } ICSR3; + union { + unsigned char BYTE; + struct { + unsigned char CH34HIZ:1; + unsigned char CH0HIZ:1; + unsigned char CH910HIZ:1; + unsigned char CH6HIZ:1; + unsigned char :4; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char PE0ZE:1; + unsigned char PE1ZE:1; + unsigned char PE2ZE:1; + unsigned char PE3ZE:1; + unsigned char PE4ZE:1; + unsigned char PE5ZE:1; + unsigned char PE6ZE:1; + unsigned char PE7ZE:1; + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short P6CZE:1; + unsigned short P5CZE:1; + unsigned short P4CZE:1; + unsigned short :1; + unsigned short P3CZEB:1; + unsigned short P2CZEB:1; + unsigned short P1CZEB:1; + unsigned short :1; + unsigned short P3CZEA:1; + unsigned short P2CZEA:1; + unsigned short P1CZEA:1; + unsigned short :1; + } BIT; + } POECR2; + union { + unsigned short WORD; + struct { + unsigned short POE9M:2; + unsigned short :6; + unsigned short PIE4:1; + unsigned short POE9E:1; + unsigned short :2; + unsigned short POE9F:1; + unsigned short :3; + } BIT; + } ICSR4; +}; + +struct st_s12ad { + union { + unsigned char BYTE; + struct { + unsigned char EXTRG:1; + unsigned char TRGE:1; + unsigned char CKS:2; + unsigned char ADIE:1; + unsigned char :1; + unsigned char ADCS:1; + unsigned char ADST:1; + } BIT; + } ADCSR; + unsigned char wk0[3]; + union { + unsigned short WORD; + struct { + unsigned short ANS:8; + unsigned short :8; + } BIT; + } ADANS; + unsigned char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short ADS:8; + unsigned short :8; + } BIT; + } ADADS; + unsigned char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char ADC:2; + unsigned char :6; + } BIT; + } ADADC; + unsigned char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short ACE:1; + unsigned short :9; + unsigned short ADRFMT:1; + } BIT; + } ADCER; + union { + unsigned char BYTE; + struct { + unsigned char ADSTRS:4; + unsigned char :4; + } BIT; + } ADSTRGR; + unsigned char wk4[15]; + unsigned short ADDRA; + unsigned short ADDRB; + unsigned short ADDRC; + unsigned short ADDRD; + unsigned short ADDRE; + unsigned short ADDRF; + unsigned short ADDRG; + unsigned short ADDRH; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B7:1; + } BIT; + } ODR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ODR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ODR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } ODR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; +}; + +struct st_port6 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; +}; + +struct st_port7 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; +}; + +struct st_port8 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } ICR; +}; + +struct st_port9 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ODR; + unsigned char wk4[63]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_portf { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } ICR; +}; + +struct st_portg { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_ioport { + union { + unsigned char BYTE; + struct { + unsigned char CS0E:1; + unsigned char CS1E:1; + unsigned char CS2E:1; + unsigned char CS3E:1; + unsigned char CS4E:1; + unsigned char CS5E:1; + unsigned char CS6E:1; + unsigned char CS7E:1; + } BIT; + } PF0CSE; + union { + unsigned char BYTE; + struct { + unsigned char CS4S:2; + unsigned char CS5S:2; + unsigned char CS6S:2; + unsigned char CS7S:2; + } BIT; + } PF1CSS; + union { + unsigned char BYTE; + struct { + unsigned char CS0S:1; + unsigned char :1; + unsigned char CS1S:2; + unsigned char CS2S:2; + unsigned char CS3S:2; + } BIT; + } PF2CSS; + union { + unsigned char BYTE; + struct { + unsigned char A16E:1; + unsigned char A17E:1; + unsigned char A18E:1; + unsigned char A19E:1; + unsigned char A20E:1; + unsigned char A21E:1; + unsigned char A22E:1; + unsigned char A23E:1; + } BIT; + } PF3BUS; + union { + unsigned char BYTE; + struct { + unsigned char ADRLE:2; + unsigned char A10E:1; + unsigned char A11E:1; + unsigned char A12E:1; + unsigned char A13E:1; + unsigned char A14E:1; + unsigned char A15E:1; + } BIT; + } PF4BUS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ADRHMS:1; + unsigned char :2; + unsigned char DHE:1; + unsigned char DH32E:1; + unsigned char WR1BC1E:1; + unsigned char WR32BC32E:1; + } BIT; + } PF5BUS; + union { + unsigned char BYTE; + struct { + unsigned char WAITS:2; + unsigned char :2; + unsigned char MDSDE:1; + unsigned char :1; + unsigned char DQM1E:1; + unsigned char SDCLKE:1; + } BIT; + } PF6BUS; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char EDMA0S:2; + unsigned char EDMA1S:2; + } BIT; + } PF7DMA; + union { + unsigned char BYTE; + struct { + unsigned char ITS8:1; + unsigned char ITS9:1; + unsigned char ITS10:1; + unsigned char ITS11:1; + unsigned char :1; + unsigned char ITS13:1; + unsigned char :1; + unsigned char ITS15:1; + } BIT; + } PF8IRQ; + union { + unsigned char BYTE; + struct { + unsigned char ITS0:1; + unsigned char ITS1:1; + unsigned char ITS2:1; + unsigned char ITS3:1; + unsigned char ITS4:1; + unsigned char ITS5:1; + unsigned char ITS6:1; + unsigned char ITS7:1; + } BIT; + } PF9IRQ; + union { + unsigned char BYTE; + struct { + unsigned char ADTRG0S:1; + unsigned char :7; + } BIT; + } PFAADC; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char TMR2S:1; + unsigned char TMR3S:1; + unsigned char :4; + } BIT; + } PFBTMR; + union { + unsigned char BYTE; + struct { + unsigned char MTUS0:1; + unsigned char MTUS1:1; + unsigned char MTUS2:1; + unsigned char MTUS3:1; + unsigned char MTUS4:1; + unsigned char MTUS5:1; + unsigned char MTUS6:1; + unsigned char TCLKS:1; + } BIT; + } PFCMTU; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MTUS6:1; + unsigned char TCLKS:1; + } BIT; + } PFDMTU; + union { + unsigned char BYTE; + struct { + unsigned char ENETE0:1; + unsigned char ENETE1:1; + unsigned char ENETE2:1; + unsigned char ENETE3:1; + unsigned char PHYMODE:1; + unsigned char :2; + unsigned char EE:1; + } BIT; + } PFENET; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SCI1S:1; + unsigned char SCI2S:1; + unsigned char SCI3S:1; + unsigned char :2; + unsigned char SCI6S:1; + unsigned char :1; + } BIT; + } PFFSCI; + union { + unsigned char BYTE; + struct { + unsigned char RSPIS:1; + unsigned char RSPCKE:1; + unsigned char MOSIE:1; + unsigned char MISOE:1; + unsigned char SSL0E:1; + unsigned char SSL1E:1; + unsigned char SSL2E:1; + unsigned char SSL3E:1; + } BIT; + } PFGSPI; + union { + unsigned char BYTE; + struct { + unsigned char RSPIS:1; + unsigned char RSPCKE:1; + unsigned char MOSIE:1; + unsigned char MISOE:1; + unsigned char SSL0E:1; + unsigned char SSL1E:1; + unsigned char SSL2E:1; + unsigned char SSL3E:1; + } BIT; + } PFHSPI; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CAN0E:1; + unsigned char :7; + } BIT; + } PFJCAN; + union { + unsigned char BYTE; + struct { + unsigned char USBMD:2; + unsigned char PUPHZS:1; + unsigned char PDHZS:1; + unsigned char USBE:1; + unsigned char :3; + } BIT; + } PFKUSB; + union { + unsigned char BYTE; + struct { + unsigned char USBMD:2; + unsigned char PUPHZS:1; + unsigned char PDHZS:1; + unsigned char USBE:1; + unsigned char :3; + } BIT; + } PFLUSB; + union { + unsigned char BYTE; + struct { + unsigned char POE0E:1; + unsigned char POE1E:1; + unsigned char POE2E:1; + unsigned char POE3E:1; + unsigned char POE4E:1; + unsigned char POE5E:1; + unsigned char POE6E:1; + unsigned char POE7E:1; + } BIT; + } PFMPOE; + union { + unsigned char BYTE; + struct { + unsigned char POE8E:1; + unsigned char POE9E:1; + unsigned char :6; + } BIT; + } PFNPOE; +}; + +struct st_flash { + unsigned char DMMY; + union { + unsigned char BYTE; + struct { + unsigned char FLWE:2; + unsigned char :6; + } BIT; + } FWEPROR; + unsigned char wk0[7799160]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char FRDMD:1; + unsigned char :3; + } BIT; + } FMODR; + unsigned char wk1[13]; + union { + unsigned char BYTE; + struct { + unsigned char DFLWPE:1; + unsigned char DFLRPE:1; + unsigned char :1; + unsigned char DFLAE:1; + unsigned char CMDLK:1; + unsigned char :2; + unsigned char ROMAE:1; + } BIT; + } FASTAT; + union { + unsigned char BYTE; + struct { + unsigned char DFLWPEIE:1; + unsigned char DFLRPEIE:1; + unsigned char :1; + unsigned char DFLAEIE:1; + unsigned char CMDLKIE:1; + unsigned char :2; + unsigned char ROMAEIE:1; + } BIT; + } FAEINT; + union { + unsigned char BYTE; + struct { + unsigned char FRDYIE:1; + unsigned char :7; + } BIT; + } FRDYIE; + unsigned char wk2[45]; + union { + unsigned short WORD; + struct { + unsigned short DBRE00:1; + unsigned short DBRE01:1; + unsigned short DBRE02:1; + unsigned short DBRE03:1; + unsigned short DBRE04:1; + unsigned short DBRE05:1; + unsigned short DBRE06:1; + unsigned short DBRE07:1; + unsigned short KEY:8; + } BIT; + } DFLRE0; + union { + unsigned short WORD; + struct { + unsigned short DBRE08:1; + unsigned short DBRE09:1; + unsigned short DBRE10:1; + unsigned short DBRE11:1; + unsigned short DBRE12:1; + unsigned short DBRE13:1; + unsigned short DBRE14:1; + unsigned short DBRE15:1; + unsigned short KEY:8; + } BIT; + } DFLRE1; + unsigned char wk3[12]; + union { + unsigned short WORD; + struct { + unsigned short DBWE00:1; + unsigned short DBWE01:1; + unsigned short DBWE02:1; + unsigned short DBWE03:1; + unsigned short DBWE04:1; + unsigned short DBWE05:1; + unsigned short DBWE06:1; + unsigned short DBWE07:1; + unsigned short KEY:8; + } BIT; + } DFLWE0; + union { + unsigned short WORD; + struct { + unsigned short DBWE08:1; + unsigned short DBWE09:1; + unsigned short DBWE10:1; + unsigned short DBWE11:1; + unsigned short DBWE12:1; + unsigned short DBWE13:1; + unsigned short DBWE14:1; + unsigned short DBWE15:1; + unsigned short KEY:8; + } BIT; + } DFLWE1; + union { + unsigned short WORD; + struct { + unsigned short FCRME:1; + unsigned short :7; + unsigned short KEY:8; + } BIT; + } FCURAME; + unsigned char wk4[15194]; + union { + unsigned char BYTE; + struct { + unsigned char PRGSPD:1; + unsigned char ERSSPD:1; + unsigned char :1; + unsigned char SUSRDY:1; + unsigned char PRGERR:1; + unsigned char ERSERR:1; + unsigned char ILGLERR:1; + unsigned char FRDY:1; + } BIT; + } FSTATR0; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char FLOCKST:1; + unsigned char :2; + unsigned char FCUERR:1; + } BIT; + } FSTATR1; + union { + unsigned short WORD; + struct { + unsigned short FENTRY0:1; + unsigned short :6; + unsigned short FENTRYD:1; + unsigned short FEKEY:8; + } BIT; + } FENTRYR; + union { + unsigned short WORD; + struct { + unsigned short FPROTCN:1; + unsigned short :7; + unsigned short FPKEY:8; + } BIT; + } FPROTR; + union { + unsigned short WORD; + struct { + unsigned short FRESET:1; + unsigned short :7; + unsigned short FPKEY:8; + } BIT; + } FRESETR; + unsigned char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short PCMDR:8; + unsigned short CMDR:8; + } BIT; + } FCMDR; + unsigned char wk6[12]; + union { + unsigned short WORD; + struct { + unsigned short ESUSPMD:1; + unsigned short :15; + } BIT; + } FCPSR; + union { + unsigned short WORD; + struct { + unsigned short BCSIZE:1; + unsigned short :2; + unsigned short BCADR:8; + unsigned short :5; + } BIT; + } DFLBCCNT; + union { + unsigned short WORD; + struct { + unsigned short PEERRST:8; + unsigned short :8; + } BIT; + } FPESTAT; + union { + unsigned short WORD; + struct { + unsigned short BCST:1; + unsigned short :15; + } BIT; + } DFLBCSTAT; + unsigned char wk7[24]; + union { + unsigned short WORD; + struct { + unsigned short PCKA:8; + unsigned short :8; + } BIT; + } PCKAR; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char F1HZ:1; + unsigned char F2HZ:1; + unsigned char F4HZ:1; + unsigned char F8HZ:1; + unsigned char F16HZ:1; + unsigned char F32HZ:1; + unsigned char F64HZ:1; + } BIT; + } R64CNT; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char SEC1:4; + unsigned char SEC10:3; + unsigned char :1; + } BIT; + } RSECCNT; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char MIN1:4; + unsigned char MIN10:3; + unsigned char :1; + } BIT; + } RMINCNT; + unsigned char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char HOUR1:4; + unsigned char HOUR10:2; + unsigned char :2; + } BIT; + } RHRCNT; + unsigned char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAY:3; + unsigned char :5; + } BIT; + } RWKCNT; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAY1:4; + unsigned char DAY10:2; + unsigned char :2; + } BIT; + } RDAYCNT; + unsigned char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char MON1:4; + unsigned char MON10:1; + unsigned char :3; + } BIT; + } RMONCNT; + unsigned char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short YEAR1:4; + unsigned short YEAR10:4; + unsigned short YEAR100:4; + unsigned short YEAR1000:4; + } BIT; + } RYRCNT; + union { + unsigned char BYTE; + struct { + unsigned char SEC1:4; + unsigned char SEC10:3; + unsigned char ENB:1; + } BIT; + } RSECAR; + unsigned char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char MIN1:4; + unsigned char MIN10:3; + unsigned char ENB:1; + } BIT; + } RMINAR; + unsigned char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char HOUR1:4; + unsigned char HOUR10:2; + unsigned char :1; + unsigned char ENB:1; + } BIT; + } RHRAR; + unsigned char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAY:3; + unsigned char :4; + unsigned char ENB:1; + } BIT; + } RWKAR; + unsigned char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAY1:4; + unsigned char DAY10:2; + unsigned char :1; + unsigned char ENB:1; + } BIT; + } RDAYAR; + unsigned char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char MON1:4; + unsigned char MON10:1; + unsigned char :2; + unsigned char ENB:1; + } BIT; + } RMONAR; + unsigned char wk12[1]; + union { + unsigned short WORD; + struct { + unsigned short YEAR1:4; + unsigned short YEAR10:4; + unsigned short YEAR100:4; + unsigned short YEAR1000:4; + } BIT; + } RYRAR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ENB:1; + } BIT; + } RYRAREN; + unsigned char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char AIE:1; + unsigned char CIE:1; + unsigned char PIE:1; + unsigned char :1; + unsigned char PES:3; + unsigned char :1; + } BIT; + } RCR1; + unsigned char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char START:1; + unsigned char RESET:1; + unsigned char ADJ:1; + unsigned char RTCOE:1; + unsigned char :4; + } BIT; + } RCR2; +}; + +struct st_can { + struct { + union { + unsigned long LONG; + union { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long EID:18; + unsigned long SID:11; + unsigned long :1; + unsigned long RTR:1; + unsigned long IDE:1; + } BIT; + } ID; + union { + unsigned short WORD; + struct { + unsigned char DLC:4; + unsigned char :4; + unsigned char :8; + } BIT; + } DLC; + unsigned char DATA[8]; + union{ + unsigned short WORD; + struct { + unsigned char TSH; + unsigned char TSL; + } BYTE; + } TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long EID:18; + unsigned long SID:11; + unsigned long :3; + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long EID:18; + unsigned long SID:11; + unsigned long :1; + unsigned long RTR:1; + unsigned long IDE:1; + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long EID:18; + unsigned long SID:11; + unsigned long :1; + unsigned long RTR:1; + unsigned long IDE:1; + } BIT; + } FIDCR1; + unsigned long MKIVLR; + unsigned long MIER; + unsigned char wk32[1008]; + union { + unsigned char BYTE; + union { + struct { + unsigned char SENTDATA:1; + unsigned char TRMACTIVE:1; + unsigned char TRMABT:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char RECREQ:1; + unsigned char TRMREQ:1; + } TX; + struct { + unsigned char NEWDATA:1; + unsigned char INVALDATA:1; + unsigned char MSGLOST:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char RECREQ:1; + unsigned char TRMREQ:1; + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char MBM:1; + unsigned char IDFM:2; + unsigned char MLM:1; + unsigned char TPM:1; + unsigned char TSRC:1; + unsigned char TSPS:2; + unsigned char CANM:2; + unsigned char SLPM:1; + unsigned char BOM:2; + unsigned char RBOC:1; + unsigned char :2; + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char NDST:1; + unsigned char SDST:1; + unsigned char RFST:1; + unsigned char TFST:1; + unsigned char NMLST:1; + unsigned char FMLST:1; + unsigned char TABST:1; + unsigned char EST:1; + unsigned char RSTST:1; + unsigned char HLTST:1; + unsigned char SLPST:1; + unsigned char EPST:1; + unsigned char BOST:1; + unsigned char TRMST:1; + unsigned char RECST:1; + unsigned char :1; + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long :8; + unsigned long TSEG2:3; + unsigned long :1; + unsigned long SJW:2; + unsigned long :2; + unsigned long BRP:10; + unsigned long :2; + unsigned long TSEG1:4; + } BIT; + } BCR; + union { + unsigned char BYTE; + struct { + unsigned char RFE:1; + unsigned char RFUST:3; + unsigned char RFMLF:1; + unsigned char RFFST:1; + unsigned char RFWST:1; + unsigned char RFEST:1; + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + unsigned char TFE:1; + unsigned char TFUST:3; + unsigned char :2; + unsigned char TFFST:1; + unsigned char TFEST:1; + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + unsigned char BEIE:1; + unsigned char EWIE:1; + unsigned char EPIE:1; + unsigned char BOEIE:1; + unsigned char BORIE:1; + unsigned char ORIE:1; + unsigned char OLIE:1; + unsigned char BLIE:1; + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + unsigned char BEIF:1; + unsigned char EWIF:1; + unsigned char EPIF:1; + unsigned char BOEIF:1; + unsigned char BORIF:1; + unsigned char ORIF:1; + unsigned char OLIF:1; + unsigned char BLIF:1; + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + unsigned char SEF:1; + unsigned char FEF:1; + unsigned char AEF:1; + unsigned char CEF:1; + unsigned char BE1F:1; + unsigned char BE0F:1; + unsigned char ADEF:1; + unsigned char EDPM:1; + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + unsigned char MBNST:5; + unsigned char :2; + unsigned char SEST:1; + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + unsigned char MBSM:2; + unsigned char :6; + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + unsigned char TSTE:1; + unsigned char TSTM:2; + unsigned char :5; + } BIT; + } TCR; +}; + +struct st_usb0 { + union { + unsigned short WORD; + struct { + unsigned short USBE:1; + unsigned short :3; + unsigned short DPRPU:1; + unsigned short DRPD:1; + unsigned short DCFM:1; + unsigned short :3; + unsigned short SCKE:1; + unsigned short :5; + } BIT; + } SYSCFG; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short LNST:2; + unsigned short IDMON:1; + unsigned short :3; + unsigned short HTACT:1; + unsigned short :7; + unsigned short OVCMON:2; + } BIT; + } SYSSTS0; + unsigned char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short RHST:3; + unsigned short :1; + unsigned short UACT:1; + unsigned short RESUME:1; + unsigned short USBRST:1; + unsigned short RWUPE:1; + unsigned short WKUP:1; + unsigned short VBUSEN:1; + unsigned short EXICEN:1; + unsigned short HNPBTOA:1; + unsigned short :4; + } BIT; + } DVSTCTR0; + unsigned char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + unsigned char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + unsigned char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + unsigned char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short CURPIPE:4; + unsigned short :1; + unsigned short ISEL:1; + unsigned short :2; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :3; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short DTLN:8; + unsigned short TLN:1; + unsigned short :4; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } CFIFOCTR; + unsigned char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short CURPIPE:4; + unsigned short :4; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short DREQE:1; + unsigned short DCLRM:1; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short DTLN:8; + unsigned short TLN:1; + unsigned short :4; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short CURPIPE:4; + unsigned short :4; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short DREQE:1; + unsigned short DCLRM:1; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short DTLN:8; + unsigned short TLN:1; + unsigned short :4; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short BRDYE:1; + unsigned short NRDYE:1; + unsigned short BEMPE:1; + unsigned short CTRE:1; + unsigned short DVSE:1; + unsigned short SOFE:1; + unsigned short RSME:1; + unsigned short VBSE:1; + } BIT; + } INTENB0; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short SACKE:1; + unsigned short SIGNE:1; + unsigned short EOFERRE:1; + unsigned short :4; + unsigned short ATTCHE:1; + unsigned short DTCHE:1; + unsigned short :1; + unsigned short BCHGE:1; + unsigned short OVRCRE:1; + } BIT; + } INTENB1; + unsigned char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE9BRDYE:1; + unsigned short :6; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE9BRDYE:1; + unsigned short :6; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE9BEMPE:1; + unsigned short :6; + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short EDGESTS:1; + unsigned short :1; + unsigned short BRDYM:1; + unsigned short :1; + unsigned short TRNENSEL:1; + unsigned short :7; + } BIT; + } SOFCFG; + unsigned char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short CTSQ:3; + unsigned short VALID:1; + unsigned short DVSQ:3; + unsigned short VBSTS:1; + unsigned short BRDY:1; + unsigned short NRDY:1; + unsigned short BEMP:1; + unsigned short CTRT:1; + unsigned short DVST:1; + unsigned short SOFR:1; + unsigned short RESM:1; + unsigned short VBINT:1; + } BIT; + } INTSTS0; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short SACK:1; + unsigned short SIGN:1; + unsigned short EOFERR:1; + unsigned short :4; + unsigned short ATTCH:1; + unsigned short DTCH:1; + unsigned short :1; + unsigned short BCHG:1; + unsigned short OVRCR:1; + } BIT; + } INTSTS1; + unsigned char wk9[2]; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE9BRDY:1; + unsigned short :6; + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE9BRDY:1; + unsigned short :6; + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BENP:1; + unsigned short PIPE1BENP:1; + unsigned short PIPE2BENP:1; + unsigned short PIPE3BENP:1; + unsigned short PIPE4BENP:1; + unsigned short PIPE5BENP:1; + unsigned short PIPE6BENP:1; + unsigned short PIPE7BENP:1; + unsigned short PIPE8BENP:1; + unsigned short PIPE9BENP:1; + unsigned short :6; + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + unsigned short FRNM:11; + unsigned short :3; + unsigned short CRCE:1; + unsigned short OVRN:1; + } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short DVCHG:1; + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + unsigned short USBADDR:7; + unsigned short :1; + unsigned short STSRECOV:4; + unsigned short :4; + } BIT; + } USBADDR; + unsigned char wk10[2]; + union { + unsigned short WORD; + struct { + unsigned short BMREQUESTTYPE:8; + unsigned short BREQUEST:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short DIR:1; + unsigned short :2; + unsigned short SHTNAK:1; + unsigned short :8; + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + unsigned short MXPS:7; + unsigned short :5; + unsigned short DEVSEL:4; + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short CCPL:1; + unsigned short :2; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short :2; + unsigned short SUREQCLR:1; + unsigned short :2; + unsigned short SUREQ:1; + unsigned short BSTS:1; + } BIT; + } DCPCTR; + unsigned char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short PIPESEL:4; + unsigned short :12; + } BIT; + } PIPESEL; + unsigned char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short EPNUM:4; + unsigned short DIR:1; + unsigned short :2; + unsigned short SHTNAK:1; + unsigned short :1; + unsigned short DBLB:1; + unsigned short BFRE:1; + unsigned short :3; + unsigned short TYPE:2; + } BIT; + } PIPECFG; + unsigned char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short MXPS:8; + unsigned short XPS:1; + unsigned short :3; + unsigned short DEVSEL:4; + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + unsigned short IITV:3; + unsigned short :9; + unsigned short IFIS:1; + unsigned short :3; + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE9CTR; + unsigned char wk14[14]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + unsigned char wk15[44]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD0; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD1; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD2; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD3; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD4; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD5; +}; + +struct st_usb { + union { + unsigned long LONG; + struct { + unsigned long SRPC0:1; + unsigned long :3; + unsigned long FIXPHY0:1; + unsigned long :3; + unsigned long SRPC1:1; + unsigned long :3; + unsigned long FIXPHY1:1; + unsigned long :3; + unsigned long DP0:1; + unsigned long DM0:1; + unsigned long :2; + unsigned long DOVCA0:1; + unsigned long DOVCB0:1; + unsigned long :1; + unsigned long DVBSTS0:1; + unsigned long DP1:1; + unsigned long DM1:1; + unsigned long :2; + unsigned long DOVCA1:1; + unsigned long DOVCB1:1; + unsigned long :1; + unsigned long DVSTS1:1; + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + unsigned long DPINTE0:1; + unsigned long DMINTE0:1; + unsigned long :2; + unsigned long DOVRCRAE0:1; + unsigned long DOVRCRBE0:1; + unsigned long :1; + unsigned long DVBSE0:1; + unsigned long DPINTE1:1; + unsigned long DMINTE1:1; + unsigned long :2; + unsigned long DOVRCRAE1:1; + unsigned long DOVRCRBE1:1; + unsigned long :1; + unsigned long DVBSE1:1; + unsigned long DPINT0:1; + unsigned long DMINT0:1; + unsigned long :2; + unsigned long DOVRCRA0:1; + unsigned long DOVRCRB0:1; + unsigned long :1; + unsigned long DVBINT0:1; + unsigned long DPINT1:1; + unsigned long DMINT1:1; + unsigned long :2; + unsigned long DOVRCRA1:1; + unsigned long DOVRCRB1:1; + unsigned long :1; + unsigned long DVBINT1:1; + } BIT; + } DPUSR1R; +}; + +struct st_edmac { + union { + unsigned long LONG; + struct { + unsigned long SWR:1; + unsigned long :3; + unsigned long DL:2; + unsigned long DE:1; + unsigned long :25; + } BIT; + } EDMR; + unsigned char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long TR:1; + unsigned long :31; + } BIT; + } EDTRR; + unsigned char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long RR:1; + unsigned long :31; + } BIT; + } EDRRR; + unsigned char wk2[4]; + void *TDLAR; + unsigned char wk3[4]; + void *RDLAR; + unsigned char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long CERF:1; + unsigned long PRE:1; + unsigned long RTSF:1; + unsigned long RTLF:1; + unsigned long RRF:1; + unsigned long :2; + unsigned long RMAF:1; + unsigned long TRO:1; + unsigned long CD:1; + unsigned long DLC:1; + unsigned long CND:1; + unsigned long :4; + unsigned long RFOF:1; + unsigned long RDE:1; + unsigned long FR:1; + unsigned long TFUF:1; + unsigned long TDE:1; + unsigned long TC:1; + unsigned long ECI:1; + unsigned long ADE:1; + unsigned long RFCOF:1; + unsigned long RABT:1; + unsigned long TABT:1; + unsigned long :3; + unsigned long TWB:1; + unsigned long :1; + } BIT; + } EESR; + unsigned char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long CERFIP:1; + unsigned long PREIP:1; + unsigned long RTSFIP:1; + unsigned long RTLFIP:1; + unsigned long RRFIP:1; + unsigned long :2; + unsigned long RMAFIP:1; + unsigned long TROIP:1; + unsigned long CDIP:1; + unsigned long DLCIP:1; + unsigned long CNDIP:1; + unsigned long :4; + unsigned long RFOFIP:1; + unsigned long RDEIP:1; + unsigned long FRIP:1; + unsigned long TFUFIP:1; + unsigned long TDEIP:1; + unsigned long TCIP:1; + unsigned long ECIIP:1; + unsigned long ADEIP:1; + unsigned long RFCOFIP:1; + unsigned long RABTIP:1; + unsigned long TABTIP:1; + unsigned long :3; + unsigned long TWBIP:1; + unsigned long :1; + } BIT; + } EESIPR; + unsigned char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long CERFCE:1; + unsigned long PRECE:1; + unsigned long RTSFCE:1; + unsigned long RTLFCE:1; + unsigned long RRFCE:1; + unsigned long :2; + unsigned long RMAFCE:1; + unsigned long TROCE:1; + unsigned long CDCE:1; + unsigned long DLCCE:1; + unsigned long CNDCE:1; + unsigned long :20; + } BIT; + } TRSCER; + unsigned char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long MFC:16; + unsigned long :16; + } BIT; + } RMFCR; + unsigned char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long TFT:11; + unsigned long :21; + } BIT; + } TFTR; + unsigned char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long RFD:5; + unsigned long :3; + unsigned long TFD:5; + unsigned long :19; + } BIT; + } FDR; + unsigned char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long RNR:1; + unsigned long RNC:1; + unsigned long :30; + } BIT; + } RMCR; + unsigned char wk11[8]; + union { + unsigned long LONG; + struct { + unsigned long UNDER:16; + unsigned long :16; + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + unsigned long OVER:16; + unsigned long :16; + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + unsigned long TLB:1; + unsigned long :31; + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + unsigned long RFDO:3; + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + } BIT; + } FCFTR; + unsigned char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long PADR:6; + unsigned long :10; + unsigned long PADS:2; + unsigned long :14; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long TIS:1; + unsigned long :3; + unsigned long TIM:1; + unsigned long :27; + } BIT; + } TRIMD; + unsigned char wk13[72]; + void *RBWAR; + void *RDFAR; + unsigned char wk14[4]; + void *TBRAR; + void *TDFAR; +}; + +struct st_etherc { + union { + unsigned long LONG; + struct { + unsigned long PRM:1; + unsigned long DM:1; + unsigned long RTM:1; + unsigned long ILB:1; + unsigned long :1; + unsigned long TE:1; + unsigned long RE:1; + unsigned long :2; + unsigned long MPDE:1; + unsigned long :2; + unsigned long PRCEF:1; + unsigned long :3; + unsigned long TXF:1; + unsigned long RXF:1; + unsigned long PFR:1; + unsigned long ZPE:1; + unsigned long TPC:1; + unsigned long :11; + } BIT; + } ECMR; + unsigned char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long RFL:12; + unsigned long :20; + } BIT; + } RFLR; + unsigned char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long ICD:1; + unsigned long MPD:1; + unsigned long LCHNG:1; + unsigned long :1; + unsigned long PSRTO:1; + unsigned long BFR:1; + unsigned long :26; + } BIT; + } ECSR; + unsigned char wk2[4]; + union { + unsigned long LONG; + struct { + unsigned long ICDIP:1; + unsigned long MPDIP:1; + unsigned long LCHNGIP:1; + unsigned long :1; + unsigned long PSRTOIP:1; + unsigned long BFSIPR:1; + unsigned long :26; + } BIT; + } ECSIPR; + unsigned char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long MDC:1; + unsigned long MMD:1; + unsigned long MDO:1; + unsigned long MDI:1; + unsigned long :28; + } BIT; + } PIR; + unsigned char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long LMON:1; + unsigned long :31; + } BIT; + } PSR; + unsigned char wk5[20]; + union { + unsigned long LONG; + struct { + unsigned long RMD:20; + unsigned long :12; + } BIT; + } RDMLR; + unsigned char wk6[12]; + union { + unsigned long LONG; + struct { + unsigned long IPG:5; + unsigned long :27; + } BIT; + } IPGR; + union { + unsigned long LONG; + struct { + unsigned long AP:16; + unsigned long :16; + } BIT; + } APR; + union { + unsigned long LONG; + struct { + unsigned long MP:16; + unsigned long :16; + } BIT; + } MPR; + unsigned char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long RPAUSE:8; + unsigned long :24; + } BIT; + } RFCF; + union { + unsigned long LONG; + struct { + unsigned long TPAUSE:16; + unsigned long :16; + } BIT; + } TPAUSER; + union { + unsigned long LONG; + struct { + unsigned long TXP:8; + unsigned long :24; + } BIT; + } TPAUSECR; + union { + unsigned long LONG; + struct { + unsigned long BCF:16; + unsigned long :16; + } BIT; + } BCFRR; + unsigned char wk8[80]; + unsigned long MAHR; + unsigned char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long MA:16; + unsigned long :16; + } BIT; + } MALR; + unsigned char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + unsigned char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16, +IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMT2_CMI2, +IR_CMT3_CMI3, +IR_ETHER_EINT, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_USB1_D0FIFO1=40,IR_USB1_D1FIFO1,IR_USB1_USBI1, +IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSPI1_SPEI1,IR_RSPI1_SPRI1,IR_RSPI1_SPTI1,IR_RSPI1_SPII1, +IR_CAN0_ERS0=56,IR_CAN0_RXF0,IR_CAN0_TXF0,IR_CAN0_RXM0,IR_CAN0_TXM0, +IR_RTC_PRD=62,IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_USB_USBR0=90,IR_USB_USBR1, +IR_RTC_ALM, +IR_WDT_WOVI=96, +IR_AD0_ADI0=98, +IR_AD1_ADI1, +IR_S12AD_ADI=102, +IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_MTU6_TGIA6,IR_MTU6_TGIB6,IR_MTU6_TGIC6,IR_MTU6_TGID6,IR_MTU6_TCIV6,IR_MTU6_TGIE6,IR_MTU6_TGIF6, +IR_MTU7_TGIA7,IR_MTU7_TGIB7,IR_MTU7_TCIV7,IR_MTU7_TCIU7, +IR_MTU8_TGIA8,IR_MTU8_TGIB8,IR_MTU8_TCIV8,IR_MTU8_TCIU8, +IR_MTU9_TGIA9,IR_MTU9_TGIB9,IR_MTU9_TGIC9,IR_MTU9_TGID9,IR_MTU9_TCIV9, +IR_MTU10_TGIA10,IR_MTU10_TGIB10,IR_MTU10_TGIC10,IR_MTU10_TGID10,IR_MTU10_TCIV10, +IR_MTU11_TGIU11,IR_MTU11_TGIV11,IR_MTU11_TGIW11, +IR_POE_OEI1,IR_POE_OEI2,IR_POE_OEI3,IR_POE_OEI4, +IR_TMR0_CMIA0,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_DMACA_DMAC0I=198,IR_DMACA_DMAC1I,IR_DMACA_DMAC2I,IR_DMACA_DMAC3I, +IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2, +IR_SCI3_ERI3,IR_SCI3_RXI3,IR_SCI3_TXI3,IR_SCI3_TEI3, +IR_SCI5_ERI5=234,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_RIIC0_ICEEI0=246,IR_RIIC0_ICRXI0,IR_RIIC0_ICTXI0,IR_RIIC0_ICTEI0, +IR_RIIC1_ICEEI1,IR_RIIC1_ICRXI1,IR_RIIC1_ICTXI1,IR_RIIC1_ICTEI1 +}; + +enum enum_dtce { +DTCE_BSC_BUSERR=16, +DTCE_FCU_FIFERR=21,DTCE_FCU_FRDYI=23, +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2, +DTCE_CMT3_CMI3, +DTCE_ETHER_EINT, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,DTCE_USB0_USBI0, +DTCE_USB1_D0FIFO1=40,DTCE_USB1_D1FIFO1,DTCE_USB1_USBI1, +DTCE_RSPI0_SPEI0=44,DTCE_RSPI0_SPRI0,DTCE_RSPI0_SPTI0,DTCE_RSPI0_SPII0, +DTCE_RSPI1_SPEI1,DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1,DTCE_RSPI1_SPII1, +DTCE_CAN0_ERS0=56,DTCE_CAN0_RXF0,DTCE_CAN0_TXF0,DTCE_CAN0_RXM0,DTCE_CAN0_TXM0, +DTCE_RTC_PRD=62,DTCE_RTC_CUP, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_USB_USBR0=90,DTCE_USB_USBR1, +DTCE_RTC_ALM, +DTCE_WDT_WOVI=96, +DTCE_AD0_ADI0=98, +DTCE_AD1_ADI1, +DTCE_S12AD_ADI=102, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,DTCE_MTU0_TCIV0,DTCE_MTU0_TGIE0,DTCE_MTU0_TGIF0, +DTCE_MTU1_TGIA1,DTCE_MTU1_TGIB1,DTCE_MTU1_TCIV1,DTCE_MTU1_TCIU1, +DTCE_MTU2_TGIA2,DTCE_MTU2_TGIB2,DTCE_MTU2_TCIV2,DTCE_MTU2_TCIU2, +DTCE_MTU3_TGIA3,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,DTCE_MTU3_TCIV3, +DTCE_MTU4_TGIA4,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_MTU6_TGIA6,DTCE_MTU6_TGIB6,DTCE_MTU6_TGIC6,DTCE_MTU6_TGID6,DTCE_MTU6_TCIV6,DTCE_MTU6_TGIE6,DTCE_MTU6_TGIF6, +DTCE_MTU7_TGIA7,DTCE_MTU7_TGIB7,DTCE_MTU7_TCIV7,DTCE_MTU7_TCIU7, +DTCE_MTU8_TGIA8,DTCE_MTU8_TGIB8,DTCE_MTU8_TCIV8,DTCE_MTU8_TCIU8, +DTCE_MTU9_TGIA9,DTCE_MTU9_TGIB9,DTCE_MTU9_TGIC9,DTCE_MTU9_TGID9,DTCE_MTU9_TCIV9, +DTCE_MTU10_TGIA10,DTCE_MTU10_TGIB10,DTCE_MTU10_TGIC10,DTCE_MTU10_TGID10,DTCE_MTU10_TCIV10, +DTCE_MTU11_TGIU11,DTCE_MTU11_TGIV11,DTCE_MTU11_TGIW11, +DTCE_POE_OEI1,DTCE_POE_OEI2,DTCE_POE_OEI3,DTCE_POE_OEI4, +DTCE_TMR0_CMIA0,DTCE_TMR0_CMIB0,DTCE_TMR0_OVI0, +DTCE_TMR1_CMIA1,DTCE_TMR1_CMIB1,DTCE_TMR1_OVI1, +DTCE_TMR2_CMIA2,DTCE_TMR2_CMIB2,DTCE_TMR2_OVI2, +DTCE_TMR3_CMIA3,DTCE_TMR3_CMIB3,DTCE_TMR3_OVI3, +DTCE_DMACA_DMAC0I=198,DTCE_DMACA_DMAC1I,DTCE_DMACA_DMAC2I,DTCE_DMACA_DMAC3I, +DTCE_EXDMAC_EXDMAC0I,DTCE_EXDMAC_EXDMAC1I, +DTCE_SCI0_ERI0=214,DTCE_SCI0_RXI0,DTCE_SCI0_TXI0,DTCE_SCI0_TEI0, +DTCE_SCI1_ERI1,DTCE_SCI1_RXI1,DTCE_SCI1_TXI1,DTCE_SCI1_TEI1, +DTCE_SCI2_ERI2,DTCE_SCI2_RXI2,DTCE_SCI2_TXI2,DTCE_SCI2_TEI2, +DTCE_SCI3_ERI3,DTCE_SCI3_RXI3,DTCE_SCI3_TXI3,DTCE_SCI3_TEI3, +DTCE_SCI5_ERI5=234,DTCE_SCI5_RXI5,DTCE_SCI5_TXI5,DTCE_SCI5_TEI5, +DTCE_SCI6_ERI6,DTCE_SCI6_RXI6,DTCE_SCI6_TXI6,DTCE_SCI6_TEI6, +DTCE_RIIC0_ICEEI0=246,DTCE_RIIC0_ICRXI0,DTCE_RIIC0_ICTXI0,DTCE_RIIC0_ICTEI0, +DTCE_RIIC1_ICEEI1,DTCE_RIIC1_ICRXI1,DTCE_RIIC1_ICTXI1,DTCE_RIIC1_ICTEI1 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03, +IER_CMT3_CMI3=0x03, +IER_ETHER_EINT=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_USB1_D0FIFO1=0x05,IER_USB1_D1FIFO1=0x05,IER_USB1_USBI1=0x05, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSPI1_SPEI1=0x06,IER_RSPI1_SPRI1=0x06,IER_RSPI1_SPTI1=0x06,IER_RSPI1_SPII1=0x06, +IER_CAN0_ERS0=0x07,IER_CAN0_RXF0=0x07,IER_CAN0_TXF0=0x07,IER_CAN0_RXM0=0x07,IER_CAN0_TXM0=0x07, +IER_RTC_PRD=0x07,IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_USB_USBR0=0x0B,IER_USB_USBR1=0x0B, +IER_RTC_ALM=0x0B, +IER_WDT_WOVI=0x0C, +IER_AD0_ADI0=0x0C, +IER_AD1_ADI1=0x0C, +IER_S12AD_ADI=0x0C, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x10, +IER_MTU6_TGIA6=0x11,IER_MTU6_TGIB6=0x11,IER_MTU6_TGIC6=0x12,IER_MTU6_TGID6=0x12,IER_MTU6_TCIV6=0x12,IER_MTU6_TGIE6=0x12,IER_MTU6_TGIF6=0x12, +IER_MTU7_TGIA7=0x12,IER_MTU7_TGIB7=0x12,IER_MTU7_TCIV7=0x12,IER_MTU7_TCIU7=0x13, +IER_MTU8_TGIA8=0x13,IER_MTU8_TGIB8=0x13,IER_MTU8_TCIV8=0x13,IER_MTU8_TCIU8=0x13, +IER_MTU9_TGIA9=0x13,IER_MTU9_TGIB9=0x13,IER_MTU9_TGIC9=0x13,IER_MTU9_TGID9=0x14,IER_MTU9_TCIV9=0x14, +IER_MTU10_TGIA10=0x14,IER_MTU10_TGIB10=0x14,IER_MTU10_TGIC10=0x14,IER_MTU10_TGID10=0x14,IER_MTU10_TCIV10=0x14, +IER_MTU11_TGIU11=0x14,IER_MTU11_TGIV11=0x15,IER_MTU11_TGIW11=0x15, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,IER_POE_OEI3=0x15,IER_POE_OEI4=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_DMACA_DMAC0I=0x18,IER_DMACA_DMAC1I=0x18,IER_DMACA_DMAC2I=0x19,IER_DMACA_DMAC3I=0x19, +IER_EXDMAC_EXDMAC0I=0x19,IER_EXDMAC_EXDMAC1I=0x19, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI2_ERI2=0x1B,IER_SCI2_RXI2=0x1B,IER_SCI2_TXI2=0x1C,IER_SCI2_TEI2=0x1C, +IER_SCI3_ERI3=0x1C,IER_SCI3_RXI3=0x1C,IER_SCI3_TXI3=0x1C,IER_SCI3_TEI3=0x1C, +IER_SCI5_ERI5=0x1D,IER_SCI5_RXI5=0x1D,IER_SCI5_TXI5=0x1D,IER_SCI5_TEI5=0x1D, +IER_SCI6_ERI6=0x1D,IER_SCI6_RXI6=0x1D,IER_SCI6_TXI6=0x1E,IER_SCI6_TEI6=0x1E, +IER_RIIC0_ICEEI0=0x1E,IER_RIIC0_ICRXI0=0x1E,IER_RIIC0_ICTXI0=0x1F,IER_RIIC0_ICTEI0=0x1F, +IER_RIIC1_ICEEI1=0x1F,IER_RIIC1_ICRXI1=0x1F,IER_RIIC1_ICTXI1=0x1F,IER_RIIC1_ICTEI1=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0x00, +IPR_FCU_FIFERR=0x01,IPR_FCU_FRDYI=0x02, +IPR_ICU_SWINT=0x03, +IPR_CMT0_CMI0=0x04, +IPR_CMT1_CMI1=0x05, +IPR_CMT2_CMI2=0x06, +IPR_CMT3_CMI3=0x07, +IPR_ETHER_EINT=0x08, +IPR_USB0_D0FIFO0=0x0C,IPR_USB0_D1FIFO0=0x0D,IPR_USB0_USBI0=0x0E, +IPR_USB1_D0FIFO1=0x10,IPR_USB1_D1FIFO1=0x11,IPR_USB1_USBI1=0x12, +IPR_RSPI0_SPEI0=0x14,IPR_RSPI0_SPRI0=0x14,IPR_RSPI0_SPTI0=0x14,IPR_RSPI0_SPII0=0x14, +IPR_RSPI1_SPEI1=0x15,IPR_RSPI1_SPRI1=0x15,IPR_RSPI1_SPTI1=0x15,IPR_RSPI1_SPII1=0x15, +IPR_CAN0_ERS0=0x18,IPR_CAN0_RXF0=0x18,IPR_CAN0_TXF0=0x18,IPR_CAN0_RXM0=0x18,IPR_CAN0_TXM0=0x18, +IPR_RTC_PRD=0x1E,IPR_RTC_CUP=0x1F, +IPR_ICU_IRQ0=0x20,IPR_ICU_IRQ1=0x21,IPR_ICU_IRQ2=0x22,IPR_ICU_IRQ3=0x23,IPR_ICU_IRQ4=0x24,IPR_ICU_IRQ5=0x25,IPR_ICU_IRQ6=0x26,IPR_ICU_IRQ7=0x27,IPR_ICU_IRQ8=0x28,IPR_ICU_IRQ9=0x29,IPR_ICU_IRQ10=0x2A,IPR_ICU_IRQ11=0x2B,IPR_ICU_IRQ12=0x2C,IPR_ICU_IRQ13=0x2D,IPR_ICU_IRQ14=0x2E,IPR_ICU_IRQ15=0x2F, +IPR_USB_USBR0=0x3A,IPR_USB_USBR1=0x3B, +IPR_RTC_ALM=0x3C, +IPR_WDT_WOVI=0x40, +IPR_AD0_ADI0=0x44, +IPR_AD1_ADI1=0x45, +IPR_S12AD_ADI=0x48, +IPR_MTU0_TGIA0=0x51,IPR_MTU0_TGIB0=0x51,IPR_MTU0_TGIC0=0x51,IPR_MTU0_TGID0=0x51,IPR_MTU0_TCIV0=0x52,IPR_MTU0_TGIE0=0x52,IPR_MTU0_TGIF0=0x52, +IPR_MTU1_TGIA1=0x53,IPR_MTU1_TGIB1=0x53,IPR_MTU1_TCIV1=0x54,IPR_MTU1_TCIU1=0x54, +IPR_MTU2_TGIA2=0x55,IPR_MTU2_TGIB2=0x55,IPR_MTU2_TCIV2=0x56,IPR_MTU2_TCIU2=0x56, +IPR_MTU3_TGIA3=0x57,IPR_MTU3_TGIB3=0x57,IPR_MTU3_TGIC3=0x57,IPR_MTU3_TGID3=0x57,IPR_MTU3_TCIV3=0x58, +IPR_MTU4_TGIA4=0x59,IPR_MTU4_TGIB4=0x59,IPR_MTU4_TGIC4=0x59,IPR_MTU4_TGID4=0x59,IPR_MTU4_TCIV4=0x5A, +IPR_MTU5_TGIU5=0x5B,IPR_MTU5_TGIV5=0x5B,IPR_MTU5_TGIW5=0x5B, +IPR_MTU6_TGIA6=0x5C,IPR_MTU6_TGIB6=0x5C,IPR_MTU6_TGIC6=0x5C,IPR_MTU6_TGID6=0x5C,IPR_MTU6_TCIV6=0x5D,IPR_MTU6_TGIE6=0x5D,IPR_MTU6_TGIF6=0x5D, +IPR_MTU7_TGIA7=0x5E,IPR_MTU7_TGIB7=0x5E,IPR_MTU7_TCIV7=0x5F,IPR_MTU7_TCIU7=0x5F, +IPR_MTU8_TGIA8=0x60,IPR_MTU8_TGIB8=0x60,IPR_MTU8_TCIV8=0x61,IPR_MTU8_TCIU8=0x61, +IPR_MTU9_TGIA9=0x62,IPR_MTU9_TGIB9=0x62,IPR_MTU9_TGIC9=0x62,IPR_MTU9_TGID9=0x62,IPR_MTU9_TCIV9=0x63, +IPR_MTU10_TGIA10=0x64,IPR_MTU10_TGIB10=0x64,IPR_MTU10_TGIC10=0x64,IPR_MTU10_TGID10=0x64,IPR_MTU10_TCIV10=0x65, +IPR_MTU11_TGIU11=0x66,IPR_MTU11_TGIV11=0x66,IPR_MTU11_TGIW11=0x66, +IPR_POE_OEI1=0x67,IPR_POE_OEI2=0x67,IPR_POE_OEI3=0x67,IPR_POE_OEI4=0x67, +IPR_TMR0_CMIA0=0x68,IPR_TMR0_CMIB0=0x68,IPR_TMR0_OVI0=0x68, +IPR_TMR1_CMIA1=0x69,IPR_TMR1_CMIB1=0x69,IPR_TMR1_OVI1=0x69, +IPR_TMR2_CMIA2=0x6A,IPR_TMR2_CMIB2=0x6A,IPR_TMR2_OVI2=0x6A, +IPR_TMR3_CMIA3=0x6B,IPR_TMR3_CMIB3=0x6B,IPR_TMR3_OVI3=0x6B, +IPR_DMACA_DMAC0I=0x70,IPR_DMACA_DMAC1I=0x71,IPR_DMACA_DMAC2I=0x72,IPR_DMACA_DMAC3I=0x73, +IPR_EXDMAC_EXDMAC0I=0x74,IPR_EXDMAC_EXDMAC1I=0x75, +IPR_SCI0_ERI0=0x80,IPR_SCI0_RXI0=0x80,IPR_SCI0_TXI0=0x80,IPR_SCI0_TEI0=0x80, +IPR_SCI1_ERI1=0x81,IPR_SCI1_RXI1=0x81,IPR_SCI1_TXI1=0x81,IPR_SCI1_TEI1=0x81, +IPR_SCI2_ERI2=0x82,IPR_SCI2_RXI2=0x82,IPR_SCI2_TXI2=0x82,IPR_SCI2_TEI2=0x82, +IPR_SCI3_ERI3=0x83,IPR_SCI3_RXI3=0x83,IPR_SCI3_TXI3=0x83,IPR_SCI3_TEI3=0x83, +IPR_SCI5_ERI5=0x85,IPR_SCI5_RXI5=0x85,IPR_SCI5_TXI5=0x85,IPR_SCI5_TEI5=0x85, +IPR_SCI6_ERI6=0x86,IPR_SCI6_RXI6=0x86,IPR_SCI6_TXI6=0x86,IPR_SCI6_TEI6=0x86, +IPR_RIIC0_ICEEI0=0x88,IPR_RIIC0_ICRXI0=0x89,IPR_RIIC0_ICTXI0=0x8A,IPR_RIIC0_ICTEI0=0x8B, +IPR_RIIC1_ICEEI1=0x8C,IPR_RIIC1_ICRXI1=0x8D,IPR_RIIC1_ICTXI1=0x8E,IPR_RIIC1_ICTEI1=0x8F, +IPR_BSC_=0x00, +IPR_CMT0_=0x04, +IPR_CMT1_=0x05, +IPR_CMT2_=0x06, +IPR_CMT3_=0x07, +IPR_ETHER_=0x08, +IPR_RSPI0_=0x14, +IPR_RSPI1_=0x15, +IPR_CAN0_=0x18, +IPR_WDT_=0x40, +IPR_AD0_=0x44, +IPR_AD1_=0x45, +IPR_S12AD_=0x48, +IPR_MTU1_TGI=0x53, +IPR_MTU1_TCI=0x54, +IPR_MTU2_TGI=0x55, +IPR_MTU2_TCI=0x56, +IPR_MTU3_TGI=0x57, +IPR_MTU4_TGI=0x59, +IPR_MTU5_=0x5B, +IPR_MTU5_TGI=0x5B, +IPR_MTU7_TGI=0x5E, +IPR_MTU7_TCI=0x5F, +IPR_MTU8_TGI=0x60, +IPR_MTU8_TCI=0x61, +IPR_MTU9_TGI=0x62, +IPR_MTU10_TGI=0x64, +IPR_MTU11_=0x66, +IPR_MTU11_TGI=0x66, +IPR_POE_=0x67, +IPR_POE_OEI=0x67, +IPR_TMR0_=0x68, +IPR_TMR1_=0x69, +IPR_TMR2_=0x6A, +IPR_TMR3_=0x6B, +IPR_SCI0_=0x80, +IPR_SCI1_=0x81, +IPR_SCI2_=0x82, +IPR_SCI3_=0x83, +IPR_SCI5_=0x85, +IPR_SCI6_=0x86 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_ETHER_EINT IEN0 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_USB1_D0FIFO1 IEN0 +#define IEN_USB1_D1FIFO1 IEN1 +#define IEN_USB1_USBI1 IEN2 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_RSPI1_SPEI1 IEN0 +#define IEN_RSPI1_SPRI1 IEN1 +#define IEN_RSPI1_SPTI1 IEN2 +#define IEN_RSPI1_SPII1 IEN3 +#define IEN_CAN0_ERS0 IEN0 +#define IEN_CAN0_RXF0 IEN1 +#define IEN_CAN0_TXF0 IEN2 +#define IEN_CAN0_RXM0 IEN3 +#define IEN_CAN0_TXM0 IEN4 +#define IEN_RTC_PRD IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_USB_USBR0 IEN2 +#define IEN_USB_USBR1 IEN3 +#define IEN_RTC_ALM IEN4 +#define IEN_WDT_WOVI IEN0 +#define IEN_AD0_ADI0 IEN2 +#define IEN_AD1_ADI1 IEN3 +#define IEN_S12AD_ADI IEN6 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN7 +#define IEN_MTU6_TGIA6 IEN6 +#define IEN_MTU6_TGIB6 IEN7 +#define IEN_MTU6_TGIC6 IEN0 +#define IEN_MTU6_TGID6 IEN1 +#define IEN_MTU6_TCIV6 IEN2 +#define IEN_MTU6_TGIE6 IEN3 +#define IEN_MTU6_TGIF6 IEN4 +#define IEN_MTU7_TGIA7 IEN5 +#define IEN_MTU7_TGIB7 IEN6 +#define IEN_MTU7_TCIV7 IEN7 +#define IEN_MTU7_TCIU7 IEN0 +#define IEN_MTU8_TGIA8 IEN1 +#define IEN_MTU8_TGIB8 IEN2 +#define IEN_MTU8_TCIV8 IEN3 +#define IEN_MTU8_TCIU8 IEN4 +#define IEN_MTU9_TGIA9 IEN5 +#define IEN_MTU9_TGIB9 IEN6 +#define IEN_MTU9_TGIC9 IEN7 +#define IEN_MTU9_TGID9 IEN0 +#define IEN_MTU9_TCIV9 IEN1 +#define IEN_MTU10_TGIA10 IEN2 +#define IEN_MTU10_TGIB10 IEN3 +#define IEN_MTU10_TGIC10 IEN4 +#define IEN_MTU10_TGID10 IEN5 +#define IEN_MTU10_TCIV10 IEN6 +#define IEN_MTU11_TGIU11 IEN7 +#define IEN_MTU11_TGIV11 IEN0 +#define IEN_MTU11_TGIW11 IEN1 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_POE_OEI3 IEN4 +#define IEN_POE_OEI4 IEN5 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_DMACA_DMAC0I IEN6 +#define IEN_DMACA_DMAC1I IEN7 +#define IEN_DMACA_DMAC2I IEN0 +#define IEN_DMACA_DMAC3I IEN1 +#define IEN_EXDMAC_EXDMAC0I IEN2 +#define IEN_EXDMAC_EXDMAC1I IEN3 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI2_ERI2 IEN6 +#define IEN_SCI2_RXI2 IEN7 +#define IEN_SCI2_TXI2 IEN0 +#define IEN_SCI2_TEI2 IEN1 +#define IEN_SCI3_ERI3 IEN2 +#define IEN_SCI3_RXI3 IEN3 +#define IEN_SCI3_TXI3 IEN4 +#define IEN_SCI3_TEI3 IEN5 +#define IEN_SCI5_ERI5 IEN2 +#define IEN_SCI5_RXI5 IEN3 +#define IEN_SCI5_TXI5 IEN4 +#define IEN_SCI5_TEI5 IEN5 +#define IEN_SCI6_ERI6 IEN6 +#define IEN_SCI6_RXI6 IEN7 +#define IEN_SCI6_TXI6 IEN0 +#define IEN_SCI6_TEI6 IEN1 +#define IEN_RIIC0_ICEEI0 IEN6 +#define IEN_RIIC0_ICRXI0 IEN7 +#define IEN_RIIC0_ICTXI0 IEN0 +#define IEN_RIIC0_ICTEI0 IEN1 +#define IEN_RIIC1_ICEEI1 IEN2 +#define IEN_RIIC1_ICRXI1 IEN3 +#define IEN_RIIC1_ICTXI1 IEN4 +#define IEN_RIIC1_ICTEI1 IEN5 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_ETHER_EINT 32 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_USB1_D0FIFO1 40 +#define VECT_USB1_D1FIFO1 41 +#define VECT_USB1_USBI1 42 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_RSPI1_SPEI1 48 +#define VECT_RSPI1_SPRI1 49 +#define VECT_RSPI1_SPTI1 50 +#define VECT_RSPI1_SPII1 51 +#define VECT_CAN0_ERS0 56 +#define VECT_CAN0_RXF0 57 +#define VECT_CAN0_TXF0 58 +#define VECT_CAN0_RXM0 59 +#define VECT_CAN0_TXM0 60 +#define VECT_RTC_PRD 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_USB_USBR0 90 +#define VECT_USB_USBR1 91 +#define VECT_RTC_ALM 92 +#define VECT_WDT_WOVI 96 +#define VECT_AD0_ADI0 98 +#define VECT_AD1_ADI1 99 +#define VECT_S12AD_ADI 102 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_MTU6_TGIA6 142 +#define VECT_MTU6_TGIB6 143 +#define VECT_MTU6_TGIC6 144 +#define VECT_MTU6_TGID6 145 +#define VECT_MTU6_TCIV6 146 +#define VECT_MTU6_TGIE6 147 +#define VECT_MTU6_TGIF6 148 +#define VECT_MTU7_TGIA7 149 +#define VECT_MTU7_TGIB7 150 +#define VECT_MTU7_TCIV7 151 +#define VECT_MTU7_TCIU7 152 +#define VECT_MTU8_TGIA8 153 +#define VECT_MTU8_TGIB8 154 +#define VECT_MTU8_TCIV8 155 +#define VECT_MTU8_TCIU8 156 +#define VECT_MTU9_TGIA9 157 +#define VECT_MTU9_TGIB9 158 +#define VECT_MTU9_TGIC9 159 +#define VECT_MTU9_TGID9 160 +#define VECT_MTU9_TCIV9 161 +#define VECT_MTU10_TGIA10 162 +#define VECT_MTU10_TGIB10 163 +#define VECT_MTU10_TGIC10 164 +#define VECT_MTU10_TGID10 165 +#define VECT_MTU10_TCIV10 166 +#define VECT_MTU11_TGIU11 167 +#define VECT_MTU11_TGIV11 168 +#define VECT_MTU11_TGIW11 169 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_POE_OEI3 172 +#define VECT_POE_OEI4 173 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_DMACA_DMAC0I 198 +#define VECT_DMACA_DMAC1I 199 +#define VECT_DMACA_DMAC2I 200 +#define VECT_DMACA_DMAC3I 201 +#define VECT_EXDMAC_EXDMAC0I 202 +#define VECT_EXDMAC_EXDMAC1I 203 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI2_ERI2 222 +#define VECT_SCI2_RXI2 223 +#define VECT_SCI2_TXI2 224 +#define VECT_SCI2_TEI2 225 +#define VECT_SCI3_ERI3 226 +#define VECT_SCI3_RXI3 227 +#define VECT_SCI3_TXI3 228 +#define VECT_SCI3_TEI3 229 +#define VECT_SCI5_ERI5 234 +#define VECT_SCI5_RXI5 235 +#define VECT_SCI5_TXI5 236 +#define VECT_SCI5_TEI5 237 +#define VECT_SCI6_ERI6 238 +#define VECT_SCI6_RXI6 239 +#define VECT_SCI6_TXI6 240 +#define VECT_SCI6_TEI6 241 +#define VECT_RIIC0_ICEEI0 246 +#define VECT_RIIC0_ICRXI0 247 +#define VECT_RIIC0_ICTXI0 248 +#define VECT_RIIC0_ICTEI0 249 +#define VECT_RIIC1_ICEEI1 250 +#define VECT_RIIC1_ICRXI1 251 +#define VECT_RIIC1_ICTXI1 252 +#define VECT_RIIC1_ICTEI1 253 + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMACA SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_AD0 SYSTEM.MSTPCRA.BIT.MSTPA23 +#define MSTP_AD1 SYSTEM.MSTPCRA.BIT.MSTPA22 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTUA SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTUB SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU9 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU10 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU11 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_USB1 SYSTEM.MSTPCRB.BIT.MSTPB18 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_EDMAC SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC1 +#define MSTP_RAM1 SYSTEM.MSTPCRC.BIT.MSTPC0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define BSC (*(volatile struct st_bsc *)0x81300) +#define DMAC0 (*(volatile struct st_dmac0 *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 *)0x820C0) +#define DMAC (*(volatile struct st_dmac *)0x82200) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define EXDMAC0 (*(volatile struct st_exdmac0 *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac0 *)0x82840) +#define EXDMAC (*(volatile struct st_exdmac *)0x82A00) +#define ICU (*(volatile struct st_icu *)0x87000) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define WDT (*(volatile union un_wdt *)0x88028) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define AD0 (*(volatile struct st_ad *)0x88040) +#define AD1 (*(volatile struct st_ad *)0x88060) +#define DA (*(volatile struct st_da *)0x880C0) +#define PPG0 (*(volatile struct st_ppg0 *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 *)0x881F0) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define SCI0 (*(volatile struct st_sci *)0x88240) +#define SCI1 (*(volatile struct st_sci *)0x88248) +#define SCI2 (*(volatile struct st_sci *)0x88250) +#define SCI3 (*(volatile struct st_sci *)0x88258) +#define SCI5 (*(volatile struct st_sci *)0x88268) +#define SCI6 (*(volatile struct st_sci *)0x88270) +#define SMCI0 (*(volatile struct st_smci *)0x88240) +#define SMCI1 (*(volatile struct st_smci *)0x88248) +#define SMCI2 (*(volatile struct st_smci *)0x88250) +#define SMCI3 (*(volatile struct st_smci *)0x88258) +#define SMCI5 (*(volatile struct st_smci *)0x88268) +#define SMCI6 (*(volatile struct st_smci *)0x88270) +#define CRC (*(volatile struct st_crc *)0x88280) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RIIC1 (*(volatile struct st_riic *)0x88320) +#define RSPI0 (*(volatile struct st_rspi *)0x88380) +#define RSPI1 (*(volatile struct st_rspi *)0x883A0) +#define MTUA (*(volatile struct st_mtu *)0x8860A) +#define MTU0 (*(volatile struct st_mtu0 *)0x88700) +#define MTU1 (*(volatile struct st_mtu1 *)0x88780) +#define MTU2 (*(volatile struct st_mtu2 *)0x88800) +#define MTU3 (*(volatile struct st_mtu3 *)0x88600) +#define MTU4 (*(volatile struct st_mtu4 *)0x88600) +#define MTU5 (*(volatile struct st_mtu5 *)0x88880) +#define POE (*(volatile struct st_poe *)0x88900) +#define MTUB (*(volatile struct st_mtu *)0x88A0A) +#define MTU6 (*(volatile struct st_mtu0 *)0x88B00) +#define MTU7 (*(volatile struct st_mtu1 *)0x88B80) +#define MTU8 (*(volatile struct st_mtu2 *)0x88C00) +#define MTU9 (*(volatile struct st_mtu3 *)0x88A00) +#define MTU10 (*(volatile struct st_mtu4 *)0x88A00) +#define MTU11 (*(volatile struct st_mtu5 *)0x88C80) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORT6 (*(volatile struct st_port6 *)0x8C006) +#define PORT7 (*(volatile struct st_port7 *)0x8C007) +#define PORT8 (*(volatile struct st_port8 *)0x8C008) +#define PORT9 (*(volatile struct st_port9 *)0x8C009) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTF (*(volatile struct st_portf *)0x8C00F) +#define PORTG (*(volatile struct st_portg *)0x8C010) +#define IOPORT (*(volatile struct st_ioport *)0x8C100) +#define FLASH (*(volatile struct st_flash *)0x8C288) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define CAN0 (*(volatile struct st_can *)0x90200) +#define USB0 (*(volatile struct st_usb0 *)0xA0000) +#define USB1 (*(volatile struct st_usb0 *)0xA0200) +#define USB (*(volatile struct st_usb *)0xA0400) +#define EDMAC (*(volatile struct st_edmac *)0xC0000) +#define ETHERC (*(volatile struct st_etherc *)0xC0100) + +#elif __RX_BIG_ENDIAN__ /*Big endian*/ + +struct st_system { + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short MDE:1; + unsigned short :5; + unsigned short MD1:1; + unsigned short MD0:1; + } BIT; + } MDMONR; + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short UBTS:1; + unsigned short :1; + unsigned short BOTS:1; + unsigned short BSW:2; + unsigned short EXB:1; + unsigned short IROM:1; + } BIT; + } MDSR; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short EXBE:1; + unsigned short ROME:1; + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RAME:1; + } BIT; + } SYSCR1; + unsigned char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short SSBY:1; + unsigned short OPE:1; + unsigned short :1; + unsigned short STS:5; + unsigned short :8; + } BIT; + } SBYCR; + unsigned char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long ACSE:1; + unsigned long :1; + unsigned long MSTPA29:1; + unsigned long MSTPA28:1; + unsigned long :4; + unsigned long MSTPA23:1; + unsigned long MSTPA22:1; + unsigned long :2; + unsigned long MSTPA19:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long :1; + unsigned long MSTPA15:1; + unsigned long MSTPA14:1; + unsigned long :2; + unsigned long MSTPA11:1; + unsigned long MSTPA10:1; + unsigned long MSTPA9:1; + unsigned long MSTPA8:1; + unsigned long :2; + unsigned long MSTPA5:1; + unsigned long MSTPA4:1; + unsigned long :4; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB31:1; + unsigned long MSTPB30:1; + unsigned long MSTPB29:1; + unsigned long MSTPB28:1; + unsigned long :1; + unsigned long MSTPB26:1; + unsigned long MSTPB25:1; + unsigned long :1; + unsigned long MSTPB23:1; + unsigned long :1; + unsigned long MSTPB21:1; + unsigned long MSTPB20:1; + unsigned long MSTPB19:1; + unsigned long MSTPB18:1; + unsigned long MSTPB17:1; + unsigned long MSTPB16:1; + unsigned long MSTPB15:1; + unsigned long :14; + unsigned long MSTPB0:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long MSTPC1:1; + unsigned long MSTPC0:1; + } BIT; + } MSTPCRC; + unsigned char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long ICK:4; + unsigned long PSTOP1:1; + unsigned long PSTOP0:1; + unsigned long :2; + unsigned long BCK:4; + unsigned long :4; + unsigned long PCK:4; + unsigned long :8; + } BIT; + } SCKCR; + unsigned char wk4[12]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCLKDIV:1; + } BIT; + } BCKCR; + unsigned char wk5[15]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short OSTDE:1; + unsigned short OSTDF:1; + unsigned short :6; + } BIT; + } OSTDCR; + unsigned char wk6[49726]; + union { + unsigned char BYTE; + struct { + unsigned char DPSBY:1; + unsigned char IOKEEP:1; + unsigned char RAMCUT2:1; + unsigned char RAMCUT1:1; + unsigned char :3; + unsigned char RAMCUT0:1; + } BIT; + } DPSBYCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char WTSTS:6; + } BIT; + } DPSWCR; + union { + unsigned char BYTE; + struct { + unsigned char DNMIE:1; + unsigned char DUSBE:1; + unsigned char DRTCE:1; + unsigned char DLVDE:1; + unsigned char DIRQ3E:1; + unsigned char DIRQ2E:1; + unsigned char DIRQ1E:1; + unsigned char DIRQ0E:1; + } BIT; + } DPSIER; + union { + unsigned char BYTE; + struct { + unsigned char DNMIF:1; + unsigned char DUSBF:1; + unsigned char DRTCFF:1; + unsigned char DLVDF:1; + unsigned char DIRQ3F:1; + unsigned char DIRQ2F:1; + unsigned char DIRQ1F:1; + unsigned char DIRQ0F:1; + } BIT; + } DPSIFR; + union { + unsigned char BYTE; + struct { + unsigned char DNMIEG:1; + unsigned char :3; + unsigned char DIRQ3EG:1; + unsigned char DIRQ2EG:1; + unsigned char DIRQ1EG:1; + unsigned char DIRQ0EG:1; + } BIT; + } DPSIEGR; + union { + unsigned char BYTE; + struct { + unsigned char DPSRSTF:1; + unsigned char :4; + unsigned char LVD2F:1; + unsigned char LVD1F:1; + unsigned char PORF:1; + } BIT; + } RSTSR; + unsigned char wk7[4]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SUBSTOP:1; + } BIT; + } SUBOSCCR; + unsigned char wk8[1]; + unsigned char LVDKEYR; + union { + unsigned char BYTE; + struct { + unsigned char LVD2E:1; + unsigned char LVD2RI:1; + unsigned char :2; + unsigned char LVD1E:1; + unsigned char LVD1RI:1; + unsigned char :2; + } BIT; + } LVDCR; + unsigned char wk9[2]; + unsigned char DPSBKR[32]; +}; + +struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char STSCLR:1; + } BIT; + } BERCLR; + unsigned char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TOEN:1; + unsigned char IGAEN:1; + } BIT; + } BEREN; + unsigned char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MST:3; + unsigned char :2; + unsigned char TO:1; + unsigned char IA:1; + } BIT; + } BERSR1; + unsigned char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ADDR:13; + unsigned short :3; + } BIT; + } BERSR2; + unsigned char wk3[7414]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS0WCR2; + unsigned char wk4[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS1WCR2; + unsigned char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS2WCR2; + unsigned char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS3WCR2; + unsigned char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS4WCR2; + unsigned char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS5WCR2; + unsigned char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS6WCR2; + unsigned char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS7WCR2; + unsigned char wk11[1926]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS0CR; + unsigned char wk12[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS0REC; + unsigned char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS1CR; + unsigned char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS1REC; + unsigned char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS2CR; + unsigned char wk16[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS2REC; + unsigned char wk17[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS3CR; + unsigned char wk18[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS3REC; + unsigned char wk19[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS4CR; + unsigned char wk20[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS4REC; + unsigned char wk21[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS5CR; + unsigned char wk22[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS5REC; + unsigned char wk23[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS6CR; + unsigned char wk24[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS6REC; + unsigned char wk25[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS7CR; + unsigned char wk26[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS7REC; + unsigned char wk27[900]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BSIZE:2; + unsigned char :3; + unsigned char EXENB:1; + } BIT; + } SDCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EMODE:1; + } BIT; + } SDCMOD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BE:1; + } BIT; + } SDAMOD; + unsigned char wk28[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SFEN:1; + } BIT; + } SDSELF; + unsigned char wk29[3]; + union { + unsigned short WORD; + struct { + unsigned short REFW:4; + unsigned short RFC:12; + } BIT; + } SDRFCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RFEN:1; + } BIT; + } SDRFEN; + unsigned char wk30[9]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char INIRQ:1; + } BIT; + } SDICR; + unsigned char wk31[3]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short PRC:3; + unsigned short ARFC:4; + unsigned short ARFI:4; + } BIT; + } SDIR; + unsigned char wk32[26]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MXC:2; + } BIT; + } SDADR; + unsigned char wk33[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RAS:3; + unsigned long :2; + unsigned long RCD:2; + unsigned long RP:3; + unsigned long WR:1; + unsigned long :5; + unsigned long CL:3; + } BIT; + } SDTR; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short MR:15; + } BIT; + } SDMOD; + unsigned char wk34[6]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SRFST:1; + unsigned char INIST:1; + unsigned char :2; + unsigned char MRSST:1; + } BIT; + } SDSR; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + unsigned char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + unsigned char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } DMAST; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char RRS:1; + unsigned char :4; + } BIT; + } DTCCR; + unsigned char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHORT:1; + } BIT; + } DTCADMOD; + unsigned char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCST:1; + } BIT; + } DTCST; + unsigned char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ACT:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSTS; +}; + +struct st_exdmac0 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char DACKS:1; + unsigned char DACKE:1; + unsigned char DACKW:1; + unsigned char :1; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long AMS:1; + unsigned long DIR:1; + unsigned long SM:2; + unsigned long :1; + unsigned long SARA:5; + unsigned long DM:2; + unsigned long :1; + unsigned long DARA:5; + } BIT; + } EDMAMD; + unsigned long EDMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } EDMSTS; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DREQS:2; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EREQ:1; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PREQ:1; + } BIT; + } EDMPRF; +}; + +struct st_exdmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } EDMAST; + unsigned char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IR:1; + } BIT; + } IR[254]; + unsigned char wk17[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCE:1; + } BIT; + } DTCER[254]; + unsigned char wk47[2]; + union { + unsigned char BYTE; + struct { + unsigned char IEN7:1; + unsigned char IEN6:1; + unsigned char IEN5:1; + unsigned char IEN4:1; + unsigned char IEN3:1; + unsigned char IEN2:1; + unsigned char IEN1:1; + unsigned char IEN0:1; + } BIT; + } IER[32]; + unsigned char wk50[192]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT:1; + } BIT; + } SWINTR; + unsigned char wk51[15]; + union { + unsigned short WORD; + struct { + unsigned short FIEN:1; + unsigned short :7; + unsigned short FVCT:8; + } BIT; + } FIR; + unsigned char wk52[14]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IPR:4; + } BIT; + } IPR[144]; + unsigned char wk67[112]; + unsigned char DMRSR0; + unsigned char wk68[3]; + unsigned char DMRSR1; + unsigned char wk69[3]; + unsigned char DMRSR2; + unsigned char wk70[3]; + unsigned char DMRSR3; + unsigned char wk71[243]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IRQMD:2; + unsigned char :2; + } BIT; + } IRQCR[16]; + unsigned char wk72[112]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OSTST:1; + unsigned char LVDST:1; + unsigned char NMIST:1; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OSTEN:1; + unsigned char LVDEN:1; + unsigned char NMIEN:1; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OSTCLR:1; + unsigned char :1; + unsigned char NMICLR:1; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NMIMD:1; + unsigned char :3; + } BIT; + } NMICR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR1:1; + unsigned short STR0:1; + } BIT; + } CMSTR0; + unsigned char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR3:1; + unsigned short STR2:1; + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short CMIE:1; + unsigned short :4; + unsigned short CKS:2; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +union un_wdt { + struct { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TMS:1; + unsigned char TME:1; + unsigned char :2; + unsigned char CKS:3; + } BIT; + } TCSR; + unsigned char TCNT; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char WOVF:1; + unsigned char RSTE:1; + unsigned char :6; + } BIT; + } RSTCSR; + } READ; + struct { + unsigned short WINA; + unsigned short WINB; + } WRITE; +}; + +struct st_iwdt { + unsigned char IWDTRR; + unsigned char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } IWDTSR; +}; + +struct st_ad { + unsigned short ADDRA; + unsigned short ADDRB; + unsigned short ADDRC; + unsigned short ADDRD; + unsigned char wk0[8]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ADIE:1; + unsigned char ADST:1; + unsigned char :1; + unsigned char CH:4; + } BIT; + } ADCSR; + union { + unsigned char BYTE; + struct { + unsigned char TRGS:3; + unsigned char :1; + unsigned char CKS:2; + unsigned char MODE:2; + } BIT; + } ADCR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + unsigned char :7; + } BIT; + } ADDPR; + unsigned char ADSSTR; + unsigned char wk1[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DIAG:2; + } BIT; + } ADDIAGR; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char DAOE1:1; + unsigned char DAOE0:1; + unsigned char DAE:1; + unsigned char :5; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + unsigned char :7; + } BIT; + } DADPR; +}; + +struct st_ppg0 { + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER15:1; + unsigned char NDER14:1; + unsigned char NDER13:1; + unsigned char NDER12:1; + unsigned char NDER11:1; + unsigned char NDER10:1; + unsigned char NDER9:1; + unsigned char NDER8:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER7:1; + unsigned char NDER6:1; + unsigned char NDER5:1; + unsigned char NDER4:1; + unsigned char NDER3:1; + unsigned char NDER2:1; + unsigned char NDER1:1; + unsigned char NDER0:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD15:1; + unsigned char POD14:1; + unsigned char POD13:1; + unsigned char POD12:1; + unsigned char POD11:1; + unsigned char POD10:1; + unsigned char POD9:1; + unsigned char POD8:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD7:1; + unsigned char POD6:1; + unsigned char POD5:1; + unsigned char POD4:1; + unsigned char POD3:1; + unsigned char POD2:1; + unsigned char POD1:1; + unsigned char POD0:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR15:1; + unsigned char NDR14:1; + unsigned char NDR13:1; + unsigned char NDR12:1; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR7:1; + unsigned char NDR6:1; + unsigned char NDR5:1; + unsigned char NDR4:1; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL2; +}; + +struct st_ppg1 { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PTRSL:1; + } BIT; + } PTRSLR; + unsigned char wk0[5]; + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER31:1; + unsigned char NDER30:1; + unsigned char NDER29:1; + unsigned char NDER28:1; + unsigned char NDER27:1; + unsigned char NDER26:1; + unsigned char NDER25:1; + unsigned char NDER24:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER23:1; + unsigned char NDER22:1; + unsigned char NDER21:1; + unsigned char NDER20:1; + unsigned char NDER19:1; + unsigned char NDER18:1; + unsigned char NDER17:1; + unsigned char NDER16:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD31:1; + unsigned char POD30:1; + unsigned char POD29:1; + unsigned char POD28:1; + unsigned char POD27:1; + unsigned char POD26:1; + unsigned char POD25:1; + unsigned char POD24:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD23:1; + unsigned char POD22:1; + unsigned char POD21:1; + unsigned char POD20:1; + unsigned char POD19:1; + unsigned char POD18:1; + unsigned char POD17:1; + unsigned char POD16:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR31:1; + unsigned char NDR30:1; + unsigned char NDR29:1; + unsigned char NDR28:1; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR23:1; + unsigned char NDR22:1; + unsigned char NDR21:1; + unsigned char NDR20:1; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL2; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADTE:1; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + unsigned char wk1[1]; + unsigned char TCORA; + unsigned char wk2[1]; + unsigned char TCORB; + unsigned char wk3[1]; + unsigned char TCNT; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + unsigned char wk1[1]; + unsigned char TCORA; + unsigned char wk2[1]; + unsigned char TCORB; + unsigned char wk3[1]; + unsigned char TCNT; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_sci { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ABCS:1; + unsigned char :3; + unsigned char ACS0:1; + } BIT; + } SEMR; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char :1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char :2; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char DORCLR:1; + unsigned char :4; + unsigned char LMS:1; + unsigned char GPS:2; + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + unsigned char :1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char :1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char FMPE:1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char SPEIE:1; + unsigned char MSTR:1; + unsigned char MODFEN:1; + unsigned char TXMD:1; + unsigned char SPMS:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SSLP3:1; + unsigned char SSLP2:1; + unsigned char SSLP1:1; + unsigned char SSLP0:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :1; + unsigned char SPOM:1; + unsigned char SPLP2:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PERF:1; + unsigned char MODF:1; + unsigned char IDLNF:1; + unsigned char OVRF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPSLN:3; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + unsigned char SPCP:3; + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + unsigned char SPR7:1; + unsigned char SPR6:1; + unsigned char SPR5:1; + unsigned char SPR4:1; + unsigned char SPR3:1; + unsigned char SPR2:1; + unsigned char SPR1:1; + unsigned char SPR0:1; + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SPLW:1; + unsigned char SPRDTD:1; + unsigned char SLSEL:2; + unsigned char SPFC:2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PTE:1; + unsigned char SPIIE:1; + unsigned char SPOE:1; + unsigned char SPPE:1; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD7; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE4D:1; + unsigned char OE4C:1; + unsigned char OE3D:1; + unsigned char OE4B:1; + unsigned char OE4A:1; + unsigned char OE3B:1; + } BIT; + } TOER; + unsigned char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BCD:1; + unsigned char N:1; + unsigned char P:1; + unsigned char FB:1; + unsigned char WF:1; + unsigned char VF:1; + unsigned char UF:1; + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2; + unsigned char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + unsigned char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + unsigned char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T3AEN:1; + unsigned char T3ACOR:3; + unsigned char T4VEN:1; + unsigned char T4VCOR:3; + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + unsigned char T4VCNT:3; + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTER; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDRE:1; + } BIT; + } TDER; + unsigned char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBR; + unsigned char wk6[41]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :6; + unsigned char WRE:1; + } BIT; + } TWCR; + unsigned char wk7[31]; + union { + unsigned char BYTE; + struct { + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char :3; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char :3; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; + unsigned char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + unsigned char TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + unsigned char wk0[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TGIEF:1; + unsigned char TGIEE:1; + } BIT; + } TIER2; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; +}; + +struct st_mtu1 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char I2BE:1; + unsigned char I2AE:1; + unsigned char I1BE:1; + unsigned char I1AE:1; + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + unsigned char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + unsigned char wk3[7]; + unsigned short TCNT; + unsigned char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + unsigned char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + unsigned char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; +}; + +struct st_mtu4 { + unsigned char DMMY; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + unsigned char wk1[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + unsigned char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + unsigned char wk3[8]; + unsigned short TCNT; + unsigned char wk4[8]; + unsigned short TGRA; + unsigned short TGRB; + unsigned char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + unsigned char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + unsigned char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT4AE:1; + unsigned short DT4AE:1; + unsigned short UT4BE:1; + unsigned short DT4BE:1; + unsigned short ITA3AE:1; + unsigned short ITA4VE:1; + unsigned short ITB3AE:1; + unsigned short ITB4VE:1; + } BIT; + } TADCR; + unsigned char wk9[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; +}; + +struct st_mtu5 { + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCRU; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORU; + unsigned char wk1[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCRV; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORV; + unsigned char wk2[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCRW; + unsigned char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORW; + unsigned char wk4[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TGIE5U:1; + unsigned char TGIE5V:1; + unsigned char TGIE5W:1; + } BIT; + } TIER; + unsigned char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CSTU5:1; + unsigned char CSTV5:1; + unsigned char CSTW5:1; + } BIT; + } TSTR; + unsigned char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMPCLR5U:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5W:1; + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned short POE3F:1; + unsigned short POE2F:1; + unsigned short POE1F:1; + unsigned short POE0F:1; + unsigned short :3; + unsigned short PIE1:1; + unsigned short POE3M:2; + unsigned short POE2M:2; + unsigned short POE1M:2; + unsigned short POE0M:2; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned short OSF1:1; + unsigned short :5; + unsigned short OCE1:1; + unsigned short OIE1:1; + unsigned short :8; + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + unsigned short POE7F:1; + unsigned short POE6F:1; + unsigned short POE5F:1; + unsigned short POE4F:1; + unsigned short :3; + unsigned short PIE2:1; + unsigned short POE7M:2; + unsigned short POE6M:2; + unsigned short POE5M:2; + unsigned short POE4M:2; + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + unsigned short OSF2:1; + unsigned short :5; + unsigned short OCE2:1; + unsigned short OIE2:1; + unsigned short :8; + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE8F:1; + unsigned short :2; + unsigned short POE8E:1; + unsigned short PIE3:1; + unsigned short :6; + unsigned short POE8M:2; + } BIT; + } ICSR3; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CH6HIZ:1; + unsigned char CH910HIZ:1; + unsigned char CH0HIZ:1; + unsigned char CH34HIZ:1; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char PE7ZE:1; + unsigned char PE6ZE:1; + unsigned char PE5ZE:1; + unsigned char PE4ZE:1; + unsigned char PE3ZE:1; + unsigned char PE2ZE:1; + unsigned char PE1ZE:1; + unsigned char PE0ZE:1; + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short P1CZEA:1; + unsigned short P2CZEA:1; + unsigned short P3CZEA:1; + unsigned short :1; + unsigned short P1CZEB:1; + unsigned short P2CZEB:1; + unsigned short P3CZEB:1; + unsigned short :1; + unsigned short P4CZE:1; + unsigned short P5CZE:1; + unsigned short P6CZE:1; + unsigned short :4; + } BIT; + } POECR2; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE9F:1; + unsigned short :2; + unsigned short POE9E:1; + unsigned short PIE4:1; + unsigned short :6; + unsigned short POE9M:2; + } BIT; + } ICSR4; +}; + +struct st_s12ad { + union { + unsigned char BYTE; + struct { + unsigned char ADST:1; + unsigned char ADCS:1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char CKS:2; + unsigned char TRGE:1; + unsigned char EXTRG:1; + } BIT; + } ADCSR; + unsigned char wk0[3]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANS:8; + } BIT; + } ADANS; + unsigned char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ADS:8; + } BIT; + } ADADS; + unsigned char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char ADC:2; + } BIT; + } ADADC; + unsigned char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :9; + unsigned short ACE:1; + unsigned short :5; + } BIT; + } ADCER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char ADSTRS:4; + } BIT; + } ADSTRGR; + unsigned char wk4[15]; + unsigned short ADDRA; + unsigned short ADDRB; + unsigned short ADDRC; + unsigned short ADDRD; + unsigned short ADDRE; + unsigned short ADDRF; + unsigned short ADDRG; + unsigned short ADDRH; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port6 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port7 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port8 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port9 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; + unsigned char wk4[63]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portf { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_portg { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_ioport { + union { + unsigned char BYTE; + struct { + unsigned char CS7E:1; + unsigned char CS6E:1; + unsigned char CS5E:1; + unsigned char CS4E:1; + unsigned char CS3E:1; + unsigned char CS2E:1; + unsigned char CS1E:1; + unsigned char CS0E:1; + } BIT; + } PF0CSE; + union { + unsigned char BYTE; + struct { + unsigned char CS7S:2; + unsigned char CS6S:2; + unsigned char CS5S:2; + unsigned char CS4S:2; + } BIT; + } PF1CSS; + union { + unsigned char BYTE; + struct { + unsigned char CS3S:2; + unsigned char CS2S:2; + unsigned char CS1S:2; + unsigned char :1; + unsigned char CS0S:1; + } BIT; + } PF2CSS; + union { + unsigned char BYTE; + struct { + unsigned char A23E:1; + unsigned char A22E:1; + unsigned char A21E:1; + unsigned char A20E:1; + unsigned char A19E:1; + unsigned char A18E:1; + unsigned char A17E:1; + unsigned char A16E:1; + } BIT; + } PF3BUS; + union { + unsigned char BYTE; + struct { + unsigned char A15E:1; + unsigned char A14E:1; + unsigned char A13E:1; + unsigned char A12E:1; + unsigned char A11E:1; + unsigned char A10E:1; + unsigned char ADRLE:2; + } BIT; + } PF4BUS; + union { + unsigned char BYTE; + struct { + unsigned char WR32BC32E:1; + unsigned char WR1BC1E:1; + unsigned char DH32E:1; + unsigned char DHE:1; + unsigned char :2; + unsigned char ADRHMS:1; + unsigned char :1; + } BIT; + } PF5BUS; + union { + unsigned char BYTE; + struct { + unsigned char SDCLKE:1; + unsigned char DQM1E:1; + unsigned char :1; + unsigned char MDSDE:1; + unsigned char :2; + unsigned char WAITS:2; + } BIT; + } PF6BUS; + union { + unsigned char BYTE; + struct { + unsigned char EDMA1S:2; + unsigned char EDMA0S:2; + unsigned char :4; + } BIT; + } PF7DMA; + union { + unsigned char BYTE; + struct { + unsigned char ITS15:1; + unsigned char :1; + unsigned char ITS13:1; + unsigned char :1; + unsigned char ITS11:1; + unsigned char ITS10:1; + unsigned char ITS9:1; + unsigned char ITS8:1; + } BIT; + } PF8IRQ; + union { + unsigned char BYTE; + struct { + unsigned char ITS7:1; + unsigned char ITS6:1; + unsigned char ITS5:1; + unsigned char ITS4:1; + unsigned char ITS3:1; + unsigned char ITS2:1; + unsigned char ITS1:1; + unsigned char ITS0:1; + } BIT; + } PF9IRQ; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ADTRG0S:1; + } BIT; + } PFAADC; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char TMR3S:1; + unsigned char TMR2S:1; + unsigned char :2; + } BIT; + } PFBTMR; + union { + unsigned char BYTE; + struct { + unsigned char TCLKS:1; + unsigned char MTUS6:1; + unsigned char MTUS5:1; + unsigned char MTUS4:1; + unsigned char MTUS3:1; + unsigned char MTUS2:1; + unsigned char MTUS1:1; + unsigned char MTUS0:1; + } BIT; + } PFCMTU; + union { + unsigned char BYTE; + struct { + unsigned char TCLKS:1; + unsigned char MTUS6:1; + unsigned char :6; + } BIT; + } PFDMTU; + union { + unsigned char BYTE; + struct { + unsigned char EE:1; + unsigned char :2; + unsigned char PHYMODE:1; + unsigned char ENETE3:1; + unsigned char ENETE2:1; + unsigned char ENETE1:1; + unsigned char ENETE0:1; + } BIT; + } PFENET; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SCI6S:1; + unsigned char :2; + unsigned char SCI3S:1; + unsigned char SCI2S:1; + unsigned char SCI1S:1; + unsigned char :1; + } BIT; + } PFFSCI; + union { + unsigned char BYTE; + struct { + unsigned char SSL3E:1; + unsigned char SSL2E:1; + unsigned char SSL1E:1; + unsigned char SSL0E:1; + unsigned char MISOE:1; + unsigned char MOSIE:1; + unsigned char RSPCKE:1; + unsigned char RSPIS:1; + } BIT; + } PFGSPI; + union { + unsigned char BYTE; + struct { + unsigned char SSL3E:1; + unsigned char SSL2E:1; + unsigned char SSL1E:1; + unsigned char SSL0E:1; + unsigned char MISOE:1; + unsigned char MOSIE:1; + unsigned char RSPCKE:1; + unsigned char RSPIS:1; + } BIT; + } PFHSPI; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CAN0E:1; + } BIT; + } PFJCAN; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char USBE:1; + unsigned char PDHZS:1; + unsigned char PUPHZS:1; + unsigned char USBMD:2; + } BIT; + } PFKUSB; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char USBE:1; + unsigned char PDHZS:1; + unsigned char PUPHZS:1; + unsigned char USBMD:2; + } BIT; + } PFLUSB; + union { + unsigned char BYTE; + struct { + unsigned char POE7E:1; + unsigned char POE6E:1; + unsigned char POE5E:1; + unsigned char POE4E:1; + unsigned char POE3E:1; + unsigned char POE2E:1; + unsigned char POE1E:1; + unsigned char POE0E:1; + } BIT; + } PFMPOE; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char POE9E:1; + unsigned char POE8E:1; + } BIT; + } PFNPOE; +}; + +struct st_flash { + unsigned char DMMY; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char FLWE:2; + } BIT; + } FWEPROR; + unsigned char wk0[7799160]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char FRDMD:1; + unsigned char :4; + } BIT; + } FMODR; + unsigned char wk1[13]; + union { + unsigned char BYTE; + struct { + unsigned char ROMAE:1; + unsigned char :2; + unsigned char CMDLK:1; + unsigned char DFLAE:1; + unsigned char :1; + unsigned char DFLRPE:1; + unsigned char DFLWPE:1; + } BIT; + } FASTAT; + union { + unsigned char BYTE; + struct { + unsigned char ROMAEIE:1; + unsigned char :2; + unsigned char CMDLKIE:1; + unsigned char DFLAEIE:1; + unsigned char :1; + unsigned char DFLRPEIE:1; + unsigned char DFLWPEIE:1; + } BIT; + } FAEINT; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FRDYIE:1; + } BIT; + } FRDYIE; + unsigned char wk2[45]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBRE07:1; + unsigned short DBRE06:1; + unsigned short DBRE05:1; + unsigned short DBRE04:1; + unsigned short DBRE03:1; + unsigned short DBRE02:1; + unsigned short DBRE01:1; + unsigned short DBRE00:1; + } BIT; + } DFLRE0; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBRE15:1; + unsigned short DBRE14:1; + unsigned short DBRE13:1; + unsigned short DBRE12:1; + unsigned short DBRE11:1; + unsigned short DBRE10:1; + unsigned short DBRE09:1; + unsigned short DBRE08:1; + } BIT; + } DFLRE1; + unsigned char wk3[12]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBWE07:1; + unsigned short DBWE06:1; + unsigned short DBWE05:1; + unsigned short DBWE04:1; + unsigned short DBWE03:1; + unsigned short DBWE02:1; + unsigned short DBWE01:1; + unsigned short DBWE00:1; + } BIT; + } DFLWE0; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBWE15:1; + unsigned short DBWE14:1; + unsigned short DBWE13:1; + unsigned short DBWE12:1; + unsigned short DBWE11:1; + unsigned short DBWE10:1; + unsigned short DBWE09:1; + unsigned short DBWE08:1; + } BIT; + } DFLWE1; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :7; + unsigned short FCRME:1; + } BIT; + } FCURAME; + unsigned char wk4[15194]; + union { + unsigned char BYTE; + struct { + unsigned char FRDY:1; + unsigned char ILGLERR:1; + unsigned char ERSERR:1; + unsigned char PRGERR:1; + unsigned char SUSRDY:1; + unsigned char :1; + unsigned char ERSSPD:1; + unsigned char PRGSPD:1; + } BIT; + } FSTATR0; + union { + unsigned char BYTE; + struct { + unsigned char FCUERR:1; + unsigned char :2; + unsigned char FLOCKST:1; + unsigned char :4; + } BIT; + } FSTATR1; + union { + unsigned short WORD; + struct { + unsigned short FEKEY:8; + unsigned short FENTRYD:1; + unsigned short :6; + unsigned short FENTRY0:1; + } BIT; + } FENTRYR; + union { + unsigned short WORD; + struct { + unsigned short FPKEY:8; + unsigned short :7; + unsigned short FPROTCN:1; + } BIT; + } FPROTR; + union { + unsigned short WORD; + struct { + unsigned short FPKEY:8; + unsigned short :7; + unsigned short FRESET:1; + } BIT; + } FRESETR; + unsigned char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short CMDR:8; + unsigned short PCMDR:8; + } BIT; + } FCMDR; + unsigned char wk6[12]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ESUSPMD:1; + } BIT; + } FCPSR; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short BCADR:8; + unsigned short :2; + unsigned short BCSIZE:1; + } BIT; + } DFLBCCNT; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short PEERRST:8; + } BIT; + } FPESTAT; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short BCST:1; + } BIT; + } DFLBCSTAT; + unsigned char wk7[24]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short PCKA:8; + } BIT; + } PCKAR; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char F64HZ:1; + unsigned char F32HZ:1; + unsigned char F16HZ:1; + unsigned char F8HZ:1; + unsigned char F4HZ:1; + unsigned char F2HZ:1; + unsigned char F1HZ:1; + unsigned char :1; + } BIT; + } R64CNT; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCNT; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCNT; + unsigned char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char HOUR10:2; + unsigned char HOUR1:4; + } BIT; + } RHRCNT; + unsigned char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAY:3; + } BIT; + } RWKCNT; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DAY10:2; + unsigned char DAY1:4; + } BIT; + } RDAYCNT; + unsigned char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCNT; + unsigned char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short YEAR1000:4; + unsigned short YEAR100:4; + unsigned short YEAR10:4; + unsigned short YEAR1:4; + } BIT; + } RYRCNT; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECAR; + unsigned char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINAR; + unsigned char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char HOUR10:2; + unsigned char HOUR1:4; + } BIT; + } RHRAR; + unsigned char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :4; + unsigned char DAY:3; + } BIT; + } RWKAR; + unsigned char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char DAY10:2; + unsigned char DAY1:4; + } BIT; + } RDAYAR; + unsigned char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :2; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONAR; + unsigned char wk12[1]; + union { + unsigned short WORD; + struct { + unsigned short YEAR1000:4; + unsigned short YEAR100:4; + unsigned short YEAR10:4; + unsigned short YEAR1:4; + } BIT; + } RYRAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :7; + } BIT; + } RYRAREN; + unsigned char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PES:3; + unsigned char :1; + unsigned char PIE:1; + unsigned char CIE:1; + unsigned char AIE:1; + } BIT; + } RCR1; + unsigned char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RTCOE:1; + unsigned char ADJ:1; + unsigned char RESET:1; + unsigned char START:1; + } BIT; + } RCR2; +}; + +struct st_can { + struct { + union { + unsigned long LONG; + union { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } ID; + union { + unsigned short WORD; + struct { + unsigned char :8; + unsigned char :4; + unsigned char DLC:4; + } BIT; + } DLC; + unsigned char DATA[8]; + union{ + unsigned short WORD; + struct { + unsigned char TSH; + unsigned char TSL; + } BYTE; + } TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long :3; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR1; + unsigned long MKIVLR; + unsigned long MIER; + unsigned char wk32[1008]; + union { + unsigned char BYTE; + union { + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char TRMABT:1; + unsigned char TRMACTIVE:1; + unsigned char SENTDATA:1; + } TX; + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char MSGLOST:1; + unsigned char INVALDATA:1; + unsigned char NEWDATA:1; + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :2; + unsigned char RBOC:1; + unsigned char BOM:2; + unsigned char SLPM:1; + unsigned char CANM:2; + unsigned char TSPS:2; + unsigned char TSRC:1; + unsigned char TPM:1; + unsigned char MLM:1; + unsigned char IDFM:2; + unsigned char MBM:1; + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :1; + unsigned char RECST:1; + unsigned char TRMST:1; + unsigned char BOST:1; + unsigned char EPST:1; + unsigned char SLPST:1; + unsigned char HLTST:1; + unsigned char RSTST:1; + unsigned char EST:1; + unsigned char TABST:1; + unsigned char FMLST:1; + unsigned char NMLST:1; + unsigned char TFST:1; + unsigned char RFST:1; + unsigned char SDST:1; + unsigned char NDST:1; + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long TSEG1:4; + unsigned long :2; + unsigned long BRP:10; + unsigned long :2; + unsigned long SJW:2; + unsigned long :1; + unsigned long TSEG2:3; + unsigned long :8; + } BIT; + } BCR; + union { + unsigned char BYTE; + struct { + unsigned char RFEST:1; + unsigned char RFWST:1; + unsigned char RFFST:1; + unsigned char RFMLF:1; + unsigned char RFUST:3; + unsigned char RFE:1; + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + unsigned char TFEST:1; + unsigned char TFFST:1; + unsigned char :2; + unsigned char TFUST:3; + unsigned char TFE:1; + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + unsigned char BLIE:1; + unsigned char OLIE:1; + unsigned char ORIE:1; + unsigned char BORIE:1; + unsigned char BOEIE:1; + unsigned char EPIE:1; + unsigned char EWIE:1; + unsigned char BEIE:1; + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + unsigned char BLIF:1; + unsigned char OLIF:1; + unsigned char ORIF:1; + unsigned char BORIF:1; + unsigned char BOEIF:1; + unsigned char EPIF:1; + unsigned char EWIF:1; + unsigned char BEIF:1; + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + unsigned char EDPM:1; + unsigned char ADEF:1; + unsigned char BE0F:1; + unsigned char BE1F:1; + unsigned char CEF:1; + unsigned char AEF:1; + unsigned char FEF:1; + unsigned char SEF:1; + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + unsigned char SEST:1; + unsigned char :2; + unsigned char MBNST:5; + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MBSM:2; + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TSTM:2; + unsigned char TSTE:1; + } BIT; + } TCR; +}; + +struct st_usb0 { + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short SCKE:1; + unsigned short :3; + unsigned short DCFM:1; + unsigned short DRPD:1; + unsigned short DPRPU:1; + unsigned short :3; + unsigned short USBE:1; + } BIT; + } SYSCFG; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short OVCMON:2; + unsigned short :7; + unsigned short HTACT:1; + unsigned short :3; + unsigned short IDMON:1; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + unsigned char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short HNPBTOA:1; + unsigned short EXICEN:1; + unsigned short VBUSEN:1; + unsigned short WKUP:1; + unsigned short RWUPE:1; + unsigned short USBRST:1; + unsigned short RESUME:1; + unsigned short UACT:1; + unsigned short :1; + unsigned short RHST:3; + } BIT; + } DVSTCTR0; + unsigned char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + unsigned char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + unsigned char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + unsigned char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short :3; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :2; + unsigned short ISEL:1; + unsigned short :1; + unsigned short CURPIPE:4; + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short TLN:1; + unsigned short DTLN:8; + } BIT; + } CFIFOCTR; + unsigned char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short TLN:1; + unsigned short DTLN:8; + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short TLN:1; + unsigned short DTLN:8; + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short VBSE:1; + unsigned short RSME:1; + unsigned short SOFE:1; + unsigned short DVSE:1; + unsigned short CTRE:1; + unsigned short BEMPE:1; + unsigned short NRDYE:1; + unsigned short BRDYE:1; + unsigned short :8; + } BIT; + } INTENB0; + union { + unsigned short WORD; + struct { + unsigned short OVRCRE:1; + unsigned short BCHGE:1; + unsigned short :1; + unsigned short DTCHE:1; + unsigned short ATTCHE:1; + unsigned short :4; + unsigned short EOFERRE:1; + unsigned short SIGNE:1; + unsigned short SACKE:1; + unsigned short :4; + } BIT; + } INTENB1; + unsigned char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short TRNENSEL:1; + unsigned short :1; + unsigned short BRDYM:1; + unsigned short :1; + unsigned short EDGESTS:1; + unsigned short :4; + } BIT; + } SOFCFG; + unsigned char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short VBINT:1; + unsigned short RESM:1; + unsigned short SOFR:1; + unsigned short DVST:1; + unsigned short CTRT:1; + unsigned short BEMP:1; + unsigned short NRDY:1; + unsigned short BRDY:1; + unsigned short VBSTS:1; + unsigned short DVSQ:3; + unsigned short VALID:1; + unsigned short CTSQ:3; + } BIT; + } INTSTS0; + union { + unsigned short WORD; + struct { + unsigned short OVRCR:1; + unsigned short BCHG:1; + unsigned short :1; + unsigned short DTCH:1; + unsigned short ATTCH:1; + unsigned short :4; + unsigned short EOFERR:1; + unsigned short SIGN:1; + unsigned short SACK:1; + unsigned short :4; + } BIT; + } INTSTS1; + unsigned char wk9[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE0BRDY:1; + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE0BRDY:1; + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BENP:1; + unsigned short PIPE8BENP:1; + unsigned short PIPE7BENP:1; + unsigned short PIPE6BENP:1; + unsigned short PIPE5BENP:1; + unsigned short PIPE4BENP:1; + unsigned short PIPE3BENP:1; + unsigned short PIPE2BENP:1; + unsigned short PIPE1BENP:1; + unsigned short PIPE0BENP:1; + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + unsigned short OVRN:1; + unsigned short CRCE:1; + unsigned short :3; + unsigned short FRNM:11; + } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + unsigned short DVCHG:1; + unsigned short :15; + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short STSRECOV:4; + unsigned short :1; + unsigned short USBADDR:7; + } BIT; + } USBADDR; + unsigned char wk10[2]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short :4; + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :5; + unsigned short MXPS:7; + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short SUREQ:1; + unsigned short :2; + unsigned short SUREQCLR:1; + unsigned short :2; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :2; + unsigned short CCPL:1; + unsigned short PID:2; + } BIT; + } DCPCTR; + unsigned char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short PIPESEL:4; + } BIT; + } PIPESEL; + unsigned char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short TYPE:2; + unsigned short :3; + unsigned short BFRE:1; + unsigned short DBLB:1; + unsigned short :1; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short EPNUM:4; + } BIT; + } PIPECFG; + unsigned char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :3; + unsigned short XPS:1; + unsigned short MXPS:8; + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short IFIS:1; + unsigned short :9; + unsigned short IITV:3; + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE9CTR; + unsigned char wk14[14]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + unsigned char wk15[44]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD2; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD3; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD4; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD5; +}; + +struct st_usb { + union { + unsigned long LONG; + struct { + unsigned long DVSTS1:1; + unsigned long :1; + unsigned long DOVCB1:1; + unsigned long DOVCA1:1; + unsigned long :2; + unsigned long DM1:1; + unsigned long DP1:1; + unsigned long DVBSTS0:1; + unsigned long :1; + unsigned long DOVCB0:1; + unsigned long DOVCA0:1; + unsigned long :2; + unsigned long DM0:1; + unsigned long DP0:1; + unsigned long :3; + unsigned long FIXPHY1:1; + unsigned long :3; + unsigned long SRPC1:1; + unsigned long :3; + unsigned long FIXPHY0:1; + unsigned long :3; + unsigned long SRPC0:1; + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + unsigned long DVBINT1:1; + unsigned long :1; + unsigned long DOVRCRB1:1; + unsigned long DOVRCRA1:1; + unsigned long :2; + unsigned long DMINT1:1; + unsigned long DPINT1:1; + unsigned long DVBINT0:1; + unsigned long :1; + unsigned long DOVRCRB0:1; + unsigned long DOVRCRA0:1; + unsigned long :2; + unsigned long DMINT0:1; + unsigned long DPINT0:1; + unsigned long DVBSE1:1; + unsigned long :1; + unsigned long DOVRCRBE1:1; + unsigned long DOVRCRAE1:1; + unsigned long :2; + unsigned long DMINTE1:1; + unsigned long DPINTE1:1; + unsigned long DVBSE0:1; + unsigned long :1; + unsigned long DOVRCRBE0:1; + unsigned long DOVRCRAE0:1; + unsigned long :2; + unsigned long DMINTE0:1; + unsigned long DPINTE0:1; + } BIT; + } DPUSR1R; +}; + +struct st_edmac { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long DE:1; + unsigned long DL:2; + unsigned long :3; + unsigned long SWR:1; + } BIT; + } EDMR; + unsigned char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TR:1; + } BIT; + } EDTRR; + unsigned char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RR:1; + } BIT; + } EDRRR; + unsigned char wk2[4]; + void *TDLAR; + unsigned char wk3[4]; + void *RDLAR; + unsigned char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWB:1; + unsigned long :3; + unsigned long TABT:1; + unsigned long RABT:1; + unsigned long RFCOF:1; + unsigned long ADE:1; + unsigned long ECI:1; + unsigned long TC:1; + unsigned long TDE:1; + unsigned long TFUF:1; + unsigned long FR:1; + unsigned long RDE:1; + unsigned long RFOF:1; + unsigned long :4; + unsigned long CND:1; + unsigned long DLC:1; + unsigned long CD:1; + unsigned long TRO:1; + unsigned long RMAF:1; + unsigned long :2; + unsigned long RRF:1; + unsigned long RTLF:1; + unsigned long RTSF:1; + unsigned long PRE:1; + unsigned long CERF:1; + } BIT; + } EESR; + unsigned char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWBIP:1; + unsigned long :3; + unsigned long TABTIP:1; + unsigned long RABTIP:1; + unsigned long RFCOFIP:1; + unsigned long ADEIP:1; + unsigned long ECIIP:1; + unsigned long TCIP:1; + unsigned long TDEIP:1; + unsigned long TFUFIP:1; + unsigned long FRIP:1; + unsigned long RDEIP:1; + unsigned long RFOFIP:1; + unsigned long :4; + unsigned long CNDIP:1; + unsigned long DLCIP:1; + unsigned long CDIP:1; + unsigned long TROIP:1; + unsigned long RMAFIP:1; + unsigned long :2; + unsigned long RRFIP:1; + unsigned long RTLFIP:1; + unsigned long RTSFIP:1; + unsigned long PREIP:1; + unsigned long CERFIP:1; + } BIT; + } EESIPR; + unsigned char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :20; + unsigned long CNDCE:1; + unsigned long DLCCE:1; + unsigned long CDCE:1; + unsigned long TROCE:1; + unsigned long RMAFCE:1; + unsigned long :2; + unsigned long RRFCE:1; + unsigned long RTLFCE:1; + unsigned long RTSFCE:1; + unsigned long PRECE:1; + unsigned long CERFCE:1; + } BIT; + } TRSCER; + unsigned char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MFC:16; + } BIT; + } RMFCR; + unsigned char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long TFT:11; + } BIT; + } TFTR; + unsigned char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TFD:5; + unsigned long :3; + unsigned long RFD:5; + } BIT; + } FDR; + unsigned char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long RNC:1; + unsigned long RNR:1; + } BIT; + } RMCR; + unsigned char wk11[8]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long UNDER:16; + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long OVER:16; + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TLB:1; + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + unsigned long RFDO:3; + } BIT; + } FCFTR; + unsigned char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long PADS:2; + unsigned long :10; + unsigned long PADR:6; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long TIM:1; + unsigned long :3; + unsigned long TIS:1; + } BIT; + } TRIMD; + unsigned char wk13[72]; + void *RBWAR; + void *RDFAR; + unsigned char wk14[4]; + void *TBRAR; + void *TDFAR; +}; + +struct st_etherc { + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long TPC:1; + unsigned long ZPE:1; + unsigned long PFR:1; + unsigned long RXF:1; + unsigned long TXF:1; + unsigned long :3; + unsigned long PRCEF:1; + unsigned long :2; + unsigned long MPDE:1; + unsigned long :2; + unsigned long RE:1; + unsigned long TE:1; + unsigned long :1; + unsigned long ILB:1; + unsigned long RTM:1; + unsigned long DM:1; + unsigned long PRM:1; + } BIT; + } ECMR; + unsigned char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :20; + unsigned long RFL:12; + } BIT; + } RFLR; + unsigned char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFR:1; + unsigned long PSRTO:1; + unsigned long :1; + unsigned long LCHNG:1; + unsigned long MPD:1; + unsigned long ICD:1; + } BIT; + } ECSR; + unsigned char wk2[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFSIPR:1; + unsigned long PSRTOIP:1; + unsigned long :1; + unsigned long LCHNGIP:1; + unsigned long MPDIP:1; + unsigned long ICDIP:1; + } BIT; + } ECSIPR; + unsigned char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long MDI:1; + unsigned long MDO:1; + unsigned long MMD:1; + unsigned long MDC:1; + } BIT; + } PIR; + unsigned char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long LMON:1; + } BIT; + } PSR; + unsigned char wk5[20]; + union { + unsigned long LONG; + struct { + unsigned long :12; + unsigned long RMD:20; + } BIT; + } RDMLR; + unsigned char wk6[12]; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long IPG:5; + } BIT; + } IPGR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long AP:16; + } BIT; + } APR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MP:16; + } BIT; + } MPR; + unsigned char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long RPAUSE:8; + } BIT; + } RFCF; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long TPAUSE:16; + } BIT; + } TPAUSER; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long TXP:8; + } BIT; + } TPAUSECR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long BCF:16; + } BIT; + } BCFRR; + unsigned char wk8[80]; + unsigned long MAHR; + unsigned char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MA:16; + } BIT; + } MALR; + unsigned char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + unsigned char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16, +IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMT2_CMI2, +IR_CMT3_CMI3, +IR_ETHER_EINT, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_USB1_D0FIFO1=40,IR_USB1_D1FIFO1,IR_USB1_USBI1, +IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSPI1_SPEI1,IR_RSPI1_SPRI1,IR_RSPI1_SPTI1,IR_RSPI1_SPII1, +IR_CAN0_ERS0=56,IR_CAN0_RXF0,IR_CAN0_TXF0,IR_CAN0_RXM0,IR_CAN0_TXM0, +IR_RTC_PRD=62,IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_USB_USBR0=90,IR_USB_USBR1, +IR_RTC_ALM, +IR_WDT_WOVI=96, +IR_AD0_ADI0=98, +IR_AD1_ADI1, +IR_S12AD_ADI=102, +IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_MTU6_TGIA6,IR_MTU6_TGIB6,IR_MTU6_TGIC6,IR_MTU6_TGID6,IR_MTU6_TCIV6,IR_MTU6_TGIE6,IR_MTU6_TGIF6, +IR_MTU7_TGIA7,IR_MTU7_TGIB7,IR_MTU7_TCIV7,IR_MTU7_TCIU7, +IR_MTU8_TGIA8,IR_MTU8_TGIB8,IR_MTU8_TCIV8,IR_MTU8_TCIU8, +IR_MTU9_TGIA9,IR_MTU9_TGIB9,IR_MTU9_TGIC9,IR_MTU9_TGID9,IR_MTU9_TCIV9, +IR_MTU10_TGIA10,IR_MTU10_TGIB10,IR_MTU10_TGIC10,IR_MTU10_TGID10,IR_MTU10_TCIV10, +IR_MTU11_TGIU11,IR_MTU11_TGIV11,IR_MTU11_TGIW11, +IR_POE_OEI1,IR_POE_OEI2,IR_POE_OEI3,IR_POE_OEI4, +IR_TMR0_CMIA0,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_DMACA_DMAC0I=198,IR_DMACA_DMAC1I,IR_DMACA_DMAC2I,IR_DMACA_DMAC3I, +IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2, +IR_SCI3_ERI3,IR_SCI3_RXI3,IR_SCI3_TXI3,IR_SCI3_TEI3, +IR_SCI5_ERI5=234,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_RIIC0_ICEEI0=246,IR_RIIC0_ICRXI0,IR_RIIC0_ICTXI0,IR_RIIC0_ICTEI0, +IR_RIIC1_ICEEI1,IR_RIIC1_ICRXI1,IR_RIIC1_ICTXI1,IR_RIIC1_ICTEI1 +}; + +enum enum_dtce { +DTCE_BSC_BUSERR=16, +DTCE_FCU_FIFERR=21,DTCE_FCU_FRDYI=23, +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2, +DTCE_CMT3_CMI3, +DTCE_ETHER_EINT, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,DTCE_USB0_USBI0, +DTCE_USB1_D0FIFO1=40,DTCE_USB1_D1FIFO1,DTCE_USB1_USBI1, +DTCE_RSPI0_SPEI0=44,DTCE_RSPI0_SPRI0,DTCE_RSPI0_SPTI0,DTCE_RSPI0_SPII0, +DTCE_RSPI1_SPEI1,DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1,DTCE_RSPI1_SPII1, +DTCE_CAN0_ERS0=56,DTCE_CAN0_RXF0,DTCE_CAN0_TXF0,DTCE_CAN0_RXM0,DTCE_CAN0_TXM0, +DTCE_RTC_PRD=62,DTCE_RTC_CUP, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_USB_USBR0=90,DTCE_USB_USBR1, +DTCE_RTC_ALM, +DTCE_WDT_WOVI=96, +DTCE_AD0_ADI0=98, +DTCE_AD1_ADI1, +DTCE_S12AD_ADI=102, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,DTCE_MTU0_TCIV0,DTCE_MTU0_TGIE0,DTCE_MTU0_TGIF0, +DTCE_MTU1_TGIA1,DTCE_MTU1_TGIB1,DTCE_MTU1_TCIV1,DTCE_MTU1_TCIU1, +DTCE_MTU2_TGIA2,DTCE_MTU2_TGIB2,DTCE_MTU2_TCIV2,DTCE_MTU2_TCIU2, +DTCE_MTU3_TGIA3,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,DTCE_MTU3_TCIV3, +DTCE_MTU4_TGIA4,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_MTU6_TGIA6,DTCE_MTU6_TGIB6,DTCE_MTU6_TGIC6,DTCE_MTU6_TGID6,DTCE_MTU6_TCIV6,DTCE_MTU6_TGIE6,DTCE_MTU6_TGIF6, +DTCE_MTU7_TGIA7,DTCE_MTU7_TGIB7,DTCE_MTU7_TCIV7,DTCE_MTU7_TCIU7, +DTCE_MTU8_TGIA8,DTCE_MTU8_TGIB8,DTCE_MTU8_TCIV8,DTCE_MTU8_TCIU8, +DTCE_MTU9_TGIA9,DTCE_MTU9_TGIB9,DTCE_MTU9_TGIC9,DTCE_MTU9_TGID9,DTCE_MTU9_TCIV9, +DTCE_MTU10_TGIA10,DTCE_MTU10_TGIB10,DTCE_MTU10_TGIC10,DTCE_MTU10_TGID10,DTCE_MTU10_TCIV10, +DTCE_MTU11_TGIU11,DTCE_MTU11_TGIV11,DTCE_MTU11_TGIW11, +DTCE_POE_OEI1,DTCE_POE_OEI2,DTCE_POE_OEI3,DTCE_POE_OEI4, +DTCE_TMR0_CMIA0,DTCE_TMR0_CMIB0,DTCE_TMR0_OVI0, +DTCE_TMR1_CMIA1,DTCE_TMR1_CMIB1,DTCE_TMR1_OVI1, +DTCE_TMR2_CMIA2,DTCE_TMR2_CMIB2,DTCE_TMR2_OVI2, +DTCE_TMR3_CMIA3,DTCE_TMR3_CMIB3,DTCE_TMR3_OVI3, +DTCE_DMACA_DMAC0I=198,DTCE_DMACA_DMAC1I,DTCE_DMACA_DMAC2I,DTCE_DMACA_DMAC3I, +DTCE_EXDMAC_EXDMAC0I,DTCE_EXDMAC_EXDMAC1I, +DTCE_SCI0_ERI0=214,DTCE_SCI0_RXI0,DTCE_SCI0_TXI0,DTCE_SCI0_TEI0, +DTCE_SCI1_ERI1,DTCE_SCI1_RXI1,DTCE_SCI1_TXI1,DTCE_SCI1_TEI1, +DTCE_SCI2_ERI2,DTCE_SCI2_RXI2,DTCE_SCI2_TXI2,DTCE_SCI2_TEI2, +DTCE_SCI3_ERI3,DTCE_SCI3_RXI3,DTCE_SCI3_TXI3,DTCE_SCI3_TEI3, +DTCE_SCI5_ERI5=234,DTCE_SCI5_RXI5,DTCE_SCI5_TXI5,DTCE_SCI5_TEI5, +DTCE_SCI6_ERI6,DTCE_SCI6_RXI6,DTCE_SCI6_TXI6,DTCE_SCI6_TEI6, +DTCE_RIIC0_ICEEI0=246,DTCE_RIIC0_ICRXI0,DTCE_RIIC0_ICTXI0,DTCE_RIIC0_ICTEI0, +DTCE_RIIC1_ICEEI1,DTCE_RIIC1_ICRXI1,DTCE_RIIC1_ICTXI1,DTCE_RIIC1_ICTEI1 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03, +IER_CMT3_CMI3=0x03, +IER_ETHER_EINT=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_USB1_D0FIFO1=0x05,IER_USB1_D1FIFO1=0x05,IER_USB1_USBI1=0x05, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSPI1_SPEI1=0x06,IER_RSPI1_SPRI1=0x06,IER_RSPI1_SPTI1=0x06,IER_RSPI1_SPII1=0x06, +IER_CAN0_ERS0=0x07,IER_CAN0_RXF0=0x07,IER_CAN0_TXF0=0x07,IER_CAN0_RXM0=0x07,IER_CAN0_TXM0=0x07, +IER_RTC_PRD=0x07,IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_USB_USBR0=0x0B,IER_USB_USBR1=0x0B, +IER_RTC_ALM=0x0B, +IER_WDT_WOVI=0x0C, +IER_AD0_ADI0=0x0C, +IER_AD1_ADI1=0x0C, +IER_S12AD_ADI=0x0C, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x10, +IER_MTU6_TGIA6=0x11,IER_MTU6_TGIB6=0x11,IER_MTU6_TGIC6=0x12,IER_MTU6_TGID6=0x12,IER_MTU6_TCIV6=0x12,IER_MTU6_TGIE6=0x12,IER_MTU6_TGIF6=0x12, +IER_MTU7_TGIA7=0x12,IER_MTU7_TGIB7=0x12,IER_MTU7_TCIV7=0x12,IER_MTU7_TCIU7=0x13, +IER_MTU8_TGIA8=0x13,IER_MTU8_TGIB8=0x13,IER_MTU8_TCIV8=0x13,IER_MTU8_TCIU8=0x13, +IER_MTU9_TGIA9=0x13,IER_MTU9_TGIB9=0x13,IER_MTU9_TGIC9=0x13,IER_MTU9_TGID9=0x14,IER_MTU9_TCIV9=0x14, +IER_MTU10_TGIA10=0x14,IER_MTU10_TGIB10=0x14,IER_MTU10_TGIC10=0x14,IER_MTU10_TGID10=0x14,IER_MTU10_TCIV10=0x14, +IER_MTU11_TGIU11=0x14,IER_MTU11_TGIV11=0x15,IER_MTU11_TGIW11=0x15, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,IER_POE_OEI3=0x15,IER_POE_OEI4=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_DMACA_DMAC0I=0x18,IER_DMACA_DMAC1I=0x18,IER_DMACA_DMAC2I=0x19,IER_DMACA_DMAC3I=0x19, +IER_EXDMAC_EXDMAC0I=0x19,IER_EXDMAC_EXDMAC1I=0x19, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI2_ERI2=0x1B,IER_SCI2_RXI2=0x1B,IER_SCI2_TXI2=0x1C,IER_SCI2_TEI2=0x1C, +IER_SCI3_ERI3=0x1C,IER_SCI3_RXI3=0x1C,IER_SCI3_TXI3=0x1C,IER_SCI3_TEI3=0x1C, +IER_SCI5_ERI5=0x1D,IER_SCI5_RXI5=0x1D,IER_SCI5_TXI5=0x1D,IER_SCI5_TEI5=0x1D, +IER_SCI6_ERI6=0x1D,IER_SCI6_RXI6=0x1D,IER_SCI6_TXI6=0x1E,IER_SCI6_TEI6=0x1E, +IER_RIIC0_ICEEI0=0x1E,IER_RIIC0_ICRXI0=0x1E,IER_RIIC0_ICTXI0=0x1F,IER_RIIC0_ICTEI0=0x1F, +IER_RIIC1_ICEEI1=0x1F,IER_RIIC1_ICRXI1=0x1F,IER_RIIC1_ICTXI1=0x1F,IER_RIIC1_ICTEI1=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0x00, +IPR_FCU_FIFERR=0x01,IPR_FCU_FRDYI=0x02, +IPR_ICU_SWINT=0x03, +IPR_CMT0_CMI0=0x04, +IPR_CMT1_CMI1=0x05, +IPR_CMT2_CMI2=0x06, +IPR_CMT3_CMI3=0x07, +IPR_ETHER_EINT=0x08, +IPR_USB0_D0FIFO0=0x0C,IPR_USB0_D1FIFO0=0x0D,IPR_USB0_USBI0=0x0E, +IPR_USB1_D0FIFO1=0x10,IPR_USB1_D1FIFO1=0x11,IPR_USB1_USBI1=0x12, +IPR_RSPI0_SPEI0=0x14,IPR_RSPI0_SPRI0=0x14,IPR_RSPI0_SPTI0=0x14,IPR_RSPI0_SPII0=0x14, +IPR_RSPI1_SPEI1=0x15,IPR_RSPI1_SPRI1=0x15,IPR_RSPI1_SPTI1=0x15,IPR_RSPI1_SPII1=0x15, +IPR_CAN0_ERS0=0x18,IPR_CAN0_RXF0=0x18,IPR_CAN0_TXF0=0x18,IPR_CAN0_RXM0=0x18,IPR_CAN0_TXM0=0x18, +IPR_RTC_PRD=0x1E,IPR_RTC_CUP=0x1F, +IPR_ICU_IRQ0=0x20,IPR_ICU_IRQ1=0x21,IPR_ICU_IRQ2=0x22,IPR_ICU_IRQ3=0x23,IPR_ICU_IRQ4=0x24,IPR_ICU_IRQ5=0x25,IPR_ICU_IRQ6=0x26,IPR_ICU_IRQ7=0x27,IPR_ICU_IRQ8=0x28,IPR_ICU_IRQ9=0x29,IPR_ICU_IRQ10=0x2A,IPR_ICU_IRQ11=0x2B,IPR_ICU_IRQ12=0x2C,IPR_ICU_IRQ13=0x2D,IPR_ICU_IRQ14=0x2E,IPR_ICU_IRQ15=0x2F, +IPR_USB_USBR0=0x3A,IPR_USB_USBR1=0x3B, +IPR_RTC_ALM=0x3C, +IPR_WDT_WOVI=0x40, +IPR_AD0_ADI0=0x44, +IPR_AD1_ADI1=0x45, +IPR_S12AD_ADI=0x48, +IPR_MTU0_TGIA0=0x51,IPR_MTU0_TGIB0=0x51,IPR_MTU0_TGIC0=0x51,IPR_MTU0_TGID0=0x51,IPR_MTU0_TCIV0=0x52,IPR_MTU0_TGIE0=0x52,IPR_MTU0_TGIF0=0x52, +IPR_MTU1_TGIA1=0x53,IPR_MTU1_TGIB1=0x53,IPR_MTU1_TCIV1=0x54,IPR_MTU1_TCIU1=0x54, +IPR_MTU2_TGIA2=0x55,IPR_MTU2_TGIB2=0x55,IPR_MTU2_TCIV2=0x56,IPR_MTU2_TCIU2=0x56, +IPR_MTU3_TGIA3=0x57,IPR_MTU3_TGIB3=0x57,IPR_MTU3_TGIC3=0x57,IPR_MTU3_TGID3=0x57,IPR_MTU3_TCIV3=0x58, +IPR_MTU4_TGIA4=0x59,IPR_MTU4_TGIB4=0x59,IPR_MTU4_TGIC4=0x59,IPR_MTU4_TGID4=0x59,IPR_MTU4_TCIV4=0x5A, +IPR_MTU5_TGIU5=0x5B,IPR_MTU5_TGIV5=0x5B,IPR_MTU5_TGIW5=0x5B, +IPR_MTU6_TGIA6=0x5C,IPR_MTU6_TGIB6=0x5C,IPR_MTU6_TGIC6=0x5C,IPR_MTU6_TGID6=0x5C,IPR_MTU6_TCIV6=0x5D,IPR_MTU6_TGIE6=0x5D,IPR_MTU6_TGIF6=0x5D, +IPR_MTU7_TGIA7=0x5E,IPR_MTU7_TGIB7=0x5E,IPR_MTU7_TCIV7=0x5F,IPR_MTU7_TCIU7=0x5F, +IPR_MTU8_TGIA8=0x60,IPR_MTU8_TGIB8=0x60,IPR_MTU8_TCIV8=0x61,IPR_MTU8_TCIU8=0x61, +IPR_MTU9_TGIA9=0x62,IPR_MTU9_TGIB9=0x62,IPR_MTU9_TGIC9=0x62,IPR_MTU9_TGID9=0x62,IPR_MTU9_TCIV9=0x63, +IPR_MTU10_TGIA10=0x64,IPR_MTU10_TGIB10=0x64,IPR_MTU10_TGIC10=0x64,IPR_MTU10_TGID10=0x64,IPR_MTU10_TCIV10=0x65, +IPR_MTU11_TGIU11=0x66,IPR_MTU11_TGIV11=0x66,IPR_MTU11_TGIW11=0x66, +IPR_POE_OEI1=0x67,IPR_POE_OEI2=0x67,IPR_POE_OEI3=0x67,IPR_POE_OEI4=0x67, +IPR_TMR0_CMIA0=0x68,IPR_TMR0_CMIB0=0x68,IPR_TMR0_OVI0=0x68, +IPR_TMR1_CMIA1=0x69,IPR_TMR1_CMIB1=0x69,IPR_TMR1_OVI1=0x69, +IPR_TMR2_CMIA2=0x6A,IPR_TMR2_CMIB2=0x6A,IPR_TMR2_OVI2=0x6A, +IPR_TMR3_CMIA3=0x6B,IPR_TMR3_CMIB3=0x6B,IPR_TMR3_OVI3=0x6B, +IPR_DMACA_DMAC0I=0x70,IPR_DMACA_DMAC1I=0x71,IPR_DMACA_DMAC2I=0x72,IPR_DMACA_DMAC3I=0x73, +IPR_EXDMAC_EXDMAC0I=0x74,IPR_EXDMAC_EXDMAC1I=0x75, +IPR_SCI0_ERI0=0x80,IPR_SCI0_RXI0=0x80,IPR_SCI0_TXI0=0x80,IPR_SCI0_TEI0=0x80, +IPR_SCI1_ERI1=0x81,IPR_SCI1_RXI1=0x81,IPR_SCI1_TXI1=0x81,IPR_SCI1_TEI1=0x81, +IPR_SCI2_ERI2=0x82,IPR_SCI2_RXI2=0x82,IPR_SCI2_TXI2=0x82,IPR_SCI2_TEI2=0x82, +IPR_SCI3_ERI3=0x83,IPR_SCI3_RXI3=0x83,IPR_SCI3_TXI3=0x83,IPR_SCI3_TEI3=0x83, +IPR_SCI5_ERI5=0x85,IPR_SCI5_RXI5=0x85,IPR_SCI5_TXI5=0x85,IPR_SCI5_TEI5=0x85, +IPR_SCI6_ERI6=0x86,IPR_SCI6_RXI6=0x86,IPR_SCI6_TXI6=0x86,IPR_SCI6_TEI6=0x86, +IPR_RIIC0_ICEEI0=0x88,IPR_RIIC0_ICRXI0=0x89,IPR_RIIC0_ICTXI0=0x8A,IPR_RIIC0_ICTEI0=0x8B, +IPR_RIIC1_ICEEI1=0x8C,IPR_RIIC1_ICRXI1=0x8D,IPR_RIIC1_ICTXI1=0x8E,IPR_RIIC1_ICTEI1=0x8F, +IPR_BSC_=0x00, +IPR_CMT0_=0x04, +IPR_CMT1_=0x05, +IPR_CMT2_=0x06, +IPR_CMT3_=0x07, +IPR_ETHER_=0x08, +IPR_RSPI0_=0x14, +IPR_RSPI1_=0x15, +IPR_CAN0_=0x18, +IPR_WDT_=0x40, +IPR_AD0_=0x44, +IPR_AD1_=0x45, +IPR_S12AD_=0x48, +IPR_MTU1_TGI=0x53, +IPR_MTU1_TCI=0x54, +IPR_MTU2_TGI=0x55, +IPR_MTU2_TCI=0x56, +IPR_MTU3_TGI=0x57, +IPR_MTU4_TGI=0x59, +IPR_MTU5_=0x5B, +IPR_MTU5_TGI=0x5B, +IPR_MTU7_TGI=0x5E, +IPR_MTU7_TCI=0x5F, +IPR_MTU8_TGI=0x60, +IPR_MTU8_TCI=0x61, +IPR_MTU9_TGI=0x62, +IPR_MTU10_TGI=0x64, +IPR_MTU11_=0x66, +IPR_MTU11_TGI=0x66, +IPR_POE_=0x67, +IPR_POE_OEI=0x67, +IPR_TMR0_=0x68, +IPR_TMR1_=0x69, +IPR_TMR2_=0x6A, +IPR_TMR3_=0x6B, +IPR_SCI0_=0x80, +IPR_SCI1_=0x81, +IPR_SCI2_=0x82, +IPR_SCI3_=0x83, +IPR_SCI5_=0x85, +IPR_SCI6_=0x86 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_ETHER_EINT IEN0 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_USB1_D0FIFO1 IEN0 +#define IEN_USB1_D1FIFO1 IEN1 +#define IEN_USB1_USBI1 IEN2 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_RSPI1_SPEI1 IEN0 +#define IEN_RSPI1_SPRI1 IEN1 +#define IEN_RSPI1_SPTI1 IEN2 +#define IEN_RSPI1_SPII1 IEN3 +#define IEN_CAN0_ERS0 IEN0 +#define IEN_CAN0_RXF0 IEN1 +#define IEN_CAN0_TXF0 IEN2 +#define IEN_CAN0_RXM0 IEN3 +#define IEN_CAN0_TXM0 IEN4 +#define IEN_RTC_PRD IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_USB_USBR0 IEN2 +#define IEN_USB_USBR1 IEN3 +#define IEN_RTC_ALM IEN4 +#define IEN_WDT_WOVI IEN0 +#define IEN_AD0_ADI0 IEN2 +#define IEN_AD1_ADI1 IEN3 +#define IEN_S12AD_ADI IEN6 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN7 +#define IEN_MTU6_TGIA6 IEN6 +#define IEN_MTU6_TGIB6 IEN7 +#define IEN_MTU6_TGIC6 IEN0 +#define IEN_MTU6_TGID6 IEN1 +#define IEN_MTU6_TCIV6 IEN2 +#define IEN_MTU6_TGIE6 IEN3 +#define IEN_MTU6_TGIF6 IEN4 +#define IEN_MTU7_TGIA7 IEN5 +#define IEN_MTU7_TGIB7 IEN6 +#define IEN_MTU7_TCIV7 IEN7 +#define IEN_MTU7_TCIU7 IEN0 +#define IEN_MTU8_TGIA8 IEN1 +#define IEN_MTU8_TGIB8 IEN2 +#define IEN_MTU8_TCIV8 IEN3 +#define IEN_MTU8_TCIU8 IEN4 +#define IEN_MTU9_TGIA9 IEN5 +#define IEN_MTU9_TGIB9 IEN6 +#define IEN_MTU9_TGIC9 IEN7 +#define IEN_MTU9_TGID9 IEN0 +#define IEN_MTU9_TCIV9 IEN1 +#define IEN_MTU10_TGIA10 IEN2 +#define IEN_MTU10_TGIB10 IEN3 +#define IEN_MTU10_TGIC10 IEN4 +#define IEN_MTU10_TGID10 IEN5 +#define IEN_MTU10_TCIV10 IEN6 +#define IEN_MTU11_TGIU11 IEN7 +#define IEN_MTU11_TGIV11 IEN0 +#define IEN_MTU11_TGIW11 IEN1 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_POE_OEI3 IEN4 +#define IEN_POE_OEI4 IEN5 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_DMACA_DMAC0I IEN6 +#define IEN_DMACA_DMAC1I IEN7 +#define IEN_DMACA_DMAC2I IEN0 +#define IEN_DMACA_DMAC3I IEN1 +#define IEN_EXDMAC_EXDMAC0I IEN2 +#define IEN_EXDMAC_EXDMAC1I IEN3 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI2_ERI2 IEN6 +#define IEN_SCI2_RXI2 IEN7 +#define IEN_SCI2_TXI2 IEN0 +#define IEN_SCI2_TEI2 IEN1 +#define IEN_SCI3_ERI3 IEN2 +#define IEN_SCI3_RXI3 IEN3 +#define IEN_SCI3_TXI3 IEN4 +#define IEN_SCI3_TEI3 IEN5 +#define IEN_SCI5_ERI5 IEN2 +#define IEN_SCI5_RXI5 IEN3 +#define IEN_SCI5_TXI5 IEN4 +#define IEN_SCI5_TEI5 IEN5 +#define IEN_SCI6_ERI6 IEN6 +#define IEN_SCI6_RXI6 IEN7 +#define IEN_SCI6_TXI6 IEN0 +#define IEN_SCI6_TEI6 IEN1 +#define IEN_RIIC0_ICEEI0 IEN6 +#define IEN_RIIC0_ICRXI0 IEN7 +#define IEN_RIIC0_ICTXI0 IEN0 +#define IEN_RIIC0_ICTEI0 IEN1 +#define IEN_RIIC1_ICEEI1 IEN2 +#define IEN_RIIC1_ICRXI1 IEN3 +#define IEN_RIIC1_ICTXI1 IEN4 +#define IEN_RIIC1_ICTEI1 IEN5 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_ETHER_EINT 32 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_USB1_D0FIFO1 40 +#define VECT_USB1_D1FIFO1 41 +#define VECT_USB1_USBI1 42 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_RSPI1_SPEI1 48 +#define VECT_RSPI1_SPRI1 49 +#define VECT_RSPI1_SPTI1 50 +#define VECT_RSPI1_SPII1 51 +#define VECT_CAN0_ERS0 56 +#define VECT_CAN0_RXF0 57 +#define VECT_CAN0_TXF0 58 +#define VECT_CAN0_RXM0 59 +#define VECT_CAN0_TXM0 60 +#define VECT_RTC_PRD 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_USB_USBR0 90 +#define VECT_USB_USBR1 91 +#define VECT_RTC_ALM 92 +#define VECT_WDT_WOVI 96 +#define VECT_AD0_ADI0 98 +#define VECT_AD1_ADI1 99 +#define VECT_S12AD_ADI 102 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_MTU6_TGIA6 142 +#define VECT_MTU6_TGIB6 143 +#define VECT_MTU6_TGIC6 144 +#define VECT_MTU6_TGID6 145 +#define VECT_MTU6_TCIV6 146 +#define VECT_MTU6_TGIE6 147 +#define VECT_MTU6_TGIF6 148 +#define VECT_MTU7_TGIA7 149 +#define VECT_MTU7_TGIB7 150 +#define VECT_MTU7_TCIV7 151 +#define VECT_MTU7_TCIU7 152 +#define VECT_MTU8_TGIA8 153 +#define VECT_MTU8_TGIB8 154 +#define VECT_MTU8_TCIV8 155 +#define VECT_MTU8_TCIU8 156 +#define VECT_MTU9_TGIA9 157 +#define VECT_MTU9_TGIB9 158 +#define VECT_MTU9_TGIC9 159 +#define VECT_MTU9_TGID9 160 +#define VECT_MTU9_TCIV9 161 +#define VECT_MTU10_TGIA10 162 +#define VECT_MTU10_TGIB10 163 +#define VECT_MTU10_TGIC10 164 +#define VECT_MTU10_TGID10 165 +#define VECT_MTU10_TCIV10 166 +#define VECT_MTU11_TGIU11 167 +#define VECT_MTU11_TGIV11 168 +#define VECT_MTU11_TGIW11 169 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_POE_OEI3 172 +#define VECT_POE_OEI4 173 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_DMACA_DMAC0I 198 +#define VECT_DMACA_DMAC1I 199 +#define VECT_DMACA_DMAC2I 200 +#define VECT_DMACA_DMAC3I 201 +#define VECT_EXDMAC_EXDMAC0I 202 +#define VECT_EXDMAC_EXDMAC1I 203 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI2_ERI2 222 +#define VECT_SCI2_RXI2 223 +#define VECT_SCI2_TXI2 224 +#define VECT_SCI2_TEI2 225 +#define VECT_SCI3_ERI3 226 +#define VECT_SCI3_RXI3 227 +#define VECT_SCI3_TXI3 228 +#define VECT_SCI3_TEI3 229 +#define VECT_SCI5_ERI5 234 +#define VECT_SCI5_RXI5 235 +#define VECT_SCI5_TXI5 236 +#define VECT_SCI5_TEI5 237 +#define VECT_SCI6_ERI6 238 +#define VECT_SCI6_RXI6 239 +#define VECT_SCI6_TXI6 240 +#define VECT_SCI6_TEI6 241 +#define VECT_RIIC0_ICEEI0 246 +#define VECT_RIIC0_ICRXI0 247 +#define VECT_RIIC0_ICTXI0 248 +#define VECT_RIIC0_ICTEI0 249 +#define VECT_RIIC1_ICEEI1 250 +#define VECT_RIIC1_ICRXI1 251 +#define VECT_RIIC1_ICTXI1 252 +#define VECT_RIIC1_ICTEI1 253 + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMACA SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_AD0 SYSTEM.MSTPCRA.BIT.MSTPA23 +#define MSTP_AD1 SYSTEM.MSTPCRA.BIT.MSTPA22 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTUA SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTUB SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU9 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU10 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU11 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_USB1 SYSTEM.MSTPCRB.BIT.MSTPB18 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_EDMAC SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC1 +#define MSTP_RAM1 SYSTEM.MSTPCRC.BIT.MSTPC0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define BSC (*(volatile struct st_bsc *)0x81300) +#define DMAC0 (*(volatile struct st_dmac0 *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 *)0x820C0) +#define DMAC (*(volatile struct st_dmac *)0x82200) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define EXDMAC0 (*(volatile struct st_exdmac0 *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac0 *)0x82840) +#define EXDMAC (*(volatile struct st_exdmac *)0x82A00) +#define ICU (*(volatile struct st_icu *)0x87000) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define WDT (*(volatile union un_wdt *)0x88028) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define AD0 (*(volatile struct st_ad *)0x88040) +#define AD1 (*(volatile struct st_ad *)0x88060) +#define DA (*(volatile struct st_da *)0x880C0) +#define PPG0 (*(volatile struct st_ppg0 *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 *)0x881F0) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define SCI0 (*(volatile struct st_sci *)0x88240) +#define SCI1 (*(volatile struct st_sci *)0x88248) +#define SCI2 (*(volatile struct st_sci *)0x88250) +#define SCI3 (*(volatile struct st_sci *)0x88258) +#define SCI5 (*(volatile struct st_sci *)0x88268) +#define SCI6 (*(volatile struct st_sci *)0x88270) +#define SMCI0 (*(volatile struct st_smci *)0x88240) +#define SMCI1 (*(volatile struct st_smci *)0x88248) +#define SMCI2 (*(volatile struct st_smci *)0x88250) +#define SMCI3 (*(volatile struct st_smci *)0x88258) +#define SMCI5 (*(volatile struct st_smci *)0x88268) +#define SMCI6 (*(volatile struct st_smci *)0x88270) +#define CRC (*(volatile struct st_crc *)0x88280) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RIIC1 (*(volatile struct st_riic *)0x88320) +#define RSPI0 (*(volatile struct st_rspi *)0x88380) +#define RSPI1 (*(volatile struct st_rspi *)0x883A0) +#define MTUA (*(volatile struct st_mtu *)0x8860A) +#define MTU0 (*(volatile struct st_mtu0 *)0x88700) +#define MTU1 (*(volatile struct st_mtu1 *)0x88780) +#define MTU2 (*(volatile struct st_mtu2 *)0x88800) +#define MTU3 (*(volatile struct st_mtu3 *)0x88600) +#define MTU4 (*(volatile struct st_mtu4 *)0x88600) +#define MTU5 (*(volatile struct st_mtu5 *)0x88880) +#define POE (*(volatile struct st_poe *)0x88900) +#define MTUB (*(volatile struct st_mtu *)0x88A0A) +#define MTU6 (*(volatile struct st_mtu0 *)0x88B00) +#define MTU7 (*(volatile struct st_mtu1 *)0x88B80) +#define MTU8 (*(volatile struct st_mtu2 *)0x88C00) +#define MTU9 (*(volatile struct st_mtu3 *)0x88A00) +#define MTU10 (*(volatile struct st_mtu4 *)0x88A00) +#define MTU11 (*(volatile struct st_mtu5 *)0x88C80) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORT6 (*(volatile struct st_port6 *)0x8C006) +#define PORT7 (*(volatile struct st_port7 *)0x8C007) +#define PORT8 (*(volatile struct st_port8 *)0x8C008) +#define PORT9 (*(volatile struct st_port9 *)0x8C009) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTF (*(volatile struct st_portf *)0x8C00F) +#define PORTG (*(volatile struct st_portg *)0x8C010) +#define IOPORT (*(volatile struct st_ioport *)0x8C100) +#define FLASH (*(volatile struct st_flash *)0x8C288) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define CAN0 (*(volatile struct st_can *)0x90200) +#define USB0 (*(volatile struct st_usb0 *)0xA0000) +#define USB1 (*(volatile struct st_usb0 *)0xA0200) +#define USB (*(volatile struct st_usb *)0xA0400) +#define EDMAC (*(volatile struct st_edmac *)0xC0000) +#define ETHERC (*(volatile struct st_etherc *)0xC0100) + +#endif /*endian*/ + +#endif /*IODEFINE_H*/ diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/typedefine.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/typedefine.h new file mode 100644 index 000000000..49b303a56 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/typedefine.h @@ -0,0 +1,23 @@ +/***********************************************************************/ +/* */ +/* FILE :typedefine.h */ +/* DATE :Wed, Aug 25, 2010 */ +/* DESCRIPTION :Aliases of Integer Type */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by KPIT GNU Project Generator. */ +/* */ +/***********************************************************************/ + + + +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQWORD; +typedef unsigned long long _UQWORD; diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/yrdkrx62ndef.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/yrdkrx62ndef.h new file mode 100644 index 000000000..29a1acee7 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/include/yrdkrx62ndef.h @@ -0,0 +1,104 @@ + +/****************************************************************************** +* DISCLAIMER +* Please refer to http://www.renesas.com/disclaimer +****************************************************************************** + Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved. +******************************************************************************* +* File Name : rsksh7216.h +* Version : 1.00 +* Description : RSK 7216 board specific settings +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.10.2009 1.00 First Release +******************************************************************************/ + +#ifndef RDKRX62N_H +#define RDKRX62N_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/* System Clock Settings */ +#define XTAL_FREQUENCY (12000000L) +#define ICLK_MUL (8) +#define PCLK_MUL (4) +#define BCLK_MUL (4) +#define ICLK_FREQUENCY (XTAL_FREQUENCY * ICLK_MUL) +#define PCLK_FREQUENCY (XTAL_FREQUENCY * PCLK_MUL) +#define BCLK_FREQUENCY (XTAL_FREQUENCY * BCLK_MUL) + +#define CMT0_CLK_SELECT (512) + +/* General Values */ +#define LED_ON (1) +#define LED_OFF (0) +#define SET_BIT_HIGH (1) +#define SET_BIT_LOW (0) +#define SET_BYTE_HIGH (0xFF) +#define SET_BYTE_LOW (0x00) + +/* Define switches to be polled if not available as interrupts */ +#define SW_ACTIVE FALSE +#define SW1 PORT4.PORT.BIT.B0 +#define SW2 PORT4.PORT.BIT.B1 +#define SW3 PORT4.PORT.BIT.B2 +#define SW1_DDR PORT4.DDR.BIT.B0 +#define SW2_DDR PORT4.DDR.BIT.B1 +#define SW3_DDR PORT4.DDR.BIT.B2 +#define SW1_ICR PORT4.ICR.BIT.B0 +#define SW2_ICR PORT4.ICR.BIT.B1 +#define SW3_ICR PORT4.ICR.BIT.B2 + +/* LEDs */ +#define LED4 PORTD.DR.BIT.B5 +#define LED5 PORTE.DR.BIT.B3 +#define LED6 PORTD.DR.BIT.B2 +#define LED7 PORTE.DR.BIT.B0 +#define LED8 PORTD.DR.BIT.B4 +#define LED9 PORTE.DR.BIT.B2 +#define LED10 PORTD.DR.BIT.B1 +#define LED11 PORTD.DR.BIT.B7 +#define LED12 PORTD.DR.BIT.B3 +#define LED13 PORTE.DR.BIT.B1 +#define LED14 PORTD.DR.BIT.B0 +#define LED15 PORTD.DR.BIT.B6 + +#define LED4_DDR PORTD.DDR.BIT.B5 +#define LED5_DDR PORTE.DDR.BIT.B3 +#define LED6_DDR PORTD.DDR.BIT.B2 +#define LED7_DDR PORTE.DDR.BIT.B0 +#define LED8_DDR PORTD.DDR.BIT.B4 +#define LED9_DDR PORTE.DDR.BIT.B2 +#define LED10_DDR PORTD.DDR.BIT.B1 +#define LED11_DDR PORTD.DDR.BIT.B7 +#define LED12_DDR PORTD.DDR.BIT.B3 +#define LED13_DDR PORTE.DDR.BIT.B1 +#define LED14_DDR PORTD.DDR.BIT.B0 +#define LED15_DDR PORTD.DDR.BIT.B6 + + + + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + + + +/* RDKRX62N_H */ +#endif + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/main-blinky.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/main-blinky.c new file mode 100644 index 000000000..fc5c05d35 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/main-blinky.c @@ -0,0 +1,227 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * This is a very simple demo that creates two tasks and one queue. One task + * (the queue receive task) blocks on the queue to wait for data to arrive, + * toggling an LED each time '100' is received. The other task (the queue send + * task) repeatedly blocks for a fixed period before sending '100' to the queue + * (causing the first task to toggle the LED). + * + * For a much more complete and complex example select either the Debug or + * Debug_with_optimisation build configurations within the HEW IDE. +*/ + +/* Hardware specific includes. */ +#include "iodefine.h" + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Priorities at which the tasks are created. */ +#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue, specified in milliseconds. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 500 / portTICK_RATE_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added so the send task should always find the +queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* + * The tasks as defined at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/* The queue used by both tasks. */ +static xQueueHandle xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main(void) +{ +extern void HardwareSetup( void ); + + /* Renesas provided CPU configuration routine. The clocks are configured in + here. */ + HardwareSetup(); + + /* Turn all LEDs off. */ + vParTestInitialise(); + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described at the top of this file. */ + xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL ); + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks running. */ + vTaskStartScheduler(); + } + + /* If all is well we will never reach here as the scheduler will now be + running. If we do reach here then it is likely that there was insufficient + heap available for the idle task to be created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +portTickType xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. + The block state is specified in ticks, the constant used converts ticks + to ms. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to flash its LED. 0 + is used so the send does not block - it shouldn't need to as the queue + should always be empty here. */ + xQueueSend( xQueue, &ulValueToSend, 0 ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; + + for( ;; ) + { + /* Wait until something arives in the queue - this will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have arrived, but is it the expected + value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + vParTestToggleLED( 0 ); + } + } +} +/*-----------------------------------------------------------*/ + +void vApplicationSetupTimerInterrupt( void ) +{ + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationMallocFailedHook( void ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationIdleHook( void ) +{ +} +/*-----------------------------------------------------------*/ + +/* The following four functions are here just to allow all three build +configurations to use the same vector table. They are not used in this +demo, but linker errors will result if they are not defined. They can +be ignored. */ +void vT0_1_ISR_Wrapper( void ) {} +void vT2_3_ISR_Wrapper( void ) {} +void vEMAC_ISR_Wrapper( void ) {} +void vTimer2_ISR_Wrapper( void ) {} +volatile unsigned long ulHighFrequencyTickCount = 0; \ No newline at end of file diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/main-full.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/main-full.c new file mode 100644 index 000000000..3a4e74cde --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/main-full.c @@ -0,0 +1,671 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* **************************************************************************** + * This project includes a lot of tasks and tests and is therefore complex. + * If you would prefer a much simpler project to get started with then select + * the 'Blinky' build configuration within the HEW IDE. + * **************************************************************************** + * + * Creates all the demo application tasks, then starts the scheduler. The web + * documentation provides more details of the standard demo application tasks, + * which provide no particular functionality but do provide a good example of + * how to use the FreeRTOS API. The tasks defined in flop.c are included in the + * set of standard demo tasks to ensure the floating point unit gets some + * exercise. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * Webserver ("uIP") task - This serves a number of dynamically generated WEB + * pages to a standard WEB browser. The IP and MAC addresses are configured by + * constants defined at the bottom of FreeRTOSConfig.h. Use either a standard + * Ethernet cable to connect through a hug, or a cross over (point to point) + * cable to connect directly. Ensure the IP address used is compatible with the + * IP address of the machine running the browser - the easiest way to achieve + * this is to ensure the first three octets of the IP addresses are the same. + * + * "Reg test" tasks - These fill the registers with known values, then check + * that each register still contains its expected value. Each task uses + * different values. The tasks run with very low priority so get preempted + * very frequently. A check variable is incremented on each iteration of the + * test loop. A register containing an unexpected value is indicative of an + * error in the context switching mechanism and will result in a branch to a + * null loop - which in turn will prevent the check variable from incrementing + * any further and allow the check task (described below) to determine that an + * error has occurred. The nature of the reg test tasks necessitates that they + * are written in assembly code. + * + * "Check" task - This only executes every five seconds but has a high priority + * to ensure it gets processor time. Its main function is to check that all the + * standard demo tasks are still operational. While no errors have been + * discovered the check task will toggle LED 5 every 5 seconds - the toggle + * rate increasing to 200ms being a visual indication that at least one task has + * reported unexpected behaviour. + * + * "High frequency timer test" - A high frequency periodic interrupt is + * generated using a timer - the interrupt is assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY so should not be effected by anything + * the kernel is doing. The frequency and priority of the interrupt, in + * combination with other standard tests executed in this demo, should result + * in interrupts nesting at least 3 and probably 4 deep. This test is only + * included in build configurations that have the optimiser switched on. In + * optimised builds the count of high frequency ticks is used as the time base + * for the run time stats. + * + * *NOTE 1* If LED5 is toggling every 5 seconds then all the demo application + * tasks are executing as expected and no errors have been reported in any + * tasks. The toggle rate increasing to 200ms indicates that at least one task + * has reported unexpected behaviour. + * + * *NOTE 2* vApplicationSetupTimerInterrupt() is called by the kernel to let + * the application set up a timer to generate the tick interrupt. In this + * example a compare match timer is used for this purpose. + * + * *NOTE 3* The CPU must be in Supervisor mode when the scheduler is started. + * The PowerON_Reset_PC() supplied in resetprg.c with this demo has + * Change_PSW_PM_to_UserMode() commented out to ensure this is the case. + * + * *NOTE 4* The IntQueue common demo tasks test interrupt nesting and make use + * of all the 8bit timers (as two cascaded 16bit units). +*/ + +/* Hardware specific includes. */ +#include "iodefine.h" + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard demo includes. */ +#include "partest.h" +#include "flash.h" +#include "IntQueue.h" +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "semtest.h" +#include "PollQ.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "recmutex.h" +#include "flop.h" + +/* Values that are passed into the reg test tasks using the task parameter. The +tasks check that the values are passed in correctly. */ +#define mainREG_TEST_1_PARAMETER ( 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( 0x12345678UL ) + +/* Priorities at which the tasks are created. */ +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainuIP_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The WEB server uses string handling functions, which in turn use a bit more +stack than most of the other tasks. */ +#define mainuIP_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3 ) + +/* The LED toggled by the check task. */ +#define mainCHECK_LED ( 5 ) + +/* The rate at which mainCHECK_LED will toggle when all the tasks are running +without error. Controlled by the check task as described at the top of this +file. */ +#define mainNO_ERROR_CYCLE_TIME ( 5000 / portTICK_RATE_MS ) + +/* The rate at which mainCHECK_LED will toggle when an error has been reported +by at least one task. Controlled by the check task as described at the top of +this file. */ +#define mainERROR_CYCLE_TIME ( 200 / portTICK_RATE_MS ) + + +/* + * vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will execute if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue or + * semaphore is created. It is also called by various parts of the demo + * application. + */ +void vApplicationMallocFailedHook( void ); + +/* + * vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set to 1 + * in FreeRTOSConfig.h. It is a hook function that is called on each iteration + * of the idle task. It is essential that code added to this hook function + * never attempts to block in any way (for example, call xQueueReceive() with + * a block time specified). If the application makes use of the vTaskDelete() + * API function (as this demo application does) then it is also important that + * vApplicationIdleHook() is permitted to return to its calling function because + * it is the responsibility of the idle task to clean up memory allocated by the + * kernel to any task that has since been deleted. + */ +void vApplicationIdleHook( void ); + +/* + * vApplicationStackOverflowHook() will only be called if + * configCHECK_FOR_STACK_OVERFLOW is set to a non-zero value. The handle and + * name of the offending task should be passed in the function parameters, but + * it is possible that the stack overflow will have corrupted these - in which + * case pxCurrentTCB can be inspected to find the same information. + */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ); + +/* + * The reg test tasks as described at the top of this file. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); + +/* + * The actual implementation of the reg test functionality, which, because of + * the direct register access, have to be in assembly. + */ +static void prvRegTest1Implementation( void ) __attribute__((naked)); +static void prvRegTest2Implementation( void ) __attribute__((naked)); + + +/* + * The check task as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Contains the implementation of the WEB server. + */ +extern void vuIP_Task( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Variables that are incremented on each iteration of the reg test tasks - +provided the tasks have not reported any errors. The check task inspects these +variables to ensure they are still incrementing as expected. If a variable +stops incrementing then it is likely that its associate task has stalled. */ +unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL; + +/* The status message that is displayed at the bottom of the "task stats" web +page, which is served by the uIP task. This will report any errors picked up +by the reg test task. */ +static const char *pcStatusMessage = NULL; + +/*-----------------------------------------------------------*/ + +void main(void) +{ +extern void HardwareSetup( void ); + + /* Renesas provided CPU configuration routine. The clocks are configured in + here. */ + HardwareSetup(); + + /* Turn all LEDs off. */ + vParTestInitialise(); + + /* Start the reg test tasks which test the context switching mechanism. */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* The web server task. */ + xTaskCreate( vuIP_Task, "uIP", mainuIP_STACK_SIZE, NULL, mainuIP_TASK_PRIORITY, NULL ); + + /* Start the check task as described at the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Create the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vStartInterruptQueueTasks(); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the tasks running. */ + vTaskStartScheduler(); + + /* If all is well we will never reach here as the scheduler will now be + running. If we do reach here then it is likely that there was insufficient + heap available for the idle task to be created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL; +portTickType xNextWakeTime, xCycleFrequency = mainNO_ERROR_CYCLE_TIME; +extern void vSetupHighFrequencyTimer( void ); + + /* If this is being executed then the kernel has been started. Start the high + frequency timer test as described at the top of this file. This is only + included in the optimised build configuration - otherwise it takes up too much + CPU time. */ + #ifdef INCLUDE_HIGH_FREQUENCY_TIMER_TEST + vSetupHighFrequencyTimer(); + #endif + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, xCycleFrequency ); + + /* Check the standard demo tasks are running without error. */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: GenQueue"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: QueuePeek\r\n"; + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: BlockQueue\r\n"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: BlockTime\r\n"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: SemTest\r\n"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: PollQueue\r\n"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: Death\r\n"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: IntMath\r\n"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: RecMutex\r\n"; + } + else if( xAreIntQueueTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: IntQueue\r\n"; + } + else if( xAreMathsTaskStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Flop\r\n"; + } + + /* Check the reg test tasks are still cycling. They will stop incrementing + their loop counters if they encounter an error. */ + if( ulRegTest1CycleCount == ulLastRegTest1CycleCount ) + { + pcStatusMessage = "Error: RegTest1\r\n"; + } + + if( ulRegTest2CycleCount == ulLastRegTest2CycleCount ) + { + pcStatusMessage = "Error: RegTest2\r\n"; + } + + ulLastRegTest1CycleCount = ulRegTest1CycleCount; + ulLastRegTest2CycleCount = ulRegTest2CycleCount; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every 5 seconds then everything is ok. A faster toggle + indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + /* Ensure the LED toggles at a faster rate if an error has occurred. */ + if( pcStatusMessage != NULL ) + { + /* Increase the rate at which this task cycles, which will increase the + rate at which mainCHECK_LED flashes to give visual feedback that an error + has occurred. */ + xCycleFrequency = mainERROR_CYCLE_TIME; + } + } +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationMallocFailedHook( void ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationIdleHook( void ) +{ +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +char *pcGetTaskStatusMessage( void ) +{ + /* Not bothered about a critical section here although technically because of + the task priorities the pointer could change it will be atomic if not near + atomic and its not critical. */ + if( pcStatusMessage == NULL ) + { + return "All tasks running without error"; + } + else + { + return ( char * ) pcStatusMessage; + } +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Implementation( void ) +{ + __asm volatile + ( + /* Put a known value in each register. */ + "MOV #1, R1 \n" \ + "MOV #2, R2 \n" \ + "MOV #3, R3 \n" \ + "MOV #4, R4 \n" \ + "MOV #5, R5 \n" \ + "MOV #6, R6 \n" \ + "MOV #7, R7 \n" \ + "MOV #8, R8 \n" \ + "MOV #9, R9 \n" \ + "MOV #10, R10 \n" \ + "MOV #11, R11 \n" \ + "MOV #12, R12 \n" \ + "MOV #13, R13 \n" \ + "MOV #14, R14 \n" \ + "MOV #15, R15 \n" \ + + /* Loop, checking each itteration that each register still contains the + expected value. */ + "TestLoop1: \n" \ + + /* Push the registers that are going to get clobbered. */ + "PUSHM R14-R15 \n" \ + + /* Increment the loop counter to show this task is still getting CPU time. */ + "MOV #_ulRegTest1CycleCount, R14 \n" \ + "MOV [ R14 ], R15 \n" \ + "ADD #1, R15 \n" \ + "MOV R15, [ R14 ] \n" \ + + /* Yield to extend the test coverage. Set the bit in the ITU SWINTR register. */ + "MOV #1, R14 \n" \ + "MOV #0872E0H, R15 \n" \ + "MOV.B R14, [R15] \n" \ + "NOP \n" \ + "NOP \n" \ + + /* Restore the clobbered registers. */ + "POPM R14-R15 \n" \ + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + "CMP #1, R1 \n" \ + "BNE RegTest1Error \n" \ + "CMP #2, R2 \n" \ + "BNE RegTest1Error \n" \ + "CMP #3, R3 \n" \ + "BNE RegTest1Error \n" \ + "CMP #4, R4 \n" \ + "BNE RegTest1Error \n" \ + "CMP #5, R5 \n" \ + "BNE RegTest1Error \n" \ + "CMP #6, R6 \n" \ + "BNE RegTest1Error \n" \ + "CMP #7, R7 \n" \ + "BNE RegTest1Error \n" \ + "CMP #8, R8 \n" \ + "BNE RegTest1Error \n" \ + "CMP #9, R9 \n" \ + "BNE RegTest1Error \n" \ + "CMP #10, R10 \n" \ + "BNE RegTest1Error \n" \ + "CMP #11, R11 \n" \ + "BNE RegTest1Error \n" \ + "CMP #12, R12 \n" \ + "BNE RegTest1Error \n" \ + "CMP #13, R13 \n" \ + "BNE RegTest1Error \n" \ + "CMP #14, R14 \n" \ + "BNE RegTest1Error \n" \ + "CMP #15, R15 \n" \ + "BNE RegTest1Error \n" \ + + /* All comparisons passed, start a new itteratio of this loop. */ + "BRA TestLoop1 \n" \ + + "RegTest1Error: \n" \ + /* A compare failed, just loop here so the loop counter stops incrementing + - causing the check task to indicate the error. */ + "BRA RegTest1Error " + ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Implementation( void ) +{ + __asm volatile + ( + /* Put a known value in each register. */ + "MOV #10H, R1 \n" \ + "MOV #20H, R2 \n" \ + "MOV #30H, R3 \n" \ + "MOV #40H, R4 \n" \ + "MOV #50H, R5 \n" \ + "MOV #60H, R6 \n" \ + "MOV #70H, R7 \n" \ + "MOV #80H, R8 \n" \ + "MOV #90H, R9 \n" \ + "MOV #100H, R10 \n" \ + "MOV #110H, R11 \n" \ + "MOV #120H, R12 \n" \ + "MOV #130H, R13 \n" \ + "MOV #140H, R14 \n" \ + "MOV #150H, R15 \n" \ + + /* Loop, checking each itteration that each register still contains the + expected value. */ + "TestLoop2: \n" \ + + /* Push the registers that are going to get clobbered. */ + "PUSHM R14-R15 \n" \ + + /* Increment the loop counter to show this task is still getting CPU time. */ + "MOV #_ulRegTest2CycleCount, R14 \n" \ + "MOV [ R14 ], R15 \n" \ + "ADD #1, R15 \n" \ + "MOV R15, [ R14 ] \n" \ + + /* Restore the clobbered registers. */ + "POPM R14-R15 \n" \ + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + "CMP #10H, R1 \n" \ + "BNE RegTest2Error \n" \ + "CMP #20H, R2 \n" \ + "BNE RegTest2Error \n" \ + "CMP #30H, R3 \n" \ + "BNE RegTest2Error \n" \ + "CMP #40H, R4 \n" \ + "BNE RegTest2Error \n" \ + "CMP #50H, R5 \n" \ + "BNE RegTest2Error \n" \ + "CMP #60H, R6 \n" \ + "BNE RegTest2Error \n" \ + "CMP #70H, R7 \n" \ + "BNE RegTest2Error \n" \ + "CMP #80H, R8 \n" \ + "BNE RegTest2Error \n" \ + "CMP #90H, R9 \n" \ + "BNE RegTest2Error \n" \ + "CMP #100H, R10 \n" \ + "BNE RegTest2Error \n" \ + "CMP #110H, R11 \n" \ + "BNE RegTest2Error \n" \ + "CMP #120H, R12 \n" \ + "BNE RegTest2Error \n" \ + "CMP #130H, R13 \n" \ + "BNE RegTest2Error \n" \ + "CMP #140H, R14 \n" \ + "BNE RegTest2Error \n" \ + "CMP #150H, R15 \n" \ + "BNE RegTest2Error \n" \ + + /* All comparisons passed, start a new itteratio of this loop. */ + "BRA TestLoop2 \n" \ + + "RegTest2Error: \n" \ + /* A compare failed, just loop here so the loop counter stops incrementing + - causing the check task to indicate the error. */ + "BRA RegTest2Error " + ); +} + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/uIP_Task.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/uIP_Task.c new file mode 100644 index 000000000..8a1ad0e3b --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/uIP_Task.c @@ -0,0 +1,270 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* uip includes. */ +#include "net/uip.h" +#include "net/uip_arp.h" +#include "apps/httpd/httpd.h" +#include "sys/timer.h" +#include "net/clock-arch.h" +#include "r_ether.h" + +/* Demo includes. */ +#include "ParTest.h" + +/*-----------------------------------------------------------*/ + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT ( 100 / portTICK_RATE_MS ) + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/*-----------------------------------------------------------*/ + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Port functions required by the uIP stack. + */ +void clock_init( void ); +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used by the ISR to wake the uIP task. */ +xSemaphoreHandle xEMACSemaphore = NULL; + +/*-----------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} +/*-----------------------------------------------------------*/ + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i, xDoneSomething; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; + + ( void ) pvParameters; + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( &xIPAddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 ); + uip_sethostaddr( &xIPAddr ); + uip_ipaddr( &xIPAddr, configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 ); + uip_setnetmask( &xIPAddr ); + prvSetMACAddress(); + httpd_init(); + + /* Create the semaphore used to wake the uIP task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Initialise the MAC. */ + vInitEmac(); + + while( lEMACWaitForLink() != pdPASS ) + { + vTaskDelay( uipINIT_WAIT ); + } + + for( ;; ) + { + xDoneSomething = pdFALSE; + + /* Is there received data ready to be processed? */ + uip_len = ( unsigned short ) ulEMACRead(); + + if( ( uip_len > 0 ) && ( uip_buf != NULL ) ) + { + /* Standard uIP loop taken from the uIP manual. */ + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + vEMACWrite(); + } + + xDoneSomething = pdTRUE; + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + vEMACWrite(); + } + + xDoneSomething = pdTRUE; + } + } + + if( timer_expired( &periodic_timer ) && ( uip_buf != NULL ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + vEMACWrite(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + + xDoneSomething = pdTRUE; + } + + if( xDoneSomething == pdFALSE ) + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 20 ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +struct uip_eth_addr xAddr; + + /* Configure the MAC address in the uIP stack. */ + xAddr.addr[ 0 ] = configMAC_ADDR0; + xAddr.addr[ 1 ] = configMAC_ADDR1; + xAddr.addr[ 2 ] = configMAC_ADDR2; + xAddr.addr[ 3 ] = configMAC_ADDR3; + xAddr.addr[ 4 ] = configMAC_ADDR4; + xAddr.addr[ 5 ] = configMAC_ADDR5; + uip_setethaddr( xAddr ); +} +/*-----------------------------------------------------------*/ + +void vApplicationProcessFormInput( char *pcInputString ) +{ +char *c; + + /* Process the form input sent by the IO page of the served HTML. */ + + c = strstr( pcInputString, "?" ); + if( c ) + { + /* Turn the LED's on or off in accordance with the check box status. */ + if( strstr( c, "LED0=1" ) != NULL ) + { + /* Turn LEDs on. */ + vParTestSetLED( 7, 1 ); + vParTestSetLED( 8, 1 ); + vParTestSetLED( 9, 1 ); + vParTestSetLED( 10, 1 ); + } + else + { + /* Turn LED 4 off. */ + vParTestSetLED( 7, 0 ); + vParTestSetLED( 8, 0 ); + vParTestSetLED( 9, 0 ); + vParTestSetLED( 10, 0 ); + } + } +} + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/vects.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/vects.c new file mode 100644 index 000000000..7e9b6b1a0 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/vects.c @@ -0,0 +1,614 @@ +/***********************************************************************/ +/* */ +/* FILE :vects.c */ +/* DATE :Wed, Aug 25, 2010 */ +/* DESCRIPTION :Vector Table */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by KPIT GNU Project Generator. */ +/* */ +/***********************************************************************/ + + + + +#include "inthandler.h" + +typedef void (*fp) (void); +extern void start(void); +extern void stack (void); +extern void vTickISR( void ); +extern void vSoftwareInterruptISR( void ); +extern void vT0_1_ISR_Wrapper( void ); +extern void vT2_3_ISR_Wrapper( void ); +extern void vEMAC_ISR_Wrapper( void ); +extern void vTimer2_ISR_Wrapper( void ); + +#define FVECT_SECT __attribute__ ((section (".fvectors"))) + +const fp HardwareVectors[] FVECT_SECT = { +//;0xffffff80 Reserved + (fp)0, +//;0xffffff84 Reserved + (fp)0, +//;0xffffff88 Reserved + (fp)0, +//;0xffffff8C Reserved + (fp)0, +//;0xffffff90 Reserved + (fp)0, +//;0xffffff94 Reserved + (fp)0, +//;0xffffff98 Reserved + (fp)0, +//;0xffffff9C Reserved + (fp)0, +//;0xffffffA0 Reserved + (fp)0, +//;0xffffffA4 Reserved + (fp)0, +//;0xffffffA8 Reserved + (fp)0, +//;0xffffffAC Reserved + (fp)0, +//;0xffffffB0 Reserved + (fp)0, +//;0xffffffB4 Reserved + (fp)0, +//;0xffffffB8 Reserved + (fp)0, +//;0xffffffBC Reserved + (fp)0, +//;0xffffffC0 Reserved + (fp)0, +//;0xffffffC4 Reserved + (fp)0, +//;0xffffffC8 Reserved + (fp)0, +//;0xffffffCC Reserved + (fp)0, +//;0xffffffd0 Exception(Supervisor Instruction) + INT_Excep_SuperVisorInst, +//;0xffffffd4 Reserved + (fp)0, +//;0xffffffd8 Reserved + (fp)0, +//;0xffffffdc Exception(Undefined Instruction) + INT_Excep_UndefinedInst, +//;0xffffffe0 Reserved + (fp)0, +//;0xffffffe4 Exception(Floating Point) + INT_Excep_FloatingPoint, +//;0xffffffe8 Reserved + (fp)0, +//;0xffffffec Reserved + (fp)0, +//;0xfffffff0 Reserved + (fp)0, +//;0xfffffff4 Reserved + (fp)0, +//;0xfffffff8 NMI + INT_NonMaskableInterrupt, +//;0xfffffffc RESET +//;<> +//;Power On Reset PC + start +//;<> +}; + +#define RVECT_SECT __attribute__ ((section (".rvectors"))) + +const fp RelocatableVectors[] RVECT_SECT = { +//;0x0000 Reserved + (fp)0, +//;0x0004 Reserved + (fp)0, +//;0x0008 Reserved + (fp)0, +//;0x000C Reserved + (fp)0, +//;0x0010 Reserved + (fp)0, +//;0x0014 Reserved + (fp)0, +//;0x0018 Reserved + (fp)0, +//;0x001C Reserved + (fp)0, +//;0x0020 Reserved + (fp)0, +//;0x0024 Reserved + (fp)0, +//;0x0028 Reserved + (fp)0, +//;0x002C Reserved + (fp)0, +//;0x0030 Reserved + (fp)0, +//;0x0034 Reserved + (fp)0, +//;0x0038 Reserved + (fp)0, +//;0x003C Reserved + (fp)0, +//;0x0040 BUSERR + (fp)INT_Excep_BUSERR, +//;0x0044 Reserved + (fp)0, +//;0x0048 Reserved + (fp)0, +//;0x004C Reserved + (fp)0, +//;0x0050 Reserved + (fp)0, +//;0x0054 FCUERR + (fp)INT_Excep_FCU_FCUERR, +//;0x0058 Reserved + (fp)0, +//;0x005C FRDYI + (fp)INT_Excep_FCU_FRDYI, +//;0x0060 Reserved + (fp)0, +//;0x0064 Reserved + (fp)0, +//;0x0068 Reserved + (fp)0, +//;0x006C Reserved + (fp)vSoftwareInterruptISR, +//;0x0070 CMTU0_CMT0 + (fp)vTickISR, +//;0x0074 CMTU0_CMT1 + (fp)INT_Excep_CMTU0_CMT1, +//;0x0078 CMTU1_CMT2 + (fp)vTimer2_ISR_Wrapper, +//;0x007C CMTU1_CMT3 + (fp)INT_Excep_CMTU1_CMT3, +//;0x0080 Ether + (fp)vEMAC_ISR_Wrapper, +//;0x0084 Reserved + (fp)0, +//;0x0088 Reserved + (fp)0, +//;0x008C Reserved + (fp)0, +//;0x0090 Reserved + (fp)0, +//;0x0094 Reserved + (fp)0, +//;0x0098 Reserved + (fp)0, +//;0x009C Reserved + (fp)0, +//;0x00A0 Reserved + (fp)0, +//;0x00A4 Reserved + (fp)0, +//;0x00A8 Reserved + (fp)0, +//;0x00AC Reserved + (fp)0, +//;0x00B0 Reserved + (fp)0, +//;0x00B4 Reserved + (fp)0, +//;0x00B8 Reserved + (fp)0, +//;0x00BC Reserved + (fp)0, +//;0x00C0 Reserved + (fp)0, +//;0x00C4 Reserved + (fp)0, +//;0x00C8 Reserved + (fp)0, +//;0x00CC Reserved + (fp)0, +//;0x00D0 Reserved + (fp)0, +//;0x00D4 Reserved + (fp)0, +//;0x00D8 Reserved + (fp)0, +//;0x00DC Reserved + (fp)0, +//;0x00E0 Reserved + (fp)0, +//;0x00E4 Reserved + (fp)0, +//;0x00E8 Reserved + (fp)0, +//;0x00EC Reserved + (fp)0, +//;0x00F0 Reserved + (fp)0, +//;0x00F4 Reserved + (fp)0, +//;0x00F8 Reserved + (fp)0, +//;0x00FC Reserved + (fp)0, +//;0x0100 IRQ0 + (fp)INT_Excep_IRQ0, +//;0x0104 IRQ1 + (fp)INT_Excep_IRQ1, +//;0x0108 IRQ2 + (fp)INT_Excep_IRQ2, +//;0x010C IRQ3 + (fp)INT_Excep_IRQ3, +//;0x0110 IRQ4 + (fp)INT_Excep_IRQ4, +//;0x0114 IRQ5 + (fp)INT_Excep_IRQ5, +//;0x0118 IRQ6 + (fp)INT_Excep_IRQ6, +//;0x011C IRQ7 + (fp)INT_Excep_IRQ7, +//;0x0120 IRQ8 + (fp)INT_Excep_IRQ8, +//;0x0124 IRQ9 + (fp)INT_Excep_IRQ9, +//;0x0128 IRQ10 + (fp)INT_Excep_IRQ10, +//;0x012C IRQ11 + (fp)INT_Excep_IRQ11, +//;0x0130 IRQ12 + (fp)INT_Excep_IRQ12, +//;0x0134 IRQ13 + (fp)INT_Excep_IRQ13, +//;0x0138 IRQ14 + (fp)INT_Excep_IRQ14, +//;0x013C IRQ15 + (fp)INT_Excep_IRQ15, +//;0x0140 Reserved + (fp)0, +//;0x0144 Reserved + (fp)0, +//;0x0148 Reserved + (fp)0, +//;0x014C Reserved + (fp)0, +//;0x0150 Reserved + (fp)0, +//;0x0154 Reserved + (fp)0, +//;0x0158 Reserved + (fp)0, +//;0x015C Reserved + (fp)0, +//;0x0160 Reserved + (fp)0, +//;0x0164 Reserved + (fp)0, +//;0x0168 Reserved + (fp)0, +//;0x016C Reserved + (fp)0, +//;0x0170 Reserved + (fp)0, +//;0x0174 Reserved + (fp)0, +//;0x0178 Reserved + (fp)0, +//;0x017C Reserved + (fp)0, +//;0x0180 WDT_WOVI + (fp)INT_Excep_WDT_WOVI, +//;0x0184 Reserved + (fp)0, +//;0x0188 AD0_ADI0 + (fp)INT_Excep_AD0_ADI0, +//;0x018C AD1_ADI1 + (fp)INT_Excep_AD1_ADI1, +//;0x0190 AD2_ADI2 + (fp)INT_Excep_AD2_ADI2, +//;0x0194 AD3_ADI3 + (fp)INT_Excep_AD3_ADI3, +//;0x0198 Reserved + (fp)0, +//;0x019C Reserved + (fp)0, +//;0x01A0 TPU0_TGI0A + (fp)INT_Excep_TPU0_TGI0A, +//;0x01A4 TPU0_TGI0B + (fp)INT_Excep_TPU0_TGI0B, +//;0x01A8 TPU0_TGI0C + (fp)INT_Excep_TPU0_TGI0C, +//;0x01AC TPU0_TGI0D + (fp)INT_Excep_TPU0_TGI0D, +//;0x01B0 TPU0_TCI0V + (fp)INT_Excep_TPU0_TCI0V, +//;0x01B4 Reserved + (fp)0, +//;0x01B8 Reserved + (fp)0, +//;0x01BC TPU1_TGI1A + (fp)INT_Excep_TPU1_TGI1A, +//;0x01C0 TPU1_TGI1B + (fp)INT_Excep_TPU1_TGI1B, +//;0x01C4 Reserved + (fp)0, +//;0x01C8 Reserved + (fp)0, +//;0x01CC TPU1_TCI1V + (fp)INT_Excep_TPU1_TCI1V, +//;0x01D0 TPU1_TCI1U + (fp)INT_Excep_TPU1_TCI1U, +//;0x01D4 TPU2_TGI2A + (fp)INT_Excep_TPU2_TGI2A, +//;0x01D8 TPU2_TGI2B + (fp)INT_Excep_TPU2_TGI2B, +//;0x01DC Reserved + (fp)0, +//;0x01E0 TPU2_TCI2V + (fp)INT_Excep_TPU2_TCI2V, +//;0x01E4 TPU2_TCI2U + (fp)INT_Excep_TPU2_TCI2U, +//;0x01E8 TPU3_TGI3A + (fp)INT_Excep_TPU3_TGI3A, +//;0x01EC TPU3_TGI3B + (fp)INT_Excep_TPU3_TGI3B, +//;0x01F0 TPU3_TGI3C + (fp)INT_Excep_TPU3_TGI3C, +//;0x01F4 TPU3_TGI3D + (fp)INT_Excep_TPU3_TGI3D, +//;0x01F8 TPU3_TCI3V + (fp)INT_Excep_TPU3_TCI3V, +//;0x01FC TPU4_TGI4A + (fp)INT_Excep_TPU4_TGI4A, +//;0x0200 TPU4_TGI4B + (fp)INT_Excep_TPU4_TGI4B, +//;0x0204 Reserved + (fp)0, +//;0x0208 Reserved + (fp)0, +//;0x020C TPU4_TCI4V + (fp)INT_Excep_TPU4_TCI4V, +//;0x0210 TPU4_TCI4U + (fp)INT_Excep_TPU4_TCI4U, +//;0x0214 TPU5_TGI5A + (fp)INT_Excep_TPU5_TGI5A, +//;0x0218 TPU5_TGI5B + (fp)INT_Excep_TPU5_TGI5B, +//;0x021C Reserved + (fp)0, +//;0x0220 TPU5_TCI5V + (fp)INT_Excep_TPU5_TCI5V, +//;0x0224 TPU5_TCI5U + (fp)INT_Excep_TPU5_TCI5U, +//;0x0228 TPU6_TGI6A + (fp)INT_Excep_TPU6_TGI6A, +//;0x022C TPU6_TGI6B + (fp)INT_Excep_TPU6_TGI6B, +//;0x0230 TPU6_TGI6C + (fp)INT_Excep_TPU6_TGI6C, +//;0x0234 TPU6_TGI6D + (fp)INT_Excep_TPU6_TGI6D, +//;0x0238 TPU6_TCI6V + (fp)INT_Excep_TPU6_TCI6V, +//;0x023C Reserved + (fp)0, +//;0x0240 Reserved + (fp)0, +//;0x0244 TPU7_TGI7A + (fp)INT_Excep_TPU7_TGI7A, +//;0x0248 TPU7_TGI7B + (fp)INT_Excep_TPU7_TGI7B, +//;0x024C Reserved + (fp)0, +//;0x0250 Reserved + (fp)0, +//;0x0254 TPU7_TCI7V + (fp)INT_Excep_TPU7_TCI7V, +//;0x0258 TPU7_TCI7U + (fp)INT_Excep_TPU7_TCI7U, +//;0x025C TPU8_TGI8A + (fp)INT_Excep_TPU8_TGI8A, +//;0x0260 TPU8_TGI8B + (fp)INT_Excep_TPU8_TGI8B, +//;0x0264 Reserved + (fp)0, +//;0x0268 TPU8_TCI8V + (fp)INT_Excep_TPU8_TCI8V, +//;0x026C TPU8_TCI8U + (fp)INT_Excep_TPU8_TCI8U, +//;0x0270 TPU9_TGI9A + (fp)INT_Excep_TPU9_TGI9A, +//;0x0274 TPU9_TGI9B + (fp)INT_Excep_TPU9_TGI9B, +//;0x0278 TPU9_TGI9C + (fp)INT_Excep_TPU9_TGI9C, +//;0x027C TPU9_TGI9D + (fp)INT_Excep_TPU9_TGI9D, +//;0x0280 TPU9_TCI9V + (fp)INT_Excep_TPU9_TCI9V, +//;0x0284 TPU10_TGI10A + (fp)INT_Excep_TPU10_TGI10A, +//;0x0288 TPU10_TGI10B + (fp)INT_Excep_TPU10_TGI10B, +//;0x028C Reserved + (fp)0, +//;0x0290 Reserved + (fp)0, +//;0x0294 TPU10_TCI10V + (fp)INT_Excep_TPU10_TCI10V, +//;0x0298 TPU10_TCI10U + (fp)INT_Excep_TPU10_TCI10U, +//;0x029C TPU11_TGI11A + (fp)INT_Excep_TPU11_TGI11A, +//;0x02A0 TPU11_TGI11B + (fp)INT_Excep_TPU11_TGI11B, +//;0x02A4 Reserved + (fp)0, +//;0x02A8 TPU11_TCI11V + (fp)INT_Excep_TPU11_TCI11V, +//;0x02AC TPU11_TCI11U + (fp)INT_Excep_TPU11_TCI11U, +//;0x02B0 Reserved + (fp)0, +//;0x02B4 Reserved + (fp)0, +//;0x02B8 TMR0_CMI0A + (fp)vT0_1_ISR_Wrapper, +//;0x02BC TMR0_CMI0B + (fp)INT_Excep_TMR0_CMI0B, +//;0x02C0 TMR0_OV0I + (fp)INT_Excep_TMR0_OV0I, +//;0x02C4 TMR1_CMI1A + (fp)INT_Excep_TMR1_CMI1A, +//;0x02C8 TMR1_CMI1B + (fp)INT_Excep_TMR1_CMI1B, +//;0x02CC TMR1_OV1I + (fp)INT_Excep_TMR1_OV1I, +//;0x02D0 TMR2_CMI2A + (fp)vT2_3_ISR_Wrapper, +//;0x02D4 TMR2_CMI2B + (fp)INT_Excep_TMR2_CMI2B, +//;0x02D8 TMR2_OV2I + (fp)INT_Excep_TMR2_OV2I, +//;0x02DC TMR3_CMI3A + (fp)INT_Excep_TMR3_CMI3A, +//;0x02E0 TMR3_CMI3B + (fp)INT_Excep_TMR3_CMI3B, +//;0x02E4 TMR3_OV3I + (fp)INT_Excep_TMR3_OV3I, +//;0x02E8 Reserved + (fp)0, +//;0x02EC Reserved + (fp)0, +//;0x02F0 Reserved + (fp)0, +//;0x02F4 Reserved + (fp)0, +//;0x02F8 Reserved + (fp)0, +//;0x02FC Reserved + (fp)0, +//;0x0300 Reserved + (fp)0, +//;0x0304 Reserved + (fp)0, +//;0x0308 Reserved + (fp)0, +//;0x030C Reserved + (fp)0, +//;0x0310 Reserved + (fp)0, +//;0x0314 Reserved + (fp)0, +//;0x0318 DMAC_DMTEND0 + (fp)INT_Excep_DMAC_DMTEND0, +//;0x031C DMAC_DMTEND1 + (fp)INT_Excep_DMAC_DMTEND1, +//;0x0320 DMAC_DMTEND2 + (fp)INT_Excep_DMAC_DMTEND2, +//;0x0324 DMAC_DMTEND3 + (fp)INT_Excep_DMAC_DMTEND3, +//;0x0328 Reserved + (fp)0, +//;0x032C Reserved + (fp)0, +//;0x0330 Reserved + (fp)0, +//;0x0334 Reserved + (fp)0, +//;0x0338 Reserved + (fp)0, +//;0x033C Reserved + (fp)0, +//;0x0340 Reserved + (fp)0, +//;0x0344 Reserved + (fp)0, +//;0x0348 Reserved + (fp)0, +//;0x034C Reserved + (fp)0, +//;0x0350 Reserved + (fp)0, +//;0x0354 Reserved + (fp)0, +//;0x0358 SCI0_ERI0 + (fp)INT_Excep_SCI0_ERI0, +//;0x035C SCI0_RXI0 + (fp)INT_Excep_SCI0_RXI0, +//;0x0360 SCI0_TXI0 + (fp)INT_Excep_SCI0_TXI0, +//;0x0364 SCI0_TEI0 + (fp)INT_Excep_SCI0_TEI0, +//;0x0368 SCI1_ERI1 + (fp)INT_Excep_SCI1_ERI1, +//;0x036C SCI1_RXI1 + (fp)INT_Excep_SCI1_RXI1, +//;0x0370 SCI1_TXI1 + (fp)INT_Excep_SCI1_TXI1, +//;0x0374 SCI1_TEI1 + (fp)INT_Excep_SCI1_TEI1, +//;0x0378 SCI2_ERI2 + (fp)INT_Excep_SCI2_ERI2, +//;0x037C SCI2_RXI2 + (fp)INT_Excep_SCI2_RXI2, +//;0x0380 SCI2_TXI2 + (fp)INT_Excep_SCI2_TXI2, +//;0x0384 SCI2_TEI2 + (fp)INT_Excep_SCI2_TEI2, +//;0x0388 SCI3_ERI3 + (fp)INT_Excep_SCI3_ERI3, +//;0x038C SCI3_RXI3 + (fp)INT_Excep_SCI3_RXI3, +//;0x0390 SCI3_TXI3 + (fp)INT_Excep_SCI3_TXI3, +//;0x0394 SCI3_TEI3 + (fp)INT_Excep_SCI3_TEI3, +//;0x0398 SCI4_ERI4 + (fp)INT_Excep_SCI4_ERI4, +//;0x039C SCI4_RXI4 + (fp)INT_Excep_SCI4_RXI4, +//;0x03A0 SCI4_TXI4 + (fp)INT_Excep_SCI4_TXI4, +//;0x03A4 SCI4_TEI4 + (fp)INT_Excep_SCI4_TEI4, +//;0x03A8 SCI5_ERI5 + (fp)INT_Excep_SCI5_ERI5, +//;0x03AC SCI5_RXI5 + (fp)INT_Excep_SCI5_RXI5, +//;0x03B0 SCI5_TXI5 + (fp)INT_Excep_SCI5_TXI5, +//;0x03B4 SCI5_TEI5 + (fp)INT_Excep_SCI5_TEI5, +//;0x03B8 SCI6_ERI6 + (fp)INT_Excep_SCI6_ERI6, +//;0x03BC SCI6_RXI6 + (fp)INT_Excep_SCI6_RXI6, +//;0x03C0 SCI6_TXI6 + (fp)INT_Excep_SCI6_TXI6, +//;0x03C4 SCI6_TEI6 + (fp)INT_Excep_SCI6_TEI6, +//;0x03C8 Reserved + (fp)0, +//;0x03CC Reserved + (fp)0, +//;0x03D0 Reserved + (fp)0, +//;0x03D4 Reserved + (fp)0, +//;0x03D8 RIIC0_EEI0 + (fp)INT_Excep_RIIC0_EEI0, +//;0x03DC RIIC0_RXI0 + (fp)INT_Excep_RIIC0_RXI0, +//;0x03E0 RIIC0_TXI0 + (fp)INT_Excep_RIIC0_TXI0, +//;0x03E4 RIIC0_TEI0 + (fp)INT_Excep_RIIC0_TEI0, +//;0x03E8 RIIC1_EEI1 + (fp)INT_Excep_RIIC1_EEI1, +//;0x03EC RIIC1_RXI1 + (fp)INT_Excep_RIIC1_RXI1, +//;0x03F0 RIIC1_TXI1 + (fp)INT_Excep_RIIC1_TXI1, +//;0x03F4 RIIC1_TEI1 + (fp)INT_Excep_RIIC1_TEI1, +//;0x03F8 Reserved + (fp)0, +//;0x03FC Reserved + (fp)0, +}; diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/EMAC.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/EMAC.c new file mode 100644 index 000000000..10ca4ff34 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/EMAC.c @@ -0,0 +1,572 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* Hardware specific includes. */ +#include "iodefine.h" +#include "typedefine.h" +#include "r_ether.h" +#include "phy.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* uIP includes. */ +#include "net/uip.h" + +/* The time to wait between attempts to obtain a free buffer. */ +#define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS ) + +/* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving +up on attempting to obtain a free buffer all together. */ +#define emacBUFFER_WAIT_ATTEMPTS ( 30 ) + +/* The number of Rx descriptors. */ +#define emacNUM_RX_DESCRIPTORS 8 + +/* The number of Tx descriptors. When using uIP there is not point in having +more than two. */ +#define emacNUM_TX_BUFFERS 2 + +/* The total number of EMAC buffers to allocate. */ +#define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS ) + +/* The time to wait for the Tx descriptor to become free. */ +#define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS ) + +/* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to +become free. */ +#define emacTX_WAIT_ATTEMPTS ( 50 ) + +/* Only Rx end and Tx end interrupts are used by this driver. */ +#define emacTX_END_INTERRUPT ( 1UL << 21UL ) +#define emacRX_END_INTERRUPT ( 1UL << 18UL ) + +/*-----------------------------------------------------------*/ + +/* The buffers and descriptors themselves. */ +static volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ] __attribute__((aligned(16))); +static volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ] __attribute__((aligned(16))); +static char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ] __attribute__((aligned(16))); + +/* Used to indicate which buffers are free and which are in use. If an index +contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise +the buffer is in use or about to be used. */ +static unsigned char ucBufferInUse[ emacNUM_BUFFERS ]; + +/*-----------------------------------------------------------*/ + +/* + * Initialise both the Rx and Tx descriptors. + */ +static void prvInitialiseDescriptors( void ); + +/* + * Return a pointer to a free buffer within xEthernetBuffers. + */ +static unsigned char *prvGetNextBuffer( void ); + +/* + * Return a buffer to the list of free buffers. + */ +static void prvReturnBuffer( unsigned char *pucBuffer ); + +/* + * Examine the status of the next Rx FIFO to see if it contains new data. + */ +static unsigned long prvCheckRxFifoStatus( void ); + +/* + * Setup the microcontroller for communication with the PHY. + */ +static void prvResetMAC( void ); + +/* + * Configure the Ethernet interface peripherals. + */ +static void prvConfigureEtherCAndEDMAC( void ); + +/* + * Something has gone wrong with the descriptor usage. Reset all the buffers + * and descriptors. + */ +static void prvResetEverything( void ); + +/* + * Wrapper and handler for the EMAC peripheral. See the documentation for this + * port on http://www.FreeRTOS.org for more information on defining interrupt + * handlers. + */ +void vEMAC_ISR_Wrapper( void ) __attribute__((naked)); +static void vEMAC_ISR_Handler( void ) __attribute__((noinline)); + +/*-----------------------------------------------------------*/ + +/* Points to the Rx descriptor currently in use. */ +static ethfifo *pxCurrentRxDesc = NULL; + +/* The buffer used by the uIP stack to both receive and send. This points to +one of the Ethernet buffers when its actually in use. */ +unsigned char *uip_buf = NULL; + +/*-----------------------------------------------------------*/ + +void vInitEmac( void ) +{ + /* Software reset. */ + prvResetMAC(); + + /* Set the Rx and Tx descriptors into their initial state. */ + prvInitialiseDescriptors(); + + /* Set the MAC address into the ETHERC */ + ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) | + ( ( unsigned long ) configMAC_ADDR1 << 16UL ) | + ( ( unsigned long ) configMAC_ADDR2 << 8UL ) | + ( unsigned long ) configMAC_ADDR3; + + ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) | + ( unsigned long ) configMAC_ADDR5; + + /* Perform rest of interface hardware configuration. */ + prvConfigureEtherCAndEDMAC(); + + /* Nothing received yet, so uip_buf points nowhere. */ + uip_buf = NULL; + + /* Initialize the PHY */ + phy_init(); +} +/*-----------------------------------------------------------*/ + +void vEMACWrite( void ) +{ +long x; + + /* Wait until the second transmission of the last packet has completed. */ + for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ ) + { + if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 ) + { + /* Descriptor is still active. */ + vTaskDelay( emacTX_WAIT_DELAY_ms ); + } + else + { + break; + } + } + + /* Is the descriptor free after waiting for it? */ + if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 ) + { + /* Something has gone wrong. */ + prvResetEverything(); + } + + /* Setup both descriptors to transmit the frame. */ + xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf; + xTxDescriptors[ 0 ].bufsize = uip_len; + xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf; + xTxDescriptors[ 1 ].bufsize = uip_len; + + /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer + for use by the stack. */ + uip_buf = prvGetNextBuffer(); + + /* Clear previous settings and go. */ + xTxDescriptors[0].status &= ~( FP1 | FP0 ); + xTxDescriptors[0].status |= ( FP1 | FP0 | ACT ); + xTxDescriptors[1].status &= ~( FP1 | FP0 ); + xTxDescriptors[1].status |= ( FP1 | FP0 | ACT ); + + EDMAC.EDTRR.LONG = 0x00000001; +} +/*-----------------------------------------------------------*/ + +unsigned long ulEMACRead( void ) +{ +unsigned long ulBytesReceived; + + ulBytesReceived = prvCheckRxFifoStatus(); + + if( ulBytesReceived > 0 ) + { + pxCurrentRxDesc->status &= ~( FP1 | FP0 ); + pxCurrentRxDesc->status |= ACT; + + if( EDMAC.EDRRR.LONG == 0x00000000L ) + { + /* Restart Ethernet if it has stopped */ + EDMAC.EDRRR.LONG = 0x00000001L; + } + + /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to + the buffer that contains the received data. */ + prvReturnBuffer( uip_buf ); + + uip_buf = ( void * ) pxCurrentRxDesc->buf_p; + + /* Move onto the next buffer in the ring. */ + pxCurrentRxDesc = pxCurrentRxDesc->next; + } + + return ulBytesReceived; +} +/*-----------------------------------------------------------*/ + +long lEMACWaitForLink( void ) +{ +long lReturn; + + /* Set the link status. */ + switch( phy_set_autonegotiate() ) + { + /* Half duplex link */ + case PHY_LINK_100H: + ETHERC.ECMR.BIT.DM = 0; + ETHERC.ECMR.BIT.RTM = 1; + lReturn = pdPASS; + break; + + case PHY_LINK_10H: + ETHERC.ECMR.BIT.DM = 0; + ETHERC.ECMR.BIT.RTM = 0; + lReturn = pdPASS; + break; + + + /* Full duplex link */ + case PHY_LINK_100F: + ETHERC.ECMR.BIT.DM = 1; + ETHERC.ECMR.BIT.RTM = 1; + lReturn = pdPASS; + break; + + case PHY_LINK_10F: + ETHERC.ECMR.BIT.DM = 1; + ETHERC.ECMR.BIT.RTM = 0; + lReturn = pdPASS; + break; + + default: + lReturn = pdFAIL; + break; + } + + if( lReturn == pdPASS ) + { + /* Enable receive and transmit. */ + ETHERC.ECMR.BIT.RE = 1; + ETHERC.ECMR.BIT.TE = 1; + + /* Enable EDMAC receive */ + EDMAC.EDRRR.LONG = 0x1; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseDescriptors( void ) +{ +volatile ethfifo *pxDescriptor; +long x; + + for( x = 0; x < emacNUM_BUFFERS; x++ ) + { + /* Ensure none of the buffers are shown as in use at the start. */ + ucBufferInUse[ x ] = pdFALSE; + } + + /* Initialise the Rx descriptors. */ + for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ ) + { + pxDescriptor = &( xRxDescriptors[ x ] ); + pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] ); + + pxDescriptor->bufsize = UIP_BUFSIZE; + pxDescriptor->size = 0; + pxDescriptor->status = ACT; + pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ x + 1 ]; + + /* Mark this buffer as in use. */ + ucBufferInUse[ x ] = pdTRUE; + } + + /* The last descriptor points back to the start. */ + pxDescriptor->status |= DL; + pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ 0 ]; + + /* Initialise the Tx descriptors. */ + for( x = 0; x < emacNUM_TX_BUFFERS; x++ ) + { + pxDescriptor = &( xTxDescriptors[ x ] ); + + /* A buffer is not allocated to the Tx descriptor until a send is + actually required. */ + pxDescriptor->buf_p = NULL; + + pxDescriptor->bufsize = UIP_BUFSIZE; + pxDescriptor->size = 0; + pxDescriptor->status = 0; + pxDescriptor->next = ( struct Descriptor * ) &xTxDescriptors[ x + 1 ]; + } + + /* The last descriptor points back to the start. */ + pxDescriptor->status |= DL; + pxDescriptor->next = ( struct Descriptor * ) &( xTxDescriptors[ 0 ] ); + + /* Use the first Rx descriptor to start with. */ + pxCurrentRxDesc = ( struct Descriptor * ) &( xRxDescriptors[ 0 ] ); +} +/*-----------------------------------------------------------*/ + +static unsigned char *prvGetNextBuffer( void ) +{ +long x; +unsigned char *pucReturn = NULL; +unsigned long ulAttempts = 0; + + while( pucReturn == NULL ) + { + /* Look through the buffers to find one that is not in use by + anything else. */ + for( x = 0; x < emacNUM_BUFFERS; x++ ) + { + if( ucBufferInUse[ x ] == pdFALSE ) + { + ucBufferInUse[ x ] = pdTRUE; + pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] ); + break; + } + } + + /* Was a buffer found? */ + if( pucReturn == NULL ) + { + ulAttempts++; + + if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS ) + { + break; + } + + /* Wait then look again. */ + vTaskDelay( emacBUFFER_WAIT_DELAY_ms ); + } + } + + return pucReturn; +} +/*-----------------------------------------------------------*/ + +static void prvReturnBuffer( unsigned char *pucBuffer ) +{ +unsigned long ul; + + /* Return a buffer to the pool of free buffers. */ + for( ul = 0; ul < emacNUM_BUFFERS; ul++ ) + { + if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer ) + { + ucBufferInUse[ ul ] = pdFALSE; + break; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvResetEverything( void ) +{ + /* Temporary code just to see if this gets called. This function has not + been implemented. */ + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static unsigned long prvCheckRxFifoStatus( void ) +{ +unsigned long ulReturn = 0; + + if( ( pxCurrentRxDesc->status & ACT ) != 0 ) + { + /* Current descriptor is still active. */ + } + else if( ( pxCurrentRxDesc->status & FE ) != 0 ) + { + /* Frame error. Clear the error. */ + pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE ); + pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF ); + pxCurrentRxDesc->status |= ACT; + pxCurrentRxDesc = pxCurrentRxDesc->next; + + if( EDMAC.EDRRR.LONG == 0x00000000UL ) + { + /* Restart Ethernet if it has stopped. */ + EDMAC.EDRRR.LONG = 0x00000001UL; + } + } + else + { + /* The descriptor contains a frame. Because of the size of the buffers + the frame should always be complete. */ + if( ( pxCurrentRxDesc->status & FP0 ) == FP0 ) + { + ulReturn = pxCurrentRxDesc->size; + } + else + { + /* Do not expect to get here. */ + prvResetEverything(); + } + } + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +static void prvResetMAC( void ) +{ + /* Ensure the EtherC and EDMAC are enabled. */ + SYSTEM.MSTPCRB.BIT.MSTPB15 = 0; + vTaskDelay( 100 / portTICK_RATE_MS ); + + EDMAC.EDMR.BIT.SWR = 1; + + /* Crude wait for reset to complete. */ + vTaskDelay( 500 / portTICK_RATE_MS ); +} +/*-----------------------------------------------------------*/ + +static void prvConfigureEtherCAndEDMAC( void ) +{ + /* Initialisation code taken from Renesas example project. */ + + /* TODO: Check bit 5 */ + ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */ + + /* Set the EDMAC interrupt priority. */ + _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* TODO: Check bit 5 */ + /* Enable interrupts of interest only. */ + EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT; + ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */ + ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */ + + /* EDMAC */ + EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */ + #ifdef __RX_LITTLE_ENDIAN__ + EDMAC.EDMR.BIT.DE = 1; + #endif + EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */ + EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */ + EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */ + EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */ + EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */ + EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */ + + /* Enable the interrupt... */ + _IEN( _ETHER_EINT ) = 1; +} +/*-----------------------------------------------------------*/ + +void vEMAC_ISR_Wrapper( void ) +{ + /* This is a naked function. See the documentation for this port on + http://www.FreeRTOS.org for more information on writing interrupts. + + /* Save the registers and enable interrupts. */ + portENTER_INTERRUPT(); + + /* Perform the actual EMAC processing. */ + vEMAC_ISR_Handler(); + + /* Restore the registers and return. */ + portEXIT_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +static void vEMAC_ISR_Handler( void ) +{ +unsigned long ul = EDMAC.EESR.LONG; +long lHigherPriorityTaskWoken = pdFALSE; +extern xSemaphoreHandle xEMACSemaphore; +static long ulTxEndInts = 0; + + /* Has a Tx end occurred? */ + if( ul & emacTX_END_INTERRUPT ) + { + ++ulTxEndInts; + if( ulTxEndInts >= 2 ) + { + /* Only return the buffer to the pool once both Txes have completed. */ + prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p ); + ulTxEndInts = 0; + } + EDMAC.EESR.LONG = emacTX_END_INTERRUPT; + } + + /* Has an Rx end occurred? */ + if( ul & emacRX_END_INTERRUPT ) + { + /* Make sure the Ethernet task is not blocked waiting for a packet. */ + xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( lHigherPriorityTaskWoken ); + EDMAC.EESR.LONG = emacRX_END_INTERRUPT; + } +} + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-cgi.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-cgi.c new file mode 100644 index 000000000..432f957bb --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-cgi.c @@ -0,0 +1,277 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ +#include "net/uip.h" +#include "net/psock.h" +#include "apps/httpd/httpd.h" +#include "apps/httpd/httpd-cgi.h" +#include "apps/httpd/httpd-fs.h" + +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +HTTPD_CGI_CALL( file, "file-stats", file_stats ); +HTTPD_CGI_CALL( tcp, "tcp-connections", tcp_stats ); +HTTPD_CGI_CALL( net, "net-stats", net_stats ); +HTTPD_CGI_CALL( rtos, "rtos-stats", rtos_stats ); +HTTPD_CGI_CALL( run, "run-time", run_time ); +HTTPD_CGI_CALL( io, "led-io", led_io ); + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &run, &io, NULL }; + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( nullfunction ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + ( void ) ptr; + ( void ) PT_YIELD_FLAG; + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +httpd_cgifunction httpd_cgi( char *name ) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for( f = calls; *f != NULL; ++f ) + { + if( strncmp((*f)->name, name, strlen((*f)->name)) == 0 ) + { + return( *f )->function; + } + } + + return nullfunction; +} + +/*---------------------------------------------------------------------------*/ +static unsigned short generate_file_stats( void *arg ) +{ + char *f = ( char * ) arg; + return sprintf( ( char * ) uip_appdata, "%5u", httpd_fs_count(f) ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( file_stats ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + + ( void ) PT_YIELD_FLAG; + + PSOCK_GENERATOR_SEND( &s->sout, generate_file_stats, strchr(ptr, ' ') + 1 ); + + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ { 0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0 }; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ { 0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, 0x44, 0 }; +static const char syn_sent[] = /* "SYN-SENT",*/ { 0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, 0x54, 0 }; +static const char established[] = /* "ESTABLISHED",*/ { 0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, 0x45, 0x44, 0 }; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ { 0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, 0x54, 0x2d, 0x31, 0 }; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ { 0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, 0x54, 0x2d, 0x32, 0 }; +static const char closing[] = /* "CLOSING",*/ { 0x43, 0x4c, 0x4f, 0x53, 0x49, 0x4e, 0x47, 0 }; +static const char time_wait[] = /* "TIME-WAIT,"*/ { 0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, 0x49, 0x54, 0 }; +static const char last_ack[] = /* "LAST-ACK"*/ { 0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, 0x4b, 0 }; + +static const char *states[] = { closed, syn_rcvd, syn_sent, established, fin_wait_1, fin_wait_2, closing, time_wait, last_ack }; + +static unsigned short generate_tcp_stats( void *arg ) +{ + struct uip_conn *conn; + struct httpd_state *s = ( struct httpd_state * ) arg; + + conn = &uip_conns[s->count]; + return sprintf( ( char * ) uip_appdata, + "%d%u.%u.%u.%u:%u%s%u%u%c %c\r\n", htons(conn->lport), + htons(conn->ripaddr.u16[0]) >> 8, htons(conn->ripaddr.u16[0]) & 0xff, htons(conn->ripaddr.u16[1]) >> 8, + htons(conn->ripaddr.u16[1]) & 0xff, htons(conn->rport), states[conn->tcpstateflags & UIP_TS_MASK], conn->nrtx, conn->timer, + (uip_outstanding(conn)) ? '*' : ' ', (uip_stopped(conn)) ? '!' : ' ' ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( tcp_stats ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + ( void ) ptr; + ( void ) PT_YIELD_FLAG; + for( s->count = 0; s->count < UIP_CONNS; ++s->count ) + { + if( (uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED ) + { + PSOCK_GENERATOR_SEND( &s->sout, generate_tcp_stats, s ); + } + } + + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +static unsigned short generate_net_stats( void *arg ) +{ + struct httpd_state *s = ( struct httpd_state * ) arg; + return sprintf( ( char * ) uip_appdata, "%5u\n", (( uip_stats_t * ) &uip_stat)[s->count] ); +} + +static PT_THREAD( net_stats ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + ( void ) ptr; + ( void ) PT_YIELD_FLAG; +#if UIP_STATISTICS + for( s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); ++s->count ) + { + PSOCK_GENERATOR_SEND( &s->sout, generate_net_stats, s ); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +extern void vTaskList( signed char *pcWriteBuffer ); +extern char *pcGetTaskStatusMessage( void ); +static char cCountBuf[128]; +long lRefreshCount = 0; +static unsigned short generate_rtos_stats( void *arg ) +{ + ( void ) arg; + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d


%s", ( int ) lRefreshCount, pcGetTaskStatusMessage() ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( rtos_stats ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + ( void ) ptr; + ( void ) PT_YIELD_FLAG; + PSOCK_GENERATOR_SEND( &s->sout, generate_rtos_stats, NULL ); + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +char *pcStatus; +unsigned long ulString; + +static unsigned short generate_io_state( void *arg ) +{ + extern long lParTestGetLEDState( unsigned long ulLED ); + ( void ) arg; + + /* Are the dynamically setable LEDs currently on or off? */ + if( lParTestGetLEDState( 8 ) ) + { + pcStatus = "checked"; + } + else + { + pcStatus = ""; + } + + sprintf( uip_appdata, "LED

", pcStatus ); + + return strlen( uip_appdata ); +} + +/*---------------------------------------------------------------------------*/ +extern void vTaskGetRunTimeStats( signed char *pcWriteBuffer ); +extern unsigned short usMaxJitter; +static char cJitterBuffer[ 200 ]; +static unsigned short generate_runtime_stats( void *arg ) +{ + ( void ) arg; + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", ( int ) lRefreshCount ); + + #ifdef INCLUDE_HIGH_FREQUENCY_TIMER_TEST + { + sprintf( cJitterBuffer, "


Max high frequency timer jitter = %d peripheral clock periods.


", ( int ) usMaxJitter ); + vTaskGetRunTimeStats( uip_appdata ); + strcat( uip_appdata, cJitterBuffer ); + } + #else + { + ( void ) cJitterBuffer; + strcpy( uip_appdata, "

Run time stats are only available in the debug_with_optimisation build configuration.

" ); + } + #endif + + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( run_time ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + ( void ) ptr; + ( void ) PT_YIELD_FLAG; + PSOCK_GENERATOR_SEND( &s->sout, generate_runtime_stats, NULL ); + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( led_io ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + ( void ) ptr; + ( void ) PT_YIELD_FLAG; + PSOCK_GENERATOR_SEND( &s->sout, generate_io_state, NULL ); + PSOCK_END( &s->sout ); +} + +/** @} */ diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/404.html b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/404.html new file mode 100644 index 000000000..43e7f4cad --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/index.html b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/index.html new file mode 100644 index 000000000..4937dc69a --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/index.shtml b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/index.shtml new file mode 100644 index 000000000..882d085ce --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS Homepage | IO | 37K jpg +

+

+

+

Task statistics

+Page will refresh every 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/io.shtml b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/io.shtml new file mode 100644 index 000000000..819e2d39b --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/io.shtml @@ -0,0 +1,28 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS Homepage | IO | 37K jpg +

+

+LED and LCD IO
+ +

+ +Use the check box to turn on or off LED 4, then click "Update IO". + + +

+

+%! led-io +

+ +

+

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+

+

+

Run-time statistics

+Page will refresh every 2 seconds.

+

Task            Abs Time      % Time
****************************************

+%! run-time
+
+ + + + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/stats.shtml b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/stats.shtml new file mode 100644 index 000000000..f54118606 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/stats.shtml @@ -0,0 +1,47 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS Homepage | IO | 37K jpg +

+

+

+

Network statistics

+ +
+IP           Packets received
+             Packets sent
+             Forwaded
+             Dropped
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets received
+             Packets sent
+             Packets dropped
+             Type errors
+             Checksum errors
+TCP          Packets received
+             Packets sent
+             Packets dropped
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissionsa
+             Syn to closed port
+UDP          Packets dropped
+             Packets received
+             Packets sent
+             Packets chkerr
+	     No connection avaliable
+
%! net-stats
+
+ + + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/tcp.shtml b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/tcp.shtml new file mode 100644 index 000000000..23dcdcae3 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS Homepage | IO | 37K jpg +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fsdata.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fsdata.c new file mode 100644 index 000000000..47823d100 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/httpd-fsdata.c @@ -0,0 +1,3871 @@ +static const char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, + 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, + 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, + 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, + 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, + 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, + 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x3c, 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0x6d, 0x6c, 0x3e, 0xd, + 0xa, 0xd, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; + +const struct httpd_fsdata_file file_logo_jpg[] = {{file_io_shtml, data_logo_jpg, data_logo_jpg + 10, sizeof(data_logo_jpg) - 10}}; + +const struct httpd_fsdata_file file_runtime_shtml[] = {{file_logo_jpg, data_runtime_shtml, data_runtime_shtml + 15, sizeof(data_runtime_shtml) - 15}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_runtime_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 8 diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/makefsdata b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/makefsdata new file mode 100644 index 000000000..a953cdd76 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/makefsdata @@ -0,0 +1,79 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + binmode FILE; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/phy.c b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/phy.c new file mode 100644 index 000000000..c4f20508f --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/phy.c @@ -0,0 +1,474 @@ +/****************************************************************************** +* DISCLAIMER + +* This software is supplied by Renesas Technology Corp. and is only +* intended for use with Renesas products. No other uses are authorized. + +* This software is owned by Renesas Technology Corp. and is protected under +* all applicable laws, including copyright laws. + +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES +* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, +* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY +* DISCLAIMED. + +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES +* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS +* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +* Renesas reserves the right, without notice, to make changes to this +* software and to discontinue the availability of this software. +* By using this software, you agree to the additional terms and +* conditions found by accessing the following link: +* http://www.renesas.com/disclaimer +****************************************************************************** +* Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved. +******************************************************************************* +* File Name : phy.c +* Version : 1.01 +* Description : Ethernet PHY device driver +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.02.2010 1.00 First Release +* : 06.04.2010 1.01 RX62N changes +******************************************************************************/ + + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include +#include "r_ether.h" +#include "phy.h" + +#include "FreeRTOS.h" +#include "task.h" +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ +uint16_t _phy_read( uint16_t reg_addr ); +void _phy_write( uint16_t reg_addr, uint16_t data ); +void _phy_preamble( void ); +void _phy_reg_set( uint16_t reg_addr, int32_t option ); +void _phy_reg_read( uint16_t *data ); +void _phy_reg_write( uint16_t data ); +void _phy_ta_z0( void ); +void _phy_ta_10( void ); +void _phy_mii_write_1( void ); +void _phy_mii_write_0( void ); + +/** + * External functions + */ + +/****************************************************************************** +* Function Name: phy_init +* Description : Resets Ethernet PHY device +* Arguments : none +* Return Value : none +******************************************************************************/ +int16_t phy_init( void ) +{ + uint16_t reg; + uint32_t count; + + /* Reset PHY */ + _phy_write(BASIC_MODE_CONTROL_REG, 0x8000); + + count = 0; + + do + { + vTaskDelay( 2 / portTICK_RATE_MS ); + reg = _phy_read(BASIC_MODE_CONTROL_REG); + count++; + } while (reg & 0x8000 && count < PHY_RESET_WAIT); + + if( count < PHY_RESET_WAIT ) + { + return R_PHY_OK; + } + + return R_PHY_ERROR; +} + +/****************************************************************************** +* Function Name: phy_set_100full +* Description : Set Ethernet PHY device to 100 Mbps full duplex +* Arguments : none +* Return Value : none +******************************************************************************/ +void phy_set_100full( void ) +{ + _phy_write(BASIC_MODE_CONTROL_REG, 0x2100); +} + +/****************************************************************************** +* Function Name: phy_set_10half +* Description : Sets Ethernet PHY device to 10 Mbps half duplexR +* Arguments : none +* Return Value : none +******************************************************************************/ +void phy_set_10half( void ) +{ + _phy_write(BASIC_MODE_CONTROL_REG, 0x0000); +} + +/****************************************************************************** +* Function Name: phy_set_autonegotiate +* Description : Starts autonegotiate and reports the other side's +* : physical capability +* Arguments : none +* Return Value : bit 8 - Full duplex 100 mbps +* : bit 7 - Half duplex 100 mbps +* : bit 6 - Full duplex 10 mbps +* : bit 5 - Half duplex 10 mbps +* : bit 4:0 - Always set to 00001 (IEEE 802.3) +* : -1 if error +******************************************************************************/ +int16_t phy_set_autonegotiate( void ) +{ + uint16_t reg; + uint32_t count; + + _phy_write(AN_ADVERTISEMENT_REG, 0x01E1); + _phy_write(BASIC_MODE_CONTROL_REG, 0x1200); + + count = 0; + + do + { + reg = _phy_read(BASIC_MODE_STATUS_REG); + count++; + vTaskDelay( 100 / portTICK_RATE_MS ); + + /* Make sure we don't break out if reg just contains 0xffff. */ + if( reg == 0xffff ) + { + reg = 0; + } + + } while (!(reg & 0x0020) && (count < PHY_AUTO_NEGOTIATON_WAIT)); + + if (count >= PHY_AUTO_NEGOTIATON_WAIT) + { + return R_PHY_ERROR; + } + else + { + /* National DP83640 fix */ + _phy_write(0x13, 0x0006); + reg = _phy_read(0x14); + _phy_write(0x14, (reg&0x7FFF)); + _phy_write(0x13, 0x0000); + + /* Get the link partner response */ + reg = (int16_t)_phy_read(AN_LINK_PARTNER_ABILITY_REG); + + if (reg & ( 1 << 8 ) ) + { + return PHY_LINK_100F; + } + if (reg & ( 1 << 7 ) ) + { + return PHY_LINK_100H; + } + if (reg & ( 1 << 6 ) ) + { + return PHY_LINK_10F; + } + if (reg & 1 << 5 ) + { + return PHY_LINK_10H; + } + + return (-1); + } +} + + +/** + * Internal functions + */ + +/****************************************************************************** +* Function Name: _phy_read +* Description : Reads a PHY register +* Arguments : reg_addr - address of the PHY register +* Return Value : read value +******************************************************************************/ +uint16_t _phy_read( uint16_t reg_addr ) +{ + uint16_t data; + + _phy_preamble(); + _phy_reg_set( reg_addr, PHY_READ ); + _phy_ta_z0(); + _phy_reg_read( &data ); + _phy_ta_z0(); + + return( data ); +} + +/****************************************************************************** +* Function Name: _phy_write +* Description : Writes to a PHY register +* Arguments : reg_addr - address of the PHY register +* : data - value +* Return Value : none +******************************************************************************/ +void _phy_write( uint16_t reg_addr, uint16_t data ) +{ + _phy_preamble(); + _phy_reg_set( reg_addr, PHY_WRITE ); + _phy_ta_10(); + _phy_reg_write( data ); + _phy_ta_z0(); +} + +/****************************************************************************** +* Function Name: _phy_preamble +* Description : As preliminary preparation for access to the PHY module register, +* "1" is output via the MII management interface. +* Arguments : none +* Return Value : none +******************************************************************************/ +void _phy_preamble( void ) +{ + int16_t i; + + i = 32; + while( i > 0 ) + { + _phy_mii_write_1(); + i--; + } +} + +/****************************************************************************** +* Function Name: _phy_reg_set +* Description : Sets a PHY device to read or write mode +* Arguments : reg_addr - address of the PHY register +* : option - mode +* Return Value : none +******************************************************************************/ +void _phy_reg_set( uint16_t reg_addr, int32_t option ) +{ + int32_t i; + uint16_t data; + + data = 0; + data = (PHY_ST << 14); /* ST code */ + + if( option == PHY_READ ) + { + data |= (PHY_READ << 12); /* OP code(RD) */ + } + else + { + data |= (PHY_WRITE << 12); /* OP code(WT) */ + } + + data |= (PHY_ADDR << 7); /* PHY Address */ + data |= (reg_addr << 2); /* Reg Address */ + + i = 14; + while( i > 0 ) + { + if( (data & 0x8000) == 0 ) + { + _phy_mii_write_0(); + } + else + { + _phy_mii_write_1(); + } + data <<= 1; + i--; + } +} + +/****************************************************************************** +* Function Name: _phy_reg_read +* Description : Reads PHY register through MII interface +* Arguments : data - pointer to store the data read +* Return Value : none +******************************************************************************/ +void _phy_reg_read( uint16_t *data ) +{ + int32_t i, j; + uint16_t reg_data; + + reg_data = 0; + i = 16; + while( i > 0 ) + { + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000000; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000001; + } + + reg_data <<= 1; + reg_data |= (uint16_t)((ETHERC.PIR.LONG & 0x00000008) >> 3); /* MDI read */ + + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000001; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000000; + } + i--; + } + *data = reg_data; +} + +/****************************************************************************** +* Function Name: _phy_reg_write +* Description : Writes to PHY register through MII interface +* Arguments : data - value to write +* Return Value : none +******************************************************************************/ +void _phy_reg_write( uint16_t data ) +{ + int32_t i; + + i = 16; + while( i > 0 ) + { + if( (data & 0x8000) == 0 ) + { + _phy_mii_write_0(); + } + else + { + _phy_mii_write_1(); + } + i--; + data <<= 1; + } +} + +/****************************************************************************** +* Function Name: _phy_ta_z0 +* Description : Performs bus release so that PHY can drive data +* : for read operation +* Arguments : none +* Return Value : none +******************************************************************************/ +void _phy_ta_z0( void ) +{ + int32_t j; + + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000000; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000001; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000001; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000000; + } +} + +/****************************************************************************** +* Function Name: _phy_ta_10 +* Description : Switches data bus so MII interface can drive data +* : for write operation +* Arguments : none +* Return Value : none +******************************************************************************/ +void _phy_ta_10(void) +{ + _phy_mii_write_1(); + _phy_mii_write_0(); +} + +/****************************************************************************** +* Function Name: _phy_mii_write_1 +* Description : Outputs 1 to the MII interface +* Arguments : none +* Return Value : none +******************************************************************************/ +void _phy_mii_write_1( void ) +{ + int32_t j; + + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000006; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000007; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000007; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000006; + } +} + +/****************************************************************************** +* Function Name: _phy_mii_write_0 +* Description : Outputs 0 to the MII interface +* Arguments : none +* Return Value : none +******************************************************************************/ +void _phy_mii_write_0( void ) +{ + int32_t j; + + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000002; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000003; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000003; + } + for(j = MDC_WAIT; j > 0; j--) + { + ETHERC.PIR.LONG = 0x00000002; + } +} + + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/phy.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/phy.h new file mode 100644 index 000000000..e2429d932 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/phy.h @@ -0,0 +1,84 @@ +/****************************************************************************** +* DISCLAIMER +* Please refer to http://www.renesas.com/disclaimer +****************************************************************************** + Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved. +******************************************************************************* +* File Name : phy.h +* Version : 1.02 +* Description : Ethernet PHY device driver +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.02.2010 1.00 First Release +* : 17.03.2010 1.01 Modification of macro definitions for access timing +* : 06.04.2010 1.02 RX62N changes +******************************************************************************/ + +#ifndef PHY_H +#define PHY_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* Standard PHY Registers */ +#define BASIC_MODE_CONTROL_REG 0 +#define BASIC_MODE_STATUS_REG 1 +#define PHY_IDENTIFIER1_REG 2 +#define PHY_IDENTIFIER2_REG 3 +#define AN_ADVERTISEMENT_REG 4 +#define AN_LINK_PARTNER_ABILITY_REG 5 +#define AN_EXPANSION_REG 6 + +/* Media Independent Interface */ +#define PHY_ST 1 +#define PHY_READ 2 +#define PHY_WRITE 1 +#define PHY_ADDR 0x01 + +#define MDC_WAIT 2 + +/* PHY return definitions */ +#define R_PHY_OK 0 +#define R_PHY_ERROR -1 + +/* Auto-Negotiation Link Partner Status */ +#define PHY_AN_LINK_PARTNER_100BASE 0x0180 +#define PHY_AN_LINK_PARTNER_FULL 0x0140 +#define PHY_AN_COMPLETE ( 1 << 5 ) + +/* + * Wait counter definitions of PHY-LSI initialization + * ICLK = 96MHz +*/ +#define PHY_RESET_WAIT 0x00000020L +#define PHY_AUTO_NEGOTIATON_WAIT 75 + +#define PHY_AN_ENABLE 0x1200 +#define PHY_AN_10_100_F_H 0xde1 + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ +/** + * External prototypes + **/ +int16_t phy_init( void ); +void phy_set_100full( void ); +void phy_set_10half( void ); +int16_t phy_set_autonegotiate( void ); + +#endif /* PHY_H */ + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/r_ether.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/r_ether.h new file mode 100644 index 000000000..f6633e1d7 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/r_ether.h @@ -0,0 +1,185 @@ +/****************************************************************************** +* DISCLAIMER +* Please refer to http://www.renesas.com/disclaimer +****************************************************************************** + Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved. +******************************************************************************* +* File Name : r_ether.h +* Version : 1.02 +* Description : Ethernet module device driver +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.02.2010 1.00 First Release +* : 03.03.2010 1.01 Buffer size is aligned on the 32-byte boundary. +* : 04.06.2010 1.02 RX62N changes +******************************************************************************/ + +#ifndef R_ETHER_H +#define R_ETHER_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ +struct Descriptor +{ + unsigned long status; +#if __RX_LITTLE_ENDIAN__ == 1 +/* Little endian */ + unsigned short size; + unsigned short bufsize; +#else +/* Big endian */ + unsigned short bufsize; + unsigned short size; + +#endif + char *buf_p; + struct Descriptor *next; +}; + +typedef struct Descriptor ethfifo; + +typedef enum _NETLNK +{ + PHY_NO_LINK = 0, + PHY_LINK_10H, + PHY_LINK_10F, + PHY_LINK_100H, + PHY_LINK_100F + +} NETLNK; + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define BUFSIZE 256 /* Must be 32-bit aligned */ +#define ENTRY 8 /* Number of RX and TX buffers */ + +#define ACT 0x80000000 +#define DL 0x40000000 +#define FP1 0x20000000 +#define FP0 0x10000000 +#define FE 0x08000000 + +#define RFOVER 0x00000200 +#define RAD 0x00000100 +#define RMAF 0x00000080 +#define RRF 0x00000010 +#define RTLF 0x00000008 +#define RTSF 0x00000004 +#define PRE 0x00000002 +#define CERF 0x00000001 + +#define TAD 0x00000100 +#define CND 0x00000008 +#define DLC 0x00000004 +#define CD 0x00000002 +#define TRO 0x00000001 + +/** + * Renesas Ethernet API return defines + **/ +#define R_ETHER_OK 0 +#define R_ETHER_ERROR -1 + +/* Ether Interface definitions */ +#define ETH_RMII_MODE 0 +#define ETH_MII_MODE 1 +/* Select Ether Interface Mode */ +#define ETH_MODE_SEL ETH_MII_MODE + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ +/** + * Renesas Ethernet API prototypes + **/ +long R_Ether_Open(unsigned long ch, unsigned char mac_addr[]); +long R_Ether_Close(unsigned long ch); +long R_Ether_Write(unsigned long ch, void *buf, unsigned long len); +long R_Ether_Read(unsigned long ch, void *buf); + +/** + * FreeRTOS Ethernet API prototypes. + */ + +/* + * Configure all the ethernet components (MAC, DMA, PHY) ready for communication. + */ +void vInitEmac( void ); + +/* + * Auto negotiate the link, returning pass or fail depending on whether a link + * was established or not. + */ +long lEMACWaitForLink( void ); + +/* + * Check the Rx status, and return the number of bytes received if any. + */ +unsigned long ulEMACRead( void ); + +/* + * Send uip_len bytes from uip_buf to the Tx descriptors and initiate a Tx. + */ +void vEMACWrite( void ); + + + + +/****************************************************/ +/* Ethernet statistic collection data */ +struct enet_stats +{ + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_errors; /* bad packets received */ + unsigned long tx_errors; /* packet transmit problems */ + unsigned long rx_dropped; /* no space in buffers */ + unsigned long tx_dropped; /* no space available */ + unsigned long multicast; /* multicast packets received */ + unsigned long collisions; + + /* detailed rx_errors: */ + unsigned long rx_length_errors; + unsigned long rx_over_errors; /* receiver ring buffer overflow */ + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_frame_errors; /* recv'd frame alignment error */ + unsigned long rx_fifo_errors; /* recv'r fifo overrun */ + unsigned long rx_missed_errors; /* receiver missed packet */ + + /* detailed tx_errors */ + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; +}; + +struct ei_device +{ + const char *name; + unsigned char open; + unsigned char Tx_act; + unsigned char Rx_act; + unsigned char txing; /* Transmit Active */ + unsigned char irqlock; /* EDMAC's interrupt disabled when '1'. */ + unsigned char dmaing; /* EDMAC Active */ + ethfifo *rxcurrent; /* current receive discripter */ + ethfifo *txcurrent; /* current transmit discripter */ + unsigned char save_irq; /* Original dev->irq value. */ + struct enet_stats stat; + unsigned char mac_addr[6]; +}; + +#endif /* R_ETHER_H */ + diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/uip-conf.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/uip-conf.h new file mode 100644 index 000000000..47d17fdcb --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/uip-conf.h @@ -0,0 +1,167 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#define UIP_CONF_EXTERNAL_BUFFER +#define UIP_CONF_PROCESS_HTTPD_FORMS 1 + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned char u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned short u16_t; + +typedef unsigned long u32_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1480 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#ifdef __RX_LITTLE_ENDIAN__ +#define UIP_CONF_BYTE_ORDER UIP_LITTLE_ENDIAN +#else +#define UIP_CONF_BYTE_ORDER UIP_BIG_ENDIAN +#endif + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#define CCIF +#define CC_REGISTER_ARG + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/webserver.h b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/webserver.h new file mode 100644 index 000000000..5267f0587 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RTOSDemo/webserver/webserver.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "apps/httpd/httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#define UIP_APPCALL httpd_appcall + + +#endif /* __WEBSERVER_H__ */ diff --git a/Demo/RX600_RX62N-RDK_GNURX/RX600_RX62N_RSK_GNURX.Hbp b/Demo/RX600_RX62N-RDK_GNURX/RX600_RX62N_RSK_GNURX.Hbp new file mode 100644 index 000000000..241474974 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RX600_RX62N_RSK_GNURX.Hbp @@ -0,0 +1,2 @@ +[Setting] +ToolChain=0 diff --git a/Demo/RX600_RX62N-RDK_GNURX/RX600_RX62N_RSK_GNURX.hws b/Demo/RX600_RX62N-RDK_GNURX/RX600_RX62N_RSK_GNURX.hws new file mode 100644 index 000000000..9d3f9eacd --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RX600_RX62N_RSK_GNURX.hws @@ -0,0 +1,40 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"11.0" +[WORKSPACE_DETAILS] +"RX600_RX62N_RSK_GNURX" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RSK_GNURX" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RSK_GNURX\RX600_RX62N_RSK_GNURX.hws" "RX" "KPIT GNURX [ELF]" +[SHARED_WORKSPACE_CONTROL_STATUS] +"" "" "" +"" "" "" +[PROJECTS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RSK_GNURX\RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RSK_GNURX\RTOSDemo\RTOSDemo.hwp" 0 +[INFORMATION] +"No workspace information available" +[SCRAP] +[PROJECT_DEPENDENCY] +[WORKSPACE_PROPERTIES] +[HELP_FILES] +[GENERAL_DATA_PROJECT] +[USERMENUTOOLS] +[CUSTOMPLACEHOLDERS] +[MAKEFILE_BUILD_INFO] +"$(WORKSPDIR)\make\$(PROJECTNAME)_$(CONFIGNAME).mak" "" "$(WORKSPDIR)\make" 0 0 0 +[VD_CONFIGURATION_OPTIONS] +"ACTIVE_DESKTOP" "0" +[VD_CONFIGURATIONS] +"0" "Default1" "1" +"1" "Default2" "1" +"2" "Default3" "1" +"3" "Default4" "1" +[OPTIONS_DEBUG_TAB] +0 0 0 0 0 +[VCS] +"" "" "" 0 +[VCS_PROJECT] +[MAKEFILE_ENV_STRINGS] +[MAKEFILE_ENV_FLAGS] +1 0 0 +[MAKEFILE_CLEAN_INFO] +"" +[END] diff --git a/Demo/RX600_RX62N-RDK_GNURX/RX600_RX62N_RSK_GNURX.tws b/Demo/RX600_RX62N-RDK_GNURX/RX600_RX62N_RSK_GNURX.tws new file mode 100644 index 000000000..fc4b52099 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_GNURX/RX600_RX62N_RSK_GNURX.tws @@ -0,0 +1,15 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.2" +[CURRENT_PROJECT] +"RTOSDemo" +[GENERAL_DATA] +[BREAKPOINTS] +[OPEN_WORKSPACE_FILES] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RSK_GNURX\RTOSDemo\main-full.c" +[WORKSPACE_FILE_STATES] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RSK_GNURX\RTOSDemo\main-full.c" -4 -23 1314 608 1 0 +[LOADED_PROJECTS] +"RTOSDemo" +[END] -- 2.39.5
LocalRemoteStateRetransmissionsTimerFlags