From 3dc22bfb1c157f315f10075937c8a2b0c9030664 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Sat, 13 Mar 2010 19:20:19 +0000 Subject: [PATCH] Very first demo for the Energy Micro EFM32 added. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@990 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../CMSIS/CM3/CoreSupport/core_cm3.c | 784 ++ .../CMSIS/CM3/CoreSupport/core_cm3.h | 1818 +++ .../DeviceSupport/EnergyMicro/EFM32/efm32.h | 109 + .../EnergyMicro/EFM32/efm32g890f128.h | 11665 ++++++++++++++++ .../EnergyMicro/EFM32/system_efm32.c | 126 + .../EnergyMicro/EFM32/system_efm32.h | 69 + .../CMSIS/CMSIS changes.htm | 320 + .../CMSIS/CMSIS debug support.htm | 243 + .../CMSIS/Documentation/CMSIS_Core.htm | 1337 ++ Demo/CORTEX_EFMG890F128_IAR/CMSIS/License.doc | Bin 0 -> 39936 bytes Demo/CORTEX_EFMG890F128_IAR/FreeRTOSConfig.h | 108 + Demo/CORTEX_EFMG890F128_IAR/ParTest.c | 109 + Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewd | 1411 ++ Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewp | 1677 +++ Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.eww | 10 + Demo/CORTEX_EFMG890F128_IAR/bsp/chip.h | 72 + Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.c | 62 + Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.h | 122 + .../bsp/dvk_bcregisters.h | 103 + .../bsp/dvk_boardcontrol.c | 235 + .../bsp/dvk_boardcontrol.h | 81 + Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_ebi.c | 248 + Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_spi.c | 229 + Demo/CORTEX_EFMG890F128_IAR/cspycomm.log | 444 + .../lcd/lcdcontroller.c | 542 + .../lcd/lcdcontroller.h | 73 + Demo/CORTEX_EFMG890F128_IAR/lcd/lcddisplay.h | 391 + Demo/CORTEX_EFMG890F128_IAR/lcdtest.c | 125 + Demo/CORTEX_EFMG890F128_IAR/lcdtest.h | 14 + Demo/CORTEX_EFMG890F128_IAR/ledtest.c | 83 + Demo/CORTEX_EFMG890F128_IAR/ledtest.h | 66 + Demo/CORTEX_EFMG890F128_IAR/main.c | 271 + .../settings/RTOSDemo.cspy.bat | 33 + .../settings/RTOSDemo.dbgdt | 79 + .../settings/RTOSDemo.dni | 90 + .../settings/RTOSDemo.wsdt | 77 + .../settings/RTOSDemo_Debug.jlink | 14 + Demo/CORTEX_EFMG890F128_IAR/startup_efm32.s | 323 + 38 files changed, 23563 insertions(+) create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32g890f128.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/CMSIS changes.htm create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/CMSIS debug support.htm create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/Documentation/CMSIS_Core.htm create mode 100644 Demo/CORTEX_EFMG890F128_IAR/CMSIS/License.doc create mode 100644 Demo/CORTEX_EFMG890F128_IAR/FreeRTOSConfig.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/ParTest.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewd create mode 100644 Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewp create mode 100644 Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.eww create mode 100644 Demo/CORTEX_EFMG890F128_IAR/bsp/chip.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_bcregisters.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_boardcontrol.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_boardcontrol.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_ebi.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_spi.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/cspycomm.log create mode 100644 Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/lcd/lcddisplay.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/lcdtest.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/lcdtest.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/ledtest.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/ledtest.h create mode 100644 Demo/CORTEX_EFMG890F128_IAR/main.c create mode 100644 Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.cspy.bat create mode 100644 Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dbgdt create mode 100644 Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dni create mode 100644 Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.wsdt create mode 100644 Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo_Debug.jlink create mode 100644 Demo/CORTEX_EFMG890F128_IAR/startup_efm32.s diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.c b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.c new file mode 100644 index 000000000..56fddc52b --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.c @@ -0,0 +1,784 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.h b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.h new file mode 100644 index 000000000..2b6b51a7d --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32.h b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32.h new file mode 100644 index 000000000..9518d72f2 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32.h @@ -0,0 +1,109 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 Gxxx Device series + * + * This is a convenience header file for defining the EFM32 part number on the + * build command line, instead of specifying the part specific header file. + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "EFM32G.h" to your source files + * @endverbatim + * @author Energy Micro AS + * @version 1.0.2 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef __EFM32_H +#define __EFM32_H + +#if defined(EFM32G200F16) +#include "efm32g200f16.h" + +#elif defined(EFM32G200F32) +#include "efm32g200f32.h" + +#elif defined(EFM32G200F64) +#include "efm32g200f64.h" + +#elif defined(EFM32G210F128) +#include "efm32g210f128.h" + +#elif defined(EFM32G230F128) +#include "efm32g230f128.h" + +#elif defined(EFM32G230F32) +#include "efm32g230f32.h" + +#elif defined(EFM32G230F64) +#include "efm32g230f64.h" + +#elif defined(EFM32G280F128) +#include "efm32g280f128.h" + +#elif defined(EFM32G280F32) +#include "efm32g280f32.h" + +#elif defined(EFM32G280F64) +#include "efm32g280f64.h" + +#elif defined(EFM32G290F128) +#include "efm32g290f128.h" + +#elif defined(EFM32G290F32) +#include "efm32g290f32.h" + +#elif defined(EFM32G290F64) +#include "efm32g290f64.h" + +#elif defined(EFM32G840F128) +#include "efm32g840f128.h" + +#elif defined(EFM32G840F32) +#include "efm32g840f32.h" + +#elif defined(EFM32G840F64) +#include "efm32g840f64.h" + +#elif defined(EFM32G880F128) +#include "efm32g880f128.h" + +#elif defined(EFM32G880F32) +#include "efm32g880f32.h" + +#elif defined(EFM32G880F64) +#include "efm32g880f64.h" + +#elif defined(EFM32G890F128) +#include "efm32g890f128.h" + +#elif defined(EFM32G890F32) +#include "efm32g890f32.h" + +#elif defined(EFM32G890F64) +#include "efm32g890f64.h" + +#else +#error "efm32.h: PART NUMBER undefined" +#endif + +#endif diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32g890f128.h b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32g890f128.h new file mode 100644 index 000000000..7d4def48a --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32g890f128.h @@ -0,0 +1,11665 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM EFM32G890F128 + * @author Energy Micro AS + * @version 1.0.2 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef __EFM32G890F128_H +#define __EFM32G890F128_H + +/**************************************************************************//** + * + * @defgroup EFM32G890F128 EFM32G890F128 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** EFM32G Peripheral Interrupt Numbers **************************************************/ + DMA_IRQn = 0, /*!< DMA Interrupt */ + GPIO_EVEN_IRQn = 1, /*!< GPIO_EVEN Interrupt */ + TIMER0_IRQn = 2, /*!< TIMER0 Interrupt */ + USART0_RX_IRQn = 3, /*!< USART0_RX Interrupt */ + USART0_TX_IRQn = 4, /*!< USART0_TX Interrupt */ + ACMP0_IRQn = 5, /*!< ACMP0 Interrupt */ + ADC0_IRQn = 6, /*!< ADC0 Interrupt */ + DAC0_IRQn = 7, /*!< DAC0 Interrupt */ + I2C0_IRQn = 8, /*!< I2C0 Interrupt */ + GPIO_ODD_IRQn = 9, /*!< GPIO_ODD Interrupt */ + TIMER1_IRQn = 10, /*!< TIMER1 Interrupt */ + TIMER2_IRQn = 11, /*!< TIMER2 Interrupt */ + USART1_RX_IRQn = 12, /*!< USART1_RX Interrupt */ + USART1_TX_IRQn = 13, /*!< USART1_TX Interrupt */ + USART2_RX_IRQn = 14, /*!< USART2_RX Interrupt */ + USART2_TX_IRQn = 15, /*!< USART2_TX Interrupt */ + UART0_RX_IRQn = 16, /*!< UART0_RX Interrupt */ + UART0_TX_IRQn = 17, /*!< UART0_TX Interrupt */ + LEUART0_IRQn = 18, /*!< LEUART0 Interrupt */ + LEUART1_IRQn = 19, /*!< LEUART1 Interrupt */ + LETIMER0_IRQn = 20, /*!< LETIMER0 Interrupt */ + PCNT0_IRQn = 21, /*!< PCNT0 Interrupt */ + PCNT1_IRQn = 22, /*!< PCNT1 Interrupt */ + PCNT2_IRQn = 23, /*!< PCNT2 Interrupt */ + RTC_IRQn = 24, /*!< RTC Interrupt */ + CMU_IRQn = 25, /*!< CMU Interrupt */ + VCMP_IRQn = 26, /*!< VCMP Interrupt */ + LCD_IRQn = 27, /*!< LCD Interrupt */ + MSC_IRQn = 28, /*!< MSC Interrupt */ + AES_IRQn = 29, /*!< AES Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFM32G890F128_Core EFM32G890F128 Core + * @{ + *****************************************************************************/ + +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __NVIC_PRIO_BITS 3 /**< NVIC intterupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** + * @} + */ + +/**************************************************************************//** +* @defgroup EFM32G890F128_Part EFM32G890F128 Part +* @{ +******************************************************************************/ + +#if !defined(EFM32G890F128) +#define EFM32G890F128 +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32G890F128" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */ +#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */ +#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */ +#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */ +#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */ +#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ +#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */ +#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ + +/** Flash and SRAM limits for EFM32G890F128 */ +#define FLASH_SIZE 0x00020000UL /**< Available flash memory */ +#define SRAM_SIZE 0x00004000UL /**< Available sram memory */ +#define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */ +#define DPI_CHAN_COUNT 8 /**< Number of DPI channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +/* Part number capabilities */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 +#define TIMER_PARAM_DTI(i) (i == 0 ? 1 : i == 1 ? 0 : i == 2 ? 0 : 0) +#define TIMER_PARAM_CCNUM(i) (i == 0 ? 3 : i == 1 ? 3 : i == 2 ? 3 : 0) +#define USART_PRESENT +#define USART_COUNT 3 +#define USART_PARAM_SC_AVAILABLE(i) (i == 0 ? 1 : i == 1 ? 1 : i == 2 ? 1 : 0) +#define USART_PARAM_IRDA_AVAILABLE(i) (i == 0 ? 1 : i == 1 ? 0 : i == 2 ? 0 : 0) +#define USART_PARAM_FULL_DATABIT_RANGE(i) (i == 0 ? 1 : i == 1 ? 1 : i == 2 ? 1 : 0) +#define USART_PARAM_SYNC_AVAILABLE(i) (i == 0 ? 1 : i == 1 ? 1 : i == 2 ? 1 : 0) +#define UART_PRESENT +#define UART_COUNT 1 +#define UART_PARAM_SC_AVAILABLE(i) (i == 0 ? 0 : 0) +#define UART_PARAM_IRDA_AVAILABLE(i) (i == 0 ? 0 : 0) +#define UART_PARAM_FULL_DATABIT_RANGE(i) (i == 0 ? 0 : 0) +#define UART_PARAM_SYNC_AVAILABLE(i) (i == 0 ? 0 : 0) +#define LEUART_PRESENT +#define LEUART_COUNT 2 +#define LETIMER_PRESENT +#define LETIMER_COUNT 1 +#define PCNT_PRESENT +#define PCNT_COUNT 3 +#define PCNT_PARAM_PCNT_WIDTH(i) (i == 0 ? 16 : i == 1 ? 8 : i == 2 ? 8 : 0) +#define I2C_PRESENT +#define I2C_COUNT 1 +#define ADC_PRESENT +#define ADC_COUNT 1 +#define ADC_PARAM_RES(i) (i == 0 ? 12 : 0) +#define DAC_PRESENT +#define DAC_COUNT 1 +#define DAC_PARAM_RES(i) (i == 0 ? 12 : 0) +#define ACMP_PRESENT +#define ACMP_COUNT 2 +#define CM3_PRESENT +#define CM3_COUNT 1 +#define CM3_FREE_PRESENT +#define CM3_FREE_COUNT 1 +#define BUSMATRIX_PRESENT +#define BUSMATRIX_COUNT 1 +#define DMEM_PRESENT +#define DMEM_COUNT 1 +#define AHB2APB_PRESENT +#define AHB2APB_COUNT 1 +#define LE_PRESENT +#define LE_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define AES_PRESENT +#define AES_COUNT 1 +#define EBI_PRESENT +#define EBI_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define DMA_PRESENT +#define DMA_COUNT 1 +#define VCMP_PRESENT +#define VCMP_COUNT 1 +#define LCD_PRESENT +#define LCD_COUNT 1 +#define LCD_PARAM_SEG_NUM 40 +#define LCD_PARAM_COM_NUM 4 +#define RTC_PRESENT +#define RTC_COUNT 1 +#define HFXTAL_PRESENT +#define HFXTAL_COUNT 1 +#define LFXTAL_PRESENT +#define LFXTAL_COUNT 1 +#define WDOG_PRESENT +#define WDOG_COUNT 1 +#define DBG_PRESENT +#define DBG_COUNT 1 +#define TMODE_PRESENT +#define TMODE_COUNT 1 +#define SCAN_PRESENT +#define SCAN_COUNT 1 + +/** + * @} + */ + +/* Include CMSIS core functionality */ +#include "core_cm3.h" +#include "system_efm32.h" +#include + +/**************************************************************************//** + * + * @defgroup EFM32G890F128_Peripheral_TypeDefs EFM32G890F128 Peripheral TypeDefs + * @{ + * + *****************************************************************************/ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_MSC + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Memory System Control Register */ + __IO uint32_t READCTRL; /**< Read Control Register */ + __IO uint32_t WRITECTRL; /**< Write Control Register */ + __O uint32_t WRITECMD; /**< Write Command Register */ + __IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IO uint32_t WDATA; /**< Write Data Register */ + __I uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[3]; /**< Reserved for future use **/ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __IO uint32_t LOCK; /**< Configuration Lock Register */ +} MSC_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_EMU + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __IO uint32_t MEMCTRL; /**< Memory Control Register */ + __IO uint32_t LOCK; /**< Configuration Lock Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IO uint32_t ATESTCTRL; /**< Analog Test Control Register */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IO uint32_t AUXCTRL; /**< Auxiliary Control Register */ +} EMU_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_RMU + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __I uint32_t RSTCAUSE; /**< Reset Cause Register */ + __O uint32_t CMD; /**< Command Register */ +} RMU_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_CMU + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< CMU Control Register */ + __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */ + __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */ + __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + __IO uint32_t CALCTRL; /**< Calibration Control Register */ + __IO uint32_t CALCNT; /**< Calibration Counter Register */ + __O uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __O uint32_t CMD; /**< Command Register */ + __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */ + __I uint32_t STATUS; /**< Status Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */ + __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IO uint32_t FREEZE; /**< Freeze Register */ + __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 */ + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 */ + uint32_t RESERVED4[1]; /**< Reserved for future use **/ + __IO uint32_t PCNTCTRL; /**< PCNT Control Register */ + __IO uint32_t LCDCTRL; /**< LCD Control Register */ + __IO uint32_t ROUTE; /**< I/O Routing Register */ + __IO uint32_t LOCK; /**< Configuration Lock Register */ +} CMU_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_AES + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __O uint32_t CMD; /**< Command Register */ + __I uint32_t STATUS; /**< Status Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t DATA; /**< DATA Register */ + __IO uint32_t XORDATA; /**< XORDATA Register */ + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IO uint32_t KEYLA; /**< KEY Low Register */ + __IO uint32_t KEYLB; /**< KEY Low Register */ + __IO uint32_t KEYLC; /**< KEY Low Register */ + __IO uint32_t KEYLD; /**< KEY Low Register */ + __IO uint32_t KEYHA; /**< KEY High Register */ + __IO uint32_t KEYHB; /**< KEY High Register */ + __IO uint32_t KEYHC; /**< KEY High Register */ + __IO uint32_t KEYHD; /**< KEY High Register */ +} AES_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_EBI + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __IO uint32_t ADDRTIMING; /**< Address Timing Register */ + __IO uint32_t RDTIMING; /**< Read Timing Register */ + __IO uint32_t WRTIMING; /**< Write Timing Register */ + __IO uint32_t POLARITY; /**< Polarity Register */ + __IO uint32_t ROUTE; /**< I/O Routing Register */ +} EBI_TypeDef; /** @} */ + +/**************************************************************************//** + * + * P + * + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Port Control Register */ + __IO uint32_t MODEL; /**< Port Pin Mode Low Register */ + __IO uint32_t MODEH; /**< Port Pin Mode High Register */ + __IO uint32_t DOUT; /**< Port Data Out Register */ + __O uint32_t DOUTSET; /**< Port Data Out Set Register */ + __O uint32_t DOUTCLR; /**< Port Data Out Clear Register */ + __O uint32_t DOUTTGL; /**< Port Data Out Toggle Register */ + __I uint32_t DIN; /**< Port Data In Register */ + __IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */ +} GPIO_P_TypeDef; + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_GPIO + * @{ + *****************************************************************************/ +typedef struct +{ + GPIO_P_TypeDef P[6]; /**< Port configuration bits */ + + uint32_t RESERVED0[10]; /**< Reserved for future use **/ + __IO uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */ + __IO uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */ + __IO uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */ + __IO uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + + __IO uint32_t ROUTE; /**< I/O Routing Register */ + __IO uint32_t INSENSE; /**< Input Sense Register */ + __IO uint32_t LOCK; /**< Configuration Lock Register */ +} GPIO_TypeDef; /** @} */ + +/**************************************************************************//** + * + * CH + * + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Channel Control Register */ +} PRS_CH_TypeDef; + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_PRS + * @{ + *****************************************************************************/ +typedef struct +{ + __O uint32_t SWPULSE; /**< Software Pulse Register */ + __IO uint32_t SWLEVEL; /**< Software Level Register */ + + uint32_t RESERVED0[2]; /**< Reserved registers */ + + PRS_CH_TypeDef CH[8]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +/**************************************************************************//** + * + * CH + * + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Channel Control Register */ +} DMA_CH_TypeDef; + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_DMA + * @{ + *****************************************************************************/ +typedef struct +{ + __I uint32_t STATUS; /**< DMA Status Registers */ + __IO uint32_t CONFIG; /**< DMA Configuration Register */ + __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */ + __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */ + __I uint32_t WAITSTATUS; /**< Channel Wait on Request Status Register */ + __O uint32_t CHSWREQ; /**< Channel Software Request Register */ + __O uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */ + __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */ + __O uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */ + __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */ + __O uint32_t CHENS; /**< Channel Enable Set Register */ + __O uint32_t CHENC; /**< Channel Enable Clear Register */ + __O uint32_t CHALTS; /**< Channel Alternate Set Register */ + __O uint32_t CHALTC; /**< Channel Alternate Clear Register */ + __O uint32_t CHPRIS; /**< Channel Priority Set Register */ + __O uint32_t CHPRIC; /**< Channel Priority Clear Register */ + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IO uint32_t ERRORC; /**< Bus Error Clear Register */ + + uint32_t RESERVED1[1004]; /**< Reserved for future use **/ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable register */ + + uint32_t RESERVED2[60]; /**< Reserved registers */ + + DMA_CH_TypeDef CH[8]; /**< Channel registers */ +} DMA_TypeDef; /** @} */ + +/**************************************************************************//** + * + * CC + * + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< CC Channel Control Register */ + __IO uint32_t CCV; /**< CC Channel Value Register */ + __I uint32_t CCVP; /**< CC Channel Value Peek Register */ + __IO uint32_t CCVB; /**< CC Channel Buffer Register */ +} TIMER_CC_TypeDef; + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_TIMER + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __O uint32_t CMD; /**< Command Register */ + __I uint32_t STATUS; /**< Status Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t TOP; /**< Counter Top Value Register */ + __IO uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IO uint32_t CNT; /**< Counter Value Register */ + __IO uint32_t ROUTE; /**< I/O Routing Register */ + + uint32_t RESERVED0[1]; /**< Reserved registers */ + + TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IO uint32_t DTCTRL; /**< DTI Control Register */ + __IO uint32_t DTTIME; /**< DTI Time Control Register */ + __IO uint32_t DTFC; /**< DTI Fault Configuration Register */ + __IO uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IO uint32_t DTFAULT; /**< DTI Fault Register */ + __O uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IO uint32_t DTLOCK; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_USART + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __IO uint32_t FRAME; /**< USART Frame Format Register */ + __IO uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __O uint32_t CMD; /**< Command Register */ + __I uint32_t STATUS; /**< USART Status Register */ + __IO uint32_t CLKDIV; /**< Clock Control Register */ + __I uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __I uint32_t RXDATA; /**< RX Buffer Data Register */ + __I uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __I uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __I uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __I uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ + __O uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __O uint32_t TXDATA; /**< TX Buffer Data Register */ + __O uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __O uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __IO uint32_t IRCTRL; /**< IrDA Control Register */ + __IO uint32_t ROUTE; /**< I/O Routing Register */ +} USART_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_LEUART + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __O uint32_t CMD; /**< Command Register */ + __I uint32_t STATUS; /**< Status Register */ + __IO uint32_t CLKDIV; /**< Clock Control Register */ + __IO uint32_t STARTFRAME; /**< Start Frame Register */ + __IO uint32_t SIGFRAME; /**< Signal Frame Register */ + __I uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */ + __I uint32_t RXDATA; /**< Receive Buffer Data Register */ + __I uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */ + __O uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */ + __O uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __IO uint32_t PULSECTRL; /**< Pulse Control Register */ + + __IO uint32_t FREEZE; /**< Freeze Register */ + __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IO uint32_t ROUTE; /**< I/O Routing Register */ +} LEUART_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_LETIMER + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __O uint32_t CMD; /**< Command Register */ + __I uint32_t STATUS; /**< Status Register */ + __I uint32_t CNT; /**< Counter Value Register */ + __IO uint32_t COMP0; /**< Compare Value Register 0 */ + __IO uint32_t COMP1; /**< Compare Value Register 1 */ + __IO uint32_t REP0; /**< Repeat Counter Register 0 */ + __IO uint32_t REP1; /**< Repeat Counter Register 1 */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + + __IO uint32_t FREEZE; /**< Freeze Register */ + __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IO uint32_t ROUTE; /**< I/O Routing Register */ +} LETIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_PCNT + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __O uint32_t CMD; /**< Command Register */ + __I uint32_t STATUS; /**< Status Register */ + __I uint32_t CNT; /**< Counter Value Register */ + __I uint32_t TOP; /**< Top Value Register */ + __IO uint32_t TOPB; /**< Top Value Buffer Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __IO uint32_t ROUTE; /**< I/O Routing Register */ + + __IO uint32_t FREEZE; /**< Freeze Register */ + __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ +} PCNT_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_I2C + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __O uint32_t CMD; /**< Command Register */ + __I uint32_t STATE; /**< State Register */ + __I uint32_t STATUS; /**< Status Register */ + __IO uint32_t CLKDIV; /**< Clock Division Register */ + __IO uint32_t SADDR; /**< Slave Address Register */ + __IO uint32_t SADDRMASK; /**< Slave Address Mask Register */ + __I uint32_t RXDATA; /**< Receive Buffer Data Register */ + __I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __O uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __IO uint32_t ROUTE; /**< I/O Routing Register */ +} I2C_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_ADC + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __O uint32_t CMD; /**< Command Register */ + __I uint32_t STATUS; /**< Status Register */ + __IO uint32_t SINGLECTRL; /**< Single Sample Control Register */ + __IO uint32_t SCANCTRL; /**< Scan Control Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __I uint32_t SINGLEDATA; /**< Single Conversion Result Data */ + __I uint32_t SCANDATA; /**< Scan Conversion Result Data */ + __I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */ + __I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */ + __IO uint32_t CAL; /**< Calibration Register */ + __IO uint32_t ROUTE; /**< I/O Routing Register */ + __IO uint32_t BIASPROG; /**< Bias Programming Register */ +} ADC_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_DAC + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __I uint32_t STATUS; /**< Status Register */ + __IO uint32_t CH0CTRL; /**< Channel 0 Control Register */ + __IO uint32_t CH1CTRL; /**< Channel 1 Control Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t CH0DATA; /**< Channel 0 Data Register */ + __IO uint32_t CH1DATA; /**< Channel 1 Data Register */ + __O uint32_t COMBDATA; /**< Combined Data Register */ + __IO uint32_t CAL; /**< Calibration Register */ + __IO uint32_t BIASPROG; /**< Bias Programming Register */ +} DAC_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_ACMP + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __IO uint32_t INPUTSEL; /**< Input Selection Register */ + __I uint32_t STATUS; /**< Status Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t ROUTE; /**< I/O Routing Register */ +} ACMP_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_VCMP + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __IO uint32_t INPUTSEL; /**< Input Selection Register */ + __I uint32_t STATUS; /**< Status Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ +} VCMP_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_LCD + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __IO uint32_t DISPCTRL; /**< Display Control Register */ + __IO uint32_t SEGEN; /**< Segment Enable Register */ + __IO uint32_t BACTRL; /**< Blink and Animation Control Register */ + __I uint32_t STATUS; /**< Status Register */ + __IO uint32_t AREGA; /**< Animation Register A */ + __IO uint32_t AREGB; /**< Animation Register B */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED0[5]; /**< Reserved for future use **/ + __IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */ + __IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */ + __IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */ + __IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */ + __IO uint32_t SEGD0H; /**< Segment Data High Register 0 */ + __IO uint32_t SEGD1H; /**< Segment Data High Register 1 */ + __IO uint32_t SEGD2H; /**< Segment Data High Register 2 */ + __IO uint32_t SEGD3H; /**< Segment Data High Register 3 */ + + __IO uint32_t FREEZE; /**< Freeze Register */ + __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ +} LCD_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_RTC + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __I uint32_t CNT; /**< Counter Value Register */ + __IO uint32_t COMP0; /**< Compare Value Register 0 */ + __IO uint32_t COMP1; /**< Compare Value Register 1 */ + __I uint32_t IF; /**< Interrupt Flag Register */ + __O uint32_t IFS; /**< Interrupt Flag Set Register */ + __O uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IO uint32_t IEN; /**< Interrupt Enable Register */ + + __IO uint32_t FREEZE; /**< Freeze Register */ + __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ +} RTC_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_WDOG + * @{ + *****************************************************************************/ +typedef struct +{ + __IO uint32_t CTRL; /**< Control Register */ + __O uint32_t CMD; /**< Command Register */ + + __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ +} WDOG_TypeDef; /** @} */ + +/** + * @} + */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_DEVINFO + * @{ + *****************************************************************************/ +typedef struct +{ + __I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ + __I uint32_t UNIQUEH; /**< High 32 bits of device unique number */ + __I uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */ + __I uint32_t PART; /**< Part description */ +} DEVINFO_TypeDef; /** @} */ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_CALIBRATE + * @{ + *****************************************************************************/ +#define CALIBRATE_MAX_REGISTERS 50 /**< Max number of address/value pairs for calibration */ + +typedef struct +{ + __I uint32_t ADDRESS; /**< Address of calibration register */ + __I uint32_t VALUE; /**< Default value for calibration register */ +} CALIBRATE_TypeDef; /** @} */ + +/** Special calibration registers */ +#define HFRCO_CALIBH (*(volatile uint32_t *) 0x0FE081DCUL) /**< Calibration value for HFRCO 28 Mhz */ +#define HFRCO_CALIBL (*(volatile uint32_t *) 0x0FE081E0UL) /**< Calibration value for HFRCO 1/7/11/21 Mhz */ +#define ADC_CALIB (*(volatile uint32_t *) 0x0FE081E4UL) /**< ADC temperature for calibration and result */ + +/**************************************************************************//** + * + * @defgroup EFM32G890F128_Peripheral_Base EFM32G890F128 Peripheral Base Addresses + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400C0000) /**< MSC base address */ +#define EMU_BASE (0x400C6000) /**< EMU base address */ +#define RMU_BASE (0x400CA000) /**< RMU base address */ +#define CMU_BASE (0x400C8000) /**< CMU base address */ +#define AES_BASE (0x400E0000) /**< AES base address */ +#define EBI_BASE (0x40008000) /**< EBI base address */ +#define GPIO_BASE (0x40006000) /**< GPIO base address */ +#define PRS_BASE (0x400CC000) /**< PRS base address */ +#define DMA_BASE (0x400C2000) /**< DMA base address */ +#define TIMER0_BASE (0x40010000) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40010400) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40010800) /**< TIMER2 base address */ +#define USART0_BASE (0x4000C000) /**< USART0 base address */ +#define USART1_BASE (0x4000C400) /**< USART1 base address */ +#define USART2_BASE (0x4000C800) /**< USART2 base address */ +#define UART0_BASE (0x4000E000) /**< UART0 base address */ +#define LEUART0_BASE (0x40084000) /**< LEUART0 base address */ +#define LEUART1_BASE (0x40084400) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40082000) /**< LETIMER0 base address */ +#define PCNT0_BASE (0x40086000) /**< PCNT0 base address */ +#define PCNT1_BASE (0x40086400) /**< PCNT1 base address */ +#define PCNT2_BASE (0x40086800) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000A000) /**< I2C0 base address */ +#define ADC0_BASE (0x40002000) /**< ADC0 base address */ +#define DAC0_BASE (0x40004000) /**< DAC0 base address */ +#define ACMP0_BASE (0x40001000) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40001400) /**< ACMP1 base address */ +#define VCMP_BASE (0x40000000) /**< VCMP base address */ +#define LCD_BASE (0x4008A000) /**< LCD base address */ +#define RTC_BASE (0x40080000) /**< RTC base address */ +#define WDOG_BASE (0x40088000) /**< WDOG base address */ +#define DEVINFO_BASE (0x0FE081F0UL) /**< DEVINFO base address */ +#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */ +/** + * @} + */ + +/**************************************************************************//** + * + * @defgroup EFM32G890F128_Peripheral_Declaration EFM32G890F128 Peripheral Declaration + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */ +/** + * @} + */ + +/**************************************************************************//** + * + * @defgroup EFM32G890F128_BitFields EFM32G890F128 Bit Fields + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * + * @addtogroup EFM32G890F128_PRS + * @{ + *****************************************************************************/ + +#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */ +#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */ +#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */ +#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */ +#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */ +#define PRS_USART1_IRTX ((17 << 16) + 0) /**< PRS USART 1 IRDA out */ +#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */ +#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */ +#define PRS_USART2_IRTX ((18 << 16) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */ +#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */ +#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */ +#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */ +#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */ +#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */ +#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */ +#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */ +#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */ +#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */ +#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */ +#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */ +#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */ +#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */ +#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */ +#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */ +#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */ +#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */ +#define PRS_UART0_IRTX ((41 << 16) + 0) /**< PRS USART 0 IRDA out */ +#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */ +#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */ +#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */ + +/** + * @} + */ + +/**************************************************************************//** + * + * @defgroup EFM32G890F128_DMA_Channel_Select EFM32G890F128 DMA Channel Select + * @{ + *****************************************************************************/ +#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ +#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ +#define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */ +#define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */ +#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ +#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ +#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ +#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ +#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ +#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ +#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ +#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ +#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ +#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ +#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ +#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ +#define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */ +#define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */ +#define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */ +#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ +#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ +#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ +#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ +#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ +#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ +#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ +#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ +#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ +#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ +#define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */ +#define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */ +#define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */ +#define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */ +#define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */ +#define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */ +#define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */ +#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ +#define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */ +#define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */ +#define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */ +#define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_TIMER + * @{ + */ + +/** Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0F030FFBUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define TIMER_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UP (0x00000000UL << 0) /**< Shifted mode UP for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DOWN (0x00000001UL << 0) /**< Shifted mode DOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UPDOWN (0x00000002UL << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_QDEC (0x00000003UL << 0) /**< Shifted mode QDEC for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_SYNC (1 << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define TIMER_CTRL_SYNC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN (1 << 4) /**< One-shot Mode Enable */ +#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define TIMER_CTRL_OSMEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QEM (1 << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CTRL_QEM_SHIFT 5 /**< Shift value for TIMER_QEM */ +#define _TIMER_CTRL_QEM_MASK 0x20UL /**< Bit mask for TIMER_QEM */ +#define TIMER_CTRL_QEM_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QEM_X2 (0x00000000UL << 5) /**< Shifted mode X2 for TIMER_CTRL */ +#define TIMER_CTRL_QEM_X4 (0x00000001UL << 5) /**< Shifted mode X4 for TIMER_CTRL */ +#define _TIMER_CTRL_QEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_QEM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */ +#define _TIMER_CTRL_QEM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN (1 << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define TIMER_CTRL_DEBUGRUN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT (1 << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define TIMER_CTRL_DMACLRACT_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define TIMER_CTRL_RISEA_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (0x00000000UL << 8) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (0x00000001UL << 8) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (0x00000002UL << 8) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (0x00000003UL << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define TIMER_CTRL_FALLA_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (0x00000000UL << 10) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (0x00000001UL << 10) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (0x00000002UL << 10) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (0x00000003UL << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define TIMER_CTRL_CLKSEL_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (0x00000000UL << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_CC1 (0x00000001UL << 16) /**< Shifted mode CC1 for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_TIMEROUF (0x00000002UL << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define TIMER_CTRL_PRESC_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1 (0x00000000UL << 24) /**< Shifted mode DIV1 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV2 (0x00000001UL << 24) /**< Shifted mode DIV2 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV4 (0x00000002UL << 24) /**< Shifted mode DIV4 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV8 (0x00000003UL << 24) /**< Shifted mode DIV8 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV16 (0x00000004UL << 24) /**< Shifted mode DIV16 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV32 (0x00000005UL << 24) /**< Shifted mode DIV32 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV64 (0x00000006UL << 24) /**< Shifted mode DIV64 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV128 (0x00000007UL << 24) /**< Shifted mode DIV128 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV256 (0x00000008UL << 24) /**< Shifted mode DIV256 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV512 (0x00000009UL << 24) /**< Shifted mode DIV512 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1024 (0x0000000AUL << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */ + +/** Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (1 << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define TIMER_CMD_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (1 << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define TIMER_CMD_STOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ + +/** Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070707UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (1 << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define TIMER_STATUS_RUNNING_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (1 << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define TIMER_STATUS_DIR_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (0x00000000UL << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (0x00000001UL << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (1 << 2) /**< TOPB Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define TIMER_STATUS_TOPBV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0 (1 << 8) /**< CC0 CCVB Valid */ +#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define TIMER_STATUS_CCVBV0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1 (1 << 9) /**< CC1 CCVB Valid */ +#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define TIMER_STATUS_CCVBV1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2 (1 << 10) /**< CC2 CCVB Valid */ +#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define TIMER_STATUS_CCVBV2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0 (1 << 16) /**< CC0 Input Capture Valid */ +#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define TIMER_STATUS_ICV0_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1 (1 << 17) /**< CC1 Input Capture Valid */ +#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define TIMER_STATUS_ICV1_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2 (1 << 18) /**< CC2 Input Capture Valid */ +#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define TIMER_STATUS_ICV2_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (1 << 24) /**< CC0 Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define TIMER_STATUS_CCPOL0_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (0x00000000UL << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (0x00000001UL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (1 << 25) /**< CC1 Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define TIMER_STATUS_CCPOL1_DEFAULT (0x00000000UL << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (0x00000000UL << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (0x00000001UL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (1 << 26) /**< CC2 Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define TIMER_STATUS_CCPOL2_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (0x00000000UL << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (0x00000001UL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ + +/** Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x00000773UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (1 << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define TIMER_IEN_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (1 << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define TIMER_IEN_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (1 << 4) /**< CC Channel 0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define TIMER_IEN_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (1 << 5) /**< CC Channel 1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define TIMER_IEN_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (1 << 6) /**< CC Channel 2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define TIMER_IEN_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Enable */ +#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define TIMER_IEN_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Enable */ +#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define TIMER_IEN_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Enable */ +#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define TIMER_IEN_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ + +/** Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x00000773UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (1 << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define TIMER_IF_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (1 << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define TIMER_IF_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (1 << 4) /**< CC Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define TIMER_IF_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (1 << 5) /**< CC Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define TIMER_IF_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (1 << 6) /**< CC Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define TIMER_IF_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define TIMER_IF_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define TIMER_IF_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define TIMER_IF_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ + +/** Bit fields for TIMER IFS */ +#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */ +#define _TIMER_IFS_MASK 0x00000773UL /**< Mask for TIMER_IFS */ +#define TIMER_IFS_OF (1 << 0) /**< Overflow Interrupt Flag Set */ +#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define TIMER_IFS_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF (1 << 1) /**< Underflow Interrupt Flag Set */ +#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define TIMER_IFS_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0 (1 << 4) /**< CC Channel 0 Interrupt Flag Set */ +#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define TIMER_IFS_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1 (1 << 5) /**< CC Channel 1 Interrupt Flag Set */ +#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define TIMER_IFS_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2 (1 << 6) /**< CC Channel 2 Interrupt Flag Set */ +#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define TIMER_IFS_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set */ +#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define TIMER_IFS_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set */ +#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define TIMER_IFS_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set */ +#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define TIMER_IFS_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ + +/** Bit fields for TIMER IFC */ +#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */ +#define _TIMER_IFC_MASK 0x00000773UL /**< Mask for TIMER_IFC */ +#define TIMER_IFC_OF (1 << 0) /**< Overflow Interrupt Flag Clear */ +#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define TIMER_IFC_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF (1 << 1) /**< Underflow Interrupt Flag Clear */ +#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define TIMER_IFC_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0 (1 << 4) /**< CC Channel 0 Interrupt Flag Clear */ +#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define TIMER_IFC_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1 (1 << 5) /**< CC Channel 1 Interrupt Flag Clear */ +#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define TIMER_IFC_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2 (1 << 6) /**< CC Channel 2 Interrupt Flag Clear */ +#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define TIMER_IFC_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear */ +#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define TIMER_IFC_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear */ +#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define TIMER_IFC_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear */ +#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define TIMER_IFC_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ + +/** Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (0x0000FFFFUL << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ + +/** Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ + +/** Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ + +/** Bit fields for TIMER ROUTE */ +#define _TIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTE */ +#define _TIMER_ROUTE_MASK 0x00030707UL /**< Mask for TIMER_ROUTE */ +#define _TIMER_ROUTE_CCPEN_SHIFT 0 /**< Shift value for TIMER_CCPEN */ +#define _TIMER_ROUTE_CCPEN_MASK 0x7UL /**< Bit mask for TIMER_CCPEN */ +#define TIMER_ROUTE_CCPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_ROUTE */ +#define _TIMER_ROUTE_CCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */ +#define _TIMER_ROUTE_CDTIPEN_SHIFT 8 /**< Shift value for TIMER_CDTIPEN */ +#define _TIMER_ROUTE_CDTIPEN_MASK 0x700UL /**< Bit mask for TIMER_CDTIPEN */ +#define TIMER_ROUTE_CDTIPEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_ROUTE */ +#define _TIMER_ROUTE_CDTIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_SHIFT 16 /**< Shift value for TIMER_LOCATION */ +#define _TIMER_ROUTE_LOCATION_MASK 0x30000UL /**< Bit mask for TIMER_LOCATION */ +#define TIMER_ROUTE_LOCATION_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC0 (0x00000000UL << 16) /**< Shifted mode LOC0 for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC1 (0x00000001UL << 16) /**< Shifted mode LOC1 for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC2 (0x00000002UL << 16) /**< Shifted mode LOC2 for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC3 (0x00000003UL << 16) /**< Shifted mode LOC3 for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTE */ + +/** Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F373F17UL /**< Mask for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define TIMER_CC_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OFF (0x00000000UL << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (0x00000001UL << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (0x00000002UL << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_PWM (0x00000003UL << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (1 << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST (1 << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define TIMER_CC_CTRL_COIST_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (0x00000000UL << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (0x00000001UL << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (0x00000002UL << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (0x00000003UL << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (0x00000000UL << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (0x00000001UL << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (0x00000002UL << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (0x00000003UL << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (0x00000000UL << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (0x00000001UL << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (0x00000002UL << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (0x00000003UL << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_MASK 0x70000UL /**< Bit mask for TIMER_PRSSEL */ +#define TIMER_CC_CTRL_PRSSEL_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (0x00000000UL << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (0x00000001UL << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (0x00000002UL << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (0x00000003UL << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (0x00000004UL << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (0x00000005UL << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (0x00000006UL << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (0x00000007UL << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL (1 << 20) /**< Input Selection */ +#define _TIMER_CC_CTRL_INSEL_SHIFT 20 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_MASK 0x100000UL /**< Bit mask for TIMER_INSEL */ +#define TIMER_CC_CTRL_INSEL_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PIN (0x00000000UL << 20) /**< Shifted mode PIN for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PRS (0x00000001UL << 20) /**< Shifted mode PRS for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT (1 << 21) /**< Digital Filter */ +#define _TIMER_CC_CTRL_FILT_SHIFT 21 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_MASK 0x200000UL /**< Bit mask for TIMER_FILT */ +#define TIMER_CC_CTRL_FILT_DEFAULT (0x00000000UL << 21) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DISABLE (0x00000000UL << 21) /**< Shifted mode DISABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_ENABLE (0x00000001UL << 21) /**< Shifted mode ENABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (0x00000000UL << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (0x00000001UL << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (0x00000002UL << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (0x00000003UL << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (0x00000000UL << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (0x00000001UL << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (0x00000002UL << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (0x00000003UL << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ + +/** Bit fields for TIMER CC_CCV */ +#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */ +#define TIMER_CC_CCV_CCV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */ + +/** Bit fields for TIMER CC_CCVP */ +#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */ +#define TIMER_CC_CCVP_CCVP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */ + +/** Bit fields for TIMER CC_CCVB */ +#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */ +#define TIMER_CC_CCVB_CCVB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */ + +/** Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x0100007FUL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN (1 << 0) /**< DTI Enable */ +#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define TIMER_DTCTRL_DTEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS (1 << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define TIMER_DTCTRL_DTDAS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_NORESTART (0x00000000UL << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_RESTART (0x00000001UL << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (1 << 2) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (1 << 3) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_MASK 0x70UL /**< Bit mask for TIMER_DTPRSSEL */ +#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN (1 << 24) /**< DTI PRS Source Enable */ +#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define TIMER_DTCTRL_DTPRSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ + +/** Bit fields for TIMER DTTIME */ +#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */ +#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define TIMER_DTTIME_DTPRESC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1 (0x00000000UL << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV2 (0x00000001UL << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV4 (0x00000002UL << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV8 (0x00000003UL << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV16 (0x00000004UL << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV32 (0x00000005UL << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV64 (0x00000006UL << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV128 (0x00000007UL << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV256 (0x00000008UL << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV512 (0x00000009UL << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1024 (0x0000000AUL << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define TIMER_DTTIME_DTRISET_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define TIMER_DTTIME_DTFALLT_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ + +/** Bit fields for TIMER DTFC */ +#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */ +#define _TIMER_DTFC_MASK 0x0F030707UL /**< Mask for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_SHIFT 0 /**< Shift value for TIMER_DTPRSFSEL0 */ +#define _TIMER_DTFC_DTPRSFSEL0_MASK 0x7UL /**< Bit mask for TIMER_DTPRSFSEL0 */ +#define TIMER_DTFC_DTPRSFSEL0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL0_PRSCH0 (0x00000000UL << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL0_PRSCH1 (0x00000001UL << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL0_PRSCH2 (0x00000002UL << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL0_PRSCH3 (0x00000003UL << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL0_PRSCH4 (0x00000004UL << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL0_PRSCH5 (0x00000005UL << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL0_PRSCH6 (0x00000006UL << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL0_PRSCH7 (0x00000007UL << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_SHIFT 8 /**< Shift value for TIMER_DTPRSFSEL1 */ +#define _TIMER_DTFC_DTPRSFSEL1_MASK 0x700UL /**< Bit mask for TIMER_DTPRSFSEL1 */ +#define TIMER_DTFC_DTPRSFSEL1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL1_PRSCH0 (0x00000000UL << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL1_PRSCH1 (0x00000001UL << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL1_PRSCH2 (0x00000002UL << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL1_PRSCH3 (0x00000003UL << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL1_PRSCH4 (0x00000004UL << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL1_PRSCH5 (0x00000005UL << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL1_PRSCH6 (0x00000006UL << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRSFSEL1_PRSCH7 (0x00000007UL << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRSFSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define TIMER_DTFC_DTFA_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_NONE (0x00000000UL << 16) /**< Shifted mode NONE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_INACTIVE (0x00000001UL << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_CLEAR (0x00000002UL << 16) /**< Shifted mode CLEAR for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_TRISTATE (0x00000003UL << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFSEN_SHIFT 24 /**< Shift value for TIMER_DTFSEN */ +#define _TIMER_DTFC_DTFSEN_MASK 0xF000000UL /**< Bit mask for TIMER_DTFSEN */ +#define TIMER_DTFC_DTFSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTFSEN_PRS0 (0x00000001UL << 24) /**< Shifted mode PRS0 for TIMER_DTFC */ +#define TIMER_DTFC_DTFSEN_PRS1 (0x00000002UL << 24) /**< Shifted mode PRS1 for TIMER_DTFC */ +#define TIMER_DTFC_DTFSEN_DEBUG (0x00000004UL << 24) /**< Shifted mode DEBUG for TIMER_DTFC */ +#define TIMER_DTFC_DTFSEN_LOCKUP (0x00000008UL << 24) /**< Shifted mode LOCKUP for TIMER_DTFC */ +#define _TIMER_DTFC_DTFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTFSEN_PRS0 0x00000001UL /**< Mode PRS0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTFSEN_PRS1 0x00000002UL /**< Mode PRS1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTFSEN_DEBUG 0x00000004UL /**< Mode DEBUG for TIMER_DTFC */ +#define _TIMER_DTFC_DTFSEN_LOCKUP 0x00000008UL /**< Mode LOCKUP for TIMER_DTFC */ + +/** Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_DTOGEN_SHIFT 0 /**< Shift value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_DTOGEN_MASK 0x3FUL /**< Bit mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGEN_CC0 (0x00000001UL << 0) /**< Shifted mode CC0 for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGEN_CC1 (0x00000002UL << 0) /**< Shifted mode CC1 for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGEN_CC2 (0x00000004UL << 0) /**< Shifted mode CC2 for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGEN_CDTI0 (0x00000008UL << 0) /**< Shifted mode CDTI0 for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGEN_CDTI1 (0x00000010UL << 0) /**< Shifted mode CDTI1 for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGEN_CDTI2 (0x00000020UL << 0) /**< Shifted mode CDTI2 for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_DTOGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_DTOGEN_CC0 0x00000001UL /**< Mode CC0 for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_DTOGEN_CC1 0x00000002UL /**< Mode CC1 for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_DTOGEN_CC2 0x00000004UL /**< Mode CC2 for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_DTOGEN_CDTI0 0x00000008UL /**< Mode CDTI0 for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_DTOGEN_CDTI1 0x00000010UL /**< Mode CDTI1 for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_DTOGEN_CDTI2 0x00000020UL /**< Mode CDTI2 for TIMER_DTOGEN */ + +/** Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_DTFS_SHIFT 0 /**< Shift value for TIMER_DTFS */ +#define _TIMER_DTFAULT_DTFS_MASK 0xFUL /**< Bit mask for TIMER_DTFS */ +#define TIMER_DTFAULT_DTFS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTFS_PRS0 (0x00000001UL << 0) /**< Shifted mode PRS0 for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTFS_PRS1 (0x00000002UL << 0) /**< Shifted mode PRS1 for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTFS_DEBUG (0x00000004UL << 0) /**< Shifted mode DEBUG for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTFS_LOCKUP (0x00000008UL << 0) /**< Shifted mode LOCKUP for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_DTFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_DTFS_PRS0 0x00000001UL /**< Mode PRS0 for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_DTFS_PRS1 0x00000002UL /**< Mode PRS1 for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_DTFS_DEBUG 0x00000004UL /**< Mode DEBUG for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_DTFS_LOCKUP 0x00000008UL /**< Mode LOCKUP for TIMER_DTFAULT */ + +/** Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_DTFSC_SHIFT 0 /**< Shift value for TIMER_DTFSC */ +#define _TIMER_DTFAULTC_DTFSC_MASK 0xFUL /**< Bit mask for TIMER_DTFSC */ +#define TIMER_DTFAULTC_DTFSC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTFSC_PRS0 (0x00000001UL << 0) /**< Shifted mode PRS0 for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTFSC_PRS1 (0x00000002UL << 0) /**< Shifted mode PRS1 for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTFSC_DEBUG (0x00000004UL << 0) /**< Shifted mode DEBUG for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTFSC_LOCKUP (0x00000008UL << 0) /**< Shifted mode LOCKUP for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_DTFSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_DTFSC_PRS0 0x00000001UL /**< Mode PRS0 for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_DTFSC_PRS1 0x00000002UL /**< Mode PRS1 for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_DTFSC_DEBUG 0x00000004UL /**< Mode DEBUG for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_DTFSC_LOCKUP 0x00000008UL /**< Mode LOCKUP for TIMER_DTFAULTC */ + +/** Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define TIMER_DTLOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCK (0x0000CE80UL << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_USART + * @{ + */ + +/** Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0x1DFFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (1 << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define USART_CTRL_SYNC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK (1 << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define USART_CTRL_LOOPBK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN (1 << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define USART_CTRL_CCEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM (1 << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define USART_CTRL_MPM_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB (1 << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define USART_CTRL_MPAB_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define USART_CTRL_OVS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (0x00000000UL << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (0x00000001UL << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (0x00000002UL << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (0x00000003UL << 5) /**< Shifted mode X4 for USART_CTRL */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (1 << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define USART_CTRL_CLKPOL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (0x00000000UL << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (0x00000001UL << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (1 << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define USART_CTRL_CLKPHA_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (0x00000000UL << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (0x00000001UL << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (1 << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define USART_CTRL_MSBF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA (1 << 11) /**< Action On Slave-Select In Master Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define USART_CTRL_CSMA_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (0x00000000UL << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (0x00000001UL << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (1 << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define USART_CTRL_TXBIL_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (0x00000000UL << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (0x00000001UL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (1 << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define USART_CTRL_RXINV_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV (1 << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define USART_CTRL_TXINV_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV (1 << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define USART_CTRL_CSINV_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS (1 << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define USART_CTRL_AUTOCS_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (1 << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define USART_CTRL_AUTOTRI_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE (1 << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define USART_CTRL_SCMODE_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (1 << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define USART_CTRL_SCRETRANS_DEFAULT (0x00000000UL << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (1 << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define USART_CTRL_SKIPPERRF_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (1 << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define USART_CTRL_BIT8DV_DEFAULT (0x00000000UL << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (1 << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define USART_CTRL_ERRSDMA_DEFAULT (0x00000000UL << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX (1 << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define USART_CTRL_ERRSRX_DEFAULT (0x00000000UL << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX (1 << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define USART_CTRL_ERRSTX_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */ +#define _USART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */ +#define USART_CTRL_TXDELAY_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXDELAY_NONE (0x00000000UL << 26) /**< Shifted mode NONE for USART_CTRL */ +#define USART_CTRL_TXDELAY_SINGLE (0x00000001UL << 26) /**< Shifted mode SINGLE for USART_CTRL */ +#define USART_CTRL_TXDELAY_DOUBLE (0x00000002UL << 26) /**< Shifted mode DOUBLE for USART_CTRL */ +#define USART_CTRL_TXDELAY_TRIPLE (0x00000003UL << 26) /**< Shifted mode TRIPLE for USART_CTRL */ +#define _USART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for USART_CTRL */ +#define _USART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for USART_CTRL */ +#define _USART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for USART_CTRL */ +#define _USART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP (1 << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define USART_CTRL_BYTESWAP_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ + +/** Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define USART_FRAME_DATABITS_FOUR (0x00000001UL << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (0x00000002UL << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (0x00000003UL << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (0x00000004UL << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (0x00000005UL << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (0x00000005UL << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (0x00000006UL << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (0x00000007UL << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (0x00000008UL << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (0x00000009UL << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (0x0000000AUL << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (0x0000000BUL << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (0x0000000CUL << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (0x0000000DUL << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define USART_FRAME_PARITY_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (0x00000000UL << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (0x00000002UL << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (0x00000003UL << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define USART_FRAME_STOPBITS_HALF (0x00000000UL << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (0x00000001UL << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (0x00000001UL << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (0x00000002UL << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (0x00000003UL << 12) /**< Shifted mode TWO for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ + +/** Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00000037UL /**< Mask for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */ +#define USART_TRIGCTRL_TSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH0 (0x00000000UL << 0) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH1 (0x00000001UL << 0) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH2 (0x00000002UL << 0) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH3 (0x00000003UL << 0) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH4 (0x00000004UL << 0) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH5 (0x00000005UL << 0) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH6 (0x00000006UL << 0) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH7 (0x00000007UL << 0) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (1 << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (1 << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ + +/** Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (1 << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define USART_CMD_RXEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (1 << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define USART_CMD_RXDIS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (1 << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define USART_CMD_TXEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (1 << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define USART_CMD_TXDIS_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (1 << 4) /**< Master Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define USART_CMD_MASTEREN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (1 << 5) /**< Master Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define USART_CMD_MASTERDIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (1 << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define USART_CMD_RXBLOCKEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (1 << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (1 << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define USART_CMD_TXTRIEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (1 << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define USART_CMD_TXTRIDIS_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (1 << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define USART_CMD_CLEARTX_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (1 << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define USART_CMD_CLEARRX_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_CMD */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ + +/** Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00000040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x000001FFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (1 << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define USART_STATUS_RXENS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (1 << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define USART_STATUS_TXENS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (1 << 2) /**< SPI Master Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define USART_STATUS_MASTER_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (1 << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define USART_STATUS_RXBLOCK_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (1 << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define USART_STATUS_TXTRI_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (1 << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define USART_STATUS_TXC_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (1 << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define USART_STATUS_TXBL_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (1 << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define USART_STATUS_RXDATAV_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (1 << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define USART_STATUS_RXFULL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ + +/** Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */ +#define USART_CLKDIV_DIV_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ + +/** Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define USART_RXDATAX_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (1 << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define USART_RXDATAX_PERR_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (1 << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define USART_RXDATAX_FERR_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ + +/** Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ + +/** Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (1 << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (1 << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (1 << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (1 << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ + +/** Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ + +/** Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (1 << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define USART_RXDATAXP_PERRP_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (1 << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define USART_RXDATAXP_FERRP_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ + +/** Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (1 << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (1 << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (1 << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (1 << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ + +/** Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (1 << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define USART_TXDATAX_UBRXAT_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (1 << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (1 << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define USART_TXDATAX_TXBREAK_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (1 << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define USART_TXDATAX_TXDISAT_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (1 << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define USART_TXDATAX_RXENAT_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ + +/** Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ + +/** Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (1 << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (1 << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (1 << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (1 << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (1 << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (1 << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (0x00000000UL << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (1 << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (1 << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (0x00000000UL << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (1 << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (1 << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ + +/** Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ + +/** Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x00001FFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (1 << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define USART_IF_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (1 << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define USART_IF_TXBL_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define USART_IF_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (1 << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define USART_IF_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (1 << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define USART_IF_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (1 << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define USART_IF_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (1 << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define USART_IF_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (1 << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define USART_IF_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR (1 << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define USART_IF_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR (1 << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define USART_IF_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (1 << 10) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define USART_IF_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM (1 << 11) /**< Slave-Select In Master Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define USART_IF_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF (1 << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define USART_IF_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ + +/** Bit fields for USART IFS */ +#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ +#define _USART_IFS_MASK 0x00001FF9UL /**< Mask for USART_IFS */ +#define USART_IFS_TXC (1 << 0) /**< Set TX Complete Interrupt Flag */ +#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define USART_IFS_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL (1 << 3) /**< Set RX Buffer Full Interrupt Flag */ +#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define USART_IFS_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF (1 << 4) /**< Set RX Overflow Interrupt Flag */ +#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define USART_IFS_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF (1 << 5) /**< Set RX Underflow Interrupt Flag */ +#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define USART_IFS_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF (1 << 6) /**< Set TX Overflow Interrupt Flag */ +#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define USART_IFS_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF (1 << 7) /**< Set TX Underflow Interrupt Flag */ +#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define USART_IFS_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR (1 << 8) /**< Set Parity Error Interrupt Flag */ +#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define USART_IFS_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR (1 << 9) /**< Set Framing Error Interrupt Flag */ +#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define USART_IFS_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF (1 << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */ +#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define USART_IFS_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM (1 << 11) /**< Set Slave-Select in Master mode Interrupt Flag */ +#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define USART_IFS_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF (1 << 12) /**< Set Collision Check Fail Interrupt Flag */ +#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define USART_IFS_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_IFS */ +#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ + +/** Bit fields for USART IFC */ +#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ +#define _USART_IFC_MASK 0x00001FF9UL /**< Mask for USART_IFC */ +#define USART_IFC_TXC (1 << 0) /**< Clear TX Complete Interrupt Flag */ +#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define USART_IFC_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL (1 << 3) /**< Clear RX Buffer Full Interrupt Flag */ +#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define USART_IFC_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF (1 << 4) /**< Clear RX Overflow Interrupt Flag */ +#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define USART_IFC_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF (1 << 5) /**< Clear RX Underflow Interrupt Flag */ +#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define USART_IFC_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF (1 << 6) /**< Clear TX Overflow Interrupt Flag */ +#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define USART_IFC_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF (1 << 7) /**< Clear TX Underflow Interrupt Flag */ +#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define USART_IFC_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR (1 << 8) /**< Clear Parity Error Interrupt Flag */ +#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define USART_IFC_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR (1 << 9) /**< Clear Framing Error Interrupt Flag */ +#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define USART_IFC_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF (1 << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */ +#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define USART_IFC_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM (1 << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */ +#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define USART_IFC_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF (1 << 12) /**< Clear Collision Check Fail Interrupt Flag */ +#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define USART_IFC_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_IFC */ +#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ + +/** Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x00001FFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (1 << 0) /**< TX Complete Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define USART_IEN_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (1 << 1) /**< TX Buffer Level Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define USART_IEN_TXBL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define USART_IEN_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (1 << 3) /**< RX Buffer Full Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define USART_IEN_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (1 << 4) /**< RX Overflow Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define USART_IEN_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (1 << 5) /**< RX Underflow Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define USART_IEN_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (1 << 6) /**< TX Overflow Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define USART_IEN_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (1 << 7) /**< TX Underflow Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define USART_IEN_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (1 << 8) /**< Parity Error Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define USART_IEN_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (1 << 9) /**< Framing Error Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define USART_IEN_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (1 << 10) /**< Multi-Processor Address Frame Interrupt Enable */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define USART_IEN_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (1 << 11) /**< Slave-Select In Master Mode Interrupt Enable */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define USART_IEN_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (1 << 12) /**< Collision Check Fail Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define USART_IEN_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ + +/** Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x000000FFUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (1 << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define USART_IRCTRL_IREN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define USART_IRCTRL_IRPW_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (0x00000000UL << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (0x00000001UL << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (0x00000002UL << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (0x00000003UL << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (1 << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define USART_IRCTRL_IRFILT_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */ +#define USART_IRCTRL_IRPRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN (1 << 7) /**< IrDA PRS Channel Enable */ +#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ +#define USART_IRCTRL_IRPRSEN_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ + +/** Bit fields for USART ROUTE */ +#define _USART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTE */ +#define _USART_ROUTE_MASK 0x0000030FUL /**< Mask for USART_ROUTE */ +#define USART_ROUTE_RXPEN (1 << 0) /**< RX Pin Enable */ +#define _USART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ +#define _USART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ +#define USART_ROUTE_RXPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_ROUTE */ +#define _USART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ +#define USART_ROUTE_TXPEN (1 << 1) /**< TX Pin Enable */ +#define _USART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ +#define _USART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ +#define USART_ROUTE_TXPEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_ROUTE */ +#define _USART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ +#define USART_ROUTE_CSPEN (1 << 2) /**< CS Pin Enable */ +#define _USART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ +#define _USART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ +#define USART_ROUTE_CSPEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_ROUTE */ +#define _USART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ +#define USART_ROUTE_CLKPEN (1 << 3) /**< RX Pin Enable */ +#define _USART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ +#define _USART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ +#define USART_ROUTE_CLKPEN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_ROUTE */ +#define _USART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ +#define _USART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */ +#define _USART_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for USART_LOCATION */ +#define USART_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_ROUTE */ +#define USART_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for USART_ROUTE */ +#define USART_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for USART_ROUTE */ +#define USART_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for USART_ROUTE */ +#define USART_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for USART_ROUTE */ +#define _USART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ +#define _USART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTE */ +#define _USART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTE */ +#define _USART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTE */ +#define _USART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTE */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_UART + * @{ + */ + +/** Bit fields for UART CTRL */ +#define _UART_CTRL_RESETVALUE 0x00000000UL /**< Default value for UART_CTRL */ +#define _UART_CTRL_MASK 0x1DFFFF7FUL /**< Mask for UART_CTRL */ +#define UART_CTRL_SYNC (1 << 0) /**< USART Synchronous Mode */ +#define _UART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _UART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define UART_CTRL_SYNC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_LOOPBK (1 << 1) /**< Loopback Enable */ +#define _UART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _UART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define UART_CTRL_LOOPBK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CCEN (1 << 2) /**< Collision Check Enable */ +#define _UART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _UART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define UART_CTRL_CCEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_MPM (1 << 3) /**< Multi-Processor Mode */ +#define _UART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _UART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define UART_CTRL_MPM_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_MPAB (1 << 4) /**< Multi-Processor Address-Bit */ +#define _UART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _UART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define UART_CTRL_MPAB_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _UART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define UART_CTRL_OVS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_OVS_X16 (0x00000000UL << 5) /**< Shifted mode X16 for UART_CTRL */ +#define UART_CTRL_OVS_X8 (0x00000001UL << 5) /**< Shifted mode X8 for UART_CTRL */ +#define UART_CTRL_OVS_X6 (0x00000002UL << 5) /**< Shifted mode X6 for UART_CTRL */ +#define UART_CTRL_OVS_X4 (0x00000003UL << 5) /**< Shifted mode X4 for UART_CTRL */ +#define _UART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for UART_CTRL */ +#define _UART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for UART_CTRL */ +#define _UART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for UART_CTRL */ +#define _UART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for UART_CTRL */ +#define UART_CTRL_CLKPOL (1 << 8) /**< Clock Polarity */ +#define _UART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _UART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define UART_CTRL_CLKPOL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CLKPOL_IDLELOW (0x00000000UL << 8) /**< Shifted mode IDLELOW for UART_CTRL */ +#define UART_CTRL_CLKPOL_IDLEHIGH (0x00000001UL << 8) /**< Shifted mode IDLEHIGH for UART_CTRL */ +#define _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for UART_CTRL */ +#define _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for UART_CTRL */ +#define UART_CTRL_CLKPHA (1 << 9) /**< Clock Edge For Setup/Sample */ +#define _UART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _UART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define UART_CTRL_CLKPHA_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CLKPHA_SAMPLELEADING (0x00000000UL << 9) /**< Shifted mode SAMPLELEADING for UART_CTRL */ +#define UART_CTRL_CLKPHA_SAMPLETRAILING (0x00000001UL << 9) /**< Shifted mode SAMPLETRAILING for UART_CTRL */ +#define _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for UART_CTRL */ +#define _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for UART_CTRL */ +#define UART_CTRL_MSBF (1 << 10) /**< Most Significant Bit First */ +#define _UART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _UART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define UART_CTRL_MSBF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CSMA (1 << 11) /**< Action On Slave-Select In Master Mode */ +#define _UART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _UART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define UART_CTRL_CSMA_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CSMA_NOACTION (0x00000000UL << 11) /**< Shifted mode NOACTION for UART_CTRL */ +#define UART_CTRL_CSMA_GOTOSLAVEMODE (0x00000001UL << 11) /**< Shifted mode GOTOSLAVEMODE for UART_CTRL */ +#define _UART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for UART_CTRL */ +#define _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for UART_CTRL */ +#define UART_CTRL_TXBIL (1 << 12) /**< TX Buffer Interrupt Level */ +#define _UART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _UART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define UART_CTRL_TXBIL_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_TXBIL_EMPTY (0x00000000UL << 12) /**< Shifted mode EMPTY for UART_CTRL */ +#define UART_CTRL_TXBIL_HALFFULL (0x00000001UL << 12) /**< Shifted mode HALFFULL for UART_CTRL */ +#define _UART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for UART_CTRL */ +#define _UART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for UART_CTRL */ +#define UART_CTRL_RXINV (1 << 13) /**< Receiver Input Invert */ +#define _UART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _UART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define UART_CTRL_RXINV_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_TXINV (1 << 14) /**< Transmitter output Invert */ +#define _UART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _UART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define UART_CTRL_TXINV_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CSINV (1 << 15) /**< Chip Select Invert */ +#define _UART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _UART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define UART_CTRL_CSINV_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_AUTOCS (1 << 16) /**< Automatic Chip Select */ +#define _UART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _UART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define UART_CTRL_AUTOCS_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_AUTOTRI (1 << 17) /**< Automatic TX Tristate */ +#define _UART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _UART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define UART_CTRL_AUTOTRI_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SCMODE (1 << 18) /**< SmartCard Mode */ +#define _UART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _UART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define UART_CTRL_SCMODE_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SCRETRANS (1 << 19) /**< SmartCard Retransmit */ +#define _UART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _UART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define UART_CTRL_SCRETRANS_DEFAULT (0x00000000UL << 19) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SKIPPERRF (1 << 20) /**< Skip Parity Error Frames */ +#define _UART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _UART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define UART_CTRL_SKIPPERRF_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_BIT8DV (1 << 21) /**< Bit 8 Default Value */ +#define _UART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _UART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define UART_CTRL_BIT8DV_DEFAULT (0x00000000UL << 21) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_ERRSDMA (1 << 22) /**< Halt DMA On Error */ +#define _UART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _UART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define UART_CTRL_ERRSDMA_DEFAULT (0x00000000UL << 22) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_ERRSRX (1 << 23) /**< Disable RX On Error */ +#define _UART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _UART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define UART_CTRL_ERRSRX_DEFAULT (0x00000000UL << 23) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_ERRSTX (1 << 24) /**< Disable TX On Error */ +#define _UART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _UART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define UART_CTRL_ERRSTX_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */ +#define _UART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */ +#define UART_CTRL_TXDELAY_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_TXDELAY_NONE (0x00000000UL << 26) /**< Shifted mode NONE for UART_CTRL */ +#define UART_CTRL_TXDELAY_SINGLE (0x00000001UL << 26) /**< Shifted mode SINGLE for UART_CTRL */ +#define UART_CTRL_TXDELAY_DOUBLE (0x00000002UL << 26) /**< Shifted mode DOUBLE for UART_CTRL */ +#define UART_CTRL_TXDELAY_TRIPLE (0x00000003UL << 26) /**< Shifted mode TRIPLE for UART_CTRL */ +#define _UART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for UART_CTRL */ +#define _UART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for UART_CTRL */ +#define _UART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for UART_CTRL */ +#define _UART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for UART_CTRL */ +#define UART_CTRL_BYTESWAP (1 << 28) /**< Byteswap In Double Accesses */ +#define _UART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _UART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define UART_CTRL_BYTESWAP_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ + +/** Bit fields for UART FRAME */ +#define _UART_FRAME_RESETVALUE 0x00001005UL /**< Default value for UART_FRAME */ +#define _UART_FRAME_MASK 0x0000330FUL /**< Mask for UART_FRAME */ +#define _UART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _UART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define UART_FRAME_DATABITS_FOUR (0x00000001UL << 0) /**< Shifted mode FOUR for UART_FRAME */ +#define UART_FRAME_DATABITS_FIVE (0x00000002UL << 0) /**< Shifted mode FIVE for UART_FRAME */ +#define UART_FRAME_DATABITS_SIX (0x00000003UL << 0) /**< Shifted mode SIX for UART_FRAME */ +#define UART_FRAME_DATABITS_SEVEN (0x00000004UL << 0) /**< Shifted mode SEVEN for UART_FRAME */ +#define UART_FRAME_DATABITS_DEFAULT (0x00000005UL << 0) /**< Shifted mode DEFAULT for UART_FRAME */ +#define UART_FRAME_DATABITS_EIGHT (0x00000005UL << 0) /**< Shifted mode EIGHT for UART_FRAME */ +#define UART_FRAME_DATABITS_NINE (0x00000006UL << 0) /**< Shifted mode NINE for UART_FRAME */ +#define UART_FRAME_DATABITS_TEN (0x00000007UL << 0) /**< Shifted mode TEN for UART_FRAME */ +#define UART_FRAME_DATABITS_ELEVEN (0x00000008UL << 0) /**< Shifted mode ELEVEN for UART_FRAME */ +#define UART_FRAME_DATABITS_TWELVE (0x00000009UL << 0) /**< Shifted mode TWELVE for UART_FRAME */ +#define UART_FRAME_DATABITS_THIRTEEN (0x0000000AUL << 0) /**< Shifted mode THIRTEEN for UART_FRAME */ +#define UART_FRAME_DATABITS_FOURTEEN (0x0000000BUL << 0) /**< Shifted mode FOURTEEN for UART_FRAME */ +#define UART_FRAME_DATABITS_FIFTEEN (0x0000000CUL << 0) /**< Shifted mode FIFTEEN for UART_FRAME */ +#define UART_FRAME_DATABITS_SIXTEEN (0x0000000DUL << 0) /**< Shifted mode SIXTEEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for UART_FRAME */ +#define _UART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for UART_FRAME */ +#define _UART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for UART_FRAME */ +#define _UART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for UART_FRAME */ +#define _UART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for UART_FRAME */ +#define _UART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for UART_FRAME */ +#define _UART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for UART_FRAME */ +#define _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for UART_FRAME */ +#define _UART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _UART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define UART_FRAME_PARITY_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_FRAME */ +#define UART_FRAME_PARITY_NONE (0x00000000UL << 8) /**< Shifted mode NONE for UART_FRAME */ +#define UART_FRAME_PARITY_EVEN (0x00000002UL << 8) /**< Shifted mode EVEN for UART_FRAME */ +#define UART_FRAME_PARITY_ODD (0x00000003UL << 8) /**< Shifted mode ODD for UART_FRAME */ +#define _UART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_FRAME */ +#define _UART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for UART_FRAME */ +#define _UART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for UART_FRAME */ +#define _UART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for UART_FRAME */ +#define _UART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _UART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define UART_FRAME_STOPBITS_HALF (0x00000000UL << 12) /**< Shifted mode HALF for UART_FRAME */ +#define UART_FRAME_STOPBITS_DEFAULT (0x00000001UL << 12) /**< Shifted mode DEFAULT for UART_FRAME */ +#define UART_FRAME_STOPBITS_ONE (0x00000001UL << 12) /**< Shifted mode ONE for UART_FRAME */ +#define UART_FRAME_STOPBITS_ONEANDAHALF (0x00000002UL << 12) /**< Shifted mode ONEANDAHALF for UART_FRAME */ +#define UART_FRAME_STOPBITS_TWO (0x00000003UL << 12) /**< Shifted mode TWO for UART_FRAME */ +#define _UART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for UART_FRAME */ +#define _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_FRAME */ +#define _UART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for UART_FRAME */ +#define _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for UART_FRAME */ +#define _UART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for UART_FRAME */ + +/** Bit fields for UART TRIGCTRL */ +#define _UART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_MASK 0x00000037UL /**< Mask for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */ +#define _UART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */ +#define UART_TRIGCTRL_TSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH0 (0x00000000UL << 0) /**< Shifted mode PRSCH0 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH1 (0x00000001UL << 0) /**< Shifted mode PRSCH1 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH2 (0x00000002UL << 0) /**< Shifted mode PRSCH2 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH3 (0x00000003UL << 0) /**< Shifted mode PRSCH3 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH4 (0x00000004UL << 0) /**< Shifted mode PRSCH4 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH5 (0x00000005UL << 0) /**< Shifted mode PRSCH5 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH6 (0x00000006UL << 0) /**< Shifted mode PRSCH6 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH7 (0x00000007UL << 0) /**< Shifted mode PRSCH7 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_RXTEN (1 << 4) /**< Receive Trigger Enable */ +#define _UART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _UART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define UART_TRIGCTRL_RXTEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TXTEN (1 << 5) /**< Transmit Trigger Enable */ +#define _UART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _UART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define UART_TRIGCTRL_TXTEN_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ + +/** Bit fields for UART CMD */ +#define _UART_CMD_RESETVALUE 0x00000000UL /**< Default value for UART_CMD */ +#define _UART_CMD_MASK 0x00000FFFUL /**< Mask for UART_CMD */ +#define UART_CMD_RXEN (1 << 0) /**< Receiver Enable */ +#define _UART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _UART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define UART_CMD_RXEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_RXDIS (1 << 1) /**< Receiver Disable */ +#define _UART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _UART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define UART_CMD_RXDIS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_TXEN (1 << 2) /**< Transmitter Enable */ +#define _UART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _UART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define UART_CMD_TXEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_TXDIS (1 << 3) /**< Transmitter Disable */ +#define _UART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _UART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define UART_CMD_TXDIS_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_MASTEREN (1 << 4) /**< Master Enable */ +#define _UART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _UART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define UART_CMD_MASTEREN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_MASTERDIS (1 << 5) /**< Master Disable */ +#define _UART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _UART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define UART_CMD_MASTERDIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_RXBLOCKEN (1 << 6) /**< Receiver Block Enable */ +#define _UART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _UART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define UART_CMD_RXBLOCKEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_RXBLOCKDIS (1 << 7) /**< Receiver Block Disable */ +#define _UART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _UART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define UART_CMD_RXBLOCKDIS_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_TXTRIEN (1 << 8) /**< Transmitter Tristate Enable */ +#define _UART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _UART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define UART_CMD_TXTRIEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_TXTRIDIS (1 << 9) /**< Transmitter Tristate Disable */ +#define _UART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _UART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define UART_CMD_TXTRIDIS_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_CLEARTX (1 << 10) /**< Clear TX */ +#define _UART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _UART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define UART_CMD_CLEARTX_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_CLEARRX (1 << 11) /**< Clear RX */ +#define _UART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _UART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define UART_CMD_CLEARRX_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_CMD */ +#define _UART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ + +/** Bit fields for UART STATUS */ +#define _UART_STATUS_RESETVALUE 0x00000040UL /**< Default value for UART_STATUS */ +#define _UART_STATUS_MASK 0x000001FFUL /**< Mask for UART_STATUS */ +#define UART_STATUS_RXENS (1 << 0) /**< Receiver Enable Status */ +#define _UART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _UART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define UART_STATUS_RXENS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXENS (1 << 1) /**< Transmitter Enable Status */ +#define _UART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _UART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define UART_STATUS_TXENS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_MASTER (1 << 2) /**< SPI Master Mode */ +#define _UART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _UART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define UART_STATUS_MASTER_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXBLOCK (1 << 3) /**< Block Incoming Data */ +#define _UART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _UART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define UART_STATUS_RXBLOCK_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXTRI (1 << 4) /**< Transmitter Tristated */ +#define _UART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _UART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define UART_STATUS_TXTRI_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXC (1 << 5) /**< TX Complete */ +#define _UART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _UART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define UART_STATUS_TXC_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXBL (1 << 6) /**< TX Buffer Level */ +#define _UART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _UART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define UART_STATUS_TXBL_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXDATAV (1 << 7) /**< RX Data Valid */ +#define _UART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _UART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define UART_STATUS_RXDATAV_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXFULL (1 << 8) /**< RX FIFO Full */ +#define _UART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _UART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define UART_STATUS_RXFULL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ + +/** Bit fields for UART CLKDIV */ +#define _UART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for UART_CLKDIV */ +#define _UART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for UART_CLKDIV */ +#define _UART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */ +#define _UART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */ +#define UART_CLKDIV_DIV_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_CLKDIV */ +#define _UART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */ + +/** Bit fields for UART RXDATAX */ +#define _UART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAX */ +#define _UART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAX */ +#define _UART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _UART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define UART_RXDATAX_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDATAX */ +#define _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */ +#define UART_RXDATAX_PERR (1 << 14) /**< Data Parity Error */ +#define _UART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _UART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define UART_RXDATAX_PERR_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_RXDATAX */ +#define _UART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */ +#define UART_RXDATAX_FERR (1 << 15) /**< Data Framing Error */ +#define _UART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _UART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define UART_RXDATAX_FERR_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_RXDATAX */ +#define _UART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */ + +/** Bit fields for UART RXDATA */ +#define _UART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATA */ +#define _UART_RXDATA_MASK 0x000000FFUL /**< Mask for UART_RXDATA */ +#define _UART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _UART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define UART_RXDATA_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDATA */ +#define _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATA */ + +/** Bit fields for UART RXDOUBLEX */ +#define _UART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define UART_RXDOUBLEX_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_PERR0 (1 << 14) /**< Data Parity Error 0 */ +#define _UART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _UART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define UART_RXDOUBLEX_PERR0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_FERR0 (1 << 15) /**< Data Framing Error 0 */ +#define _UART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _UART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define UART_RXDOUBLEX_FERR0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define UART_RXDOUBLEX_RXDATA1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_PERR1 (1 << 30) /**< Data Parity Error 1 */ +#define _UART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define UART_RXDOUBLEX_PERR1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_FERR1 (1 << 31) /**< Data Framing Error 1 */ +#define _UART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define UART_RXDOUBLEX_FERR1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ + +/** Bit fields for UART RXDOUBLE */ +#define _UART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLE */ +#define _UART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_RXDOUBLE */ +#define _UART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define UART_RXDOUBLE_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLE */ +#define _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */ +#define _UART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define UART_RXDOUBLE_RXDATA1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_RXDOUBLE */ +#define _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */ + +/** Bit fields for UART RXDATAXP */ +#define _UART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAXP */ +#define _UART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAXP */ +#define _UART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define UART_RXDATAXP_RXDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDATAXP */ +#define _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */ +#define UART_RXDATAXP_PERRP (1 << 14) /**< Data Parity Error Peek */ +#define _UART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _UART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define UART_RXDATAXP_PERRP_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_RXDATAXP */ +#define _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */ +#define UART_RXDATAXP_FERRP (1 << 15) /**< Data Framing Error Peek */ +#define _UART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _UART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define UART_RXDATAXP_FERRP_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_RXDATAXP */ +#define _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */ + +/** Bit fields for UART RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define UART_RXDOUBLEXP_RXDATAP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_PERRP0 (1 << 14) /**< Data Parity Error 0 Peek */ +#define _UART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define UART_RXDOUBLEXP_PERRP0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_FERRP0 (1 << 15) /**< Data Framing Error 0 Peek */ +#define _UART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define UART_RXDOUBLEXP_FERRP0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define UART_RXDOUBLEXP_RXDATAP1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_PERRP1 (1 << 30) /**< Data Parity Error 1 Peek */ +#define _UART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define UART_RXDOUBLEXP_PERRP1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_FERRP1 (1 << 31) /**< Data Framing Error 1 Peek */ +#define _UART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define UART_RXDOUBLEXP_FERRP1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ + +/** Bit fields for UART TXDATAX */ +#define _UART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATAX */ +#define _UART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for UART_TXDATAX */ +#define _UART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _UART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define UART_TXDATAX_TXDATAX_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_UBRXAT (1 << 11) /**< Unblock RX After Transmission */ +#define _UART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _UART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define UART_TXDATAX_UBRXAT_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXTRIAT (1 << 12) /**< Set TXTRI After Transmission */ +#define _UART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _UART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define UART_TXDATAX_TXTRIAT_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXBREAK (1 << 13) /**< Transmit Data As Break */ +#define _UART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _UART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define UART_TXDATAX_TXBREAK_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXDISAT (1 << 14) /**< Clear TXEN After Transmission */ +#define _UART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _UART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define UART_TXDATAX_TXDISAT_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_RXENAT (1 << 15) /**< Enable RX After Transmission */ +#define _UART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _UART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define UART_TXDATAX_RXENAT_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ + +/** Bit fields for UART TXDATA */ +#define _UART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATA */ +#define _UART_TXDATA_MASK 0x000000FFUL /**< Mask for UART_TXDATA */ +#define _UART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _UART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define UART_TXDATA_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TXDATA */ +#define _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATA */ + +/** Bit fields for UART TXDOUBLEX */ +#define _UART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define UART_TXDOUBLEX_TXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_UBRXAT0 (1 << 11) /**< Unblock RX After Transmission */ +#define _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define UART_TXDOUBLEX_UBRXAT0_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXTRIAT0 (1 << 12) /**< Set TXTRI After Transmission */ +#define _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define UART_TXDOUBLEX_TXTRIAT0_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXBREAK0 (1 << 13) /**< Transmit Data As Break */ +#define _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define UART_TXDOUBLEX_TXBREAK0_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXDISAT0 (1 << 14) /**< Clear TXEN After Transmission */ +#define _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define UART_TXDOUBLEX_TXDISAT0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_RXENAT0 (1 << 15) /**< Enable RX After Transmission */ +#define _UART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define UART_TXDOUBLEX_RXENAT0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define UART_TXDOUBLEX_TXDATA1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_UBRXAT1 (1 << 27) /**< Unblock RX After Transmission */ +#define _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define UART_TXDOUBLEX_UBRXAT1_DEFAULT (0x00000000UL << 27) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXTRIAT1 (1 << 28) /**< Set TXTRI After Transmission */ +#define _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define UART_TXDOUBLEX_TXTRIAT1_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXBREAK1 (1 << 29) /**< Transmit Data As Break */ +#define _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define UART_TXDOUBLEX_TXBREAK1_DEFAULT (0x00000000UL << 29) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXDISAT1 (1 << 30) /**< Clear TXEN After Transmission */ +#define _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define UART_TXDOUBLEX_TXDISAT1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_RXENAT1 (1 << 31) /**< Enable RX After Transmission */ +#define _UART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define UART_TXDOUBLEX_RXENAT1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ + +/** Bit fields for UART TXDOUBLE */ +#define _UART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLE */ +#define _UART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_TXDOUBLE */ +#define _UART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define UART_TXDOUBLE_TXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLE */ +#define _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */ +#define _UART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define UART_TXDOUBLE_TXDATA1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_TXDOUBLE */ +#define _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */ + +/** Bit fields for UART IF */ +#define _UART_IF_RESETVALUE 0x00000002UL /**< Default value for UART_IF */ +#define _UART_IF_MASK 0x00001FFFUL /**< Mask for UART_IF */ +#define UART_IF_TXC (1 << 0) /**< TX Complete Interrupt Flag */ +#define _UART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _UART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define UART_IF_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TXBL (1 << 1) /**< TX Buffer Level Interrupt Flag */ +#define _UART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _UART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define UART_IF_TXBL_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Flag */ +#define _UART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _UART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define UART_IF_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_RXFULL (1 << 3) /**< RX Buffer Full Interrupt Flag */ +#define _UART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _UART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define UART_IF_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_RXOF (1 << 4) /**< RX Overflow Interrupt Flag */ +#define _UART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _UART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define UART_IF_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_RXUF (1 << 5) /**< RX Underflow Interrupt Flag */ +#define _UART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _UART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define UART_IF_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TXOF (1 << 6) /**< TX Overflow Interrupt Flag */ +#define _UART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _UART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define UART_IF_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TXUF (1 << 7) /**< TX Underflow Interrupt Flag */ +#define _UART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _UART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define UART_IF_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_PERR (1 << 8) /**< Parity Error Interrupt Flag */ +#define _UART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _UART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define UART_IF_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_FERR (1 << 9) /**< Framing Error Interrupt Flag */ +#define _UART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _UART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define UART_IF_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_MPAF (1 << 10) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _UART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _UART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define UART_IF_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_SSM (1 << 11) /**< Slave-Select In Master Mode Interrupt Flag */ +#define _UART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _UART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define UART_IF_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_CCF (1 << 12) /**< Collision Check Fail Interrupt Flag */ +#define _UART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _UART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define UART_IF_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_IF */ +#define _UART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ + +/** Bit fields for UART IFS */ +#define _UART_IFS_RESETVALUE 0x00000000UL /**< Default value for UART_IFS */ +#define _UART_IFS_MASK 0x00001FF9UL /**< Mask for UART_IFS */ +#define UART_IFS_TXC (1 << 0) /**< Set TX Complete Interrupt Flag */ +#define _UART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _UART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define UART_IFS_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_RXFULL (1 << 3) /**< Set RX Buffer Full Interrupt Flag */ +#define _UART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _UART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define UART_IFS_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_RXOF (1 << 4) /**< Set RX Overflow Interrupt Flag */ +#define _UART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _UART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define UART_IFS_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_RXUF (1 << 5) /**< Set RX Underflow Interrupt Flag */ +#define _UART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _UART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define UART_IFS_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_TXOF (1 << 6) /**< Set TX Overflow Interrupt Flag */ +#define _UART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _UART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define UART_IFS_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_TXUF (1 << 7) /**< Set TX Underflow Interrupt Flag */ +#define _UART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _UART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define UART_IFS_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_PERR (1 << 8) /**< Set Parity Error Interrupt Flag */ +#define _UART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _UART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define UART_IFS_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_FERR (1 << 9) /**< Set Framing Error Interrupt Flag */ +#define _UART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _UART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define UART_IFS_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_MPAF (1 << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */ +#define _UART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _UART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define UART_IFS_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_SSM (1 << 11) /**< Set Slave-Select in Master mode Interrupt Flag */ +#define _UART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _UART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define UART_IFS_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_CCF (1 << 12) /**< Set Collision Check Fail Interrupt Flag */ +#define _UART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _UART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define UART_IFS_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_IFS */ +#define _UART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ + +/** Bit fields for UART IFC */ +#define _UART_IFC_RESETVALUE 0x00000000UL /**< Default value for UART_IFC */ +#define _UART_IFC_MASK 0x00001FF9UL /**< Mask for UART_IFC */ +#define UART_IFC_TXC (1 << 0) /**< Clear TX Complete Interrupt Flag */ +#define _UART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _UART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define UART_IFC_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_RXFULL (1 << 3) /**< Clear RX Buffer Full Interrupt Flag */ +#define _UART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _UART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define UART_IFC_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_RXOF (1 << 4) /**< Clear RX Overflow Interrupt Flag */ +#define _UART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _UART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define UART_IFC_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_RXUF (1 << 5) /**< Clear RX Underflow Interrupt Flag */ +#define _UART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _UART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define UART_IFC_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_TXOF (1 << 6) /**< Clear TX Overflow Interrupt Flag */ +#define _UART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _UART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define UART_IFC_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_TXUF (1 << 7) /**< Clear TX Underflow Interrupt Flag */ +#define _UART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _UART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define UART_IFC_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_PERR (1 << 8) /**< Clear Parity Error Interrupt Flag */ +#define _UART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _UART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define UART_IFC_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_FERR (1 << 9) /**< Clear Framing Error Interrupt Flag */ +#define _UART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _UART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define UART_IFC_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_MPAF (1 << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */ +#define _UART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _UART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define UART_IFC_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_SSM (1 << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */ +#define _UART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _UART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define UART_IFC_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_CCF (1 << 12) /**< Clear Collision Check Fail Interrupt Flag */ +#define _UART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _UART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define UART_IFC_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_IFC */ +#define _UART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ + +/** Bit fields for UART IEN */ +#define _UART_IEN_RESETVALUE 0x00000000UL /**< Default value for UART_IEN */ +#define _UART_IEN_MASK 0x00001FFFUL /**< Mask for UART_IEN */ +#define UART_IEN_TXC (1 << 0) /**< TX Complete Interrupt Enable */ +#define _UART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _UART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define UART_IEN_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TXBL (1 << 1) /**< TX Buffer Level Interrupt Enable */ +#define _UART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _UART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define UART_IEN_TXBL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Enable */ +#define _UART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _UART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define UART_IEN_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_RXFULL (1 << 3) /**< RX Buffer Full Interrupt Enable */ +#define _UART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _UART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define UART_IEN_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_RXOF (1 << 4) /**< RX Overflow Interrupt Enable */ +#define _UART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _UART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define UART_IEN_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_RXUF (1 << 5) /**< RX Underflow Interrupt Enable */ +#define _UART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _UART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define UART_IEN_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TXOF (1 << 6) /**< TX Overflow Interrupt Enable */ +#define _UART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _UART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define UART_IEN_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TXUF (1 << 7) /**< TX Underflow Interrupt Enable */ +#define _UART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _UART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define UART_IEN_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_PERR (1 << 8) /**< Parity Error Interrupt Enable */ +#define _UART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _UART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define UART_IEN_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_FERR (1 << 9) /**< Framing Error Interrupt Enable */ +#define _UART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _UART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define UART_IEN_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_MPAF (1 << 10) /**< Multi-Processor Address Frame Interrupt Enable */ +#define _UART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _UART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define UART_IEN_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_SSM (1 << 11) /**< Slave-Select In Master Mode Interrupt Enable */ +#define _UART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _UART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define UART_IEN_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_CCF (1 << 12) /**< Collision Check Fail Interrupt Enable */ +#define _UART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _UART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define UART_IEN_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_IEN */ +#define _UART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ + +/** Bit fields for UART IRCTRL */ +#define _UART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_IRCTRL */ +#define _UART_IRCTRL_MASK 0x000000FFUL /**< Mask for UART_IRCTRL */ +#define UART_IRCTRL_IREN (1 << 0) /**< Enable IrDA Module */ +#define _UART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _UART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define UART_IRCTRL_IREN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _UART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define UART_IRCTRL_IRPW_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define UART_IRCTRL_IRPW_ONE (0x00000000UL << 1) /**< Shifted mode ONE for UART_IRCTRL */ +#define UART_IRCTRL_IRPW_TWO (0x00000001UL << 1) /**< Shifted mode TWO for UART_IRCTRL */ +#define UART_IRCTRL_IRPW_THREE (0x00000002UL << 1) /**< Shifted mode THREE for UART_IRCTRL */ +#define UART_IRCTRL_IRPW_FOUR (0x00000003UL << 1) /**< Shifted mode FOUR for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for UART_IRCTRL */ +#define UART_IRCTRL_IRFILT (1 << 3) /**< IrDA RX Filter */ +#define _UART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _UART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define UART_IRCTRL_IRFILT_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */ +#define _UART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */ +#define UART_IRCTRL_IRPRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSEN (1 << 7) /**< IrDA PRS Channel Enable */ +#define _UART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ +#define _UART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ +#define UART_IRCTRL_IRPRSEN_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ + +/** Bit fields for UART ROUTE */ +#define _UART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTE */ +#define _UART_ROUTE_MASK 0x0000030FUL /**< Mask for UART_ROUTE */ +#define UART_ROUTE_RXPEN (1 << 0) /**< RX Pin Enable */ +#define _UART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ +#define _UART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ +#define UART_ROUTE_RXPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_ROUTE */ +#define _UART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */ +#define UART_ROUTE_TXPEN (1 << 1) /**< TX Pin Enable */ +#define _UART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ +#define _UART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ +#define UART_ROUTE_TXPEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_ROUTE */ +#define _UART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */ +#define UART_ROUTE_CSPEN (1 << 2) /**< CS Pin Enable */ +#define _UART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ +#define _UART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ +#define UART_ROUTE_CSPEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_ROUTE */ +#define _UART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */ +#define UART_ROUTE_CLKPEN (1 << 3) /**< RX Pin Enable */ +#define _UART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ +#define _UART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ +#define UART_ROUTE_CLKPEN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_ROUTE */ +#define _UART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */ +#define _UART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */ +#define _UART_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for USART_LOCATION */ +#define UART_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_ROUTE */ +#define UART_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for UART_ROUTE */ +#define UART_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for UART_ROUTE */ +#define UART_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for UART_ROUTE */ +#define UART_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for UART_ROUTE */ +#define _UART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */ +#define _UART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTE */ +#define _UART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTE */ +#define _UART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTE */ +#define _UART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTE */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_LEUART + * @{ + */ + +/** Bit fields for LEUART CTRL */ +#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */ +#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI (1 << 0) /**< Automatic Transmitter Tristate */ +#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */ +#define LEUART_CTRL_AUTOTRI_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS (1 << 1) /**< Data-Bit Mode */ +#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */ +#define LEUART_CTRL_DATABITS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_EIGHT (0x00000000UL << 1) /**< Shifted mode EIGHT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_NINE (0x00000001UL << 1) /**< Shifted mode NINE for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */ +#define LEUART_CTRL_PARITY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_NONE (0x00000000UL << 2) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_EVEN (0x00000002UL << 2) /**< Shifted mode EVEN for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_ODD (0x00000003UL << 2) /**< Shifted mode ODD for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS (1 << 4) /**< Stop-Bit Mode */ +#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */ +#define LEUART_CTRL_STOPBITS_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_ONE (0x00000000UL << 4) /**< Shifted mode ONE for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_TWO (0x00000001UL << 4) /**< Shifted mode TWO for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_INV (1 << 5) /**< Invert Input And Output */ +#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */ +#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */ +#define LEUART_CTRL_INV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA (1 << 6) /**< Halt RX DMA On Error */ +#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */ +#define LEUART_CTRL_ERRSDMA_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK (1 << 7) /**< Loopback Enable */ +#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */ +#define LEUART_CTRL_LOOPBK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX (1 << 8) /**< Start-Frame UnBlock RX */ +#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */ +#define LEUART_CTRL_SFUBRX_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM (1 << 9) /**< Multi-Processor Mode */ +#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */ +#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */ +#define LEUART_CTRL_MPM_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB (1 << 10) /**< Multi-Processor Address-Bit */ +#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */ +#define LEUART_CTRL_MPAB_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV (1 << 11) /**< Bit 8 Default Value */ +#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */ +#define LEUART_CTRL_BIT8DV_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU (1 << 12) /**< RX DMA Wakeup */ +#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */ +#define LEUART_CTRL_RXDMAWU_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU (1 << 13) /**< TX DMA Wakeup */ +#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */ +#define LEUART_CTRL_TXDMAWU_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */ +#define LEUART_CTRL_TXDELAY_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_NONE (0x00000000UL << 14) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_SINGLE (0x00000001UL << 14) /**< Shifted mode SINGLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DOUBLE (0x00000002UL << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_TRIPLE (0x00000003UL << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */ + +/** Bit fields for LEUART CMD */ +#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */ +#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */ +#define LEUART_CMD_RXEN (1 << 0) /**< Receiver Enable */ +#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */ +#define LEUART_CMD_RXEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS (1 << 1) /**< Receiver Disable */ +#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */ +#define LEUART_CMD_RXDIS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN (1 << 2) /**< Transmitter Enable */ +#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */ +#define LEUART_CMD_TXEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS (1 << 3) /**< Transmitter Disable */ +#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */ +#define LEUART_CMD_TXDIS_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN (1 << 4) /**< Receiver Block Enable */ +#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */ +#define LEUART_CMD_RXBLOCKEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS (1 << 5) /**< Receiver Block Disable */ +#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */ +#define LEUART_CMD_RXBLOCKDIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX (1 << 6) /**< Clear TX */ +#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */ +#define LEUART_CMD_CLEARTX_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX (1 << 7) /**< Clear RX */ +#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */ +#define LEUART_CMD_CLEARRX_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ + +/** Bit fields for LEUART STATUS */ +#define _LEUART_STATUS_RESETVALUE 0x00000010UL /**< Default value for LEUART_STATUS */ +#define _LEUART_STATUS_MASK 0x0000003FUL /**< Mask for LEUART_STATUS */ +#define LEUART_STATUS_RXENS (1 << 0) /**< Receiver Enable Status */ +#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */ +#define LEUART_STATUS_RXENS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS (1 << 1) /**< Transmitter Enable Status */ +#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */ +#define LEUART_STATUS_TXENS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK (1 << 2) /**< Block Incoming Data */ +#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */ +#define LEUART_STATUS_RXBLOCK_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC (1 << 3) /**< TX Complete */ +#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */ +#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */ +#define LEUART_STATUS_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL (1 << 4) /**< TX Buffer Level */ +#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */ +#define LEUART_STATUS_TXBL_DEFAULT (0x00000001UL << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV (1 << 5) /**< RX Data Valid */ +#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */ +#define LEUART_STATUS_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ + +/** Bit fields for LEUART CLKDIV */ +#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_MASK 0x00007FF8UL /**< Mask for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_MASK 0x7FF8UL /**< Bit mask for LEUART_DIV */ +#define LEUART_CLKDIV_DIV_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */ + +/** Bit fields for LEUART STARTFRAME */ +#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */ +#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */ + +/** Bit fields for LEUART SIGFRAME */ +#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */ +#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */ + +/** Bit fields for LEUART RXDATAX */ +#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */ +#define LEUART_RXDATAX_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR (1 << 14) /**< Receive Data Parity Error */ +#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */ +#define LEUART_RXDATAX_PERR_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR (1 << 15) /**< Receive Data Framing Error */ +#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */ +#define LEUART_RXDATAX_FERR_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ + +/** Bit fields for LEUART RXDATA */ +#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */ +#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */ +#define LEUART_RXDATA_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */ + +/** Bit fields for LEUART RXDATAXP */ +#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */ +#define LEUART_RXDATAXP_RXDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP (1 << 14) /**< Receive Data Parity Error Peek */ +#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */ +#define LEUART_RXDATAXP_PERRP_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP (1 << 15) /**< Receive Data Framing Error Peek */ +#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */ +#define LEUART_RXDATAXP_FERRP_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ + +/** Bit fields for LEUART TXDATAX */ +#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */ +#define LEUART_TXDATAX_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK (1 << 13) /**< Transmit Data As Break */ +#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */ +#define LEUART_TXDATAX_TXBREAK_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT (1 << 14) /**< Disable TX After Transmission */ +#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */ +#define LEUART_TXDATAX_TXDISAT_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT (1 << 15) /**< Enable RX After Transmission */ +#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */ +#define LEUART_TXDATAX_RXENAT_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ + +/** Bit fields for LEUART TXDATA */ +#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */ +#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */ +#define LEUART_TXDATA_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */ + +/** Bit fields for LEUART IF */ +#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */ +#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */ +#define LEUART_IF_TXC (1 << 0) /**< TX Complete Interrupt Flag */ +#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define LEUART_IF_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL (1 << 1) /**< TX Buffer Level Interrupt Flag */ +#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define LEUART_IF_TXBL_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Flag */ +#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define LEUART_IF_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF (1 << 3) /**< RX Overflow Interrupt Flag */ +#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define LEUART_IF_RXOF_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF (1 << 4) /**< RX Underflow Interrupt Flag */ +#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define LEUART_IF_RXUF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF (1 << 5) /**< TX Overflow Interrupt Flag */ +#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define LEUART_IF_TXOF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR (1 << 6) /**< Parity Error Interrupt Flag */ +#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define LEUART_IF_PERR_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR (1 << 7) /**< Framing Error Interrupt Flag */ +#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define LEUART_IF_FERR_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF (1 << 8) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define LEUART_IF_MPAF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF (1 << 9) /**< Start Frame Interrupt Flag */ +#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define LEUART_IF_STARTF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF (1 << 10) /**< Signal Frame Interrupt Flag */ +#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define LEUART_IF_SIGF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_IF */ +#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ + +/** Bit fields for LEUART IFS */ +#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */ +#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */ +#define LEUART_IFS_TXC (1 << 0) /**< Set TX Complete Interrupt Flag */ +#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define LEUART_IFS_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF (1 << 3) /**< Set RX Overflow Interrupt Flag */ +#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define LEUART_IFS_RXOF_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF (1 << 4) /**< Set RX Underflow Interrupt Flag */ +#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define LEUART_IFS_RXUF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF (1 << 5) /**< Set TX Overflow Interrupt Flag */ +#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define LEUART_IFS_TXOF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR (1 << 6) /**< Set Parity Error Interrupt Flag */ +#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define LEUART_IFS_PERR_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR (1 << 7) /**< Set Framing Error Interrupt Flag */ +#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define LEUART_IFS_FERR_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF (1 << 8) /**< Set Multi-Processor Address Frame Interrupt Flag */ +#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define LEUART_IFS_MPAF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF (1 << 9) /**< Set Start Frame Interrupt Flag */ +#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define LEUART_IFS_STARTF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF (1 << 10) /**< Set Signal Frame Interrupt Flag */ +#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define LEUART_IFS_SIGF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ + +/** Bit fields for LEUART IFC */ +#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */ +#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */ +#define LEUART_IFC_TXC (1 << 0) /**< Clear TX Complete Interrupt Flag */ +#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define LEUART_IFC_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF (1 << 3) /**< Clear RX Overflow Interrupt Flag */ +#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define LEUART_IFC_RXOF_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF (1 << 4) /**< Clear RX Underflow Interrupt Flag */ +#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define LEUART_IFC_RXUF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF (1 << 5) /**< Clear TX Overflow Interrupt Flag */ +#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define LEUART_IFC_TXOF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR (1 << 6) /**< Clear Parity Error Interrupt Flag */ +#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define LEUART_IFC_PERR_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR (1 << 7) /**< Clear Framing Error Interrupt Flag */ +#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define LEUART_IFC_FERR_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF (1 << 8) /**< Clear Multi-Processor Address Frame Interrupt Flag */ +#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define LEUART_IFC_MPAF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF (1 << 9) /**< Clear Start-Frame Interrupt Flag */ +#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define LEUART_IFC_STARTF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF (1 << 10) /**< Clear Signal-Frame Interrupt Flag */ +#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define LEUART_IFC_SIGF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ + +/** Bit fields for LEUART IEN */ +#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */ +#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */ +#define LEUART_IEN_TXC (1 << 0) /**< TX Complete Interrupt Enable */ +#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define LEUART_IEN_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL (1 << 1) /**< TX Buffer Level Interrupt Enable */ +#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define LEUART_IEN_TXBL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Enable */ +#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define LEUART_IEN_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF (1 << 3) /**< RX Overflow Interrupt Enable */ +#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define LEUART_IEN_RXOF_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF (1 << 4) /**< RX Underflow Interrupt Enable */ +#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define LEUART_IEN_RXUF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF (1 << 5) /**< TX Overflow Interrupt Enable */ +#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define LEUART_IEN_TXOF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR (1 << 6) /**< Parity Error Interrupt Enable */ +#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define LEUART_IEN_PERR_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR (1 << 7) /**< Framing Error Interrupt Enable */ +#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define LEUART_IEN_FERR_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF (1 << 8) /**< Multi-Processor Address Frame Interrupt Enable */ +#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define LEUART_IEN_MPAF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF (1 << 9) /**< Start Frame Interrupt Enable */ +#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define LEUART_IEN_STARTF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF (1 << 10) /**< Signal Frame Interrupt Enable */ +#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define LEUART_IEN_SIGF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ + +/** Bit fields for LEUART PULSECTRL */ +#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */ +#define LEUART_PULSECTRL_PULSEW_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN (1 << 4) /**< Pulse Generator/Extender Enable */ +#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */ +#define LEUART_PULSECTRL_PULSEEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT (1 << 5) /**< Pulse Filter */ +#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */ +#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ + +/** Bit fields for LEUART FREEZE */ +#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */ +#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */ +#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */ +#define LEUART_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */ + +/** Bit fields for LEUART SYNCBUSY */ +#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL (1 << 0) /**< LEUARTn_CTRL Register Busy */ +#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */ +#define LEUART_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD (1 << 1) /**< LEUARTn_CMD Register Busy */ +#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */ +#define LEUART_SYNCBUSY_CMD_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV (1 << 2) /**< LEUARTn_CLKDIV Register Busy */ +#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */ +#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME (1 << 3) /**< LEUARTn_STARTFRAME Register Busy */ +#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */ +#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME (1 << 4) /**< LEUARTn_SIGFRAME Register Busy */ +#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */ +#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX (1 << 5) /**< LEUARTn_TXDATAX Register Busy */ +#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */ +#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA (1 << 6) /**< LEUARTn_TXDATA Register Busy */ +#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */ +#define LEUART_SYNCBUSY_TXDATA_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL (1 << 7) /**< LEUARTn_PULSECTRL Register Busy */ +#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */ +#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ + +/** Bit fields for LEUART ROUTE */ +#define _LEUART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTE */ +#define _LEUART_ROUTE_MASK 0x00000303UL /**< Mask for LEUART_ROUTE */ +#define LEUART_ROUTE_RXPEN (1 << 0) /**< RX Pin Enable */ +#define _LEUART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */ +#define _LEUART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */ +#define LEUART_ROUTE_RXPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_ROUTE */ +#define _LEUART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */ +#define LEUART_ROUTE_TXPEN (1 << 1) /**< TX Pin Enable */ +#define _LEUART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */ +#define _LEUART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */ +#define LEUART_ROUTE_TXPEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_ROUTE */ +#define _LEUART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */ +#define _LEUART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LEUART_LOCATION */ +#define _LEUART_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for LEUART_LOCATION */ +#define LEUART_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_ROUTE */ +#define LEUART_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for LEUART_ROUTE */ +#define LEUART_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for LEUART_ROUTE */ +#define LEUART_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for LEUART_ROUTE */ +#define LEUART_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for LEUART_ROUTE */ +#define _LEUART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */ +#define _LEUART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTE */ +#define _LEUART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTE */ +#define _LEUART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTE */ +#define _LEUART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTE */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_LETIMER + * @{ + */ + +/** Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x00001FFFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define LETIMER_CTRL_REPMODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (0x00000000UL << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (0x00000001UL << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (0x00000002UL << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (0x00000003UL << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define LETIMER_CTRL_UFOA0_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (0x00000000UL << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (0x00000001UL << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (0x00000002UL << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (0x00000003UL << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define LETIMER_CTRL_UFOA1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (0x00000000UL << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (0x00000001UL << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (0x00000002UL << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (0x00000003UL << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (1 << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define LETIMER_CTRL_OPOL0_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (1 << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define LETIMER_CTRL_OPOL1_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (1 << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP (1 << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */ +#define LETIMER_CTRL_COMP0TOP_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_RTCC0TEN (1 << 10) /**< RTC Compare 0 Trigger Enable */ +#define _LETIMER_CTRL_RTCC0TEN_SHIFT 10 /**< Shift value for LETIMER_RTCC0TEN */ +#define _LETIMER_CTRL_RTCC0TEN_MASK 0x400UL /**< Bit mask for LETIMER_RTCC0TEN */ +#define LETIMER_CTRL_RTCC0TEN_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_RTCC0TEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_RTCC1TEN (1 << 11) /**< RTC Compare 1 Trigger Enable */ +#define _LETIMER_CTRL_RTCC1TEN_SHIFT 11 /**< Shift value for LETIMER_RTCC1TEN */ +#define _LETIMER_CTRL_RTCC1TEN_MASK 0x800UL /**< Bit mask for LETIMER_RTCC1TEN */ +#define LETIMER_CTRL_RTCC1TEN_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_RTCC1TEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (1 << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ + +/** Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (1 << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define LETIMER_CMD_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (1 << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define LETIMER_CMD_STOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (1 << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define LETIMER_CMD_CLEAR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (1 << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define LETIMER_CMD_CTO0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (1 << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define LETIMER_CMD_CTO1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ + +/** Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (1 << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define LETIMER_STATUS_RUNNING_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ + +/** Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ + +/** Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ + +/** Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ + +/** Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ + +/** Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ + +/** Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (1 << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define LETIMER_IF_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (1 << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define LETIMER_IF_COMP1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (1 << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define LETIMER_IF_UF_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (1 << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define LETIMER_IF_REP0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (1 << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define LETIMER_IF_REP1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ + +/** Bit fields for LETIMER IFS */ +#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */ +#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */ +#define LETIMER_IFS_COMP0 (1 << 0) /**< Set Compare Match 0 Interrupt Flag */ +#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define LETIMER_IFS_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1 (1 << 1) /**< Set Compare Match 1 Interrupt Flag */ +#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define LETIMER_IFS_COMP1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF (1 << 2) /**< Set Underflow Interrupt Flag */ +#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define LETIMER_IFS_UF_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0 (1 << 3) /**< Set Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define LETIMER_IFS_REP0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1 (1 << 4) /**< Set Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define LETIMER_IFS_REP1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ + +/** Bit fields for LETIMER IFC */ +#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */ +#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */ +#define LETIMER_IFC_COMP0 (1 << 0) /**< Clear Compare Match 0 Interrupt Flag */ +#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define LETIMER_IFC_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1 (1 << 1) /**< Clear Compare Match 1 Interrupt Flag */ +#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define LETIMER_IFC_COMP1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF (1 << 2) /**< Clear Underflow Interrupt Flag */ +#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define LETIMER_IFC_UF_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0 (1 << 3) /**< Clear Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define LETIMER_IFC_REP0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1 (1 << 4) /**< Clear Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define LETIMER_IFC_REP1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ + +/** Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (1 << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define LETIMER_IEN_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (1 << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define LETIMER_IEN_COMP1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (1 << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define LETIMER_IEN_UF_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (1 << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define LETIMER_IEN_REP0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (1 << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define LETIMER_IEN_REP1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ + +/** Bit fields for LETIMER FREEZE */ +#define _LETIMER_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_FREEZE */ +#define _LETIMER_FREEZE_MASK 0x00000001UL /**< Mask for LETIMER_FREEZE */ +#define LETIMER_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */ +#define _LETIMER_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LETIMER_REGFREEZE */ +#define _LETIMER_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LETIMER_REGFREEZE */ +#define LETIMER_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_FREEZE */ +#define LETIMER_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for LETIMER_FREEZE */ +#define LETIMER_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for LETIMER_FREEZE */ +#define _LETIMER_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_FREEZE */ +#define _LETIMER_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LETIMER_FREEZE */ +#define _LETIMER_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LETIMER_FREEZE */ + +/** Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x0000003FUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTRL (1 << 0) /**< LETIMERn_CTRL Register Busy */ +#define _LETIMER_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LETIMER_CTRL */ +#define _LETIMER_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LETIMER_CTRL */ +#define LETIMER_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD (1 << 1) /**< LETIMERn_CMD Register Busy */ +#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */ +#define LETIMER_SYNCBUSY_CMD_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_COMP0 (1 << 2) /**< LETIMERn_COMP0 Register Busy */ +#define _LETIMER_SYNCBUSY_COMP0_SHIFT 2 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_SYNCBUSY_COMP0_MASK 0x4UL /**< Bit mask for LETIMER_COMP0 */ +#define LETIMER_SYNCBUSY_COMP0_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_COMP1 (1 << 3) /**< LETIMERn_COMP1 Register Busy */ +#define _LETIMER_SYNCBUSY_COMP1_SHIFT 3 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_SYNCBUSY_COMP1_MASK 0x8UL /**< Bit mask for LETIMER_COMP1 */ +#define LETIMER_SYNCBUSY_COMP1_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (1 << 4) /**< LETIMERn_REP0 Register Busy */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 4 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x10UL /**< Bit mask for LETIMER_REP0 */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (1 << 5) /**< LETIMERn_REP1 Register Busy */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 5 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x20UL /**< Bit mask for LETIMER_REP1 */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ + +/** Bit fields for LETIMER ROUTE */ +#define _LETIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_MASK 0x00000303UL /**< Mask for LETIMER_ROUTE */ +#define LETIMER_ROUTE_OUT0PEN (1 << 0) /**< Output 0 Pin Enable */ +#define _LETIMER_ROUTE_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTE_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */ +#define LETIMER_ROUTE_OUT0PEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */ +#define LETIMER_ROUTE_OUT1PEN (1 << 1) /**< Output 1 Pin Enable */ +#define _LETIMER_ROUTE_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTE_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */ +#define LETIMER_ROUTE_OUT1PEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LETIMER_LOCATION */ +#define _LETIMER_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for LETIMER_LOCATION */ +#define LETIMER_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTE */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_PCNT + * @{ + */ + +/** Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0x0000003FUL /**< Mask for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CTRL_MODE_MASK 0x3UL /**< Bit mask for PCNT_MODE */ +#define PCNT_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DISABLE (0x00000000UL << 0) /**< Shifted mode DISABLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVRSINGLE (0x00000001UL << 0) /**< Shifted mode OVRSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKSINGLE (0x00000002UL << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKQUAD (0x00000003UL << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVRSINGLE 0x00000001UL /**< Mode OVRSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (1 << 2) /**< Non-Quadrature Mode Counter Direction Control */ +#define _PCNT_CTRL_CNTDIR_SHIFT 2 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x4UL /**< Bit mask for PCNT_CNTDIR */ +#define PCNT_CTRL_CNTDIR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (0x00000000UL << 2) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (0x00000001UL << 2) /**< Shifted mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (1 << 3) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 3 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x8UL /**< Bit mask for PCNT_EDGE */ +#define PCNT_CTRL_EDGE_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (0x00000000UL << 3) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (0x00000001UL << 3) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_FILT (1 << 4) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CTRL_FILT_SHIFT 4 /**< Shift value for PCNT_FILT */ +#define _PCNT_CTRL_FILT_MASK 0x10UL /**< Bit mask for PCNT_FILT */ +#define PCNT_CTRL_FILT_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN (1 << 5) /**< Enable PCNT Clock Domain Reset */ +#define _PCNT_CTRL_RSTEN_SHIFT 5 /**< Shift value for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_MASK 0x20UL /**< Bit mask for PCNT_RSTEN */ +#define PCNT_CTRL_RSTEN_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ + +/** Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (1 << 0) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */ +#define PCNT_CMD_LCNTIM_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM (1 << 1) /**< Load TOPB Immediately */ +#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */ +#define PCNT_CMD_LTOPBIM_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ + +/** Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (1 << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define PCNT_STATUS_DIR_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (0x00000000UL << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (0x00000001UL << 0) /**< Shifted mode DOWN for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ + +/** Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ + +/** Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (0x0000FFFFUL << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for PCNT_TOP */ + +/** Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x0000FFFFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (0x0000FFFFUL << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for PCNT_TOPB */ + +/** Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x00000007UL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (1 << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define PCNT_IF_UF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (1 << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define PCNT_IF_OF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (1 << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define PCNT_IF_DIRCNG_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ + +/** Bit fields for PCNT IFS */ +#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */ +#define _PCNT_IFS_MASK 0x00000007UL /**< Mask for PCNT_IFS */ +#define PCNT_IFS_UF (1 << 0) /**< Underflow interrupt set */ +#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define PCNT_IFS_UF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF (1 << 1) /**< Overflow Interrupt Set */ +#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define PCNT_IFS_OF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG (1 << 2) /**< Direction Change Detect Interrupt Set */ +#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define PCNT_IFS_DIRCNG_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ + +/** Bit fields for PCNT IFC */ +#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */ +#define _PCNT_IFC_MASK 0x00000007UL /**< Mask for PCNT_IFC */ +#define PCNT_IFC_UF (1 << 0) /**< Underflow Interrupt Clear */ +#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define PCNT_IFC_UF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF (1 << 1) /**< Overflow Interrupt Clear */ +#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define PCNT_IFC_OF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG (1 << 2) /**< Direction Change Detect Interrupt Clear */ +#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define PCNT_IFC_DIRCNG_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ + +/** Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x00000007UL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (1 << 0) /**< Underflow Interrupt Enable */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define PCNT_IEN_UF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (1 << 1) /**< Overflow Interrupt Enable */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define PCNT_IEN_OF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (1 << 2) /**< Direction Change Detect Interrupt Enable */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define PCNT_IEN_DIRCNG_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ + +/** Bit fields for PCNT ROUTE */ +#define _PCNT_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTE */ +#define _PCNT_ROUTE_MASK 0x00000300UL /**< Mask for PCNT_ROUTE */ +#define _PCNT_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PCNT_LOCATION */ +#define _PCNT_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for PCNT_LOCATION */ +#define PCNT_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for PCNT_ROUTE */ +#define PCNT_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for PCNT_ROUTE */ +#define PCNT_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for PCNT_ROUTE */ +#define PCNT_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for PCNT_ROUTE */ +#define _PCNT_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTE */ +#define _PCNT_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTE */ +#define _PCNT_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTE */ +#define _PCNT_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTE */ + +/** Bit fields for PCNT FREEZE */ +#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */ +#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */ +#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */ +#define PCNT_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */ + +/** Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x00000007UL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (1 << 0) /**< PCNTn_CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (1 << 1) /**< PCNTn_CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (1 << 2) /**< PCNTn_TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_I2C + * @{ + */ + +/** Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_EN (1 << 0) /**< I2C Enable */ +#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define I2C_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE (1 << 1) /**< Addressable as Slave */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define I2C_CTRL_SLAVE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (0x00000000UL << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (0x00000001UL << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (1 << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define I2C_CTRL_AUTOACK_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (0x00000000UL << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (0x00000001UL << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (1 << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define I2C_CTRL_AUTOSE_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (0x00000000UL << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (0x00000001UL << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (1 << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define I2C_CTRL_AUTOSN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (0x00000000UL << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (0x00000001UL << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (1 << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define I2C_CTRL_ARBDIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (1 << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define I2C_CTRL_GCAMEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define I2C_CTRL_CLHR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (0x00000000UL << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (0x00000001UL << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (0x00000002UL << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define I2C_CTRL_BITO_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (0x00000000UL << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_40PCC (0x00000001UL << 12) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_80PCC (0x00000002UL << 12) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_160PCC (0x00000003UL << 12) /**< Shifted mode 160PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (1 << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define I2C_CTRL_GIBITO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (0x00000000UL << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (0x00000001UL << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define I2C_CTRL_CLTO_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (0x00000000UL << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_40PCC (0x00000001UL << 16) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_80PCC (0x00000002UL << 16) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_160PCC (0x00000003UL << 16) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_320PPC (0x00000004UL << 16) /**< Shifted mode 320PPC for I2C_CTRL */ +#define I2C_CTRL_CLTO_1024PPC (0x00000005UL << 16) /**< Shifted mode 1024PPC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */ + +/** Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (1 << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define I2C_CMD_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (1 << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define I2C_CMD_STOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (1 << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define I2C_CMD_ACK_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (1 << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define I2C_CMD_NACK_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (1 << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define I2C_CMD_CONT_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (1 << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define I2C_CMD_ABORT_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (1 << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define I2C_CMD_CLEARTX_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (1 << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define I2C_CMD_CLEARPC_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ + +/** Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (1 << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define I2C_STATE_BUSY_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (1 << 1) /**< Master */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define I2C_STATE_MASTER_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (1 << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define I2C_STATE_TRANSMITTER_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (1 << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define I2C_STATE_NACKED_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (1 << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define I2C_STATE_BUSHOLD_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (0x00000000UL << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (0x00000001UL << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (0x00000002UL << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (0x00000003UL << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (0x00000004UL << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (0x00000005UL << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (0x00000006UL << 5) /**< Shifted mode DATAACK for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ + +/** Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (1 << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define I2C_STATUS_PSTART_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (1 << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define I2C_STATUS_PSTOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (1 << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define I2C_STATUS_PACK_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (1 << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define I2C_STATUS_PNACK_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (1 << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define I2C_STATUS_PCONT_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (1 << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define I2C_STATUS_PABORT_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (1 << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define I2C_STATUS_TXC_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (1 << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define I2C_STATUS_TXBL_DEFAULT (0x00000001UL << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (1 << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define I2C_STATUS_RXDATAV_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ + +/** Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define I2C_CLKDIV_DIV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ + +/** Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define I2C_SADDR_ADDR_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ + +/** Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ +#define I2C_SADDRMASK_MASK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ + +/** Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ + +/** Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ + +/** Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ + +/** Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (1 << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define I2C_IF_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (1 << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define I2C_IF_RSTART_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (1 << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define I2C_IF_ADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (1 << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define I2C_IF_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (1 << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define I2C_IF_TXBL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (1 << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define I2C_IF_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (1 << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define I2C_IF_ACK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (1 << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define I2C_IF_NACK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (1 << 8) /**< Master STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define I2C_IF_MSTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (1 << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define I2C_IF_ARBLOST_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (1 << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define I2C_IF_BUSERR_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (1 << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define I2C_IF_BUSHOLD_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (1 << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define I2C_IF_TXOF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (1 << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define I2C_IF_RXUF_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (1 << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define I2C_IF_BITO_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (1 << 15) /**< Clock Low Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define I2C_IF_CLTO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (1 << 16) /**< Slave STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define I2C_IF_SSTOP_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ + +/** Bit fields for I2C IFS */ +#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ +#define _I2C_IFS_MASK 0x0001FFFFUL /**< Mask for I2C_IFS */ +#define I2C_IFS_START (1 << 0) /**< Set START Interrupt Flag */ +#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define I2C_IFS_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART (1 << 1) /**< Set Repeated START Interrupt Flag */ +#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define I2C_IFS_RSTART_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR (1 << 2) /**< Set Address Interrupt Flag */ +#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define I2C_IFS_ADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC (1 << 3) /**< Set Transfer Completed Interrupt Flag */ +#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define I2C_IFS_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXBL (1 << 4) /**< Set Transmit Buffer level Interrupt Flag */ +#define _I2C_IFS_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IFS_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define I2C_IFS_TXBL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXDATAV (1 << 5) /**< Set Receive Data Valid Interrupt Flag */ +#define _I2C_IFS_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IFS_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define I2C_IFS_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK (1 << 6) /**< Set Acknowledge Received Interrupt Flag */ +#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define I2C_IFS_ACK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK (1 << 7) /**< Set Not Acknowledge Received Interrupt Flag */ +#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define I2C_IFS_NACK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP (1 << 8) /**< Set MSTOP Interrupt Flag */ +#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define I2C_IFS_MSTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST (1 << 9) /**< Set Arbitration Lost Interrupt Flag */ +#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define I2C_IFS_ARBLOST_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR (1 << 10) /**< Set Bus Error Interrupt Flag */ +#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define I2C_IFS_BUSERR_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD (1 << 11) /**< Set Bus Held Interrupt Flag */ +#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define I2C_IFS_BUSHOLD_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF (1 << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define I2C_IFS_TXOF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF (1 << 13) /**< Set Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define I2C_IFS_RXUF_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO (1 << 14) /**< Set Bus Idle Timeout Interrupt Flag */ +#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define I2C_IFS_BITO_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO (1 << 15) /**< Set Clock Low Interrupt Flag */ +#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define I2C_IFS_CLTO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP (1 << 16) /**< Set SSTOP Interrupt Flag */ +#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define I2C_IFS_SSTOP_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_IFS */ +#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ + +/** Bit fields for I2C IFC */ +#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ +#define _I2C_IFC_MASK 0x0001FFFFUL /**< Mask for I2C_IFC */ +#define I2C_IFC_START (1 << 0) /**< Clear START Interrupt Flag */ +#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define I2C_IFC_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART (1 << 1) /**< Clear Repeated START Interrupt Flag */ +#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define I2C_IFC_RSTART_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR (1 << 2) /**< Clear Address Interrupt Flag */ +#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define I2C_IFC_ADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC (1 << 3) /**< Clear Transfer Completed Interrupt Flag */ +#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define I2C_IFC_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXBL (1 << 4) /**< Clear Transmit Buffer level Interrupt Flag */ +#define _I2C_IFC_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IFC_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define I2C_IFC_TXBL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXDATAV (1 << 5) /**< Clear Receive Data Valid Interrupt Flag */ +#define _I2C_IFC_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IFC_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define I2C_IFC_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK (1 << 6) /**< Clear Acknowledge Received Interrupt Flag */ +#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define I2C_IFC_ACK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK (1 << 7) /**< Clear Not Acknowledge Received Interrupt Flag */ +#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define I2C_IFC_NACK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP (1 << 8) /**< Clear MSTOP Interrupt Flag */ +#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define I2C_IFC_MSTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST (1 << 9) /**< Clear Arbitration Lost Interrupt Flag */ +#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define I2C_IFC_ARBLOST_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR (1 << 10) /**< Clear Bus Error Interrupt Flag */ +#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define I2C_IFC_BUSERR_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD (1 << 11) /**< Clear Bus Held Interrupt Flag */ +#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define I2C_IFC_BUSHOLD_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF (1 << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define I2C_IFC_TXOF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF (1 << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define I2C_IFC_RXUF_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO (1 << 14) /**< Clear Bus Idle Timeout Interrupt Flag */ +#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define I2C_IFC_BITO_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO (1 << 15) /**< Clear Clock Low Interrupt Flag */ +#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define I2C_IFC_CLTO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP (1 << 16) /**< Clear SSTOP Interrupt Flag */ +#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define I2C_IFC_SSTOP_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_IFC */ +#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ + +/** Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (1 << 0) /**< START Condition Interrupt Enable */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define I2C_IEN_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (1 << 1) /**< Repeated START condition Interrupt Enable */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define I2C_IEN_RSTART_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (1 << 2) /**< Address Interrupt Enable */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define I2C_IEN_ADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (1 << 3) /**< Transfer Completed Interrupt Enable */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define I2C_IEN_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (1 << 4) /**< Transmit Buffer level Interrupt Enable */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define I2C_IEN_TXBL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (1 << 5) /**< Receive Data Valid Interrupt Enable */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define I2C_IEN_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (1 << 6) /**< Acknowledge Received Interrupt Enable */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define I2C_IEN_ACK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (1 << 7) /**< Not Acknowledge Received Interrupt Enable */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define I2C_IEN_NACK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (1 << 8) /**< MSTOP Interrupt Enable */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define I2C_IEN_MSTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (1 << 9) /**< Arbitration Lost Interrupt Enable */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define I2C_IEN_ARBLOST_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (1 << 10) /**< Bus Error Interrupt Enable */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define I2C_IEN_BUSERR_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (1 << 11) /**< Bus Held Interrupt Enable */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define I2C_IEN_BUSHOLD_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (1 << 12) /**< Transmit Buffer Overflow Interrupt Enable */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define I2C_IEN_TXOF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (1 << 13) /**< Receive Buffer Underflow Interrupt Enable */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define I2C_IEN_RXUF_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (1 << 14) /**< Bus Idle Timeout Interrupt Enable */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define I2C_IEN_BITO_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (1 << 15) /**< Clock Low Interrupt Enable */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define I2C_IEN_CLTO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (1 << 16) /**< SSTOP Interrupt Enable */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define I2C_IEN_SSTOP_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ + +/** Bit fields for I2C ROUTE */ +#define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */ +#define _I2C_ROUTE_MASK 0x00000303UL /**< Mask for I2C_ROUTE */ +#define I2C_ROUTE_SDAPEN (1 << 0) /**< SDA Pin Enable */ +#define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ +#define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ +#define I2C_ROUTE_SDAPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */ +#define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */ +#define I2C_ROUTE_SCLPEN (1 << 1) /**< SCL Pin Enable */ +#define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ +#define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ +#define I2C_ROUTE_SCLPEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */ +#define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */ +#define _I2C_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for I2C_LOCATION */ +#define I2C_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_ADC + * @{ + */ + +/** Bit fields for ADC CTRL */ +#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */ +#define _ADC_CTRL_MASK 0x0F1F7F3BUL /**< Mask for ADC_CTRL */ +#define _ADC_CTRL_ENERGYMODE_SHIFT 0 /**< Shift value for ADC_ENERGYMODE */ +#define _ADC_CTRL_ENERGYMODE_MASK 0x3UL /**< Bit mask for ADC_ENERGYMODE */ +#define ADC_CTRL_ENERGYMODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ENERGYMODE_NORMAL (0x00000000UL << 0) /**< Shifted mode NORMAL for ADC_CTRL */ +#define ADC_CTRL_ENERGYMODE_FASTBG (0x00000001UL << 0) /**< Shifted mode FASTBG for ADC_CTRL */ +#define ADC_CTRL_ENERGYMODE_KEEPSCANREFWARM (0x00000002UL << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */ +#define ADC_CTRL_ENERGYMODE_KEEPADCWARM (0x00000003UL << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */ +#define _ADC_CTRL_ENERGYMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ENERGYMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */ +#define _ADC_CTRL_ENERGYMODE_FASTBG 0x00000001UL /**< Mode FASTBG for ADC_CTRL */ +#define _ADC_CTRL_ENERGYMODE_KEEPSCANREFWARM 0x00000002UL /**< Mode KEEPSCANREFWARM for ADC_CTRL */ +#define _ADC_CTRL_ENERGYMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_TAILGATE (1 << 3) /**< Conversion Tailgating */ +#define _ADC_CTRL_TAILGATE_SHIFT 3 /**< Shift value for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_MASK 0x8UL /**< Bit mask for ADC_TAILGATE */ +#define ADC_CTRL_TAILGATE_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_LPFMODE_SHIFT 4 /**< Shift value for ADC_LPFMODE */ +#define _ADC_CTRL_LPFMODE_MASK 0x30UL /**< Bit mask for ADC_LPFMODE */ +#define ADC_CTRL_LPFMODE_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_LPFMODE_BYPASS (0x00000000UL << 4) /**< Shifted mode BYPASS for ADC_CTRL */ +#define ADC_CTRL_LPFMODE_RCFILT (0x00000001UL << 4) /**< Shifted mode RCFILT for ADC_CTRL */ +#define ADC_CTRL_LPFMODE_DECAP (0x00000002UL << 4) /**< Shifted mode DECAP for ADC_CTRL */ +#define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /**< Mode BYPASS for ADC_CTRL */ +#define _ADC_CTRL_LPFMODE_RCFILT 0x00000001UL /**< Mode RCFILT for ADC_CTRL */ +#define _ADC_CTRL_LPFMODE_DECAP 0x00000002UL /**< Mode DECAP for ADC_CTRL */ +#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */ +#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */ +#define ADC_CTRL_PRESC_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_PRESC_NODIVISION (0x00000000UL << 8) /**< Shifted mode NODIVISION for ADC_CTRL */ +#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */ +#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_MASK 0x1F0000UL /**< Bit mask for ADC_TIMEBASE */ +#define ADC_CTRL_TIMEBASE_DEFAULT (0x0000001FUL << 16) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_SHIFT 24 /**< Shift value for ADC_OSRSEL */ +#define _ADC_CTRL_OSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OSRSEL */ +#define ADC_CTRL_OSRSEL_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR2 (0x00000000UL << 24) /**< Shifted mode OSR2 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR4 (0x00000001UL << 24) /**< Shifted mode OSR4 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR8 (0x00000002UL << 24) /**< Shifted mode OSR8 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR16 (0x00000003UL << 24) /**< Shifted mode OSR16 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR32 (0x00000004UL << 24) /**< Shifted mode OSR32 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR64 (0x00000005UL << 24) /**< Shifted mode OSR64 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR128 (0x00000006UL << 24) /**< Shifted mode OSR128 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR256 (0x00000007UL << 24) /**< Shifted mode OSR256 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR512 (0x00000008UL << 24) /**< Shifted mode OSR512 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR1024 (0x00000009UL << 24) /**< Shifted mode OSR1024 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR2048 (0x0000000AUL << 24) /**< Shifted mode OSR2048 for ADC_CTRL */ +#define ADC_CTRL_OSRSEL_OSR4096 (0x0000000BUL << 24) /**< Shifted mode OSR4096 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR2 0x00000000UL /**< Mode OSR2 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR4 0x00000001UL /**< Mode OSR4 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR8 0x00000002UL /**< Mode OSR8 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR16 0x00000003UL /**< Mode OSR16 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR32 0x00000004UL /**< Mode OSR32 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR64 0x00000005UL /**< Mode OSR64 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR128 0x00000006UL /**< Mode OSR128 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR256 0x00000007UL /**< Mode OSR256 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR512 0x00000008UL /**< Mode OSR512 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR1024 0x00000009UL /**< Mode OSR1024 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR2048 0x0000000AUL /**< Mode OSR2048 for ADC_CTRL */ +#define _ADC_CTRL_OSRSEL_OSR4096 0x0000000BUL /**< Mode OSR4096 for ADC_CTRL */ + +/** Bit fields for ADC CMD */ +#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */ +#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */ +#define ADC_CMD_SINGLESTART (1 << 0) /**< Single Conversion Start */ +#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */ +#define ADC_CMD_SINGLESTART_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_CMD */ +#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP (1 << 1) /**< Single Conversion Stop */ +#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */ +#define ADC_CMD_SINGLESTOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_CMD */ +#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART (1 << 2) /**< Scan Sequence Start */ +#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */ +#define ADC_CMD_SCANSTART_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for ADC_CMD */ +#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP (1 << 3) /**< Scan Sequence Stop */ +#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */ +#define ADC_CMD_SCANSTOP_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for ADC_CMD */ +#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ + +/** Bit fields for ADC STATUS */ +#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */ +#define _ADC_STATUS_MASK 0x07031303UL /**< Mask for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT (1 << 0) /**< Single Conversion Active */ +#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */ +#define ADC_STATUS_SINGLEACT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT (1 << 1) /**< Scan Conversion Active */ +#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */ +#define ADC_STATUS_SCANACT_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM (1 << 8) /**< Single Reference Warmed Up */ +#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */ +#define ADC_STATUS_SINGLEREFWARM_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM (1 << 9) /**< Scan Reference Warmed Up */ +#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */ +#define ADC_STATUS_SCANREFWARM_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_WARM (1 << 12) /**< ADC Warmed Up */ +#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */ +#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */ +#define ADC_STATUS_WARM_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV (1 << 16) /**< Single Sample Data Valid */ +#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */ +#define ADC_STATUS_SINGLEDV_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV (1 << 17) /**< Scan Data Valid */ +#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */ +#define ADC_STATUS_SCANDV_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_SHIFT 24 /**< Shift value for ADC_SCANDATASRC */ +#define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /**< Bit mask for ADC_SCANDATASRC */ +#define ADC_STATUS_SCANDATASRC_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CHANNEL0 (0x00000000UL << 24) /**< Shifted mode CHANNEL0 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CHANNEL1 (0x00000001UL << 24) /**< Shifted mode CHANNEL1 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CHANNEL2 (0x00000002UL << 24) /**< Shifted mode CHANNEL2 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CHANNEL3 (0x00000003UL << 24) /**< Shifted mode CHANNEL3 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CHANNEL4 (0x00000004UL << 24) /**< Shifted mode CHANNEL4 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CHANNEL5 (0x00000005UL << 24) /**< Shifted mode CHANNEL5 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CHANNEL6 (0x00000006UL << 24) /**< Shifted mode CHANNEL6 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CHANNEL7 (0x00000007UL << 24) /**< Shifted mode CHANNEL7 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CHANNEL0 0x00000000UL /**< Mode CHANNEL0 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CHANNEL1 0x00000001UL /**< Mode CHANNEL1 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CHANNEL2 0x00000002UL /**< Mode CHANNEL2 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CHANNEL3 0x00000003UL /**< Mode CHANNEL3 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CHANNEL4 0x00000004UL /**< Mode CHANNEL4 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CHANNEL5 0x00000005UL /**< Mode CHANNEL5 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CHANNEL6 0x00000006UL /**< Mode CHANNEL6 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CHANNEL7 0x00000007UL /**< Mode CHANNEL7 for ADC_STATUS */ + +/** Bit fields for ADC SINGLECTRL */ +#define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_MASK 0x71F70F37UL /**< Mask for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEREP (1 << 0) /**< Single Sample Repetitive Mode */ +#define _ADC_SINGLECTRL_SINGLEREP_SHIFT 0 /**< Shift value for ADC_SINGLEREP */ +#define _ADC_SINGLECTRL_SINGLEREP_MASK 0x1UL /**< Bit mask for ADC_SINGLEREP */ +#define ADC_SINGLECTRL_SINGLEREP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEDIFF (1 << 1) /**< Single Sample Differential Mode */ +#define _ADC_SINGLECTRL_SINGLEDIFF_SHIFT 1 /**< Shift value for ADC_SINGLEDIFF */ +#define _ADC_SINGLECTRL_SINGLEDIFF_MASK 0x2UL /**< Bit mask for ADC_SINGLEDIFF */ +#define ADC_SINGLECTRL_SINGLEDIFF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEADJ (1 << 2) /**< Single Sample Result Adjustment */ +#define _ADC_SINGLECTRL_SINGLEADJ_SHIFT 2 /**< Shift value for ADC_SINGLEADJ */ +#define _ADC_SINGLECTRL_SINGLEADJ_MASK 0x4UL /**< Bit mask for ADC_SINGLEADJ */ +#define ADC_SINGLECTRL_SINGLEADJ_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEADJ_RIGHT (0x00000000UL << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEADJ_LEFT (0x00000001UL << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLERES_SHIFT 4 /**< Shift value for ADC_SINGLERES */ +#define _ADC_SINGLECTRL_SINGLERES_MASK 0x30UL /**< Bit mask for ADC_SINGLERES */ +#define ADC_SINGLECTRL_SINGLERES_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLERES_12BIT (0x00000000UL << 4) /**< Shifted mode 12BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLERES_8BIT (0x00000001UL << 4) /**< Shifted mode 8BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLERES_6BIT (0x00000002UL << 4) /**< Shifted mode 6BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLERES_OS (0x00000003UL << 4) /**< Shifted mode OS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLERES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLERES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLERES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLERES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLERES_OS 0x00000003UL /**< Mode OS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_SHIFT 8 /**< Shift value for ADC_SINGLESEL */ +#define _ADC_SINGLECTRL_SINGLESEL_MASK 0xF00UL /**< Bit mask for ADC_SINGLESEL */ +#define ADC_SINGLECTRL_SINGLESEL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL0 (0x00000000UL << 8) /**< Shifted mode CHANNEL0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL1 (0x00000001UL << 8) /**< Shifted mode CHANNEL1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL2 (0x00000002UL << 8) /**< Shifted mode CHANNEL2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL3 (0x00000003UL << 8) /**< Shifted mode CHANNEL3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL4 (0x00000004UL << 8) /**< Shifted mode CHANNEL4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL5 (0x00000005UL << 8) /**< Shifted mode CHANNEL5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL6 (0x00000006UL << 8) /**< Shifted mode CHANNEL6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL7 (0x00000007UL << 8) /**< Shifted mode CHANNEL7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL8 (0x00000008UL << 8) /**< Shifted mode CHANNEL8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL9 (0x00000009UL << 8) /**< Shifted mode CHANNEL9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL10 (0x0000000AUL << 8) /**< Shifted mode CHANNEL10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL11 (0x0000000BUL << 8) /**< Shifted mode CHANNEL11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL12 (0x0000000CUL << 8) /**< Shifted mode CHANNEL12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL13 (0x0000000DUL << 8) /**< Shifted mode CHANNEL13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLESEL_CHANNEL14 (0x0000000EUL << 8) /**< Shifted mode CHANNEL14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL0 0x00000000UL /**< Mode CHANNEL0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL1 0x00000001UL /**< Mode CHANNEL1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL2 0x00000002UL /**< Mode CHANNEL2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL3 0x00000003UL /**< Mode CHANNEL3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL4 0x00000004UL /**< Mode CHANNEL4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL5 0x00000005UL /**< Mode CHANNEL5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL6 0x00000006UL /**< Mode CHANNEL6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL7 0x00000007UL /**< Mode CHANNEL7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL8 0x00000008UL /**< Mode CHANNEL8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL9 0x00000009UL /**< Mode CHANNEL9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL10 0x0000000AUL /**< Mode CHANNEL10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL11 0x0000000BUL /**< Mode CHANNEL11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL12 0x0000000CUL /**< Mode CHANNEL12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL13 0x0000000DUL /**< Mode CHANNEL13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL14 0x0000000EUL /**< Mode CHANNEL14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREF_SHIFT 16 /**< Shift value for ADC_SINGLEREF */ +#define _ADC_SINGLECTRL_SINGLEREF_MASK 0x70000UL /**< Bit mask for ADC_SINGLEREF */ +#define ADC_SINGLECTRL_SINGLEREF_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEREF_1V25 (0x00000000UL << 16) /**< Shifted mode 1V25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEREF_2V5 (0x00000001UL << 16) /**< Shifted mode 2V5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEREF_VDD (0x00000002UL << 16) /**< Shifted mode VDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEREF_5VDIFF (0x00000003UL << 16) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEREF_EXTSINGLE (0x00000004UL << 16) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEREF_EXTDIFF (0x00000005UL << 16) /**< Shifted mode EXTDIFF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEREF_2XVDDVSS (0x00000006UL << 16) /**< Shifted mode 2XVDDVSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREF_EXTDIFF 0x00000005UL /**< Mode EXTDIFF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEREF_2XVDDVSS 0x00000006UL /**< Mode 2XVDDVSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_SHIFT 20 /**< Shift value for ADC_SINGLEAT */ +#define _ADC_SINGLECTRL_SINGLEAT_MASK 0xF00000UL /**< Bit mask for ADC_SINGLEAT */ +#define ADC_SINGLECTRL_SINGLEAT_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEAT_1CYCLE (0x00000000UL << 20) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEAT_2CYCLES (0x00000001UL << 20) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEAT_4CYCLES (0x00000002UL << 20) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEAT_8CYCLES (0x00000003UL << 20) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEAT_16CYCLES (0x00000004UL << 20) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEAT_32CYCLES (0x00000005UL << 20) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEAT_64CYCLES (0x00000006UL << 20) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEAT_128CYCLES (0x00000007UL << 20) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEAT_256CYCLES (0x00000008UL << 20) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEAT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEPRSEN (1 << 24) /**< Single Sample PRS Trigger Enable */ +#define _ADC_SINGLECTRL_SINGLEPRSEN_SHIFT 24 /**< Shift value for ADC_SINGLEPRSEN */ +#define _ADC_SINGLECTRL_SINGLEPRSEN_MASK 0x1000000UL /**< Bit mask for ADC_SINGLEPRSEN */ +#define ADC_SINGLECTRL_SINGLEPRSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_SHIFT 28 /**< Shift value for ADC_SINGLEPRSSEL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_MASK 0x70000000UL /**< Bit mask for ADC_SINGLEPRSSEL */ +#define ADC_SINGLECTRL_SINGLEPRSSEL_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH0 (0x00000000UL << 28) /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH1 (0x00000001UL << 28) /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH2 (0x00000002UL << 28) /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH3 (0x00000003UL << 28) /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH4 (0x00000004UL << 28) /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH5 (0x00000005UL << 28) /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH6 (0x00000006UL << 28) /**< Shifted mode PRSCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH7 (0x00000007UL << 28) /**< Shifted mode PRSCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRL */ + +/** Bit fields for ADC SCANCTRL */ +#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_MASK 0x71F7FF37UL /**< Mask for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANREP (1 << 0) /**< Scan Sequence Repetitive Mode */ +#define _ADC_SCANCTRL_SCANREP_SHIFT 0 /**< Shift value for ADC_SCANREP */ +#define _ADC_SCANCTRL_SCANREP_MASK 0x1UL /**< Bit mask for ADC_SCANREP */ +#define ADC_SCANCTRL_SCANREP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANDIFF (1 << 1) /**< Scan Sequence Differential Mode */ +#define _ADC_SCANCTRL_SCANDIFF_SHIFT 1 /**< Shift value for ADC_SCANDIFF */ +#define _ADC_SCANCTRL_SCANDIFF_MASK 0x2UL /**< Bit mask for ADC_SCANDIFF */ +#define ADC_SCANCTRL_SCANDIFF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANADJ (1 << 2) /**< Scan Sequence Result Adjustment */ +#define _ADC_SCANCTRL_SCANADJ_SHIFT 2 /**< Shift value for ADC_SCANADJ */ +#define _ADC_SCANCTRL_SCANADJ_MASK 0x4UL /**< Bit mask for ADC_SCANADJ */ +#define ADC_SCANCTRL_SCANADJ_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANADJ_RIGHT (0x00000000UL << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANADJ_LEFT (0x00000001UL << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANRES_SHIFT 4 /**< Shift value for ADC_SCANRES */ +#define _ADC_SCANCTRL_SCANRES_MASK 0x30UL /**< Bit mask for ADC_SCANRES */ +#define ADC_SCANCTRL_SCANRES_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANRES_12BIT (0x00000000UL << 4) /**< Shifted mode 12BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANRES_8BIT (0x00000001UL << 4) /**< Shifted mode 8BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANRES_6BIT (0x00000002UL << 4) /**< Shifted mode 6BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANRES_OS (0x00000003UL << 4) /**< Shifted mode OS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANRES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANRES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANRES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANRES_OS 0x00000003UL /**< Mode OS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_SHIFT 8 /**< Shift value for ADC_SCANMASK */ +#define _ADC_SCANCTRL_SCANMASK_MASK 0xFF00UL /**< Bit mask for ADC_SCANMASK */ +#define ADC_SCANCTRL_SCANMASK_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANMASK_CHANNEL0 (0x00000000UL << 8) /**< Shifted mode CHANNEL0 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANMASK_CHANNEL1 (0x00000001UL << 8) /**< Shifted mode CHANNEL1 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANMASK_CHANNEL2 (0x00000002UL << 8) /**< Shifted mode CHANNEL2 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANMASK_CHANNEL3 (0x00000003UL << 8) /**< Shifted mode CHANNEL3 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANMASK_CHANNEL4 (0x00000004UL << 8) /**< Shifted mode CHANNEL4 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANMASK_CHANNEL5 (0x00000005UL << 8) /**< Shifted mode CHANNEL5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANMASK_CHANNEL6 (0x00000006UL << 8) /**< Shifted mode CHANNEL6 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANMASK_CHANNEL7 (0x00000007UL << 8) /**< Shifted mode CHANNEL7 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_CHANNEL0 0x00000000UL /**< Mode CHANNEL0 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_CHANNEL1 0x00000001UL /**< Mode CHANNEL1 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_CHANNEL2 0x00000002UL /**< Mode CHANNEL2 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_CHANNEL3 0x00000003UL /**< Mode CHANNEL3 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_CHANNEL4 0x00000004UL /**< Mode CHANNEL4 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_CHANNEL5 0x00000005UL /**< Mode CHANNEL5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_CHANNEL6 0x00000006UL /**< Mode CHANNEL6 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANMASK_CHANNEL7 0x00000007UL /**< Mode CHANNEL7 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREF_SHIFT 16 /**< Shift value for ADC_SCANREF */ +#define _ADC_SCANCTRL_SCANREF_MASK 0x70000UL /**< Bit mask for ADC_SCANREF */ +#define ADC_SCANCTRL_SCANREF_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANREF_1V25 (0x00000000UL << 16) /**< Shifted mode 1V25 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANREF_2V5 (0x00000001UL << 16) /**< Shifted mode 2V5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANREF_VDD (0x00000002UL << 16) /**< Shifted mode VDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANREF_5VDIFF (0x00000003UL << 16) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANREF_EXTSINGLE (0x00000004UL << 16) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANREF_EXTDIFF (0x00000005UL << 16) /**< Shifted mode EXTDIFF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANREF_2XVDDVSS (0x00000006UL << 16) /**< Shifted mode 2XVDDVSS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREF_EXTDIFF 0x00000005UL /**< Mode EXTDIFF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANREF_2XVDDVSS 0x00000006UL /**< Mode 2XVDDVSS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_SHIFT 20 /**< Shift value for ADC_SCANAT */ +#define _ADC_SCANCTRL_SCANAT_MASK 0xF00000UL /**< Bit mask for ADC_SCANAT */ +#define ADC_SCANCTRL_SCANAT_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANAT_1CYCLE (0x00000000UL << 20) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANAT_2CYCLES (0x00000001UL << 20) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANAT_4CYCLES (0x00000002UL << 20) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANAT_8CYCLES (0x00000003UL << 20) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANAT_16CYCLES (0x00000004UL << 20) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANAT_32CYCLES (0x00000005UL << 20) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANAT_64CYCLES (0x00000006UL << 20) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANAT_128CYCLES (0x00000007UL << 20) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANAT_256CYCLES (0x00000008UL << 20) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANAT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANPRSEN (1 << 24) /**< Scan Sequence PRS Trigger Enable */ +#define _ADC_SCANCTRL_SCANPRSEN_SHIFT 24 /**< Shift value for ADC_SCANPRSEN */ +#define _ADC_SCANCTRL_SCANPRSEN_MASK 0x1000000UL /**< Bit mask for ADC_SCANPRSEN */ +#define ADC_SCANCTRL_SCANPRSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_SHIFT 28 /**< Shift value for ADC_SCANPRSSEL */ +#define _ADC_SCANCTRL_SCANPRSSEL_MASK 0x70000000UL /**< Bit mask for ADC_SCANPRSSEL */ +#define ADC_SCANCTRL_SCANPRSSEL_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANPRSSEL_PRSCH0 (0x00000000UL << 28) /**< Shifted mode PRSCH0 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANPRSSEL_PRSCH1 (0x00000001UL << 28) /**< Shifted mode PRSCH1 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANPRSSEL_PRSCH2 (0x00000002UL << 28) /**< Shifted mode PRSCH2 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANPRSSEL_PRSCH3 (0x00000003UL << 28) /**< Shifted mode PRSCH3 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANPRSSEL_PRSCH4 (0x00000004UL << 28) /**< Shifted mode PRSCH4 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANPRSSEL_PRSCH5 (0x00000005UL << 28) /**< Shifted mode PRSCH5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANPRSSEL_PRSCH6 (0x00000006UL << 28) /**< Shifted mode PRSCH6 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_SCANPRSSEL_PRSCH7 (0x00000007UL << 28) /**< Shifted mode PRSCH7 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRL */ + +/** Bit fields for ADC IEN */ +#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */ +#define _ADC_IEN_MASK 0x00000303UL /**< Mask for ADC_IEN */ +#define ADC_IEN_SINGLE (1 << 0) /**< Single Conversion Complete Interrupt Enable */ +#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define ADC_IEN_SINGLE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_IEN */ +#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN (1 << 1) /**< Scan Conversion Complete Interrupt Enable */ +#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define ADC_IEN_SCAN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_IEN */ +#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF (1 << 8) /**< Single Result Overflow Interrupt Enable */ +#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define ADC_IEN_SINGLEOF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_IEN */ +#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF (1 << 9) /**< Scan Result Overflow Interrupt Enable */ +#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define ADC_IEN_SCANOF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_IEN */ +#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ + +/** Bit fields for ADC IF */ +#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */ +#define _ADC_IF_MASK 0x00000303UL /**< Mask for ADC_IF */ +#define ADC_IF_SINGLE (1 << 0) /**< Single Conversion Complete Interrupt Flag */ +#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define ADC_IF_SINGLE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_IF */ +#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN (1 << 1) /**< Scan Conversion Complete Interrupt Flag */ +#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define ADC_IF_SCAN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_IF */ +#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF (1 << 8) /**< Single Result Overflow Interrupt Flag */ +#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define ADC_IF_SINGLEOF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_IF */ +#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF (1 << 9) /**< Scan Result Overflow Interrupt Flag */ +#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define ADC_IF_SCANOF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_IF */ +#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ + +/** Bit fields for ADC IFS */ +#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */ +#define _ADC_IFS_MASK 0x00000303UL /**< Mask for ADC_IFS */ +#define ADC_IFS_SINGLE (1 << 0) /**< Single Conversion Complete Interrupt Flag Set */ +#define _ADC_IFS_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IFS_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define ADC_IFS_SINGLE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_IFS */ +#define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCAN (1 << 1) /**< Scan Conversion Complete Interrupt Flag Set */ +#define _ADC_IFS_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IFS_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define ADC_IFS_SCAN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_IFS */ +#define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEOF (1 << 8) /**< Single Result Overflow Interrupt Flag Set */ +#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define ADC_IFS_SINGLEOF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_IFS */ +#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF (1 << 9) /**< Scan Result Overflow Interrupt Flag Set */ +#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define ADC_IFS_SCANOF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_IFS */ +#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ + +/** Bit fields for ADC IFC */ +#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */ +#define _ADC_IFC_MASK 0x00000303UL /**< Mask for ADC_IFC */ +#define ADC_IFC_SINGLE (1 << 0) /**< Single Conversion Complete Interrupt Flag Clear */ +#define _ADC_IFC_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IFC_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define ADC_IFC_SINGLE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_IFC */ +#define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCAN (1 << 1) /**< Scan Conversion Complete Interrupt Flag Clear */ +#define _ADC_IFC_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IFC_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define ADC_IFC_SCAN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_IFC */ +#define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEOF (1 << 8) /**< Single Result Overflow Interrupt Flag Clear */ +#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define ADC_IFC_SINGLEOF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_IFC */ +#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF (1 << 9) /**< Scan Result Overflow Interrupt Flag Clear */ +#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define ADC_IFC_SCANOF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_IFC */ +#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ + +/** Bit fields for ADC SINGLEDATA */ +#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_SINGLEDATA_SHIFT 0 /**< Shift value for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SINGLEDATA */ +#define ADC_SINGLEDATA_SINGLEDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_SINGLEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */ + +/** Bit fields for ADC SCANDATA */ +#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */ +#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */ +#define _ADC_SCANDATA_SCANDATA_SHIFT 0 /**< Shift value for ADC_SCANDATA */ +#define _ADC_SCANDATA_SCANDATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANDATA */ +#define ADC_SCANDATA_SCANDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */ +#define _ADC_SCANDATA_SCANDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */ + +/** Bit fields for ADC SINGLEDATAP */ +#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_SINGLEDATA_SHIFT 0 /**< Shift value for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATAP_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SINGLEDATA */ +#define ADC_SINGLEDATAP_SINGLEDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_SINGLEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */ + +/** Bit fields for ADC SCANDATAP */ +#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_SCANDATAP_SHIFT 0 /**< Shift value for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_SCANDATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANDATAP */ +#define ADC_SCANDATAP_SCANDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_SCANDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */ + +/** Bit fields for ADC CAL */ +#define _ADC_CAL_RESETVALUE 0x3F003F00UL /**< Default value for ADC_CAL */ +#define _ADC_CAL_MASK 0x7F7F7F7FUL /**< Mask for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /**< Bit mask for ADC_SINGLEOFFSET */ +#define ADC_CAL_SINGLEOFFSET_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */ +#define ADC_CAL_SINGLEGAIN_DEFAULT (0x0000003FUL << 8) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /**< Bit mask for ADC_SCANOFFSET */ +#define ADC_CAL_SCANOFFSET_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */ +#define ADC_CAL_SCANGAIN_DEFAULT (0x0000003FUL << 24) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */ + +/** Bit fields for ADC ROUTE */ +#define _ADC_ROUTE_RESETVALUE 0x00000000UL /**< Default value for ADC_ROUTE */ +#define _ADC_ROUTE_MASK 0x00000001UL /**< Mask for ADC_ROUTE */ +#define ADC_ROUTE_VCMPEN (1 << 0) /**< VCM Pin Output Enable */ +#define _ADC_ROUTE_VCMPEN_SHIFT 0 /**< Shift value for ADC_VCMPEN */ +#define _ADC_ROUTE_VCMPEN_MASK 0x1UL /**< Bit mask for ADC_VCMPEN */ +#define ADC_ROUTE_VCMPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_ROUTE */ +#define _ADC_ROUTE_VCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_ROUTE */ + +/** Bit fields for ADC BIASPROG */ +#define _ADC_BIASPROG_RESETVALUE 0x00000747UL /**< Default value for ADC_BIASPROG */ +#define _ADC_BIASPROG_MASK 0x00000F4FUL /**< Mask for ADC_BIASPROG */ +#define _ADC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for ADC_BIASPROG */ +#define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for ADC_BIASPROG */ +#define ADC_BIASPROG_BIASPROG_DEFAULT (0x00000007UL << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_HALFBIAS (1 << 6) /**< Half Bias Current */ +#define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for ADC_HALFBIAS */ +#define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for ADC_HALFBIAS */ +#define ADC_BIASPROG_HALFBIAS_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /**< Shift value for ADC_COMPBIAS */ +#define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /**< Bit mask for ADC_COMPBIAS */ +#define ADC_BIASPROG_COMPBIAS_DEFAULT (0x00000007UL << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_DAC + * @{ + */ + +/** Bit fields for DAC CTRL */ +#define _DAC_CTRL_RESETVALUE 0x00000010UL /**< Default value for DAC_CTRL */ +#define _DAC_CTRL_MASK 0x0037D3FFUL /**< Mask for DAC_CTRL */ +#define DAC_CTRL_DIFF (1 << 0) /**< Differential Mode */ +#define _DAC_CTRL_DIFF_SHIFT 0 /**< Shift value for DAC_DIFF */ +#define _DAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for DAC_DIFF */ +#define DAC_CTRL_DIFF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_SINEMODE (1 << 1) /**< Sine Mode */ +#define _DAC_CTRL_SINEMODE_SHIFT 1 /**< Shift value for DAC_SINEMODE */ +#define _DAC_CTRL_SINEMODE_MASK 0x2UL /**< Bit mask for DAC_SINEMODE */ +#define DAC_CTRL_SINEMODE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_CONVMODE_SHIFT 2 /**< Shift value for DAC_CONVMODE */ +#define _DAC_CTRL_CONVMODE_MASK 0xCUL /**< Bit mask for DAC_CONVMODE */ +#define DAC_CTRL_CONVMODE_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_CONVMODE_CONTINUOUS (0x00000000UL << 2) /**< Shifted mode CONTINUOUS for DAC_CTRL */ +#define DAC_CTRL_CONVMODE_SAMPLEHOLD (0x00000001UL << 2) /**< Shifted mode SAMPLEHOLD for DAC_CTRL */ +#define DAC_CTRL_CONVMODE_SAMPLEOFF (0x00000002UL << 2) /**< Shifted mode SAMPLEOFF for DAC_CTRL */ +#define _DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for DAC_CTRL */ +#define _DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL /**< Mode SAMPLEHOLD for DAC_CTRL */ +#define _DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL /**< Mode SAMPLEOFF for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_SHIFT 4 /**< Shift value for DAC_OUTMODE */ +#define _DAC_CTRL_OUTMODE_MASK 0x30UL /**< Bit mask for DAC_OUTMODE */ +#define DAC_CTRL_OUTMODE_DISABLE (0x00000000UL << 4) /**< Shifted mode DISABLE for DAC_CTRL */ +#define DAC_CTRL_OUTMODE_DEFAULT (0x00000001UL << 4) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_OUTMODE_PIN (0x00000001UL << 4) /**< Shifted mode PIN for DAC_CTRL */ +#define DAC_CTRL_OUTMODE_ADC (0x00000002UL << 4) /**< Shifted mode ADC for DAC_CTRL */ +#define DAC_CTRL_OUTMODE_PINADC (0x00000003UL << 4) /**< Shifted mode PINADC for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_PIN 0x00000001UL /**< Mode PIN for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_ADC 0x00000002UL /**< Mode ADC for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_PINADC 0x00000003UL /**< Mode PINADC for DAC_CTRL */ +#define DAC_CTRL_OUTENPRS (1 << 6) /**< PRS Controlled Output Enable */ +#define _DAC_CTRL_OUTENPRS_SHIFT 6 /**< Shift value for DAC_OUTENPRS */ +#define _DAC_CTRL_OUTENPRS_MASK 0x40UL /**< Bit mask for DAC_OUTENPRS */ +#define DAC_CTRL_OUTENPRS_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_CH0PRESCRST (1 << 7) /**< Channel 0 Start Reset Prescaler */ +#define _DAC_CTRL_CH0PRESCRST_SHIFT 7 /**< Shift value for DAC_CH0PRESCRST */ +#define _DAC_CTRL_CH0PRESCRST_MASK 0x80UL /**< Bit mask for DAC_CH0PRESCRST */ +#define DAC_CTRL_CH0PRESCRST_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for DAC_REFSEL */ +#define _DAC_CTRL_REFSEL_MASK 0x300UL /**< Bit mask for DAC_REFSEL */ +#define DAC_CTRL_REFSEL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_REFSEL_1V25 (0x00000000UL << 8) /**< Shifted mode 1V25 for DAC_CTRL */ +#define DAC_CTRL_REFSEL_2V5 (0x00000001UL << 8) /**< Shifted mode 2V5 for DAC_CTRL */ +#define DAC_CTRL_REFSEL_VDD (0x00000002UL << 8) /**< Shifted mode VDD for DAC_CTRL */ +#define _DAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_REFSEL_1V25 0x00000000UL /**< Mode 1V25 for DAC_CTRL */ +#define _DAC_CTRL_REFSEL_2V5 0x00000001UL /**< Mode 2V5 for DAC_CTRL */ +#define _DAC_CTRL_REFSEL_VDD 0x00000002UL /**< Mode VDD for DAC_CTRL */ +#define DAC_CTRL_LPFEN (1 << 12) /**< Low Pass Filter Enable */ +#define _DAC_CTRL_LPFEN_SHIFT 12 /**< Shift value for DAC_LPFEN */ +#define _DAC_CTRL_LPFEN_MASK 0x1000UL /**< Bit mask for DAC_LPFEN */ +#define DAC_CTRL_LPFEN_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_LPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_LPFFREQ_SHIFT 14 /**< Shift value for DAC_LPFFREQ */ +#define _DAC_CTRL_LPFFREQ_MASK 0xC000UL /**< Bit mask for DAC_LPFFREQ */ +#define DAC_CTRL_LPFFREQ_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_LPFFREQ_FREQ0 (0x00000000UL << 14) /**< Shifted mode FREQ0 for DAC_CTRL */ +#define DAC_CTRL_LPFFREQ_FREQ1 (0x00000001UL << 14) /**< Shifted mode FREQ1 for DAC_CTRL */ +#define DAC_CTRL_LPFFREQ_FREQ2 (0x00000002UL << 14) /**< Shifted mode FREQ2 for DAC_CTRL */ +#define DAC_CTRL_LPFFREQ_FREQ3 (0x00000003UL << 14) /**< Shifted mode FREQ3 for DAC_CTRL */ +#define _DAC_CTRL_LPFFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_LPFFREQ_FREQ0 0x00000000UL /**< Mode FREQ0 for DAC_CTRL */ +#define _DAC_CTRL_LPFFREQ_FREQ1 0x00000001UL /**< Mode FREQ1 for DAC_CTRL */ +#define _DAC_CTRL_LPFFREQ_FREQ2 0x00000002UL /**< Mode FREQ2 for DAC_CTRL */ +#define _DAC_CTRL_LPFFREQ_FREQ3 0x00000003UL /**< Mode FREQ3 for DAC_CTRL */ +#define _DAC_CTRL_PRESC_SHIFT 16 /**< Shift value for DAC_PRESC */ +#define _DAC_CTRL_PRESC_MASK 0x70000UL /**< Bit mask for DAC_PRESC */ +#define DAC_CTRL_PRESC_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_PRESC_NODIVISION (0x00000000UL << 16) /**< Shifted mode NODIVISION for DAC_CTRL */ +#define _DAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_SHIFT 20 /**< Shift value for DAC_REFRSEL */ +#define _DAC_CTRL_REFRSEL_MASK 0x300000UL /**< Bit mask for DAC_REFRSEL */ +#define DAC_CTRL_REFRSEL_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_REFRSEL_8CYCLES (0x00000000UL << 20) /**< Shifted mode 8CYCLES for DAC_CTRL */ +#define DAC_CTRL_REFRSEL_16CYCLES (0x00000001UL << 20) /**< Shifted mode 16CYCLES for DAC_CTRL */ +#define DAC_CTRL_REFRSEL_32CYCLES (0x00000002UL << 20) /**< Shifted mode 32CYCLES for DAC_CTRL */ +#define DAC_CTRL_REFRSEL_64CYCLES (0x00000003UL << 20) /**< Shifted mode 64CYCLES for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL /**< Mode 8CYCLES for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL /**< Mode 16CYCLES for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL /**< Mode 32CYCLES for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL /**< Mode 64CYCLES for DAC_CTRL */ + +/** Bit fields for DAC STATUS */ +#define _DAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DAC_STATUS */ +#define _DAC_STATUS_MASK 0x00000003UL /**< Mask for DAC_STATUS */ +#define DAC_STATUS_CH0DV (1 << 0) /**< Channel 0 Data Valid */ +#define _DAC_STATUS_CH0DV_SHIFT 0 /**< Shift value for DAC_CH0DV */ +#define _DAC_STATUS_CH0DV_MASK 0x1UL /**< Bit mask for DAC_CH0DV */ +#define DAC_STATUS_CH0DV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_STATUS */ +#define _DAC_STATUS_CH0DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */ +#define DAC_STATUS_CH1DV (1 << 1) /**< Channel 1 Data Valid */ +#define _DAC_STATUS_CH1DV_SHIFT 1 /**< Shift value for DAC_CH1DV */ +#define _DAC_STATUS_CH1DV_MASK 0x2UL /**< Bit mask for DAC_CH1DV */ +#define DAC_STATUS_CH1DV_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_STATUS */ +#define _DAC_STATUS_CH1DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */ + +/** Bit fields for DAC CH0CTRL */ +#define _DAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_MASK 0x00000077UL /**< Mask for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0EN (1 << 0) /**< Channel 0 Enable */ +#define _DAC_CH0CTRL_CH0EN_SHIFT 0 /**< Shift value for DAC_CH0EN */ +#define _DAC_CH0CTRL_CH0EN_MASK 0x1UL /**< Bit mask for DAC_CH0EN */ +#define DAC_CH0CTRL_CH0EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0REFREN (1 << 1) /**< Channel 0 Automatic Refresh Enable */ +#define _DAC_CH0CTRL_CH0REFREN_SHIFT 1 /**< Shift value for DAC_CH0REFREN */ +#define _DAC_CH0CTRL_CH0REFREN_MASK 0x2UL /**< Bit mask for DAC_CH0REFREN */ +#define DAC_CH0CTRL_CH0REFREN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0PRSEN (1 << 2) /**< Channel 0 PRS Trigger Enable */ +#define _DAC_CH0CTRL_CH0PRSEN_SHIFT 2 /**< Shift value for DAC_CH0PRSEN */ +#define _DAC_CH0CTRL_CH0PRSEN_MASK 0x4UL /**< Bit mask for DAC_CH0PRSEN */ +#define DAC_CH0CTRL_CH0PRSEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_SHIFT 4 /**< Shift value for DAC_CH0PRSSEL */ +#define _DAC_CH0CTRL_CH0PRSSEL_MASK 0x70UL /**< Bit mask for DAC_CH0PRSSEL */ +#define DAC_CH0CTRL_CH0PRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0PRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0PRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0PRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0PRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0PRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0PRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0PRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_CH0PRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH0CTRL */ + +/** Bit fields for DAC CH1CTRL */ +#define _DAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_MASK 0x00000077UL /**< Mask for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1EN (1 << 0) /**< Channel 1 Enable */ +#define _DAC_CH1CTRL_CH1EN_SHIFT 0 /**< Shift value for DAC_CH1EN */ +#define _DAC_CH1CTRL_CH1EN_MASK 0x1UL /**< Bit mask for DAC_CH1EN */ +#define DAC_CH1CTRL_CH1EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1REFREN (1 << 1) /**< Channel 1 Automatic Refresh Enable */ +#define _DAC_CH1CTRL_CH1REFREN_SHIFT 1 /**< Shift value for DAC_CH1REFREN */ +#define _DAC_CH1CTRL_CH1REFREN_MASK 0x2UL /**< Bit mask for DAC_CH1REFREN */ +#define DAC_CH1CTRL_CH1REFREN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1PRSEN (1 << 2) /**< Channel 1 PRS Trigger Enable */ +#define _DAC_CH1CTRL_CH1PRSEN_SHIFT 2 /**< Shift value for DAC_CH1PRSEN */ +#define _DAC_CH1CTRL_CH1PRSEN_MASK 0x4UL /**< Bit mask for DAC_CH1PRSEN */ +#define DAC_CH1CTRL_CH1PRSEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_SHIFT 4 /**< Shift value for DAC_CH1PRSSEL */ +#define _DAC_CH1CTRL_CH1PRSSEL_MASK 0x70UL /**< Bit mask for DAC_CH1PRSSEL */ +#define DAC_CH1CTRL_CH1PRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1PRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1PRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1PRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1PRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1PRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1PRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1PRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_CH1PRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH1CTRL */ + +/** Bit fields for DAC IEN */ +#define _DAC_IEN_RESETVALUE 0x00000000UL /**< Default value for DAC_IEN */ +#define _DAC_IEN_MASK 0x00000033UL /**< Mask for DAC_IEN */ +#define DAC_IEN_CH0 (1 << 0) /**< Channel 0 Conversion Complete Interrupt Enable */ +#define _DAC_IEN_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */ +#define _DAC_IEN_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */ +#define DAC_IEN_CH0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_IEN */ +#define _DAC_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH1 (1 << 1) /**< Channel 1 Conversion Complete Interrupt Enable */ +#define _DAC_IEN_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */ +#define _DAC_IEN_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */ +#define DAC_IEN_CH1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_IEN */ +#define _DAC_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH0UF (1 << 4) /**< Channel 0 Conversion Data Underflow Interrupt Enable */ +#define _DAC_IEN_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */ +#define _DAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */ +#define DAC_IEN_CH0UF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_IEN */ +#define _DAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH1UF (1 << 5) /**< Channel 1 Conversion Data Underflow Interrupt Enable */ +#define _DAC_IEN_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */ +#define _DAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */ +#define DAC_IEN_CH1UF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DAC_IEN */ +#define _DAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */ + +/** Bit fields for DAC IF */ +#define _DAC_IF_RESETVALUE 0x00000000UL /**< Default value for DAC_IF */ +#define _DAC_IF_MASK 0x00000033UL /**< Mask for DAC_IF */ +#define DAC_IF_CH0 (1 << 0) /**< Channel 0 Conversion Complete Interrupt Flag */ +#define _DAC_IF_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */ +#define _DAC_IF_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */ +#define DAC_IF_CH0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_IF */ +#define _DAC_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */ +#define DAC_IF_CH1 (1 << 1) /**< Channel 1 Conversion Complete Interrupt Flag */ +#define _DAC_IF_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */ +#define _DAC_IF_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */ +#define DAC_IF_CH1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_IF */ +#define _DAC_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */ +#define DAC_IF_CH0UF (1 << 4) /**< Channel 0 Data Underflow Interrupt Flag */ +#define _DAC_IF_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */ +#define _DAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */ +#define DAC_IF_CH0UF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_IF */ +#define _DAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */ +#define DAC_IF_CH1UF (1 << 5) /**< Channel 1 Data Underflow Interrupt Flag */ +#define _DAC_IF_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */ +#define _DAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */ +#define DAC_IF_CH1UF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DAC_IF */ +#define _DAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */ + +/** Bit fields for DAC IFS */ +#define _DAC_IFS_RESETVALUE 0x00000000UL /**< Default value for DAC_IFS */ +#define _DAC_IFS_MASK 0x00000033UL /**< Mask for DAC_IFS */ +#define DAC_IFS_CH0 (1 << 0) /**< Channel 0 Conversion Complete Interrupt Flag Set */ +#define _DAC_IFS_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */ +#define _DAC_IFS_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */ +#define DAC_IFS_CH0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_IFS */ +#define _DAC_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH1 (1 << 1) /**< Channel 1 Conversion Complete Interrupt Flag Set */ +#define _DAC_IFS_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */ +#define _DAC_IFS_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */ +#define DAC_IFS_CH1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_IFS */ +#define _DAC_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH0UF (1 << 4) /**< Channel 0 Data Underflow Interrupt Flag Set */ +#define _DAC_IFS_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */ +#define _DAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */ +#define DAC_IFS_CH0UF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_IFS */ +#define _DAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH1UF (1 << 5) /**< Channel 1 Data Underflow Interrupt Flag Set */ +#define _DAC_IFS_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */ +#define _DAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */ +#define DAC_IFS_CH1UF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DAC_IFS */ +#define _DAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */ + +/** Bit fields for DAC IFC */ +#define _DAC_IFC_RESETVALUE 0x00000000UL /**< Default value for DAC_IFC */ +#define _DAC_IFC_MASK 0x00000033UL /**< Mask for DAC_IFC */ +#define DAC_IFC_CH0 (1 << 0) /**< Channel 0 Conversion Complete Interrupt Flag Clear */ +#define _DAC_IFC_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */ +#define _DAC_IFC_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */ +#define DAC_IFC_CH0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_IFC */ +#define _DAC_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH1 (1 << 1) /**< Channel 1 Conversion Complete Interrupt Flag Clear */ +#define _DAC_IFC_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */ +#define _DAC_IFC_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */ +#define DAC_IFC_CH1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_IFC */ +#define _DAC_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH0UF (1 << 4) /**< Channel 0 Data Underflow Interrupt Flag Clear */ +#define _DAC_IFC_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */ +#define _DAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */ +#define DAC_IFC_CH0UF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_IFC */ +#define _DAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH1UF (1 << 5) /**< Channel 1 Data Underflow Interrupt Flag Clear */ +#define _DAC_IFC_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */ +#define _DAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */ +#define DAC_IFC_CH1UF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DAC_IFC */ +#define _DAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */ + +/** Bit fields for DAC CH0DATA */ +#define _DAC_CH0DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0DATA */ +#define _DAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH0DATA */ +#define _DAC_CH0DATA_CH0DATA_SHIFT 0 /**< Shift value for DAC_CH0DATA */ +#define _DAC_CH0DATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for DAC_CH0DATA */ +#define DAC_CH0DATA_CH0DATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CH0DATA */ +#define _DAC_CH0DATA_CH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0DATA */ + +/** Bit fields for DAC CH1DATA */ +#define _DAC_CH1DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1DATA */ +#define _DAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH1DATA */ +#define _DAC_CH1DATA_CH1DATA_SHIFT 0 /**< Shift value for DAC_CH1DATA */ +#define _DAC_CH1DATA_CH1DATA_MASK 0xFFFUL /**< Bit mask for DAC_CH1DATA */ +#define DAC_CH1DATA_CH1DATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CH1DATA */ +#define _DAC_CH1DATA_CH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1DATA */ + +/** Bit fields for DAC COMBDATA */ +#define _DAC_COMBDATA_RESETVALUE 0x00000000UL /**< Default value for DAC_COMBDATA */ +#define _DAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for DAC_COMBDATA */ +#define _DAC_COMBDATA_CH0CDATA_SHIFT 0 /**< Shift value for DAC_CH0CDATA */ +#define _DAC_COMBDATA_CH0CDATA_MASK 0xFFFUL /**< Bit mask for DAC_CH0CDATA */ +#define DAC_COMBDATA_CH0CDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_COMBDATA */ +#define _DAC_COMBDATA_CH0CDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */ +#define _DAC_COMBDATA_CH1CDATA_SHIFT 16 /**< Shift value for DAC_CH1CDATA */ +#define _DAC_COMBDATA_CH1CDATA_MASK 0xFFF0000UL /**< Bit mask for DAC_CH1CDATA */ +#define DAC_COMBDATA_CH1CDATA_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for DAC_COMBDATA */ +#define _DAC_COMBDATA_CH1CDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */ + +/** Bit fields for DAC CAL */ +#define _DAC_CAL_RESETVALUE 0x00400000UL /**< Default value for DAC_CAL */ +#define _DAC_CAL_MASK 0x007F7F7FUL /**< Mask for DAC_CAL */ +#define _DAC_CAL_CH0OFFSET_SHIFT 0 /**< Shift value for DAC_CH0OFFSET */ +#define _DAC_CAL_CH0OFFSET_MASK 0x7FUL /**< Bit mask for DAC_CH0OFFSET */ +#define DAC_CAL_CH0OFFSET_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CAL */ +#define _DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */ +#define _DAC_CAL_CH1OFFSET_SHIFT 8 /**< Shift value for DAC_CH1OFFSET */ +#define _DAC_CAL_CH1OFFSET_MASK 0x7F00UL /**< Bit mask for DAC_CH1OFFSET */ +#define DAC_CAL_CH1OFFSET_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for DAC_CAL */ +#define _DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */ +#define _DAC_CAL_GAIN_SHIFT 16 /**< Shift value for DAC_GAIN */ +#define _DAC_CAL_GAIN_MASK 0x7F0000UL /**< Bit mask for DAC_GAIN */ +#define DAC_CAL_GAIN_DEFAULT (0x00000040UL << 16) /**< Shifted mode DEFAULT for DAC_CAL */ +#define _DAC_CAL_GAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for DAC_CAL */ + +/** Bit fields for DAC BIASPROG */ +#define _DAC_BIASPROG_RESETVALUE 0x00000047UL /**< Default value for DAC_BIASPROG */ +#define _DAC_BIASPROG_MASK 0x0000004FUL /**< Mask for DAC_BIASPROG */ +#define _DAC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for DAC_BIASPROG */ +#define _DAC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for DAC_BIASPROG */ +#define DAC_BIASPROG_BIASPROG_DEFAULT (0x00000007UL << 0) /**< Shifted mode DEFAULT for DAC_BIASPROG */ +#define _DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */ +#define DAC_BIASPROG_HALFBIAS (1 << 6) /**< Half Bias Current */ +#define _DAC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for DAC_HALFBIAS */ +#define _DAC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for DAC_HALFBIAS */ +#define DAC_BIASPROG_HALFBIAS_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for DAC_BIASPROG */ +#define _DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_ACMP + * @{ + */ + +/** Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0xCF03077FUL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_EN (1 << 0) /**< Analog Comparator Enable */ +#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define ACMP_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_MUXEN (1 << 1) /**< Input Mux Enable */ +#define _ACMP_CTRL_MUXEN_SHIFT 1 /**< Shift value for ACMP_MUXEN */ +#define _ACMP_CTRL_MUXEN_MASK 0x2UL /**< Bit mask for ACMP_MUXEN */ +#define ACMP_CTRL_MUXEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL (1 << 2) /**< Inactive Value */ +#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */ +#define ACMP_CTRL_INACTVAL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_LOW (0x00000000UL << 2) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_HIGH (0x00000001UL << 2) /**< Shifted mode HIGH for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (1 << 3) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */ +#define ACMP_CTRL_GPIOINV_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (0x00000000UL << 3) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (0x00000001UL << 3) /**< Shifted mode INV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_SHIFT 4 /**< Shift value for ACMP_HYSTSEL */ +#define _ACMP_CTRL_HYSTSEL_MASK 0x70UL /**< Bit mask for ACMP_HYSTSEL */ +#define ACMP_CTRL_HYSTSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST0 (0x00000000UL << 4) /**< Shifted mode HYST0 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST1 (0x00000001UL << 4) /**< Shifted mode HYST1 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST2 (0x00000002UL << 4) /**< Shifted mode HYST2 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST3 (0x00000003UL << 4) /**< Shifted mode HYST3 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST4 (0x00000004UL << 4) /**< Shifted mode HYST4 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST5 (0x00000005UL << 4) /**< Shifted mode HYST5 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST6 (0x00000006UL << 4) /**< Shifted mode HYST6 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST7 (0x00000007UL << 4) /**< Shifted mode HYST7 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for ACMP_WARMTIME */ +#define _ACMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for ACMP_WARMTIME */ +#define ACMP_CTRL_WARMTIME_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_4CYCLES (0x00000000UL << 8) /**< Shifted mode 4CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_8CYCLES (0x00000001UL << 8) /**< Shifted mode 8CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_16CYCLES (0x00000002UL << 8) /**< Shifted mode 16CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_32CYCLES (0x00000003UL << 8) /**< Shifted mode 32CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_64CYCLES (0x00000004UL << 8) /**< Shifted mode 64CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_128CYCLES (0x00000005UL << 8) /**< Shifted mode 128CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_256CYCLES (0x00000006UL << 8) /**< Shifted mode 256CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_512CYCLES (0x00000007UL << 8) /**< Shifted mode 512CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_IRISE (1 << 16) /**< Rising Edge Interrupt Sense */ +#define _ACMP_CTRL_IRISE_SHIFT 16 /**< Shift value for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for ACMP_IRISE */ +#define ACMP_CTRL_IRISE_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DISABLED (0x00000000UL << 16) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_ENABLED (0x00000001UL << 16) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL (1 << 17) /**< Falling Edge Interrupt Sense */ +#define _ACMP_CTRL_IFALL_SHIFT 17 /**< Shift value for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for ACMP_IFALL */ +#define ACMP_CTRL_IFALL_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DISABLED (0x00000000UL << 17) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_ENABLED (0x00000001UL << 17) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for ACMP_BIASPROG */ +#define ACMP_CTRL_BIASPROG_DEFAULT (0x00000007UL << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_HALFBIAS (1 << 30) /**< Half Bias Current */ +#define _ACMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for ACMP_HALFBIAS */ +#define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for ACMP_HALFBIAS */ +#define ACMP_CTRL_HALFBIAS_DEFAULT (0x00000001UL << 30) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS (1 << 31) /**< Full Bias Current */ +#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */ +#define ACMP_CTRL_FULLBIAS_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ + +/** Bit fields for ACMP INPUTSEL */ +#define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL /**< Default value for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_MASK 0x31013FF7UL /**< Mask for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL /**< Bit mask for ACMP_POSSEL */ +#define ACMP_INPUTSEL_POSSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_POSPIN0 (0x00000000UL << 0) /**< Shifted mode POSPIN0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_POSPIN1 (0x00000001UL << 0) /**< Shifted mode POSPIN1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_POSPIN2 (0x00000002UL << 0) /**< Shifted mode POSPIN2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_POSPIN3 (0x00000003UL << 0) /**< Shifted mode POSPIN3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_POSPIN4 (0x00000004UL << 0) /**< Shifted mode POSPIN4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_POSPIN5 (0x00000005UL << 0) /**< Shifted mode POSPIN5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_POSPIN6 (0x00000006UL << 0) /**< Shifted mode POSPIN6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_POSPIN7 (0x00000007UL << 0) /**< Shifted mode POSPIN7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_POSPIN0 0x00000000UL /**< Mode POSPIN0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_POSPIN1 0x00000001UL /**< Mode POSPIN1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_POSPIN2 0x00000002UL /**< Mode POSPIN2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_POSPIN3 0x00000003UL /**< Mode POSPIN3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_POSPIN4 0x00000004UL /**< Mode POSPIN4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_POSPIN5 0x00000005UL /**< Mode POSPIN5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_POSPIN6 0x00000006UL /**< Mode POSPIN6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_POSPIN7 0x00000007UL /**< Mode POSPIN7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL /**< Bit mask for ACMP_NEGSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEGPIN0 (0x00000000UL << 4) /**< Shifted mode NEGPIN0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEGPIN1 (0x00000001UL << 4) /**< Shifted mode NEGPIN1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEGPIN2 (0x00000002UL << 4) /**< Shifted mode NEGPIN2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEGPIN3 (0x00000003UL << 4) /**< Shifted mode NEGPIN3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEGPIN4 (0x00000004UL << 4) /**< Shifted mode NEGPIN4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEGPIN5 (0x00000005UL << 4) /**< Shifted mode NEGPIN5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEGPIN6 (0x00000006UL << 4) /**< Shifted mode NEGPIN6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEGPIN7 (0x00000007UL << 4) /**< Shifted mode NEGPIN7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DEFAULT (0x00000008UL << 4) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEG1V25 (0x00000008UL << 4) /**< Shifted mode NEG1V25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEG2V5 (0x00000009UL << 4) /**< Shifted mode NEG2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_NEGVDD (0x0000000AUL << 4) /**< Shifted mode NEGVDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CAPSENSE (0x0000000BUL << 4) /**< Shifted mode CAPSENSE for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEGPIN0 0x00000000UL /**< Mode NEGPIN0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEGPIN1 0x00000001UL /**< Mode NEGPIN1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEGPIN2 0x00000002UL /**< Mode NEGPIN2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEGPIN3 0x00000003UL /**< Mode NEGPIN3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEGPIN4 0x00000004UL /**< Mode NEGPIN4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEGPIN5 0x00000005UL /**< Mode NEGPIN5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEGPIN6 0x00000006UL /**< Mode NEGPIN6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEGPIN7 0x00000007UL /**< Mode NEGPIN7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEG1V25 0x00000008UL /**< Mode NEG1V25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEG2V5 0x00000009UL /**< Mode NEG2V5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_NEGVDD 0x0000000AUL /**< Mode NEGVDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL /**< Mode CAPSENSE for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 /**< Shift value for ACMP_VDDLEVEL */ +#define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL /**< Bit mask for ACMP_VDDLEVEL */ +#define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_LPREF (1 << 16) /**< Low Power Reference Mode */ +#define _ACMP_INPUTSEL_LPREF_SHIFT 16 /**< Shift value for ACMP_LPREF */ +#define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL /**< Bit mask for ACMP_LPREF */ +#define ACMP_INPUTSEL_LPREF_DEFAULT (0x00000001UL << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN (1 << 24) /**< Capacitive Sense Mode Internal Resistor Enable */ +#define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 /**< Shift value for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL /**< Bit mask for ACMP_CSRESEN */ +#define ACMP_INPUTSEL_CSRESEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_30KOHM (0x00000000UL << 28) /**< Shifted mode 30KOHM for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_60KOHM (0x00000001UL << 28) /**< Shifted mode 60KOHM for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_90KOHM (0x00000002UL << 28) /**< Shifted mode 90KOHM for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_120KOHM (0x00000003UL << 28) /**< Shifted mode 120KOHM for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_30KOHM 0x00000000UL /**< Mode 30KOHM for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_60KOHM 0x00000001UL /**< Mode 60KOHM for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_90KOHM 0x00000002UL /**< Mode 90KOHM for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_120KOHM 0x00000003UL /**< Mode 120KOHM for ACMP_INPUTSEL */ + +/** Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x00000003UL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT (1 << 0) /**< Analog Comparator Active */ +#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */ +#define ACMP_STATUS_ACMPACT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (1 << 1) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ + +/** Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x00000003UL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_EDGE (1 << 0) /**< Edge Trigger Interrupt Enable */ +#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define ACMP_IEN_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP (1 << 1) /**< Warm-up Interrupt Enable */ +#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define ACMP_IEN_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ + +/** Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x00000003UL /**< Mask for ACMP_IF */ +#define ACMP_IF_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag */ +#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define ACMP_IF_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP (1 << 1) /**< Warm-up Interrupt Flag */ +#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define ACMP_IF_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ + +/** Bit fields for ACMP IFS */ +#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */ +#define _ACMP_IFS_MASK 0x00000003UL /**< Mask for ACMP_IFS */ +#define ACMP_IFS_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag Set */ +#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define ACMP_IFS_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP (1 << 1) /**< Warm-up Interrupt Flag Set */ +#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define ACMP_IFS_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ + +/** Bit fields for ACMP IFC */ +#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */ +#define _ACMP_IFC_MASK 0x00000003UL /**< Mask for ACMP_IFC */ +#define ACMP_IFC_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag Clear */ +#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define ACMP_IFC_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP (1 << 1) /**< Warm-up Interrupt Flag Clear */ +#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define ACMP_IFC_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ + +/** Bit fields for ACMP ROUTE */ +#define _ACMP_ROUTE_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTE */ +#define _ACMP_ROUTE_MASK 0x00000301UL /**< Mask for ACMP_ROUTE */ +#define ACMP_ROUTE_ACMPPEN (1 << 0) /**< ACMP Output Pin Enable */ +#define _ACMP_ROUTE_ACMPPEN_SHIFT 0 /**< Shift value for ACMP_ACMPPEN */ +#define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL /**< Bit mask for ACMP_ACMPPEN */ +#define ACMP_ROUTE_ACMPPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_ROUTE */ +#define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_SHIFT 8 /**< Shift value for ACMP_LOCATION */ +#define _ACMP_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for ACMP_LOCATION */ +#define ACMP_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ACMP_ROUTE */ +#define ACMP_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for ACMP_ROUTE */ +#define ACMP_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for ACMP_ROUTE */ +#define ACMP_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */ +#define ACMP_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTE */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_MSC + * @{ + */ + +/** Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_BUSFAULT (1 << 0) /**< Bus Fault Response Enable */ +#define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */ +#define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */ +#define MSC_CTRL_BUSFAULT_GENERATE (0x00000000UL << 0) /**< Shifted mode GENERATE for MSC_CTRL */ +#define MSC_CTRL_BUSFAULT_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_BUSFAULT_IGNORE (0x00000001UL << 0) /**< Shifted mode IGNORE for MSC_CTRL */ +#define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */ +#define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */ + +/** Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x00000007UL /**< Mask for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */ +#define MSC_READCTRL_MODE_WS0 (0x00000000UL << 0) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (0x00000001UL << 0) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0SCBTP (0x00000002UL << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1SCBTP (0x00000003UL << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */ +#define MSC_READCTRL_MODE_RESERVED0 (0x00000004UL << 0) /**< Shifted mode RESERVED0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_RESERVED1 (0x00000005UL << 0) /**< Shifted mode RESERVED1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_RESERVED2 (0x00000006UL << 0) /**< Shifted mode RESERVED2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_RESERVED3 (0x00000007UL << 0) /**< Shifted mode RESERVED3 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_RESERVED0 0x00000004UL /**< Mode RESERVED0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_RESERVED1 0x00000005UL /**< Mode RESERVED1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_RESERVED2 0x00000006UL /**< Mode RESERVED2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_RESERVED3 0x00000007UL /**< Mode RESERVED3 for MSC_READCTRL */ + +/** Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (1 << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define MSC_WRITECTRL_WREN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (1 << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ + +/** Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000001FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (1 << 0) /**< Load MSC_ADDRB into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (1 << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (1 << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (1 << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (1 << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ + +/** Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ + +/** Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ + +/** Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0x0000003FUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (1 << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define MSC_STATUS_BUSY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (1 << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define MSC_STATUS_LOCKED_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (1 << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define MSC_STATUS_INVADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (1 << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define MSC_STATUS_WDATAREADY_DEFAULT (0x00000001UL << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (1 << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (1 << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ + +/** Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x00000003UL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (1 << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define MSC_IF_ERASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (1 << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define MSC_IF_WRITE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ + +/** Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x00000003UL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (1 << 0) /**< Erase Done Interrupt Set */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define MSC_IFS_ERASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (1 << 1) /**< Write Done Interrupt Set */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define MSC_IFS_WRITE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ + +/** Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x00000003UL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (1 << 0) /**< Erase Done Interrupt Clear */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define MSC_IFC_ERASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (1 << 1) /**< Write Done Interrupt Clear */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define MSC_IFC_WRITE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ + +/** Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x00000003UL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (1 << 0) /**< Erase Done Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define MSC_IEN_ERASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (1 << 1) /**< Write Done Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define MSC_IEN_WRITE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ + +/** Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define MSC_LOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (0x00001B71UL << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_EMU + * @{ + */ + +/** Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EMVREG (1 << 0) /**< Energy Mode Voltage Regulator Control */ +#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */ +#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */ +#define EMU_CTRL_EMVREG_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EMVREG_OFF (0x00000000UL << 0) /**< Shifted mode OFF for EMU_CTRL */ +#define EMU_CTRL_EMVREG_ON (0x00000001UL << 0) /**< Shifted mode ON for EMU_CTRL */ +#define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EMVREG_OFF 0x00000000UL /**< Mode OFF for EMU_CTRL */ +#define _EMU_CTRL_EMVREG_ON 0x00000001UL /**< Mode ON for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (1 << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4CTRL_SHIFT 2 /**< Shift value for EMU_EM4CTRL */ +#define _EMU_CTRL_EM4CTRL_MASK 0xCUL /**< Bit mask for EMU_EM4CTRL */ +#define EMU_CTRL_EM4CTRL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ + +/** Bit fields for EMU MEMCTRL */ +#define _EMU_MEMCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_MASK 0x00000007UL /**< Mask for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_POWERDOWN_SHIFT 0 /**< Shift value for EMU_POWERDOWN */ +#define _EMU_MEMCTRL_POWERDOWN_MASK 0x7UL /**< Bit mask for EMU_POWERDOWN */ +#define EMU_MEMCTRL_POWERDOWN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_MEMCTRL */ +#define EMU_MEMCTRL_POWERDOWN_BLK3 (0x00000004UL << 0) /**< Shifted mode BLK3 for EMU_MEMCTRL */ +#define EMU_MEMCTRL_POWERDOWN_BLK23 (0x00000006UL << 0) /**< Shifted mode BLK23 for EMU_MEMCTRL */ +#define EMU_MEMCTRL_POWERDOWN_BLK123 (0x00000007UL << 0) /**< Shifted mode BLK123 for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL /**< Mode BLK3 for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL /**< Mode BLK23 for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL /**< Mode BLK123 for EMU_MEMCTRL */ + +/** Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define EMU_LOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (0x0000ADE8UL << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ + +/** Bit fields for EMU ATESTCTRL */ +#define _EMU_ATESTCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_ATESTCTRL */ +#define _EMU_ATESTCTRL_MASK 0x07FFFF0FUL /**< Mask for EMU_ATESTCTRL */ +#define _EMU_ATESTCTRL_ATESTSEL_SHIFT 0 /**< Shift value for EMU_ATESTSEL */ +#define _EMU_ATESTCTRL_ATESTSEL_MASK 0xFUL /**< Bit mask for EMU_ATESTSEL */ +#define EMU_ATESTCTRL_ATESTSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */ +#define _EMU_ATESTCTRL_ATESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */ +#define _EMU_ATESTCTRL_ATESTBUS_SHIFT 8 /**< Shift value for EMU_ATESTBUS */ +#define _EMU_ATESTCTRL_ATESTBUS_MASK 0xFFFF00UL /**< Bit mask for EMU_ATESTBUS */ +#define EMU_ATESTCTRL_ATESTBUS_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */ +#define _EMU_ATESTCTRL_ATESTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */ +#define EMU_ATESTCTRL_DACATESTINEN (1 << 24) /**< DAC Test Input Enable */ +#define _EMU_ATESTCTRL_DACATESTINEN_SHIFT 24 /**< Shift value for EMU_DACATESTINEN */ +#define _EMU_ATESTCTRL_DACATESTINEN_MASK 0x1000000UL /**< Bit mask for EMU_DACATESTINEN */ +#define EMU_ATESTCTRL_DACATESTINEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */ +#define _EMU_ATESTCTRL_DACATESTINEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */ +#define EMU_ATESTCTRL_DAC_ATESTOUTEN (1 << 25) /**< DAC Test Output Enable */ +#define _EMU_ATESTCTRL_DAC_ATESTOUTEN_SHIFT 25 /**< Shift value for EMU_DAC_ATESTOUTEN */ +#define _EMU_ATESTCTRL_DAC_ATESTOUTEN_MASK 0x2000000UL /**< Bit mask for EMU_DAC_ATESTOUTEN */ +#define EMU_ATESTCTRL_DAC_ATESTOUTEN_DEFAULT (0x00000000UL << 25) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */ +#define _EMU_ATESTCTRL_DAC_ATESTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */ +#define EMU_ATESTCTRL_ANATESTINEN (1 << 26) /**< Analog Test Input Enable */ +#define _EMU_ATESTCTRL_ANATESTINEN_SHIFT 26 /**< Shift value for EMU_ANATESTINEN */ +#define _EMU_ATESTCTRL_ANATESTINEN_MASK 0x4000000UL /**< Bit mask for EMU_ANATESTINEN */ +#define EMU_ATESTCTRL_ANATESTINEN_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */ +#define _EMU_ATESTCTRL_ANATESTINEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */ + +/** Bit fields for EMU AUXCTRL */ +#define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_AUXCTRL */ +#define _EMU_AUXCTRL_MASK 0x000000FFUL /**< Mask for EMU_AUXCTRL */ +#define _EMU_AUXCTRL_AUX_SHIFT 0 /**< Shift value for EMU_AUX */ +#define _EMU_AUXCTRL_AUX_MASK 0xFFUL /**< Bit mask for EMU_AUX */ +#define EMU_AUXCTRL_AUX_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */ +#define EMU_AUXCTRL_AUX_HRCCLR (0x00000001UL << 0) /**< Shifted mode HRCCLR for EMU_AUXCTRL */ +#define _EMU_AUXCTRL_AUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_AUXCTRL */ +#define _EMU_AUXCTRL_AUX_HRCCLR 0x00000001UL /**< Mode HRCCLR for EMU_AUXCTRL */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_RMU + * @{ + */ + +/** Bit fields for RMU CTRL */ +#define _RMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for RMU_CTRL */ +#define _RMU_CTRL_MASK 0x00000001UL /**< Mask for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRDIS (1 << 0) /**< Lockup Reset Disable */ +#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */ +#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */ +#define RMU_CTRL_LOCKUPRDIS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ + +/** Bit fields for RMU RSTCAUSE */ +#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_MASK 0x0000007FUL /**< Mask for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST (1 << 0) /**< Power On Reset */ +#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ +#define RMU_RSTCAUSE_PORST_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODUNREGRST (1 << 1) /**< Brown Out Detector Unregulated Domain Reset */ +#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */ +#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */ +#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODREGRST (1 << 2) /**< Brown Out Detector Regulated Domain Reset */ +#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */ +#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */ +#define RMU_RSTCAUSE_BODREGRST_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST (1 << 3) /**< External Pin Reset */ +#define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */ +#define RMU_RSTCAUSE_EXTRST_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST (1 << 4) /**< Watchdog Reset */ +#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */ +#define RMU_RSTCAUSE_WDOGRST_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST (1 << 5) /**< LOCKUP Reset */ +#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */ +#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST (1 << 6) /**< System Request Reset */ +#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */ +#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ + +/** Bit fields for RMU CMD */ +#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ +#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ +#define RMU_CMD_RCCLR (1 << 0) /**< Reset Cause Clear */ +#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ +#define RMU_CMD_RCCLR_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RMU_CMD */ +#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_CMU + * @{ + */ + +/** Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00FE3EEFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */ +#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */ +#define CMU_CTRL_HFXOMODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFXOMODE_XTAL (0x00000000UL << 0) /**< Shifted mode XTAL for CMU_CTRL */ +#define CMU_CTRL_HFXOMODE_BUFEXTCLK (0x00000001UL << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ +#define CMU_CTRL_HFXOMODE_DIGEXTCLK (0x00000002UL << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ +#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ +#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ +#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ +#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */ +#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */ +#define CMU_CTRL_HFXOBOOST_50PCENT (0x00000000UL << 2) /**< Shifted mode 50PCENT for CMU_CTRL */ +#define CMU_CTRL_HFXOBOOST_70PCENT (0x00000001UL << 2) /**< Shifted mode 70PCENT for CMU_CTRL */ +#define CMU_CTRL_HFXOBOOST_80PCENT (0x00000002UL << 2) /**< Shifted mode 80PCENT for CMU_CTRL */ +#define CMU_CTRL_HFXOBOOST_DEFAULT (0x00000003UL << 2) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFXOBOOST_100PCENT (0x00000003UL << 2) /**< Shifted mode 100PCENT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */ +#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */ +#define CMU_CTRL_HFXOBUFCUR_80PCENT (0x00000000UL << 5) /**< Shifted mode 80PCENT for CMU_CTRL */ +#define CMU_CTRL_HFXOBUFCUR_DEFAULT (0x00000001UL << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFXOBUFCUR_100PCENT (0x00000001UL << 5) /**< Shifted mode 100PCENT for CMU_CTRL */ +#define CMU_CTRL_HFXOBUFCUR_120PCENT (0x00000002UL << 5) /**< Shifted mode 120PCENT for CMU_CTRL */ +#define CMU_CTRL_HFXOBUFCUR_150PCENT (0x00000003UL << 5) /**< Shifted mode 150PCENT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBUFCUR_80PCENT 0x00000000UL /**< Mode 80PCENT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBUFCUR_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBUFCUR_120PCENT 0x00000002UL /**< Mode 120PCENT for CMU_CTRL */ +#define _CMU_CTRL_HFXOBUFCUR_150PCENT 0x00000003UL /**< Mode 150PCENT for CMU_CTRL */ +#define CMU_CTRL_HFXOGLITCHDETEN (1 << 7) /**< HFXO Glitch Detector Enable */ +#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */ +#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */ +#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */ +#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */ +#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (0x00000000UL << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */ +#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (0x00000001UL << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */ +#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (0x00000002UL << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */ +#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (0x00000003UL << 9) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (0x00000003UL << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */ +#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ +#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */ +#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */ +#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */ +#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */ +#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */ +#define CMU_CTRL_LFXOMODE_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_LFXOMODE_XTAL (0x00000000UL << 11) /**< Shifted mode XTAL for CMU_CTRL */ +#define CMU_CTRL_LFXOMODE_BUFEXTCLK (0x00000001UL << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ +#define CMU_CTRL_LFXOMODE_DIGEXTCLK (0x00000002UL << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ +#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ +#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ +#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ +#define CMU_CTRL_LFXOBOOST (1 << 13) /**< LFXO Start-up Boost Current */ +#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */ +#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */ +#define CMU_CTRL_LFXOBOOST_70PCENT (0x00000000UL << 13) /**< Shifted mode 70PCENT for CMU_CTRL */ +#define CMU_CTRL_LFXOBOOST_DEFAULT (0x00000001UL << 13) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_LFXOBOOST_100PCENT (0x00000001UL << 13) /**< Shifted mode 100PCENT for CMU_CTRL */ +#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */ +#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */ +#define CMU_CTRL_LFXOBUFCUR (1 << 17) /**< LFXO Boost Buffer Current */ +#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */ +#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */ +#define CMU_CTRL_LFXOBUFCUR_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_LFXOBUFCUR_100PCENT (0x00000000UL << 17) /**< Shifted mode 100PCENT for CMU_CTRL */ +#define CMU_CTRL_LFXOBUFCUR_150PCENT (0x00000001UL << 17) /**< Shifted mode 150PCENT for CMU_CTRL */ +#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_LFXOBUFCUR_100PCENT 0x00000000UL /**< Mode 100PCENT for CMU_CTRL */ +#define _CMU_CTRL_LFXOBUFCUR_150PCENT 0x00000001UL /**< Mode 150PCENT for CMU_CTRL */ +#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */ +#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */ +#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (0x00000000UL << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */ +#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (0x00000001UL << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */ +#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (0x00000002UL << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */ +#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (0x00000003UL << 18) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (0x00000003UL << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */ +#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ +#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */ +#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */ +#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCO (0x00000000UL << 20) /**< Shifted mode HFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (0x00000001UL << 20) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (0x00000002UL << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (0x00000003UL << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (0x00000004UL << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (0x00000005UL << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (0x00000006UL << 20) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1 (1 << 23) /**< Clock Output Select 1 */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x800000UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (0x00000000UL << 23) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (0x00000000UL << 23) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (0x00000001UL << 23) /**< Shifted mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */ + +/** Bit fields for CMU HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_MASK 0x0000000FUL /**< Mask for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (0x00000000UL << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (0x00000001UL << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (0x00000002UL << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (0x00000003UL << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (0x00000004UL << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (0x00000005UL << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (0x00000006UL << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (0x00000007UL << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (0x00000008UL << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (0x00000009UL << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */ +#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */ + +/** Bit fields for CMU HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (0x00000000UL << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (0x00000001UL << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (0x00000002UL << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (0x00000003UL << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (0x00000004UL << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (0x00000005UL << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (0x00000006UL << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (0x00000007UL << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (0x00000008UL << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (0x00000009UL << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKEN (1 << 8) /**< HFPERCLK Enable */ +#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */ +#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (0x00000001UL << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ +#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ + +/** Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (0x00000080UL << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */ +#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */ +#define CMU_HFRCOCTRL_BAND_1MHZ (0x00000000UL << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_BAND_7MHZ (0x00000001UL << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_BAND_11MHZ (0x00000002UL << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_BAND_DEFAULT (0x00000003UL << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_BAND_14MHZ (0x00000003UL << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_BAND_21MHZ (0x00000004UL << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_BAND_28MHZ (0x00000005UL << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */ +#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */ +#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ + +/** Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (0x00000040UL << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ + +/** Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0x000000FFUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (0x00000080UL << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/** Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x00000007UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_REFSEL_SHIFT 0 /**< Shift value for CMU_REFSEL */ +#define _CMU_CALCTRL_REFSEL_MASK 0x7UL /**< Bit mask for CMU_REFSEL */ +#define CMU_CALCTRL_REFSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_REFSEL_HFXO (0x00000000UL << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_REFSEL_LFXO (0x00000001UL << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_REFSEL_HFRCO (0x00000002UL << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_REFSEL_LFRCO (0x00000003UL << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_REFSEL_AUXHFRCO (0x00000004UL << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_REFSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_REFSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_REFSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ + +/** Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ + +/** Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (1 << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (1 << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (1 << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (1 << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (1 << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (1 << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (1 << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (1 << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (1 << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (1 << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ + +/** Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x0000000FUL /**< Mask for CMU_CMD */ +#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */ +#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */ +#define CMU_CMD_HFCLKSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFCLKSEL_HFRCO (0x00000001UL << 0) /**< Shifted mode HFRCO for CMU_CMD */ +#define CMU_CMD_HFCLKSEL_HFXO (0x00000002UL << 0) /**< Shifted mode HFXO for CMU_CMD */ +#define CMU_CMD_HFCLKSEL_LFRCO (0x00000003UL << 0) /**< Shifted mode LFRCO for CMU_CMD */ +#define CMU_CMD_HFCLKSEL_LFXO (0x00000004UL << 0) /**< Shifted mode LFXO for CMU_CMD */ +#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */ +#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */ +#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */ +#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */ +#define CMU_CMD_CALSTART (1 << 3) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */ +#define CMU_CMD_CALSTART_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_CMD */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ + +/** Bit fields for CMU LFCLKSEL */ +#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_MASK 0x0000000FUL /**< Mask for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */ +#define CMU_LFCLKSEL_LFA_DISABLED (0x00000000UL << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ +#define CMU_LFCLKSEL_LFA_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ +#define CMU_LFCLKSEL_LFA_LFRCO (0x00000001UL << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ +#define CMU_LFCLKSEL_LFA_LFXO (0x00000002UL << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */ +#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (0x00000003UL << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */ +#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */ +#define CMU_LFCLKSEL_LFB_DISABLED (0x00000000UL << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ +#define CMU_LFCLKSEL_LFB_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ +#define CMU_LFCLKSEL_LFB_LFRCO (0x00000001UL << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ +#define CMU_LFCLKSEL_LFB_LFXO (0x00000002UL << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */ +#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (0x00000003UL << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ +#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ + +/** Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (1 << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (1 << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define CMU_STATUS_HFRCORDY_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (1 << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define CMU_STATUS_HFXOENS_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (1 << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define CMU_STATUS_HFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (1 << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (1 << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (1 << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (1 << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define CMU_STATUS_LFRCORDY_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (1 << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define CMU_STATUS_LFXOENS_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (1 << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define CMU_STATUS_LFXORDY_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOSEL (1 << 10) /**< HFRCO Selected */ +#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */ +#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */ +#define CMU_STATUS_HFRCOSEL_DEFAULT (0x00000001UL << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOSEL (1 << 11) /**< HFXO Selected */ +#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */ +#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */ +#define CMU_STATUS_HFXOSEL_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOSEL (1 << 12) /**< HFRCO Selected */ +#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */ +#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */ +#define CMU_STATUS_LFRCOSEL_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOSEL (1 << 13) /**< HFXO Selected */ +#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */ +#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */ +#define CMU_STATUS_LFXOSEL_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALBSY (1 << 14) /**< Calibration Busy */ +#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */ +#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */ +#define CMU_STATUS_CALBSY_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ + +/** Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x0000003FUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (1 << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define CMU_IF_HFRCORDY_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (1 << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define CMU_IF_HFXORDY_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (1 << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define CMU_IF_LFRCORDY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (1 << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define CMU_IF_LFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (1 << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (1 << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define CMU_IF_CALRDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ + +/** Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0x0000003FUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (1 << 0) /**< HFRCO Ready Interrupt Flag Set */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define CMU_IFS_HFRCORDY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (1 << 1) /**< HFXO Ready Interrupt Flag Set */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define CMU_IFS_HFXORDY_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (1 << 2) /**< LFRCO Ready Interrupt Flag Set */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define CMU_IFS_LFRCORDY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (1 << 3) /**< LFXO Ready Interrupt Flag Set */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define CMU_IFS_LFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (1 << 4) /**< AUXHFRCO Ready Interrupt Flag Set */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (1 << 5) /**< Calibration Ready Interrupt Flag Set */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define CMU_IFS_CALRDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ + +/** Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0x0000003FUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (1 << 0) /**< HFRCO Ready Interrupt Flag Clear */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define CMU_IFC_HFRCORDY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (1 << 1) /**< HFXO Ready Interrupt Flag Clear */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define CMU_IFC_HFXORDY_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (1 << 2) /**< LFRCO Ready Interrupt Flag Clear */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define CMU_IFC_LFRCORDY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (1 << 3) /**< LFXO Ready Interrupt Flag Clear */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define CMU_IFC_LFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (1 << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (1 << 5) /**< Calibration Ready Interrupt Flag Clear */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define CMU_IFC_CALRDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ + +/** Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x0000003FUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (1 << 0) /**< HFRCO Ready Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define CMU_IEN_HFRCORDY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (1 << 1) /**< HFXO Ready Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define CMU_IEN_HFXORDY_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (1 << 2) /**< LFRCO Ready Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define CMU_IEN_LFRCORDY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (1 << 3) /**< LFXO Ready Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define CMU_IEN_LFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (1 << 4) /**< AUXHFRCO Ready Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (1 << 5) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define CMU_IEN_CALRDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ + +/** Bit fields for CMU HFCORECLKEN0 */ +#define _CMU_HFCORECLKEN0_RESETVALUE 0x0000000FUL /**< Default value for CMU_HFCORECLKEN0 */ +#define _CMU_HFCORECLKEN0_MASK 0x0000000FUL /**< Mask for CMU_HFCORECLKEN0 */ +#define CMU_HFCORECLKEN0_AES (1 << 0) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFCORECLKEN0_AES_SHIFT 0 /**< Shift value for CMU_AES */ +#define _CMU_HFCORECLKEN0_AES_MASK 0x1UL /**< Bit mask for CMU_AES */ +#define CMU_HFCORECLKEN0_AES_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ +#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ +#define CMU_HFCORECLKEN0_DMA (1 << 1) /**< Direct Memory Access Controller Clock Enable */ +#define _CMU_HFCORECLKEN0_DMA_SHIFT 1 /**< Shift value for CMU_DMA */ +#define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL /**< Bit mask for CMU_DMA */ +#define CMU_HFCORECLKEN0_DMA_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ +#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ +#define CMU_HFCORECLKEN0_LE (1 << 2) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFCORECLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ +#define _CMU_HFCORECLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ +#define CMU_HFCORECLKEN0_LE_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ +#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ +#define CMU_HFCORECLKEN0_EBI (1 << 3) /**< External Bus Interface Clock Enable */ +#define _CMU_HFCORECLKEN0_EBI_SHIFT 3 /**< Shift value for CMU_EBI */ +#define _CMU_HFCORECLKEN0_EBI_MASK 0x8UL /**< Bit mask for CMU_EBI */ +#define CMU_HFCORECLKEN0_EBI_DEFAULT (0x00000001UL << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ +#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ + +/** Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x0000FFFFUL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x0000FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (1 << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (1 << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (1 << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_UART0 (1 << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */ +#define CMU_HFPERCLKEN0_UART0_DEFAULT (0x00000001UL << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (1 << 4) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (0x00000001UL << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (1 << 5) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (0x00000001UL << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (1 << 6) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (1 << 7) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 7 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x80UL /**< Bit mask for CMU_ACMP0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (0x00000001UL << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (1 << 8) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 8 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x100UL /**< Bit mask for CMU_ACMP1 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (0x00000001UL << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_PRS (1 << 10) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFPERCLKEN0_PRS_SHIFT 10 /**< Shift value for CMU_PRS */ +#define _CMU_HFPERCLKEN0_PRS_MASK 0x400UL /**< Bit mask for CMU_PRS */ +#define CMU_HFPERCLKEN0_PRS_DEFAULT (0x00000001UL << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_DAC0 (1 << 11) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_DAC0_SHIFT 11 /**< Shift value for CMU_DAC0 */ +#define _CMU_HFPERCLKEN0_DAC0_MASK 0x800UL /**< Bit mask for CMU_DAC0 */ +#define CMU_HFPERCLKEN0_DAC0_DEFAULT (0x00000001UL << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_GPIO (1 << 12) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFPERCLKEN0_GPIO_SHIFT 12 /**< Shift value for CMU_GPIO */ +#define _CMU_HFPERCLKEN0_GPIO_MASK 0x1000UL /**< Bit mask for CMU_GPIO */ +#define CMU_HFPERCLKEN0_GPIO_DEFAULT (0x00000001UL << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_VCMP (1 << 13) /**< Voltage Comparator Clock Enable */ +#define _CMU_HFPERCLKEN0_VCMP_SHIFT 13 /**< Shift value for CMU_VCMP */ +#define _CMU_HFPERCLKEN0_VCMP_MASK 0x2000UL /**< Bit mask for CMU_VCMP */ +#define CMU_HFPERCLKEN0_VCMP_DEFAULT (0x00000001UL << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (1 << 14) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 14 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL /**< Bit mask for CMU_ADC0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (0x00000001UL << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (1 << 15) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 15 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x8000UL /**< Bit mask for CMU_I2C0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (0x00000001UL << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ + +/** Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (1 << 0) /**< Low Frequency A Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (1 << 2) /**< Low Frequency A Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (1 << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (1 << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ + +/** Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ + +/** Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000007UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (1 << 0) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x1UL /**< Bit mask for CMU_RTC */ +#define CMU_LFACLKEN0_RTC_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (1 << 1) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 1 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x2UL /**< Bit mask for CMU_LETIMER0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (1 << 2) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 2 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x4UL /**< Bit mask for CMU_LCD */ +#define CMU_LFACLKEN0_LCD_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ + +/** Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000003UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (1 << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (1 << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ + +/** Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000003FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xFUL /**< Bit mask for CMU_RTC */ +#define CMU_LFAPRESC0_RTC_DIV1 (0x00000000UL << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (0x00000001UL << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (0x00000002UL << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (0x00000003UL << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (0x00000004UL << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (0x00000005UL << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (0x00000006UL << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (0x00000007UL << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (0x00000008UL << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (0x00000009UL << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (0x0000000AUL << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (0x0000000BUL << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (0x0000000CUL << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (0x0000000DUL << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (0x0000000EUL << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (0x0000000FUL << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 4 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF0UL /**< Bit mask for CMU_LETIMER0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (0x00000000UL << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (0x00000001UL << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (0x00000002UL << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (0x00000003UL << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (0x00000004UL << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (0x00000005UL << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (0x00000006UL << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (0x00000007UL << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (0x00000008UL << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (0x00000009UL << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (0x0000000AUL << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (0x0000000BUL << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (0x0000000CUL << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (0x0000000DUL << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (0x0000000EUL << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (0x0000000FUL << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 8 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x300UL /**< Bit mask for CMU_LCD */ +#define CMU_LFAPRESC0_LCD_DIV16 (0x00000000UL << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (0x00000001UL << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (0x00000002UL << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (0x00000003UL << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */ + +/** Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (0x00000000UL << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (0x00000001UL << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (0x00000002UL << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (0x00000003UL << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (0x00000000UL << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (0x00000001UL << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (0x00000002UL << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (0x00000003UL << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ + +/** Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000015UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (1 << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (1 << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (0x00000000UL << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (0x00000001UL << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (1 << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (1 << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (0x00000000UL << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (0x00000001UL << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (1 << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (0x00000001UL << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (1 << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (0x00000000UL << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (0x00000001UL << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ + +/** Bit fields for CMU LCDCTRL */ +#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */ +#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */ +#define CMU_LCDCTRL_FDIV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBOOSTEN (1 << 3) /**< Voltage Boost Enable */ +#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */ +#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */ +#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_SHIFT 4 /**< Shift value for CMU_VBFREQ */ +#define _CMU_LCDCTRL_VBFREQ_MASK 0x70UL /**< Bit mask for CMU_VBFREQ */ +#define CMU_LCDCTRL_VBFREQ_32KHZ (0x00000000UL << 4) /**< Shifted mode 32KHZ for CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBFREQ_16KHZ (0x00000001UL << 4) /**< Shifted mode 16KHZ for CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBFREQ_DEFAULT (0x00000002UL << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBFREQ_8KHZ (0x00000002UL << 4) /**< Shifted mode 8KHZ for CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBFREQ_4KHZ (0x00000003UL << 4) /**< Shifted mode 4KHZ for CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBFREQ_2KHZ (0x00000004UL << 4) /**< Shifted mode 2KHZ for CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBFREQ_1KHZ (0x00000005UL << 4) /**< Shifted mode 1KHZ for CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBFREQ_512HZ (0x00000006UL << 4) /**< Shifted mode 512HZ for CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBFREQ_256HZ (0x00000007UL << 4) /**< Shifted mode 256HZ for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_32KHZ 0x00000000UL /**< Mode 32KHZ for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_16KHZ 0x00000001UL /**< Mode 16KHZ for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_8KHZ 0x00000002UL /**< Mode 8KHZ for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_4KHZ 0x00000003UL /**< Mode 4KHZ for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_2KHZ 0x00000004UL /**< Mode 2KHZ for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_1KHZ 0x00000005UL /**< Mode 1KHZ for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_512HZ 0x00000006UL /**< Mode 512HZ for CMU_LCDCTRL */ +#define _CMU_LCDCTRL_VBFREQ_256HZ 0x00000007UL /**< Mode 256HZ for CMU_LCDCTRL */ + +/** Bit fields for CMU ROUTE */ +#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */ +#define _CMU_ROUTE_MASK 0x00000007UL /**< Mask for CMU_ROUTE */ +#define CMU_ROUTE_CLKOUT0PEN (1 << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */ +#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ +#define CMU_ROUTE_CLKOUT1PEN (1 << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */ +#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ +#define CMU_ROUTE_LOCATION (1 << 2) /**< I/O Location */ +#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */ +#define _CMU_ROUTE_LOCATION_MASK 0x4UL /**< Bit mask for CMU_LOCATION */ +#define CMU_ROUTE_LOCATION_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */ +#define CMU_ROUTE_LOCATION_LOC0 (0x00000000UL << 2) /**< Shifted mode LOC0 for CMU_ROUTE */ +#define CMU_ROUTE_LOCATION_LOC1 (0x00000001UL << 2) /**< Shifted mode LOC1 for CMU_ROUTE */ +#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ +#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */ +#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */ + +/** Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define CMU_LOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (0x0000580EUL << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_AES + * @{ + */ + +/** Bit fields for AES CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x00000037UL /**< Mask for AES_CTRL */ +#define AES_CTRL_DECRYPT (1 << 0) /**< Decryption/Encryption Mode */ +#define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */ +#define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */ +#define AES_CTRL_DECRYPT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_AES256 (1 << 1) /**< AES-256 Mode */ +#define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */ +#define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */ +#define AES_CTRL_AES256_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_KEYBUFEN (1 << 2) /**< Key Buffer Enable */ +#define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */ +#define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */ +#define AES_CTRL_KEYBUFEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_DATASTART (1 << 4) /**< AES_DATA Write Start */ +#define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */ +#define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */ +#define AES_CTRL_DATASTART_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for AES_CTRL */ +#define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_XORSTART (1 << 5) /**< AES_XORDATA Write Start */ +#define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */ +#define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */ +#define AES_CTRL_XORSTART_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for AES_CTRL */ +#define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ + +/** Bit fields for AES CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_START (1 << 0) /**< Encryption/Decryption Start */ +#define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */ +#define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */ +#define AES_CMD_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STOP (1 << 1) /**< Encryption/Decryption Stop */ +#define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */ +#define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */ +#define AES_CMD_STOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for AES_CMD */ +#define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ + +/** Bit fields for AES STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */ +#define AES_STATUS_RUNNING (1 << 0) /**< AES Running */ +#define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */ +#define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */ +#define AES_STATUS_RUNNING_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ + +/** Bit fields for AES IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */ +#define AES_IEN_DONE (1 << 0) /**< Encryption/Decryption Done Interrupt Enable */ +#define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */ +#define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ +#define AES_IEN_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ + +/** Bit fields for AES IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */ +#define AES_IF_DONE (1 << 0) /**< Encryption/Decryption Done Interrupt Flag */ +#define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */ +#define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ +#define AES_IF_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ + +/** Bit fields for AES IFS */ +#define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */ +#define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */ +#define AES_IFS_DONE (1 << 0) /**< Encryption/Decryption Done Interrupt Flag Set */ +#define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */ +#define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ +#define AES_IFS_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_IFS */ +#define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */ + +/** Bit fields for AES IFC */ +#define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */ +#define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */ +#define AES_IFC_DONE (1 << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */ +#define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */ +#define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ +#define AES_IFC_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_IFC */ +#define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */ + +/** Bit fields for AES DATA */ +#define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */ +#define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */ +#define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */ +#define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */ +#define AES_DATA_DATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_DATA */ +#define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */ + +/** Bit fields for AES XORDATA */ +#define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */ +#define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */ +#define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */ +#define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */ +#define AES_XORDATA_XORDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_XORDATA */ +#define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */ + +/** Bit fields for AES KEYLA */ +#define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */ +#define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */ +#define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */ +#define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */ +#define AES_KEYLA_KEYLA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYLA */ +#define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */ + +/** Bit fields for AES KEYLB */ +#define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */ +#define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */ +#define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */ +#define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */ +#define AES_KEYLB_KEYLB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYLB */ +#define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */ + +/** Bit fields for AES KEYLC */ +#define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */ +#define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */ +#define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */ +#define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */ +#define AES_KEYLC_KEYLC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYLC */ +#define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */ + +/** Bit fields for AES KEYLD */ +#define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */ +#define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */ +#define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */ +#define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */ +#define AES_KEYLD_KEYLD_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYLD */ +#define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */ + +/** Bit fields for AES KEYHA */ +#define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */ +#define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */ +#define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */ +#define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */ +#define AES_KEYHA_KEYHA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYHA */ +#define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */ + +/** Bit fields for AES KEYHB */ +#define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */ +#define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */ +#define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */ +#define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */ +#define AES_KEYHB_KEYHB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYHB */ +#define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */ + +/** Bit fields for AES KEYHC */ +#define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */ +#define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */ +#define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */ +#define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */ +#define AES_KEYHC_KEYHC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYHC */ +#define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */ + +/** Bit fields for AES KEYHD */ +#define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */ +#define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */ +#define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */ +#define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */ +#define AES_KEYHD_KEYHD_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYHD */ +#define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_EBI + * @{ + */ + +/** Bit fields for EBI CTRL */ +#define _EBI_CTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_CTRL */ +#define _EBI_CTRL_MASK 0x00030F07UL /**< Mask for EBI_CTRL */ +#define _EBI_CTRL_MODE_SHIFT 0 /**< Shift value for EBI_MODE */ +#define _EBI_CTRL_MODE_MASK 0x7UL /**< Bit mask for EBI_MODE */ +#define EBI_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_MODE_D8A8 (0x00000000UL << 0) /**< Shifted mode D8A8 for EBI_CTRL */ +#define EBI_CTRL_MODE_D16A16ALE (0x00000001UL << 0) /**< Shifted mode D16A16ALE for EBI_CTRL */ +#define EBI_CTRL_MODE_D8A24ALE (0x00000002UL << 0) /**< Shifted mode D8A24ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_MODE_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ +#define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ +#define EBI_CTRL_BANK0EN (1 << 8) /**< Bank 0 Enable */ +#define _EBI_CTRL_BANK0EN_SHIFT 8 /**< Shift value for EBI_BANK0EN */ +#define _EBI_CTRL_BANK0EN_MASK 0x100UL /**< Bit mask for EBI_BANK0EN */ +#define EBI_CTRL_BANK0EN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK1EN (1 << 9) /**< Bank 1 Enable */ +#define _EBI_CTRL_BANK1EN_SHIFT 9 /**< Shift value for EBI_BANK1EN */ +#define _EBI_CTRL_BANK1EN_MASK 0x200UL /**< Bit mask for EBI_BANK1EN */ +#define EBI_CTRL_BANK1EN_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK2EN (1 << 10) /**< Bank 2 Enable */ +#define _EBI_CTRL_BANK2EN_SHIFT 10 /**< Shift value for EBI_BANK2EN */ +#define _EBI_CTRL_BANK2EN_MASK 0x400UL /**< Bit mask for EBI_BANK2EN */ +#define EBI_CTRL_BANK2EN_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK3EN (1 << 11) /**< Bank 3 Enable */ +#define _EBI_CTRL_BANK3EN_SHIFT 11 /**< Shift value for EBI_BANK3EN */ +#define _EBI_CTRL_BANK3EN_MASK 0x800UL /**< Bit mask for EBI_BANK3EN */ +#define EBI_CTRL_BANK3EN_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYEN (1 << 16) /**< ARDY Enable */ +#define _EBI_CTRL_ARDYEN_SHIFT 16 /**< Shift value for EBI_ARDYEN */ +#define _EBI_CTRL_ARDYEN_MASK 0x10000UL /**< Bit mask for EBI_ARDYEN */ +#define EBI_CTRL_ARDYEN_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYTODIS (1 << 17) /**< ARDY Timeout Disable */ +#define _EBI_CTRL_ARDYTODIS_SHIFT 17 /**< Shift value for EBI_ARDYTODIS */ +#define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL /**< Bit mask for EBI_ARDYTODIS */ +#define EBI_CTRL_ARDYTODIS_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ + +/** Bit fields for EBI ADDRTIMING */ +#define _EBI_ADDRTIMING_RESETVALUE 0x00000100UL /**< Default value for EBI_ADDRTIMING */ +#define _EBI_ADDRTIMING_MASK 0x00000303UL /**< Mask for EBI_ADDRTIMING */ +#define _EBI_ADDRTIMING_ADDRSET_SHIFT 0 /**< Shift value for EBI_ADDRSET */ +#define _EBI_ADDRTIMING_ADDRSET_MASK 0x3UL /**< Bit mask for EBI_ADDRSET */ +#define EBI_ADDRTIMING_ADDRSET_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ +#define _EBI_ADDRTIMING_ADDRSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING */ +#define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ +#define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */ +#define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (0x00000001UL << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ +#define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000001UL /**< Mode DEFAULT for EBI_ADDRTIMING */ + +/** Bit fields for EBI RDTIMING */ +#define _EBI_RDTIMING_RESETVALUE 0x00000000UL /**< Default value for EBI_RDTIMING */ +#define _EBI_RDTIMING_MASK 0x00030F03UL /**< Mask for EBI_RDTIMING */ +#define _EBI_RDTIMING_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ +#define _EBI_RDTIMING_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */ +#define EBI_RDTIMING_RDSETUP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING */ +#define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ +#define _EBI_RDTIMING_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ +#define _EBI_RDTIMING_RDSTRB_MASK 0xF00UL /**< Bit mask for EBI_RDSTRB */ +#define EBI_RDTIMING_RDSTRB_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING */ +#define _EBI_RDTIMING_RDSTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ +#define _EBI_RDTIMING_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ +#define _EBI_RDTIMING_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */ +#define EBI_RDTIMING_RDHOLD_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING */ +#define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ + +/** Bit fields for EBI WRTIMING */ +#define _EBI_WRTIMING_RESETVALUE 0x00010000UL /**< Default value for EBI_WRTIMING */ +#define _EBI_WRTIMING_MASK 0x00030F03UL /**< Mask for EBI_WRTIMING */ +#define _EBI_WRTIMING_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ +#define _EBI_WRTIMING_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */ +#define EBI_WRTIMING_WRSETUP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING */ +#define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */ +#define _EBI_WRTIMING_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ +#define _EBI_WRTIMING_WRSTRB_MASK 0xF00UL /**< Bit mask for EBI_WRSTRB */ +#define EBI_WRTIMING_WRSTRB_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING */ +#define _EBI_WRTIMING_WRSTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */ +#define _EBI_WRTIMING_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ +#define _EBI_WRTIMING_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */ +#define EBI_WRTIMING_WRHOLD_DEFAULT (0x00000001UL << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING */ +#define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000001UL /**< Mode DEFAULT for EBI_WRTIMING */ + +/** Bit fields for EBI POLARITY */ +#define _EBI_POLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY */ +#define _EBI_POLARITY_MASK 0x0000001FUL /**< Mask for EBI_POLARITY */ +#define EBI_POLARITY_CSPOL (1 << 0) /**< Chip Select Polarity */ +#define _EBI_POLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ +#define _EBI_POLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ +#define EBI_POLARITY_CSPOL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_CSPOL_ACTIVELOW (0x00000000UL << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_CSPOL_ACTIVEHIGH (0x00000001UL << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_REPOL (1 << 1) /**< Read Enable Polarity */ +#define _EBI_POLARITY_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ +#define _EBI_POLARITY_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ +#define EBI_POLARITY_REPOL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_REPOL_ACTIVELOW (0x00000000UL << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_REPOL_ACTIVEHIGH (0x00000001UL << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_WEPOL (1 << 2) /**< Write Enable Polarity */ +#define _EBI_POLARITY_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ +#define _EBI_POLARITY_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ +#define EBI_POLARITY_WEPOL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_WEPOL_ACTIVELOW (0x00000000UL << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_WEPOL_ACTIVEHIGH (0x00000001UL << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_ALEPOL (1 << 3) /**< Address Latch Polarity */ +#define _EBI_POLARITY_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ +#define _EBI_POLARITY_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ +#define EBI_POLARITY_ALEPOL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_ALEPOL_ACTIVELOW (0x00000000UL << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_ALEPOL_ACTIVEHIGH (0x00000001UL << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_ARDYPOL (1 << 4) /**< ARDY Polarity */ +#define _EBI_POLARITY_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ +#define _EBI_POLARITY_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ +#define EBI_POLARITY_ARDYPOL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_ARDYPOL_ACTIVELOW (0x00000000UL << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (0x00000001UL << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ + +/** Bit fields for EBI ROUTE */ +#define _EBI_ROUTE_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTE */ +#define _EBI_ROUTE_MASK 0x0000007FUL /**< Mask for EBI_ROUTE */ +#define EBI_ROUTE_EBIPEN (1 << 0) /**< EBI Pin Enable */ +#define _EBI_ROUTE_EBIPEN_SHIFT 0 /**< Shift value for EBI_EBIPEN */ +#define _EBI_ROUTE_EBIPEN_MASK 0x1UL /**< Bit mask for EBI_EBIPEN */ +#define EBI_ROUTE_EBIPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_ROUTE */ +#define _EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ +#define EBI_ROUTE_CS0PEN (1 << 1) /**< EBI_CS0 Pin Enable */ +#define _EBI_ROUTE_CS0PEN_SHIFT 1 /**< Shift value for EBI_CS0PEN */ +#define _EBI_ROUTE_CS0PEN_MASK 0x2UL /**< Bit mask for EBI_CS0PEN */ +#define EBI_ROUTE_CS0PEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for EBI_ROUTE */ +#define _EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ +#define EBI_ROUTE_CS1PEN (1 << 2) /**< EBI_CS1 Pin Enable */ +#define _EBI_ROUTE_CS1PEN_SHIFT 2 /**< Shift value for EBI_CS1PEN */ +#define _EBI_ROUTE_CS1PEN_MASK 0x4UL /**< Bit mask for EBI_CS1PEN */ +#define EBI_ROUTE_CS1PEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for EBI_ROUTE */ +#define _EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ +#define EBI_ROUTE_CS2PEN (1 << 3) /**< EBI_CS2 Pin Enable */ +#define _EBI_ROUTE_CS2PEN_SHIFT 3 /**< Shift value for EBI_CS2PEN */ +#define _EBI_ROUTE_CS2PEN_MASK 0x8UL /**< Bit mask for EBI_CS2PEN */ +#define EBI_ROUTE_CS2PEN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for EBI_ROUTE */ +#define _EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ +#define EBI_ROUTE_CS3PEN (1 << 4) /**< EBI_CS3 Pin Enable */ +#define _EBI_ROUTE_CS3PEN_SHIFT 4 /**< Shift value for EBI_CS3PEN */ +#define _EBI_ROUTE_CS3PEN_MASK 0x10UL /**< Bit mask for EBI_CS3PEN */ +#define EBI_ROUTE_CS3PEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for EBI_ROUTE */ +#define _EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ +#define EBI_ROUTE_ALEPEN (1 << 5) /**< EBI_ALE Pin Enable */ +#define _EBI_ROUTE_ALEPEN_SHIFT 5 /**< Shift value for EBI_ALEPEN */ +#define _EBI_ROUTE_ALEPEN_MASK 0x20UL /**< Bit mask for EBI_ALEPEN */ +#define EBI_ROUTE_ALEPEN_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for EBI_ROUTE */ +#define _EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ +#define EBI_ROUTE_ARDYPEN (1 << 6) /**< EBI_ARDY Pin Enable */ +#define _EBI_ROUTE_ARDYPEN_SHIFT 6 /**< Shift value for EBI_ARDYPEN */ +#define _EBI_ROUTE_ARDYPEN_MASK 0x40UL /**< Bit mask for EBI_ARDYPEN */ +#define EBI_ROUTE_ARDYPEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for EBI_ROUTE */ +#define _EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_GPIO + * @{ + */ + +/** Bit fields for GPIO P_CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x00000003UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVEMODE_SHIFT 0 /**< Shift value for GPIO_DRIVEMODE */ +#define _GPIO_P_CTRL_DRIVEMODE_MASK 0x3UL /**< Bit mask for GPIO_DRIVEMODE */ +#define GPIO_P_CTRL_DRIVEMODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVEMODE_STANDARD (0x00000000UL << 0) /**< Shifted mode STANDARD for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVEMODE_LOWEST (0x00000001UL << 0) /**< Shifted mode LOWEST for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVEMODE_HIGH (0x00000002UL << 0) /**< Shifted mode HIGH for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVEMODE_LOW (0x00000003UL << 0) /**< Shifted mode LOW for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVEMODE_STANDARD 0x00000000UL /**< Mode STANDARD for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVEMODE_LOWEST 0x00000001UL /**< Mode LOWEST for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVEMODE_HIGH 0x00000002UL /**< Mode HIGH for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVEMODE_LOW 0x00000003UL /**< Mode LOW for GPIO_P_CTRL */ + +/** Bit fields for GPIO P_MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define GPIO_P_MODEL_MODE0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (0x00000000UL << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (0x00000001UL << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (0x00000002UL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (0x00000003UL << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULL (0x00000004UL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLDRIVE (0x00000005UL << 0) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (0x00000006UL << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (0x00000007UL << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDAND (0x00000008UL << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (0x00000009UL << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (0x0000000AUL << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (0x0000000BUL << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDDRIVE (0x0000000CUL << 0) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER (0x0000000DUL << 0) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP (0x0000000EUL << 0) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 0) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define GPIO_P_MODEL_MODE1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (0x00000000UL << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (0x00000001UL << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (0x00000002UL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (0x00000003UL << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULL (0x00000004UL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLDRIVE (0x00000005UL << 4) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (0x00000006UL << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (0x00000007UL << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDAND (0x00000008UL << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (0x00000009UL << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (0x0000000AUL << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (0x0000000BUL << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDDRIVE (0x0000000CUL << 4) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER (0x0000000DUL << 4) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP (0x0000000EUL << 4) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 4) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define GPIO_P_MODEL_MODE2_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (0x00000000UL << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (0x00000001UL << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (0x00000002UL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (0x00000003UL << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULL (0x00000004UL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLDRIVE (0x00000005UL << 8) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (0x00000006UL << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (0x00000007UL << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDAND (0x00000008UL << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (0x00000009UL << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (0x0000000AUL << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (0x0000000BUL << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDDRIVE (0x0000000CUL << 8) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER (0x0000000DUL << 8) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP (0x0000000EUL << 8) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 8) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define GPIO_P_MODEL_MODE3_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (0x00000000UL << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (0x00000001UL << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (0x00000002UL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (0x00000003UL << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULL (0x00000004UL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLDRIVE (0x00000005UL << 12) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (0x00000006UL << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (0x00000007UL << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDAND (0x00000008UL << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (0x00000009UL << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (0x0000000AUL << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (0x0000000BUL << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDDRIVE (0x0000000CUL << 12) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER (0x0000000DUL << 12) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP (0x0000000EUL << 12) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 12) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define GPIO_P_MODEL_MODE4_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (0x00000000UL << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (0x00000001UL << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (0x00000002UL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (0x00000003UL << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULL (0x00000004UL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLDRIVE (0x00000005UL << 16) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (0x00000006UL << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (0x00000007UL << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDAND (0x00000008UL << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (0x00000009UL << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (0x0000000AUL << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (0x0000000BUL << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDDRIVE (0x0000000CUL << 16) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER (0x0000000DUL << 16) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP (0x0000000EUL << 16) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 16) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define GPIO_P_MODEL_MODE5_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (0x00000000UL << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (0x00000001UL << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (0x00000002UL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (0x00000003UL << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULL (0x00000004UL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLDRIVE (0x00000005UL << 20) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (0x00000006UL << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (0x00000007UL << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDAND (0x00000008UL << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (0x00000009UL << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (0x0000000AUL << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (0x0000000BUL << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDDRIVE (0x0000000CUL << 20) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER (0x0000000DUL << 20) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP (0x0000000EUL << 20) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 20) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define GPIO_P_MODEL_MODE6_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (0x00000000UL << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (0x00000001UL << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (0x00000002UL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (0x00000003UL << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULL (0x00000004UL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLDRIVE (0x00000005UL << 24) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (0x00000006UL << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (0x00000007UL << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDAND (0x00000008UL << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (0x00000009UL << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (0x0000000AUL << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (0x0000000BUL << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDDRIVE (0x0000000CUL << 24) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER (0x0000000DUL << 24) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP (0x0000000EUL << 24) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 24) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define GPIO_P_MODEL_MODE7_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (0x00000000UL << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (0x00000001UL << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (0x00000002UL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (0x00000003UL << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULL (0x00000004UL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLDRIVE (0x00000005UL << 28) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (0x00000006UL << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (0x00000007UL << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDAND (0x00000008UL << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (0x00000009UL << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (0x0000000AUL << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (0x0000000BUL << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDDRIVE (0x0000000CUL << 28) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER (0x0000000DUL << 28) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP (0x0000000EUL << 28) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 28) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ + +/** Bit fields for GPIO P_MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */ +#define GPIO_P_MODEH_MODE8_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DISABLED (0x00000000UL << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUT (0x00000001UL << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULL (0x00000002UL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (0x00000003UL << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULL (0x00000004UL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULLDRIVE (0x00000005UL << 0) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDOR (0x00000006UL << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (0x00000007UL << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDAND (0x00000008UL << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (0x00000009UL << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (0x0000000AUL << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (0x0000000BUL << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDDRIVE (0x0000000CUL << 0) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER (0x0000000DUL << 0) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP (0x0000000EUL << 0) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 0) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */ +#define GPIO_P_MODEH_MODE9_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DISABLED (0x00000000UL << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUT (0x00000001UL << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULL (0x00000002UL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (0x00000003UL << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULL (0x00000004UL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULLDRIVE (0x00000005UL << 4) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDOR (0x00000006UL << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (0x00000007UL << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDAND (0x00000008UL << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (0x00000009UL << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (0x0000000AUL << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (0x0000000BUL << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDDRIVE (0x0000000CUL << 4) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER (0x0000000DUL << 4) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP (0x0000000EUL << 4) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 4) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */ +#define GPIO_P_MODEH_MODE10_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DISABLED (0x00000000UL << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUT (0x00000001UL << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULL (0x00000002UL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (0x00000003UL << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULL (0x00000004UL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULLDRIVE (0x00000005UL << 8) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDOR (0x00000006UL << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (0x00000007UL << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDAND (0x00000008UL << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (0x00000009UL << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (0x0000000AUL << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (0x0000000BUL << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDDRIVE (0x0000000CUL << 8) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER (0x0000000DUL << 8) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP (0x0000000EUL << 8) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 8) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */ +#define GPIO_P_MODEH_MODE11_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DISABLED (0x00000000UL << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUT (0x00000001UL << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULL (0x00000002UL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (0x00000003UL << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULL (0x00000004UL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULLDRIVE (0x00000005UL << 12) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDOR (0x00000006UL << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (0x00000007UL << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDAND (0x00000008UL << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (0x00000009UL << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (0x0000000AUL << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (0x0000000BUL << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDDRIVE (0x0000000CUL << 12) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER (0x0000000DUL << 12) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP (0x0000000EUL << 12) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 12) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */ +#define GPIO_P_MODEH_MODE12_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DISABLED (0x00000000UL << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUT (0x00000001UL << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULL (0x00000002UL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (0x00000003UL << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULL (0x00000004UL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULLDRIVE (0x00000005UL << 16) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDOR (0x00000006UL << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (0x00000007UL << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDAND (0x00000008UL << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (0x00000009UL << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (0x0000000AUL << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (0x0000000BUL << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDDRIVE (0x0000000CUL << 16) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER (0x0000000DUL << 16) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP (0x0000000EUL << 16) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 16) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */ +#define GPIO_P_MODEH_MODE13_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DISABLED (0x00000000UL << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUT (0x00000001UL << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULL (0x00000002UL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (0x00000003UL << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULL (0x00000004UL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULLDRIVE (0x00000005UL << 20) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDOR (0x00000006UL << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (0x00000007UL << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDAND (0x00000008UL << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (0x00000009UL << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (0x0000000AUL << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (0x0000000BUL << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDDRIVE (0x0000000CUL << 20) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER (0x0000000DUL << 20) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP (0x0000000EUL << 20) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 20) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */ +#define GPIO_P_MODEH_MODE14_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DISABLED (0x00000000UL << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUT (0x00000001UL << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULL (0x00000002UL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (0x00000003UL << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULL (0x00000004UL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULLDRIVE (0x00000005UL << 24) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDOR (0x00000006UL << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (0x00000007UL << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDAND (0x00000008UL << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (0x00000009UL << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (0x0000000AUL << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (0x0000000BUL << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDDRIVE (0x0000000CUL << 24) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER (0x0000000DUL << 24) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP (0x0000000EUL << 24) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 24) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */ +#define GPIO_P_MODEH_MODE15_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DISABLED (0x00000000UL << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUT (0x00000001UL << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULL (0x00000002UL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (0x00000003UL << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULL (0x00000004UL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULLDRIVE (0x00000005UL << 28) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDOR (0x00000006UL << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (0x00000007UL << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDAND (0x00000008UL << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (0x00000009UL << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (0x0000000AUL << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (0x0000000BUL << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDDRIVE (0x0000000CUL << 28) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER (0x0000000DUL << 28) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP (0x0000000EUL << 28) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 28) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ + +/** Bit fields for GPIO P_DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ + +/** Bit fields for GPIO P_DOUTSET */ +#define _GPIO_P_DOUTSET_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTSET */ +#define _GPIO_P_DOUTSET_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTSET */ +#define _GPIO_P_DOUTSET_DOUTSET_SHIFT 0 /**< Shift value for GPIO_DOUTSET */ +#define _GPIO_P_DOUTSET_DOUTSET_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTSET */ +#define GPIO_P_DOUTSET_DOUTSET_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTSET */ +#define _GPIO_P_DOUTSET_DOUTSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTSET */ + +/** Bit fields for GPIO P_DOUTCLR */ +#define _GPIO_P_DOUTCLR_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTCLR */ +#define _GPIO_P_DOUTCLR_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTCLR */ +#define _GPIO_P_DOUTCLR_DOUTCLR_SHIFT 0 /**< Shift value for GPIO_DOUTCLR */ +#define _GPIO_P_DOUTCLR_DOUTCLR_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTCLR */ +#define GPIO_P_DOUTCLR_DOUTCLR_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTCLR */ +#define _GPIO_P_DOUTCLR_DOUTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTCLR */ + +/** Bit fields for GPIO P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */ +#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */ + +/** Bit fields for GPIO P_DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ + +/** Bit fields for GPIO P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */ +#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (0x0000FFFFUL << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */ + +/** Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x77777777UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x7UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (0x00000000UL << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (0x00000001UL << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (0x00000002UL << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (0x00000003UL << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTE (0x00000004UL << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (0x00000005UL << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x70UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (0x00000000UL << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (0x00000001UL << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (0x00000002UL << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (0x00000003UL << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTE (0x00000004UL << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (0x00000005UL << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x700UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (0x00000000UL << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (0x00000001UL << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (0x00000002UL << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (0x00000003UL << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTE (0x00000004UL << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (0x00000005UL << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x7000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (0x00000000UL << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (0x00000001UL << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (0x00000002UL << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (0x00000003UL << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTE (0x00000004UL << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (0x00000005UL << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x70000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (0x00000000UL << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (0x00000001UL << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (0x00000002UL << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (0x00000003UL << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTE (0x00000004UL << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (0x00000005UL << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x700000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (0x00000000UL << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (0x00000001UL << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (0x00000002UL << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (0x00000003UL << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTE (0x00000004UL << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (0x00000005UL << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x7000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (0x00000000UL << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (0x00000001UL << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (0x00000002UL << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (0x00000003UL << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTE (0x00000004UL << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (0x00000005UL << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x70000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (0x00000000UL << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (0x00000001UL << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (0x00000002UL << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (0x00000003UL << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTE (0x00000004UL << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (0x00000005UL << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ + +/** Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x77777777UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0x7UL /**< Bit mask for GPIO_EXTIPSEL8 */ +#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (0x00000000UL << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (0x00000001UL << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (0x00000002UL << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (0x00000003UL << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTE (0x00000004UL << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (0x00000005UL << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0x70UL /**< Bit mask for GPIO_EXTIPSEL9 */ +#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (0x00000000UL << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (0x00000001UL << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (0x00000002UL << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (0x00000003UL << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTE (0x00000004UL << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (0x00000005UL << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0x700UL /**< Bit mask for GPIO_EXTIPSEL10 */ +#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (0x00000000UL << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (0x00000001UL << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (0x00000002UL << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (0x00000003UL << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTE (0x00000004UL << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (0x00000005UL << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0x7000UL /**< Bit mask for GPIO_EXTIPSEL11 */ +#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (0x00000000UL << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (0x00000001UL << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (0x00000002UL << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (0x00000003UL << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTE (0x00000004UL << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (0x00000005UL << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0x70000UL /**< Bit mask for GPIO_EXTIPSEL12 */ +#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (0x00000000UL << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (0x00000001UL << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (0x00000002UL << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (0x00000003UL << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTE (0x00000004UL << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (0x00000005UL << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0x700000UL /**< Bit mask for GPIO_EXTIPSEL13 */ +#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (0x00000000UL << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (0x00000001UL << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (0x00000002UL << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (0x00000003UL << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTE (0x00000004UL << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (0x00000005UL << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0x7000000UL /**< Bit mask for GPIO_EXTIPSEL14 */ +#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (0x00000000UL << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (0x00000001UL << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (0x00000002UL << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (0x00000003UL << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTE (0x00000004UL << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (0x00000005UL << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL16_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL16 */ +#define _GPIO_EXTIPSELH_EXTIPSEL16_MASK 0x70000000UL /**< Bit mask for GPIO_EXTIPSEL16 */ +#define GPIO_EXTIPSELH_EXTIPSEL16_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL16_PORTA (0x00000000UL << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL16_PORTB (0x00000001UL << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL16_PORTC (0x00000002UL << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL16_PORTD (0x00000003UL << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL16_PORTE (0x00000004UL << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL16_PORTF (0x00000005UL << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL16_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ + +/** Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ + +/** Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ + +/** Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0000FFFFUL /**< Mask for GPIO_IEN */ +#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define GPIO_IEN_EXT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ + +/** Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0000FFFFUL /**< Mask for GPIO_IF */ +#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define GPIO_IF_EXT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ + +/** Bit fields for GPIO IFS */ +#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */ +#define _GPIO_IFS_MASK 0x0000FFFFUL /**< Mask for GPIO_IFS */ +#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define GPIO_IFS_EXT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_IFS */ +#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ + +/** Bit fields for GPIO IFC */ +#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */ +#define _GPIO_IFC_MASK 0x0000FFFFUL /**< Mask for GPIO_IFC */ +#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define GPIO_IFC_EXT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_IFC */ +#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ + +/** Bit fields for GPIO ROUTE */ +#define _GPIO_ROUTE_RESETVALUE 0x00000003UL /**< Default value for GPIO_ROUTE */ +#define _GPIO_ROUTE_MASK 0x00000307UL /**< Mask for GPIO_ROUTE */ +#define GPIO_ROUTE_SWCLKPEN (1 << 0) /**< Serial Wire Clock Pin Enable */ +#define _GPIO_ROUTE_SWCLKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKPEN */ +#define _GPIO_ROUTE_SWCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKPEN */ +#define GPIO_ROUTE_SWCLKPEN_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for GPIO_ROUTE */ +#define _GPIO_ROUTE_SWCLKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTE */ +#define GPIO_ROUTE_SWDIOPEN (1 << 1) /**< Serial Wire Data Pin Enable */ +#define _GPIO_ROUTE_SWDIOPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOPEN */ +#define _GPIO_ROUTE_SWDIOPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOPEN */ +#define GPIO_ROUTE_SWDIOPEN_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for GPIO_ROUTE */ +#define _GPIO_ROUTE_SWDIOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTE */ +#define GPIO_ROUTE_SWVPEN (1 << 2) /**< Serial Wire Viewer Pin Enable */ +#define _GPIO_ROUTE_SWVPEN_SHIFT 2 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_ROUTE_SWVPEN_MASK 0x4UL /**< Bit mask for GPIO_SWVPEN */ +#define GPIO_ROUTE_SWVPEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for GPIO_ROUTE */ +#define _GPIO_ROUTE_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ +#define _GPIO_ROUTE_SWLOCATION_SHIFT 8 /**< Shift value for GPIO_SWLOCATION */ +#define _GPIO_ROUTE_SWLOCATION_MASK 0x300UL /**< Bit mask for GPIO_SWLOCATION */ +#define GPIO_ROUTE_SWLOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_ROUTE */ +#define GPIO_ROUTE_SWLOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for GPIO_ROUTE */ +#define GPIO_ROUTE_SWLOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for GPIO_ROUTE */ +#define GPIO_ROUTE_SWLOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for GPIO_ROUTE */ +#define GPIO_ROUTE_SWLOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for GPIO_ROUTE */ +#define _GPIO_ROUTE_SWLOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ +#define _GPIO_ROUTE_SWLOCATION_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTE */ +#define _GPIO_ROUTE_SWLOCATION_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTE */ +#define _GPIO_ROUTE_SWLOCATION_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTE */ +#define _GPIO_ROUTE_SWLOCATION_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTE */ + +/** Bit fields for GPIO INSENSE */ +#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */ +#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */ +#define GPIO_INSENSE_INTSENSE (1 << 0) /**< Interrupt Sense Enable */ +#define _GPIO_INSENSE_INTSENSE_SHIFT 0 /**< Shift value for GPIO_INTSENSE */ +#define _GPIO_INSENSE_INTSENSE_MASK 0x1UL /**< Bit mask for GPIO_INTSENSE */ +#define GPIO_INSENSE_INTSENSE_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */ +#define _GPIO_INSENSE_INTSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_PRSSENSE (1 << 1) /**< PRS Sense Enable */ +#define _GPIO_INSENSE_PRSSENSE_SHIFT 1 /**< Shift value for GPIO_PRSSENSE */ +#define _GPIO_INSENSE_PRSSENSE_MASK 0x2UL /**< Bit mask for GPIO_PRSSENSE */ +#define GPIO_INSENSE_PRSSENSE_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */ +#define _GPIO_INSENSE_PRSSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ + +/** Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (0x0000A534UL << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_PRS + * @{ + */ + +/** Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x000000FFUL /**< Mask for PRS_SWPULSE */ +#define _PRS_SWPULSE_SWPULSE_SHIFT 0 /**< Shift value for PRS_SWPULSE */ +#define _PRS_SWPULSE_SWPULSE_MASK 0xFFUL /**< Bit mask for PRS_SWPULSE */ +#define PRS_SWPULSE_SWPULSE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define _PRS_SWPULSE_SWPULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ + +/** Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x000000FFUL /**< Mask for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_SWLEVEL_SHIFT 0 /**< Shift value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_SWLEVEL_MASK 0xFFUL /**< Bit mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_SWLEVEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_SWLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ + +/** Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x033F0007UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define PRS_CH_CTRL_SIGSEL_VCMPOUT (0x00000000UL << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (0x00000000UL << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (0x00000000UL << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (0x00000000UL << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (0x00000000UL << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (0x00000000UL << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (0x00000000UL << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (0x00000001UL << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (0x00000001UL << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (0x00000001UL << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (0x00000001UL << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (0x00000001UL << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (0x00000001UL << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (0x00000001UL << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (0x00000001UL << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (0x00000002UL << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (0x00000002UL << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (0x00000002UL << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (0x00000002UL << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (0x00000002UL << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (0x00000002UL << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (0x00000003UL << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (0x00000004UL << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (0x00000005UL << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (0x00000006UL << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (0x00000007UL << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (0x00000000UL << 16) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VCMP (0x00000001UL << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (0x00000002UL << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (0x00000003UL << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_DAC0 (0x00000006UL << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (0x00000008UL << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (0x00000010UL << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (0x00000011UL << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (0x00000012UL << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (0x0000001CUL << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (0x0000001DUL << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (0x0000001EUL << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (0x00000028UL << 16) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (0x00000029UL << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (0x00000030UL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (0x00000031UL << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (0x00000000UL << 24) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (0x00000001UL << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (0x00000002UL << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (0x00000003UL << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_DMA + * @{ + */ + +/** Bit fields for DMA STATUS */ +#define _DMA_STATUS_RESETVALUE 0x10070000UL /**< Default value for DMA_STATUS */ +#define _DMA_STATUS_MASK 0xF01F00F1UL /**< Mask for DMA_STATUS */ +#define DMA_STATUS_EN (1 << 0) /**< DMA Enable Status */ +#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */ +#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */ +#define DMA_STATUS_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_STATUS */ +#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */ +#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */ +#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */ +#define DMA_STATUS_STATE_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DMA_STATUS */ +#define DMA_STATUS_STATE_IDLE (0x00000000UL << 4) /**< Shifted mode IDLE for DMA_STATUS */ +#define DMA_STATUS_STATE_RDCHCTRLDATA (0x00000001UL << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */ +#define DMA_STATUS_STATE_RDSRCENDPTR (0x00000002UL << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */ +#define DMA_STATUS_STATE_RDDSTENDPTR (0x00000003UL << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */ +#define DMA_STATUS_STATE_RDSRCDATA (0x00000004UL << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */ +#define DMA_STATUS_STATE_WRDSTDATA (0x00000005UL << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */ +#define DMA_STATUS_STATE_WAITREQCLR (0x00000006UL << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */ +#define DMA_STATUS_STATE_WRCHCTRLDATA (0x00000007UL << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */ +#define DMA_STATUS_STATE_STALLED (0x00000008UL << 4) /**< Shifted mode STALLED for DMA_STATUS */ +#define DMA_STATUS_STATE_DONE (0x00000009UL << 4) /**< Shifted mode DONE for DMA_STATUS */ +#define DMA_STATUS_STATE_PERSCATTRANS (0x0000000AUL << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */ +#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */ +#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */ +#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */ +#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */ +#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */ +#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */ +#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */ +#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */ +#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */ +#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */ +#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */ +#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */ +#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */ +#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */ +#define DMA_STATUS_CHNUM_DEFAULT (0x00000007UL << 16) /**< Shifted mode DEFAULT for DMA_STATUS */ +#define _DMA_STATUS_CHNUM_DEFAULT 0x00000007UL /**< Mode DEFAULT for DMA_STATUS */ +#define _DMA_STATUS_TEST_SHIFT 28 /**< Shift value for DMA_TEST */ +#define _DMA_STATUS_TEST_MASK 0xF0000000UL /**< Bit mask for DMA_TEST */ +#define DMA_STATUS_TEST_DEFAULT (0x00000001UL << 28) /**< Shifted mode DEFAULT for DMA_STATUS */ +#define _DMA_STATUS_TEST_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_STATUS */ + +/** Bit fields for DMA CONFIG */ +#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */ +#define _DMA_CONFIG_MASK 0x000000E1UL /**< Mask for DMA_CONFIG */ +#define DMA_CONFIG_EN (1 << 0) /**< Enable DMA */ +#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */ +#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */ +#define DMA_CONFIG_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */ +#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */ +#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */ +#define _DMA_CONFIG_CHPROT_MASK 0xE0UL /**< Bit mask for DMA_CHPROT */ +#define DMA_CONFIG_CHPROT_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */ +#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */ + +/** Bit fields for DMA CTRLBASE */ +#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */ +#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */ +#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */ +#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */ +#define DMA_CTRLBASE_CTRLBASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */ +#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */ + +/** Bit fields for DMA ALTCTRLBASE */ +#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL /**< Default value for DMA_ALTCTRLBASE */ +#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */ +#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */ +#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */ +#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (0x00000080UL << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */ +#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */ + +/** Bit fields for DMA WAITSTATUS */ +#define _DMA_WAITSTATUS_RESETVALUE 0x000000FFUL /**< Default value for DMA_WAITSTATUS */ +#define _DMA_WAITSTATUS_MASK 0xFFFFFFFFUL /**< Mask for DMA_WAITSTATUS */ +#define _DMA_WAITSTATUS_WAITSTATUS_SHIFT 0 /**< Shift value for DMA_WAITSTATUS */ +#define _DMA_WAITSTATUS_WAITSTATUS_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_WAITSTATUS */ +#define DMA_WAITSTATUS_WAITSTATUS_DEFAULT (0x000000FFUL << 0) /**< Shifted mode DEFAULT for DMA_WAITSTATUS */ +#define _DMA_WAITSTATUS_WAITSTATUS_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DMA_WAITSTATUS */ + +/** Bit fields for DMA CHSWREQ */ +#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */ +#define _DMA_CHSWREQ_MASK 0x000000FFUL /**< Mask for DMA_CHSWREQ */ +#define _DMA_CHSWREQ_CHSWREQ_SHIFT 0 /**< Shift value for DMA_CHSWREQ */ +#define _DMA_CHSWREQ_CHSWREQ_MASK 0xFFUL /**< Bit mask for DMA_CHSWREQ */ +#define DMA_CHSWREQ_CHSWREQ_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */ +#define _DMA_CHSWREQ_CHSWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */ + +/** Bit fields for DMA CHUSEBURSTS */ +#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */ +#define _DMA_CHUSEBURSTS_MASK 0x000000FFUL /**< Mask for DMA_CHUSEBURSTS */ +#define _DMA_CHUSEBURSTS_CHUSEBURSTS_SHIFT 0 /**< Shift value for DMA_CHUSEBURSTS */ +#define _DMA_CHUSEBURSTS_CHUSEBURSTS_MASK 0xFFUL /**< Bit mask for DMA_CHUSEBURSTS */ +#define DMA_CHUSEBURSTS_CHUSEBURSTS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */ +#define DMA_CHUSEBURSTS_CHUSEBURSTS_SINGLEANDBURST (0x00000000UL << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */ +#define DMA_CHUSEBURSTS_CHUSEBURSTS_BURSTONLY (0x00000001UL << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */ +#define _DMA_CHUSEBURSTS_CHUSEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */ +#define _DMA_CHUSEBURSTS_CHUSEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */ +#define _DMA_CHUSEBURSTS_CHUSEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */ + +/** Bit fields for DMA CHUSEBURSTC */ +#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */ +#define _DMA_CHUSEBURSTC_MASK 0x000000FFUL /**< Mask for DMA_CHUSEBURSTC */ +#define _DMA_CHUSEBURSTC_CHUSEBURSTC_SHIFT 0 /**< Shift value for DMA_CHUSEBURSTC */ +#define _DMA_CHUSEBURSTC_CHUSEBURSTC_MASK 0xFFUL /**< Bit mask for DMA_CHUSEBURSTC */ +#define DMA_CHUSEBURSTC_CHUSEBURSTC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */ +#define _DMA_CHUSEBURSTC_CHUSEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */ + +/** Bit fields for DMA CHREQMASKS */ +#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */ +#define _DMA_CHREQMASKS_MASK 0x000000FFUL /**< Mask for DMA_CHREQMASKS */ +#define _DMA_CHREQMASKS_CHREQMASKS_SHIFT 0 /**< Shift value for DMA_CHREQMASKS */ +#define _DMA_CHREQMASKS_CHREQMASKS_MASK 0xFFUL /**< Bit mask for DMA_CHREQMASKS */ +#define DMA_CHREQMASKS_CHREQMASKS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */ +#define _DMA_CHREQMASKS_CHREQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */ + +/** Bit fields for DMA CHREQMASKC */ +#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */ +#define _DMA_CHREQMASKC_MASK 0x000000FFUL /**< Mask for DMA_CHREQMASKC */ +#define _DMA_CHREQMASKC_CHREQMASKC_SHIFT 0 /**< Shift value for DMA_CHREQMASKC */ +#define _DMA_CHREQMASKC_CHREQMASKC_MASK 0xFFUL /**< Bit mask for DMA_CHREQMASKC */ +#define DMA_CHREQMASKC_CHREQMASKC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */ +#define _DMA_CHREQMASKC_CHREQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */ + +/** Bit fields for DMA CHENS */ +#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */ +#define _DMA_CHENS_MASK 0x000000FFUL /**< Mask for DMA_CHENS */ +#define _DMA_CHENS_CHENS_SHIFT 0 /**< Shift value for DMA_CHENS */ +#define _DMA_CHENS_CHENS_MASK 0xFFUL /**< Bit mask for DMA_CHENS */ +#define DMA_CHENS_CHENS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHENS */ +#define _DMA_CHENS_CHENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */ + +/** Bit fields for DMA CHENC */ +#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */ +#define _DMA_CHENC_MASK 0x000000FFUL /**< Mask for DMA_CHENC */ +#define _DMA_CHENC_CHENC_SHIFT 0 /**< Shift value for DMA_CHENC */ +#define _DMA_CHENC_CHENC_MASK 0xFFUL /**< Bit mask for DMA_CHENC */ +#define DMA_CHENC_CHENC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHENC */ +#define _DMA_CHENC_CHENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */ + +/** Bit fields for DMA CHALTS */ +#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */ +#define _DMA_CHALTS_MASK 0x000000FFUL /**< Mask for DMA_CHALTS */ +#define _DMA_CHALTS_CHALTS_SHIFT 0 /**< Shift value for DMA_CHALTS */ +#define _DMA_CHALTS_CHALTS_MASK 0xFFUL /**< Bit mask for DMA_CHALTS */ +#define DMA_CHALTS_CHALTS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */ +#define _DMA_CHALTS_CHALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */ + +/** Bit fields for DMA CHALTC */ +#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */ +#define _DMA_CHALTC_MASK 0x000000FFUL /**< Mask for DMA_CHALTC */ +#define _DMA_CHALTC_CHALTC_SHIFT 0 /**< Shift value for DMA_CHALTC */ +#define _DMA_CHALTC_CHALTC_MASK 0xFFUL /**< Bit mask for DMA_CHALTC */ +#define DMA_CHALTC_CHALTC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */ +#define _DMA_CHALTC_CHALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */ + +/** Bit fields for DMA CHPRIS */ +#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */ +#define _DMA_CHPRIS_MASK 0x000000FFUL /**< Mask for DMA_CHPRIS */ +#define _DMA_CHPRIS_CHPRIS_SHIFT 0 /**< Shift value for DMA_CHPRIS */ +#define _DMA_CHPRIS_CHPRIS_MASK 0xFFUL /**< Bit mask for DMA_CHPRIS */ +#define DMA_CHPRIS_CHPRIS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */ +#define _DMA_CHPRIS_CHPRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */ + +/** Bit fields for DMA CHPRIC */ +#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */ +#define _DMA_CHPRIC_MASK 0x000000FFUL /**< Mask for DMA_CHPRIC */ +#define _DMA_CHPRIC_CHPRIC_SHIFT 0 /**< Shift value for DMA_CHPRIC */ +#define _DMA_CHPRIC_CHPRIC_MASK 0xFFUL /**< Bit mask for DMA_CHPRIC */ +#define DMA_CHPRIC_CHPRIC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */ +#define _DMA_CHPRIC_CHPRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */ + +/** Bit fields for DMA ERRORC */ +#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */ +#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */ +#define DMA_ERRORC_ERRORC (1 << 0) /**< Bus Error Clear */ +#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */ +#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */ +#define DMA_ERRORC_ERRORC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */ +#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */ + +/** Bit fields for DMA IF */ +#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */ +#define _DMA_IF_MASK 0x800000FFUL /**< Mask for DMA_IF */ +#define _DMA_IF_DONE_SHIFT 0 /**< Shift value for DMA_DONE */ +#define _DMA_IF_DONE_MASK 0xFFUL /**< Bit mask for DMA_DONE */ +#define DMA_IF_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_IF */ +#define _DMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */ +#define DMA_IF_ERR (1 << 31) /**< DMA Error Interrupt Flag */ +#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */ +#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */ +#define DMA_IF_ERR_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for DMA_IF */ +#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */ + +/** Bit fields for DMA IFS */ +#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */ +#define _DMA_IFS_MASK 0x800000FFUL /**< Mask for DMA_IFS */ +#define _DMA_IFS_DONE_SHIFT 0 /**< Shift value for DMA_DONE */ +#define _DMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for DMA_DONE */ +#define DMA_IFS_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_IFS */ +#define _DMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */ +#define DMA_IFS_ERR (1 << 31) /**< DMA Error Interrupt Flag Set */ +#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */ +#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */ +#define DMA_IFS_ERR_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for DMA_IFS */ +#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */ + +/** Bit fields for DMA IFC */ +#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */ +#define _DMA_IFC_MASK 0x800000FFUL /**< Mask for DMA_IFC */ +#define _DMA_IFC_DONE_SHIFT 0 /**< Shift value for DMA_DONE */ +#define _DMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for DMA_DONE */ +#define DMA_IFC_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_IFC */ +#define _DMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */ +#define DMA_IFC_ERR (1 << 31) /**< DMA Error Interrupt Flag Clear */ +#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */ +#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */ +#define DMA_IFC_ERR_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for DMA_IFC */ +#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */ + +/** Bit fields for DMA IEN */ +#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */ +#define _DMA_IEN_MASK 0x800000FFUL /**< Mask for DMA_IEN */ +#define _DMA_IEN_DONE_SHIFT 0 /**< Shift value for DMA_DONE */ +#define _DMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for DMA_DONE */ +#define DMA_IEN_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_IEN */ +#define _DMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */ +#define DMA_IEN_ERR (1 << 31) /**< DMA Error Interrupt Flag Enable */ +#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */ +#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */ +#define DMA_IEN_ERR_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for DMA_IEN */ +#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */ + +/** Bit fields for DMA CH_CTRL */ +#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */ +#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */ +#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (0x00000000UL << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (0x00000000UL << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (0x00000000UL << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (0x00000000UL << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (0x00000000UL << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (0x00000000UL << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (0x00000000UL << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (0x00000000UL << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (0x00000000UL << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (0x00000000UL << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (0x00000000UL << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_UART0RXDATAV (0x00000000UL << 0) /**< Shifted mode UART0RXDATAV for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_MSCWDATA (0x00000000UL << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_AESDATAWR (0x00000000UL << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (0x00000001UL << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (0x00000001UL << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_USART0TXBL (0x00000001UL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_USART1TXBL (0x00000001UL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_USART2TXBL (0x00000001UL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (0x00000001UL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (0x00000001UL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (0x00000001UL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000001UL << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000001UL << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000001UL << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_UART0TXBL (0x00000001UL << 0) /**< Shifted mode UART0TXBL for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (0x00000001UL << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (0x00000002UL << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (0x00000002UL << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (0x00000002UL << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (0x00000002UL << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (0x00000002UL << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000002UL << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000002UL << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000002UL << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (0x00000002UL << 0) /**< Shifted mode UART0TXEMPTY for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_AESDATARD (0x00000002UL << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000003UL << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000003UL << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000003UL << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SIGSEL_AESKEYWR (0x00000003UL << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL /**< Mode UART0RXDATAV for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL /**< Mode UART0TXBL for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL /**< Mode UART0TXEMPTY for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */ +#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */ +#define DMA_CH_CTRL_SOURCESEL_NONE (0x00000000UL << 16) /**< Shifted mode NONE for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_ADC0 (0x00000008UL << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_DAC0 (0x0000000AUL << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_USART0 (0x0000000CUL << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_USART1 (0x0000000DUL << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_USART2 (0x0000000EUL << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_LEUART0 (0x00000010UL << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_LEUART1 (0x00000011UL << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_I2C0 (0x00000014UL << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_TIMER0 (0x00000018UL << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_TIMER1 (0x00000019UL << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_TIMER2 (0x0000001AUL << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_UART0 (0x0000002CUL << 16) /**< Shifted mode UART0 for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_IMEM (0x00000030UL << 16) /**< Shifted mode IMEM for DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_AES (0x00000031UL << 16) /**< Shifted mode AES for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL /**< Mode UART0 for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_IMEM 0x00000030UL /**< Mode IMEM for DMA_CH_CTRL */ +#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_VCMP + * @{ + */ + +/** Bit fields for VCMP CTRL */ +#define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */ +#define _VCMP_CTRL_MASK 0x4F030715UL /**< Mask for VCMP_CTRL */ +#define VCMP_CTRL_EN (1 << 0) /**< Voltage Supply Comparator Enable */ +#define _VCMP_CTRL_EN_SHIFT 0 /**< Shift value for VCMP_EN */ +#define _VCMP_CTRL_EN_MASK 0x1UL /**< Bit mask for VCMP_EN */ +#define VCMP_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_INACTVAL (1 << 2) /**< Inactive Value */ +#define _VCMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for VCMP_INACTVAL */ +#define _VCMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for VCMP_INACTVAL */ +#define VCMP_CTRL_INACTVAL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_HYSTEN (1 << 4) /**< Hysteresis Enable */ +#define _VCMP_CTRL_HYSTEN_SHIFT 4 /**< Shift value for VCMP_HYSTEN */ +#define _VCMP_CTRL_HYSTEN_MASK 0x10UL /**< Bit mask for VCMP_HYSTEN */ +#define VCMP_CTRL_HYSTEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for VCMP_WARMTIME */ +#define _VCMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for VCMP_WARMTIME */ +#define VCMP_CTRL_WARMTIME_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_4CYCLES (0x00000000UL << 8) /**< Shifted mode 4CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_8CYCLES (0x00000001UL << 8) /**< Shifted mode 8CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_16CYCLES (0x00000002UL << 8) /**< Shifted mode 16CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_32CYCLES (0x00000003UL << 8) /**< Shifted mode 32CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_64CYCLES (0x00000004UL << 8) /**< Shifted mode 64CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_128CYCLES (0x00000005UL << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_256CYCLES (0x00000006UL << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_512CYCLES (0x00000007UL << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_IRISE (1 << 16) /**< Rising Edge Interrupt Sense */ +#define _VCMP_CTRL_IRISE_SHIFT 16 /**< Shift value for VCMP_IRISE */ +#define _VCMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for VCMP_IRISE */ +#define VCMP_CTRL_IRISE_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_IFALL (1 << 17) /**< Falling Edge Interrupt Sense */ +#define _VCMP_CTRL_IFALL_SHIFT 17 /**< Shift value for VCMP_IFALL */ +#define _VCMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for VCMP_IFALL */ +#define VCMP_CTRL_IFALL_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for VCMP_BIASPROG */ +#define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for VCMP_BIASPROG */ +#define VCMP_CTRL_BIASPROG_DEFAULT (0x00000007UL << 24) /**< Shifted mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_HALFBIAS (1 << 30) /**< Half Bias Current */ +#define _VCMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for VCMP_HALFBIAS */ +#define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for VCMP_HALFBIAS */ +#define VCMP_CTRL_HALFBIAS_DEFAULT (0x00000001UL << 30) /**< Shifted mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VCMP_CTRL */ + +/** Bit fields for VCMP INPUTSEL */ +#define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for VCMP_INPUTSEL */ +#define _VCMP_INPUTSEL_MASK 0x0000013FUL /**< Mask for VCMP_INPUTSEL */ +#define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /**< Shift value for VCMP_TRIGLEVEL */ +#define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /**< Bit mask for VCMP_TRIGLEVEL */ +#define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */ +#define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */ +#define VCMP_INPUTSEL_LPREF (1 << 8) /**< Low Power Reference */ +#define _VCMP_INPUTSEL_LPREF_SHIFT 8 /**< Shift value for VCMP_LPREF */ +#define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /**< Bit mask for VCMP_LPREF */ +#define VCMP_INPUTSEL_LPREF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */ +#define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */ + +/** Bit fields for VCMP STATUS */ +#define _VCMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for VCMP_STATUS */ +#define _VCMP_STATUS_MASK 0x00000003UL /**< Mask for VCMP_STATUS */ +#define VCMP_STATUS_VCMPACT (1 << 0) /**< Voltage Supply Comparator Active */ +#define _VCMP_STATUS_VCMPACT_SHIFT 0 /**< Shift value for VCMP_VCMPACT */ +#define _VCMP_STATUS_VCMPACT_MASK 0x1UL /**< Bit mask for VCMP_VCMPACT */ +#define VCMP_STATUS_VCMPACT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */ +#define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */ +#define VCMP_STATUS_VCMPOUT (1 << 1) /**< Voltage Supply Comparator Output */ +#define _VCMP_STATUS_VCMPOUT_SHIFT 1 /**< Shift value for VCMP_VCMPOUT */ +#define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /**< Bit mask for VCMP_VCMPOUT */ +#define VCMP_STATUS_VCMPOUT_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */ +#define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */ + +/** Bit fields for VCMP IEN */ +#define _VCMP_IEN_RESETVALUE 0x00000000UL /**< Default value for VCMP_IEN */ +#define _VCMP_IEN_MASK 0x00000003UL /**< Mask for VCMP_IEN */ +#define VCMP_IEN_EDGE (1 << 0) /**< Edge Trigger Interrupt Enable */ +#define _VCMP_IEN_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ +#define _VCMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ +#define VCMP_IEN_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_IEN */ +#define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */ +#define VCMP_IEN_WARMUP (1 << 1) /**< Warm-up Interrupt Enable */ +#define _VCMP_IEN_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ +#define _VCMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ +#define VCMP_IEN_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_IEN */ +#define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */ + +/** Bit fields for VCMP IF */ +#define _VCMP_IF_RESETVALUE 0x00000000UL /**< Default value for VCMP_IF */ +#define _VCMP_IF_MASK 0x00000003UL /**< Mask for VCMP_IF */ +#define VCMP_IF_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag */ +#define _VCMP_IF_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ +#define _VCMP_IF_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ +#define VCMP_IF_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_IF */ +#define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */ +#define VCMP_IF_WARMUP (1 << 1) /**< Warm-up Interrupt Flag */ +#define _VCMP_IF_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ +#define _VCMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ +#define VCMP_IF_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_IF */ +#define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */ + +/** Bit fields for VCMP IFS */ +#define _VCMP_IFS_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFS */ +#define _VCMP_IFS_MASK 0x00000003UL /**< Mask for VCMP_IFS */ +#define VCMP_IFS_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag Set */ +#define _VCMP_IFS_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ +#define _VCMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ +#define VCMP_IFS_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_IFS */ +#define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */ +#define VCMP_IFS_WARMUP (1 << 1) /**< Warm-up Interrupt Flag Set */ +#define _VCMP_IFS_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ +#define _VCMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ +#define VCMP_IFS_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_IFS */ +#define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */ + +/** Bit fields for VCMP IFC */ +#define _VCMP_IFC_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFC */ +#define _VCMP_IFC_MASK 0x00000003UL /**< Mask for VCMP_IFC */ +#define VCMP_IFC_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag Clear */ +#define _VCMP_IFC_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ +#define _VCMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ +#define VCMP_IFC_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_IFC */ +#define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */ +#define VCMP_IFC_WARMUP (1 << 1) /**< Warm-up Interrupt Flag Clear */ +#define _VCMP_IFC_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ +#define _VCMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ +#define VCMP_IFC_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_IFC */ +#define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_LCD + * @{ + */ + +/** Bit fields for LCD CTRL */ +#define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */ +#define _LCD_CTRL_MASK 0x00000007UL /**< Mask for LCD_CTRL */ +#define LCD_CTRL_EN (1 << 0) /**< LCD Enable */ +#define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */ +#define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */ +#define LCD_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */ +#define LCD_CTRL_UDCTRL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_REGULAR (0x00000000UL << 1) /**< Shifted mode REGULAR for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_LFCEVENT (0x00000001UL << 1) /**< Shifted mode LFCEVENT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FRAMESTART (0x00000002UL << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_LFCEVENT 0x00000001UL /**< Mode LFCEVENT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */ + +/** Bit fields for LCD DISPCTRL */ +#define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MASK 0x001D9F1FUL /**< Mask for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */ +#define LCD_DISPCTRL_MUX_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_STATIC (0x00000000UL << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DUPLEX (0x00000001UL << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_TRIPLEX (0x00000002UL << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_QUADRUPLEX (0x00000003UL << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */ +#define LCD_DISPCTRL_BIAS_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_STATIC (0x00000000UL << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEHALF (0x00000001UL << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONETHIRD (0x00000002UL << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE (1 << 4) /**< Waveform Selection */ +#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */ +#define LCD_DISPCTRL_WAVE_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_LOWPOWER (0x00000000UL << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_NORMAL (0x00000001UL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */ +#define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */ +#define LCD_DISPCTRL_CONLEV_MIN (0x00000000UL << 8) /**< Shifted mode MIN for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONLEV_DEFAULT (0x0000001FUL << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONLEV_MAX (0x0000001FUL << 8) /**< Shifted mode MAX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONCONF (1 << 15) /**< Contrast Configuration */ +#define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */ +#define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */ +#define LCD_DISPCTRL_CONCONF_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONCONF_VLCD (0x00000000UL << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONCONF_GND (0x00000001UL << 15) /**< Shifted mode GND for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VLCDSEL (1 << 16) /**< VLCD Selection */ +#define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */ +#define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */ +#define LCD_DISPCTRL_VLCDSEL_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VLCDSEL_VDD (0x00000000UL << 16) /**< Shifted mode VDD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (0x00000001UL << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */ +#define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */ +#define LCD_DISPCTRL_VBLEV_3V00 (0x00000000UL << 18) /**< Shifted mode 3V00 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_3V09 (0x00000001UL << 18) /**< Shifted mode 3V09 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_3V17 (0x00000002UL << 18) /**< Shifted mode 3V17 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_DEFAULT (0x00000003UL << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_3V26 (0x00000003UL << 18) /**< Shifted mode 3V26 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_3V34 (0x00000004UL << 18) /**< Shifted mode 3V34 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_3V43 (0x00000005UL << 18) /**< Shifted mode 3V43 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_3V51 (0x00000006UL << 18) /**< Shifted mode 3V51 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_3V60 (0x00000007UL << 18) /**< Shifted mode 3V60 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_3V00 0x00000000UL /**< Mode 3V00 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_3V09 0x00000001UL /**< Mode 3V09 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_3V17 0x00000002UL /**< Mode 3V17 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_3V26 0x00000003UL /**< Mode 3V26 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_3V34 0x00000004UL /**< Mode 3V34 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_3V43 0x00000005UL /**< Mode 3V43 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_3V51 0x00000006UL /**< Mode 3V51 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_3V60 0x00000007UL /**< Mode 3V60 for LCD_DISPCTRL */ + +/** Bit fields for LCD SEGEN */ +#define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */ +#define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */ +#define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */ +#define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */ +#define LCD_SEGEN_SEGEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */ +#define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */ + +/** Bit fields for LCD BACTRL */ +#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */ +#define _LCD_BACTRL_MASK 0x00FF01FFUL /**< Mask for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN (1 << 0) /**< Blink Enable */ +#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */ +#define LCD_BACTRL_BLINKEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK (1 << 1) /**< Blank Display */ +#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */ +#define LCD_BACTRL_BLANK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AEN (1 << 2) /**< Animation Enable */ +#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */ +#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */ +#define LCD_BACTRL_AEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */ +#define LCD_BACTRL_AREGASC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_NOSHIFT (0x00000000UL << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTLEFT (0x00000001UL << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTRIGHT (0x00000002UL << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */ +#define LCD_BACTRL_AREGBSC_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_NOSHIFT (0x00000000UL << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTLEFT (0x00000001UL << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (0x00000002UL << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL (1 << 7) /**< Animate Logic Function Select */ +#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */ +#define LCD_BACTRL_ALOGSEL_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_AND (0x00000000UL << 7) /**< Shifted mode AND for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_OR (0x00000001UL << 7) /**< Shifted mode OR for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */ +#define LCD_BACTRL_FCEN (1 << 8) /**< Frame Counter Enable */ +#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */ +#define LCD_BACTRL_FCEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */ +#define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */ +#define LCD_BACTRL_FCPRESC_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV1 (0x00000000UL << 16) /**< Shifted mode DIV1 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV2 (0x00000001UL << 16) /**< Shifted mode DIV2 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV4 (0x00000002UL << 16) /**< Shifted mode DIV4 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV8 (0x00000003UL << 16) /**< Shifted mode DIV8 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */ +#define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */ +#define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */ +#define LCD_BACTRL_FCTOP_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ + +/** Bit fields for LCD STATUS */ +#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */ +#define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */ +#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */ +#define LCD_STATUS_ASTATE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK (1 << 8) /**< Blink State */ +#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */ +#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */ +#define LCD_STATUS_BLINK_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ + +/** Bit fields for LCD AREGA */ +#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */ +#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */ +#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */ +#define LCD_AREGA_AREGA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_AREGA */ +#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */ + +/** Bit fields for LCD AREGB */ +#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */ +#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */ +#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */ +#define LCD_AREGB_AREGB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_AREGB */ +#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */ + +/** Bit fields for LCD IF */ +#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */ +#define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */ +#define LCD_IF_FC (1 << 0) /**< Frame Counter Interrupt Flag */ +#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define LCD_IF_FC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_IF */ +#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ + +/** Bit fields for LCD IFS */ +#define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */ +#define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */ +#define LCD_IFS_FC (1 << 0) /**< Frame Counter Interrupt Flag Set */ +#define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define LCD_IFS_FC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_IFS */ +#define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */ + +/** Bit fields for LCD IFC */ +#define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */ +#define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */ +#define LCD_IFC_FC (1 << 0) /**< Frame Counter Interrupt Flag Clear */ +#define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define LCD_IFC_FC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_IFC */ +#define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */ + +/** Bit fields for LCD IEN */ +#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */ +#define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */ +#define LCD_IEN_FC (1 << 0) /**< Frame Counter Interrupt Enable */ +#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define LCD_IEN_FC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_IEN */ +#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ + +/** Bit fields for LCD SEGD0L */ +#define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */ +#define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */ +#define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */ +#define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */ +#define LCD_SEGD0L_SEGD0L_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */ +#define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */ + +/** Bit fields for LCD SEGD1L */ +#define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */ +#define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */ +#define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */ +#define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */ +#define LCD_SEGD1L_SEGD1L_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */ +#define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */ + +/** Bit fields for LCD SEGD2L */ +#define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */ +#define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */ +#define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */ +#define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */ +#define LCD_SEGD2L_SEGD2L_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */ +#define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */ + +/** Bit fields for LCD SEGD3L */ +#define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */ +#define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */ +#define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */ +#define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */ +#define LCD_SEGD3L_SEGD3L_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */ +#define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */ + +/** Bit fields for LCD SEGD0H */ +#define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */ +#define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */ +#define LCD_SEGD0H_SEGD0H_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */ + +/** Bit fields for LCD SEGD1H */ +#define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */ +#define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */ +#define LCD_SEGD1H_SEGD1H_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */ + +/** Bit fields for LCD SEGD2H */ +#define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */ +#define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */ +#define LCD_SEGD2H_SEGD2H_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */ + +/** Bit fields for LCD SEGD3H */ +#define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */ +#define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */ +#define LCD_SEGD3H_SEGD3H_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */ + +/** Bit fields for LCD FREEZE */ +#define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */ +#define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */ +#define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */ +#define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */ +#define LCD_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for LCD_FREEZE */ +#define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */ +#define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */ +#define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */ + +/** Bit fields for LCD SYNCBUSY */ +#define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_CTRL (1 << 0) /**< LCD_CTRL Register Busy */ +#define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */ +#define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */ +#define LCD_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_BACTRL (1 << 1) /**< LCD_BACTRL Register Busy */ +#define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */ +#define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */ +#define LCD_SYNCBUSY_BACTRL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGA (1 << 2) /**< LCD_AREGA Register Busy */ +#define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */ +#define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */ +#define LCD_SYNCBUSY_AREGA_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGB (1 << 3) /**< LCD_AREGB Register Busy */ +#define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */ +#define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */ +#define LCD_SYNCBUSY_AREGB_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0L (1 << 4) /**< LCD_SEGD0L Register Busy */ +#define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */ +#define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */ +#define LCD_SYNCBUSY_SEGD0L_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1L (1 << 5) /**< LCD_SEGD1L Register Busy */ +#define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */ +#define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */ +#define LCD_SYNCBUSY_SEGD1L_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2L (1 << 6) /**< LCD_SEGD2L Register Busy */ +#define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */ +#define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */ +#define LCD_SYNCBUSY_SEGD2L_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3L (1 << 7) /**< LCD_SEGD3L Register Busy */ +#define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */ +#define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */ +#define LCD_SYNCBUSY_SEGD3L_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0H (1 << 8) /**< LCD_SEGD0H Register Busy */ +#define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */ +#define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */ +#define LCD_SYNCBUSY_SEGD0H_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1H (1 << 9) /**< LCD_SEGD1H Register Busy */ +#define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */ +#define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */ +#define LCD_SYNCBUSY_SEGD1H_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2H (1 << 10) /**< LCD_SEGD2H Register Busy */ +#define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */ +#define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */ +#define LCD_SYNCBUSY_SEGD2H_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3H (1 << 11) /**< LCD_SEGD3H Register Busy */ +#define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */ +#define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */ +#define LCD_SYNCBUSY_SEGD3H_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_RTC + * @{ + */ + +/** Bit fields for RTC CTRL */ +#define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */ +#define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */ +#define RTC_CTRL_EN (1 << 0) /**< RTC Enable */ +#define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */ +#define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */ +#define RTC_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_CTRL */ +#define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_DEBUGRUN (1 << 1) /**< Debug Mode Run Enable */ +#define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */ +#define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */ +#define RTC_CTRL_DEBUGRUN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_CTRL */ +#define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP (1 << 2) /**< Compare Channel 0 is Top Value */ +#define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */ +#define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */ +#define RTC_CTRL_COMP0TOP_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP_DISABLE (0x00000000UL << 2) /**< Shifted mode DISABLE for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP_ENABLE (0x00000001UL << 2) /**< Shifted mode ENABLE for RTC_CTRL */ +#define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ +#define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */ +#define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */ + +/** Bit fields for RTC CNT */ +#define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */ +#define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */ +#define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */ +#define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */ +#define RTC_CNT_CNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_CNT */ +#define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */ + +/** Bit fields for RTC COMP0 */ +#define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */ +#define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */ +#define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */ +#define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */ +#define RTC_COMP0_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */ +#define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */ + +/** Bit fields for RTC COMP1 */ +#define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */ +#define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */ +#define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */ +#define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */ +#define RTC_COMP1_COMP1_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */ +#define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */ + +/** Bit fields for RTC IF */ +#define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */ +#define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */ +#define RTC_IF_OF (1 << 0) /**< Overflow Interrupt Flag */ +#define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */ +#define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ +#define RTC_IF_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_IF */ +#define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ +#define RTC_IF_COMP0 (1 << 1) /**< Compare Match 0 Interrupt Flag */ +#define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ +#define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ +#define RTC_IF_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_IF */ +#define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ +#define RTC_IF_COMP1 (1 << 2) /**< Compare Match 1 Interrupt Flag */ +#define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ +#define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ +#define RTC_IF_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_IF */ +#define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ + +/** Bit fields for RTC IFS */ +#define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */ +#define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */ +#define RTC_IFS_OF (1 << 0) /**< Set Overflow Interrupt Flag */ +#define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */ +#define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ +#define RTC_IFS_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_IFS */ +#define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ +#define RTC_IFS_COMP0 (1 << 1) /**< Set Compare match 0 Interrupt Flag */ +#define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ +#define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ +#define RTC_IFS_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_IFS */ +#define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ +#define RTC_IFS_COMP1 (1 << 2) /**< Set Compare match 1 Interrupt Flag */ +#define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ +#define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ +#define RTC_IFS_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_IFS */ +#define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ + +/** Bit fields for RTC IFC */ +#define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */ +#define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */ +#define RTC_IFC_OF (1 << 0) /**< Clear Overflow Interrupt Flag */ +#define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */ +#define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ +#define RTC_IFC_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_IFC */ +#define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ +#define RTC_IFC_COMP0 (1 << 1) /**< Clear Compare match 0 Interrupt Flag */ +#define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ +#define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ +#define RTC_IFC_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_IFC */ +#define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ +#define RTC_IFC_COMP1 (1 << 2) /**< Clear Compare match 1 Interrupt Flag */ +#define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ +#define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ +#define RTC_IFC_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_IFC */ +#define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ + +/** Bit fields for RTC IEN */ +#define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */ +#define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */ +#define RTC_IEN_OF (1 << 0) /**< Overflow Interrupt Enable */ +#define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */ +#define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ +#define RTC_IEN_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_IEN */ +#define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ +#define RTC_IEN_COMP0 (1 << 1) /**< Compare Match 0 Interrupt Enable */ +#define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ +#define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ +#define RTC_IEN_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_IEN */ +#define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ +#define RTC_IEN_COMP1 (1 << 2) /**< Compare Match 1 Interrupt Enable */ +#define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ +#define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ +#define RTC_IEN_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_IEN */ +#define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ + +/** Bit fields for RTC FREEZE */ +#define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */ +#define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */ +#define RTC_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */ +#define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */ +#define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */ +#define RTC_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */ +#define RTC_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for RTC_FREEZE */ +#define RTC_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for RTC_FREEZE */ +#define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */ +#define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */ +#define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */ + +/** Bit fields for RTC SYNCBUSY */ +#define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */ +#define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */ +#define RTC_SYNCBUSY_CTRL (1 << 0) /**< RTC_CTRL Register Busy */ +#define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */ +#define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */ +#define RTC_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ +#define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ +#define RTC_SYNCBUSY_COMP0 (1 << 1) /**< RTC_COMP0 Register Busy */ +#define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ +#define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ +#define RTC_SYNCBUSY_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ +#define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ +#define RTC_SYNCBUSY_COMP1 (1 << 2) /**< RTC_COMP1 Register Busy */ +#define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ +#define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ +#define RTC_SYNCBUSY_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ +#define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_WDOG + * @{ + */ + +/** Bit fields for WDOG CTRL */ +#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */ +#define _WDOG_CTRL_MASK 0x00003F7FUL /**< Mask for WDOG_CTRL */ +#define WDOG_CTRL_EN (1 << 0) /**< Watchdog Timer Enable */ +#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define WDOG_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN (1 << 1) /**< Debug Mode Run Enable */ +#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */ +#define WDOG_CTRL_DEBUGRUN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN (1 << 2) /**< Energy Mode 2 Run Enable */ +#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define WDOG_CTRL_EM2RUN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN (1 << 3) /**< Energy Mode 3 Run Enable */ +#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define WDOG_CTRL_EM3RUN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK (1 << 4) /**< Configuration lock */ +#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */ +#define WDOG_CTRL_LOCK_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK (1 << 5) /**< Energy Mode 4 Block */ +#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */ +#define WDOG_CTRL_EM4BLOCK_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK (1 << 6) /**< Oscillator disabling by software block */ +#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */ +#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */ +#define WDOG_CTRL_PERSEL_DEFAULT (0x0000000FUL << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */ +#define WDOG_CTRL_CLKSEL_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_1KHZ (0x00000000UL << 12) /**< Shifted mode 1KHZ for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFRCO (0x00000001UL << 12) /**< Shifted mode LFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFXO (0x00000002UL << 12) /**< Shifted mode LFXO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_1KHZ 0x00000000UL /**< Mode 1KHZ for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */ + +/** Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (1 << 0) /**< Watchdog Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define WDOG_CMD_CLEAR_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (0x00000000UL << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (0x00000001UL << 0) /**< Shifted mode CLEARED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ + +/** Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000003UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL (1 << 0) /**< WDOG_CTRL Register Busy */ +#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */ +#define WDOG_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (1 << 1) /**< WDOG_CMD Register Busy */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ + +/** + * @} + */ + +/** + * @addtogroup EFM32G890F128_DEVINFO + * @\{ + */ +/** Bit fields for EFM32G890F128_DEVINFO */ +#define _DEVINFO_UNIQUEL_MASK (0xFFFFFFFFUL) +#define _DEVINFO_UNIQUEL_SHIFT 0 +#define _DEVINFO_UNIQUEH_MASK (0xFFFFFFFFUL) +#define _DEVINFO_UNIQUEH_SHIFT 0 +#define _DEVINFO_MSIZE_FLASH_MASK (0xFFFF0000UL) +#define _DEVINFO_MSIZE_FLASH_SHIFT 16 +#define _DEVINFO_MSIZE_SRAM_MASK (0x0000FFFFUL) +#define _DEVINFO_MSIZE_SRAM_SHIFT 0 +#define _DEVINFO_PART_DEVICE_FAMILY_MASK (0x00FF0000UL) +#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 +#define _DEVINFO_PART_DEVICE_NUMBER_MASK (0x0000FFFFUL) +#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 + +/** + * @\} + */ + +/** + * @addtogroup EFM32G890F128_CALIB + * @\{ + */ + +/** Bit fields for Calibration Special Registers */ +#define _HFRCO_CALIBH_28MHZ_MASK (0x000000FFUL) +#define _HFRCO_CALIBH_28MHZ_SHIFT 0 +#define _HFRCO_CALIBL_21MHZ_MASK (0xFF000000UL) +#define _HFRCO_CALIBL_21MHZ_SHIFT 24 +#define _HFRCO_CALIBL_11MHZ_MASK (0x00FF0000UL) +#define _HFRCO_CALIBL_11MHZ_SHIFT 16 +#define _HFRCO_CALIBL_7MHZ_MASK (0x0000FF00UL) +#define _HFRCO_CALIBL_7MHZ_SHIFT 8 +#define _HFRCO_CALIBL_1MHZ_MASK (0x000000FFUL) +#define _HFRCO_CALIBL_1MHZ_SHIFT 0 +#define _ADC_CALIB_TEMP_MASK (0xFF000000UL) +#define _ADC_CALIB_TEMP_SHIFT 24 +#define _ADC_CALIB_TUNING_MASK (0x00FFFFFFUL) +#define _ADC_CALIB_TUNING_SHIFT 0 + +/** + * @\} + */ + +/**************************************************************************//** + * + * Unlock codes + * + *****************************************************************************/ +/** @addtogroup EFM32G890F128_MSC + * @{ + */ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +/** + * @} + *//** @addtogroup EFM32G890F128_EMU + * @{ + */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +/** + * @} + *//** @addtogroup EFM32G890F128_CMU + * @{ + */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +/** + * @} + *//** @addtogroup EFM32G890F128_GPIO + * @{ + */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +/** + * @} + *//** @addtogroup EFM32G890F128_TIMER + * @{ + */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +/** + * @} + */ + +/**************************************************************************//** + * + * @defgroup EFM32G890F128_Alternate_Function EFM32G890F128 Alternate Function + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32G890F128_AF_Channels EFM32G890F128 AF Channels + * @{ + *****************************************************************************/ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 79 +#define AFCHANLOC_MAX 4 +/** Analog AF channels */ +#define AFACHAN_MAX 37 + +/** Peripheral Alternate Function (AF) channels */ +#define AF_CMU_CLKOUT0 0 +#define AF_CMU_CLKOUT1 1 +#define AF_EBI_ADDRDAT00 2 +#define AF_EBI_ADDRDAT01 3 +#define AF_EBI_ADDRDAT02 4 +#define AF_EBI_ADDRDAT03 5 +#define AF_EBI_ADDRDAT04 6 +#define AF_EBI_ADDRDAT05 7 +#define AF_EBI_ADDRDAT06 8 +#define AF_EBI_ADDRDAT07 9 +#define AF_EBI_ADDRDAT08 10 +#define AF_EBI_ADDRDAT09 11 +#define AF_EBI_ADDRDAT10 12 +#define AF_EBI_ADDRDAT11 13 +#define AF_EBI_ADDRDAT12 14 +#define AF_EBI_ADDRDAT13 15 +#define AF_EBI_ADDRDAT14 16 +#define AF_EBI_ADDRDAT15 17 +#define AF_EBI_CS0 18 +#define AF_EBI_CS1 19 +#define AF_EBI_CS2 20 +#define AF_EBI_CS3 21 +#define AF_EBI_WEn 22 +#define AF_EBI_REn 23 +#define AF_EBI_ARDY 24 +#define AF_EBI_ALE 25 +#define AF_TIMER0_CC0 26 +#define AF_TIMER0_CC1 27 +#define AF_TIMER0_CC2 28 +#define AF_TIMER0_CCC0 29 +#define AF_TIMER0_CCC1 30 +#define AF_TIMER0_CCC2 31 +#define AF_TIMER1_CC0 32 +#define AF_TIMER1_CC1 33 +#define AF_TIMER1_CC2 34 +#define AF_TIMER1_CCC0 35 +#define AF_TIMER1_CCC1 36 +#define AF_TIMER1_CCC2 37 +#define AF_TIMER2_CC0 38 +#define AF_TIMER2_CC1 39 +#define AF_TIMER2_CC2 40 +#define AF_TIMER2_CCC0 41 +#define AF_TIMER2_CCC1 42 +#define AF_TIMER2_CCC2 43 +#define AF_USART0_TX 44 +#define AF_USART0_RX 45 +#define AF_USART0_CLK 46 +#define AF_USART0_CS 47 +#define AF_USART1_TX 48 +#define AF_USART1_RX 49 +#define AF_USART1_CLK 50 +#define AF_USART1_CS 51 +#define AF_USART2_TX 52 +#define AF_USART2_RX 53 +#define AF_USART2_CLK 54 +#define AF_USART2_CS 55 +#define AF_UART0_TX 56 +#define AF_UART0_RX 57 +#define AF_UART0_CLK 58 +#define AF_UART0_CS 59 +#define AF_LEUART0_TX 60 +#define AF_LEUART0_RX 61 +#define AF_LEUART1_TX 62 +#define AF_LEUART1_RX 63 +#define AF_LETIMER0_OUT0 64 +#define AF_LETIMER0_OUT1 65 +#define AF_PCNT0_S0IN 66 +#define AF_PCNT0_S1IN 67 +#define AF_PCNT1_S0IN 68 +#define AF_PCNT1_S1IN 69 +#define AF_PCNT2_S0IN 70 +#define AF_PCNT2_S1IN 71 +#define AF_I2C0_SDA 72 +#define AF_I2C0_SCL 73 +#define AF_ACMP0_OUT 74 +#define AF_ACMP1_OUT 75 +#define AF_DBG_SWV 76 +#define AF_DBG_SWDITMS 77 +#define AF_DBG_SWCLKTCK 78 + +/** Analog AF channels */ +#define AFA_MSC_TM0 0 +#define AFA_MSC_TM1 1 +#define AFA_MSC_TM2 2 +#define AFA_ADC0_CH0 3 +#define AFA_ADC0_CH1 4 +#define AFA_ADC0_CH2 5 +#define AFA_ADC0_CH3 6 +#define AFA_ADC0_CH4 7 +#define AFA_ADC0_CH5 8 +#define AFA_ADC0_CH6 9 +#define AFA_ADC0_CH7 10 +#define AFA_ADC0_VCM 11 +#define AFA_DAC0_OUT0 12 +#define AFA_DAC0_OUT1 13 +#define AFA_ACMP0_CH0 14 +#define AFA_ACMP0_CH1 15 +#define AFA_ACMP0_CH2 16 +#define AFA_ACMP0_CH3 17 +#define AFA_ACMP0_CH4 18 +#define AFA_ACMP0_CH5 19 +#define AFA_ACMP0_CH6 20 +#define AFA_ACMP0_CH7 21 +#define AFA_ACMP1_CH0 22 +#define AFA_ACMP1_CH1 23 +#define AFA_ACMP1_CH2 24 +#define AFA_ACMP1_CH3 25 +#define AFA_ACMP1_CH4 26 +#define AFA_ACMP1_CH5 27 +#define AFA_ACMP1_CH6 28 +#define AFA_ACMP1_CH7 29 +#define AFA_LCD_BCAP_P 30 +#define AFA_LCD_BCAP_N 31 +#define AFA_LCD_BEXT 32 +#define AFA_HFXTAL_P 33 +#define AFA_HFXTAL_N 34 +#define AFA_LFXTAL_P 35 +#define AFA_LFXTAL_N 36 + +/** Digital AF */ +#define AF_TIMER_CC0(i) (i == 0 ? AF_TIMER0_CC0 : i == 1 ? AF_TIMER1_CC0 : i == 2 ? AF_TIMER2_CC0 : -1) +#define AF_UART_CLK(i) (i == 0 ? AF_UART0_CLK : -1) +#define AF_I2C_SDA(i) (i == 0 ? AF_I2C0_SDA : -1) +#define AF_TIMER_CC1(i) (i == 0 ? AF_TIMER0_CC1 : i == 1 ? AF_TIMER1_CC1 : i == 2 ? AF_TIMER2_CC1 : -1) +#define AF_USART_CS(i) (i == 0 ? AF_USART0_CS : i == 1 ? AF_USART1_CS : i == 2 ? AF_USART2_CS : -1) +#define AF_I2C_SCL(i) (i == 0 ? AF_I2C0_SCL : -1) +#define AF_TIMER_CC2(i) (i == 0 ? AF_TIMER0_CC2 : i == 1 ? AF_TIMER1_CC2 : i == 2 ? AF_TIMER2_CC2 : -1) +#define AF_USART_CLK(i) (i == 0 ? AF_USART0_CLK : i == 1 ? AF_USART1_CLK : i == 2 ? AF_USART2_CLK : -1) +#define AF_UART_RX(i) (i == 0 ? AF_UART0_RX : -1) +#define AF_UART_TX(i) (i == 0 ? AF_UART0_TX : -1) +#define AF_LETIMER_OUT1(i) (i == 0 ? AF_LETIMER0_OUT1 : -1) +#define AF_LEUART_RX(i) (i == 0 ? AF_LEUART0_RX : i == 1 ? AF_LEUART1_RX : -1) +#define AF_TIMER_CCC0(i) (i == 0 ? AF_TIMER0_CCC0 : i == 1 ? AF_TIMER1_CCC0 : i == 2 ? AF_TIMER2_CCC0 : -1) +#define AF_PCNT_S1IN(i) (i == 0 ? AF_PCNT0_S1IN : i == 1 ? AF_PCNT1_S1IN : i == 2 ? AF_PCNT2_S1IN : -1) +#define AF_LEUART_TX(i) (i == 0 ? AF_LEUART0_TX : i == 1 ? AF_LEUART1_TX : -1) +#define AF_TIMER_CCC2(i) (i == 0 ? AF_TIMER0_CCC2 : i == 1 ? AF_TIMER1_CCC2 : i == 2 ? AF_TIMER2_CCC2 : -1) +#define AF_TIMER_CCC1(i) (i == 0 ? AF_TIMER0_CCC1 : i == 1 ? AF_TIMER1_CCC1 : i == 2 ? AF_TIMER2_CCC1 : -1) +#define AF_USART_TX(i) (i == 0 ? AF_USART0_TX : i == 1 ? AF_USART1_TX : i == 2 ? AF_USART2_TX : -1) +#define AF_LETIMER_OUT0(i) (i == 0 ? AF_LETIMER0_OUT0 : -1) +#define AF_ACMP_OUT(i) (i == 0 ? AF_ACMP0_OUT : i == 1 ? AF_ACMP1_OUT : -1) +#define AF_USART_RX(i) (i == 0 ? AF_USART0_RX : i == 1 ? AF_USART1_RX : i == 2 ? AF_USART2_RX : -1) +#define AF_UART_CS(i) (i == 0 ? AF_UART0_CS : -1) +#define AF_PCNT_S0IN(i) (i == 0 ? AF_PCNT0_S0IN : i == 1 ? AF_PCNT1_S0IN : i == 2 ? AF_PCNT2_S0IN : -1) +#define AFA_DAC_OUT1(i) (i == 0 ? AFA_DAC0_OUT1 : -1) +#define AFA_DAC_OUT0(i) (i == 0 ? AFA_DAC0_OUT0 : -1) +#define AFA_ADC_CH7(i) (i == 0 ? AFA_ADC0_CH7 : -1) +#define AFA_ADC_VCM(i) (i == 0 ? AFA_ADC0_VCM : -1) +#define AFA_ACMP_CH1(i) (i == 0 ? AFA_ACMP0_CH1 : i == 1 ? AFA_ACMP1_CH1 : -1) +#define AFA_ADC_CH0(i) (i == 0 ? AFA_ADC0_CH0 : -1) +#define AFA_ACMP_CH0(i) (i == 0 ? AFA_ACMP0_CH0 : i == 1 ? AFA_ACMP1_CH0 : -1) +#define AFA_ACMP_CH3(i) (i == 0 ? AFA_ACMP0_CH3 : i == 1 ? AFA_ACMP1_CH3 : -1) +#define AFA_ADC_CH1(i) (i == 0 ? AFA_ADC0_CH1 : -1) +#define AFA_ACMP_CH2(i) (i == 0 ? AFA_ACMP0_CH2 : i == 1 ? AFA_ACMP1_CH2 : -1) +#define AFA_ADC_CH2(i) (i == 0 ? AFA_ADC0_CH2 : -1) +#define AFA_ADC_CH3(i) (i == 0 ? AFA_ADC0_CH3 : -1) +#define AFA_ADC_CH4(i) (i == 0 ? AFA_ADC0_CH4 : -1) +#define AFA_ADC_CH5(i) (i == 0 ? AFA_ADC0_CH5 : -1) +#define AFA_ADC_CH6(i) (i == 0 ? AFA_ADC0_CH6 : -1) +#define AFA_ACMP_CH5(i) (i == 0 ? AFA_ACMP0_CH5 : i == 1 ? AFA_ACMP1_CH5 : -1) +#define AFA_ACMP_CH4(i) (i == 0 ? AFA_ACMP0_CH4 : i == 1 ? AFA_ACMP1_CH4 : -1) +#define AFA_ACMP_CH7(i) (i == 0 ? AFA_ACMP0_CH7 : i == 1 ? AFA_ACMP1_CH7 : -1) +#define AFA_ACMP_CH6(i) (i == 0 ? AFA_ACMP0_CH6 : i == 1 ? AFA_ACMP1_CH6 : -1) + +/** + * @} + */ + +/**************************************************************************//** + * @defgroup EFM32G890F128_AF_Ports EFM32G890F128 AF Ports + * @{ + *****************************************************************************/ + +/** AF port for function f */ +#define AF_CMU_CLKOUT0_PORT(f) (f == 0 ? 0 : f == 1 ? 2 : -1) +#define AF_CMU_CLKOUT1_PORT(f) (f == 0 ? 0 : f == 1 ? 3 : -1) +#define AF_EBI_ADDRDAT00_PORT(f) (f == 0 ? 4 : -1) +#define AF_EBI_ADDRDAT01_PORT(f) (f == 0 ? 4 : -1) +#define AF_EBI_ADDRDAT02_PORT(f) (f == 0 ? 4 : -1) +#define AF_EBI_ADDRDAT03_PORT(f) (f == 0 ? 4 : -1) +#define AF_EBI_ADDRDAT04_PORT(f) (f == 0 ? 4 : -1) +#define AF_EBI_ADDRDAT05_PORT(f) (f == 0 ? 4 : -1) +#define AF_EBI_ADDRDAT06_PORT(f) (f == 0 ? 4 : -1) +#define AF_EBI_ADDRDAT07_PORT(f) (f == 0 ? 4 : -1) +#define AF_EBI_ADDRDAT08_PORT(f) (f == 0 ? 0 : -1) +#define AF_EBI_ADDRDAT09_PORT(f) (f == 0 ? 0 : -1) +#define AF_EBI_ADDRDAT10_PORT(f) (f == 0 ? 0 : -1) +#define AF_EBI_ADDRDAT11_PORT(f) (f == 0 ? 0 : -1) +#define AF_EBI_ADDRDAT12_PORT(f) (f == 0 ? 0 : -1) +#define AF_EBI_ADDRDAT13_PORT(f) (f == 0 ? 0 : -1) +#define AF_EBI_ADDRDAT14_PORT(f) (f == 0 ? 0 : -1) +#define AF_EBI_ADDRDAT15_PORT(f) (f == 0 ? 0 : -1) +#define AF_EBI_CS0_PORT(f) (f == 0 ? 3 : -1) +#define AF_EBI_CS1_PORT(f) (f == 0 ? 3 : -1) +#define AF_EBI_CS2_PORT(f) (f == 0 ? 3 : -1) +#define AF_EBI_CS3_PORT(f) (f == 0 ? 3 : -1) +#define AF_EBI_WEn_PORT(f) (f == 0 ? 5 : -1) +#define AF_EBI_REn_PORT(f) (f == 0 ? 5 : -1) +#define AF_EBI_ARDY_PORT(f) (f == 0 ? 5 : -1) +#define AF_EBI_ALE_PORT(f) (f == 0 ? 5 : -1) +#define AF_TIMER0_CC0_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 5 : f == 3 ? 3 : -1) +#define AF_TIMER0_CC1_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 5 : f == 3 ? 3 : -1) +#define AF_TIMER0_CC2_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 5 : f == 3 ? 3 : -1) +#define AF_TIMER0_CCC0_PORT(f) (f == 0 ? 0 : f == 1 ? 2 : f == 2 ? 5 : f == 3 ? 2 : -1) +#define AF_TIMER0_CCC1_PORT(f) (f == 0 ? 0 : f == 1 ? 2 : f == 2 ? 5 : f == 3 ? 2 : -1) +#define AF_TIMER0_CCC2_PORT(f) (f == 0 ? 0 : f == 1 ? 2 : f == 2 ? 5 : f == 3 ? 2 : -1) +#define AF_TIMER1_CC0_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 1 : -1) +#define AF_TIMER1_CC1_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 1 : -1) +#define AF_TIMER1_CC2_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 1 : -1) +#define AF_TIMER1_CCC0_PORT(f) (-1) +#define AF_TIMER1_CCC1_PORT(f) (-1) +#define AF_TIMER1_CCC2_PORT(f) (-1) +#define AF_TIMER2_CC0_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 2 : -1) +#define AF_TIMER2_CC1_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 2 : -1) +#define AF_TIMER2_CC2_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 2 : -1) +#define AF_TIMER2_CCC0_PORT(f) (-1) +#define AF_TIMER2_CCC1_PORT(f) (-1) +#define AF_TIMER2_CCC2_PORT(f) (-1) +#define AF_USART0_TX_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : f == 2 ? 2 : -1) +#define AF_USART0_RX_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : f == 2 ? 2 : -1) +#define AF_USART0_CLK_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : f == 2 ? 2 : -1) +#define AF_USART0_CS_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : f == 2 ? 2 : -1) +#define AF_USART1_TX_PORT(f) (f == 0 ? 2 : f == 1 ? 3 : -1) +#define AF_USART1_RX_PORT(f) (f == 0 ? 2 : f == 1 ? 3 : -1) +#define AF_USART1_CLK_PORT(f) (f == 0 ? 1 : f == 1 ? 3 : -1) +#define AF_USART1_CS_PORT(f) (f == 0 ? 1 : f == 1 ? 3 : -1) +#define AF_USART2_TX_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1) +#define AF_USART2_RX_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1) +#define AF_USART2_CLK_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1) +#define AF_USART2_CS_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1) +#define AF_UART0_TX_PORT(f) (f == 0 ? 5 : f == 1 ? 4 : f == 2 ? 0 : f == 3 ? 2 : -1) +#define AF_UART0_RX_PORT(f) (f == 0 ? 5 : f == 1 ? 4 : f == 2 ? 0 : f == 3 ? 2 : -1) +#define AF_UART0_CLK_PORT(f) (-1) +#define AF_UART0_CS_PORT(f) (-1) +#define AF_LEUART0_TX_PORT(f) (f == 0 ? 3 : f == 1 ? 1 : f == 2 ? 4 : -1) +#define AF_LEUART0_RX_PORT(f) (f == 0 ? 3 : f == 1 ? 1 : f == 2 ? 4 : -1) +#define AF_LEUART1_TX_PORT(f) (f == 0 ? 2 : f == 1 ? 0 : -1) +#define AF_LEUART1_RX_PORT(f) (f == 0 ? 2 : f == 1 ? 0 : -1) +#define AF_LETIMER0_OUT0_PORT(f) (f == 0 ? 3 : f == 1 ? 1 : f == 2 ? 5 : f == 3 ? 2 : -1) +#define AF_LETIMER0_OUT1_PORT(f) (f == 0 ? 3 : f == 1 ? 1 : f == 2 ? 5 : f == 3 ? 2 : -1) +#define AF_PCNT0_S0IN_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 2 : -1) +#define AF_PCNT0_S1IN_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 2 : -1) +#define AF_PCNT1_S0IN_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1) +#define AF_PCNT1_S1IN_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1) +#define AF_PCNT2_S0IN_PORT(f) (f == 0 ? 3 : f == 1 ? 4 : -1) +#define AF_PCNT2_S1IN_PORT(f) (f == 0 ? 3 : f == 1 ? 4 : -1) +#define AF_I2C0_SDA_PORT(f) (f == 0 ? 0 : f == 1 ? 3 : f == 2 ? 2 : f == 3 ? 3 : -1) +#define AF_I2C0_SCL_PORT(f) (f == 0 ? 0 : f == 1 ? 3 : f == 2 ? 2 : f == 3 ? 3 : -1) +#define AF_ACMP0_OUT_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : -1) +#define AF_ACMP1_OUT_PORT(f) (f == 0 ? 5 : f == 1 ? 4 : -1) +#define AF_DBG_SWV_PORT(f) (f == 0 ? 5 : f == 1 ? 2 : -1) +#define AF_DBG_SWDITMS_PORT(f) (f == 0 ? 5 : f == 1 ? 5 : -1) +#define AF_DBG_SWCLKTCK_PORT(f) (f == 0 ? 5 : f == 1 ? 5 : -1) + +/** + * @} + */ + +/**************************************************************************//** + * @defgroup EFM32G890F128_AF_Pins EFM32G890F128 AF Pins + * @{ + *****************************************************************************/ + +/** AF pin for function f */ +#define AF_CMU_CLKOUT0_PIN(f) (f == 0 ? 2 : f == 1 ? 12 : -1) +#define AF_CMU_CLKOUT1_PIN(f) (f == 0 ? 1 : f == 1 ? 8 : -1) +#define AF_EBI_ADDRDAT00_PIN(f) (f == 0 ? 8 : -1) +#define AF_EBI_ADDRDAT01_PIN(f) (f == 0 ? 9 : -1) +#define AF_EBI_ADDRDAT02_PIN(f) (f == 0 ? 10 : -1) +#define AF_EBI_ADDRDAT03_PIN(f) (f == 0 ? 11 : -1) +#define AF_EBI_ADDRDAT04_PIN(f) (f == 0 ? 12 : -1) +#define AF_EBI_ADDRDAT05_PIN(f) (f == 0 ? 13 : -1) +#define AF_EBI_ADDRDAT06_PIN(f) (f == 0 ? 14 : -1) +#define AF_EBI_ADDRDAT07_PIN(f) (f == 0 ? 15 : -1) +#define AF_EBI_ADDRDAT08_PIN(f) (f == 0 ? 15 : -1) +#define AF_EBI_ADDRDAT09_PIN(f) (f == 0 ? 0 : -1) +#define AF_EBI_ADDRDAT10_PIN(f) (f == 0 ? 1 : -1) +#define AF_EBI_ADDRDAT11_PIN(f) (f == 0 ? 2 : -1) +#define AF_EBI_ADDRDAT12_PIN(f) (f == 0 ? 3 : -1) +#define AF_EBI_ADDRDAT13_PIN(f) (f == 0 ? 4 : -1) +#define AF_EBI_ADDRDAT14_PIN(f) (f == 0 ? 5 : -1) +#define AF_EBI_ADDRDAT15_PIN(f) (f == 0 ? 6 : -1) +#define AF_EBI_CS0_PIN(f) (f == 0 ? 9 : -1) +#define AF_EBI_CS1_PIN(f) (f == 0 ? 10 : -1) +#define AF_EBI_CS2_PIN(f) (f == 0 ? 11 : -1) +#define AF_EBI_CS3_PIN(f) (f == 0 ? 12 : -1) +#define AF_EBI_WEn_PIN(f) (f == 0 ? 4 : -1) +#define AF_EBI_REn_PIN(f) (f == 0 ? 5 : -1) +#define AF_EBI_ARDY_PIN(f) (f == 0 ? 2 : -1) +#define AF_EBI_ALE_PIN(f) (f == 0 ? 3 : -1) +#define AF_TIMER0_CC0_PIN(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 6 : f == 3 ? 1 : -1) +#define AF_TIMER0_CC1_PIN(f) (f == 0 ? 1 : f == 1 ? 1 : f == 2 ? 7 : f == 3 ? 2 : -1) +#define AF_TIMER0_CC2_PIN(f) (f == 0 ? 2 : f == 1 ? 2 : f == 2 ? 8 : f == 3 ? 3 : -1) +#define AF_TIMER0_CCC0_PIN(f) (f == 0 ? 3 : f == 1 ? 13 : f == 2 ? 3 : f == 3 ? 13 : -1) +#define AF_TIMER0_CCC1_PIN(f) (f == 0 ? 4 : f == 1 ? 14 : f == 2 ? 4 : f == 3 ? 14 : -1) +#define AF_TIMER0_CCC2_PIN(f) (f == 0 ? 5 : f == 1 ? 15 : f == 2 ? 5 : f == 3 ? 15 : -1) +#define AF_TIMER1_CC0_PIN(f) (f == 0 ? 13 : f == 1 ? 10 : f == 2 ? 0 : -1) +#define AF_TIMER1_CC1_PIN(f) (f == 0 ? 14 : f == 1 ? 11 : f == 2 ? 1 : -1) +#define AF_TIMER1_CC2_PIN(f) (f == 0 ? 15 : f == 1 ? 12 : f == 2 ? 2 : -1) +#define AF_TIMER1_CCC0_PIN(f) (-1) +#define AF_TIMER1_CCC1_PIN(f) (-1) +#define AF_TIMER1_CCC2_PIN(f) (-1) +#define AF_TIMER2_CC0_PIN(f) (f == 0 ? 8 : f == 1 ? 12 : f == 2 ? 8 : -1) +#define AF_TIMER2_CC1_PIN(f) (f == 0 ? 9 : f == 1 ? 13 : f == 2 ? 9 : -1) +#define AF_TIMER2_CC2_PIN(f) (f == 0 ? 10 : f == 1 ? 14 : f == 2 ? 10 : -1) +#define AF_TIMER2_CCC0_PIN(f) (-1) +#define AF_TIMER2_CCC1_PIN(f) (-1) +#define AF_TIMER2_CCC2_PIN(f) (-1) +#define AF_USART0_TX_PIN(f) (f == 0 ? 10 : f == 1 ? 7 : f == 2 ? 11 : -1) +#define AF_USART0_RX_PIN(f) (f == 0 ? 11 : f == 1 ? 6 : f == 2 ? 10 : -1) +#define AF_USART0_CLK_PIN(f) (f == 0 ? 12 : f == 1 ? 5 : f == 2 ? 9 : -1) +#define AF_USART0_CS_PIN(f) (f == 0 ? 13 : f == 1 ? 4 : f == 2 ? 8 : -1) +#define AF_USART1_TX_PIN(f) (f == 0 ? 0 : f == 1 ? 0 : -1) +#define AF_USART1_RX_PIN(f) (f == 0 ? 1 : f == 1 ? 1 : -1) +#define AF_USART1_CLK_PIN(f) (f == 0 ? 7 : f == 1 ? 2 : -1) +#define AF_USART1_CS_PIN(f) (f == 0 ? 8 : f == 1 ? 3 : -1) +#define AF_USART2_TX_PIN(f) (f == 0 ? 2 : f == 1 ? 3 : -1) +#define AF_USART2_RX_PIN(f) (f == 0 ? 3 : f == 1 ? 4 : -1) +#define AF_USART2_CLK_PIN(f) (f == 0 ? 4 : f == 1 ? 5 : -1) +#define AF_USART2_CS_PIN(f) (f == 0 ? 5 : f == 1 ? 6 : -1) +#define AF_UART0_TX_PIN(f) (f == 0 ? 6 : f == 1 ? 0 : f == 2 ? 3 : f == 3 ? 14 : -1) +#define AF_UART0_RX_PIN(f) (f == 0 ? 7 : f == 1 ? 1 : f == 2 ? 4 : f == 3 ? 15 : -1) +#define AF_UART0_CLK_PIN(f) (-1) +#define AF_UART0_CS_PIN(f) (-1) +#define AF_LEUART0_TX_PIN(f) (f == 0 ? 4 : f == 1 ? 13 : f == 2 ? 14 : -1) +#define AF_LEUART0_RX_PIN(f) (f == 0 ? 5 : f == 1 ? 14 : f == 2 ? 15 : -1) +#define AF_LEUART1_TX_PIN(f) (f == 0 ? 6 : f == 1 ? 5 : -1) +#define AF_LEUART1_RX_PIN(f) (f == 0 ? 7 : f == 1 ? 6 : -1) +#define AF_LETIMER0_OUT0_PIN(f) (f == 0 ? 6 : f == 1 ? 11 : f == 2 ? 0 : f == 3 ? 4 : -1) +#define AF_LETIMER0_OUT1_PIN(f) (f == 0 ? 7 : f == 1 ? 12 : f == 2 ? 1 : f == 3 ? 5 : -1) +#define AF_PCNT0_S0IN_PIN(f) (f == 0 ? 13 : f == 1 ? 0 : f == 2 ? 0 : -1) +#define AF_PCNT0_S1IN_PIN(f) (f == 0 ? 14 : f == 1 ? 1 : f == 2 ? 1 : -1) +#define AF_PCNT1_S0IN_PIN(f) (f == 0 ? 4 : f == 1 ? 3 : -1) +#define AF_PCNT1_S1IN_PIN(f) (f == 0 ? 5 : f == 1 ? 4 : -1) +#define AF_PCNT2_S0IN_PIN(f) (f == 0 ? 0 : f == 1 ? 8 : -1) +#define AF_PCNT2_S1IN_PIN(f) (f == 0 ? 1 : f == 1 ? 9 : -1) +#define AF_I2C0_SDA_PIN(f) (f == 0 ? 0 : f == 1 ? 6 : f == 2 ? 6 : f == 3 ? 14 : -1) +#define AF_I2C0_SCL_PIN(f) (f == 0 ? 1 : f == 1 ? 7 : f == 2 ? 7 : f == 3 ? 15 : -1) +#define AF_ACMP0_OUT_PIN(f) (f == 0 ? 13 : f == 1 ? 2 : -1) +#define AF_ACMP1_OUT_PIN(f) (f == 0 ? 2 : f == 1 ? 3 : -1) +#define AF_DBG_SWV_PIN(f) (f == 0 ? 2 : f == 1 ? 15 : -1) +#define AF_DBG_SWDITMS_PIN(f) (f == 0 ? 1 : f == 1 ? 1 : -1) +#define AF_DBG_SWCLKTCK_PIN(f) (f == 0 ? 0 : f == 1 ? 0 : -1) + +/** + * @} + */ + +/** Grouped by channel c, function f */ +#define AF_PORT(c, f) ( \ + c == 0 ? AF_CMU_CLKOUT0_PORT(f) : \ + c == 1 ? AF_CMU_CLKOUT1_PORT(f) : \ + c == 2 ? AF_EBI_ADDRDAT00_PORT(f) : \ + c == 3 ? AF_EBI_ADDRDAT01_PORT(f) : \ + c == 4 ? AF_EBI_ADDRDAT02_PORT(f) : \ + c == 5 ? AF_EBI_ADDRDAT03_PORT(f) : \ + c == 6 ? AF_EBI_ADDRDAT04_PORT(f) : \ + c == 7 ? AF_EBI_ADDRDAT05_PORT(f) : \ + c == 8 ? AF_EBI_ADDRDAT06_PORT(f) : \ + c == 9 ? AF_EBI_ADDRDAT07_PORT(f) : \ + c == 10 ? AF_EBI_ADDRDAT08_PORT(f) : \ + c == 11 ? AF_EBI_ADDRDAT09_PORT(f) : \ + c == 12 ? AF_EBI_ADDRDAT10_PORT(f) : \ + c == 13 ? AF_EBI_ADDRDAT11_PORT(f) : \ + c == 14 ? AF_EBI_ADDRDAT12_PORT(f) : \ + c == 15 ? AF_EBI_ADDRDAT13_PORT(f) : \ + c == 16 ? AF_EBI_ADDRDAT14_PORT(f) : \ + c == 17 ? AF_EBI_ADDRDAT15_PORT(f) : \ + c == 18 ? AF_EBI_CS0_PORT(f) : \ + c == 19 ? AF_EBI_CS1_PORT(f) : \ + c == 20 ? AF_EBI_CS2_PORT(f) : \ + c == 21 ? AF_EBI_CS3_PORT(f) : \ + c == 22 ? AF_EBI_WEn_PORT(f) : \ + c == 23 ? AF_EBI_REn_PORT(f) : \ + c == 24 ? AF_EBI_ARDY_PORT(f) : \ + c == 25 ? AF_EBI_ALE_PORT(f) : \ + c == 26 ? AF_TIMER0_CC0_PORT(f) : \ + c == 27 ? AF_TIMER0_CC1_PORT(f) : \ + c == 28 ? AF_TIMER0_CC2_PORT(f) : \ + c == 29 ? AF_TIMER0_CCC0_PORT(f) : \ + c == 30 ? AF_TIMER0_CCC1_PORT(f) : \ + c == 31 ? AF_TIMER0_CCC2_PORT(f) : \ + c == 32 ? AF_TIMER1_CC0_PORT(f) : \ + c == 33 ? AF_TIMER1_CC1_PORT(f) : \ + c == 34 ? AF_TIMER1_CC2_PORT(f) : \ + c == 35 ? AF_TIMER1_CCC0_PORT(f) : \ + c == 36 ? AF_TIMER1_CCC1_PORT(f) : \ + c == 37 ? AF_TIMER1_CCC2_PORT(f) : \ + c == 38 ? AF_TIMER2_CC0_PORT(f) : \ + c == 39 ? AF_TIMER2_CC1_PORT(f) : \ + c == 40 ? AF_TIMER2_CC2_PORT(f) : \ + c == 41 ? AF_TIMER2_CCC0_PORT(f) : \ + c == 42 ? AF_TIMER2_CCC1_PORT(f) : \ + c == 43 ? AF_TIMER2_CCC2_PORT(f) : \ + c == 44 ? AF_USART0_TX_PORT(f) : \ + c == 45 ? AF_USART0_RX_PORT(f) : \ + c == 46 ? AF_USART0_CLK_PORT(f) : \ + c == 47 ? AF_USART0_CS_PORT(f) : \ + c == 48 ? AF_USART1_TX_PORT(f) : \ + c == 49 ? AF_USART1_RX_PORT(f) : \ + c == 50 ? AF_USART1_CLK_PORT(f) : \ + c == 51 ? AF_USART1_CS_PORT(f) : \ + c == 52 ? AF_USART2_TX_PORT(f) : \ + c == 53 ? AF_USART2_RX_PORT(f) : \ + c == 54 ? AF_USART2_CLK_PORT(f) : \ + c == 55 ? AF_USART2_CS_PORT(f) : \ + c == 56 ? AF_UART0_TX_PORT(f) : \ + c == 57 ? AF_UART0_RX_PORT(f) : \ + c == 58 ? AF_UART0_CLK_PORT(f) : \ + c == 59 ? AF_UART0_CS_PORT(f) : \ + c == 60 ? AF_LEUART0_TX_PORT(f) : \ + c == 61 ? AF_LEUART0_RX_PORT(f) : \ + c == 62 ? AF_LEUART1_TX_PORT(f) : \ + c == 63 ? AF_LEUART1_RX_PORT(f) : \ + c == 64 ? AF_LETIMER0_OUT0_PORT(f) : \ + c == 65 ? AF_LETIMER0_OUT1_PORT(f) : \ + c == 66 ? AF_PCNT0_S0IN_PORT(f) : \ + c == 67 ? AF_PCNT0_S1IN_PORT(f) : \ + c == 68 ? AF_PCNT1_S0IN_PORT(f) : \ + c == 69 ? AF_PCNT1_S1IN_PORT(f) : \ + c == 70 ? AF_PCNT2_S0IN_PORT(f) : \ + c == 71 ? AF_PCNT2_S1IN_PORT(f) : \ + c == 72 ? AF_I2C0_SDA_PORT(f) : \ + c == 73 ? AF_I2C0_SCL_PORT(f) : \ + c == 74 ? AF_ACMP0_OUT_PORT(f) : \ + c == 75 ? AF_ACMP1_OUT_PORT(f) : \ + c == 76 ? AF_DBG_SWV_PORT(f) : \ + c == 77 ? AF_DBG_SWDITMS_PORT(f) : \ + c == 78 ? AF_DBG_SWCLKTCK_PORT(f) : \ + -1) + +#define AF_PIN(c, f) ( \ + c == 0 ? AF_CMU_CLKOUT0_PIN(f) : \ + c == 1 ? AF_CMU_CLKOUT1_PIN(f) : \ + c == 2 ? AF_EBI_ADDRDAT00_PIN(f) : \ + c == 3 ? AF_EBI_ADDRDAT01_PIN(f) : \ + c == 4 ? AF_EBI_ADDRDAT02_PIN(f) : \ + c == 5 ? AF_EBI_ADDRDAT03_PIN(f) : \ + c == 6 ? AF_EBI_ADDRDAT04_PIN(f) : \ + c == 7 ? AF_EBI_ADDRDAT05_PIN(f) : \ + c == 8 ? AF_EBI_ADDRDAT06_PIN(f) : \ + c == 9 ? AF_EBI_ADDRDAT07_PIN(f) : \ + c == 10 ? AF_EBI_ADDRDAT08_PIN(f) : \ + c == 11 ? AF_EBI_ADDRDAT09_PIN(f) : \ + c == 12 ? AF_EBI_ADDRDAT10_PIN(f) : \ + c == 13 ? AF_EBI_ADDRDAT11_PIN(f) : \ + c == 14 ? AF_EBI_ADDRDAT12_PIN(f) : \ + c == 15 ? AF_EBI_ADDRDAT13_PIN(f) : \ + c == 16 ? AF_EBI_ADDRDAT14_PIN(f) : \ + c == 17 ? AF_EBI_ADDRDAT15_PIN(f) : \ + c == 18 ? AF_EBI_CS0_PIN(f) : \ + c == 19 ? AF_EBI_CS1_PIN(f) : \ + c == 20 ? AF_EBI_CS2_PIN(f) : \ + c == 21 ? AF_EBI_CS3_PIN(f) : \ + c == 22 ? AF_EBI_WEn_PIN(f) : \ + c == 23 ? AF_EBI_REn_PIN(f) : \ + c == 24 ? AF_EBI_ARDY_PIN(f) : \ + c == 25 ? AF_EBI_ALE_PIN(f) : \ + c == 26 ? AF_TIMER0_CC0_PIN(f) : \ + c == 27 ? AF_TIMER0_CC1_PIN(f) : \ + c == 28 ? AF_TIMER0_CC2_PIN(f) : \ + c == 29 ? AF_TIMER0_CCC0_PIN(f) : \ + c == 30 ? AF_TIMER0_CCC1_PIN(f) : \ + c == 31 ? AF_TIMER0_CCC2_PIN(f) : \ + c == 32 ? AF_TIMER1_CC0_PIN(f) : \ + c == 33 ? AF_TIMER1_CC1_PIN(f) : \ + c == 34 ? AF_TIMER1_CC2_PIN(f) : \ + c == 35 ? AF_TIMER1_CCC0_PIN(f) : \ + c == 36 ? AF_TIMER1_CCC1_PIN(f) : \ + c == 37 ? AF_TIMER1_CCC2_PIN(f) : \ + c == 38 ? AF_TIMER2_CC0_PIN(f) : \ + c == 39 ? AF_TIMER2_CC1_PIN(f) : \ + c == 40 ? AF_TIMER2_CC2_PIN(f) : \ + c == 41 ? AF_TIMER2_CCC0_PIN(f) : \ + c == 42 ? AF_TIMER2_CCC1_PIN(f) : \ + c == 43 ? AF_TIMER2_CCC2_PIN(f) : \ + c == 44 ? AF_USART0_TX_PIN(f) : \ + c == 45 ? AF_USART0_RX_PIN(f) : \ + c == 46 ? AF_USART0_CLK_PIN(f) : \ + c == 47 ? AF_USART0_CS_PIN(f) : \ + c == 48 ? AF_USART1_TX_PIN(f) : \ + c == 49 ? AF_USART1_RX_PIN(f) : \ + c == 50 ? AF_USART1_CLK_PIN(f) : \ + c == 51 ? AF_USART1_CS_PIN(f) : \ + c == 52 ? AF_USART2_TX_PIN(f) : \ + c == 53 ? AF_USART2_RX_PIN(f) : \ + c == 54 ? AF_USART2_CLK_PIN(f) : \ + c == 55 ? AF_USART2_CS_PIN(f) : \ + c == 56 ? AF_UART0_TX_PIN(f) : \ + c == 57 ? AF_UART0_RX_PIN(f) : \ + c == 58 ? AF_UART0_CLK_PIN(f) : \ + c == 59 ? AF_UART0_CS_PIN(f) : \ + c == 60 ? AF_LEUART0_TX_PIN(f) : \ + c == 61 ? AF_LEUART0_RX_PIN(f) : \ + c == 62 ? AF_LEUART1_TX_PIN(f) : \ + c == 63 ? AF_LEUART1_RX_PIN(f) : \ + c == 64 ? AF_LETIMER0_OUT0_PIN(f) : \ + c == 65 ? AF_LETIMER0_OUT1_PIN(f) : \ + c == 66 ? AF_PCNT0_S0IN_PIN(f) : \ + c == 67 ? AF_PCNT0_S1IN_PIN(f) : \ + c == 68 ? AF_PCNT1_S0IN_PIN(f) : \ + c == 69 ? AF_PCNT1_S1IN_PIN(f) : \ + c == 70 ? AF_PCNT2_S0IN_PIN(f) : \ + c == 71 ? AF_PCNT2_S1IN_PIN(f) : \ + c == 72 ? AF_I2C0_SDA_PIN(f) : \ + c == 73 ? AF_I2C0_SCL_PIN(f) : \ + c == 74 ? AF_ACMP0_OUT_PIN(f) : \ + c == 75 ? AF_ACMP1_OUT_PIN(f) : \ + c == 76 ? AF_DBG_SWV_PIN(f) : \ + c == 77 ? AF_DBG_SWDITMS_PIN(f) : \ + c == 78 ? AF_DBG_SWCLKTCK_PIN(f) : \ + -1) + +/** AF channel output count for channel c */ +#define AF_COUNT(c) ( \ + c == 0 ? 2 : \ + c == 1 ? 2 : \ + c == 2 ? 1 : \ + c == 3 ? 1 : \ + c == 4 ? 1 : \ + c == 5 ? 1 : \ + c == 6 ? 1 : \ + c == 7 ? 1 : \ + c == 8 ? 1 : \ + c == 9 ? 1 : \ + c == 10 ? 1 : \ + c == 11 ? 1 : \ + c == 12 ? 1 : \ + c == 13 ? 1 : \ + c == 14 ? 1 : \ + c == 15 ? 1 : \ + c == 16 ? 1 : \ + c == 17 ? 1 : \ + c == 18 ? 1 : \ + c == 19 ? 1 : \ + c == 20 ? 1 : \ + c == 21 ? 1 : \ + c == 22 ? 1 : \ + c == 23 ? 1 : \ + c == 24 ? 1 : \ + c == 25 ? 1 : \ + c == 26 ? 4 : \ + c == 27 ? 4 : \ + c == 28 ? 4 : \ + c == 29 ? 4 : \ + c == 30 ? 4 : \ + c == 31 ? 4 : \ + c == 32 ? 3 : \ + c == 33 ? 3 : \ + c == 34 ? 3 : \ + c == 35 ? 0 : \ + c == 36 ? 0 : \ + c == 37 ? 0 : \ + c == 38 ? 3 : \ + c == 39 ? 3 : \ + c == 40 ? 3 : \ + c == 41 ? 0 : \ + c == 42 ? 0 : \ + c == 43 ? 0 : \ + c == 44 ? 3 : \ + c == 45 ? 3 : \ + c == 46 ? 3 : \ + c == 47 ? 3 : \ + c == 48 ? 2 : \ + c == 49 ? 2 : \ + c == 50 ? 2 : \ + c == 51 ? 2 : \ + c == 52 ? 2 : \ + c == 53 ? 2 : \ + c == 54 ? 2 : \ + c == 55 ? 2 : \ + c == 56 ? 4 : \ + c == 57 ? 4 : \ + c == 58 ? 0 : \ + c == 59 ? 0 : \ + c == 60 ? 3 : \ + c == 61 ? 3 : \ + c == 62 ? 2 : \ + c == 63 ? 2 : \ + c == 64 ? 4 : \ + c == 65 ? 4 : \ + c == 66 ? 3 : \ + c == 67 ? 3 : \ + c == 68 ? 2 : \ + c == 69 ? 2 : \ + c == 70 ? 2 : \ + c == 71 ? 2 : \ + c == 72 ? 4 : \ + c == 73 ? 4 : \ + c == 74 ? 2 : \ + c == 75 ? 2 : \ + c == 76 ? 2 : \ + c == 77 ? 2 : \ + c == 78 ? 2 : \ + -1) + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @brief Set the value of a bit field within a register. + * + * @param REG + * The register to update + * @param MASK + * The mask for the bit field to update + * @param VALUE + * The value to write to the bit field + * @param OFFSET + * The number of bits that the field is offset within the register. + * 0 (zero) means LSB. + */ +#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ + REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); + +/** + * @} + */ + +/** + * @} + */ diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c new file mode 100644 index 000000000..a5bbf09e6 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c @@ -0,0 +1,126 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 devices + * + * @author Energy Micro AS + * @version 1.0.2 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#include +#include "efm32.h" + +uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ + +#ifndef EFM32_HFXO_FREQ +#define EFM32_HFXO_FREQ 32000000 +#endif +#ifndef EFM32_LFXO_FREQ +#define EFM32_LFXO_FREQ 32768 +#endif +#ifndef EFM32_LFRCO_FREQ +#define EFM32_LFRCO_FREQ 32768 +#endif + +/**************************************************************************//** + * @brief Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + *****************************************************************************/ +void SystemInit(void) +{ +#if EFM32_AUXHFROCO_ENABLE + CMU_TypeDef *cmu = CMU; + + /* Enable clocks to debug modules in Cortex */ + /* This will enable Debug Trace and MSC Flash programming clocks */ + cmu->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN; +#endif +} + +/**************************************************************************//** + * @brief Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + *****************************************************************************/ +void SystemCoreClockUpdate(void) +{ + CMU_TypeDef *cmu = CMU; + uint32_t inputClock; + + /* Check source for core clock */ + switch (cmu->STATUS & + (CMU_STATUS_HFRCOSEL | + CMU_STATUS_HFXOSEL | + CMU_STATUS_LFRCOSEL | + CMU_STATUS_LFXOSEL)) + { + case CMU_STATUS_HFXOSEL: + inputClock = EFM32_HFXO_FREQ; + break; + case CMU_STATUS_LFRCOSEL: + inputClock = EFM32_LFRCO_FREQ; + break; + case CMU_STATUS_LFXOSEL: + inputClock = EFM32_LFXO_FREQ; + break; + case CMU_STATUS_HFRCOSEL: + default: + switch ((cmu->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) >> _CMU_HFRCOCTRL_BAND_SHIFT) + { + case _CMU_HFRCOCTRL_BAND_28MHZ: + inputClock = 28000000; + break; + case _CMU_HFRCOCTRL_BAND_21MHZ: + inputClock = 21000000; + break; + case _CMU_HFRCOCTRL_BAND_14MHZ: + inputClock = 14000000; + break; + case _CMU_HFRCOCTRL_BAND_11MHZ: + inputClock = 11000000; + break; + case _CMU_HFRCOCTRL_BAND_7MHZ: + inputClock = 7000000; + break; + case _CMU_HFRCOCTRL_BAND_1MHZ: + inputClock = 1500000; + break; + default: + inputClock = 0; + break; + } + break; + } + /* Adjust according to clock divisor */ + SystemCoreClock = inputClock / (1<<((cmu->HFCORECLKDIV & _CMU_HFCORECLKDIV_MASK)>>_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT)); +} + diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.h b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.h new file mode 100644 index 000000000..5421f5dca --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.h @@ -0,0 +1,69 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 devices + * + * @author Energy Micro AS + * @version 1.0.2 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef __SYSTEM_EFM32_H +#define __SYSTEM_EFM32_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ + +/**************************************************************************//** + * @brief Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + *****************************************************************************/ +extern void SystemInit(void); + +/**************************************************************************//** + * @brief Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + *****************************************************************************/ +extern void SystemCoreClockUpdate(void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CMSIS changes.htm b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CMSIS changes.htm new file mode 100644 index 000000000..162ffcc9d --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CMSIS changes.htm @@ -0,0 +1,320 @@ + + + +CMSIS Changes + + + + + + + + +

Changes to CMSIS version V1.20

+ +
+ +

1. Removed CMSIS Middelware packages

+

+ CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found. +

+ +

2. SystemFrequency renamed to SystemCoreClock

+

+ The variable name SystemCoreClock is more precise than SystemFrequency + because the variable holds the clock value at which the core is running. +

+ +

3. Changed startup concept

+

+ The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit + from main) has the weakness that it does not work for controllers which need a already + configuerd clock system to configure the external memory controller. +

+ +

Changed startup concept

+
    +
  • + SystemInit() is called from startup file before premain. +
    • +
  • + SystemInit() configures the clock system and also configures + an existing external memory controller. +
    • +
  • + SystemInit() must not use global variables. +
    • +
  • + SystemCoreClock is initialized with a correct predefined value. +
    • +
  • + Additional function void SystemCoreClockUpdate (void) is provided.
    + SystemCoreClockUpdate() updates the variable SystemCoreClock + and must be called whenever the core clock is changed.
    + SystemCoreClockUpdate() evaluates the clock register settings and calculates + the current core clock. +
    • +
+ + +

4. Advanced Debug Functions

+

+ ITM communication channel is only capable for OUT direction. To allow also communication for + IN direction a simple concept is provided. +

+
    +
  • + Global variable volatile int ITM_RxBuffer used for IN data. +
    • +
  • + Function int ITM_CheckChar (void) checks if a new character is available. +
    • +
  • + Function int ITM_ReceiveChar (void) retrieves the new character. +
    • +
+ +

+ For detailed explanation see file CMSIS debug support.htm. +

+ + +

5. Core Register Bit Definitions

+

+ Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the + defines correspond with the Cortex-M Technical Reference Manual. +

+

+ e.g. SysTick structure with bit definitions +

+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+  memory mapped structure for SysTick
+  @{
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+ +

7. DoxyGen Tags

+

+ DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation + using DoxyGen. +

+ +

8. Folder Structure

+

+ The folder structure is changed to differentiate the single support packages. +

+ +
    +
  • CM0
    • +
  • CM3 +
      +
    • CoreSupport
      • +
    • DeviceSupport
      • +
        +
      • Vendor +
          +
        • Device +
            +
          • Startup +
              +
            • Toolchain
              • +
            • Toolchain
              • +
            • ...
              • +
            +
            • +
          +
          • +
        • Device
          • +
        • ...
          • +
        +
        • +
      • Vendor
        • +
      • ...
        • +
      + +
    • Example +
        +
      • Toolchain +
          +
        • Device
          • +
        • Device
          • +
        • ...
          • +
        +
        • +
      • Toolchain
        • +
      • ...
        • +
      +
      • +
    +
    • + +
  • Documentation
    • +
+ +

9. Open Points

+

+ Following points need to be clarified and solved: +

+
    +
  • +

    + Equivalent C and Assembler startup files. +

    +

    + Is there a need for having C startup files although assembler startup files are + very efficient and do not need to be changed? +

    +

    • +
  • +

    + Placing of HEAP in external RAM. +

    +

    + It must be possible to place HEAP in external RAM if the device supports an + external memory controller. +

    +
    • +
  • +

    + Placing of STACK /HEAP. +

    +

    + STACK should always be placed at the end of internal RAM. +

    +

    + If HEAP is placed in internal RAM than it should be placed after RW ZI section. +

    +
    • +
  • +

    + Removing core_cm3.c and core_cm0.c. +

    +

    + On a long term the functions in core_cm3.c and core_cm0.c must be replaced with + appropriate compiler intrinsics. +

    +
    • +
+ + +

10. Limitations

+

+ The following limitations are not covered with the current CMSIS version: +

+
    +
  • + No C startup files for ARM toolchain are provided. +
    • +
  • + No C startup files for GNU toolchain are provided. +
    • +
  • + No C startup files for IAR toolchain are provided. +
    • +
  • + No Tasking projects are provided yet. +
    • +
diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CMSIS debug support.htm b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CMSIS debug support.htm new file mode 100644 index 000000000..efda685be --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CMSIS debug support.htm @@ -0,0 +1,243 @@ + + + +CMSIS Debug Support + + + + + + + + +

CMSIS Debug Support

+ +
+ +

Cortex-M3 ITM Debug Access

+

+ The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with + the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has + 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM + communication channels are used by CMSIS to output the following information: +

+
    +
  • ITM Channel 0: used for printf-style output via the debug interface.
    • +
  • ITM Channel 31: is reserved for RTOS kernel awareness debugging.
    • +
+ +

Debug IN / OUT functions

+

CMSIS provides following debug functions:

+
    +
  • ITM_SendChar (uses ITM channel 0)
    • +
  • ITM_ReceiveChar (uses global variable)
    • +
  • ITM_CheckChar (uses global variable)
    • +
+ +

ITM_SendChar

+

+ ITM_SendChar is used to transmit a character over ITM channel 0 from + the microcontroller system to the debug system.
+ Only a 8 bit value is transmitted. +

+
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  /* check if debugger connected and ITM channel enabled for tracing */
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
+      (ITM->TCR & ITM_TCR_ITMENA)                  &&
+      (ITM->TER & (1UL << 0))  ) 
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }  
+  return (ch);
+}
+ +

ITM_ReceiveChar

+

+ ITM communication channel is only capable for OUT direction. For IN direction + a globel variable is used. A simple mechansim detects if a character is received. + The project to test need to be build with debug information. +

+ +

+ The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system + to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake. +

+
+extern volatile int ITM_RxBuffer;                    /* variable to receive characters                             */
+
+

+ A dedicated bit pattern is used to determin if ITM_RxBuffer is empty + or contains a valid value. +

+
+#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
+
+

+ ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking. + It returns the received character or '-1' if no character was available. +

+
+static __INLINE int ITM_ReceiveChar (void) {
+  int ch = -1;                               /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+  
+  return (ch); 
+}
+
+ +

ITM_CheckChar

+

+ ITM_CheckChar is used to check if a character is received. +

+
+static __INLINE int ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+ + +

ITM Debug Support in uVision

+

+ uVision uses in a debug session the Debug (printf) Viewer window to + display the debug data. +

+

Direction microcontroller system -> uVision:

+
    +
  • + Characters received via ITM communication channel 0 are written in a printf style + to Debug (printf) Viewer window. +
    • +
+ +

Direction uVision -> microcontroller system:

+
    +
  • Check if ITM_RxBuffer variable is available (only performed once).
    • +
  • Read character from Debug (printf) Viewer window.
    • +
  • If ITM_RxBuffer empty write character to ITM_RxBuffer.
    • +
+ +

Note

+
    +

  • Current solution does not use a buffer machanism for trasmitting the characters.

    +
    • +
+ +

RTX Kernel awareness in uVision

+

+ uVision / RTX are using a simple and efficient solution for RTX Kernel awareness. + No format overhead is necessary.
+ uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access + to ITM communication channel 31. +

+ +

Following RTX events are traced:

+
    +
  • Task Create / Delete event +
      +
    1. 32 bit access. Task start address is transmitted
      2. +
    2. 16 bit access. Task ID and Create/Delete flag are transmitted
      + High byte holds Create/Delete flag, Low byte holds TASK ID. +
      3. +
    +
    • +
  • Task switch event +
      +
    1. 8 bit access. Task ID of current task is transmitted
      2. +
    +
    • +
+ +

Note

+
    +

  • Other RTOS information could be retrieved via memory read access in a polling mode manner.

    +
    • +
+ + +

 

+ +
+ +

Copyright © KEIL - An ARM Company.
+All rights reserved.
+Visit our web site at www.keil.com. +

+ + + + \ No newline at end of file diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/Documentation/CMSIS_Core.htm b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/Documentation/CMSIS_Core.htm new file mode 100644 index 000000000..6fd131e12 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/Documentation/CMSIS_Core.htm @@ -0,0 +1,1337 @@ + + + + CMSIS: Cortex Microcontroller Software Interface Standard + + + +

Cortex Microcontroller Software Interface Standard

+ +

This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

+

Version: 1.30 - 30. October 2009

+ +

Information in this file, the accompany manuals, and software is
+ Copyright © ARM Ltd.
All rights reserved. +

+ +
+ +

Revision History

+
    +
  • Version 1.00: initial release.
    • +
  • Version 1.01: added __LDREXx, __STREXx, and __CLREX.
    • +
  • Version 1.02: added Cortex-M0.
    • +
  • Version 1.10: second review.
    • +
  • Version 1.20: third review.
    • +
  • Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.
    • +
  • Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.
    • +
  • Version 1.30: updated Device Support Packages.
    • +
+ +
+ +

Contents

+ +
    +
  1. About
    2. +
  2. Coding Rules and Conventions
    3. +
  3. CMSIS Files
    4. +
  4. Core Peripheral Access Layer
    5. +
  5. CMSIS Example
    6. +
+ +

About

+ +

+ The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges + that are faced when software components are deployed to physical microcontroller devices based on a + Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M + processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation + with various silicon and software vendors and provides a common approach to interface to peripherals, + real-time operating systems, and middleware components. +

+ +

ARM provides as part of the CMSIS the following software layers that are +available for various compiler implementations:

+
    +
  • Core Peripheral Access Layer: contains name definitions, + address definitions and helper functions to + access core registers and peripherals. It defines also a device + independent interface for RTOS Kernels that includes debug channel + definitions.
    • +
+ +

These software layers are expanded by Silicon partners with:

+
    +
  • Device Peripheral Access Layer: provides definitions + for all device peripherals
    • +
  • Access Functions for Peripherals (optional): provides + additional helper functions for peripherals
    • +
+ +

CMSIS defines for a Cortex-M Microcontroller System:

+
    +
  • A common way to access peripheral registers + and a common way to define exception vectors.
    • +
  • The register names of the Core + Peripherals and the names of the Core + Exception Vectors.
    • +
  • An device independent interface for RTOS Kernels including a debug + channel.
    • +
+ +

+ By using CMSIS compliant software components, the user can easier re-use template code. + CMSIS is intended to enable the combination of software components from multiple middleware vendors. +

+ +

Coding Rules and Conventions

+ +

+ The following section describes the coding rules and conventions used in the CMSIS + implementation. It contains also information about data types and version number information. +

+ +

Essentials

+
    +
  • The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, + there are disable and enable sequences for PC-LINT inserted.
    • +
  • ANSI standard data types defined in the ANSI C header file + <stdint.h> are used.
    • +
  • #define constants that include expressions must be enclosed by + parenthesis.
    • +
  • Variables and parameters have a complete data type.
    • +
  • All functions in the Core Peripheral Access Layer are + re-entrant.
    • +
  • The Core Peripheral Access Layer has no blocking code + (which means that wait/query loops are done at other software layers).
    • +
  • For each exception/interrupt there is definition for: +
      +
    • an exception/interrupt handler with the postfix _Handler + (for exceptions) or _IRQHandler (for interrupts).
      • +
    • a default exception/interrupt handler (weak definition) that contains an endless loop.
      • +
    • a #define of the interrupt number with the postfix _IRQn.
      • +
    • +
+ +

Recommendations

+ +

The CMSIS recommends the following conventions for identifiers.

+
    +
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • +
  • CamelCase names to identify peripherals access functions and interrupts.
    • +
  • PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
    • +
  • Doxygen comments for all functions are included as described under Function Comments below.
    • +
+ +Comments + +
    +
  • Comments use the ANSI C90 style (/* comment */) or C++ style + (// comment). It is assumed that the programming tools support today + consistently the C++ comment style.
    • +
  • Function Comments provide for each function the following information: +
      +
    • one-line brief function overview.
      • +
    • detailed parameter explanation.
      • +
    • detailed information about return values.
      • +
    • detailed description of the actual function.
      • +
    +

    Doxygen Example:

    + 
    +/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
    +
    • +
+ +

Data Types and IO Type Qualifiers

+ +

+ The Cortex-M HAL uses the standard types from the standard ANSI C header file + <stdint.h>. IO Type Qualifiers are used to specify the access + to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of + debug information of peripheral registers. +

+ + + + + + + + + + + + + + + + + + + + + + + + +
IO Type Qualifier#defineDescription
__Ivolatile constRead access only
__OvolatileWrite access only
__IOvolatileRead and write access
+ +

CMSIS Version Number

+

+ File core_cm3.h contains the version number of the CMSIS with the following define: +

+ +
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
+#define __CM3_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
+ +

+ File core_cm0.h contains the version number of the CMSIS with the following define: +

+ +
+#define __CM0_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
+#define __CM0_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
+ + +

CMSIS Cortex Core

+

+ File core_cm3.h contains the type of the CMSIS Cortex-M with the following define: +

+ +
+#define __CORTEX_M                (0x03)
+ +

+ File core_cm0.h contains the type of the CMSIS Cortex-M with the following define: +

+ +
+#define __CORTEX_M                (0x00)
+ + +

CMSIS Files

+

+ This section describes the Files provided in context with the CMSIS to access the Cortex-M + hardware and peripherals. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FileProviderDescription
device.hDevice specific (provided by silicon partner)Defines the peripherals for the actual device. The file may use + several other include files to define the peripherals of the actual device.
core_cm0.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm0.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
core_cm3.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
startup_deviceARM (adapted by compiler partner / silicon partner)Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_deviceARM (adapted by silicon partner)Provides a device specific configuration file for the device. It configures the device initializes + typically the oscillator (PLL) that is part of the microcontroller device
+ +

device.h

+ +

+ The file device.h is provided by the silicon vendor and is the + central include file that the application programmer is using in + the C source code. This file contains: +

+
    +
  • +

    Interrupt Number Definition: provides interrupt numbers + (IRQn) for all core and device specific exceptions and interrupts.

    +
    • +
  • +

    Configuration for core_cm0.h / core_cm3.h: reflects the + actual configuration of the Cortex-M processor that is part of the actual + device. As such the file core_cm0.h / core_cm3.h is included that + implements access to processor registers and core peripherals.

    +
    • +
  • +

    Device Peripheral Access Layer: provides definitions + for all device peripherals. It contains all data structures and the address + mapping for the device specific peripherals.

    +
    • +
  • Access Functions for Peripherals (optional): provides + additional helper functions for peripherals that are useful for programming + of these peripherals. Access Functions may be provided as inline functions + or can be extern references to a device specific library provided by the + silicon vendor.
    • +
+ + +

Interrupt Number Definition

+ +

To access the device specific interrupts the device.h file defines IRQn +numbers for the complete device using a enum typedef as shown below:

+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
+  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
+  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
+  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
+  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
+  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
+  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
+  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
+  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
+  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
+/******  STM32 specific Interrupt Numbers ****************************************************************/
+  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
+  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
+  :
+  :
+  } IRQn_Type;
+ + +

Configuration for core_cm0.h / core_cm3.h

+

+ The Cortex-M core configuration options which are defined for each device implementation. Some + configuration options are reflected in the CMSIS layer using the #define settings described below. +

+

+ To access core peripherals file device.h includes file core_cm0.h / core_cm3.h. + Several features in core_cm0.h / core_cm3.h are configured by the following defines that must be + defined before #include <core_cm0.h> / #include <core_cm3.h> + preprocessor command. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#defineFileValueDescription
__NVIC_PRIO_BITScore_cm0.h(2)Number of priority bits implemented in the NVIC (device specific)
__NVIC_PRIO_BITScore_cm3.h(2 ... 8)Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENTcore_cm0.h, core_cm3.h(0, 1)Defines if an MPU is present or not
__Vendor_SysTickConfigcore_cm0.h, core_cm3.h(1)When this define is setup to 1, the SysTickConfig function + in core_cm3.h is excluded. In this case the device.h + file must contain a vendor specific implementation of this function.
+ + +

Device Peripheral Access Layer

+

+ Each peripheral uses a prefix which consists of <device abbreviation>_ + and <peripheral name>_ to identify peripheral registers that access this + specific peripheral. The intention of this is to avoid name collisions caused + due to short names. If more than one peripheral of the same type exists, + identifiers have a postfix (digit or letter). For example: +

+
    +
  • <device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device. + 
    +typedef struct
+{
+  union {
+  __I  uint8_t  RBR;                     /*!< Offset: 0x000   Receiver Buffer Register    */
+  __O  uint8_t  THR;                     /*!< Offset: 0x000   Transmit Holding Register   */
+  __IO uint8_t  DLL;                     /*!< Offset: 0x000   Divisor Latch LSB           */
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;                     /*!< Offset: 0x004   Divisor Latch MSB           */
+  __IO uint32_t IER;                     /*!< Offset: 0x004   Interrupt Enable Register   */
+  };
+  union {
+  __I  uint32_t IIR;                     /*!< Offset: 0x008   Interrupt ID Register       */
+  __O  uint8_t  FCR;                     /*!< Offset: 0x008   FIFO Control Register       */
+  };
+  __IO uint8_t  LCR;                     /*!< Offset: 0x00C   Line Control Register       */
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;                     /*!< Offset: 0x014   Line Status Register        */
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;                     /*!< Offset: 0x01C   Scratch Pad Register        */
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;                     /*!< Offset: 0x020   Autobaud Control Register   */
+  __IO uint8_t  ICR;                     /*!< Offset: 0x024   IrDA Control Register       */
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;                     /*!< Offset: 0x028   Fractional Divider Register */
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;                     /*!< Offset: 0x030   Transmit Enable Register    */
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058   FIFO Level Register         */
+} LPC_UART_TypeDef;
    +
    • +
  • <device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. + For example UART1->DR is the data register of UART1. + 
    +#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
    +
    • +
+ +
Minimal Requiements
+

+ To access the peripheral registers and related function in a device the files device.h + and core_cm0.h / core_cm3.h defines as a minimum: +

+
    +
  • The Register Layout Typedef for each peripheral that defines all register names. + Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of + the peripheral registers. For example: + 
    +typedef struct {
+  __IO uint32_t CTRL;      /* SysTick Control and Status Register */
+  __IO uint32_t LOAD;      /* SysTick Reload Value Register       */
+  __IO uint32_t VAL;       /* SysTick Current Value Register      */
+  __I  uint32_t CALIB;     /* SysTick Calibration Register        */
+  } SysTick_Type;
    +
    • + +
  • + Base Address for each peripheral (in case of multiple peripherals + that use the same register layout typedef multiple base addresses are defined). For example: + 
    +#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
    +
    • + +
  • + Access Definition for each peripheral (in case of multiple peripherals that use + the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, + LPC_UART2). For Example: + 
    +#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */
    +
    • +
+ +

+ These definitions allow to access the peripheral registers from user code with simple assignments like: +

+
SysTick->CTRL = 0;
+ +
Optional Features
+

In addition the device.h file may define:

+
    +
  • + #define constants that simplify access to the peripheral registers. + These constant define bit-positions or other specific patterns are that required for the + programming of the peripheral registers. The identifiers used start with + <device abbreviation>_ and <peripheral name>_. + It is recommended to use CAPITAL letters for such #define constants. +
    • +
  • + Functions that perform more complex functions with the peripheral (i.e. status query before + a sending register is accessed). Again these function start with + <device abbreviation>_ and <peripheral name>_. +
    • +
+ +

core_cm0.h and core_cm0.c

+

+ File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers + and core peripherals with efficient functions (defined as static inline). +

+

+ File core_cm0.c defines several helper functions that access processor registers. +

+

Together these files implement the Core Peripheral Access Layer for a Cortex-M0.

+ +

core_cm3.h and core_cm3.c

+

+ File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers + and core peripherals with efficient functions (defined as static inline). +

+

+ File core_cm3.c defines several helper functions that access processor registers. +

+

Together these files implement the Core Peripheral Access Layer for a Cortex-M3.

+ +

startup_device

+

+ A template file for startup_device is provided by ARM for each supported + compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific + interrupt handlers. Each interrupt handler is defined as weak function + to an dummy handler. Therefore the interrupt handler can be directly used in application software + without any requirements to adapt the startup_device file. +

+

+ The following exception names are fixed and define the start of the vector table for a Cortex-M0: +

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+ +

+ The following exception names are fixed and define the start of the vector table for a Cortex-M3: +

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+ +

+ In the following examples for device specific interrupts are shown: +

+
+; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper
+ +

+ Device specific interrupts must have a dummy function that can be overwritten in user code. + Below is an example for this dummy function. +

+
+Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP
+ +

+ The user application may simply define an interrupt handler function by using the handler name + as shown below. +

+
+void WWDG_IRQHandler(void)
+{
+  :
+  :
+}
+ + +

system_device.c

+

+ A template file for system_device.c is provided by ARM but adapted by + the silicon vendor to match their actual device. As a minimum requirement + this file must provide a device specific system configuration function and a global variable + that contains the system frequency. It configures the device and initializes typically the + oscillator (PLL) that is part of the microcontroller device. +

+

+ The file system_device.c must provide + as a minimum requirement the SystemInit function as shown below. +

+ + + + + + + + + + + + + + + + +
Function DefinitionDescription
void SystemInit (void)Setup the microcontroller system. Typically this function configures the + oscillator (PLL) that is part of the microcontroller device. For systems + with variable clock speed it also updates the variable SystemCoreClock.
+ SystemInit is called from startup_device file.
void SystemCoreClockUpdate (void)Updates the variable SystemCoreClock and must be called whenever the + core clock is changed during program execution. SystemCoreClockUpdate() + evaluates the clock register settings and calculates the current core clock. +
+ +

+ Also part of the file system_device.c + is the variable SystemCoreClock which contains the current CPU clock speed shown below. +

+ + + + + + + + + + + + +
Variable DefinitionDescription
uint32_t SystemCoreClockContains the system core clock (which is the system clock frequency supplied + to the SysTick timer and the processor core clock). This variable can be + used by the user application to setup the SysTick timer or configure other + parameters. It may also be used by debugger to query the frequency of the + debug timer or configure the trace clock speed.
+ SystemCoreClock is initialized with a correct predefined value.

+ The compiler must be configured to avoid the removal of this variable in + case that the application program is not using it. It is important for + debug systems that the variable is physically present in memory so that + it can be examined to configure the debugger.
+ +

Note

+
    +

  • The above definitions are the minimum requirements for the file + system_device.c. This + file may export more functions or variables that provide a more flexible + configuration of the microcontroller system.

    +
    • +
+ + +

Core Peripheral Access Layer

+ +

Cortex-M Core Register Access

+

+ The following functions are defined in core_cm0.h / core_cm3.h + and provide access to Cortex-M core registers. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Function DefinitionCoreCore RegisterDescription
void __enable_irq (void)M0, M3PRIMASK = 0Global Interrupt enable (using the instruction CPSIE + i)
void __disable_irq (void)M0, M3PRIMASK = 1Global Interrupt disable (using the instruction + CPSID i)
void __set_PRIMASK (uint32_t value)M0, M3PRIMASK = valueAssign value to Priority Mask Register (using the instruction + MSR)
uint32_t __get_PRIMASK (void)M0, M3return PRIMASKReturn Priority Mask Register (using the instruction + MRS)
void __enable_fault_irq (void)M3FAULTMASK = 0Global Fault exception and Interrupt enable (using the + instruction CPSIE + f)
void __disable_fault_irq (void)M3FAULTMASK = 1Global Fault exception and Interrupt disable (using the + instruction CPSID f)
void __set_FAULTMASK (uint32_t value)M3FAULTMASK = valueAssign value to Fault Mask Register (using the instruction + MSR)
uint32_t __get_FAULTMASK (void)M3return FAULTMASKReturn Fault Mask Register (using the instruction MRS)
void __set_BASEPRI (uint32_t value)M3BASEPRI = valueSet Base Priority (using the instruction MSR)
uiuint32_t __get_BASEPRI (void)M3return BASEPRIReturn Base Priority (using the instruction MRS)
void __set_CONTROL (uint32_t value)M0, M3CONTROL = valueSet CONTROL register value (using the instruction MSR)
uint32_t __get_CONTROL (void)M0, M3return CONTROLReturn Control Register Value (using the instruction + MRS)
void __set_PSP (uint32_t TopOfProcStack)M0, M3PSP = TopOfProcStackSet Process Stack Pointer value (using the instruction + MSR)
uint32_t __get_PSP (void)M0, M3return PSPReturn Process Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack)M0, M3MSP = TopOfMainStackSet Main Stack Pointer (using the instruction MSR)
uint32_t __get_MSP (void)M0, M3return MSPReturn Main Stack Pointer (using the instruction MRS)
+ +

Cortex-M Instruction Access

+

+ The following functions are defined in core_cm0.h / core_cm3.hand + generate specific Cortex-M instructions. The functions are implemented in the file + core_cm0.c / core_cm3.c. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameCoreGenerated CPU InstructionDescription
void __NOP (void)M0, M3NOPNo Operation
void __WFI (void)M0, M3WFIWait for Interrupt
void __WFE (void)M0, M3WFEWait for Event
void __SEV (void)M0, M3SEVSet Event
void __ISB (void)M0, M3ISBInstruction Synchronization Barrier
void __DSB (void)M0, M3DSBData Synchronization Barrier
void __DMB (void)M0, M3DMBData Memory Barrier
uint32_t __REV (uint32_t value)M0, M3REVReverse byte order in integer value.
uint32_t __REV16 (uint16_t value)M0, M3REV16Reverse byte order in unsigned short value.
sint32_t __REVSH (sint16_t value)M0, M3REVSHReverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value)M3RBITReverse bit order of value
uint8_t __LDREXB (uint8_t *addr)M3LDREXBLoad exclusive byte
uint16_t __LDREXH (uint16_t *addr)M3LDREXHLoad exclusive half-word
uint32_t __LDREXW (uint32_t *addr)M3LDREXWLoad exclusive word
uint32_t __STREXB (uint8_t value, uint8_t *addr)M3STREXBStore exclusive byte
uint32_t __STREXB (uint16_t value, uint16_t *addr)M3STREXHStore exclusive half-word
uint32_t __STREXB (uint32_t value, uint32_t *addr)M3STREXWStore exclusive word
void __CLREX (void)M3CLREXRemove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
+ + +

NVIC Access Functions

+

+ The CMSIS provides access to the NVIC via the register interface structure and several helper + functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to + identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative + IRQn values are used for processor core exceptions. +

+

+ For the IRQn values of core exceptions the file device.h provides + the following enum names. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Core Exception enum ValueCoreIRQnDescription
NonMaskableInt_IRQnM0, M3-14Cortex-M Non Maskable Interrupt
HardFault_IRQnM0, M3-13Cortex-M Hard Fault Interrupt
MemoryManagement_IRQnM3-12Cortex-M Memory Management Interrupt
BusFault_IRQnM3-11Cortex-M Bus Fault Interrupt
UsageFault_IRQnM3-10Cortex-M Usage Fault Interrupt
SVCall_IRQnM0, M3-5Cortex-M SV Call Interrupt
DebugMonitor_IRQnM3-4Cortex-M Debug Monitor Interrupt
PendSV_IRQnM0, M3-2Cortex-M Pend SV Interrupt
SysTick_IRQnM0, M3-1Cortex-M System Tick Interrupt
+ +

The following functions simplify the setup of the NVIC. +The functions are defined as static inline.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameCoreParameterDescription
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)M3Priority Grouping ValueSet the Priority Grouping (Groups . Subgroups)
uint32_t NVIC_GetPriorityGrouping (void)M3(void)Get the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn)M0, M3IRQ NumberEnable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn)M0, M3IRQ NumberDisable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberReturn 1 if IRQn is pending else 0
void NVIC_SetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberSet IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberClear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn)M3IRQ NumberReturn 1 if IRQn is active else 0
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)M0, M3IRQ Number, PrioritySet Priority for IRQn
+ (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn)M0, M3IRQ NumberGet Priority for IRQn
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)M3IRQ Number, Priority Group, Preemptive Priority, Sub PriorityEncode priority for given group, preemptive and sub priority
NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)M3IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub PriorityDeccode given priority to group, preemptive and sub priority
void NVIC_SystemReset (void)M0, M3(void)Resets the System
+

Note

+
    +

  • The processor exceptions have negative enum values. Device specific interrupts + have positive enum values and start with 0. The values are defined in + device.h file. +

    +
    • +

  • The values for PreemptPriority and SubPriority + used in functions NVIC_EncodePriority and NVIC_DecodePriority + depend on the available __NVIC_PRIO_BITS implemented in the NVIC. +

    +
    • +
+ + +

SysTick Configuration Function

+ +

The following function is used to configure the SysTick timer and start the +SysTick interrupt.

+ + + + + + + + + + + + + + +
NameParameterDescription
uint32_t SysTickConfig + (uint32_t ticks)ticks is SysTick counter reload valueSetup the SysTick timer and enable the SysTick interrupt. After this + call the SysTick timer creates interrupts with the specified time + interval.
+
+ Return: 0 when successful, 1 on failure.
+
+ + +

Cortex-M3 ITM Debug Access

+ +

The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that +provides together with the Serial Viewer Output trace capabilities for the +microcontroller system. The ITM has 32 communication channels; two ITM +communication channels are used by CMSIS to output the following information:

+
    +
  • ITM Channel 0: implements the ITM_SendChar function + which can be used for printf-style output via the debug interface.
    • +
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for + kernel awareness debugging.
    • +
+

Note

+
    +

  • The ITM channel 31 is selected for the RTOS kernel since some kernels + may use the Privileged level for program execution. ITM + channels have 4 groups with 8 channels each, whereby each group can be + configured for access rights in the Unprivileged level. The ITM channel 0 + may be therefore enabled for the user task whereas ITM channel 31 may be + accessible only in Privileged level from the RTOS kernel itself.

    +
    • +
+ +

The prototype of the ITM_SendChar routine is shown in the +table below.

+ + + + + + + + + + + + + + +
NameParameterDescription
void uint32_t ITM_SendChar(uint32_t chr)character to outputThe function outputs a character via the ITM channel 0. The + function returns when no debugger is connected that has booked the + output. It is blocking when a debugger is connected, but the + previous character send is not transmitted.

+ Return: the input character 'chr'.
+ +

+ Example for the usage of the ITM Channel 31 for RTOS Kernels: +

+
+  // check if debugger connected and ITM channel enabled for tracing
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+  (ITM->TCR & ITM_TCR_ITMENA) &&
+  (ITM->TER & (1UL << 31))) {
+    // transmit trace data
+    while (ITM->PORT31_U32 == 0);
+    ITM->PORT[31].u8 = task_id;      // id of next task
+    while (ITM->PORT[31].u32 == 0);
+    ITM->PORT[31].u32 = task_status; // status information
+  }
+ + +

Cortex-M3 additional Debug Access

+ +

CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. +Data can be transmitted via a certain global buffer variable towards the target system.

+ +

The buffer variable and the prototypes of the additional functions are shown in the +table below.

+ + + + + + + + + + + + + + + + + + + + + + + + +
NameParameterDescription
extern volatile int ITM_RxBuffer Buffer to transmit data towards debug system.

+ Value 0x5AA55AA5 indicates that buffer is empty.
int ITM_ReceiveChar (void)noneThe nonblocking functions returns the character stored in + ITM_RxBuffer.

+ Return: -1 indicates that no character was received.
int ITM_CheckChar (void)noneThe function checks if a character is available in ITM_RxBuffer.

+ Return: 1 indicates that a character is available, 0 indicates that + no character is available.
+ + +

CMSIS Example

+

+ The following section shows a typical example for using the CMSIS layer in user applications. + The example is based on a STM32F10x Device. +

+
+#include "stm32f10x.h"
+
+volatile uint32_t msTicks;                       /* timeTicks counter */
+
+void SysTick_Handler(void) {
+  msTicks++;                                     /* increment timeTicks counter */
+}
+
+__INLINE static void Delay (uint32_t dlyTicks) {
+  uint32_t curTicks = msTicks;
+
+  while ((msTicks - curTicks) < dlyTicks);
+}
+
+__INLINE static void LED_Config(void) {
+  ;                                              /* Configure the LEDs */
+}
+
+__INLINE static void LED_On (uint32_t led) {
+  ;                                              /* Turn On  LED */
+}
+
+__INLINE static void LED_Off (uint32_t led) {
+  ;                                              /* Turn Off LED */
+}
+
+int main (void) {
+  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
+    ;                                            /* Handle Error */
+    while (1);
+  }
+  
+  LED_Config();                                  /* configure the LEDs */                            
+ 
+  while(1) {
+    LED_On (0x100);                              /* Turn  on the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+    LED_Off (0x100);                             /* Turn off the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+  }
+}
+ + + \ No newline at end of file diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/License.doc b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/License.doc new file mode 100644 index 0000000000000000000000000000000000000000..b6b8acecc137bca709444106cba045d3d01daedd GIT binary patch literal 39936 zcmeI53w&Hvz3*2ZZBuBVr4Jqg-IP)q2qBafkZ1Flwy9}S@}SfrFqxSo(8g!^moP(odvq z?1-P~rSnWxy)k$1Uu5y=1Ks4`kH|Iruxr=e*@t}heulg3&0El=OJVTdj~gA%QG|Cj zO)+Lpu`#RnaU+7^2}E5={8@zmi%^7jOmp+yxSuhvaXWRk`>gP6Zlm7w=Y;hFFQKlHfxaQ}ERf8S{OfPon%>RWR!E`Qf)aD%tq)`9jqjy!`t7(C??8 zN6#+|{a z7IHL08H+OOzPDoR@5VzOOM$dFX^6)r68iU4Fg?y;)TbzaJ;w zfA-UD=0C%aU$0-4&mXn(2YTc4*$@5p{bxV)%jXOIe4|5O9{n(1c|ZOc=#m^xbd7Gu zfA;z8Kj#bm`hEQn3@<~+{E9)35(eW{#(!42uD!^k`MrctL%f<0wU(VHKEEdlwYX3W z-7+I9V|p%J1rF>!2i7P1Q%++%5=%s4PA2KJrwO`aPAl=m)Fq=aC!B~nt$ndbyfYpN zXX43()0s@!Ty@D*Cbq>{6OW{lkz^v1O7`@`QWWmY41`lLry-Gvr8>h@)S97|a4LFY zd3oEahE^xkRPVI6hFYA)hPqHwUC60f*%At^2{pAjq}Di%p_Mg_fyl+zdl|P?IJKd+ zb)is`v%b0ASsZF;TSYZBPHRKc%Epk>&{W@WMnipjO=G3g+~UW&)lqvx+xiNphQ@1J z*3kBvhPF_>vv>hd3o4uy6reT{<}|Ocx2?_XEl^k2Tn~v9Yh4?vYgo}xSJT$e+~m~M z)itkKThp|jw#g3V9+g#&ZGed8rpEQox`xI^o2A*!K>ccG{L0&!Z4YUtu9;5R2HRHE zwAol%4y|o-Y8o4TO4~v$Yg+04C^~A_J9QBC5jB5(gUiuv;tUB5O|5Ozpd=!i#mIFH z(AF+qDypt|t?in}WR)VQ>1Yg>?)HYB1Y)Yjgjv6_SwAe>cBdHMB$Il0a0jfE3wI|wV_iv}DxJ|Jq`SjCJx(H-apH+cPd`0e9Ivp2 z;=O%6vEEoB<7%X2r;|i)rJTP0j-GhBI~H})L88-6D%KfGNzFy6%T_U>yC+dIRfiLU zPAn0o4iOiNbSIKM$*y=ztPW?K-teH)5pxo;NGzQWrv{}md&8Sz4hpd!)v4lrsbsW2 zl2KG2`ce8)l*J&?))7fUx@r_7#u8HLbo6H&X-{>VlD+9z&t|g6w)CZFwP(;t$1)lO zO52{q)1%b$;#gHzm7{jzQpcSsR5QJbrYnhrhh4EmEEUcqQ$%!xBb&Umo_I$poDyY_ z?sC(wqtXed)3M$TRYxM+*~DFtKPNex!#(k+HySA?8tdrqa?<`vK%s8bzgC5loNylu zaF-G&NcM>s@jE@3&cu4vKr|KKOap%Llbn`@);gFH>5kKAreC$dXN>~6d$s-q6D#a! zGMv5P^rnGiYE#-SVtw6%Y1-{^dcuRr{tW%>goBw_7wsb!k$5W7AJ0H~I^LB?pCm#S z$2V6vEp3g%Ea{GSbvr$=&9NRtN+aUS-~`n%!OH!`Ze>eNQ(J5KF)S0U{T&!|xWY*eB`cXC2o)m|OQezfm_xl<9wnc!$>|FZYNDx;{zSO5 zGu{)o{K|C4Q&CcpacGp4u(+ebiBSq75SC;#?oKu@inclsD_7*lvo9oVzK}oq!ov8InkN-=GR)6$F&|m1#1josM`yQ&%izL>aK$-GP)72AS3N+YE1V}@Z!qhG|nN+*>Z4EMlpakkPy{(7PVaps+6v9+^K zEJu$`cQporCz3V#BQ#Q0&-V4F`jRLYq%|tJOZHh^*&W`jN#jMuqLoN{q91FE=@HB@ z9IHIZPRLX_ScPJtJNmWx)BViLL8ZYyJO2mbG#iblGpRUANhzLkLwR+_Bi&ZVAUnA= z*-3OVUU7$e(N}4ozCp-DFggdVz@(+EJ>zqf)w!7A^_Dh~tw&<(uXum2 zOsaIJd=z=Mvs2U9YL(PxmJ=2~@hpYT$!I-*S7`*-E``JE*zjDEov;M0(l&~jV@-H1 zFs=&lX1k^gn#5HDEDd&il#3yk&V@j74pY+;9&q#6d6ck2k?zMd*M zrqXKCaOAxHxLt!C%lt|w6VIR;#U<&DSXw5@#HvgM^6TTQl9bAf#S>L{O!UHGmZOYZ z<41bIn=S%3=4?M1;ecHtGK@(w6|+oLbB3vA#n^B)ZkIIF7UiLFS-?fz*$$* zqBXoBge!aI+LlmjYo*h$W^H2wrQ`*))wH#@HMguMwyCbMy&i|E5;w37H=xb+JFN#< zX({px1}eo5S`%uiTSXf+wGEB9t(8tIMOs(X)Tv(QbUa)e+tl3D(6pk323+@<)>kyN zH9?W}XKS3bH7#uob?uEcEza8ZmbJ~Tp-C}9j*m-w$O*NyG`F;RY@oBDmNV$MnAy^> za#fpLIsuJswHR(4#tD;#I)%KUQ8ylgQH<&pN*Kz9<8T8o5h zd1vP+=6>c4WbF{w? zS10U5dcyJE>|%xqO<`0IdeCP<1xBO#D^qmXu7i2QHrp7YtZEESXqosG&Vp>E3p|%t zbWwL4p8H!;*1GW@AQZI+O|Fi>_UnagFV$TNu=ebj$pn!-rQF=IKvg=M7=4>QFhB(Ezd01)hM7RMvJ$qUxSO&mCRh3W?u0ScFLs>xw~6 zr>r=)MbQ@PV)3QPa1?g5dAkD%zf(}&i;b&+p?DN~ zEu89zb89Oexy*N6;cr5Z~NOO^(1jBrsPB2P<8 z50-l@C38l$y`&?Sip1giAnsl`oz&g{3GxBFCRF19`vP(%{Y{D7tsw5363~eUEN4ls zWr)FMyF#*MBSqRqq$(YaN9@*tJH@j3B1|OogsXkzN82q3*@+zU4mU?w2DDz?j3aNdpLvhvULhXC!s;OSYtM1$} zX^0;7#oPK9vdJOdZuCfs$N2pT1c;p~_Mkd#*J!{O{7Lj>TQFTDD;x&Ov^V{ zCs=8$E>Nf7WDbh6f-how!&~CL{k_y;RTmT{2V5oZ?K5dhgZae<%<&#;$0ydxudLFs zR-^++!PUiLtOCEZuQdNyf|?UUoYy5@%`iG>v*avVOZ+#AI?eqqGsi zIKQZ8 zTJ9`}Mx8ZWxaM37oU@LQbF?zV`?@t)@pGz=L$ztq`LZqxzndlpY7B)*WnJV z4YjnbcNWwk@BNHYlO<$m{UO?I1i*i8hiyj1QzXK%rbEIp2mC?+zY+| zUjFgR-@5DitsA$l+q&X}!$p`gxBJ$zkD7Vivris0b*uL=&8v&e>ELV-=Gh!Dulvhq zY|EWSX{C*m{q2F|Yfe;&oA8IIum2K;+aF5mOR8}FjFmx5(} z5PbM%@Zo{H51$XFjCcqp1n=QR$-u%s*cwSgmz z;anlP?DJOhm@#mY=e;jGuz1#GzkK^_!gC32`kNKo?V+YX`p82H)YyHY40p?ZstAe!qC>1tRF&;Xv zTT^D-Jggv^CP4-3SEAKLVxBV%9e(@;r=T0#omX<_pmgcQFXm3mmd;y$R;Me+s2+@6 z0jN(Ca2$G}ChsarTk3_|mkHaVrhIGeEREe)!G8e{g0F+e!H>Ydfqw^o1kIcZUkhR& z13nIJ05^g!fv7*>25~FJ5rw z__fiZte{cSF_IVNAdN*DWI#W-0DKDE0{%O=mUVs`coIAX{sm;$f9_ufe**s>%*P&B z0PX{ig6{y?2s?kd^XZ+B?R@$hPv8CYV>f+bAiiPshSmHGkL}32?A*|DnR70~=}({Y z^So)lKKa{u)AH6i8Qnu3l^>U<(6(kpYu@%H1^N1vSF*Ak$(w^#mt?+?x8}R{cqV7s zej1-SoTQ!$_64VbCeRGR;5G0DXv4-k2b>4e;0ACHxDPxHehPj8ehpp)vI*Y+zXxxD zU0@a`-46qcz~Nvi*aU6@H-lTiz2H&sZSc?F8Sv_}+h2X?)jMB(_SI+Yk8WPw{_IuH zUUlbH7kK|VFX+4~JAXE;`0V&hivCtKTuvxwRxapOt_d7eDvt_kx@xcX7gg!E)7 zpRhKwSo|&HIQjwLXfTbxJ}Cp!!CG)SXa{G30dPLJ99#je2KR!Oz#HHl@cIj{KmPE2 zw|(ZKzS}Ok?K9`x)^yP+BPVzEDJ#<(KK!$svN^1AkDhhj1UY`aWJm5C6KIOO+8|5a zU9*qOU2`@^-c_2mrKR)D_Iy6-aKH2Bn54u_C@E&P=BdWJ>|kTApU?O?#{3pE;}fg} zr-M&|E5WCLe1)sPXTde#T5vts25tm5frIfS=7SyCvF7HL;KOslhY=|w9{wemZN$Tf zZ13jb$zav*;{*QQ@b&2MZT7BoZ_^dM;iF5;9($Ye?PaET+pNWh78Sd3_RlLv`*3+Z zJ_*|x4=-`C*aU6{KLalUhrdWW1bhsf4L%QU2mc$q1PJ&&_F^6Ck+z{FbS6X^>ks6Vfk$x@J4 zk3zveCzs`{-x2>G1&1;BD?k`r3#1Ef0;f2}EC&r>JxGHL_^;rfz-z$Q89TXu6TJG9 zNBQ@)&+Fe+{JU_|$5xt2UF^xpd&=(>1@`3VRbF2#%M(qkoccGL<42YMBX15@I`WPz zb+|dk8yh!AUP`ml`e&5uY@KR*T&u*)(RdXff(`)ZEx`T{vm+|MI_H=pF(0kZ?-_h+_G@{|iIX|& z%(j|W(#Dfh`Xb3NyCe7PZWk?z=A6r)fMd02hL-KzqUZ z+y4>U!N1q^^snFgHws5&8}aa~V79{j`_6%YrD%8eOK1AF<;*;`tJ=!`#X08+y8pYy`+*tPe7E=mG*lmuu3la|*X)Cvc`L6aOS63*zRN}x zZVDWDA33lbQ}K7Zip_E}BP)DUO_NEQl<75L(?i=*Kl@=E?PtzeRa6=#>|HgzEDbVX zEOGUwX8F!tUoiD%#uPtw9#1jTNsax~nK6!8%Y6!T+220XP239FO^~Xq#l+3;cYU33 zxRx2FjS?Ny5F__UDi1XKzKMIX^rurz(HVG zAOW_5!RhRxajNRa2*lHR3(s5j47+u|0jj@@o!RU6Wp{;L`QL(OcGcE`)4?afmEcq0 zCU7wQaKHsXJ8zmQDTnVcNfID0drv#r`(S*&duZIP{BR?ipT1}B>3{Y<*jBzgLHe25 z*|MBK$leF*4BiLp&q4oH_m1L8F#o%}SDnQ<%G$OVj=!`_=u2!@fzN_#z_s9dunpV@ ze3_Xakeds+-|ETF&CqN=Mx}7bgYLNsX)YfMeDV13L6Hegwb*NjU%|bK#+eT#|0rpD zS9`r3A{5-q_B~J9czVL}W#%|_=1Ci;&Y_Z9e5w=<2`>&*nOn@c_MO=KuY-eY@_W_4 zwlBH)GwuCI+xTfyJopme;{F4&M1!Ze9=B zn|2pOJ=usO`7OCFx{>-cG;ixNi@&Q?0iWnxD8v zMss*SAYCP$gjs9k`cTC1;@TVnRJTsJ=q-oJY94Y>!8kx^defnKEBZbRJ_4G-Mc`WS zIdCVq3)~GJ0{;ZQ34RUq9z=bZJukEChN0Q*_V*C`d%$oE9oumNxoC2SC@#jM!3VK^ zqqMD{=jG<$-)RE4-}l^QhK7dpcNH^n?TdF@N5V`~wnO_Iwh(h;Z&R{E63o`!4z?1A zpT5JNK|E%!VzY-WXDBm;Smm!J+{cSABA!15!P(w(huHTB4a_u8s2PJNY|2b&iH7sE zk|NvotQ{&~lL?b>{t|F0xB_VLlY{XLcpe#a+_;Nrgwr6@ z4TtY(NaS1h_uaN~;w0M80G$f@JY0=zT?a0rCl>>`-0Gpf#QSbmK37XzcosYdd~V29 zAI%ZD?mjn4=;=s^BgGTI<(l%byTIj-i#7yY-VP8e9!iG(4d~horqF4$_tAM^OYZ1eK@b4)|~T=O-~R9}7Ee&(qI_BZoW2bv9==bLjY9rMTehnPb)Ei}cv zK|FuO;pWAXBaBW<=-lDG$!fb*^@~%EHT$nS*60Mv_YXMHJkxoy(K-A#SJasM!YfQI zf3$Vil+{LWt98moXJ_@-PKow)M(1)uQ`Z}923=aZ!E88TgPGd3!9>qL+vvQ++_S>w zbG02t@53+LZTg_xV)mW9H3;+l@|y>&)+~XMNA;&5qvh zu0H#5^U8)FnR{!VG9_pH*tB2twE5-v|7wnQerj}5_jKo36FL4_qZ2(Z)x2o*R|z_S zaAfx{%qe^P%IN&M-XZJ6LVM$D=IQd+%}e#K8=ZpeDEXb4y5%kNO3&M-YVj^R#&@Ha zwH0+Un#kWavfD(YY8DF>33RV_?OJYz{Ml{HnIAe~&*3LO4=T%7HQGg6E{(yDcFrVj z?d}-0e}wiFu~vF=e0J&+K@r zm@mKEEaxnJ;&S1|6F;+}*bYxEENNhx7E4c4qGaZ=gd<}WqwA0oW0wK9H8-yCJ6R5t zO}k^tL#*_dTypSI{ej&6_N(o(GPa_^h26PEj{!sMU1i69{5*}5FVBAb$Z*w}dY-;x z*WN6>ry280Q2`Z`|JORie0<>30`B?BYpiyuKTtj!mLRc{W|Qn zC;4q>Hn~sTHf&`%jFH2gY1+|mV6ODp_aB;jdRGz#aY`rbOic2QMYXx*LuQMuzb~7| zrEHqHkobFfC-M@KU60;KP_N$kXjY|t@(bbn#({Uxx~Rr6^%oKI(kE`;`KRXYnfF{< zW{y1k>(5ma_b>^PBc-aDs@ymf(@ts2zEZ5JXvv)TC?7Kzw{?27d z{a+@6_ZkE7L7`R#g<3Nd`t)&IxC$I7aG=0}0tX5lC~%;_fdU5#94K(0z<~k>K7bs^ z=l{!(EdI$4e{yTphh|=X6aIhYpYE$CZpx^*K78*=Ab*{J{T|mx?^9kd1hfb6Nx-2- za}Cg&JMA6F*S`bEm;VZoFMmJK+r9q=pY7_V5-K*zq`u_%4TGWR6CBEpY28z=w7?rpP zh~`^>{Piz;&q~w2$H-3@+N@%sAKlnuOVNBb%KHSNt=-=p(L2zw-#T>ZRjYjQFuQA^ z4;2zsxC$I7aG=0}0tX5lC~%;_fdU5#94K(0z<~k>{_Z&-|5N^@{7!j)@=fKn>V3U@ zY`v$~yLma9^26nm%g2^KDo;~Bz24!=cb8|W)3oy6N1x8ssaqYL;i#DPF6R?E;1I9? zyu$&Og@lKJMc{C-7*v2Gz>%O590jU?+*0|^#{iX;|Icw9vkV*ujt3_Io$6KkNrWeZ zQ^2W!qcmnYr~yiU8`OLEdKNwimrly*?|~f?vZr`boPyh(YaXXZd_GBrrcReMx%)N* zE9`^!^VFQxm*~ubB8R-VW9(@-_b;ivsND+o;_oiizT{TnWC|ZjrU$)qTMTBZw*JR68N!YliaPCm8>a?PG-@qtzTACE&pQv*4=K5Vs z`{H;hm~8txd*YveoHC~8yGPFn9{+9UC)t0UTl3p5GIjJ;XUUrRTkVZX*{y3Iw3pxZ zWc#lM&fBe4#?Sn2+8@8h-AjEh?Mrq)D7r4lr^3C zU;jHIYZ|O+)p<3d?3~tpm7iX9g89RTAN+I9wcVQ;h1?Ty;4iuU4^_6tk7NCBgs4Yd zGXeW;_)97i(V8p0u>QZd^_G g!+ZG+YJlCX=dW%57tSBCAIe6m^l&ZsOP@db55$o82LJ#7 literal 0 HcmV?d00001 diff --git a/Demo/CORTEX_EFMG890F128_IAR/FreeRTOSConfig.h b/Demo/CORTEX_EFMG890F128_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..d4d0a7f43 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/FreeRTOSConfig.h @@ -0,0 +1,108 @@ +/* + FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( 14000000UL ) +#define configTICK_RATE_HZ ( ( portTickType ) 100 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 +#define configUSE_MUTEXES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +#define configUSE_COUNTING_SEMAPHORES 0 +#define configUSE_ALTERNATIVE_API 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configGENERATE_RUN_TIME_STATS 0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#define configKERNEL_INTERRUPT_PRIORITY 255 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_EFMG890F128_IAR/ParTest.c b/Demo/CORTEX_EFMG890F128_IAR/ParTest.c new file mode 100644 index 000000000..0915b022d --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/ParTest.c @@ -0,0 +1,109 @@ +/* + FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo app includes. */ +#include "partest.h" + +/* Library includes. */ +#include "dvk.h" + +void vParTestInitialise( void ) +{ + DVK_init(); + DVK_setLEDs( 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned long ulLEDs; + + /* Suspend all other tasks, in order to make sure no other tasks excecutes + this code at the same time. */ + vTaskSuspendAll(); + { + ulLEDs = DVK_getLEDs(); + + if( xValue == pdTRUE ) + { + /* Turn the LED on if xValue is true. */ + ulLEDs = ulLEDs | ( 1 << uxLED ); + } + else + { + /* Turn the LED off if xValue is not true. */ + ulLEDs &= ~( 1 << uxLED ); + } + + DVK_setLEDs( ulLEDs ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned long ulLEDs; + + vTaskSuspendAll(); + { + ulLEDs = DVK_getLEDs(); + ulLEDs = ulLEDs ^ ( 1 << uxLED ); + DVK_setLEDs( ulLEDs ); + } + xTaskResumeAll(); +} diff --git a/Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewd b/Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..29d302c7f --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewd @@ -0,0 +1,1411 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 1 + 1 + 1 + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB5_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + JLINK_ID + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 1 + 1 + 0 + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB5_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewp b/Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..e631e98ff --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.ewp @@ -0,0 +1,1677 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 17 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Demo + + Common demo tasks + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\QPeek.c + + + $PROJ_DIR$\..\Common\Minimal\recmutex.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + + $PROJ_DIR$\lcdtest.c + + + $PROJ_DIR$\ledtest.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest.c + + + + Energy Micro Code + + bsp + + $PROJ_DIR$\bsp\dvk.c + + + $PROJ_DIR$\bsp\dvk_boardcontrol.c + + + $PROJ_DIR$\bsp\dvk_ebi.c + + + $PROJ_DIR$\bsp\dvk_spi.c + + + + CMSIS + + $PROJ_DIR$\CMSIS\CM3\CoreSupport\core_cm3.c + + + $PROJ_DIR$\CMSIS\CM3\DeviceSupport\EnergyMicro\EFM32\system_efm32.c + + + + $PROJ_DIR$\lcd\lcdcontroller.c + + + + FreeRTOS source + + Port layer + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + $PROJ_DIR$\startup_efm32.s + + + + diff --git a/Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.eww b/Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/Demo/CORTEX_EFMG890F128_IAR/bsp/chip.h b/Demo/CORTEX_EFMG890F128_IAR/bsp/chip.h new file mode 100644 index 000000000..3fed3d9f7 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/bsp/chip.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file + * @brief Chip initialization, SW workarounds for chip errata issues + * @author Energy Micro AS + * @version 1.1.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef __CHIP_H +#define __CHIP_H + +#include + +/**************************************************************************//** + * @brief Chip errata workarounds + *****************************************************************************/ +static inline void CHIP_init(void) +{ + uint32_t rev; + volatile uint32_t *reg; + + rev = *(volatile uint32_t *)(0x0FE081FC); + /* Engineering Sample calibration setup */ + if ((rev >> 24) == 0) + { + reg = (volatile uint32_t *) 0x400CA00C; + *reg &= ~(0x70UL); + /* DREG */ + reg = (volatile uint32_t *) 0x400C6020; + *reg &= ~(0xE0000000UL); + *reg |= ~(7 << 25); + } + if ((rev >> 24) <= 1) + { + /* DREG */ + reg = (volatile uint32_t *) 0x400C6020; + *reg &= ~(0x00001F80UL); + /* Update CMU reset values */ + reg = (volatile uint32_t *) 0x400C8040; + *reg = 0; + reg = (volatile uint32_t *) 0x400C8044; + *reg = 0; + reg = (volatile uint32_t *) 0x400C8058; + *reg = 0; + reg = (volatile uint32_t *) 0x400C8060; + *reg = 0; + reg = (volatile uint32_t *) 0x400C8078; + *reg = 0; + } +} + +#endif diff --git a/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.c b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.c new file mode 100644 index 000000000..720c95caa --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.c @@ -0,0 +1,62 @@ +/**************************************************************************//** + * @file + * @brief DVK board support package, initialization + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#include "efm32.h" +#include "dvk.h" + +/**************************************************************************//** + * @brief Initializes DVK, configures board control access + *****************************************************************************/ +void DVK_init(void) +{ +#ifdef DVK_EBI_CONTROL + DVK_EBI_init(); +#endif +#ifdef DVK_SPI_CONTROL + DVK_SPI_init(); +#endif + /* Inform AEM application that we are in Energy Mode 0 by default */ + DVK_setEnergyMode(0); +} + +/**************************************************************************//** + * @brief Disables DVK, free up resources + *****************************************************************************/ +void DVK_disable(void) +{ +#ifdef DVK_EBI_CONTROL + /* Handover bus control */ + DVK_disableBus(); + /* Disable EBI interface */ + DVK_EBI_disable(); +#endif + +#ifdef DVK_SPI_CONTROL + DVK_SPI_disable(); +#endif +} diff --git a/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.h b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.h new file mode 100644 index 000000000..318e9f0bb --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk.h @@ -0,0 +1,122 @@ +/**************************************************************************//** + * @file + * @brief DVK Board Support, master header file + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef __DVK_H +#define __DVK_H + +#include +#include "dvk_boardcontrol.h" +#include "dvk_bcregisters.h" + +/* IF not user overrides default, try to decide DVK access interface based on + * part number */ +#ifndef DVK_SPI_CONTROL +#ifndef DVK_EBI_CONTROL + +#if defined(EFM32G200F16) +#define DVK_SPI_CONTROL +#elif defined(EFM32G200F32) +#define DVK_SPI_CONTROL +#elif defined(EFM32G200F64) +#define DVK_SPI_CONTROL +#elif defined(EFM32G210F128) +#define DVK_SPI_CONTROL +#elif defined(EFM32G230F128) +#define DVK_SPI_CONTROL +#elif defined(EFM32G230F32) +#define DVK_SPI_CONTROL +#elif defined(EFM32G230F64) +#define DVK_SPI_CONTROL +#elif defined(EFM32G280F128) +#define DVK_EBI_CONTROL +#elif defined(EFM32G280F32) +#define DVK_EBI_CONTROL +#elif defined(EFM32G280F64) +#define DVK_EBI_CONTROL +#elif defined(EFM32G290F128) +#define DVK_EBI_CONTROL +#elif defined(EFM32G290F32) +#define DVK_EBI_CONTROL +#elif defined(EFM32G290F64) +#define DVK_EBI_CONTROL +#elif defined(EFM32G840F128) +#define DVK_SPI_CONTROL +#elif defined(EFM32G840F32) +#define DVK_SPI_CONTROL +#elif defined(EFM32G840F64) +#define DVK_SPI_CONTROL +#elif defined(EFM32G880F128) +#define DVK_SPI_CONTROL +#elif defined(EFM32G880F32) +#define DVK_SPI_CONTROL +#elif defined(EFM32G880F64) +#define DVK_SPI_CONTROL +#elif defined(EFM32G890F128) +#define DVK_SPI_CONTROL +#elif defined(EFM32G890F32) +#define DVK_SPI_CONTROL +#elif defined(EFM32G890F64) +#define DVK_SPI_CONTROL +#else +#define DVK_SPI_CONTROL +#endif + +#endif +#endif + +/* EBI access */ +void DVK_EBI_init(void); +void DVK_EBI_disable(void); + +void DVK_EBI_writeRegister(volatile uint16_t *addr, uint16_t data); +uint16_t DVK_EBI_readRegister(volatile uint16_t *addr); + +/* SPI access */ +void DVK_SPI_init(void); +void DVK_SPI_disable(void); + +void DVK_SPI_writeRegister(volatile uint16_t *addr, uint16_t data); +uint16_t DVK_SPI_readRegister(volatile uint16_t *addr); + + +/* Accodring to configuration, use either SPI or EBI */ +#ifdef DVK_EBI_CONTROL +#define DVK_writeRegister(A, B) DVK_EBI_writeRegister(A, B) +#define DVK_readRegister(A) DVK_EBI_readRegister(A) +#endif + +#ifdef DVK_SPI_CONTROL +#define DVK_writeRegister(A, B) DVK_SPI_writeRegister(A, B) +#define DVK_readRegister(A) DVK_SPI_readRegister(A) +#endif + +/* General initialization routines */ +void DVK_init(void); +void DVK_disable(void); + +#endif diff --git a/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_bcregisters.h b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_bcregisters.h new file mode 100644 index 000000000..71dc18318 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_bcregisters.h @@ -0,0 +1,103 @@ +/**************************************************************************//** + * @file + * @brief Board Control register definitions + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef __DVK_BCREGISTERS_H +#define __DVK_BCREGISTERS_H + +#include + +/**************************************************************************//** + * Defines FPGA register bank for Energy Micro Development Kit (DVK) board, + * i.e. board control registers + *****************************************************************************/ +#define BC_REGISTER_BASE 0x8c000000 + +#define BC_CFG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x00)) +#define BC_EM ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x01)) +#define BC_MAGIC ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x02)) +#define BC_LED ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x03)) +#define BC_PUSHBUTTON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x04)) +#define BC_DIPSWITCH ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x05)) +#define BC_JOYSTICK ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x06)) +#define BC_AEM ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x07)) +#define BC_DISPLAY_CTRL ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x08)) +#define BC_EBI_CFG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x09)) +#define BC_BUS_CFG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0a)) +#define BC_PERCTRL ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0c)) +#define BC_AEMSTATE ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0d)) +#define BC_SPI_CFG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0e)) +#define BC_RESET ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0f)) +#define BC_ADC_START ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x10)) +#define BC_ADC_STATUS ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x11)) +#define BC_ADC_DATA ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x12)) +#define BC_HW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x14)) +#define BC_FW_BUILDNO ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x15)) +#define BC_FW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x16)) +#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17)) +#define BC_SCRATCH_EFM0 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x18)) +#define BC_SCRATCH_EFM1 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x19)) +#define BC_SCRATCH_EFM2 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1A)) +#define BC_SCRATCH_EFM3 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1B)) +#define BC_SCRATCH_BC0 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1C)) +#define BC_SCRATCH_BC1 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1D)) +#define BC_SCRATCH_BC2 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1E)) +#define BC_SCRATCH_BC3 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1f)) +#define BC_INTFLAG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x20)) +#define BC_INTEN ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x21)) + +/**************************************************************************//** + * Defines bit fields for board control registers + *****************************************************************************/ +#define BC_PERCTRL_ACCEL (1 << 0) +#define BC_PERCTRL_AMBIENT (1 << 1) +#define BC_PERCTRL_POTMETER (1 << 2) +#define BC_PERCTRL_RS232A (1 << 3) +#define BC_PERCTRL_RS232B (1 << 4) +#define BC_PERCTRL_SPI (1 << 5) +#define BC_PERCTRL_I2C (1 << 6) +#define BC_PERCTRL_IRDA (1 << 7) +#define BC_PERCTRL_ANALOG_SE (1 << 8) +#define BC_PERCTRL_ANALOG_DIFF (1 << 9) +#define BC_PERCTRL_AUDIO_OUT (1 << 10) +#define BC_PERCTRL_AUDIO_IN (1 << 11) +#define BC_PERCTRL_ACCEL_GSEL (1 << 12) +#define BC_PERCTRL_ACCEL_SELFTEST (1 << 13) +#define BC_PERCTRL_RS232_SHUTDOWN (1 << 14) +#define BC_PERCTRL_IRDA_SHUTDOWN (1 << 15) + +#define BC_INTEN_PB (1 << 0) +#define BC_INTEN_DIP (1 << 1) +#define BC_INTEN_JOYSTICK (1 << 2) +#define BC_INTEN_AEM (1 << 3) + +#define BC_CFG_SPI (0) +#define BC_CFG_EBI (1) + +#define BC_MAGIC_VALUE (0xef32) + +#endif diff --git a/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_boardcontrol.c b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_boardcontrol.c new file mode 100644 index 000000000..456fff1e0 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_boardcontrol.c @@ -0,0 +1,235 @@ +/**************************************************************************//** + * @file + * @brief DVK Peripheral Board Control API implementation + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#include "efm32.h" +#include "dvk.h" +#include "dvk_boardcontrol.h" +#include "dvk_bcregisters.h" + +/**************************************************************************//** + * @brief Enable EFM32 access to periheral on DVK board + * @param peri Peripheral to enable + *****************************************************************************/ +void DVK_enablePeripheral(DVKPeripheral peri) +{ + uint16_t bit; + uint16_t tmp; + + /* Calculate which bit to set */ + bit = (uint16_t) peri; + + /* Read peripheral control register */ + tmp = DVK_readRegister(BC_PERCTRL); + + /* Enable peripheral */ + tmp |= bit; + + /* Special case for RS232, if enabled disable shutdown */ + if ((peri == DVK_RS232A) || (peri == DVK_RS232B)) + { + /* clear shutdown bit */ + tmp &= ~(BC_PERCTRL_RS232_SHUTDOWN); + } + + /* Special case for IRDA if enabled disable shutdown */ + if (peri == DVK_IRDA) + { + /* clear shutdown bit */ + tmp &= ~(BC_PERCTRL_IRDA_SHUTDOWN); + } + + DVK_writeRegister(BC_PERCTRL, tmp); +} + +/**************************************************************************//** + * @brief Disable EFM32 access to peripheral on DVK board + * @param peri Peripheral to disable + *****************************************************************************/ +void DVK_disablePeripheral(DVKPeripheral peri) +{ + uint16_t bit; + uint16_t tmp; + + /* Calculate which bit to set */ + bit = (uint16_t) peri; + + /* Read peripheral control register */ + tmp = DVK_readRegister(BC_PERCTRL); + + /* Disable peripheral */ + tmp &= ~(bit); + + /* Special case for RS232, if enabled disable shutdown */ + if ((peri == DVK_RS232A) || (peri == DVK_RS232B)) + { + /* Set shutdown bit */ + tmp |= (BC_PERCTRL_RS232_SHUTDOWN); + } + + /* Special case for IRDA */ + if (peri == DVK_IRDA) + { + /* Set shutdown bit */ + tmp |= (BC_PERCTRL_IRDA_SHUTDOWN); + } + + + DVK_writeRegister(BC_PERCTRL, tmp); +} + + +/**************************************************************************//** + * @brief Enable BUS access + *****************************************************************************/ +void DVK_enableBus(void) +{ + /* Enable bus access */ + DVK_writeRegister(BC_BUS_CFG, 1); +} + + +/**************************************************************************//** + * @brief Disable BUS access + *****************************************************************************/ +void DVK_disableBus(void) +{ + DVK_writeRegister(BC_BUS_CFG, 0); +} + + +/**************************************************************************//** + * @brief Inform AEM about current energy mode + * @param energyMode What energy mode we are going to use next + *****************************************************************************/ +void DVK_setEnergyMode(uint16_t energyMode) +{ + DVK_writeRegister(BC_EM, energyMode); +} + + +/**************************************************************************//** + * @brief Get status of bush buttons + * @return Status of push buttons + *****************************************************************************/ +uint16_t DVK_getPushButtons(void) +{ + uint16_t tmp; + + tmp = (~(DVK_readRegister(BC_PUSHBUTTON))) & 0x000f; + return tmp; +} + +/**************************************************************************//** + * @brief Get joystick button status + * @return Joystick controller status + *****************************************************************************/ +uint16_t DVK_getJoystick(void) +{ + uint16_t tmp; + + tmp = (~(DVK_readRegister(BC_JOYSTICK))) & 0x001f; + return tmp; +} + +/**************************************************************************//** + * @brief Get dipswitch status + * The DIP switches are free for user programmable purposes + * @return Joystick controller status + *****************************************************************************/ +uint16_t DVK_getDipSwitch(void) +{ + uint16_t tmp; + + tmp = (~(DVK_readRegister(BC_DIPSWITCH))) & 0x00ff; + return tmp; +} + +/**************************************************************************//** + * @brief Sets user leds + * @param leds 16-bits which enables or disables the board "User leds" + *****************************************************************************/ +void DVK_setLEDs(uint16_t leds) +{ + DVK_writeRegister(BC_LED, leds); +} + +/**************************************************************************//** + * @brief Get status of user LEDs + * @return Status of 16 user leds, bit 1 = on, bit 0 = off + *****************************************************************************/ +uint16_t DVK_getLEDs(void) +{ + return DVK_readRegister(BC_LED); +} + +/**************************************************************************//** + * @brief Enable "Control" buttons/joystick/dip switch interrupts + * @param flags Board control interrupt flags, BC_INTEN_ + *****************************************************************************/ +void DVK_enableInterrupt(uint16_t flags) +{ + uint16_t tmp; + + /* Add flags to interrupt enable register */ + tmp = DVK_readRegister(BC_INTEN); + tmp |= flags; + DVK_writeRegister(BC_INTEN, tmp); +} + +/**************************************************************************//** + * @brief Disable "Control" buttons/joystick/dip switch interrupts + * @param flags Board control interrupt flags, BC_INTEN_ + *****************************************************************************/ +void DVK_disableInterrupt(uint16_t flags) +{ + uint16_t tmp; + + /* Clear flags from interrupt enable register */ + tmp = DVK_readRegister(BC_INTEN); + flags = ~(flags); + tmp &= flags; + DVK_writeRegister(BC_INTEN, tmp); +} + +/**************************************************************************//** + * @brief Clear interrupts + * @param flags Board control interrupt flags, BC_INTEN_ + *****************************************************************************/ +void DVK_clearInterruptFlags(uint16_t flags) +{ + DVK_writeRegister(BC_INTFLAG, flags); +} + +/**************************************************************************//** + * @brief Read interrupt flags + * @return Returns currently triggered interrupts + *****************************************************************************/ +uint16_t DVK_getInterruptFlags(void) +{ + return DVK_readRegister(BC_INTFLAG); +} diff --git a/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_boardcontrol.h b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_boardcontrol.h new file mode 100644 index 000000000..90280d2a0 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_boardcontrol.h @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file + * @brief DVK Peripheral Board Control, prototypes and definitions + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef __DVK_BOARDCONTROL_H +#define __DVK_BOARDCONTROL_H + +#include +#include "dvk_bcregisters.h" + +/** Periperhal access switches */ +typedef enum +{ + DVK_ACCEL = BC_PERCTRL_ACCEL, + DVK_AMBIENT = BC_PERCTRL_AMBIENT, + DVK_POTMETER = BC_PERCTRL_POTMETER, + DVK_RS232A = BC_PERCTRL_RS232A, + DVK_RS232B = BC_PERCTRL_RS232B, + DVK_SPI = BC_PERCTRL_SPI, + DVK_I2C = BC_PERCTRL_I2C, + DVK_IRDA = BC_PERCTRL_IRDA, + DVK_ANALOG_SE = BC_PERCTRL_ANALOG_SE, + DVK_ANALOG_DIFF = BC_PERCTRL_ANALOG_DIFF, + DVK_AUDIO_OUT = BC_PERCTRL_AUDIO_OUT, + DVK_AUDIO_IN = BC_PERCTRL_AUDIO_IN, + DVK_ACCEL_GSEL = BC_PERCTRL_ACCEL_GSEL, + DVK_ACCEL_SELFTEST = BC_PERCTRL_ACCEL_SELFTEST, + DVK_RS232_SHUTDOWN = BC_PERCTRL_RS232_SHUTDOWN, + DVK_IRDA_SHUTDOWN = BC_PERCTRL_IRDA_SHUTDOWN, +} DVKPeripheral; + +/* Peripheral Control */ +void DVK_enablePeripheral(DVKPeripheral peri); +void DVK_disablePeripheral(DVKPeripheral peri); +void DVK_enableBus(void); +void DVK_disableBus(void); + +/* Read board controllers */ +uint16_t DVK_getPushButtons(void); +uint16_t DVK_getJoystick(void); +uint16_t DVK_getDipSwitch(void); + +/* Report AEM status */ +void DVK_setEnergyMode(uint16_t energyMode); + +/* User LEDs */ +void DVK_setLEDs(uint16_t leds); +uint16_t DVK_getLEDs(void); + +/* Interrupt callback */ +void DVK_enableInterrupt(uint16_t flags); +void DVK_disableInterrupt(uint16_t flags); + +uint16_t DVK_getInterruptFlags(void); +void DVK_clearInterruptFlags(uint16_t flags); + +#endif diff --git a/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_ebi.c b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_ebi.c new file mode 100644 index 000000000..8701365bd --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_ebi.c @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file + * @brief EBI implementation of Board Control interface + * This implementation works for devices w/o LCD display on the + * MCU module, specifically the EFM32_G2xx_DK development board + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#include "efm32.h" +#include "dvk.h" +#include "dvk_bcregisters.h" + +/**************************************************************************//** + * @brief Configure EBI (external bus interface) for Board Control register + * access + *****************************************************************************/ +void DVK_EBI_configure(void) +{ + GPIO_TypeDef *gpio = GPIO; + EBI_TypeDef *ebi = EBI; + CMU_TypeDef *cmu = CMU; + + /* Run time check if we have EBI on-chip capability on this device */ + switch ((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) >> + _DEVINFO_PART_DEVICE_NUMBER_SHIFT) + { + /* Only device types EFM32G 280/290/880 and 890 have EBI capability */ + case 280: + case 290: + case 880: + case 890: + break; + default: + /* This device do not have EBI capability - use SPI to interface DVK */ + /* With high probability your project has been configured for an */ + /* incorrect part number. */ + while (1) ; + } + + /* Enable clocks */ + cmu->HFCORECLKEN0 |= CMU_HFCORECLKEN0_EBI; + cmu->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; + + /* Configure bus connect PC bit 12 active low */ + gpio->P[2].MODEH |= + GPIO_P_MODEH_MODE12_PUSHPULL; + + gpio->P[2].DOUT &= ~(1UL << 12); + + /* Configure GPIO pins as push pull */ + /* EBI AD9..15 */ + gpio->P[0].MODEL |= + (GPIO_P_MODEL_MODE0_PUSHPULL | + GPIO_P_MODEL_MODE1_PUSHPULL | + GPIO_P_MODEL_MODE2_PUSHPULL | + GPIO_P_MODEL_MODE3_PUSHPULL | + GPIO_P_MODEL_MODE4_PUSHPULL | + GPIO_P_MODEL_MODE5_PUSHPULL | + GPIO_P_MODEL_MODE6_PUSHPULL); + /* EBI AD8 */ + gpio->P[0].MODEH |= + GPIO_P_MODEH_MODE15_PUSHPULL; + /* EBI CS0-CS3 */ + gpio->P[3].MODEH |= + (GPIO_P_MODEH_MODE9_PUSHPULL | + GPIO_P_MODEH_MODE10_PUSHPULL | + GPIO_P_MODEH_MODE11_PUSHPULL | + GPIO_P_MODEH_MODE12_PUSHPULL); + /* EBI AD0..7 */ + gpio->P[4].MODEH |= + (GPIO_P_MODEH_MODE8_PUSHPULL | + GPIO_P_MODEH_MODE9_PUSHPULL | + GPIO_P_MODEH_MODE10_PUSHPULL | + GPIO_P_MODEH_MODE11_PUSHPULL | + GPIO_P_MODEH_MODE12_PUSHPULL | + GPIO_P_MODEH_MODE13_PUSHPULL | + GPIO_P_MODEH_MODE14_PUSHPULL | + GPIO_P_MODEH_MODE15_PUSHPULL); + /* EBI ARDY/ALEN/Wen/Ren */ + gpio->P[5].MODEL |= + (GPIO_P_MODEL_MODE2_PUSHPULL | + GPIO_P_MODEL_MODE3_PUSHPULL | + GPIO_P_MODEL_MODE4_PUSHPULL | + GPIO_P_MODEL_MODE5_PUSHPULL); + + /* Configure EBI controller */ + /* 16 bit address, 16 bit data mode */ + /* Enable bank 0 address map 0x80000000, FPGA Flash */ + /* Enable bank 1 address map 0x84000000, FPGA SRAM */ + /* Enable bank 2 address map 0x88000000, FPGA TFT Display (SSD2119) */ + /* Enable bank 3 address map 0x8c000000, FPGA Board Control Registers */ + ebi->CTRL = + EBI_CTRL_MODE_D16A16ALE | + EBI_CTRL_BANK0EN | + EBI_CTRL_BANK1EN | + EBI_CTRL_BANK2EN | + EBI_CTRL_BANK3EN; + + /* Setup and hold time */ + ebi->ADDRTIMING = 3 << _EBI_ADDRTIMING_ADDRHOLD_SHIFT | 3 << _EBI_ADDRTIMING_ADDRSET_SHIFT; + + /* Default values for all write timing registers, read timing conservative */ + ebi->RDTIMING = 7 << _EBI_RDTIMING_RDSTRB_SHIFT | 3 << _EBI_RDTIMING_RDHOLD_SHIFT | 3 << _EBI_RDTIMING_RDSETUP_SHIFT; + ebi->WRTIMING = 7 << _EBI_WRTIMING_WRSTRB_SHIFT | 3 << _EBI_WRTIMING_WRHOLD_SHIFT | 3 << _EBI_WRTIMING_WRSETUP_SHIFT; + ebi->POLARITY = _EBI_POLARITY_RESETVALUE; + + /* Toggle on all chip selects for all banks */ + ebi->ROUTE = + EBI_ROUTE_CS0PEN | + EBI_ROUTE_CS1PEN | + EBI_ROUTE_CS2PEN | + EBI_ROUTE_CS3PEN | + EBI_ROUTE_ALEPEN | + EBI_ROUTE_EBIPEN; +} + + +/**************************************************************************//** + * @brief Initialize EBI + * access + *****************************************************************************/ +void DVK_EBI_init(void) +{ + uint16_t ebiMagic; + int ctr; + volatile int i; + + /* Configure EBI */ + DVK_EBI_configure(); + /* Verify that EBI access is working, if not kit is in SPI mode and needs to + * be configured for EBI access */ + ebiMagic = DVK_EBI_readRegister(BC_MAGIC); + if (ebiMagic != BC_MAGIC_VALUE) + { + /* Disable EBI */ + DVK_EBI_disable(); + /* Enable SPI interface */ + DVK_SPI_init(); + /* Set EBI mode - after this SPI access will no longer be available */ + DVK_SPI_writeRegister(BC_CFG, BC_CFG_EBI); + /* Disable SPI */ + DVK_SPI_disable(); + /* Now setup EBI again */ + DVK_EBI_configure(); + /* Wait until ready */ + ctr = 0; + do { + /* Check if FPGA responds */ + ebiMagic = DVK_EBI_readRegister(BC_MAGIC); + ctr++; + DVK_EBI_writeRegister(BC_LED, ctr); + } while (ebiMagic != BC_MAGIC_VALUE); + } +} + +/**************************************************************************//** + * @brief Disable EBI interface, free all GPIO pins + *****************************************************************************/ +void DVK_EBI_disable(void) +{ + GPIO_TypeDef *gpio = GPIO; + EBI_TypeDef *ebi = EBI; + CMU_TypeDef *cmu = CMU; + + /* Toggle off all chip selects for all banks */ + ebi->ROUTE = _EBI_ROUTE_RESETVALUE; + + /* Disable EBI controller */ + ebi->CTRL = _EBI_CTRL_RESETVALUE; + + /* Disable EBI clock */ + cmu->HFCORECLKEN0 &= ~(CMU_HFCORECLKEN0_EBI); + + /* Disable EBI _BC_BUS_CONNECT */ + gpio->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE12_MASK); + + /* Configure GPIO pins as disabled */ + gpio->P[0].MODEL &= ~( + _GPIO_P_MODEL_MODE0_MASK | + _GPIO_P_MODEL_MODE1_MASK | + _GPIO_P_MODEL_MODE2_MASK | + _GPIO_P_MODEL_MODE3_MASK | + _GPIO_P_MODEL_MODE4_MASK | + _GPIO_P_MODEL_MODE5_MASK | + _GPIO_P_MODEL_MODE6_MASK); + gpio->P[0].MODEH &= ~(_GPIO_P_MODEH_MODE15_MASK); + gpio->P[3].MODEH &= ~( + _GPIO_P_MODEH_MODE9_MASK| + _GPIO_P_MODEH_MODE10_MASK| + _GPIO_P_MODEH_MODE11_MASK| + _GPIO_P_MODEH_MODE12_MASK + ); + gpio->P[4].MODEH &= ~( + _GPIO_P_MODEH_MODE8_MASK | + _GPIO_P_MODEH_MODE9_MASK | + _GPIO_P_MODEH_MODE10_MASK | + _GPIO_P_MODEH_MODE11_MASK | + _GPIO_P_MODEH_MODE12_MASK | + _GPIO_P_MODEH_MODE13_MASK | + _GPIO_P_MODEH_MODE14_MASK | + _GPIO_P_MODEH_MODE15_MASK); + gpio->P[5].MODEL &= ~( + _GPIO_P_MODEL_MODE2_MASK | + _GPIO_P_MODEL_MODE3_MASK | + _GPIO_P_MODEL_MODE4_MASK | + _GPIO_P_MODEL_MODE5_MASK); +} + +/**************************************************************************//** + * @brief Write data into 16-bit board control register + * @param addr Address to board control register + * @param data Data to write into register + *****************************************************************************/ +void DVK_EBI_writeRegister(volatile uint16_t *addr, uint16_t data) +{ + *addr = data; +} + +/**************************************************************************//** + * @brief Write data into 16-bit board control register + * @param addr Register to read from + *****************************************************************************/ +uint16_t DVK_EBI_readRegister(volatile uint16_t *addr) +{ + return *addr; +} diff --git a/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_spi.c b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_spi.c new file mode 100644 index 000000000..3ba08b0ec --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_spi.c @@ -0,0 +1,229 @@ +/**************************************************************************//** + * @file + * @brief SPI implementation of Board Control interface + * This implementation use the USART2 SPI interface to control board + * control registers. It works + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#include "efm32.h" +#include "dvk.h" +#include "dvk_bcregisters.h" + +#define clear_bit(reg, bit) (reg &= ~(1 << bit)) + +static volatile uint16_t *lastAddr = 0; + +/**************************************************************************//** + * @brief Initializes USART2 SPI interface for access to FPGA registers + * for board control + *****************************************************************************/ +static void spiInit(void) +{ + USART_TypeDef *usart = USART2; + GPIO_TypeDef *gpio = GPIO; + uint32_t clk, spidiv; + const uint32_t baudrate = 7000000; + const uint32_t div = (2 * baudrate / 256); + + /* Configure SPI bus connect pins */ + gpio->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE13_MASK); + gpio->P[2].MODEH |= (GPIO_P_MODEH_MODE13_PUSHPULL); + gpio->P[2].DOUT &= ~(1UL << 13); + + /* Configure SPI pins */ + gpio->P[2].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK | + _GPIO_P_MODEL_MODE3_MASK | + _GPIO_P_MODEL_MODE4_MASK | + _GPIO_P_MODEL_MODE5_MASK); + gpio->P[2].MODEL |= (GPIO_P_MODEL_MODE2_PUSHPULL | + GPIO_P_MODEL_MODE3_PUSHPULL | + GPIO_P_MODEL_MODE4_PUSHPULL | + GPIO_P_MODEL_MODE5_PUSHPULL); + gpio->P[2].DOUT |= (1UL << 5); + + /* Configure USART2 as SPI master with manual CS */ + /* Get peripheral clock - ensure updated SystemCoreClock */ + SystemCoreClockUpdate(); + clk = (SystemCoreClock >> ((CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >> + _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT)); + /* Drive spi at max 7Mhz or half clockrate if core freq < 14Mhz */ + if (clk < 14000000) + { + spidiv = 0; + } + else + { + spidiv = (clk) / (div) - 256; + } + + /* Never allow higher frequency than specified, round up 1/4 div */ + if (spidiv & 0x3f) spidiv += 0x40; + + usart->CLKDIV = spidiv; + usart->CTRL = USART_CTRL_SYNC; + usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + usart->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN; + usart->CMD = USART_CMD_MASTEREN | USART_CMD_TXEN | USART_CMD_RXEN; +} + +/**************************************************************************//** + * @brief Disables GPIO pins and USART2 from FPGA register access + *****************************************************************************/ +static void spiDisable(void) +{ + USART_TypeDef *usart = USART2; + GPIO_TypeDef *gpio = GPIO; + + /* Disable USART2 */ + usart->CTRL = _USART_CTRL_RESETVALUE; + usart->ROUTE = _USART_ROUTE_RESETVALUE; + usart->CMD = USART_CMD_MASTERDIS | USART_CMD_TXDIS | USART_CMD_RXDIS; + + /* Disable SPI pins */ + gpio->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE13_MASK); + gpio->P[2].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK | + _GPIO_P_MODEL_MODE3_MASK | + _GPIO_P_MODEL_MODE4_MASK | + _GPIO_P_MODEL_MODE5_MASK); +} + +/**************************************************************************//** + * @brief Performs USART2 SPI Transfer + *****************************************************************************/ +static uint16_t spiAccess(uint8_t spiadr, uint8_t rw, uint16_t spidata) +{ + USART_TypeDef *usart = USART2; + GPIO_TypeDef *gpio = GPIO; + uint16_t tmp; + + clear_bit(gpio->P[2].DOUT, 5); + + /* SPI address */ + usart->TXDATA = (spiadr & 0x3) | rw << 3; + while (!(usart->STATUS & USART_STATUS_TXC)) ; + tmp = (usart->RXDATA) << 0; + + /* SPI data LSB */ + usart->TXDATA = spidata & 0xFF; + while (!(usart->STATUS & USART_STATUS_TXC)) ; + tmp = (usart->RXDATA); + + /* SPI data MSB */ + usart->TXDATA = spidata >> 8; + while (!(usart->STATUS & USART_STATUS_TXC)) ; + tmp |= (usart->RXDATA) << 8; + + gpio->P[2].DOUT |= (1 << 5); + + return tmp; +} + +/**************************************************************************//** + * @brief Performs USART2 SPI write to FPGA register + * @param spiadr Address of register + * @param spidata Data to write + *****************************************************************************/ +static void spiWrite(uint8_t spiadr, uint16_t spidata) +{ + spiAccess(spiadr, 0, spidata); +} + +/**************************************************************************//** + * @brief Performs USART2 SPI read from FPGA register + * @param spiadr Address of register + * @param spidata Dummy data + *****************************************************************************/ +static uint16_t spiRead(uint8_t spiadr, uint16_t spidata) +{ + return spiAccess(spiadr, 1, spidata); +} + +/**************************************************************************//** + * @brief Initializes DVK register access + *****************************************************************************/ +void DVK_SPI_init(void) +{ + uint16_t spiMagic; + + spiInit(); + /* Read "board control Magic" register to verify SPI is up and running */ + /* if not FPGA is configured to be in EBI mode */ + + spiMagic = DVK_SPI_readRegister(BC_MAGIC); + if (spiMagic != BC_MAGIC_VALUE) + { + /* Development Kit is configured to use EBI mode, restart of kit required */ + /* to use USART2-SPI for configuration */ + spiDisable(); + while (1) ; + } +} + +/**************************************************************************//** + * @brief Disable and free up resources used by SPI board control access + *****************************************************************************/ +void DVK_SPI_disable(void) +{ + spiDisable(); +} + +/**************************************************************************//** + * @brief Perform read from DVK board control register + * @param addr Address of register to read from + *****************************************************************************/ +uint16_t DVK_SPI_readRegister(volatile uint16_t *addr) +{ + uint16_t data; + + if (addr != lastAddr) + { + spiWrite(0x00, 0xFFFF & ((uint32_t) addr)); /*LSBs of address*/ + spiWrite(0x01, 0xFF & ((uint32_t) addr >> 16)); /*MSBs of address*/ + spiWrite(0x02, (0x0C000000 & (uint32_t) addr) >> 26); /*Chip select*/ + } + /* Read twice */ + data = spiRead(0x03, 0); + data = spiRead(0x03, 0); + lastAddr = addr; + return data; +} + +/**************************************************************************//** + * @brief Perform write to DVK board control register + * @param addr Address of register to write to + * @param data 16-bit to write into register + *****************************************************************************/ +void DVK_SPI_writeRegister(volatile uint16_t *addr, uint16_t data) +{ + if (addr != lastAddr) + { + spiWrite(0x00, 0xFFFF & ((uint32_t) addr)); /*LSBs of address*/ + spiWrite(0x01, 0xFF & ((uint32_t) addr >> 16)); /*MSBs of address*/ + spiWrite(0x02, (0x0C000000 & (uint32_t) addr) >> 26); /*Chip select*/ + } + spiWrite(0x03, data); /*Data*/ + lastAddr = addr; +} diff --git a/Demo/CORTEX_EFMG890F128_IAR/cspycomm.log b/Demo/CORTEX_EFMG890F128_IAR/cspycomm.log new file mode 100644 index 000000000..5b49862ae --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/cspycomm.log @@ -0,0 +1,444 @@ +Logging started @ 2010-03-13 15:06 +DLL Compiled: Jan 25 2010 14:43:57 + +Firmware: Energy Micro EFM32 compiled Nov 17 2009 17:38:20 +Hardware: V7.00 returns O.K. (0190ms, 0001ms total) +T0134 000:214 JLINKARM_GetDLLVersion() returns 41009 (0000ms, 0191ms total) +T0134 000:214 JLINKARM_GetCompileDateTime() (0000ms, 0191ms total) +T0134 000:214 JLINKARM_GetFirmwareString(...) (0000ms, 0191ms total) +T0134 000:215 JLINKARM_TIF_Select(JLINKARM_TIF_SWD) returns 0x00 (0000ms, 0191ms total) +T0134 000:215 JLINKARM_SelectDeviceFamily(3) (0000ms, 0191ms total) +T0134 000:215 JLINKARM_SetSpeed(32) (0001ms, 0191ms total) +T0134 000:216 JLINKARM_SetResetDelay(0) (0000ms, 0192ms total) +T0134 000:216 JLINKARM_ResetPullsRESET(ON) (0000ms, 0192ms total) +T0134 000:216 JLINKARM_Reset() >0x108 TIF>Found SWD-DP with ID 0x2BA01477 >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x66 TIF> >0x66 TIF> >0x35 TIF> >0x16D TIF> >0xD0 TIF> >0x16D TIF> >0xD0 TIF>TPIU fitted. >0xD0 TIF> >0xD0 TIF> FPUnit: 6 code (BP) slots and 2 literal slots >0xD0 TIF> (0438ms, 0192ms total) +T0134 000:654 JLINKARM_Halt() returns 0x00 (0012ms, 0630ms total) +T0134 000:669 JLINKARM_IsHalted() returns TRUE (0013ms, 0643ms total) +T0134 000:682 JLINKARM_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED00) -- Data: 30 C2 2F 41 returns 0x01 (0014ms, 0643ms total) +T0134 000:696 JLINKARM_GetEmuCaps() returns 0x8AEA5833 (0000ms, 0657ms total) +T0134 000:696 JLINKARM_GetEmuCaps() returns 0x8AEA5833 (0000ms, 0657ms total) +T0134 000:700 JLINKARM_SWO_Control(JLINKARM_SWO_CMD_GET_SPEED_INFO, ...) returns 0x00 (0003ms, 0657ms total) +T0134 000:739 JLINKARM_GetSpeed() returns 0x20 (0000ms, 0660ms total) +T0134 000:739 JLINKARM_SetMaxSpeed() (0001ms, 0660ms total) +T0134 000:767 JLINKARM_BeginDownload(Flags = 0x03) (0000ms, 0661ms total) +T0134 000:879 JLINKARM_WriteMem(0x20000000, 0x0008 Bytes, ...) -- Data: 00 20 00 20 55 02 00 20 -- CPU_WriteMem(8 bytes @ 0x20000000) returns 0x08 (0001ms, 0661ms total) +T0134 000:880 JLINKARM_WriteMem(0x20000080, 0x0280 Bytes, ...) -- Data: D9 02 00 20 04 00 00 00 7C 1E 00 20 00 00 00 00 ... -- CPU_WriteMem(640 bytes @ 0x20000080) returns 0x280 (0009ms, 0662ms total) +T0134 000:893 JLINKARM_EndDownload() (0000ms, 0671ms total) +T0134 001:251 JLINKARM_ReadMemU32(0x20000000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x20000000) -- Data: 00 20 00 20 returns 0x01 (0002ms, 0671ms total) +T0134 001:253 JLINKARM_ReadMemU32(0x20000004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x20000004) -- Data: 55 02 00 20 returns 0x01 (0002ms, 0673ms total) +T0134 001:255 JLINKARM_ReadReg(R15) returns 0x00001D08 (0000ms, 0675ms total) +T0134 001:255 JLINKARM_WriteReg(R15, 0x20000254) returns 0x00 (0000ms, 0675ms total) +T0134 001:255 JLINKARM_ReadReg(MSP) returns 0x20000400 (0000ms, 0675ms total) +T0134 001:255 JLINKARM_ReadReg(PSP) returns 0x00000000 (0000ms, 0675ms total) +T0134 001:255 JLINKARM_ReadReg(CFBP) returns 0x00000000 (0000ms, 0675ms total) +T0134 001:255 JLINKARM_WriteReg(MSP, 0x20002000) returns 0x00 (0000ms, 0675ms total) +T0134 001:255 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 00 returns 0x01 (0003ms, 0675ms total) +T0134 001:258 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0678ms total) +T0134 001:260 JLINKARM_ReadReg(R15) returns 0x20000254 (0000ms, 0679ms total) +T0134 001:260 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x05 (0002ms, 0679ms total) +T0134 001:307 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x20000250) -- Data: FE E7 returns 0x01 (0002ms, 0681ms total) +T0134 001:309 JLINKARM_SetBPEx(Addr = 0x20000250, Type = 0xFFFFFFF2) -- CPU_ReadMem(4 bytes @ 0x20000250) -- CPU_WriteMem(4 bytes @ 0x20000250) -- CPU_ReadMem(4 bytes @ 0x20000250) -- CPU_WriteMem(4 bytes @ 0x20000250) -- CPU_ReadMem(2 bytes @ 0x20000250) returns 0x00000001 (0009ms, 0683ms total) +T0134 001:318 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 0692ms total) +T0134 001:325 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0699ms total) +T0134 001:325 JLINKARM_WriteMem(0x20001E24, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(2 bytes @ 0x20000250) -- CPU_WriteMem(4 bytes @ 0x20001E24) returns 0x04 (0001ms, 0699ms total) +T0134 001:326 JLINKARM_EndDownload() (0000ms, 0700ms total) +T0134 001:326 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0700ms total) +T0134 001:326 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0001ms, 0700ms total) +T0134 001:327 JLINKARM_EndDownload() (0000ms, 0701ms total) +T0A20 001:328 JLINKARM_ReadReg(R15) returns 0x20000254 (0000ms, 0701ms total) +T0A20 001:328 JLINKARM_ReadMemU16(0x20000254, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x20000254) -- Data: FF F7 returns 0x01 (0003ms, 0701ms total) +T0A20 001:331 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 0704ms total) +T0A20 001:338 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0711ms total) +T0A20 001:340 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0713ms total) +T0A20 001:341 JLINKARM_ReadMemU32(0xE0002000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0002000) -- Data: 60 02 00 00 returns 0x01 (0002ms, 0714ms total) +T0A20 001:343 JLINKARM_ReadMemU32(0xE0002000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0002000) -- Data: 60 02 00 00 returns 0x01 (0002ms, 0716ms total) +T0A20 001:345 JLINKARM_ReadMemU32(0xE0001000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- Data: 00 00 00 40 returns 0x01 (0002ms, 0718ms total) +T0A20 001:347 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0720ms total) +T0A20 001:349 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0722ms total) +T0A20 001:350 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0723ms total) +T0A20 001:351 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0724ms total) +T0A20 001:352 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0725ms total) +T0A20 001:353 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0726ms total) +T0A20 001:354 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0010ms, 0727ms total) +T0A20 001:366 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0009ms, 0737ms total) +T0A20 001:375 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0737ms total) +T0A20 001:377 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0739ms total) +T0A20 001:378 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0740ms total) +T0A20 001:384 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0746ms total) +T0A20 001:385 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0747ms total) +T0A20 001:386 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0748ms total) +T0A20 001:387 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0749ms total) +T0A20 001:388 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 0750ms total) +T0A20 001:388 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 0750ms total) +T0A20 001:388 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0002ms, 0750ms total) +T0A20 001:391 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0752ms total) +T0A20 001:391 JLINKARM_WriteMem(0x20000300, 0x0068 Bytes, ...) -- Data: 00 00 00 00 00 02 00 00 00 02 00 00 00 02 00 00 ... -- CPU_WriteMem(104 bytes @ 0x20000300) returns 0x68 (0002ms, 0752ms total) +T0A20 001:393 JLINKARM_EndDownload() (0000ms, 0754ms total) +T0A20 001:394 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0754ms total) +T0A20 001:394 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 00 00 00 0D 00 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0001ms, 0754ms total) +T0A20 001:395 JLINKARM_EndDownload() (0000ms, 0755ms total) +T0A20 001:395 JLINKARM_WriteReg(R15, 0x20000264) returns 0x00 (0000ms, 0755ms total) +T0A20 001:396 JLINKARM_ReadReg(R15) returns 0x20000264 (0000ms, 0756ms total) +T0A20 001:396 JLINKARM_ReadMemU16(0x20000264, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x20000264) -- Data: FF F7 returns 0x01 (0003ms, 0756ms total) +T0A20 001:399 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0759ms total) +T0A20 001:405 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0765ms total) +T0A20 001:407 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0767ms total) +T0A20 001:408 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0768ms total) +T0A20 001:409 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0000ms, 0769ms total) +T0A20 001:409 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0769ms total) +T0A20 001:410 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0770ms total) +T0A20 001:411 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0010ms, 0771ms total) +T0A20 001:423 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:425 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:427 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:429 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:431 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:433 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:435 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:437 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:439 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:442 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:445 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:448 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:450 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:453 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:456 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:459 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:462 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:465 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:467 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:469 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:471 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:473 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:475 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:477 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:479 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:481 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:484 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:487 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:490 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:492 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:495 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:498 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:501 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:504 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:507 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:509 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:511 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:513 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:515 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:517 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:519 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:521 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:523 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:526 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:529 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:532 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:534 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:537 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:540 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:543 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:546 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:549 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:551 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:553 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:555 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:557 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:559 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:561 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:563 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:565 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:568 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:571 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:574 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:576 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:579 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:582 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:585 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:587 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:590 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:593 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:595 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:597 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:599 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:601 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:603 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:605 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:607 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:610 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:613 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:616 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:618 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:621 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:624 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:627 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:630 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:633 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:635 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:637 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:639 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:641 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:643 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:645 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:647 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:650 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:653 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:656 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:659 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:661 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:664 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:667 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:670 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:673 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:675 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:677 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:679 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:681 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:683 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:685 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:687 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:689 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total) +T0A20 001:692 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:695 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:698 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:700 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:703 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total) +T0A20 001:706 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0010ms, 0781ms total) +T0A20 001:716 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0781ms total) +T0A20 001:718 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0783ms total) +T0A20 001:719 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 0784ms total) +T0A20 001:726 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0791ms total) +T0A20 001:727 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0792ms total) +T0A20 001:728 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0793ms total) +T0A20 001:729 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0794ms total) +T0A20 001:731 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 0795ms total) +T0A20 001:731 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 0795ms total) +T0A20 001:731 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0002ms, 0795ms total) +T0A20 001:733 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0797ms total) +T0A20 001:733 JLINKARM_WriteMem(0x20000300, 0x1A00 Bytes, ...) -- Data: 00 04 00 20 09 1D 00 00 CB 1D 00 00 CF 1D 00 00 ... -- CPU_WriteMem(6656 bytes @ 0x20000300) returns 0x1A00 (0080ms, 0797ms total) +T0A20 001:814 JLINKARM_EndDownload() (0000ms, 0878ms total) +T0A20 001:814 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0878ms total) +T0A20 001:814 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 00 00 00 00 1A 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0002ms, 0878ms total) +T0A20 001:816 JLINKARM_EndDownload() (0000ms, 0880ms total) +T0A20 001:816 JLINKARM_WriteReg(R15, 0x2000025C) returns 0x00 (0000ms, 0880ms total) +T0A20 001:816 JLINKARM_ReadReg(R15) returns 0x2000025C (0000ms, 0880ms total) +T0A20 001:816 JLINKARM_ReadMemU16(0x2000025C, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x2000025C) -- Data: FF F7 returns 0x01 (0003ms, 0880ms total) +T0A20 001:819 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0883ms total) +T0A20 001:825 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0001ms, 0889ms total) +T0A20 001:826 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0890ms total) +T0A20 001:827 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0891ms total) +T0A20 001:828 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0892ms total) +T0A20 001:829 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0893ms total) +T0A20 001:830 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0894ms total) +T0A20 001:831 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0008ms, 0895ms total) +T0A20 001:841 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:843 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:845 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:847 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:849 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:851 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:853 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:855 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:858 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:861 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:864 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:867 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:869 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:872 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:875 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:878 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:881 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:883 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:885 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:887 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:889 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:891 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:893 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:895 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:897 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:900 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:903 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:906 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:909 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:911 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:914 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:917 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:920 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total) +T0A20 001:923 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:925 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:927 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:929 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:931 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:933 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:935 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total) +T0A20 001:937 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0010ms, 0903ms total) +T0A20 001:947 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0903ms total) +T0A20 001:949 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0905ms total) +T0A20 001:950 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0906ms total) +T0A20 001:956 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0912ms total) +T0A20 001:957 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0913ms total) +T0A20 001:958 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0914ms total) +T0A20 001:959 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0915ms total) +T0A20 001:960 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 0916ms total) +T0A20 001:960 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 0916ms total) +T0A20 001:960 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0002ms, 0916ms total) +T0A20 001:962 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0918ms total) +T0A20 001:962 JLINKARM_WriteMem(0x20000300, 0x0028 Bytes, ...) -- Data: 00 1A 00 00 00 02 00 00 00 1C 00 00 00 02 00 00 ... -- CPU_WriteMem(40 bytes @ 0x20000300) returns 0x28 (0001ms, 0918ms total) +T0A20 001:963 JLINKARM_EndDownload() (0000ms, 0919ms total) +T0A20 001:963 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0919ms total) +T0A20 001:963 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 00 00 00 05 00 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0002ms, 0919ms total) +T0A20 001:965 JLINKARM_EndDownload() (0000ms, 0921ms total) +T0A20 001:965 JLINKARM_WriteReg(R15, 0x20000264) returns 0x00 (0000ms, 0921ms total) +T0A20 001:965 JLINKARM_ReadReg(R15) returns 0x20000264 (0000ms, 0921ms total) +T0A20 001:965 JLINKARM_ReadMemU16(0x20000264, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x20000264) -- Data: FF F7 returns 0x01 (0003ms, 0921ms total) +T0A20 001:968 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0924ms total) +T0A20 001:974 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0930ms total) +T0A20 001:976 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0932ms total) +T0A20 001:977 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0933ms total) +T0A20 001:978 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0934ms total) +T0A20 001:979 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0935ms total) +T0A20 001:981 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0937ms total) +T0A20 001:982 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0008ms, 0938ms total) +T0A20 001:992 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 001:994 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total) +T0A20 001:997 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total) +T0A20 002:000 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total) +T0A20 002:003 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:005 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:007 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:009 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:011 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:013 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:015 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:017 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:019 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:021 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total) +T0A20 002:023 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total) +T0A20 002:027 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total) +T0A20 002:030 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:033 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:035 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:038 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:041 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:044 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:047 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:049 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:051 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:055 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:057 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:059 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:061 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:063 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:066 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:069 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:072 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:075 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:077 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:080 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:083 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:085 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:088 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total) +T0A20 002:091 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:093 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:095 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:097 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total) +T0A20 002:099 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0010ms, 0947ms total) +T0A20 002:109 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0947ms total) +T0A20 002:111 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0949ms total) +T0A20 002:112 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0950ms total) +T0A20 002:118 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0956ms total) +T0A20 002:119 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0957ms total) +T0A20 002:120 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0958ms total) +T0A20 002:121 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0959ms total) +T0A20 002:122 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 0960ms total) +T0A20 002:122 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 0960ms total) +T0A20 002:122 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0002ms, 0960ms total) +T0A20 002:124 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0962ms total) +T0A20 002:124 JLINKARM_WriteMem(0x20000300, 0x0928 Bytes, ...) -- Data: 01 3B 52 1E 00 F8 01 3B 03 B1 F8 D1 11 00 1C BF ... -- CPU_WriteMem(2344 bytes @ 0x20000300) returns 0x928 (0030ms, 0962ms total) +T0A20 002:154 JLINKARM_EndDownload() (0000ms, 0992ms total) +T0A20 002:154 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0992ms total) +T0A20 002:154 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 1A 00 00 28 09 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0001ms, 0992ms total) +T0A20 002:155 JLINKARM_EndDownload() (0000ms, 0993ms total) +T0A20 002:155 JLINKARM_WriteReg(R15, 0x2000025C) returns 0x00 (0000ms, 0993ms total) +T0A20 002:155 JLINKARM_ReadReg(R15) returns 0x2000025C (0000ms, 0993ms total) +T0A20 002:155 JLINKARM_ReadMemU16(0x2000025C, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x2000025C) -- Data: FF F7 returns 0x01 (0002ms, 0993ms total) +T0A20 002:157 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0005ms, 0995ms total) +T0A20 002:162 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 1000ms total) +T0A20 002:164 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 1002ms total) +T0A20 002:165 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 1003ms total) +T0A20 002:166 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 1004ms total) +T0A20 002:167 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 1005ms total) +T0A20 002:168 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 1006ms total) +T0A20 002:169 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0009ms, 1007ms total) +T0A20 002:180 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total) +T0A20 002:183 JLINKARM_IsHalted() returns FALSE (0000ms, 1016ms total) +T0A20 002:185 JLINKARM_IsHalted() returns FALSE (0000ms, 1016ms total) +T0A20 002:187 JLINKARM_IsHalted() returns FALSE (0000ms, 1016ms total) +T0A20 002:189 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total) +T0A20 002:192 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total) +T0A20 002:195 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total) +T0A20 002:198 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total) +T0A20 002:200 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total) +T0A20 002:203 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total) +T0A20 002:206 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total) +T0A20 002:209 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total) +T0A20 002:212 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0010ms, 1016ms total) +T0A20 002:222 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 1016ms total) +T0A20 002:224 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 1018ms total) +T0A20 002:225 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0008ms, 1019ms total) +T0A20 002:233 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 1027ms total) +T0A20 002:234 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 1028ms total) +T0A20 002:235 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 1029ms total) +T0A20 002:236 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0002ms, 1030ms total) +T0A20 002:238 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 1032ms total) +T0A20 002:238 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 1032ms total) +T0A20 002:238 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 1A 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0003ms, 1032ms total) +T0134 002:243 JLINKARM_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 1035ms total) +T0134 002:243 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 1035ms total) +T0134 002:253 JLINKARM_SetResetDelay(0) (0000ms, 1042ms total) +T0134 002:253 JLINKARM_ResetPullsRESET(ON) (0000ms, 1042ms total) +T0134 002:253 JLINKARM_Reset() >0x108 TIF>Found SWD-DP with ID 0x2BA01477 >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x66 TIF> >0x66 TIF> >0x35 TIF> >0x16D TIF> >0xD0 TIF> >0xD0 TIF>TPIU fitted. >0xD0 TIF> >0xD0 TIF> FPUnit: 6 code (BP) slots and 2 literal slots >0xD0 TIF> (0056ms, 1042ms total) +T0134 002:310 JLINKARM_ReadReg(R15) returns 0x00001D08 (0000ms, 1098ms total) +T0134 002:310 JLINKARM_WriteReg(R15, 0x20000254) returns 0x00 (0000ms, 1098ms total) +T0134 002:310 JLINKARM_ReadReg(MSP) returns 0x20000400 (0000ms, 1098ms total) +T0134 002:310 JLINKARM_ReadReg(PSP) returns 0x00000000 (0000ms, 1098ms total) +T0134 002:310 JLINKARM_ReadReg(CFBP) returns 0x00000000 (0001ms, 1098ms total) +T0134 002:311 JLINKARM_WriteReg(MSP, 0x20002000) returns 0x00 (0000ms, 1099ms total) +T0134 002:311 JLINKARM_IsHalted() returns TRUE (0000ms, 1099ms total) +T0134 002:311 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 00 returns 0x01 (0002ms, 1099ms total) +T0134 002:314 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 1102ms total) +T0134 002:318 JLINKARM_BeginDownload(Flags = 0x03) (0000ms, 1103ms total) +T0134 002:786 JLINKARM_ReadMemU32(0x00000000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000000) -- Data: 00 04 00 20 returns 0x01 (0003ms, 1103ms total) +T0134 002:789 JLINKARM_ReadMemU32(0x00000004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000004) -- Data: 09 1D 00 00 returns 0x01 (0002ms, 1106ms total) +T0134 002:791 JLINKARM_ResetPullsRESET(OFF) (0000ms, 1108ms total) +T0134 002:791 JLINKARM_Reset() >0x108 TIF>Found SWD-DP with ID 0x2BA01477 >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x66 TIF> >0x66 TIF> >0x35 TIF> >0x16D TIF> >0xD0 TIF> >0xD0 TIF>TPIU fitted. >0xD0 TIF> >0xD0 TIF> FPUnit: 6 code (BP) slots and 2 literal slots >0xD0 TIF> (0051ms, 1108ms total) +T0134 002:842 JLINKARM_ReadReg(R15) returns 0x00001D08 (0000ms, 1159ms total) +T0134 002:842 JLINKARM_ReadReg(MSP) returns 0x20000400 (0000ms, 1159ms total) +T0134 002:842 JLINKARM_ReadReg(PSP) returns 0x00000000 (0000ms, 1159ms total) +T0134 002:842 JLINKARM_ReadReg(CFBP) returns 0x00000000 (0000ms, 1159ms total) +T0134 002:842 JLINKARM_IsHalted() returns TRUE (0001ms, 1159ms total) +T0134 002:843 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 00 returns 0x01 (0002ms, 1159ms total) +T0134 002:845 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 1161ms total) +T0134 003:676 JLINKARM_ReadMemU32(0x00000008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000008) -- Data: CB 1D 00 00 returns 0x01 (0003ms, 1162ms total) +T0134 003:679 JLINKARM_ReadMemU32(0x0000000C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x0000000C) -- Data: CF 1D 00 00 returns 0x01 (0002ms, 1165ms total) +T0134 003:681 JLINKARM_ReadMemU32(0x00000010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000010) -- Data: D3 1D 00 00 returns 0x01 (0002ms, 1167ms total) +T0134 003:683 JLINKARM_ReadMemU32(0x00000014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000014) -- Data: D7 1D 00 00 returns 0x01 (0002ms, 1169ms total) +T0134 003:685 JLINKARM_ReadMemU32(0x00000018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000018) -- Data: DB 1D 00 00 returns 0x01 (0003ms, 1171ms total) +T0134 003:688 JLINKARM_ReadMemU32(0x0000002C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x0000002C) -- Data: 0D 19 00 00 returns 0x01 (0002ms, 1174ms total) +T0134 003:690 JLINKARM_ReadMemU32(0x00000030, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000030) -- Data: E3 1D 00 00 returns 0x01 (0002ms, 1176ms total) +T0134 003:692 JLINKARM_ReadMemU32(0x00000038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000038) -- Data: BB 18 00 00 returns 0x01 (0002ms, 1178ms total) +T0134 003:694 JLINKARM_ReadMemU32(0x0000003C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x0000003C) -- Data: 81 16 00 00 returns 0x01 (0002ms, 1180ms total) +T0134 003:697 JLINKARM_ReadReg(R15) returns 0x00001D08 (0000ms, 1182ms total) +T0134 003:698 JLINKARM_ReadMemU16(0x0000156C, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x0000156C) -- Data: 00 B5 returns 0x01 (0002ms, 1182ms total) +T0134 003:700 JLINKARM_SetBPEx(Addr = 0x0000156C, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 1184ms total) +T0134 003:700 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 1184ms total) +T0A20 004:578 JLINKARM_ReadMemU16(0x00001D08, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x00001D08) -- Data: 01 48 returns 0x01 (0003ms, 1190ms total) +T0A20 004:581 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 1193ms total) +T0A20 004:588 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 1200ms total) +T0A20 004:590 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0002ms, 1202ms total) +T0A20 004:592 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 1204ms total) +T0A20 004:593 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 1205ms total) +T0A20 004:594 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 1206ms total) +T0A20 004:595 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0003ms, 1207ms total) +T0A20 004:598 JLINKARM_SWO_Control(JLINKARM_SWO_CMD_START, ...) -- UART -- 2250000bps + ***** Error: USB communication timed out: Requested 4 bytes, received 0 bytes ! returns 0x00 (7094ms, 1210ms total) diff --git a/Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.c b/Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.c new file mode 100644 index 000000000..4243484e2 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.c @@ -0,0 +1,542 @@ +/**************************************************************************//** + * @file + * @brief LCD Controller driver + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ +#include "FreeRTOS.h" +#include "task.h" + +#include +#include +#include +#include "efm32.h" +#include "lcdcontroller.h" +#include "lcddisplay.h" + +/** Counts every n'th frame */ +int frameCounter = 0; + +/**************************************************************************//** + * @brief LCD Interrupt Handler, triggers on frame counter, every n'th frame + *****************************************************************************/ +void LCD_IRQHandler(void) +{ + LCD_TypeDef *lcd = LCD; + + /* clear interrupt */ + lcd->IFC = 0xFFFFFFFF; + frameCounter++; +} + +/**************************************************************************//** + * @brief Enables a segment on the LCD display + * @param lcd Pointer to LCD register block + * @param com COM segment number + * @param bitvalue Bit value for segment + *****************************************************************************/ +static void LCD_enableSegment(LCD_TypeDef * lcd, int com, int bitvalue) +{ + switch (com) + { + case 0: + lcd->SEGD0L |= bitvalue; + break; + case 1: + lcd->SEGD1L |= bitvalue; + break; + case 2: + lcd->SEGD2L |= bitvalue; + break; + case 3: + lcd->SEGD3L |= bitvalue; + break; + case 4: + lcd->SEGD0H |= bitvalue; + break; + case 5: + lcd->SEGD1H |= bitvalue; + break; + case 6: + lcd->SEGD2H |= bitvalue; + break; + case 7: + lcd->SEGD3H |= bitvalue; + break; + } +} + +/**************************************************************************//** + * @brief Disables a segment on the LCD Display + * @param lcd Pointer to LCD register structure + * @param com COM segment number + * @param bitvalue Bit value for segment + *****************************************************************************/ +static void LCD_disableSegment(LCD_TypeDef * lcd, int com, int bitvalue) +{ + switch (com) + { + case 0: + lcd->SEGD0L &= ~bitvalue; + break; + case 1: + lcd->SEGD1L &= ~bitvalue; + break; + case 2: + lcd->SEGD2L &= ~bitvalue; + break; + case 3: + lcd->SEGD3L &= ~bitvalue; + break; + case 4: + lcd->SEGD0H &= ~bitvalue; + break; + case 5: + lcd->SEGD1H &= ~bitvalue; + break; + case 6: + lcd->SEGD2H &= ~bitvalue; + break; + case 7: + lcd->SEGD3H &= ~bitvalue; + break; + } +} + +/**************************************************************************//** + * @brief Write number on numeric part on LCD display + * @param lcd Pointer to LCD control block + * @param value Numeric value to put on display, in range -999 to +9999 + *****************************************************************************/ +void LCD_Number(LCD_TypeDef *lcd, int value) +{ + int num, i, com, bit, digit, div, neg; + uint16_t bitpattern; + + /* Parameter consistancy check */ + if (value >= 9999) + { + value = 9999; + } + if (value <= -1000) + { + value = -999; + } + if (value < 0) + { + value = abs(value); + neg = 1; + } + else + { + neg = 0; + } + /* Extract useful digits */ + div = 1; + for (digit = 0; digit < 4; digit++) + { + num = (value / div) % 10; + if ((neg == 1) && (digit == 3)) num = 10; + bitpattern = EM_Numbers[num]; + for (i = 0; i < 7; i++) + { + bit = EFMDisplay.Number[digit].bit[i]; + com = EFMDisplay.Number[digit].com[i]; + if (bitpattern & (1 << i)) + { + LCD_enableSegment(lcd, com, 1 << bit); + } + else + { + LCD_disableSegment(lcd, com, 1 << bit); + } + } + div = div * 10; + } +} + +/**************************************************************************//** + * @brief Turn all segments on numeric display off + * @param lcd Pointer to LCD register structure + *****************************************************************************/ +void LCD_NumberOff(LCD_TypeDef *lcd) +{ + int digit, i, bit, com; + + /* Turn off all segments */ + for (digit = 0; digit < 4; digit++) + { + for (i = 0; i < 7; i++) + { + bit = EFMDisplay.Number[digit].bit[i]; + com = EFMDisplay.Number[digit].com[i]; + LCD_disableSegment(lcd, com, 1 << bit); + } + } + return; +} + + +/**************************************************************************//** + * @brief Write text on LCD display + * @param lcd Pointer to LCD register structure + * @param string Text string to show on display + *****************************************************************************/ +void LCD_Write(LCD_TypeDef *lcd, char *string) +{ + int data, length, index; + uint16_t bitfield; + uint32_t value; + uint32_t com, bit; + int i; + + length = strlen(string); + index = 0; + /* fill out all characters on display */ + for (index = 0; index < 7; index++) + { + if (index < length) + { + data = (int) *string; + } + else /* padding with space */ + { + data = 0x20; /* SPACE */ + } + /* defined letters currently starts at "SPACE" - 0x20; */ + data = data - 0x20; + bitfield = EM_alphabet[data]; + + + for (i = 0; i < 14; i++) + { + bit = EFMDisplay.Text[index].bit[i]; + com = EFMDisplay.Text[index].com[i]; + value = (1 << bit); + + if (bitfield & (1 << i)) + { + /* Turn on segment */ + LCD_enableSegment(lcd, com, value); + } + else + { + /* Turn off segment */ + LCD_disableSegment(lcd, com, value); + } + } + string++; + } + while (lcd->SYNCBUSY) ; +} + +/**************************************************************************//** + * @brief LCD Disable all segments + * @param lcd Pointer to LCD register block + *****************************************************************************/ +void LCD_AllOff(LCD_TypeDef *lcd) +{ + lcd->SEGD0L = 0x00000000; + lcd->SEGD0H = 0x00000000; + lcd->SEGD1L = 0x00000000; + lcd->SEGD1H = 0x00000000; + lcd->SEGD2L = 0x00000000; + lcd->SEGD2H = 0x00000000; + lcd->SEGD3L = 0x00000000; + lcd->SEGD3H = 0x00000000; + while (lcd->SYNCBUSY) ; +} + +/**************************************************************************//** + * @brief LCD Enable all segments + * @param lcd Pointer to LCD register block + *****************************************************************************/ +void LCD_AllOn(LCD_TypeDef *lcd) +{ + lcd->SEGD0L = 0xffffffff; + lcd->SEGD0H = 0xffffffff; + lcd->SEGD1L = 0xffffffff; + lcd->SEGD1H = 0xffffffff; + lcd->SEGD2L = 0xffffffff; + lcd->SEGD2H = 0xffffffff; + lcd->SEGD3L = 0xffffffff; + lcd->SEGD3H = 0xffffffff; + while (lcd->SYNCBUSY) ; +} + +/**************************************************************************//** + * @brief LCD Light up or shut off Energy Mode indicator + * @param lcd Pointer to LCD register block + * @pararm em Energy Mode numer 0 to 4 + * @param on Zero is off, non-zero is on + *****************************************************************************/ +void LCD_EnergyMode(LCD_TypeDef *lcd, int em, int on) +{ + uint32_t com, bitvalue; + + com = EFMDisplay.EMode.com[em]; + bitvalue = 1 << EFMDisplay.EMode.bit[em]; + + if (on) + { + LCD_enableSegment(lcd, com, bitvalue); + } + else + { + LCD_disableSegment(lcd, com, bitvalue); + } +} + +/**************************************************************************//** + * @brief LCD Light up or shut off Ring of Indicators + * @param lcd Pointer to LCD register block + * @param anum "Segment number" on "Ring", range 0 - 7 + * @param on Zero is off, non-zero is on + *****************************************************************************/ +void LCD_ARing(LCD_TypeDef *lcd, int anum, int on) +{ + uint32_t com, bitvalue; + + com = EFMDisplay.ARing.com[anum]; + bitvalue = 1 << EFMDisplay.ARing.bit[anum]; + + if (on) + { + LCD_enableSegment(lcd, com, bitvalue); + } + else + { + LCD_disableSegment(lcd, com, bitvalue); + } +} + +/**************************************************************************//** + * @brief LCD Light up or shut off various symbols on LCD Display + * @param lcd Pointer to LCD register block + * @param s Which symbol to turn on or off + * @param on Zero is off, non-zero is on + *****************************************************************************/ +void LCD_Symbol(LCD_TypeDef *lcd, lcdSymbol s, int on) +{ + int com, bit; + + switch (s) + { + case LCD_SYMBOL_GECKO: + com = 3; bit = 8; + break; + case LCD_SYMBOL_ANT: + com = 3; bit = 1; + break; + case LCD_SYMBOL_PAD0: + com = 1; bit = 8; + break; + case LCD_SYMBOL_PAD1: + com = 2; bit = 8; + break; + case LCD_SYMBOL_AM: + com = 4; bit = 0; + break; + case LCD_SYMBOL_PM: + com = 4; bit = 3; + break; + case LCD_SYMBOL_EFM32: + com = 0; bit = 8; + break; + case LCD_SYMBOL_MINUS: + com = 0; bit = 9; + break; + case LCD_SYMBOL_COL3: + com = 0; bit = 16; + break; + case LCD_SYMBOL_COL5: + com = 0; bit = 24; + break; + case LCD_SYMBOL_COL10: + com = 4; bit = 7; + break; + case LCD_SYMBOL_DP2: + com = 4; bit = 2; + break; + case LCD_SYMBOL_DP3: + com = 5; bit = 2; + break; + case LCD_SYMBOL_DP4: + com = 6; bit = 2; + break; + case LCD_SYMBOL_DP5: + com = 7; bit = 2; + break; + case LCD_SYMBOL_DP6: + com = 0; bit = 21; + break; + case LCD_SYMBOL_DP10: + com = 4; bit = 5; + break; + } + if (on) + { + LCD_enableSegment(lcd, com, 1 << bit); + } + else + { + LCD_disableSegment(lcd, com, 1 << bit); + } +} + +/**************************************************************************//** + * @brief LCD Light up or shut off Battery Indicator + * @param lcd Pointer to LCD register block + * @param batteryLevel Battery Level, 0 to 4 (0 turns all off) + *****************************************************************************/ +void LCD_Battery(LCD_TypeDef *lcd, int batteryLevel) +{ + uint32_t com, bitvalue; + int i, on; + + for (i = 0; i < 4; i++) + { + if (i < batteryLevel) + { + on = 1; + } + else + { + on = 0; + } + com = EFMDisplay.Battery.com[i]; + bitvalue = 1 << EFMDisplay.Battery.bit[i]; + + if (on) + { + LCD_enableSegment(lcd, com, bitvalue); + } + else + { + LCD_disableSegment(lcd, com, bitvalue); + } + } +} + +/**************************************************************************//** + * @brief LCD Initialization routine for EFM32 DVK display + * @param lcd Pointer to LCD register block + *****************************************************************************/ +void LCD_Init(LCD_TypeDef *lcd) +{ + CMU_TypeDef *cmu = CMU; + + /* Enable LFXO oscillator */ + cmu->OSCENCMD |= CMU_OSCENCMD_LFXOEN; + while (!(cmu->STATUS & CMU_STATUS_LFXORDY)) ; + + /* Enable LCD clock in CMU */ + cmu->LFACLKEN0 |= CMU_LFACLKEN0_LCD; + + /* Select LFXO for LCD */ + cmu->LFCLKSEL = CMU_LFCLKSEL_LFA_LFXO | CMU_LFCLKSEL_LFB_LFXO; + + /* LCD Controller Prescaler (divide by 1) */ + /* CLKlcd = 0.25 kHz */ + cmu->LFAPRESC0 &= ~_CMU_LFAPRESC0_LCD_MASK; + cmu->LFAPRESC0 |= _CMU_LFAPRESC0_LCD_DIV128 << _CMU_LFAPRESC0_LCD_SHIFT; + + /* Set up interrupt handler */ + lcd->IEN = 0; + while (lcd->SYNCBUSY) ; + + /* Clear pending interrupts */ + lcd->IFC = ~0; + /* Enable interrupt */ + NVIC_EnableIRQ(LCD_IRQn); + lcd->IEN = LCD_IEN_FC; + + /* Frame rate is 32Hz, 0.25Khz LFCLK128, QUADRUPLEX mode, FDIV=0 */ + lcd->DISPCTRL = LCD_DISPCTRL_MUX_QUADRUPLEX | + LCD_DISPCTRL_BIAS_ONETHIRD | + LCD_DISPCTRL_WAVE_LOWPOWER | + LCD_DISPCTRL_CONLEV_MAX | + LCD_DISPCTRL_VLCDSEL_VDD | + LCD_DISPCTRL_VBLEV_3V00; + + /* No voltage boost, framerate 32Hz */ + cmu->LCDCTRL = 0; + + /* Turn all segments off */ + LCD_AllOff(lcd); + + /* Enable all segment registers */ + lcd->SEGEN = 0x000003FF; + lcd->CTRL = LCD_CTRL_EN | LCD_CTRL_UDCTRL_FRAMESTART; + while (lcd->SYNCBUSY) ; + + /* Configure LCD to give a frame counter interrupt every 8th frame. */ + lcd->BACTRL = LCD_BACTRL_FCEN | (7 << _LCD_BACTRL_FCTOP_SHIFT) | (0 << _LCD_BACTRL_FCPRESC_SHIFT); + while (lcd->SYNCBUSY) ; + lcd->IFC = LCD_IFC_FC; + lcd->IEN = LCD_IEN_FC; +} + + +/**************************************************************************//** + * @brief Disables LCD controller + * @param lcd Pointer to LCD register block + *****************************************************************************/ +void LCD_Disable(LCD_TypeDef *lcd) +{ + CMU_TypeDef *cmu = CMU; + + /* Turn off interrupts */ + lcd->IEN = 0x00000000; + lcd->IFC = LCD_IFC_FC; + NVIC_DisableIRQ(LCD_IRQn); + /* Disable LCD */ + lcd->CTRL = 0; + /* Turn off LCD clock */ + cmu->LFACLKEN0 &= ~(CMU_LFACLKEN0_LCD); + /* Turn off voltage boost if enabled */ + cmu->LCDCTRL = 0; +} + +/**************************************************************************//** + * @brief LCD scrolls a text over the display, sort of "polled printf" + * @param lcd Pointer to LCD register block + *****************************************************************************/ +void LCD_ScrollText(LCD_TypeDef *lcd, char *scrolltext) +{ + int i, len; + char buffer[8]; + + buffer[7] = 0x00; + len = strlen(scrolltext); + if (len < 7) return; + for (i = 0; i < (len - 7); i++) + { + memcpy(buffer, scrolltext + i, 7); + LCD_Write(lcd, buffer); + vTaskDelay(100/portTICK_RATE_MS); + } +} + + diff --git a/Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.h b/Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.h new file mode 100644 index 000000000..605bea4fa --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.h @@ -0,0 +1,73 @@ +/**************************************************************************//** + * @file + * @brief LCD Controller header file + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef _LCDCONTROLLER_H +#define _LCDCONTROLLER_H + +#include "efm32.h" + +/* Range of symbols available on display */ +typedef enum +{ + LCD_SYMBOL_GECKO, + LCD_SYMBOL_ANT, + LCD_SYMBOL_PAD0, + LCD_SYMBOL_PAD1, + LCD_SYMBOL_AM, + LCD_SYMBOL_PM, + LCD_SYMBOL_EFM32, + LCD_SYMBOL_MINUS, + LCD_SYMBOL_COL3, + LCD_SYMBOL_COL5, + LCD_SYMBOL_COL10, + LCD_SYMBOL_DP2, + LCD_SYMBOL_DP3, + LCD_SYMBOL_DP4, + LCD_SYMBOL_DP5, + LCD_SYMBOL_DP6, + LCD_SYMBOL_DP10, +} lcdSymbol; + +/* Regular functions */ +void LCD_Init(LCD_TypeDef *lcd); +void LCD_IRQHandler(void); +void LCD_Disable(LCD_TypeDef *lcd); + +void LCD_AllOff(LCD_TypeDef *lcd); +void LCD_AllOn(LCD_TypeDef *lcd); + +void LCD_ARing(LCD_TypeDef *lcd, int anum, int on); +void LCD_Battery(LCD_TypeDef *lcd, int batteryLevel); +void LCD_EnergyMode(LCD_TypeDef *lcd, int em, int on); +void LCD_Number(LCD_TypeDef *lcd, int value); +void LCD_NumberOff(LCD_TypeDef *lcd); +void LCD_Symbol(LCD_TypeDef *lcd, lcdSymbol s, int on); +void LCD_Write(LCD_TypeDef *lcd, char *string); +void LCD_ScrollText(LCD_TypeDef *lcd, char *scrolltext); + +#endif diff --git a/Demo/CORTEX_EFMG890F128_IAR/lcd/lcddisplay.h b/Demo/CORTEX_EFMG890F128_IAR/lcd/lcddisplay.h new file mode 100644 index 000000000..fe798604f --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/lcd/lcddisplay.h @@ -0,0 +1,391 @@ +/**************************************************************************//** + * @file + * @brief LCD Controller font and display layout for EFM32 development MCU + * module + * @author Energy Micro AS + * @version 1.0.1 + ****************************************************************************** + * @section License + * (C) Copyright 2009 Energy Micro AS, http://www.energymicro.com + ****************************************************************************** + * + * This source code is the property of Energy Micro AS. The source and compiled + * code may only be used on Energy Micro "EFM32" microcontrollers. + * + * This copyright notice may not be removed from the source code nor changed. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no + * obligation to support this Software. Energy Micro AS is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Energy Micro AS will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ****************************************************************************/ + +#ifndef _LCDDISPLAY_H +#define _LCDDISPLAY_H + +#include +/**************************************************************************//** + * @brief + * Defines each text symbol's segment in terms of COM and BIT numbers, + * in a way that we can enumerate each bit for each text segment in the + * following bit pattern: + * @verbatim + * -------0------ + * + * | \7 |8 /9 | + * |5 \ | / |1 + * + * --6--- ---10-- + * + * | / | \11 | + * |4 /13 |12 \ |2 + * + * -------3------ + * @endverbatim + * E.g.: First text character bit pattern #3 (above) is + * Segment 1D for Display + * Location COM 3, BIT 0 + *****************************************************************************/ +typedef struct +{ + uint32_t com[14]; /**< LCD COM line (for multiplexing) */ + uint32_t bit[14]; /**< LCD bit number */ +} CHAR_TypeDef; + + +/**************************************************************************//** + * @brief Defines segment COM and BIT fields numeric display + *****************************************************************************/ +typedef struct +{ + uint32_t com[7]; + uint32_t bit[7]; +} NUMBER_TypeDef; + +/**************************************************************************//** + * @brief Defines segment COM and BIT fields for Energy Modes on display + *****************************************************************************/ +typedef struct +{ + uint32_t com[5]; /**< LCD COM line (for multiplexing) */ + uint32_t bit[5]; /**< LCD bit number */ +} EM_TypeDef; + +/**************************************************************************//** + * @brief Defines segment COM and BIT fields for A-wheel (suited for Anim) + *****************************************************************************/ +typedef struct +{ + uint32_t com[8]; /**< LCD COM line (for multiplexing) */ + uint32_t bit[8]; /**< LCD bit number */ +} ARING_TypeDef; + +/**************************************************************************//** + * @brief Defines segment COM and BIT fields for A-wheel (suited for Anim) + *****************************************************************************/ +typedef struct +{ + uint32_t com[4]; /**< LCD COM line (for multiplexing) */ + uint32_t bit[4]; /**< LCD bit number */ +} BATTERY_TypeDef; + +/**************************************************************************//** + * @brief Defines prototype for all segments in display + *****************************************************************************/ +typedef struct +{ + CHAR_TypeDef Text[7]; + NUMBER_TypeDef Number[4]; + EM_TypeDef EMode; + ARING_TypeDef ARing; + BATTERY_TypeDef Battery; +} MCU_DISPLAY; + +/**************************************************************************//** + * @brief Working instance of LCD display + *****************************************************************************/ +MCU_DISPLAY EFMDisplay = { + .Text = { + { /* 1 */ + .com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0, + .bit[0] = 10, .bit[1] = 12, .bit[2] = 12, .bit[3] = 10, + + .com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2, + .bit[4] = 9, .bit[5] = 9, .bit[6] = 9, .bit[7] = 10, + + .com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0, + .bit[8] = 11, .bit[9] = 11, .bit[10] = 12, .bit[11] = 11, + + .com[12] = 1, .com[13] = 1, + .bit[12] = 11, .bit[13] = 10 + }, + { /* 2 */ + .com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0, + .bit[0] = 14, .bit[1] = 16, .bit[2] = 16, .bit[3] = 14, + + .com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2, + .bit[4] = 13, .bit[5] = 13, .bit[6] = 13, .bit[7] = 14, + + .com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0, + .bit[8] = 15, .bit[9] = 15, .bit[10] = 16, .bit[11] = 15, + + .com[12] = 1, .com[13] = 1, + .bit[12] = 15, .bit[13] = 14 + }, + { /* 3 */ + .com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0, + .bit[0] = 18, .bit[1] = 20, .bit[2] = 20, .bit[3] = 18, + + .com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2, + .bit[4] = 17, .bit[5] = 17, .bit[6] = 17, .bit[7] = 18, + + .com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0, + .bit[8] = 19, .bit[9] = 19, .bit[10] = 20, .bit[11] = 19, + + .com[12] = 1, .com[13] = 1, + .bit[12] = 19, .bit[13] = 18 + }, + { /* 4 */ + .com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0, + .bit[0] = 22, .bit[1] = 24, .bit[2] = 24, .bit[3] = 22, + + .com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2, + .bit[4] = 21, .bit[5] = 21, .bit[6] = 21, .bit[7] = 22, + + .com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0, + .bit[8] = 23, .bit[9] = 23, .bit[10] = 24, .bit[11] = 23, + + .com[12] = 1, .com[13] = 1, + .bit[12] = 23, .bit[13] = 22 + }, + { /* 5 */ + .com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0, + .bit[0] = 25, .bit[1] = 6, .bit[2] = 6, .bit[3] = 25, + + .com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2, + .bit[4] = 7, .bit[5] = 7, .bit[6] = 7, .bit[7] = 25, + + .com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0, + .bit[8] = 26, .bit[9] = 26, .bit[10] = 6, .bit[11] = 26, + + .com[12] = 1, .com[13] = 1, + .bit[12] = 26, .bit[13] = 25 + }, + { /* 6 */ + .com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0, + .bit[0] = 27, .bit[1] = 04, .bit[2] = 04, .bit[3] = 27, + + .com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2, + .bit[4] = 5, .bit[5] = 5, .bit[6] = 5, .bit[7] = 27, + + .com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0, + .bit[8] = 28, .bit[9] = 28, .bit[10] = 4, .bit[11] = 28, + + .com[12] = 1, .com[13] = 1, + .bit[12] = 28, .bit[13] = 27 + }, + { /* 7 */ + .com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0, + .bit[0] = 29, .bit[1] = 2, .bit[2] = 2, .bit[3] = 29, + + .com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2, + .bit[4] = 03, .bit[5] = 3, .bit[6] = 3, .bit[7] = 29, + + .com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0, + .bit[8] = 30, .bit[9] = 30, .bit[10] = 2, .bit[11] = 30, + + .com[12] = 1, .com[13] = 1, + .bit[12] = 30, .bit[13] = 29 + } + }, + .Number = { + { + .com[0] = 3, .com[1] = 2, .com[2] = 1, .com[3] = 0, + .bit[0] = 31, .bit[1] = 31, .bit[2] = 31, .bit[3] = 31, + + .com[4] = 5, .com[5] = 7, .com[6] = 6, + .bit[4] = 0, .bit[5] = 0, .bit[6] = 0, + }, + { + .com[0] = 7, .com[1] = 6, .com[2] = 5, .com[3] = 4, + .bit[0] = 1, .bit[1] = 1, .bit[2] = 1, .bit[3] = 1, + + .com[4] = 5, .com[5] = 7, .com[6] = 6, + .bit[4] = 3, .bit[5] = 3, .bit[6] = 3, + }, + { + .com[0] = 7, .com[1] = 6, .com[2] = 5, .com[3] = 4, + .bit[0] = 4, .bit[1] = 4, .bit[2] = 4, .bit[3] = 4, + + .com[4] = 5, .com[5] = 7, .com[6] = 6, + .bit[4] = 5, .bit[5] = 5, .bit[6] = 5, + }, + { + .com[0] = 7, .com[1] = 6, .com[2] = 5, .com[3] = 4, + .bit[0] = 6, .bit[1] = 6, .bit[2] = 6, .bit[3] = 6, + + .com[4] = 5, .com[5] = 7, .com[6] = 6, + .bit[4] = 7, .bit[5] = 7, .bit[6] = 7, + }, + }, + .EMode = { + .com[0] = 1, .bit[0] = 1, + .com[1] = 2, .bit[1] = 1, + .com[2] = 1, .bit[2] = 0, + .com[3] = 2, .bit[3] = 0, + .com[4] = 3, .bit[4] = 0, + }, + .ARing = { + .com[0] = 0, .bit[0] = 0, + .com[1] = 0, .bit[1] = 1, + .com[2] = 0, .bit[2] = 2, + .com[3] = 0, .bit[3] = 3, + + .com[4] = 0, .bit[4] = 4, + .com[5] = 0, .bit[5] = 5, + .com[6] = 0, .bit[6] = 6, + .com[7] = 0, .bit[7] = 7, + }, + .Battery = { + .com[0] = 0, .bit[0] = 12, + .com[1] = 0, .bit[1] = 17, + .com[2] = 0, .bit[2] = 20, + .com[3] = 0, .bit[3] = 13, + } +}; + +/**************************************************************************//** + * @brief + * Defines higlighted segments for the alphabet, starting from "blank" (SPACE) + * Uses bit pattern as defined for text segments above. + * E.g. a capital O, would have bits 0 1 2 3 4 5 => 0x003f defined + *****************************************************************************/ +uint16_t EM_alphabet[] = { + 0x0000, /* space */ + 0x1100, /* ! */ + 0x0280, /* " */ + 0x0000, /* # */ + 0x0000, /* $ */ + 0x0000, /* % */ + 0x0000, /* & */ + 0x0000, /* £ */ + 0x0039, /* ( */ + 0x000f, /* ) */ + 0x0000, /* * */ + 0x1540, /* + */ + 0x0000, /* , */ + 0x0440, /* - */ + 0x0000, /* . */ + 0x2200, /* / */ + + 0x003f, /* 0 */ + 0x0006, /* 1 */ + 0x045b, /* 2 */ + 0x044f, /* 3 */ + 0x0466, /* 4 */ + 0x046d, /* 5 */ + 0x047d, /* 6 */ + 0x0007, /* 7 */ + 0x047f, /* 8 */ + 0x046f, /* 9 */ + + 0x0000, /* : */ + 0x0000, /* ; */ + 0x0a00, /* < */ + 0x0000, /* = */ + 0x2080, /* > */ + 0x0000, /* ? */ + 0xffff, /* @ */ + + 0x0477, /* A */ + 0x0a79, /* B */ + 0x0039, /* C */ + 0x20b0, /* D */ + 0x0079, /* E */ + 0x0071, /* F */ + 0x047d, /* G */ + 0x0476, /* H */ + 0x0006, /* I */ + 0x000e, /* J */ + 0x0a70, /* K */ + 0x0038, /* L */ + 0x02b6, /* M */ + 0x08b6, /* N */ + 0x003f, /* O */ + 0x0473, /* P */ + 0x083f, /* Q */ + 0x0c73, /* R */ + 0x046d, /* S */ + 0x1101, /* T */ + 0x003e, /* U */ + 0x2230, /* V */ + 0x2836, /* W */ + 0x2a80, /* X */ + 0x046e, /* Y */ + 0x2209, /* Z */ + + 0x0039, /* [ */ + 0x0880, /* backslash */ + 0x000f, /* ] */ + 0x0001, /* ^ */ + 0x0008, /* _ */ + 0x0100, /* ` */ + + 0x1058, /* a */ + 0x047c, /* b */ + 0x0058, /* c */ + 0x045e, /* d */ + 0x2058, /* e */ + 0x0471, /* f */ + 0x0c0c, /* g */ + 0x0474, /* h */ + 0x0004, /* i */ + 0x000e, /* j */ + 0x0c70, /* k */ + 0x0038, /* l */ + 0x1454, /* m */ + 0x0454, /* n */ + 0x045c, /* o */ + 0x0473, /* p */ + 0x0467, /* q */ + 0x0450, /* r */ + 0x0c08, /* s */ + 0x0078, /* t */ + 0x001c, /* u */ + 0x2010, /* v */ + 0x2814, /* w */ + 0x2a80, /* x */ + 0x080c, /* y */ + 0x2048, /* z */ + + 0x0000, +}; + +/**************************************************************************//** + * @brief + * Defines higlighted segments for the numeric display + *****************************************************************************/ +uint16_t EM_Numbers[] = +{ + 0x003f, /* 0 */ + 0x0006, /* 1 */ + 0x005b, /* 2 */ + 0x004f, /* 3 */ + 0x0066, /* 4 */ + 0x006d, /* 5 */ + 0x007d, /* 6 */ + 0x0007, /* 7 */ + 0x007f, /* 8 */ + 0x006f, /* 9 */ + 0x0040, /* - */ +}; + +#endif + diff --git a/Demo/CORTEX_EFMG890F128_IAR/lcdtest.c b/Demo/CORTEX_EFMG890F128_IAR/lcdtest.c new file mode 100644 index 000000000..0e8754473 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/lcdtest.c @@ -0,0 +1,125 @@ +/* + FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "lcdtest.h" + +#define lcdSHORT_DELAY ( 60 / portTICK_RATE_MS ) +#define lcdQUARTER_SECOND ( 250 / portTICK_RATE_MS ) +#define lcdONE_SECOND ( 1000 / portTICK_RATE_MS ) + +void vLCDTask( void *pvParameters ) +{ +long x; +LCD_TypeDef *xLCD = LCD; +char *pcScrollText = "FreeRTOS Energy Micro "; + + /* Loop through various different displays. */ + for( ;; ) + { + /* Start by scrolling some text. */ + LCD_ScrollText( xLCD, pcScrollText ); + LCD_AllOff( xLCD ); + + /* Count down from 100 on the number section of the LCD display. */ + for( x = 100; x > 0; x--) + { + LCD_Number( xLCD, x ); + vTaskDelay( 10 ); + } + LCD_NumberOff( xLCD ); + + /* Turn on gecko and EFM32 symbol. */ + LCD_Symbol( xLCD, LCD_SYMBOL_GECKO, 1 ); + LCD_Symbol( xLCD, LCD_SYMBOL_EFM32, 1 ); + LCD_Write( xLCD, " Gecko " ); + vTaskDelay( lcdONE_SECOND ); + + LCD_AllOn( xLCD); + vTaskDelay( lcdONE_SECOND ); + + LCD_AllOff( xLCD); + LCD_Write( xLCD, "OOOOOOO" ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, "XXXXXXX" ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, "+++++++" ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, "@@@@@@@" ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, "ENERGY " ); + vTaskDelay( lcdQUARTER_SECOND ); + LCD_Write( xLCD, "@@ERGY " ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, " @@RGY " ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, " M@@GY " ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, " MI@@Y " ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, " MIC@@ " ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, " MICR@@" ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, " MICRO@" ); + vTaskDelay( lcdSHORT_DELAY ); + LCD_Write( xLCD, " MICRO " ); + vTaskDelay( lcdQUARTER_SECOND ); + LCD_Write( xLCD, "-EFM32-" ); + vTaskDelay( lcdQUARTER_SECOND ); + } +} \ No newline at end of file diff --git a/Demo/CORTEX_EFMG890F128_IAR/lcdtest.h b/Demo/CORTEX_EFMG890F128_IAR/lcdtest.h new file mode 100644 index 000000000..6f69c029a --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/lcdtest.h @@ -0,0 +1,14 @@ +#ifndef _LCDTEST_H +#define _LCDTEST_H + +#include "FreeRTOS.h" +#include "task.h" + +#include "lcdcontroller.h" + +/* + * The task that writes to the LCD. + */ +void vLCDTask( void *pvParameters ); + +#endif diff --git a/Demo/CORTEX_EFMG890F128_IAR/ledtest.c b/Demo/CORTEX_EFMG890F128_IAR/ledtest.c new file mode 100644 index 000000000..b29f2b063 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/ledtest.c @@ -0,0 +1,83 @@ +/* + FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo app includes. */ +#include "ledtest.h" + +#define lLEDOnE_SECOND ( 1000UL / portTICK_RATE_MS ) + +void vLEDTask( void *pvParameters ) +{ +long lLEDOn = pdTRUE, x; + + for( ;; ) + { + for( x = 8; x < 16; x++ ) + { + /*Depending on if lLEDOn is true or false, turn on or off led number i*/ + vParTestSetLED( x,lLEDOn ); + + /*Delay for 1000 ms*/ + vTaskDelay( lLEDOnE_SECOND ); + } + + /*After the for loop, we flip lLEDOn. On the next run through the + for loop above, the leds will be flipped.*/ + lLEDOn = ~lLEDOn; + } +} + diff --git a/Demo/CORTEX_EFMG890F128_IAR/ledtest.h b/Demo/CORTEX_EFMG890F128_IAR/ledtest.h new file mode 100644 index 000000000..122816f68 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/ledtest.h @@ -0,0 +1,66 @@ +/* + FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef LEDTEST_H +#define LEDTEST_H + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/* + * A task that writes to the LEDs. + */ +void vLEDTask( void *pvParamters ); + +#endif /* LEDTEST_H */ diff --git a/Demo/CORTEX_EFMG890F128_IAR/main.c b/Demo/CORTEX_EFMG890F128_IAR/main.c new file mode 100644 index 000000000..aad46671d --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/main.c @@ -0,0 +1,271 @@ +/* + FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "LCD test" task - the LCD task writes a continually repeating series of patterns + * to the LCD display. + * + * "LED test" task - This is a very simple task that just turns on user LEDs + * 8 to 15 in turn, before turning them off again. + * + * "Check task" - The check task only runs every five seconds but has the highest + * priority so is guaranteed to get processing time. Its main job is to inspect + * all the other standard demo tasks to ensure they are executing without error. + * The Check task will toggle LED 0 every five seconds while no errors exist, + * with the toggle frequency increasing to 200ms should an error be detected in + * any other task. + * + * Both the check task and the idle task place the processor into energy saving + * mode 1, which will be exited following each tick interrupt. The check task + * is the highest priority task in the system, so while it is executing no other + * task will execute. If the check task places the processor into a low power + * mode without blocking then the energy consumption as viewed on the Energy + * Micro Gecko board will go down noticibly as in effect no tasks will be running. + * The check task places the processor into low power mode for two out of every + * five seconds. The current use of low power modes is very basic. Future + * FreeRTOS releases will aim to make significant improvements. + * + */ + /* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Common demo application includes. */ +#include "partest.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "recmutex.h" +#include "semtest.h" + +/* Demo application includes. */ +#include "lcdcontroller.h" +#include "ledtest.h" +#include "lcdtest.h" +#include "chip.h" + +/* Task priorities. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainGEN_Q_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/* A period of two seconds, adjusted to use the tick frequency. */ +#define mainTWO_SECONDS ( 2000 / portTICK_RATE_MS ) + +/* The length of the delay between each cycle of the check task when an error +has / has not been detected. */ +#define mainNO_ERROR_CHECK_FREQUENCY ( 5000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_FREQUENCY ( 200 / portTICK_RATE_MS ) + +/* The LED that is toggled by the check task. The rate of the toggle indicates +whether or not an error has been found, as defined by the +mainNO_ERROR_CHECK_FREQUENCY and mainERROR_CHECK_FREQUENCY definitions above. */ +#define mainCHECK_LED ( 0 ) + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as required by the demo. + */ +static void prvSetupHardware( void ); + +/* + * The check task as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Put the CPU into the least low power low power mode. + */ +static void prvLowPowerMode1( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Perform the necessary hardware configuration. */ + prvSetupHardware(); + + /* Create the task that writes various text and patterns to the LCD. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Create a task that writes to LEDs 8 to 15. */ + xTaskCreate( vLEDTask, "LCDTask", configMINIMAL_STACK_SIZE, NULL, mainLED_TASK_PRIORITY, NULL ); + + /* Create some of the standard demo tasks. These just test the port and + demonstrate how the FreeRTOS API can be used. They do not provide any + specific functionality. */ + vStartGenericQueueTasks( mainGEN_Q_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY ); + + /* Create the check task as described at the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* The scheduler should now be running the tasks so the following code should + never be reached. If it is reached then there was insufficient heap space + for the idle task to be created. In this case the heap size is set by + configTOTAL_HEAP_SIZE in FreeRTOSConfig.h. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* Use the idle task to place the CPU into a low power mode. Greater power + saving could be achieved by not including any demo tasks that never block. */ + prvLowPowerMode1(); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ) +{ + /* This function will be called if a task overflows its stack, if + configCHECK_FOR_STACK_OVERFLOW != 0. It might be that the function + parameters have been corrupted, depending on the severity of the stack + overflow. When this is the case pxCurrentTCB can be inspected in the + debugger to find the offending task. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +portTickType xLastExecutionTime, xFrequency = mainNO_ERROR_CHECK_FREQUENCY; +long lCount; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Perform this check at a frequency that indicates whether or not an + error has been found. */ + vTaskDelayUntil( &xLastExecutionTime, xFrequency ); + + /* Check all the other tasks are running without error. */ + if( xAreGenericQueueTasksStillRunning() != pdPASS ) + { + xFrequency = mainERROR_CHECK_FREQUENCY; + } + + if( xAreQueuePeekTasksStillRunning() != pdPASS ) + { + xFrequency = mainERROR_CHECK_FREQUENCY; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdPASS ) + { + xFrequency = mainERROR_CHECK_FREQUENCY; + } + + if( xAreSemaphoreTasksStillRunning() != pdPASS ) + { + xFrequency = mainERROR_CHECK_FREQUENCY; + } + + /* Toggle the LED to show that the check hook function is running. + The toggle freequency will increase if an error has been found in any + task. */ + vParTestToggleLED( mainCHECK_LED ); + + /* Just loop around putting the processor into low power mode 1 for + a while. This is the highest priority task, and this loop does not + cause it to block, so it will remain as the running task. Each time it + runs for the next two seconds it will simply put the processor to sleep. + No other task will run so nothing else will happen. This periodic two + seconds of lower power should be viewable using the Advanced Energy + Monitor on the Energy Micro Gecko board. */ + for( lCount = 0; lCount < mainTWO_SECONDS; lCount++ ) + { + prvLowPowerMode1(); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Initialise the LEDs. */ + vParTestInitialise(); + + /* Configure the LCD. */ + LCD_Init( LCD ); +} +/*-----------------------------------------------------------*/ + +static void prvLowPowerMode1( void ) +{ + /* Clear SLEEPDEEP for EM1 */ + SCB->SCR &= ~( 1 << SCB_SCR_SLEEPDEEP_Pos ); + + /* Power down. */ + __WFI(); +} + + diff --git a/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.cspy.bat b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.cspy.bat new file mode 100644 index 000000000..75c3b8c99 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.cspy.bat @@ -0,0 +1,33 @@ +@REM This bat file has been generated by the IAR Embeddded Workbench +@REM C-SPY interactive debugger,as an aid to preparing a command +@REM line for running the cspybat command line utility with the +@REM appropriate settings. +@REM +@REM After making some adjustments to this file, you can launch cspybat +@REM by typing the name of this file followed by the name of the debug +@REM file (usually an ubrof file). Note that this file is generated +@REM every time a new debug session is initialized, so you may want to +@REM move or rename the file before making changes. +@REM +@REM Note: some command line arguments cannot be properly generated +@REM by this process. Specifically, the plugin which is responsible +@REM for the Terminal I/O window (and other C runtime functionality) +@REM comes in a special version for cspybat, and the name of that +@REM plugin dll is not known when generating this file. It resides in +@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or +@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding +@REM tool chain. Replace the '' parameter +@REM below with the appropriate file name. Other plugins loaded by +@REM C-SPY are usually not needed by, or will not work in, cspybat +@REM but they are listed at the end of this file for reference. + + +"C:\devtools\IAR Systems\Embedded Workbench 5.4\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\config\flashloader\EnergyMicro\FlashEFM32.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\CONFIG\debugger\EnergyMicro\EFM32G890F128.ddf" "--semihosting" "--device=EFM32G890F128" "-d" "jlink" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" + + +@REM Loaded plugins: +@REM C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armlibsupport.dll +@REM C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\CodeCoverage\CodeCoverage.dll +@REM C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\Profiling\Profiling.dll +@REM C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\stack\stack.dll +@REM C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\SymList\SymList.dll diff --git a/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dbgdt b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..8fdf1b1c3 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,79 @@ + + + + + + + + + 201622 + + 20 + 1216 + 324 + 81 + + + + + + + + 231272727 + + + + + + 200100 + 200100100100100 + + + + + + + + TabID-7696-3812 + Debug Log + Debug-Log + + + + TabID-7174-3822 + Build + Build + + + + + 0 + + + TabID-18445-3816 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Energy Micro CodeRTOSDemo/Energy Micro Code/bspRTOSDemo/FreeRTOS source + + + + 0 + + + + + + TextEditor$WS_DIR$\main.c060404540450TextEditor$WS_DIR$\..\..\Source\portable\MemMang\heap_2.c02511064710666TextEditor$WS_DIR$\..\..\..\..\..\..\devtools\IAR Systems\Embedded Workbench 5.4\arm\INC\DLib_Product_string.h03614081408TextEditor$WS_DIR$\..\Common\Minimal\GenQTest.c03211852818528TextEditor$WS_DIR$\ParTest.c06841534153TextEditor$WS_DIR$\bsp\dvk_boardcontrol.c0163588358830100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2740305-2-2200200119048203666182738755601-2-21981682-2-216842001002381203666119048203666 + + + + diff --git a/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dni b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..314bfe70b --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dni @@ -0,0 +1,90 @@ +[DebugChecksum] +Checksum=-346520476 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[InstructionProfiling] +Enabled=_ 0 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=0 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[TraceHelper] +Enabled=0 +ShowSource=1 +[JLinkDriver] +SWOInfo_CpuClock=0x044AA200 +SWOInfo_SWOClockAutoDetect=0 +SWOInfo_JtagSpeed=0x001E8480 +SWOInfo_SWOPrescaler=0x00000024 +SWOInfo_SWOClockWanted=0x001E8480 +SWOInfo_HWTraceEnabled=1 +SWOInfo_TimestampsEnabled=1 +SWOInfo_TimestampsPrescalerIndex=0x00000000 +SWOInfo_TimestampsPrescalerData=0x00000000 +SWOInfo_PCSamplingEnabled=0 +SWOInfo_PCSamplingCYCTAP=0x00000001 +SWOInfo_PCSamplingPOSTCNT=0x0000000F +SWOInfo_DataLogMode=0x00000000 +SWOInfo_CPIEnabled=0 +SWOInfo_EXCEnabled=0 +SWOInfo_SLEEPEnabled=0 +SWOInfo_LSUEnabled=0 +SWOInfo_FOLDEnabled=0 +SWOInfo_EXCTRCEnabled=1 +SWOInfo_ITMPortsEnabled=0x00000000 +SWOInfo_ITMPortsTermIO=0x00000000 +SWOInfo_ITMPortsLogFile=0x00000000 +SWOInfo_ITMLogFile=$PROJ_DIR$\ITM.log +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[DataLog] +LogEnabled=0 +SumEnabled=0 +ShowTimeLog=1 +ShowTimeSum=1 +[InterruptLog] +LogEnabled=1 +SumEnabled=1 +GraphEnabled=0 +ShowTimeLog=1 +ShowTimeSum=1 +SumSortOrder=0 +[TraceHelperExtra] +Enabled=0 +ShowSource=1 +[DriverProfiling] +Enabled=0 +Source=4 +Graph=0 +[Disassemble mode] +mode=1 +[Breakpoints] +Count=0 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.wsdt b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..c78b3c773 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,77 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 228272727 + + + + + + + 20121632481 + + + + + 201622 + + + + + + + + TabID-28378-3630 + Workspace + Workspace + + + RTOSDemoRTOSDemo/DemoRTOSDemo/Output + + + + 0 + + + TabID-11879-3734 + Build + Build + + + + TabID-7638-1339 + Debug Log + Debug-Log + + + + + 0 + + + + + + TextEditor$WS_DIR$\main.c000000100000010000001 + + + + + + + iaridepm.enu1-2-2740302-2-2200200119048203666180952755601-2-21981682-2-216842001002381203666119048203666 + + + + diff --git a/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo_Debug.jlink b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo_Debug.jlink new file mode 100644 index 000000000..e49918734 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo_Debug.jlink @@ -0,0 +1,14 @@ +[FLASH] +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ADUC7020X62" +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 diff --git a/Demo/CORTEX_EFMG890F128_IAR/startup_efm32.s b/Demo/CORTEX_EFMG890F128_IAR/startup_efm32.s new file mode 100644 index 000000000..ef0128092 --- /dev/null +++ b/Demo/CORTEX_EFMG890F128_IAR/startup_efm32.s @@ -0,0 +1,323 @@ +;/*************************************************************************//** +; * @file: startup_efm32.s +; * @purpose: CMSIS Cortex-M3 Core Device Startup File +; * for the Energy Micro 'EFM32G' Device Series +; * @version 1.0.2 +; * @date: 10. September 2009 +; *---------------------------------------------------------------------------- +; * +; * Copyright (C) 2009 ARM Limited. All rights reserved. +; * +; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD vPortSVCHandler + DCD DebugMon_Handler + DCD 0 + DCD xPortPendSVHandler + DCD xPortSysTickHandler + + ; External Interrupts + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 5: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 6: ADC0 Interrupt + DCD DAC0_IRQHandler ; 7: DAC0 Interrupt + DCD I2C0_IRQHandler ; 8: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 9: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 10: TIMER1 Interrupt + DCD TIMER2_IRQHandler ; 11: TIMER2 Interrupt + DCD USART1_RX_IRQHandler ; 12: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 13: USART1_TX Interrupt + DCD USART2_RX_IRQHandler ; 14: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 15: USART2_TX Interrupt + DCD UART0_RX_IRQHandler ; 16: UART0_RX Interrupt + DCD UART0_TX_IRQHandler ; 17: UART0_TX Interrupt + DCD LEUART0_IRQHandler ; 18: LEUART0 Interrupt + DCD LEUART1_IRQHandler ; 19: LEUART1 Interrupt + DCD LETIMER0_IRQHandler ; 20: LETIMER0 Interrupt + DCD PCNT0_IRQHandler ; 21: PCNT0 Interrupt + DCD PCNT1_IRQHandler ; 22: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 23: PCNT2 Interrupt + DCD SYSTICCK_IRQHandler;DCD RTC_IRQHandler ; 24: RTC Interrupt + DCD CMU_IRQHandler ; 25: CMU Interrupt + DCD VCMP_IRQHandler ; 26: VCMP Interrupt + DCD LCD_IRQHandler ; 27: LCD Interrupt + DCD MSC_IRQHandler ; 28: MSC Interrupt + DCD AES_IRQHandler ; 29: AES Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK vPortSVCHandler + SECTION .text:CODE:REORDER(1) +vPortSVCHandler + B vPortSVCHandler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK xPortPendSVHandler + SECTION .text:CODE:REORDER(1) +xPortPendSVHandler + B xPortPendSVHandler + + PUBWEAK SYSTICCK_IRQHandler + SECTION .text:CODE:REORDER(1) +SYSTICCK_IRQHandler + B SYSTICCK_IRQHandler + ; EFM32G specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK UART0_RX_IRQHandler + SECTION .text:CODE:REORDER(1) +UART0_RX_IRQHandler + B UART0_RX_IRQHandler + + PUBWEAK UART0_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +UART0_TX_IRQHandler + B UART0_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK LEUART1_IRQHandler + SECTION .text:CODE:REORDER(1) +LEUART1_IRQHandler + B LEUART1_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK xPortSysTickHandler + SECTION .text:CODE:REORDER(1) +xPortSysTickHandler + B xPortSysTickHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + END -- 2.39.5