From 444f202360fb50a1c461ab4b57daa59d05fc8fdf Mon Sep 17 00:00:00 2001
From: Mark Vels <mark.vels@team-embedded.nl>
Date: Tue, 1 Nov 2011 13:29:11 +0100
Subject: [PATCH] tx27stk5: add board init support for KaRo TX27 CPU module

This patch adds support for a KaRo TX27 CPU module on a StarterkitV base board.
The register settings have been extracted from a RedBoot distribution
that is distributed along with the hardware by KaRo.

This setup has been tested with a JTAGKey. The testing has been focussed
on loading a program into memory and start execution.
Although the flash seems to be correctly detected, no effort has been put
in testing the NAND programming yet.

Change-Id: Ib17763f1e3ecacd0eb9b5fdc32f8cba7a5e59be5
Signed-off-by: Mark Vels <mark.vels@team-embedded.nl>
Reviewed-on: http://openocd.zylin.com/158
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
---
 tcl/board/tx27_stk5.cfg | 64 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 tcl/board/tx27_stk5.cfg

diff --git a/tcl/board/tx27_stk5.cfg b/tcl/board/tx27_stk5.cfg
new file mode 100644
index 00000000..962788cb
--- /dev/null
+++ b/tcl/board/tx27_stk5.cfg
@@ -0,0 +1,64 @@
+# KaRo TX27 CPU Module on a StarterkitV base board
+#
+# http://www.karo-electronics.com/tx27.html
+#
+source [find target/imx27.cfg]
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { tx27_init }
+
+proc tx27_init { } {
+	# This setup puts RAM at 0xA0000000
+	# init_aipi (AIPI1.PSR0, AIPI2.PSR0, AIPI1.PSR1 and AIPI2.PSR1)
+	mww 0x10000000 0x20040304
+	mww 0x10020000 0x00000000
+	mww 0x10000004 0xDFFBFCFB
+	mww 0x10020004 0xFFFFFFFF
+
+	sleep 100
+
+	#init_max ( PORT0.MPR, #PORT0.AMPR, #PORT1.MPR, #PORT1.AMPR, #PORT2.MPR, #PORT2.AMPR)
+	mww 0x1003F000 0x00302145
+	mww 0x1003F004 0x00302145
+	mww 0x1003F100 0x00302145
+	mww 0x1003F104 0x00302145
+	mww 0x1003F200 0x00302145
+	mww 0x1003F204 0x00302145
+
+	#init_drive_strength (#DSCR3, #DSCR5, #DSCR6, #DSCR7, #DSCR8 )
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
+
+	#init_sdram_speed
+	#mww 0xD8001010 0x00000004
+	mww 0xD8001010 0x00000024
+
+	mww 0xD8001004 0x00395729
+
+	mww 0xD8001000 0x92120000
+	mww 0xA0000400 0x0
+
+	mww 0xD8001000 0xA2120000
+	mww 0xA0000000 0x0
+	mww 0xA0000000 0x0
+
+	mww 0xD8001000 0xB2120000
+	mdb 0xA0000000
+	mdb 0xA0000033
+
+	mww 0xD8001000 0x82126485
+
+	# =============================================
+	# Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz)
+	# =============================================
+	mww 0xD8002000 0x23524E80
+	mww 0xD8002004 0x10000D03
+	mww 0xD8002008 0x00720900
+
+	nand probe 0
+}
+
+nand device tx27.nand imx27 $_TARGETNAME hwecc
-- 
2.39.5