From 4fa3cc7746d661f048f39a53c39b692369426e24 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Tue, 22 Jun 2010 12:49:56 +0200
Subject: [PATCH] am3517 evm: use physical write to memory while target is
 running
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 tcl/board/am3517evm.cfg | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tcl/board/am3517evm.cfg b/tcl/board/am3517evm.cfg
index a639fa67..db762557 100644
--- a/tcl/board/am3517evm.cfg
+++ b/tcl/board/am3517evm.cfg
@@ -76,20 +76,20 @@ proc omap3_dbginit {target} {
      # General Cortex A8 debug initialisation
      cortex_a8 dbginit
      # Enable DBGU signal for OMAP353x
-     $target mww 0x5401d030 0x00002000
+     $target mww phys 0x5401d030 0x00002000
 }
 
 # be absolutely certain the JTAG clock will work with the worst-case
 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
 # OK to speed up *after* PLL and clock tree setup.
 
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10; halt; halt }
+$_TARGETNAME configure -event "reset-start" { adapter_khz 10}
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
 # would issue.  RST_DPLL3 (4) is a cold reset.
 set PRM_RSTCTRL 0x48307250
-$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2"
 
 $_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME; adapter_khz 1000"
 
-- 
2.39.5