From 595dc1e162e2d8dce6a97a0199554d59b2589a5f Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 16 Feb 2016 17:03:51 +0900
Subject: [PATCH] ARM: dts: uniphier: add GPIO controller nodes

Make the GPIO driver really active.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/dts/uniphier-ph1-ld4.dtsi     | 112 ++++++++++++++
 arch/arm/dts/uniphier-ph1-pro4.dtsi    | 203 +++++++++++++++++++++++++
 arch/arm/dts/uniphier-ph1-pro5.dtsi    | 203 +++++++++++++++++++++++++
 arch/arm/dts/uniphier-ph1-sld3.dtsi    | 112 ++++++++++++++
 arch/arm/dts/uniphier-ph1-sld8.dtsi    | 112 ++++++++++++++
 arch/arm/dts/uniphier-proxstream2.dtsi | 196 ++++++++++++++++++++++++
 6 files changed, 938 insertions(+)

diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 7c8759f929..f13c6db271 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -56,6 +56,118 @@
 		cache-level = <2>;
 	};
 
+	port0x: gpio@55000008 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000008 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port1x: gpio@55000010 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000010 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port2x: gpio@55000018 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000018 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port3x: gpio@55000020 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000020 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port4: gpio@55000028 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000028 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port5x: gpio@55000030 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000030 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port6x: gpio@55000038 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000038 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port7x: gpio@55000040 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000040 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port8x: gpio@55000048 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000048 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port9x: gpio@55000050 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000050 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port10x: gpio@55000058 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000058 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port11x: gpio@55000060 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000060 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port12x: gpio@55000068 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000068 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port13x: gpio@55000070 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000070 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port14x: gpio@55000078 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000078 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port16x: gpio@55000088 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000088 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	i2c0: i2c@58400000 {
 		compatible = "socionext,uniphier-i2c";
 		status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index cb5b8f1a86..6637aeaa07 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -64,6 +64,209 @@
 		cache-level = <2>;
 	};
 
+	port0x: gpio@55000008 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000008 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port1x: gpio@55000010 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000010 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port2x: gpio@55000018 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000018 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port3x: gpio@55000020 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000020 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port4: gpio@55000028 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000028 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port5x: gpio@55000030 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000030 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port6x: gpio@55000038 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000038 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port7x: gpio@55000040 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000040 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port8x: gpio@55000048 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000048 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port9x: gpio@55000050 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000050 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port10x: gpio@55000058 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000058 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port11x: gpio@55000060 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000060 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port12x: gpio@55000068 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000068 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port13x: gpio@55000070 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000070 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port14x: gpio@55000078 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000078 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port17x: gpio@550000a0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000a0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port18x: gpio@550000a8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000a8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port19x: gpio@550000b0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000b0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port20x: gpio@550000b8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000b8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port21x: gpio@550000c0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000c0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port22x: gpio@550000c8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000c8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port23x: gpio@550000d0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000d0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port24x: gpio@550000d8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000d8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port25x: gpio@550000e0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000e0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port26x: gpio@550000e8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000e8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port27x: gpio@550000f0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000f0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port28x: gpio@550000f8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000f8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port29x: gpio@55000100 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000100 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port30x: gpio@55000108 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000108 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	i2c0: i2c@58780000 {
 		compatible = "socionext,uniphier-fi2c";
 		status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 087b25a950..67a435e913 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -76,6 +76,209 @@
 		cache-level = <3>;
 	};
 
+	port0x: gpio@55000008 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000008 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port1x: gpio@55000010 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000010 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port2x: gpio@55000018 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000018 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port3x: gpio@55000020 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000020 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port4: gpio@55000028 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000028 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port5x: gpio@55000030 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000030 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port6x: gpio@55000038 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000038 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port7x: gpio@55000040 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000040 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port8x: gpio@55000048 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000048 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port9x: gpio@55000050 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000050 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port10x: gpio@55000058 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000058 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port11x: gpio@55000060 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000060 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port12x: gpio@55000068 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000068 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port13x: gpio@55000070 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000070 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port14x: gpio@55000078 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000078 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port17x: gpio@550000a0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000a0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port18x: gpio@550000a8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000a8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port19x: gpio@550000b0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000b0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port20x: gpio@550000b8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000b8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port21x: gpio@550000c0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000c0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port22x: gpio@550000c8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000c8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port23x: gpio@550000d0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000d0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port24x: gpio@550000d8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000d8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port25x: gpio@550000e0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000e0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port26x: gpio@550000e8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000e8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port27x: gpio@550000f0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000f0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port28x: gpio@550000f8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000f8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port29x: gpio@55000100 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000100 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port30x: gpio@55000108 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000108 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	i2c0: i2c@58780000 {
 		compatible = "socionext,uniphier-fi2c";
 		status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index e01bd30345..9a6ca575bd 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -111,6 +111,118 @@
 			clock-frequency = <36864000>;
 		};
 
+		port0x: gpio@55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port1x: gpio@55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port2x: gpio@55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port3x: gpio@55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port4: gpio@55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port5x: gpio@55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port6x: gpio@55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port7x: gpio@55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port8x: gpio@55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port9x: gpio@55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port10x: gpio@55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port11x: gpio@55000060 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000060 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port12x: gpio@55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port13x: gpio@55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port14x: gpio@55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		port16x: gpio@55000088 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000088 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
 		i2c0: i2c@58400000 {
 			compatible = "socionext,uniphier-i2c";
 			status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index f93db83661..985848a027 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -56,6 +56,118 @@
 		cache-level = <2>;
 	};
 
+	port0x: gpio@55000008 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000008 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port1x: gpio@55000010 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000010 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port2x: gpio@55000018 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000018 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port3x: gpio@55000020 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000020 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port4: gpio@55000028 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000028 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port5x: gpio@55000030 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000030 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port6x: gpio@55000038 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000038 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port7x: gpio@55000040 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000040 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port8x: gpio@55000048 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000048 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port9x: gpio@55000050 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000050 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port10x: gpio@55000058 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000058 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port11x: gpio@55000060 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000060 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port12x: gpio@55000068 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000068 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port13x: gpio@55000070 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000070 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port14x: gpio@55000078 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000078 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port16x: gpio@55000088 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000088 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	i2c0: i2c@58400000 {
 		compatible = "socionext,uniphier-i2c";
 		status = "disabled";
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index 2d324f95a4..21fad0cdee 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -78,6 +78,202 @@
 		cache-level = <2>;
 	};
 
+	port0x: gpio@55000008 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000008 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port1x: gpio@55000010 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000010 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port2x: gpio@55000018 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000018 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port3x: gpio@55000020 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000020 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port4: gpio@55000028 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000028 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port5x: gpio@55000030 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000030 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port6x: gpio@55000038 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000038 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port7x: gpio@55000040 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000040 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port8x: gpio@55000048 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000048 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port9x: gpio@55000050 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000050 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port10x: gpio@55000058 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000058 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port12x: gpio@55000068 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000068 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port13x: gpio@55000070 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000070 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port14x: gpio@55000078 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000078 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port15x: gpio@55000080 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000080 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port16x: gpio@55000088 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000088 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port17x: gpio@550000a0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000a0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port18x: gpio@550000a8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000a8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port19x: gpio@550000b0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000b0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port20x: gpio@550000b8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000b8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port21x: gpio@550000c0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000c0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port22x: gpio@550000c8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000c8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port23x: gpio@550000d0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000d0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port24x: gpio@550000d8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000d8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port25x: gpio@550000e0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000e0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port26x: gpio@550000e8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000e8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port27x: gpio@550000f0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000f0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port28x: gpio@550000f8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000f8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	i2c0: i2c@58780000 {
 		compatible = "socionext,uniphier-fi2c";
 		status = "disabled";
-- 
2.39.5