From 5b457d00730d4aa0c6450d21a9104723e606fb98 Mon Sep 17 00:00:00 2001 From: Grant Erickson Date: Wed, 9 Jul 2008 11:55:46 -0700 Subject: [PATCH] PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r) While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in the 405EX(r), SDRAM_MCSTAT has a different DCR value. Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF which causes SDRAM initialization to periodically fail since it can prematurely indicate SDRAM ready status. Signed-off-by: Grant Erickson Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index cdccd8fe6f..59f1c30839 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -354,7 +354,11 @@ /* * Memory controller registers */ +#ifndef CONFIG_405EX #define SDRAM_MCSTAT 0x14 /* memory controller status */ +#else +#define SDRAM_MCSTAT 0x1F /* memory controller status */ +#endif #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ -- 2.39.5