From 5c035e322f20a99679f626bb4b99c047b46d722f Mon Sep 17 00:00:00 2001 From: Matthias Welwarsky Date: Wed, 20 Sep 2017 14:09:28 +0200 Subject: [PATCH] tcl/board: add board configuration for NXP IMX7SABRE configuration also contains a reset-init procedure that disables the watchdog and initilizes the boards DDR memory so that you can upload baremetal (e.g. boot loader) code into DDR and start it from there. Change-Id: I4d2311b3708a5fcb5174a3447f34ae3904de7243 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/4227 Tested-by: jenkins Reviewed-by: Matthias Welwarsky --- tcl/board/nxp_imx7sabre.cfg | 114 ++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 tcl/board/nxp_imx7sabre.cfg diff --git a/tcl/board/nxp_imx7sabre.cfg b/tcl/board/nxp_imx7sabre.cfg new file mode 100644 index 00000000..25b7b878 --- /dev/null +++ b/tcl/board/nxp_imx7sabre.cfg @@ -0,0 +1,114 @@ +# NXP IMX7SABRE board +# use on-board JTAG header +transport select jtag + +# set a safe speed, can be overridden +adapter_khz 1000 + +# reset configuration has TRST and SRST support +reset_config trst_and_srst srst_push_pull +# need at least 100ms delay after SRST release for JTAG +adapter_nsrst_delay 100 + +# source the target file +source [find target/imx7.cfg] +# import mrw proc +source [find mem_helper.tcl] + +# function to disable the on-chip watchdog +proc imx7_disable_wdog { } { + # echo "disable watchdog power-down counter" + mwh phys 0x30280008 0x00 +} + +proc imx7_uart_dbgconf { } { + # disable response to debug_req signal for uart1 + mww phys 0x308600b4 0x0a60 +} + +proc check_bits_set_32 { addr mask } { + while { [expr [mrw $addr] & $mask == 0] } { } +} + +proc apply_dcd { } { + # echo "apply dcd" + + mww phys 0x30340004 0x4F400005 + # Clear then set bit30 to ensure exit from DDR retention + mww phys 0x30360388 0x40000000 + mww phys 0x30360384 0x40000000 + + mww phys 0x30391000 0x00000002 + mww phys 0x307a0000 0x01040001 + mww phys 0x307a01a0 0x80400003 + mww phys 0x307a01a4 0x00100020 + mww phys 0x307a01a8 0x80100004 + mww phys 0x307a0064 0x00400046 + mww phys 0x307a0490 0x00000001 + mww phys 0x307a00d0 0x00020083 + mww phys 0x307a00d4 0x00690000 + mww phys 0x307a00dc 0x09300004 + mww phys 0x307a00e0 0x04080000 + mww phys 0x307a00e4 0x00100004 + mww phys 0x307a00f4 0x0000033f + mww phys 0x307a0100 0x09081109 + mww phys 0x307a0104 0x0007020d + mww phys 0x307a0108 0x03040407 + mww phys 0x307a010c 0x00002006 + mww phys 0x307a0110 0x04020205 + mww phys 0x307a0114 0x03030202 + mww phys 0x307a0120 0x00000803 + mww phys 0x307a0180 0x00800020 + mww phys 0x307a0184 0x02000100 + mww phys 0x307a0190 0x02098204 + mww phys 0x307a0194 0x00030303 + mww phys 0x307a0200 0x00000016 + mww phys 0x307a0204 0x00171717 + mww phys 0x307a0214 0x04040404 + mww phys 0x307a0218 0x0f040404 + mww phys 0x307a0240 0x06000604 + mww phys 0x307a0244 0x00000001 + mww phys 0x30391000 0x00000000 + mww phys 0x30790000 0x17420f40 + mww phys 0x30790004 0x10210100 + mww phys 0x30790010 0x00060807 + mww phys 0x307900b0 0x1010007e + mww phys 0x3079009c 0x00000d6e + mww phys 0x30790020 0x08080808 + mww phys 0x30790030 0x08080808 + mww phys 0x30790050 0x01000010 + mww phys 0x30790050 0x00000010 + + mww phys 0x307900c0 0x0e407304 + mww phys 0x307900c0 0x0e447304 + mww phys 0x307900c0 0x0e447306 + + check_bits_set_32 0x307900c4 0x1 + + mww phys 0x307900c0 0x0e447304 + mww phys 0x307900c0 0x0e407304 + + + mww phys 0x30384130 0x00000000 + mww phys 0x30340020 0x00000178 + mww phys 0x30384130 0x00000002 + mww phys 0x30790018 0x0000000f + + check_bits_set_32 0x307a0004 0x1 +} + +# disable internal reset-assert handling to +# allow reset-init to work +$_TARGETNAME.0 configure -event reset-assert "" +$_TARGETNAME.1 configure -event reset-assert "" +$_TARGETNAME_2 configure -event reset-assert "" + +$_TARGETNAME.0 configure -event reset-init { + global _CHIPNAME + imx7_disable_wdog + imx7_uart_dbgconf + apply_dcd + $_CHIPNAME.dap memaccess 0 +} + +target smp $_TARGETNAME.0 $_TARGETNAME.1 -- 2.39.5