From 5f405e7fa0c4baf4cc57a82d2fcddb86789cfaed Mon Sep 17 00:00:00 2001 From: Schuyler Patton Date: Fri, 8 Apr 2016 16:53:44 -0500 Subject: [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings Update EMIF data based on recommendations from the now standard TI EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB data sheet Update T_RRD from 5 to 6 based on AM57xx TRM - Minimum number of DDR cycles from activate to ativate for a different bank, minus 1. Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR clocks cycles for which SDRAM must remain in self refresh, minus 1. Signed-off-by: Schuyler Patton Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Reviewed-by: Tom Rini --- board/ti/am57xx/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index a5f02e6390..02925f639f 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -131,9 +131,9 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_config2 = 0x08000000, .ref_ctrl = 0x000040F1, .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xcccf36ab, + .sdram_tim1 = 0xcccf36b3, .sdram_tim2 = 0x308f7fda, - .sdram_tim3 = 0x409f88a8, + .sdram_tim3 = 0x407f88a8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000, -- 2.39.5