From 5f7bbd13a89940fc349e8ce63566e205d8514a62 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 4 Jan 2011 18:01:49 -0600 Subject: [PATCH] powerpc/85xx: Convert MPC8568MDS to use common SRIO init code Signed-off-by: Kumar Gala --- board/freescale/mpc8568mds/law.c | 3 +-- include/configs/MPC8568MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index e24b72bfe0..c5cf7ba812 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -50,7 +50,6 @@ */ struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a491650ab9..f684e79695 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007, 2010 Freescale Semiconductor. + * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +35,9 @@ #define CONFIG_SYS_TEXT_BASE 0xfff80000 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller */ #define CONFIG_PCIE1 1 /* PCIE controller */ @@ -303,9 +306,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ -#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #ifdef CONFIG_QE /* -- 2.39.5