From 67ceefa79b86d9d72b7487005a6a8a61cd6a1d66 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 5 Jul 2010 04:55:05 -0400 Subject: [PATCH] Blackfin: convert plat-nand code to GPIO framework Use the new GPIO framework code in both the Blackfin arch and the nand_plat driver to simplify things greatly. Signed-off-by: Mike Frysinger --- include/configs/bf537-pnav.h | 9 +-------- include/configs/bf537-stamp.h | 9 +-------- include/configs/bf561-acvilon.h | 8 +------- include/configs/ip04.h | 10 +--------- 4 files changed, 4 insertions(+), 32 deletions(-) diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index cf40d06b88..73ad95efe2 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -132,7 +132,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF12 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -141,13 +140,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12 /* diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 92ceb3815b..64e86d64ff 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -157,7 +157,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF3 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -166,13 +165,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTFIO() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \ - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3 /* diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index 0be170c3ee..ed8d9443b3 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -145,7 +145,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) -#define BFIN_NAND_READY PF10 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -154,12 +153,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \ - bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 /* diff --git a/include/configs/ip04.h b/include/configs/ip04.h index 425a745408..c024d78c18 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -116,7 +116,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF10 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -125,14 +124,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \ - bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \ - bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 /* -- 2.39.5