From 6ab8a2b0ee7541f6e44fd8dca8cbacd8b7f45e65 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 9 May 2018 00:18:38 +0200 Subject: [PATCH] apalis_t30: describe pcie ports Add some more comments describing the various PCIe ports available. Signed-off-by: Marcel Ziswiler Signed-off-by: Tom Warren --- arch/arm/dts/tegra30-apalis.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 0b84dae215..0852d8dc53 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -43,16 +43,19 @@ vddio-pex-ctl-supply = <&sys_3v3_reg>; hvdd-pex-supply = <&sys_3v3_reg>; + /* Apalis Type Specific 4 Lane PCIe */ pci@1,0 { /* TS_DIFF1/2/3/4 left disabled */ nvidia,num-lanes = <4>; }; + /* Apalis PCIe */ pci@2,0 { /* PCIE1_RX/TX left disabled */ nvidia,num-lanes = <1>; }; + /* I210 Gigabit Ethernet Controller (On-module) */ pci@3,0 { status = "okay"; nvidia,num-lanes = <1>; -- 2.39.5