From 6b7a5cca0b93511acff5c89a812b28baa75c596a Mon Sep 17 00:00:00 2001 From: rtel Date: Thu, 21 Feb 2019 18:08:36 +0000 Subject: [PATCH] Update version number in +TCP code. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2642 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- New - FreeRTOS+TCP.url => FreeRTOS+TCP.url | 0 .../Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c | 2 +- .../Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c | 2 +- .../Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c | 4 +- .../Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c | 7 +- .../FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c | 4 +- .../FreeRTOS_Stream_Buffer.c | 2 +- .../FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c | 4 +- .../FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c | 21 +- .../FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c | 2 +- .../Source/FreeRTOS-Plus-TCP/History.txt | 4 + .../include/FreeRTOSIPConfigDefaults.h | 2 +- .../FreeRTOS-Plus-TCP/include/FreeRTOS_ARP.h | 2 +- .../FreeRTOS-Plus-TCP/include/FreeRTOS_DHCP.h | 2 +- .../FreeRTOS-Plus-TCP/include/FreeRTOS_DNS.h | 2 +- .../FreeRTOS-Plus-TCP/include/FreeRTOS_IP.h | 2 +- .../include/FreeRTOS_IP_Private.h | 2 +- .../include/FreeRTOS_Sockets.h | 2 +- .../include/FreeRTOS_Stream_Buffer.h | 2 +- .../include/FreeRTOS_TCP_IP.h | 2 +- .../include/FreeRTOS_TCP_WIN.h | 5 +- .../include/FreeRTOS_UDP_IP.h | 2 +- .../include/FreeRTOS_errno_TCP.h | 2 +- .../include/IPTraceMacroDefaults.h | 2 +- .../include/NetworkBufferManagement.h | 2 +- .../include/NetworkInterface.h | 2 +- .../BufferManagement/BufferAllocation_1.c | 2 +- .../BufferManagement/BufferAllocation_2.c | 2 +- .../portable/Compiler/GCC/pack_struct_end.h | 2 +- .../portable/Compiler/GCC/pack_struct_start.h | 2 +- .../portable/Compiler/IAR/pack_struct_end.h | 2 +- .../portable/Compiler/IAR/pack_struct_start.h | 2 +- .../portable/Compiler/MSVC/pack_struct_end.h | 2 +- .../Compiler/MSVC/pack_struct_start.h | 2 +- .../Compiler/Renesas/pack_struct_end.h | 2 +- .../Compiler/Renesas/pack_struct_start.h | 2 +- .../ATSAM4E/NetworkInterface.c | 2 +- .../LPC17xx/NetworkInterface.c | 2 +- .../LPC18xx/NetworkInterface.c | 231 +- .../NetworkInterface/SH2A/NetworkInterface.c | 2 +- .../STM32F7xx/NetworkInterface.c | 2 +- .../STM32Fxx/NetworkInterface.c | 282 ++- .../STM32Fxx/stm32f4xx_hal_eth.h | 2225 +---------------- .../WinPCap/NetworkInterface.c | 2 +- .../NetworkInterface/Zynq/NetworkInterface.c | 68 +- .../NetworkInterface/Zynq/uncached_memory.c | 29 +- .../NetworkInterface/Zynq/x_emacpsif_dma.c | 84 +- .../NetworkInterface/Zynq/x_emacpsif_hw.c | 10 +- .../Zynq/x_emacpsif_physpeed.c | 58 +- .../ksz8851snl/NetworkInterface.c | 2 +- 50 files changed, 499 insertions(+), 2605 deletions(-) rename New - FreeRTOS+TCP.url => FreeRTOS+TCP.url (100%) diff --git a/New - FreeRTOS+TCP.url b/FreeRTOS+TCP.url similarity index 100% rename from New - FreeRTOS+TCP.url rename to FreeRTOS+TCP.url diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c index b31b76894..ed34d9aac 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c index 8e475bf73..62cfd874b 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c index ab33e2cf7..925cec929 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -1340,7 +1340,7 @@ TickType_t xTimeoutTime = pdMS_TO_TICKS( 200 ); { BaseType_t x; BaseType_t xFound = pdFALSE; - uint32_t ulCurrentTimeSeconds = ( xTaskGetTickCount() / portTICK_PERIOD_MS ) / 1000UL; + uint32_t ulCurrentTimeSeconds = ( xTaskGetTickCount() / portTICK_PERIOD_MS ) / 1000; static BaseType_t xFreeEntry = 0; /* For each entry in the DNS cache table. */ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c index 996b52838..325a69ac4 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -1288,6 +1288,11 @@ static void prvProcessNetworkDownEvent( void ) } #endif + /* Per the ARP Cache Validation section of https://tools.ietf.org/html/rfc1122, + treat network down as a "delivery problem" and flush the ARP cache for this + interface. */ + FreeRTOS_ClearARP( ); + /* The network has been disconnected (or is being initialised for the first time). Perform whatever hardware processing is necessary to bring it up again, or wait for it to be available again. This is hardware dependent. */ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c index 24f75e84b..ce03f6136 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -3339,7 +3339,7 @@ void vSocketWakeUpUser( FreeRTOS_Socket_t *pxSocket ) } else { - FreeRTOS_printf( ( "Prot Port IP-Remote : Port R/T Status Alive tmout Child\n" ) ); + FreeRTOS_printf( ( "Prot Port IP-Remote : Port R/T Status Alive tmout Child\n" ) ); for( pxIterator = ( ListItem_t * ) listGET_HEAD_ENTRY( &xBoundTCPSocketsList ); pxIterator != ( ListItem_t * ) listGET_END_MARKER( &xBoundTCPSocketsList ); pxIterator = ( ListItem_t * ) listGET_NEXT( pxIterator ) ) diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c index 7729582e5..f903fadc1 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c index 8148846b3..7ec07336c 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -1197,7 +1197,7 @@ UBaseType_t uxNewMSS; else if( pucPtr[ 0 ] == TCP_OPT_MSS ) { /* Confirm that the option fits in the remaining buffer space. */ - if( ( xRemainingOptionsBytes < TCP_OPT_MSS_LEN ) || ( pucPtr[ 1 ] != TCP_OPT_MSS_LEN ) ) + if( ( xRemainingOptionsBytes < TCP_OPT_MSS_LEN )|| ( pucPtr[ 1 ] != TCP_OPT_MSS_LEN ) ) { break; } diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c index 11dc00f01..93fde9590 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -199,7 +199,7 @@ extern void vListInsertGeneric( List_t * const pxList, ListItem_t * const pxNewL /*-----------------------------------------------------------*/ -/* TCP segement pool. */ +/* TCP segment pool. */ #if( ipconfigUSE_TCP_WIN == 1 ) static TCPSegment_t *xTCPSegments = NULL; #endif /* ipconfigUSE_TCP_WIN == 1 */ @@ -673,6 +673,23 @@ const int32_t l500ms = 500; } /*-----------------------------------------------------------*/ +#if( ipconfigUSE_TCP_WIN == 1 ) + + void vTCPSegmentCleanup( void ) + { + /* Free and clear the TCP segments pointer. This function should only be called + * once FreeRTOS+TCP will no longer be used. No thread-safety is provided for this + * function. */ + if( xTCPSegments != NULL ) + { + vPortFreeLarge( xTCPSegments ); + xTCPSegments = NULL; + } + } + +#endif /* ipconfgiUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + /*============================================================================= * * ###### # # diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c index 532b89b91..87d60fcb7 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/History.txt b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/History.txt index b485a2833..07ad698a2 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/History.txt +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/History.txt @@ -1,3 +1,7 @@ +Changes in V2.0.11 + + + Updates some drivers in the portable layer. + Changes between 160919 and 180821 releases: + Multiple security improvements and fixes in packet parsing routines, DNS diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOSIPConfigDefaults.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOSIPConfigDefaults.h index 4b3a74115..ebe531ea0 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOSIPConfigDefaults.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOSIPConfigDefaults.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_ARP.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_ARP.h index 5f7e7871f..b9974b460 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_ARP.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_ARP.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DHCP.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DHCP.h index 3cdb4b6a8..64421e5ff 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DHCP.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DHCP.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DNS.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DNS.h index 9ab08873e..cf59577e8 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DNS.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DNS.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP.h index 11342aeeb..1ac4ed77c 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP_Private.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP_Private.h index 254201d19..d6784cf6d 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP_Private.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP_Private.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Sockets.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Sockets.h index a8a5710b7..630e681c6 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Sockets.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Sockets.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Stream_Buffer.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Stream_Buffer.h index 1d088e716..1ebb86d8d 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Stream_Buffer.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Stream_Buffer.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_IP.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_IP.h index 4a7aa00f9..503fa101b 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_IP.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_IP.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_WIN.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_WIN.h index 92b790297..691332289 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_WIN.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_WIN.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -154,6 +154,9 @@ void vTCPWindowDestroy( TCPWindow_t *pxWindow ); /* Initialize a window */ void vTCPWindowInit( TCPWindow_t *pxWindow, uint32_t ulAckNumber, uint32_t ulSequenceNumber, uint32_t ulMSS ); +/* Clean up allocated segments. Should only be called when FreeRTOS+TCP will no longer be used. */ +void vTCPSegmentCleanup( void ); + /*============================================================================= * * Rx functions diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_UDP_IP.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_UDP_IP.h index ca70b3abd..991595216 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_UDP_IP.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_UDP_IP.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_errno_TCP.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_errno_TCP.h index bb405eaf9..fffe22df0 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_errno_TCP.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_errno_TCP.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/IPTraceMacroDefaults.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/IPTraceMacroDefaults.h index 6f1f5e360..3fa8eab8b 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/IPTraceMacroDefaults.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/IPTraceMacroDefaults.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkBufferManagement.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkBufferManagement.h index e05f0ac8f..8e4f90315 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkBufferManagement.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkBufferManagement.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkInterface.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkInterface.h index f5f246503..2924b7976 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkInterface.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkInterface.h @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_1.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_1.c index f8b04e420..3540b15c2 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_1.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_1.c @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_2.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_2.c index e158e39bb..5647ac695 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_2.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_2.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.7 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_end.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_end.h index 606f7df15..d61b8d003 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_end.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_end.h @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_start.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_start.h index 8893ec01f..5a88f78cf 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_start.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_start.h @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_end.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_end.h index 104ecef17..85e670819 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_end.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_end.h @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_start.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_start.h index f012d9988..15e6eb69b 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_start.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_start.h @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_end.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_end.h index 54dffdde5..19a0f39ef 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_end.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_end.h @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_start.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_start.h index f133207cb..54a3e6885 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_start.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_start.h @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_end.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_end.h index b49313602..c8de043f9 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_end.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_end.h @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_start.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_start.h index 9436de7de..55b2fd5ef 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_start.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_start.h @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/NetworkInterface.c index f7aab8a7a..7d83e07eb 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/NetworkInterface.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/NetworkInterface.c @@ -1,5 +1,5 @@ /* - * FreeRTOS+TCP V2.0.3 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC17xx/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC17xx/NetworkInterface.c index 7799731b4..e0d04e454 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC17xx/NetworkInterface.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC17xx/NetworkInterface.c @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/NetworkInterface.c index c90c401db..ac01d41af 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/NetworkInterface.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/NetworkInterface.c @@ -1,28 +1,27 @@ /* - * FreeRTOS+TCP V2.0.3 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://aws.amazon.com/freertos - * http://www.FreeRTOS.org - */ - +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ /* Standard includes. */ #include @@ -230,121 +229,105 @@ static SemaphoreHandle_t xTXDescriptorSemaphore = NULL; BaseType_t xNetworkInterfaceInitialise( void ) { BaseType_t xReturn = pdPASS; -static BaseType_t xHasInitialised = pdFALSE; - if( xHasInitialised == pdFALSE ) - { - xHasInitialised = pdTRUE; + /* The interrupt will be turned on when a link is established. */ + NVIC_DisableIRQ( ETHERNET_IRQn ); + + /* Disable receive and transmit DMA processes. */ + LPC_ETHERNET->DMA_OP_MODE &= ~( DMA_OM_ST | DMA_OM_SR ); - /* The interrupt will be turned on when a link is established. */ - NVIC_DisableIRQ( ETHERNET_IRQn ); + /* Disable packet reception. */ + LPC_ETHERNET->MAC_CONFIG &= ~( MAC_CFG_RE | MAC_CFG_TE ); - /* Disable receive and transmit DMA processes. */ - LPC_ETHERNET->DMA_OP_MODE &= ~( DMA_OM_ST | DMA_OM_SR ); + /* Call the LPCOpen function to initialise the hardware. */ + Chip_ENET_Init( LPC_ETHERNET ); - /* Disable packet reception. */ - LPC_ETHERNET->MAC_CONFIG &= ~( MAC_CFG_RE | MAC_CFG_TE ); + /* Save MAC address. */ + Chip_ENET_SetADDR( LPC_ETHERNET, ucMACAddress ); - /* Call the LPCOpen function to initialise the hardware. */ - Chip_ENET_Init( LPC_ETHERNET ); + /* Clear all MAC address hash entries. */ + LPC_ETHERNET->MAC_HASHTABLE_HIGH = 0; + LPC_ETHERNET->MAC_HASHTABLE_LOW = 0; - /* Save MAC address. */ - Chip_ENET_SetADDR( LPC_ETHERNET, ucMACAddress ); + #if( ipconfigUSE_LLMNR == 1 ) + { + prvAddMACAddress( xLLMNR_MACAddress ); + } + #endif /* ipconfigUSE_LLMNR == 1 */ - /* Clear all MAC address hash entries. */ - LPC_ETHERNET->MAC_HASHTABLE_HIGH = 0; - LPC_ETHERNET->MAC_HASHTABLE_LOW = 0; + /* Promiscuous flag (PR) and Receive All flag (RA) set to zero. The + registers MAC_HASHTABLE_[LOW|HIGH] will be loaded to allow certain + multi-cast addresses. */ + LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FF_HMC; - #if( ipconfigUSE_LLMNR == 1 ) + #if( configUSE_RMII == 1 ) + { + if( lpc_phy_init( pdTRUE, prvDelay ) != SUCCESS ) { - prvAddMACAddress( xLLMNR_MACAddress ); + xReturn = pdFAIL; } - #endif /* ipconfigUSE_LLMNR == 1 */ - - /* Promiscuous flag (PR) and Receive All flag (RA) set to zero. The - registers MAC_HASHTABLE_[LOW|HIGH] will be loaded to allow certain - multi-cast addresses. */ - LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FF_HMC; - - #if( configUSE_RMII == 1 ) + } + #else + { + #warning This path has not been tested. + if( lpc_phy_init( pdFALSE, prvDelay ) != SUCCESS ) { - if( lpc_phy_init( pdTRUE, prvDelay ) != SUCCESS ) - { - xReturn = pdFAIL; - } + xReturn = pdFAIL; } - #else + } + #endif + + if( xReturn == pdPASS ) + { + /* Guard against the task being created more than once and the + descriptors being initialised more than once. */ + if( xRxHanderTask == NULL ) { - #warning This path has not been tested. - if( lpc_phy_init( pdFALSE, prvDelay ) != SUCCESS ) - { - xReturn = pdFAIL; - } + xReturn = xTaskCreate( prvEMACHandlerTask, "EMAC", nwRX_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xRxHanderTask ); + configASSERT( xReturn ); } - #endif - if( xReturn == pdPASS ) + if( xTXDescriptorSemaphore == NULL ) { - if( xTXDescriptorSemaphore == NULL ) - { - /* Create a counting semaphore, with a value of 'configNUM_TX_DESCRIPTORS' - and a maximum of 'configNUM_TX_DESCRIPTORS'. */ - xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) configNUM_TX_DESCRIPTORS, ( UBaseType_t ) configNUM_TX_DESCRIPTORS ); - configASSERT( xTXDescriptorSemaphore ); - } + /* Create a counting semaphore, with a value of 'configNUM_TX_DESCRIPTORS' + and a maximum of 'configNUM_TX_DESCRIPTORS'. */ + xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) configNUM_TX_DESCRIPTORS, ( UBaseType_t ) configNUM_TX_DESCRIPTORS ); + configASSERT( xTXDescriptorSemaphore ); + } - /* Enable MAC interrupts. */ - LPC_ETHERNET->DMA_INT_EN = nwDMA_INTERRUPT_MASK; + /* Enable MAC interrupts. */ + LPC_ETHERNET->DMA_INT_EN = nwDMA_INTERRUPT_MASK; + } - /* Auto-negotiate was already started. Wait for it to complete. */ - xReturn = prvSetLinkSpeed(); + if( xReturn != pdFAIL ) + { + /* Auto-negotiate was already started. Wait for it to complete. */ + xReturn = prvSetLinkSpeed(); - if( xReturn == pdPASS ) - { - /* Initialise the descriptors. */ - prvSetupTxDescriptors(); - prvSetupRxDescriptors(); + if( xReturn == pdPASS ) + { + /* Initialise the descriptors. */ + prvSetupTxDescriptors(); + prvSetupRxDescriptors(); - /* Clear all interrupts. */ - LPC_ETHERNET->DMA_STAT = DMA_ST_ALL; + /* Clear all interrupts. */ + LPC_ETHERNET->DMA_STAT = DMA_ST_ALL; - /* Enable receive and transmit DMA processes. */ - LPC_ETHERNET->DMA_OP_MODE |= DMA_OM_ST | DMA_OM_SR; + /* Enable receive and transmit DMA processes. */ + LPC_ETHERNET->DMA_OP_MODE |= DMA_OM_ST | DMA_OM_SR; - /* Set Receiver / Transmitter Enable. */ - LPC_ETHERNET->MAC_CONFIG |= MAC_CFG_RE | MAC_CFG_TE; + /* Set Receiver / Transmitter Enable. */ + LPC_ETHERNET->MAC_CONFIG |= MAC_CFG_RE | MAC_CFG_TE; - /* Start receive polling. */ - LPC_ETHERNET->DMA_REC_POLL_DEMAND = 1; + /* Start receive polling. */ + LPC_ETHERNET->DMA_REC_POLL_DEMAND = 1; - /* Enable interrupts in the NVIC. */ - NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY ); - NVIC_EnableIRQ( ETHERNET_IRQn ); - } - /* Guard against the task being created more than once and the - descriptors being initialised more than once. */ - if( xRxHanderTask == NULL ) - { - xReturn = xTaskCreate( prvEMACHandlerTask, "EMAC", nwRX_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xRxHanderTask ); - configASSERT( xReturn ); - } + /* Enable interrupts in the NVIC. */ + NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY ); + NVIC_EnableIRQ( ETHERNET_IRQn ); } } - /* Once prvEMACHandlerTask() has started, the variable - 'ulPHYLinkStatus' will be updated by that task. - The IP-task will keep on calling this function untill - it finally returns pdPASS. - Only then can the DHCP-procedure start (if configured). */ - if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != 0 ) - { - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - return xReturn; } /*-----------------------------------------------------------*/ @@ -461,7 +444,7 @@ const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50 ); /* The DMA descriptor will 'own' this Network Buffer, until it has been sent. So don't release it now. */ - bReleaseAfterSend = pdFALSE; + bReleaseAfterSend = false; } #else { @@ -667,6 +650,8 @@ BaseType_t xReturn; } /*-----------------------------------------------------------*/ +uint32_t ulDataAvailable; + configPLACE_IN_SECTION_RAM static BaseType_t prvNetworkInterfaceInput() { @@ -680,7 +665,9 @@ NetworkBufferDescriptor_t *pxDescriptor; #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) NetworkBufferDescriptor_t *pxNewDescriptor; #endif /* ipconfigZERO_COPY_RX_DRIVER */ -IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; +#if( ipconfigUSE_LINKED_RX_MESSAGES == 0 ) + IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; +#endif /* Process each descriptor that is not still in use by the DMA. */ ulStatus = xDMARxDescriptors[ ulNextRxDescriptorToProcess ].STATUS; @@ -690,6 +677,7 @@ IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; if( ( ulStatus & nwRX_STATUS_ERROR_BITS ) != 0 ) { /* There is some reception error. */ + intCount[ 3 ]++; /* Clear error bits. */ ulStatus &= ~( ( uint32_t )nwRX_STATUS_ERROR_BITS ); } @@ -775,10 +763,19 @@ IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; else { iptraceNETWORK_INTERFACE_RECEIVE(); + + /* The data that was available at the top of this + loop has been sent, so is no longer available. */ + ulDataAvailable = pdFALSE; } } } } + else + { + /* The packet is discarded as uninteresting. */ + ulDataAvailable = pdFALSE; + } /* Got here because received data was sent to the IP task or the data contained an error and was discarded. Give the descriptor back to the DMA. */ @@ -825,6 +822,7 @@ const uint32_t ulTxInterruptMask = /* Remember that an RX event has happened. */ ulISREvents |= EMAC_IF_RX_EVENT; vTaskNotifyGiveFromISR( xRxHanderTask, &xHigherPriorityTaskWoken ); + intCount[ 0 ]++; } /* TX group interrupt(s). */ @@ -833,6 +831,7 @@ const uint32_t ulTxInterruptMask = /* Remember that a TX event has happened. */ ulISREvents |= EMAC_IF_TX_EVENT; vTaskNotifyGiveFromISR( xRxHanderTask, &xHigherPriorityTaskWoken ); + intCount[ 1 ]++; } /* Test for 'Abnormal interrupt summary'. */ @@ -880,11 +879,11 @@ const TickType_t xAutoNegotiateDelay = pdMS_TO_TICKS( 5000UL ); if( ( ulPhyStatus & PHY_LINK_FULLDUPLX ) != 0x00 ) { - Chip_ENET_SetDuplex( LPC_ETHERNET, pdTRUE ); + Chip_ENET_SetDuplex( LPC_ETHERNET, true ); } else { - Chip_ENET_SetDuplex( LPC_ETHERNET, pdFALSE ); + Chip_ENET_SetDuplex( LPC_ETHERNET, false ); } xReturn = pdPASS; diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/SH2A/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/SH2A/NetworkInterface.c index de077131f..44d19f3a9 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/SH2A/NetworkInterface.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/SH2A/NetworkInterface.c @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/NetworkInterface.c index 7c05b8679..7de2902f8 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/NetworkInterface.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/NetworkInterface.c @@ -4,7 +4,7 @@ */ /* - * FreeRTOS+TCP V2.0.1 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/NetworkInterface.c index 268273cd9..ab17be237 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/NetworkInterface.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/NetworkInterface.c @@ -4,7 +4,7 @@ */ /* - * FreeRTOS+TCP V2.0.3 + * FreeRTOS+TCP V2.0.11 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -26,8 +26,7 @@ * * http://aws.amazon.com/freertos * http://www.FreeRTOS.org - */ - +*/ /* Standard includes. */ #include @@ -49,13 +48,21 @@ #include "NetworkInterface.h" #include "phyHandling.h" +#define __STM32_HAL_LEGACY 1 + /* ST includes. */ -#ifdef STM32F7xx +#if defined( STM32F7xx ) #include "stm32f7xx_hal.h" -#else +#elif defined( STM32F4xx ) #include "stm32f4xx_hal.h" +#elif defined( STM32F2xx ) + #include "stm32f2xx_hal.h" +#else + #error What part? #endif +#include "stm32fxx_hal_eth.h" + /* Interrupt events to process. Currently only the Rx event is processed although code for other events is included to allow for possible future expansion. */ @@ -69,7 +76,9 @@ expansion. */ ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \ ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T ) - +#ifndef niEMAC_HANDLER_TASK_PRIORITY + #define niEMAC_HANDLER_TASK_PRIORITY configMAX_PRIORITIES - 1 +#endif #define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) /* The bits in the two byte IP header field that make up the fragment offset value. */ @@ -124,7 +133,11 @@ and the index of the PHY in use ( between 0 and 31 ). */ #endif /* STM32F7xx */ #endif /* ipconfigUSE_RMII */ - +#if( ipconfigUSE_RMII != 0 ) + #warning Using RMII, make sure if this is correct +#else + #warning Using MII, make sure if this is correct +#endif /*-----------------------------------------------------------*/ @@ -166,9 +179,9 @@ static void prvDMATxDescListInit( void ); */ static void prvDMARxDescListInit( void ); -/* After packets have been sent, the network -buffers will be released. */ -static void vClearTXBuffers( void ); + /* After packets have been sent, the network + buffers will be released. */ + static void vClearTXBuffers( void ); /*-----------------------------------------------------------*/ @@ -186,10 +199,10 @@ static EthernetPhy_t xPhyObject; /* Ethernet handle. */ static ETH_HandleTypeDef xETH; -/* xTXDescriptorSemaphore is a counting semaphore with -a maximum count of ETH_TXBUFNB, which is the number of -DMA TX descriptors. */ -static SemaphoreHandle_t xTXDescriptorSemaphore = NULL; + /* xTXDescriptorSemaphore is a counting semaphore with + a maximum count of ETH_TXBUFNB, which is the number of + DMA TX descriptors. */ + static SemaphoreHandle_t xTXDescriptorSemaphore = NULL; /* * Note: it is adviced to define both @@ -235,9 +248,6 @@ __attribute__ ((section(".first_data"))) static __IO ETH_DMADescTypeDef *DMATxDescToClear; #endif -/* ucMACAddress as it appears in main.c */ -extern const uint8_t ucMACAddress[ 6 ]; - /* Holds the handle of the task used as a deferred interrupt processor. The handle is used so direct notifications can be sent to the task for all EMAC/DMA related interrupts. */ @@ -289,43 +299,43 @@ BaseType_t xHigherPriorityTaskWoken = pdFALSE; } /*-----------------------------------------------------------*/ -void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth ) -{ -BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - /* This call-back is only useful in case packets are being sent - zero-copy. Once they're sent, the buffers will be released - by the function vClearTXBuffers(). */ - ulISREvents |= EMAC_IF_TX_EVENT; - /* Wakeup the prvEMACHandlerTask. */ - if( xEMACTaskHandle != NULL ) + void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth ) { - vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken ); - portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); - } + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* This call-back is only useful in case packets are being sent + zero-copy. Once they're sent, the buffers will be released + by the function vClearTXBuffers(). */ + ulISREvents |= EMAC_IF_TX_EVENT; + /* Wakeup the prvEMACHandlerTask. */ + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } -} + } /*-----------------------------------------------------------*/ -static void vClearTXBuffers() -{ -__IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc; + static void vClearTXBuffers() + { + __IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc; size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore ); #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) NetworkBufferDescriptor_t *pxNetworkBuffer; uint8_t *ucPayLoad; #endif - /* This function is called after a TX-completion interrupt. - It will release each Network Buffer used in xNetworkInterfaceOutput(). - 'uxCount' represents the number of descriptors given to DMA for transmission. - After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */ - while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) ) - { - if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) ) + /* This function is called after a TX-completion interrupt. + It will release each Network Buffer used in xNetworkInterfaceOutput(). + 'uxCount' represents the number of descriptors given to DMA for transmission. + After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */ + while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) ) { - break; - } + if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) ) + { + break; + } #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) { ucPayLoad = ( uint8_t * )DMATxDescToClear->Buffer1Addr; @@ -342,13 +352,13 @@ size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescr } #endif /* ipconfigZERO_COPY_TX_DRIVER */ - DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr ); + DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr ); - uxCount--; - /* Tell the counting semaphore that one more TX descriptor is available. */ - xSemaphoreGive( xTXDescriptorSemaphore ); + uxCount--; + /* Tell the counting semaphore that one more TX descriptor is available. */ + xSemaphoreGive( xTXDescriptorSemaphore ); + } } -} /*-----------------------------------------------------------*/ BaseType_t xNetworkInterfaceInitialise( void ) @@ -358,11 +368,11 @@ BaseType_t xResult; if( xEMACTaskHandle == NULL ) { - if( xTXDescriptorSemaphore == NULL ) - { - xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB ); - configASSERT( xTXDescriptorSemaphore ); - } + if( xTXDescriptorSemaphore == NULL ) + { + xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB ); + configASSERT( xTXDescriptorSemaphore ); + } /* Initialise ETH */ @@ -373,7 +383,7 @@ BaseType_t xResult; /* Value of PhyAddress doesn't matter, will be probed for. */ xETH.Init.PhyAddress = 0; - xETH.Init.MACAddr = ( uint8_t *) ucMACAddress; + xETH.Init.MACAddr = ( uint8_t *)FreeRTOS_GetMACAddress(); xETH.Init.RxMode = ETH_RXINTERRUPT_MODE; /* using the ETH_CHECKSUM_BY_HARDWARE option: @@ -387,7 +397,7 @@ BaseType_t xResult; } #else { - xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII; + xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII; } #endif /* ipconfigUSE_RMII */ @@ -404,8 +414,8 @@ BaseType_t xResult; memset( &DMATxDscrTab, '\0', sizeof( DMATxDscrTab ) ); memset( &DMARxDscrTab, '\0', sizeof( DMARxDscrTab ) ); - /* Initialize Tx Descriptors list: Chain Mode */ - DMATxDescToClear = DMATxDscrTab; + /* Initialize Tx Descriptors list: Chain Mode */ + DMATxDescToClear = DMATxDscrTab; /* Initialise TX-descriptors. */ prvDMATxDescListInit(); @@ -427,7 +437,7 @@ BaseType_t xResult; possible priority to ensure the interrupt handler can return directly to it. The task's handle is stored in xEMACTaskHandle so interrupts can notify the task when there is something to process. */ - xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xEMACTaskHandle ); + xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, niEMAC_HANDLER_TASK_PRIORITY, &xEMACTaskHandle ); } /* if( xEMACTaskHandle == NULL ) */ if( xPhyObject.ulLinkStatusMask != 0 ) @@ -580,30 +590,37 @@ __IO ETH_DMADescTypeDef *pxDmaTxDesc; /* Do not wait too long for a free TX DMA buffer. */ const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u ); - #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) + /* Open a do {} while ( 0 ) loop to be able to call break. */ + do { - ProtocolPacket_t *pxPacket; - - #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + if( xCheckLoopback( pxDescriptor, bReleaseAfterSend ) != 0 ) { - configASSERT( bReleaseAfterSend != 0 ); + /* The packet has been sent back to the IP-task. + The IP-task will further handle it. + Do not release the descriptor. */ + bReleaseAfterSend = pdFALSE; + break; } - #endif /* ipconfigZERO_COPY_RX_DRIVER */ + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) + { + ProtocolPacket_t *pxPacket; - /* If the peripheral must calculate the checksum, it wants - the protocol checksum to have a value of zero. */ - pxPacket = ( ProtocolPacket_t * ) ( pxDescriptor->pucEthernetBuffer ); + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + configASSERT( bReleaseAfterSend != 0 ); + } + #endif /* ipconfigZERO_COPY_RX_DRIVER */ - if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ipPROTOCOL_ICMP ) - { - pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u; - } - } - #endif + /* If the peripheral must calculate the checksum, it wants + the protocol checksum to have a value of zero. */ + pxPacket = ( ProtocolPacket_t * ) ( pxDescriptor->pucEthernetBuffer ); - /* Open a do {} while ( 0 ) loop to be able to call break. */ - do - { + if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ipPROTOCOL_ICMP ) + { + pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u; + } + } + #endif /* ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM */ if( xPhyObject.ulLinkStatusMask != 0 ) { if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS ) @@ -653,6 +670,15 @@ const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u ); pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS; /* Set frame size */ pxDmaTxDesc->ControlBufferSize = ( ulTransmitSize & ETH_DMATXDESC_TBS1 ); + + #if( NETWORK_BUFFERS_CACHED != 0 ) + { + BaseType_t xlength = CACHE_LINE_SIZE * ( ( ulTransmitSize + NETWORK_BUFFER_HEADER_SIZE + CACHE_LINE_SIZE - 1 ) / CACHE_LINE_SIZE ); + uint32_t *pulBuffer = ( uint32_t )( pxDescriptor->pucEthernetBuffer - NETWORK_BUFFER_HEADER_SIZE ); + cache_clean_invalidate_by_addr( pulBuffer, xlength ); + } + #endif + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN; @@ -787,11 +813,16 @@ uint8_t *pucBuffer; } /* Obtain the size of the packet and put it into the "usReceivedLength" variable. */ - /* In order to make the code easier and faster, only packets in a single buffer - will be accepted. This can be done by making the buffers large enough to - hold a complete Ethernet packet (1536 bytes). */ - if( xReceivedLength > 0ul && xReceivedLength < ETH_RX_BUF_SIZE ) + + /* get received frame */ + if( xReceivedLength > 0ul ) { + /* In order to make the code easier and faster, only packets in a single buffer + will be accepted. This can be done by making the buffers large enough to + hold a complete Ethernet packet (1536 bytes). + Therefore, two sanity checks: */ + configASSERT( xReceivedLength <= ETH_RX_BUF_SIZE ); + if( ( pxDMARxDescriptor->Status & ( ETH_DMARXDESC_CE | ETH_DMARXDESC_IPV4HCE | ETH_DMARXDESC_FT ) ) != ETH_DMARXDESC_FT ) { /* Not an Ethernet frame-type or a checmsum error. */ @@ -893,7 +924,7 @@ uint8_t *pucBuffer; BaseType_t xSTM32_PhyRead( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue ) -{ + { uint16_t usPrevAddress = xETH.Init.PhyAddress; BaseType_t xResult; HAL_StatusTypeDef xHALResult; @@ -911,11 +942,11 @@ HAL_StatusTypeDef xHALResult; xResult = -1; } return xResult; -} + } /*-----------------------------------------------------------*/ BaseType_t xSTM32_PhyWrite( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue ) -{ + { uint16_t usPrevAddress = xETH.Init.PhyAddress; BaseType_t xResult; HAL_StatusTypeDef xHALResult; @@ -925,35 +956,16 @@ HAL_StatusTypeDef xHALResult; xETH.Init.PhyAddress = usPrevAddress; if( xHALResult == HAL_OK ) - { + { xResult = 0; - } - else - { + } + else + { xResult = -1; - } + } return xResult; -} -/*-----------------------------------------------------------*/ - -void phy_test() -{ -BaseType_t xPhyCount; -BaseType_t xPhyIndex; - - vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite ); - xPhyCount = xPhyDiscover( &xPhyObject ); - FreeRTOS_printf( ( "PHY count %ld\n", xPhyCount ) ); - for( xPhyIndex = 0; xPhyIndex < xPhyCount; xPhyIndex++ ) - { - FreeRTOS_printf( ( "PHY[%d] at address %d ( 0x%08X )\n", - xPhyIndex, - xPhyObject.ucPhyIndexes[ xPhyIndex ], - xPhyObject.ulPhyIDs[ xPhyIndex ] ) ); - } - -} +/*-----------------------------------------------------------*/ void vMACBProbePhy( void ) { @@ -976,27 +988,27 @@ static void prvEthernetUpdateConfig( BaseType_t xForce ) { xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) ); - /* Configure the MAC with the Duplex Mode fixed by the - auto-negotiation process. */ + /* Configure the MAC with the Duplex Mode fixed by the + auto-negotiation process. */ if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL ) - { - xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX; - } - else - { - xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX; - } + { + xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX; + } + else + { + xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX; + } - /* Configure the MAC with the speed fixed by the - auto-negotiation process. */ + /* Configure the MAC with the speed fixed by the + auto-negotiation process. */ if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 ) - { - xETH.Init.Speed = ETH_SPEED_10M; - } - else - { - xETH.Init.Speed = ETH_SPEED_100M; - } + { + xETH.Init.Speed = ETH_SPEED_10M; + } + else + { + xETH.Init.Speed = ETH_SPEED_100M; + } } else /* AutoNegotiation Disable */ { @@ -1061,14 +1073,11 @@ BaseType_t xReturn; /* Uncomment this in case BufferAllocation_1.c is used. */ -/* #define niBUFFER_1_PACKET_SIZE 1536 -static __attribute__ ((section(".first_data"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) ); - void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ) { - +static __attribute__ ((section(".first_data"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) ); uint8_t *ucRAMBuffer = ucNetworkPackets; uint32_t ul; @@ -1079,7 +1088,6 @@ uint32_t ul; ucRAMBuffer += niBUFFER_1_PACKET_SIZE; } } -*/ /*-----------------------------------------------------------*/ static void prvEMACHandlerTask( void *pvParameters ) @@ -1157,9 +1165,9 @@ const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); { /* Code to release TX buffers if zero-copy is used. */ ulISREvents &= ~EMAC_IF_TX_EVENT; - /* Check if DMA packets have been delivered. */ - vClearTXBuffers(); - } + /* Check if DMA packets have been delivered. */ + vClearTXBuffers(); + } if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 ) { @@ -1167,10 +1175,10 @@ const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); ulISREvents &= ~EMAC_IF_ERR_EVENT; } if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 ) - { + { /* Something has changed to a Link Status, need re-check. */ - prvEthernetUpdateConfig( pdFALSE ); - } + prvEthernetUpdateConfig( pdFALSE ); + } } } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h index d2a72b010..93b9caff0 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h @@ -1,2225 +1,6 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_eth.h - * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 - * @brief Header file of ETH HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_ETH_H -#define __STM32F4xx_HAL_ETH_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup ETH - * @{ - */ - -/** @addtogroup ETH_Private_Macros - * @{ - */ -#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) -#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ - ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) -#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ - ((SPEED) == ETH_SPEED_100M)) -#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ - ((MODE) == ETH_MODE_HALFDUPLEX)) -#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ - ((MODE) == ETH_MODE_HALFDUPLEX)) -#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ - ((MODE) == ETH_RXINTERRUPT_MODE)) -#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ - ((MODE) == ETH_RXINTERRUPT_MODE)) -#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ - ((MODE) == ETH_RXINTERRUPT_MODE)) -#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ - ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) -#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ - ((MODE) == ETH_MEDIA_INTERFACE_RMII)) -#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ - ((CMD) == ETH_WATCHDOG_DISABLE)) -#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ - ((CMD) == ETH_JABBER_DISABLE)) -#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_40BIT)) -#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ - ((CMD) == ETH_CARRIERSENCE_DISABLE)) -#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ - ((CMD) == ETH_RECEIVEOWN_DISABLE)) -#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ - ((CMD) == ETH_LOOPBACKMODE_DISABLE)) -#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ - ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) -#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ - ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) -#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ - ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) -#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_1)) -#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ - ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) -#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ - ((CMD) == ETH_RECEIVEAll_DISABLE)) -#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) -#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) -#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ - ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) -#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ - ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) -#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ - ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) -#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) -#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) -#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) -#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ - ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) -#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) -#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ - ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) -#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) -#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) -#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ - ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) -#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) -#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ - ((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ - ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) -#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) -#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ - ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) -#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) -#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ - ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) -#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) -#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) -#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) -#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) -#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) -#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ - ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) -#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ - ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) -#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ - ((CMD) == ETH_FIXEDBURST_DISABLE)) -#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) -#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ - ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) -#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ - ((FLAG) == ETH_DMATXDESC_IC) || \ - ((FLAG) == ETH_DMATXDESC_LS) || \ - ((FLAG) == ETH_DMATXDESC_FS) || \ - ((FLAG) == ETH_DMATXDESC_DC) || \ - ((FLAG) == ETH_DMATXDESC_DP) || \ - ((FLAG) == ETH_DMATXDESC_TTSE) || \ - ((FLAG) == ETH_DMATXDESC_TER) || \ - ((FLAG) == ETH_DMATXDESC_TCH) || \ - ((FLAG) == ETH_DMATXDESC_TTSS) || \ - ((FLAG) == ETH_DMATXDESC_IHE) || \ - ((FLAG) == ETH_DMATXDESC_ES) || \ - ((FLAG) == ETH_DMATXDESC_JT) || \ - ((FLAG) == ETH_DMATXDESC_FF) || \ - ((FLAG) == ETH_DMATXDESC_PCE) || \ - ((FLAG) == ETH_DMATXDESC_LCA) || \ - ((FLAG) == ETH_DMATXDESC_NC) || \ - ((FLAG) == ETH_DMATXDESC_LCO) || \ - ((FLAG) == ETH_DMATXDESC_EC) || \ - ((FLAG) == ETH_DMATXDESC_VF) || \ - ((FLAG) == ETH_DMATXDESC_CC) || \ - ((FLAG) == ETH_DMATXDESC_ED) || \ - ((FLAG) == ETH_DMATXDESC_UF) || \ - ((FLAG) == ETH_DMATXDESC_DB)) -#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ - ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) -#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) -#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) -#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ - ((FLAG) == ETH_DMARXDESC_AFM) || \ - ((FLAG) == ETH_DMARXDESC_ES) || \ - ((FLAG) == ETH_DMARXDESC_DE) || \ - ((FLAG) == ETH_DMARXDESC_SAF) || \ - ((FLAG) == ETH_DMARXDESC_LE) || \ - ((FLAG) == ETH_DMARXDESC_OE) || \ - ((FLAG) == ETH_DMARXDESC_VLAN) || \ - ((FLAG) == ETH_DMARXDESC_FS) || \ - ((FLAG) == ETH_DMARXDESC_LS) || \ - ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ - ((FLAG) == ETH_DMARXDESC_LC) || \ - ((FLAG) == ETH_DMARXDESC_FT) || \ - ((FLAG) == ETH_DMARXDESC_RWT) || \ - ((FLAG) == ETH_DMARXDESC_RE) || \ - ((FLAG) == ETH_DMARXDESC_DBE) || \ - ((FLAG) == ETH_DMARXDESC_CE) || \ - ((FLAG) == ETH_DMARXDESC_MAMPCE)) -#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ - ((BUFFER) == ETH_DMARXDESC_BUFFER2)) -#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ - ((FLAG) == ETH_PMT_FLAG_MPR)) -#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) -#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ - ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ - ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ - ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ - ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ - ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ - ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ - ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ - ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ - ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ - ((FLAG) == ETH_DMA_FLAG_T)) -#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00)) -#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ - ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ - ((IT) == ETH_MAC_IT_PMT)) -#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ - ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ - ((FLAG) == ETH_MAC_FLAG_PMT)) -#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00)) -#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ - ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ - ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ - ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ - ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ - ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ - ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ - ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ - ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) -#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ - ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) -#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ - ((IT) != 0x00)) -#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ - ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ - ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) -#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ - ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) - - -/** - * @} - */ - -/** @addtogroup ETH_Private_Defines - * @{ - */ -/* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001) - -/* ETHERNET Errors */ -#define ETH_SUCCESS ((uint32_t)0) -#define ETH_ERROR ((uint32_t)1) - -/* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3) - -/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16) - -/* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16) - -/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16) - -/* ETHERNET DMA Rx descriptors Frame length Shift */ -#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16) - -/* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */ - -/* ETHERNET MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) - -/* ETHERNET MACCR register Mask */ -#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) - -/* ETHERNET MACFCR register Mask */ -#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) - -/* ETHERNET DMAOMR register Mask */ -#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) - -/* ETHERNET Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8 - -/* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 - /** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ETH_Exported_Types ETH Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */ - HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */ - HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */ - HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ -}HAL_ETH_StateTypeDef; - -/** - * @brief ETH Init Structure definition - */ - -typedef struct -{ - uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY - The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - and the mode (half/full-duplex). - This parameter can be a value of @ref ETH_AutoNegotiation */ - - uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. - This parameter can be a value of @ref ETH_Speed */ - - uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - This parameter can be a value of @ref ETH_Duplex_Mode */ - - uint16_t PhyAddress; /*!< Ethernet PHY address. - This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ - - uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. - This parameter can be a value of @ref ETH_Rx_Mode */ - - uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. - This parameter can be a value of @ref ETH_Checksum_Mode */ - - uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. - This parameter can be a value of @ref ETH_Media_Interface */ - -} ETH_InitTypeDef; - - - /** - * @brief ETH MAC Configuration Structure definition - */ - -typedef struct -{ - uint32_t Watchdog; /*!< Selects or not the Watchdog timer - When enabled, the MAC allows no more then 2048 bytes to be received. - When disabled, the MAC can receive up to 16384 bytes. - This parameter can be a value of @ref ETH_Watchdog */ - - uint32_t Jabber; /*!< Selects or not Jabber timer - When enabled, the MAC allows no more then 2048 bytes to be sent. - When disabled, the MAC can send up to 16384 bytes. - This parameter can be a value of @ref ETH_Jabber */ - - uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. - This parameter can be a value of @ref ETH_Inter_Frame_Gap */ - - uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. - This parameter can be a value of @ref ETH_Carrier_Sense */ - - uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, - ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode. - This parameter can be a value of @ref ETH_Receive_Own */ - - uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. - This parameter can be a value of @ref ETH_Loop_Back_Mode */ - - uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - This parameter can be a value of @ref ETH_Checksum_Offload */ - - uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a collision occurs (Half-Duplex mode). - This parameter can be a value of @ref ETH_Retry_Transmission */ - - uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. - This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ - - uint32_t BackOffLimit; /*!< Selects the BackOff limit value. - This parameter can be a value of @ref ETH_Back_Off_Limit */ - - uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). - This parameter can be a value of @ref ETH_Deferral_Check */ - - uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). - This parameter can be a value of @ref ETH_Receive_All */ - - uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. - This parameter can be a value of @ref ETH_Source_Addr_Filter */ - - uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - This parameter can be a value of @ref ETH_Pass_Control_Frames */ - - uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. - This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ - - uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. - This parameter can be a value of @ref ETH_Destination_Addr_Filter */ - - uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode - This parameter can be a value of @ref ETH_Promiscuous_Mode */ - - uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. - This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ - - uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. - This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ - - uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - - uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - - uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ - - uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. - This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ - - uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame. - This parameter can be a value of @ref ETH_Pause_Low_Threshold */ - - uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address). - This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ - - uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and - disable its transmitter for a specified time (Pause Time) - This parameter can be a value of @ref ETH_Receive_Flow_Control */ - - uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - or the MAC back-pressure operation (Half-Duplex mode) - This parameter can be a value of @ref ETH_Transmit_Flow_Control */ - - uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering. - This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ - - uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ - -} ETH_MACInitTypeDef; - - -/** - * @brief ETH DMA Configuration Structure definition - */ - -typedef struct -{ - uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. - This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ - - uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. - This parameter can be a value of @ref ETH_Receive_Store_Forward */ - - uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. - This parameter can be a value of @ref ETH_Flush_Received_Frame */ - - uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. - This parameter can be a value of @ref ETH_Transmit_Store_Forward */ - - uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. - This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ - - uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. - This parameter can be a value of @ref ETH_Forward_Error_Frames */ - - uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - and length less than 64 bytes) including pad-bytes and CRC) - This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ - - uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. - This parameter can be a value of @ref ETH_Receive_Threshold_Control */ - - uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second - frame of Transmit data even before obtaining the status for the first frame. - This parameter can be a value of @ref ETH_Second_Frame_Operate */ - - uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. - This parameter can be a value of @ref ETH_Address_Aligned_Beats */ - - uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. - This parameter can be a value of @ref ETH_Fixed_Burst */ - - uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. - This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ - - uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. - This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ - - uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. - This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ - - uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) - This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. - This parameter can be a value of @ref ETH_DMA_Arbitration */ -} ETH_DMAInitTypeDef; - - -/** - * @brief ETH DMA Descriptors data structure definition - */ - -typedef struct -{ - __IO uint32_t Status; /*!< Status */ - - uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ - - uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ - - uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ - - /*!< Enhanced ETHERNET DMA PTP Descriptors */ - uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ - - uint32_t Reserved1; /*!< Reserved */ - - uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ - - uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ - -} ETH_DMADescTypeDef; - - -/** - * @brief Received Frame Informations structure definition - */ -typedef struct -{ - ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ - - ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ - - uint32_t SegCount; /*!< Segment count */ - - uint32_t length; /*!< Frame length */ - - uint32_t buffer; /*!< Frame buffer */ - -} ETH_DMARxFrameInfos; - - -/** - * @brief ETH Handle Structure definition - */ - -typedef struct -{ - ETH_TypeDef *Instance; /*!< Register base address */ - - ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ - - uint32_t LinkStatus; /*!< Ethernet link status */ - - ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ - - ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ - - ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ - - __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ - - HAL_LockTypeDef Lock; /*!< ETH Lock */ - -} ETH_HandleTypeDef; - - /** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ETH_Exported_Constants ETH Exported Constants - * @{ - */ - -/** @defgroup ETH_Buffers_setting ETH Buffers setting - * @{ - */ -#define ETH_MAX_PACKET_SIZE (1536u) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */ -#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */ -#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */ -#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */ - - /* Ethernet driver receive buffers are organized in a chained linked-list, when - an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO - to the driver receive buffers memory. - - Depending on the size of the received ethernet packet and the size of - each ethernet driver receive buffer, the received packet can take one or more - ethernet driver receive buffer. - - In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE - and the total count of the driver receive buffers ETH_RXBUFNB. - - The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_RX_BUF_SIZE - #error please define ETH_RX_BUF_SIZE - #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ -#ifndef ETH_RXBUFNB - #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#endif - - - /* Ethernet driver transmit buffers are organized in a chained linked-list, when - an ethernet packet is transmitted, Tx-DMA will transfer the packet from the - driver transmit buffers memory to the TxFIFO. - - Depending on the size of the Ethernet packet to be transmitted and the size of - each ethernet driver transmit buffer, the packet to be transmitted can take - one or more ethernet driver transmit buffer. - - In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE - and the total count of the driver transmit buffers ETH_TXBUFNB. - - The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_TX_BUF_SIZE - #error please define ETH_TX_BUF_SIZE - #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ -#ifndef ETH_TXBUFNB - #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ -#endif - - /** - * @} - */ - -/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor - * @{ - */ - -/* - DMA Tx Descriptor - ----------------------------------------------------------------------------------------------- - TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | - ----------------------------------------------------------------------------------------------- - TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | - ----------------------------------------------------------------------------------------------- - TDES2 | Buffer1 Address [31:0] | - ----------------------------------------------------------------------------------------------- - TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - ----------------------------------------------------------------------------------------------- -*/ - -/** - * @brief Bit definition of TDES0 register: DMA Tx descriptor status register - */ -#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ -#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */ -#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */ -#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */ -#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */ -#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ -#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ -#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ -#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ -#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ -#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ -#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ -#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */ -#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */ -#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ -#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ -#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */ -#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ -#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ -#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ - -/** - * @brief Bit definition of TDES1 register - */ -#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ -#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ - -/** - * @brief Bit definition of TDES2 register - */ -#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of TDES3 register - */ -#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ - - /*--------------------------------------------------------------------------------------------- - TDES6 | Transmit Time Stamp Low [31:0] | - ----------------------------------------------------------------------------------------------- - TDES7 | Transmit Time Stamp High [31:0] | - ----------------------------------------------------------------------------------------------*/ - -/* Bit definition of TDES6 register */ - #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */ - -/* Bit definition of TDES7 register */ - #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */ - -/** - * @} - */ -/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor - * @{ - */ - /* - DMA Rx Descriptor - -------------------------------------------------------------------------------------------------------------------- - RDES0 | OWN(31) | Status [30:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES2 | Buffer1 Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- -*/ - -/** - * @brief Bit definition of RDES0 register: DMA Rx descriptor status register - */ -#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ -#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ -#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */ -#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ -#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ -#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ -#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ -#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ -#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ -#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ -#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ -#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ -#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ -#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ -#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ -#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */ -#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ - -/** - * @brief Bit definition of RDES1 register - */ -#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ -#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ -#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ -#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ -#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ - -/** - * @brief Bit definition of RDES2 register - */ -#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of RDES3 register - */ -#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ - -/*--------------------------------------------------------------------------------------------------------------------- - RDES4 | Reserved[31:15] | Extended Status [14:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES5 | Reserved[31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES6 | Receive Time Stamp Low [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES7 | Receive Time Stamp High [31:0] | - --------------------------------------------------------------------------------------------------------------------*/ - -/* Bit definition of RDES4 register */ -#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */ -#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */ -#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */ - #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */ -#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */ -#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */ -#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */ -#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */ -#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */ - #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */ - -/* Bit definition of RDES6 register */ -#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */ - -/* Bit definition of RDES7 register */ -#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */ -/** - * @} - */ - /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation - * @{ - */ -#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001) -#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ -/** @defgroup ETH_Speed ETH Speed - * @{ - */ -#define ETH_SPEED_10M ((uint32_t)0x00000000) -#define ETH_SPEED_100M ((uint32_t)0x00004000) - -/** - * @} - */ -/** @defgroup ETH_Duplex_Mode ETH Duplex Mode - * @{ - */ -#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800) -#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000) -/** - * @} - */ -/** @defgroup ETH_Rx_Mode ETH Rx Mode - * @{ - */ -#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000) -#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001) -/** - * @} - */ - -/** @defgroup ETH_Checksum_Mode ETH Checksum Mode - * @{ - */ -#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000) -#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001) -/** - * @} - */ - -/** @defgroup ETH_Media_Interface ETH Media Interface - * @{ - */ -#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000) -#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) -/** - * @} - */ - -/** @defgroup ETH_Watchdog ETH Watchdog - * @{ - */ -#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000) -#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000) -/** - * @} - */ - -/** @defgroup ETH_Jabber ETH Jabber - * @{ - */ -#define ETH_JABBER_ENABLE ((uint32_t)0x00000000) -#define ETH_JABBER_DISABLE ((uint32_t)0x00400000) -/** - * @} - */ - -/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap - * @{ - */ -#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ -#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ -#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ -#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ -#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ -#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ -#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ -#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ -/** - * @} - */ - -/** @defgroup ETH_Carrier_Sense ETH Carrier Sense - * @{ - */ -#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000) -#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000) -/** - * @} - */ - -/** @defgroup ETH_Receive_Own ETH Receive Own - * @{ - */ -#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000) -#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000) -/** - * @} - */ - -/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode - * @{ - */ -#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000) -#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Checksum_Offload ETH Checksum Offload - * @{ - */ -#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400) -#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Retry_Transmission ETH Retry Transmission - * @{ - */ -#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000) -#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200) -/** - * @} - */ - -/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip - * @{ - */ -#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080) -#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit - * @{ - */ -#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000) -#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020) -#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040) -#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060) -/** - * @} - */ - -/** @defgroup ETH_Deferral_Check ETH Deferral Check - * @{ - */ -#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010) -#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Receive_All ETH Receive All - * @{ - */ -#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000) -#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter - * @{ - */ -#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200) -#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300) -#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames - * @{ - */ -#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ -#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ -#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ -/** - * @} - */ - -/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception - * @{ - */ -#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000) -#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020) -/** - * @} - */ - -/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter - * @{ - */ -#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000) -#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode - * @{ - */ -#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001) -#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter - * @{ - */ -#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404) -#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004) -#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) -#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010) -/** - * @} - */ - -/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter - * @{ - */ -#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402) -#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002) -#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause - * @{ - */ -#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000) -#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080) -/** - * @} - */ - -/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold - * @{ - */ -#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ -/** - * @} - */ - -/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect - * @{ - */ -#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008) -#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control - * @{ - */ -#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004) -#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control - * @{ - */ -#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002) -#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison - * @{ - */ -#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000) -#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses ETH MAC addresses - * @{ - */ -#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000) -#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008) -#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010) -#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA - * @{ - */ -#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000) -#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes - * @{ - */ -#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ -#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ -#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ -#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags - * @{ - */ -#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ -#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ -/** - * @} - */ - -/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame - * @{ - */ -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000) -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000) -/** - * @} - */ - -/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward - * @{ - */ -#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000) -#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame - * @{ - */ -#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000) -#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward - * @{ - */ -#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000) -#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control - * @{ - */ -#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ -/** - * @} - */ - -/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames - * @{ - */ -#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080) -#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames - * @{ - */ -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040) -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control - * @{ - */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ -/** - * @} - */ - -/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate - * @{ - */ -#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004) -#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats - * @{ - */ -#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000) -#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Fixed_Burst ETH Fixed Burst - * @{ - */ -#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000) -#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length - * @{ - */ -#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ -/** - * @} - */ - -/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length - * @{ - */ -#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format - * @{ - */ -#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080) -#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration - * @{ - */ -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000) -#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002) -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment - * @{ - */ -#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */ -#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control - * @{ - */ -#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */ -#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers - * @{ - */ -#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ -#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ -/** - * @} - */ - -/** @defgroup ETH_PMT_Flags ETH PMT Flags - * @{ - */ -#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ -#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ -/** - * @} - */ - -/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts - * @{ - */ -#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ -/** - * @} - */ - -/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts - * @{ - */ -#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ -#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Flags ETH MAC Flags - * @{ - */ -#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ -#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ -#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ -#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ -#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Flags ETH DMA Flags - * @{ - */ -#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */ -#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ -#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ -#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ -#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ -#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ -#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ -#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ -#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ -#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ -#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ -#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ -#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ -#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ -#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ -#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ -#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts - * @{ - */ -#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ -#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ -#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ -#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ -#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts - * @{ - */ -#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ -#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ -#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ -#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ -#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ -#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ -#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ -#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ -#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ -#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ -#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ -#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ -#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ -#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ -#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ -/** - * @} - */ - -/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state - * @{ - */ -#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ -#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ -#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */ -#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ -#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */ -#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ - -/** - * @} - */ - - -/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state - * @{ - */ -#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ -#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ -#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */ -#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */ -#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ -#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_overflow ETH DMA overflow - * @{ - */ -#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ -#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ -/** - * @} - */ - -/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP - * @{ - */ -#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ETH_Exported_Macros ETH Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ + * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to + * a single module that works for both parts: "stm32fxx_hal_eth" */ -/** @brief Reset ETH handle state - * @param __HANDLE__: specifies the ETH handle. - * @retval None - */ -#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) - -/** - * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag of TDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag of RDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Enables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) - -/** - * @brief Disables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) - -/** - * @brief Set the specified DMA Rx Desc Own bit. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) - -/** - * @brief Returns the specified ETHERNET DMA Tx Desc collision count. - * @param __HANDLE__: ETH Handle - * @retval The Transmit descriptor collision counter value. - */ -#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) - -/** - * @brief Set the specified DMA Tx Desc Own bit. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) - -/** - * @brief Enables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) - -/** - * @brief Disables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) - -/** - * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. - * @param __HANDLE__: ETH Handle - * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. - * This parameter can be one of the following values: - * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass - * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) - -/** - * @brief Enables the DMA Tx Desc CRC. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) - -/** - * @brief Disables the DMA Tx Desc CRC. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) - -/** - * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) - -/** - * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) - -/** - * @brief Enables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) - -/** - * @brief Disables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) - -/** - * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the ETHERNET flow control busy bit is set or not. - * @param __HANDLE__: ETH Handle - * @retval The new state of flow control busy status bit (SET or RESET). - */ -#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) - -/** - * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Disables the MAC BackPressure operation activation (Half-duplex only). - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval The state of ETHERNET MAC flag. - */ -#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Enables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be - * enabled @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) - -/** - * @brief Disables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be - * disabled. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) - -/** - * @brief Clears the ETHERNET DMA IT pending bit. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. -* @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __OVERFLOW__: specifies the DMA overflow flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter - * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter - * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). - */ -#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) - -/** - * @brief Set the DMA Receive status watchdog timer register value - * @param __HANDLE__: ETH Handle - * @param __VALUE__: DMA Receive status watchdog timer register value - * @retval None - */ -#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) - -/** - * @brief Enables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) - -/** - * @brief Disables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) - -/** - * @brief Enables the MAC Wake-Up Frame Detection. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) - -/** - * @brief Disables the MAC Wake-Up Frame Detection. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Magic Packet Detection. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) - -/** - * @brief Disables the MAC Magic Packet Detection. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Power Down. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) - -/** - * @brief Disables the MAC Power Down. - * @param __HANDLE__: ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) - -/** - * @brief Checks whether the specified ETHERNET PMT flag is set or not. - * @param __HANDLE__: ETH Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval The new state of ETHERNET PMT Flag (SET or RESET). - */ -#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) - -/** - * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ - (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) - -/** - * @brief Enables the MMC Counter Freeze. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) - -/** - * @brief Disables the MMC Counter Freeze. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) - -/** - * @brief Enables the MMC Reset On Read. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) - -/** - * @brief Disables the MMC Reset On Read. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) - -/** - * @brief Enables the MMC Counter Stop Rollover. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) - -/** - * @brief Disables the MMC Counter Stop Rollover. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) - -/** - * @brief Resets the MMC Counters. - * @param __HANDLE__: ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) - -/** - * @brief Enables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) -/** - * @brief Disables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) -/** - * @brief Enables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) - -/** - * @brief Disables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) - -/** - * @brief Enables the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disables the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enable event on ETH External event line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disable event on ETH External event line - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Get flag of the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Clear flag of the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables rising edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP - -/** - * @brief Disables the rising edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disables falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP - -/** - * @brief Disables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP - -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup ETH_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ - -/** @addtogroup ETH_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); - -/** - * @} - */ -/* IO operation functions ****************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); -/* Communication with PHY functions*/ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); -/* Callback in non blocking modes (Interrupt) */ -void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ - -/** @addtogroup ETH_Exported_Functions_Group3 - * @{ - */ - -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group4 - * @{ - */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_ETH_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#include "stm32fxx_hal_eth.h" diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/NetworkInterface.c index 86579ecdb..e8d12a6a7 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/NetworkInterface.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/NetworkInterface.c @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/NetworkInterface.c index 9d0b825a3..ad0717780 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/NetworkInterface.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/NetworkInterface.c @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -21,7 +21,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. http://aws.amazon.com/freertos http://www.FreeRTOS.org -*/ + */ /* Standard includes. */ #include @@ -38,6 +38,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "FreeRTOS_IP.h" #include "FreeRTOS_Sockets.h" #include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_ARP.h" #include "NetworkBufferManagement.h" #include "NetworkInterface.h" @@ -50,10 +51,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Provided memory configured as uncached. */ #include "uncached_memory.h" -#ifndef BMSR_LINK_STATUS - #define BMSR_LINK_STATUS 0x0004UL +#ifndef niEMAC_HANDLER_TASK_PRIORITY + #define niEMAC_HANDLER_TASK_PRIORITY configMAX_PRIORITIES - 1 #endif +#define niBMSR_LINK_STATUS 0x0004UL +#define niBMSR_AN_COMPLETE 0x0020u /* Auto-Negotiation process completed */ + #ifndef PHY_LS_HIGH_CHECK_TIME_MS /* Check if the LinkSStatus in the PHY is still high after 15 seconds of not receiving packets. */ @@ -188,7 +192,7 @@ const TickType_t xWaitLinkDelay = pdMS_TO_TICKS( 7000UL ), xWaitRelinkDelay = pd possible priority to ensure the interrupt handler can return directly to it. The task's handle is stored in xEMACTaskHandle so interrupts can notify the task when there is something to process. */ - xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xEMACTaskHandle ); + xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, niEMAC_HANDLER_TASK_PRIORITY, &xEMACTaskHandle ); } else { @@ -206,7 +210,34 @@ const TickType_t xWaitLinkDelay = pdMS_TO_TICKS( 7000UL ), xWaitRelinkDelay = pd BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxBuffer, BaseType_t bReleaseAfterSend ) { - if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) + if( xCheckLoopback( pxBuffer, bReleaseAfterSend ) != 0 ) + { + /* The packet has been sent back to the IP-task. + The IP-task will further handle it. + Do not release the descriptor. */ + return pdTRUE; + } + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) + { + ProtocolPacket_t *pxPacket; + + /* If the peripheral must calculate the checksum, it wants + the protocol checksum to have a value of zero. */ + pxPacket = ( ProtocolPacket_t * ) ( pxBuffer->pucEthernetBuffer ); + if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ipPROTOCOL_ICMP ) + { + IPHeader_t *pxIPHeader = &( pxPacket->xUDPPacket.xIPHeader ); + + pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u; + pxIPHeader->usHeaderChecksum = 0u; + pxIPHeader->usHeaderChecksum = usGenerateChecksum( 0UL, ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipSIZE_OF_IPv4_HEADER ); + pxIPHeader->usHeaderChecksum = ~FreeRTOS_htons( pxIPHeader->usHeaderChecksum ); + + usGenerateProtocolChecksum( (uint8_t*)&( pxPacket->xUDPPacket ), pxBuffer->xDataLength, pdTRUE ); + } + } + #endif /* ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM */ + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != 0 ) { iptraceNETWORK_INTERFACE_TRANSMIT(); emacps_send_message( &xEMACpsif, pxBuffer, bReleaseAfterSend ); @@ -249,7 +280,7 @@ BaseType_t xReturn; } ulPHYLinkStatus = ulReadMDIO( PHY_REG_01_BMSR ); - if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != 0 ) { xReturn = pdTRUE; break; @@ -281,7 +312,7 @@ BaseType_t xGetPhyLinkStatus( void ) { BaseType_t xReturn; - if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) == 0 ) + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) == 0 ) { xReturn = pdFALSE; } @@ -298,11 +329,12 @@ static void prvEMACHandlerTask( void *pvParameters ) { TimeOut_t xPhyTime; TickType_t xPhyRemTime; -UBaseType_t uxLastMinBufferCount = 0; UBaseType_t uxCurrentCount; BaseType_t xResult = 0; uint32_t xStatus; const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); +UBaseType_t uxLastMinBufferCount = 0; +UBaseType_t uxCurrentBufferCount = 0; /* Remove compiler warnings about unused parameters. */ ( void ) pvParameters; @@ -316,14 +348,14 @@ const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); for( ;; ) { - uxCurrentCount = uxGetMinimumFreeNetworkBuffers(); - if( uxLastMinBufferCount != uxCurrentCount ) + uxCurrentBufferCount = uxGetMinimumFreeNetworkBuffers(); + if( uxLastMinBufferCount != uxCurrentBufferCount ) { /* The logging produced below may be helpful while tuning +TCP: see how many buffers are in use. */ - uxLastMinBufferCount = uxCurrentCount; + uxLastMinBufferCount = uxCurrentBufferCount; FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n", - uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) ); + uxGetNumberOfFreeNetworkBuffers(), uxCurrentBufferCount ) ); } #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) @@ -364,7 +396,6 @@ const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); xEMACpsif.isr_events &= ~EMAC_IF_ERR_EVENT; emacps_check_errors( &xEMACpsif ); } - if( xResult > 0 ) { /* A packet was received. No need to check for the PHY status now, @@ -372,19 +403,22 @@ const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); vTaskSetTimeOutState( &xPhyTime ); xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); xResult = 0; + /* Indicate that the Link Status is high, so that + xNetworkInterfaceOutput() can send packets. */ + ulPHYLinkStatus |= niBMSR_LINK_STATUS; } else if( xTaskCheckForTimeOut( &xPhyTime, &xPhyRemTime ) != pdFALSE ) { xStatus = ulReadMDIO( PHY_REG_01_BMSR ); - if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != ( xStatus & BMSR_LINK_STATUS ) ) + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != ( xStatus & niBMSR_LINK_STATUS ) ) { ulPHYLinkStatus = xStatus; - FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d\n", ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) ); + FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d\n", ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != 0 ) ); } vTaskSetTimeOutState( &xPhyTime ); - if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != 0 ) { xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); } diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.c index 5834adaf1..b43e50ec2 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.c @@ -1,5 +1,3 @@ -#warning Temoporary file and a dependent on the Zynq network interface. - /* * uncached_memory.c * @@ -19,6 +17,21 @@ * uncached memory. */ +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" + #include "Zynq/x_emacpsif.h" #include "Zynq/x_topology.h" #include "xstatus.h" @@ -28,12 +41,8 @@ #include "xil_exception.h" #include "xil_mmu.h" -#include "FreeRTOS.h" - #include "uncached_memory.h" -#include "Demo_Logging.h" - #define UNCACHED_MEMORY_SIZE 0x100000ul #define DDR_MEMORY_END (XPAR_PS7_DDR_0_S_AXI_HIGHADDR+1) @@ -100,7 +109,7 @@ static void vInitialiseUncachedMemory( ) if( ( ( u32 )pucStartOfMemory ) + UNCACHED_MEMORY_SIZE > DDR_MEMORY_END ) { - vLoggingPrintf("vInitialiseUncachedMemory: Can not allocate uncached memory\n" ); +// vLoggingPrintf("vInitialiseUncachedMemory: Can not allocate uncached memory\n" ); } else { @@ -109,7 +118,11 @@ static void vInitialiseUncachedMemory( ) * address range that starts after "_end" is made uncached * by setting appropriate attributes in the translation table. */ - Xil_SetTlbAttributes( ( uint32_t )pucStartOfMemory, 0xc02 ); // addr, attr + /* FIXME claudio rossi. Modified to prevent data abort exception (misaligned access) + * when application is compiled with -O1 or more optimization flag. + */ +/* Xil_SetTlbAttributes( ( uint32_t )pucStartOfMemory, 0xc02 ); // addr, attr */ + Xil_SetTlbAttributes( ( uint32_t )pucStartOfMemory, 0x1c02 ); // addr, attr /* For experiments in the SDIO driver, make the remaining uncached memory public */ pucHeadOfMemory = pucStartOfMemory; diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_dma.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_dma.c index b81841dcf..895564ca3 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_dma.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_dma.c @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -21,16 +21,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. http://aws.amazon.com/freertos http://www.FreeRTOS.org -*/ - -#include "Zynq/x_emacpsif.h" -#include "Zynq/x_topology.h" -#include "xstatus.h" - -#include "xparameters.h" -#include "xparameters_ps.h" -#include "xil_exception.h" -#include "xil_mmu.h" + */ #include "FreeRTOS.h" #include "task.h" @@ -43,6 +34,15 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "FreeRTOS_IP_Private.h" #include "NetworkBufferManagement.h" +#include "Zynq/x_emacpsif.h" +#include "Zynq/x_topology.h" +#include "xstatus.h" + +#include "xparameters.h" +#include "xparameters_ps.h" +#include "xil_exception.h" +#include "xil_mmu.h" + #include "uncached_memory.h" /* Two defines used to set or clear the EMAC interrupt */ @@ -201,7 +201,7 @@ BaseType_t xReturn; XStatus emacps_send_message(xemacpsif_s *xemacpsif, NetworkBufferDescriptor_t *pxBuffer, int iReleaseAfterSend ) { int head = xemacpsif->txHead; -int tail = xemacpsif->txTail; +//int tail = xemacpsif->txTail; int iHasSent = 0; uint32_t ulBaseAddress = xemacpsif->emacps.Config.BaseAddress; TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 5000u ); @@ -313,10 +313,7 @@ void emacps_recv_handler(void *arg) portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); } -static NetworkBufferDescriptor_t *ethMsg = NULL; -static NetworkBufferDescriptor_t *ethLast = NULL; - -static void passEthMessages( void ) +static void passEthMessages( NetworkBufferDescriptor_t *ethMsg ) { IPStackEvent_t xRxEvent; @@ -338,20 +335,50 @@ IPStackEvent_t xRxEvent; iptraceETHERNET_RX_EVENT_LOST(); FreeRTOS_printf( ( "passEthMessages: Can not queue return packet!\n" ) ); } - - ethMsg = ethLast = NULL; } +TickType_t ack_reception_delay = 10; + int emacps_check_rx( xemacpsif_s *xemacpsif ) { NetworkBufferDescriptor_t *pxBuffer, *pxNewBuffer; int rx_bytes; volatile int msgCount = 0; int head = xemacpsif->rxHead; +BaseType_t bHasDataPacket = pdFALSE; +NetworkBufferDescriptor_t *ethMsg = NULL; +NetworkBufferDescriptor_t *ethLast = NULL; /* There seems to be an issue (SI# 692601), see comments below. */ resetrx_on_no_rxdata(xemacpsif); + { + static int maxcount = 0; + int count = 0; + for( ;; ) + { + if( ( ( xemacpsif->rxSegments[ head ].address & XEMACPS_RXBUF_NEW_MASK ) == 0 ) || + ( pxDMA_rx_buffers[ head ] == NULL ) ) + { + break; + } + count++; + if( ++head == ipconfigNIC_N_RX_DESC ) + { + head = 0; + } + if( head == xemacpsif->rxHead ) + { + break; + } + } + if (maxcount < count) { + maxcount = count; + FreeRTOS_printf( ( "emacps_check_rx: %d packets\n", maxcount ) ); + } + head = xemacpsif->rxHead; + } + /* This FreeRTOS+TCP driver shall be compiled with the option "ipconfigUSE_LINKED_RX_MESSAGES" enabled. It allows the driver to send a chain of RX messages within one message to the IP-task. */ @@ -384,7 +411,10 @@ int head = xemacpsif->rxHead; rx_bytes = xemacpsif->rxSegments[ head ].flags & XEMACPS_RXBUF_LEN_MASK; pxBuffer->xDataLength = rx_bytes; - +if( rx_bytes > 60 ) +{ + bHasDataPacket = 1; +} if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 ) { Xil_DCacheInvalidateRange( ( ( uint32_t )pxBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE, (unsigned)rx_bytes ); @@ -421,8 +451,11 @@ int head = xemacpsif->rxHead; addr |= XEMACPS_RXBUF_WRAP_MASK; } /* Clearing 'XEMACPS_RXBUF_NEW_MASK' 0x00000001 *< Used bit.. */ - xemacpsif->rxSegments[ head ].address = addr; xemacpsif->rxSegments[ head ].flags = 0; + xemacpsif->rxSegments[ head ].address = addr; + if (xemacpsif->rxSegments[ head ].address) { + // Just to read it + } } } @@ -435,7 +468,11 @@ int head = xemacpsif->rxHead; if( ethMsg != NULL ) { - passEthMessages( ); + if( bHasDataPacket == pdFALSE ) + { +// vTaskDelay( ack_reception_delay ); + } + passEthMessages( ethMsg ); } return msgCount; @@ -455,9 +492,9 @@ unsigned char *ucTxBuffer; xemacpsif->txSegments[ index ].address = ( uint32_t )ucTxBuffer; xemacpsif->txSegments[ index ].flags = XEMACPS_TXBUF_USED_MASK; #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) - pxDMA_tx_buffers[ index ] = ( void* )NULL; + pxDMA_tx_buffers[ index ] = ( unsigned char * )NULL; #else - pxDMA_tx_buffers[ index ] = ( void* )( ucTxBuffer + TX_OFFSET ); + pxDMA_tx_buffers[ index ] = ( unsigned char * )( ucTxBuffer + TX_OFFSET ); #endif ucTxBuffer += xemacpsif->uTxUnitSize; } @@ -601,6 +638,7 @@ void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif) tempcntr = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET ); if ( ( tempcntr == 0 ) && ( xemacpsif->last_rx_frms_cntr == 0 ) ) { +FreeRTOS_printf( ( "resetrx_on_no_rxdata: RESET~\n" ) ); regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET); regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK); diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.c index e9443cda8..83c504ad0 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.c @@ -22,19 +22,19 @@ #include #include -#include "Zynq/x_emacpsif.h" - /* FreeRTOS includes. */ #include "FreeRTOS.h" #include "task.h" #include "queue.h" -///* FreeRTOS+TCP includes. */ /* FreeRTOS+TCP includes. */ #include "FreeRTOS_IP.h" #include "FreeRTOS_Sockets.h" #include "FreeRTOS_IP_Private.h" #include "NetworkBufferManagement.h" +#include "NetworkInterface.h" + +#include "Zynq/x_emacpsif.h" extern TaskHandle_t xEMACTaskHandle; @@ -42,8 +42,6 @@ extern TaskHandle_t xEMACTaskHandle; *** to run it on a PEEP board ***/ -unsigned int link_speed = 100; - void setup_isr( xemacpsif_s *xemacpsif ) { /* @@ -141,8 +139,6 @@ int xResult; return xResult; } -BaseType_t xNetworkInterfaceInitialise( void ); - static void emacps_handle_error(void *arg, u8 Direction, u32 ErrorWord) { xemacpsif_s *xemacpsif; diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c index 12b8c60c8..dd0cf0ab7 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c @@ -53,24 +53,23 @@ #include #include -#include "Zynq/x_emacpsif.h" -//#include "lwipopts.h" -#include "xparameters_ps.h" -#include "xparameters.h" - /* FreeRTOS includes. */ #include "FreeRTOS.h" #include "task.h" #include "queue.h" #include "semphr.h" -///* FreeRTOS+TCP includes. */ /* FreeRTOS+TCP includes. */ #include "FreeRTOS_IP.h" #include "FreeRTOS_Sockets.h" #include "FreeRTOS_IP_Private.h" #include "NetworkBufferManagement.h" +#include "Zynq/x_emacpsif.h" +#include "xparameters_ps.h" +#include "xparameters.h" + + int phy_detected = 0; /*** IMPORTANT: Define PEEP in xemacpsif.h and sys_arch_raw.c @@ -99,6 +98,8 @@ int phy_detected = 0; #define IEEE_CONTROL_REG_OFFSET 0 #define IEEE_STATUS_REG_OFFSET 1 +#define IEEE_PHYSID1_OFFSET 2 +#define IEEE_PHYSID2_OFFSET 3 #define IEEE_AUTONEGO_ADVERTISE_REG 4 #define IEEE_PARTNER_ABILITIES_1_REG_OFFSET 5 #define IEEE_1000_ADVERTISE_REG_OFFSET 9 @@ -135,9 +136,6 @@ int phy_detected = 0; #define IEEE_PAUSE_MASK 0x0400 #define IEEE_AUTONEG_ERROR_MASK 0x8000 -#define PHY_DETECT_REG 1 -#define PHY_DETECT_MASK 0x1808 - #define XEMACPS_GMII2RGMII_SPEED1000_FD 0x140 #define XEMACPS_GMII2RGMII_SPEED100_FD 0x2100 #define XEMACPS_GMII2RGMII_SPEED10_FD 0x100 @@ -163,19 +161,17 @@ int phy_detected = 0; static int detect_phy(XEmacPs *xemacpsp) { - u16 phy_reg; - u32 phy_addr; - - for (phy_addr = 31; phy_addr > 0; phy_addr--) { - XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_DETECT_REG, - &phy_reg); - - if ((phy_reg != 0xFFFF) && - ((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { - /* Found a valid PHY address */ - FreeRTOS_printf( ("XEmacPs detect_phy: PHY detected at address %d.\r\n", - phy_addr)); - FreeRTOS_printf( ("XEmacPs detect_phy: PHY detected.\n" ) ); + u16 id_lower, id_upper; + u32 phy_addr, id; + + for (phy_addr = 0; phy_addr < 32; phy_addr++) { + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PHYSID1_OFFSET, &id_lower); + + if ((id_lower != ( u16 )0xFFFFu) && (id_lower != ( u16 )0x0u)) { + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PHYSID2_OFFSET, &id_upper); + id = ( ( ( uint32_t ) id_upper ) << 16 ) | ( id_lower & 0xFFF0 ); + FreeRTOS_printf( ("XEmacPs detect_phy: %04lX at address %d.\n", id, phy_addr ) ); phy_detected = phy_addr; return phy_addr; } @@ -238,7 +234,7 @@ unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS) return 10; - xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\r\n", + xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\n", __FUNCTION__); return 10; @@ -257,7 +253,7 @@ unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) case (IEEE_CTRL_LINKSPEED_10M): return 10; default: - xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\r\n", + xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\n", __FUNCTION__, phylinkspeed); return 10; } @@ -282,7 +278,7 @@ unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) #else u32 phy_addr = detect_phy(xemacpsp); #endif - xil_printf("Start PHY autonegotiation \r\n"); + xil_printf("Start PHY autonegotiation \n"); #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 #else @@ -338,7 +334,7 @@ unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) break; } #endif - xil_printf("Waiting for PHY to complete autonegotiation.\r\n"); + xil_printf("Waiting for PHY to complete autonegotiation.\n"); XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) { @@ -348,14 +344,14 @@ unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_STATUS_REG_2, &temp); if (temp & IEEE_AUTONEG_ERROR_MASK) { - xil_printf("Auto negotiation error \r\n"); + xil_printf("Auto negotiation error \n"); } #endif XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); } - xil_printf("autonegotiation complete \r\n"); + xil_printf("autonegotiation complete \n"); #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 #else @@ -363,7 +359,7 @@ unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) #endif #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 - xil_printf("Waiting for Link to be up; Polling for SGMII core Reg \r\n"); + xil_printf("Waiting for Link to be up; Polling for SGMII core Reg \n"); XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp); while(!(temp & 0x8000)) { XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp); @@ -380,7 +376,7 @@ unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); return 10; } else { - xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Deafulting to Speed = 10 Mbps\r\n"); + xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Deafulting to Speed = 10 Mbps\n"); XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); XEmacPs_PhyWrite(xemacpsp, phy_addr, 0, 0x0100); return 10; @@ -579,7 +575,7 @@ unsigned Phy_Setup (XEmacPs *xemacpsp) XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting); } - xil_printf("link speed: %d\r\n", link_speed); + xil_printf("link speed: %d\n", link_speed); return link_speed; } diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/NetworkInterface.c index 0b7e0dc23..544e5ba09 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/NetworkInterface.c +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/NetworkInterface.c @@ -1,5 +1,5 @@ /* -FreeRTOS+TCP V2.0.7 +FreeRTOS+TCP V2.0.11 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of -- 2.39.5