From 6dc954e6a249052e9c1b6e1a53eae11db9bf64f2 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Tue, 5 Jun 2007 09:44:58 +0000 Subject: [PATCH] Update to V4.3.0 as described in http://www.FreeRTOS.org/History.txt git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@85 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- Demo/Cygnal/FreeRTOSConfig.h | 2 +- Demo/Cygnal/Makefile | 2 +- Demo/Cygnal/ParTest/ParTest.c | 2 +- Demo/Cygnal/c8051f120.h | 912 +++++++++--------- Demo/Cygnal/main.c | 2 +- Demo/Cygnal/serial/serial.c | 2 +- Demo/Flshlite/FRConfig.h | 2 +- Demo/Flshlite/FileIO/fileIO.c | 2 +- Demo/Flshlite/FreeRTOSConfig.h | 2 +- Demo/Flshlite/ParTest/ParTest.c | 2 +- Demo/Flshlite/main.c | 2 +- Demo/Flshlite/serial/serial.c | 2 +- Demo/H8S/RTOSDemo/FreeRTOSConfig.h | 2 +- Demo/H8S/RTOSDemo/ParTest/ParTest.c | 2 +- Demo/H8S/RTOSDemo/main.c | 2 +- Demo/H8S/RTOSDemo/serial/serial.c | 2 +- .../HCS12_CodeWarrior_banked/FreeRTOSConfig.h | 2 +- .../ParTest/ParTest.c | 2 +- Demo/HCS12_CodeWarrior_banked/main.c | 2 +- Demo/HCS12_CodeWarrior_banked/serial/serial.c | 2 +- Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h | 2 +- .../HCS12_CodeWarrior_small/ParTest/ParTest.c | 2 +- Demo/HCS12_CodeWarrior_small/main.c | 2 +- Demo/HCS12_CodeWarrior_small/serial/serial.c | 2 +- Demo/HCS12_GCC_banked/FreeRTOSConfig.h | 2 +- Demo/HCS12_GCC_banked/ParTest.c | 2 +- Demo/HCS12_GCC_banked/main.c | 2 +- Demo/HCS12_GCC_banked/startup.c | 2 +- Demo/dsPIC_MPLAB/FreeRTOSConfig.h | 4 +- Demo/dsPIC_MPLAB/ParTest/ParTest.c | 2 +- Demo/dsPIC_MPLAB/RTOSDemo.mcw | Bin 150528 -> 150528 bytes Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcp | 20 +- Demo/dsPIC_MPLAB/lcd.c | 332 +++++++ Demo/dsPIC_MPLAB/lcd.h | 57 ++ Demo/dsPIC_MPLAB/main.c | 346 ++----- Demo/dsPIC_MPLAB/serial/serial.c | 13 +- Demo/dsPIC_MPLAB/timertest.c | 144 +++ Demo/dsPIC_MPLAB/timertest.h | 45 + 38 files changed, 1173 insertions(+), 756 deletions(-) create mode 100644 Demo/dsPIC_MPLAB/lcd.c create mode 100644 Demo/dsPIC_MPLAB/lcd.h create mode 100644 Demo/dsPIC_MPLAB/timertest.c create mode 100644 Demo/dsPIC_MPLAB/timertest.h diff --git a/Demo/Cygnal/FreeRTOSConfig.h b/Demo/Cygnal/FreeRTOSConfig.h index 0ccb18501..c676a2a9d 100644 --- a/Demo/Cygnal/FreeRTOSConfig.h +++ b/Demo/Cygnal/FreeRTOSConfig.h @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/Cygnal/Makefile b/Demo/Cygnal/Makefile index 5f7ca79fa..45ff2f712 100644 --- a/Demo/Cygnal/Makefile +++ b/Demo/Cygnal/Makefile @@ -1,4 +1,4 @@ -# FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. +# FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. # # This file is part of the FreeRTOS.org distribution. # diff --git a/Demo/Cygnal/ParTest/ParTest.c b/Demo/Cygnal/ParTest/ParTest.c index 8674ed842..df4dc6f23 100644 --- a/Demo/Cygnal/ParTest/ParTest.c +++ b/Demo/Cygnal/ParTest/ParTest.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/Cygnal/c8051f120.h b/Demo/Cygnal/c8051f120.h index ef9df9ad8..2986ab9c7 100644 --- a/Demo/Cygnal/c8051f120.h +++ b/Demo/Cygnal/c8051f120.h @@ -1,456 +1,456 @@ -/*------------------------------------------------------------------------- - Register Declarations for the Cygnal C8051F12x Processor Range - - Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --------------------------------------------------------------------------*/ - -#ifndef C8051F120_H -#define C8051F120_H - - -/* BYTE Registers */ - -/* All Pages */ -sfr at 0x80 P0 ; /* PORT 0 */ -sfr at 0x81 SP ; /* STACK POINTER */ -sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */ -sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */ -sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */ -sfr at 0x87 PCON ; /* POWER CONTROL */ -sfr at 0x90 P1 ; /* PORT 1 */ -sfr at 0xA0 P2 ; /* PORT 2 */ -sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ -sfr at 0xB0 P3 ; /* PORT 3 */ -sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */ -sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ -sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -sfr at 0xE0 ACC ; /* ACCUMULATOR */ -sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ -sfr at 0xF0 B ; /* B REGISTER */ -sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ -sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ - -/* Page 0x00 */ -sfr at 0x88 TCON ; /* TIMER CONTROL */ -sfr at 0x89 TMOD ; /* TIMER MODE */ -sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */ -sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */ -sfr at 0x91 SSTA0 ; /* UART 0 STATUS */ -sfr at 0x98 SCON0 ; /* UART 0 CONTROL */ -sfr at 0x98 SCON ; /* UART 0 CONTROL */ -sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */ -sfr at 0x99 SBUF ; /* UART 0 BUFFER */ -sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */ -sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */ -sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */ -sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */ -sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */ -sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */ -sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ -sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */ -sfr at 0xB7 FLSCL ; /* FLASH SCALE */ -sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */ -sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ -sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ -sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ -sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ -sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ -sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ -sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ -sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ -sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ -sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ -sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ -sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ -sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ -sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ -sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */ -sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ -sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ -sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ -sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ -sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ -sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ -sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */ -sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */ -sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */ -sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */ -sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */ -sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */ -sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ -sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xEF RSTSRC ; /* RESET SOURCE */ -sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */ -sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ -sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ -sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */ - -/* Page 0x01 */ -sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */ -sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */ -sfr at 0x98 SCON1 ; /* UART 1 CONTROL */ -sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */ -sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */ -sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */ -sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */ -sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */ -sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ -sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ -sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */ - -/* Page 0x02 */ -sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */ -sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */ -sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */ -sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */ -sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */ -sfr at 0xBE ADC2 ; /* ADC 2 DATA */ -sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */ -sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */ -sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */ -sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */ -sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */ -sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */ - -/* Page 0x02 */ -sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */ -sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */ -sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */ -sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */ -sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */ -sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */ -sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */ -sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */ -sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */ -sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */ -sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */ -sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */ -sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */ - -/* Page 0x0F */ -sfr at 0x88 FLSTAT ; /* FLASH STATUS */ -sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */ -sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ -sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */ -sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */ -sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */ -sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */ -sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */ -sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */ -sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */ -sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */ -sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */ -sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */ -sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */ -sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */ -sfr at 0xA3 CCH0LC ; /* CACHE LOCK */ -sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */ -sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */ -sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ -sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ -sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */ -sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */ -sfr at 0xC8 P4 ; /* PORT 4 */ -sfr at 0xD8 P5 ; /* PORT 5 */ -sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */ -sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */ -sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */ -sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */ -sfr at 0xE8 P6 ; /* PORT 6 */ -sfr at 0xF8 P7 ; /* PORT 7 */ - - -/* BIT Registers */ - -/* P0 0x80 */ -sbit at 0x80 P0_0 ; -sbit at 0x81 P0_1 ; -sbit at 0x82 P0_2 ; -sbit at 0x83 P0_3 ; -sbit at 0x84 P0_4 ; -sbit at 0x85 P0_5 ; -sbit at 0x86 P0_6 ; -sbit at 0x87 P0_7 ; - -/* TCON 0x88 */ -sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ -sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ -sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ -sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ -sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ -sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ -sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ -sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ - -/* CPT0CN 0x88 */ -sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */ -sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */ -sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */ -sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */ -sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */ -sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */ -sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */ -sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */ - -/* CPT1CN 0x88 */ -sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */ -sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */ -sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */ -sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */ -sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */ -sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */ -sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */ -sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */ - -/* FLSTAT 0x88 */ -sbit at 0x88 FLHBUSY ; /* FLASH BUSY */ - -/* SCON0 0x98 */ -sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */ -sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */ -sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */ -sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */ -sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */ -sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */ -sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */ -sbit at 0x9C REN ; /* UART 0 RX ENABLE */ -sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */ -sbit at 0x9E SM10 ; /* UART 0 MODE 1 */ -sbit at 0x9F SM00 ; /* UART 0 MODE 0 */ - -/* SCON1 0x98 */ -sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */ -sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */ -sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */ -sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */ -sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */ -sbit at 0x9D MCE1 ; /* UART 1 MCE */ -sbit at 0x9F S1MODE ; /* UART 1 MODE */ - -/* IE 0xA8 */ -sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ -sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ -sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ -sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ -sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */ -sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */ -sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ -sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ - -/* IP 0xB8 */ -sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ -sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ -sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ -sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ -sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ -sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ - -/* SMB0CN 0xC0 */ -sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ -sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ -sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ -sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ -sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ -sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ -sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ -sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ - -/* TMR2CN 0xC8 */ -sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */ -sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */ -sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ -sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ -sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */ -sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ - -/* TMR3CN 0xC8 */ -sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */ -sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */ -sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */ -sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */ -sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */ -sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */ - -/* TMR4CN 0xC8 */ -sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */ -sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */ -sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */ -sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */ -sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */ -sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */ - -/* P4 0xC8 */ -sbit at 0xC8 P4_0 ; -sbit at 0xC9 P4_1 ; -sbit at 0xCA P4_2 ; -sbit at 0xCB P4_3 ; -sbit at 0xCC P4_4 ; -sbit at 0xCD P4_5 ; -sbit at 0xCE P4_6 ; -sbit at 0xCF P4_7 ; - -/* PSW 0xD0 */ -sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ -sbit at 0xD1 F1 ; /* USER FLAG 1 */ -sbit at 0xD2 OV ; /* OVERFLOW FLAG */ -sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ -sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ -sbit at 0xD5 F0 ; /* USER FLAG 0 */ -sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ -sbit at 0xD7 CY ; /* CARRY FLAG */ - -/* PCA0CN D8H */ -sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ -sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ -sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ -sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ -sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ -sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */ -sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ -sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ - -/* P5 0xD8 */ -sbit at 0xD8 P5_0 ; -sbit at 0xD9 P5_1 ; -sbit at 0xDA P5_2 ; -sbit at 0xDB P5_3 ; -sbit at 0xDC P5_4 ; -sbit at 0xDD P5_5 ; -sbit at 0xDE P5_6 ; -sbit at 0xDF P5_7 ; - -/* ADC0CN E8H */ -sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ -sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */ -sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */ -sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */ -sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ -sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */ -sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ -sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ - -/* ADC2CN E8H */ -sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */ -sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */ -sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */ -sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */ -sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */ -sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */ -sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */ -sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */ - -/* P6 0xE8 */ -sbit at 0xE8 P6_0 ; -sbit at 0xE9 P6_1 ; -sbit at 0xEA P6_2 ; -sbit at 0xEB P6_3 ; -sbit at 0xEC P6_4 ; -sbit at 0xED P6_5 ; -sbit at 0xEE P6_6 ; -sbit at 0xEF P6_7 ; - -/* SPI0CN F8H */ -sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ -sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */ -sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */ -sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */ -sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ -sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ -sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ -sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ - -/* P7 0xF8 */ -sbit at 0xF8 P7_0 ; -sbit at 0xF9 P7_1 ; -sbit at 0xFA P7_2 ; -sbit at 0xFB P7_3 ; -sbit at 0xFC P7_4 ; -sbit at 0xFD P7_5 ; -sbit at 0xFE P7_6 ; -sbit at 0xFF P7_7 ; - - -/* Predefined SFR Bit Masks */ - -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ -#define ECCF 0x01 /* PCA0CPMn */ -#define PWM 0x02 /* PCA0CPMn */ -#define TOG 0x04 /* PCA0CPMn */ -#define MAT 0x08 /* PCA0CPMn */ -#define CAPN 0x10 /* PCA0CPMn */ -#define CAPP 0x20 /* PCA0CPMn */ -#define ECOM 0x40 /* PCA0CPMn */ -#define PWM16 0x80 /* PCA0CPMn */ -#define PORSF 0x02 /* RSTSRC */ -#define SWRSF 0x10 /* RSTSRC */ - - -/* SFR PAGE DEFINITIONS */ - -#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */ -#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */ -#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */ -#define CPT0_PAGE 0x01 /* COMPARATOR 0 */ -#define CPT1_PAGE 0x02 /* COMPARATOR 1 */ -#define UART0_PAGE 0x00 /* UART 0 */ -#define UART1_PAGE 0x01 /* UART 1 */ -#define SPI0_PAGE 0x00 /* SPI 0 */ -#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */ -#define ADC0_PAGE 0x00 /* ADC 0 */ -#define ADC2_PAGE 0x02 /* ADC 2 */ -#define SMB0_PAGE 0x00 /* SMBUS 0 */ -#define TMR2_PAGE 0x00 /* TIMER 2 */ -#define TMR3_PAGE 0x01 /* TIMER 3 */ -#define TMR4_PAGE 0x02 /* TIMER 4 */ -#define DAC0_PAGE 0x00 /* DAC 0 */ -#define DAC1_PAGE 0x01 /* DAC 1 */ -#define PCA0_PAGE 0x00 /* PCA 0 */ -#define PLL0_PAGE 0x0F /* PLL 0 */ - -#endif +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal C8051F12x Processor Range + + Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F120_H +#define C8051F120_H + + +/* BYTE Registers */ + +/* All Pages */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */ +sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */ +sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ + +/* Page 0x00 */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */ +sfr at 0x91 SSTA0 ; /* UART 0 STATUS */ +sfr at 0x98 SCON0 ; /* UART 0 CONTROL */ +sfr at 0x98 SCON ; /* UART 0 CONTROL */ +sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */ +sfr at 0x99 SBUF ; /* UART 0 BUFFER */ +sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */ +sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */ +sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */ +sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */ +sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */ +sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ +sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */ +sfr at 0xB7 FLSCL ; /* FLASH SCALE */ +sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */ +sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ +sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ +sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ +sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ +sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ +sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ +sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */ +sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */ +sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */ +sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */ +sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */ +sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */ +sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ +sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ +sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */ + +/* Page 0x01 */ +sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */ +sfr at 0x98 SCON1 ; /* UART 1 CONTROL */ +sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */ +sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */ +sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */ + +/* Page 0x02 */ +sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */ +sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */ +sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */ +sfr at 0xBE ADC2 ; /* ADC 2 DATA */ +sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */ +sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */ +sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */ +sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */ +sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */ +sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */ + +/* Page 0x02 */ +sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */ +sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */ +sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */ +sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */ +sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */ +sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */ +sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */ +sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */ +sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */ +sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */ +sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */ +sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */ +sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */ + +/* Page 0x0F */ +sfr at 0x88 FLSTAT ; /* FLASH STATUS */ +sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */ +sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */ +sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */ +sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */ +sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */ +sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */ +sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */ +sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */ +sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */ +sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */ +sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */ +sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */ +sfr at 0xA3 CCH0LC ; /* CACHE LOCK */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */ +sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */ +sfr at 0xC8 P4 ; /* PORT 4 */ +sfr at 0xD8 P5 ; /* PORT 5 */ +sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */ +sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */ +sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */ +sfr at 0xE8 P6 ; /* PORT 6 */ +sfr at 0xF8 P7 ; /* PORT 7 */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ + +/* CPT0CN 0x88 */ +sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */ +sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */ +sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */ + +/* CPT1CN 0x88 */ +sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */ +sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */ +sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */ + +/* FLSTAT 0x88 */ +sbit at 0x88 FLHBUSY ; /* FLASH BUSY */ + +/* SCON0 0x98 */ +sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */ +sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */ +sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */ +sbit at 0x9C REN ; /* UART 0 RX ENABLE */ +sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */ +sbit at 0x9E SM10 ; /* UART 0 MODE 1 */ +sbit at 0x9F SM00 ; /* UART 0 MODE 0 */ + +/* SCON1 0x98 */ +sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */ +sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */ +sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */ +sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */ +sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */ +sbit at 0x9D MCE1 ; /* UART 1 MCE */ +sbit at 0x9F S1MODE ; /* UART 1 MODE */ + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ +sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ +sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ +sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ +sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ +sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */ +sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */ +sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */ +sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ + +/* TMR3CN 0xC8 */ +sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */ +sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */ +sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */ +sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */ +sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */ + +/* TMR4CN 0xC8 */ +sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */ +sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */ +sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */ +sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */ +sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */ + +/* P4 0xC8 */ +sbit at 0xC8 P4_0 ; +sbit at 0xC9 P4_1 ; +sbit at 0xCA P4_2 ; +sbit at 0xCB P4_3 ; +sbit at 0xCC P4_4 ; +sbit at 0xCD P4_5 ; +sbit at 0xCE P4_6 ; +sbit at 0xCF P4_7 ; + +/* PSW 0xD0 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* CARRY FLAG */ + +/* PCA0CN D8H */ +sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ +sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ +sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ +sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ +sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ +sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */ +sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ +sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ + +/* P5 0xD8 */ +sbit at 0xD8 P5_0 ; +sbit at 0xD9 P5_1 ; +sbit at 0xDA P5_2 ; +sbit at 0xDB P5_3 ; +sbit at 0xDC P5_4 ; +sbit at 0xDD P5_5 ; +sbit at 0xDE P5_6 ; +sbit at 0xDF P5_7 ; + +/* ADC0CN E8H */ +sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ +sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */ +sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */ +sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */ +sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */ +sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ + +/* ADC2CN E8H */ +sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */ +sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */ +sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */ +sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */ +sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */ +sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */ +sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */ +sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */ + +/* P6 0xE8 */ +sbit at 0xE8 P6_0 ; +sbit at 0xE9 P6_1 ; +sbit at 0xEA P6_2 ; +sbit at 0xEB P6_3 ; +sbit at 0xEC P6_4 ; +sbit at 0xED P6_5 ; +sbit at 0xEE P6_6 ; +sbit at 0xEF P6_7 ; + +/* SPI0CN F8H */ +sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */ +sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */ +sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */ +sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ + +/* P7 0xF8 */ +sbit at 0xF8 P7_0 ; +sbit at 0xF9 P7_1 ; +sbit at 0xFA P7_2 ; +sbit at 0xFB P7_3 ; +sbit at 0xFC P7_4 ; +sbit at 0xFD P7_5 ; +sbit at 0xFE P7_6 ; +sbit at 0xFF P7_7 ; + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ + + +/* SFR PAGE DEFINITIONS */ + +#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */ +#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */ +#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */ +#define CPT0_PAGE 0x01 /* COMPARATOR 0 */ +#define CPT1_PAGE 0x02 /* COMPARATOR 1 */ +#define UART0_PAGE 0x00 /* UART 0 */ +#define UART1_PAGE 0x01 /* UART 1 */ +#define SPI0_PAGE 0x00 /* SPI 0 */ +#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */ +#define ADC0_PAGE 0x00 /* ADC 0 */ +#define ADC2_PAGE 0x02 /* ADC 2 */ +#define SMB0_PAGE 0x00 /* SMBUS 0 */ +#define TMR2_PAGE 0x00 /* TIMER 2 */ +#define TMR3_PAGE 0x01 /* TIMER 3 */ +#define TMR4_PAGE 0x02 /* TIMER 4 */ +#define DAC0_PAGE 0x00 /* DAC 0 */ +#define DAC1_PAGE 0x01 /* DAC 1 */ +#define PCA0_PAGE 0x00 /* PCA 0 */ +#define PLL0_PAGE 0x0F /* PLL 0 */ + +#endif diff --git a/Demo/Cygnal/main.c b/Demo/Cygnal/main.c index f2df1c37e..527cb54bf 100644 --- a/Demo/Cygnal/main.c +++ b/Demo/Cygnal/main.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/Cygnal/serial/serial.c b/Demo/Cygnal/serial/serial.c index 385b93fb2..9ae7a3da2 100644 --- a/Demo/Cygnal/serial/serial.c +++ b/Demo/Cygnal/serial/serial.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/Flshlite/FRConfig.h b/Demo/Flshlite/FRConfig.h index faf650384..f743c96a6 100644 --- a/Demo/Flshlite/FRConfig.h +++ b/Demo/Flshlite/FRConfig.h @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/Flshlite/FileIO/fileIO.c b/Demo/Flshlite/FileIO/fileIO.c index 81c557885..87d29b4a8 100644 --- a/Demo/Flshlite/FileIO/fileIO.c +++ b/Demo/Flshlite/FileIO/fileIO.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/Flshlite/FreeRTOSConfig.h b/Demo/Flshlite/FreeRTOSConfig.h index f31634608..5bf5942a7 100644 --- a/Demo/Flshlite/FreeRTOSConfig.h +++ b/Demo/Flshlite/FreeRTOSConfig.h @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/Flshlite/ParTest/ParTest.c b/Demo/Flshlite/ParTest/ParTest.c index 775e3a523..9c47f69de 100644 --- a/Demo/Flshlite/ParTest/ParTest.c +++ b/Demo/Flshlite/ParTest/ParTest.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/Flshlite/main.c b/Demo/Flshlite/main.c index 225e4044d..d79d007a1 100644 --- a/Demo/Flshlite/main.c +++ b/Demo/Flshlite/main.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/Flshlite/serial/serial.c b/Demo/Flshlite/serial/serial.c index 9f71b5c7d..02efe0081 100644 --- a/Demo/Flshlite/serial/serial.c +++ b/Demo/Flshlite/serial/serial.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/H8S/RTOSDemo/FreeRTOSConfig.h b/Demo/H8S/RTOSDemo/FreeRTOSConfig.h index 7a0e8081d..128ce186d 100644 --- a/Demo/H8S/RTOSDemo/FreeRTOSConfig.h +++ b/Demo/H8S/RTOSDemo/FreeRTOSConfig.h @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/H8S/RTOSDemo/ParTest/ParTest.c b/Demo/H8S/RTOSDemo/ParTest/ParTest.c index 3e41663d7..985ea90d9 100644 --- a/Demo/H8S/RTOSDemo/ParTest/ParTest.c +++ b/Demo/H8S/RTOSDemo/ParTest/ParTest.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/H8S/RTOSDemo/main.c b/Demo/H8S/RTOSDemo/main.c index ff506699b..21ff199a9 100644 --- a/Demo/H8S/RTOSDemo/main.c +++ b/Demo/H8S/RTOSDemo/main.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/H8S/RTOSDemo/serial/serial.c b/Demo/H8S/RTOSDemo/serial/serial.c index 6afcc6184..84eaa93ed 100644 --- a/Demo/H8S/RTOSDemo/serial/serial.c +++ b/Demo/H8S/RTOSDemo/serial/serial.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h index dd0579913..74b00d0d6 100644 --- a/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h +++ b/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c index b9d905f1c..3b401887e 100644 --- a/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c +++ b/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_CodeWarrior_banked/main.c b/Demo/HCS12_CodeWarrior_banked/main.c index a11d43921..4829e895a 100644 --- a/Demo/HCS12_CodeWarrior_banked/main.c +++ b/Demo/HCS12_CodeWarrior_banked/main.c @@ -1,6 +1,6 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_CodeWarrior_banked/serial/serial.c b/Demo/HCS12_CodeWarrior_banked/serial/serial.c index 642ed2db3..4efb678ac 100644 --- a/Demo/HCS12_CodeWarrior_banked/serial/serial.c +++ b/Demo/HCS12_CodeWarrior_banked/serial/serial.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h index 16c3b370c..993bd2593 100644 --- a/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h +++ b/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c index b9d905f1c..3b401887e 100644 --- a/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c +++ b/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_CodeWarrior_small/main.c b/Demo/HCS12_CodeWarrior_small/main.c index 33f63edb2..d6ad8baec 100644 --- a/Demo/HCS12_CodeWarrior_small/main.c +++ b/Demo/HCS12_CodeWarrior_small/main.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_CodeWarrior_small/serial/serial.c b/Demo/HCS12_CodeWarrior_small/serial/serial.c index fb07258b3..16538ecaf 100644 --- a/Demo/HCS12_CodeWarrior_small/serial/serial.c +++ b/Demo/HCS12_CodeWarrior_small/serial/serial.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_GCC_banked/FreeRTOSConfig.h b/Demo/HCS12_GCC_banked/FreeRTOSConfig.h index a21c9c541..b547a4028 100644 --- a/Demo/HCS12_GCC_banked/FreeRTOSConfig.h +++ b/Demo/HCS12_GCC_banked/FreeRTOSConfig.h @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_GCC_banked/ParTest.c b/Demo/HCS12_GCC_banked/ParTest.c index d3a3b8ee8..d7a55a7d8 100644 --- a/Demo/HCS12_GCC_banked/ParTest.c +++ b/Demo/HCS12_GCC_banked/ParTest.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_GCC_banked/main.c b/Demo/HCS12_GCC_banked/main.c index 5bfd4d998..b21bd3b25 100644 --- a/Demo/HCS12_GCC_banked/main.c +++ b/Demo/HCS12_GCC_banked/main.c @@ -1,6 +1,6 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/HCS12_GCC_banked/startup.c b/Demo/HCS12_GCC_banked/startup.c index b777e8227..689c2c99f 100644 --- a/Demo/HCS12_GCC_banked/startup.c +++ b/Demo/HCS12_GCC_banked/startup.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/dsPIC_MPLAB/FreeRTOSConfig.h b/Demo/dsPIC_MPLAB/FreeRTOSConfig.h index eee614899..1d5e40c8c 100644 --- a/Demo/dsPIC_MPLAB/FreeRTOSConfig.h +++ b/Demo/dsPIC_MPLAB/FreeRTOSConfig.h @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. @@ -77,4 +77,6 @@ to exclude the API function. */ #define INCLUDE_vTaskDelay 1 +#define configKERNEL_INTERRUPT_PRIORITY 0x01 + #endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/dsPIC_MPLAB/ParTest/ParTest.c b/Demo/dsPIC_MPLAB/ParTest/ParTest.c index 75a184c3c..86c45a9ad 100644 --- a/Demo/dsPIC_MPLAB/ParTest/ParTest.c +++ b/Demo/dsPIC_MPLAB/ParTest/ParTest.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. diff --git a/Demo/dsPIC_MPLAB/RTOSDemo.mcw b/Demo/dsPIC_MPLAB/RTOSDemo.mcw index a85e0aebd8b172936f0764fd909627a39d5b1ad1..02fb43b1d3e5180cfd8962a2320a08269489b085 100644 GIT binary patch delta 1503 zcmaJBZA@EL^q%$s{Qy?VT9}ql+!xyr$_iUiKKfcHRlruJV6_Ii@j^@~Z7AczG^Lrt zk!4Z3yZH9Q=r-ntnVT+6_H@xmvgtI_#Q)P|YE1kw9cHjFqttUBEiN(fv?u5Lo^$Rw z_a#oM6DQRlomFs`2qCF?#dRoHsEORa`Q8msqGlmA$sJKroyw@oN3r`k&%Rb66s`^( z7^mA*t|>zJc>66!{G6hh*ntrI%b?4tCkn+HZz6@{!`D>W0Loiroq>G+hn}?f9Pyo; zm#|nC2l%T*T7|ZiWj)cY=t=4Cv$04{GL}XNAq~9mj1yvz54LSJ)e&|cb3TTK-;iHM zbU)fcl$lCuQEo&mKxAOQZKUPuGAHw6x?Dt70D~IDRqQ(JYepH95H-?-S>ZKdGAr_S zJp0a86P;3T%2Tzpq2>gASG}3%whuegF=RrB0R`znO@fnGa zGZ~R8H5JDa^aqy z-qiS}vRyG+F5gBv&Eg-18ETAq(-m@#Ipk0MWt4LSKjGu7Q+Bfq*ce8a^jLB_&Bns& zj-ZbXFYXTd96sZWXMLH^J7=5_r)Ra58@5#NI50xkGSzuc&|BIaJCKqIjPm?wjEyk^ zLLOq(ef|0@Sk*dO!IjX~eBChiN2)O5W5gF?=GbAR48FpZ(Cs%7FGfC#ygSc8*qSg~ z6PJu-r~4UZVmbzHkAZNEV$9N{S=KM&d38s4d5y=El-D;OFBnwGh2w^%!Ucarp7-Zh zmhoAnq8oBRQ3~``-7{bllRIG-UD8eFt~@f0RvImuR=Az1KZ{&o@4zh1C;V;xR$Z+~P7IX=P{R2_&Q_j9FZzu2Yqbp4mAIg#Mhh9*X zr?zc;jMsGx^q0=P{<&wa!8$$DTXmi$gY(CGgu=D-u$V2Q=ZDQ3@9Ih6liqQ6fB!gZ zoPqiD{7dKrz zSm6T4?Z(ZL=56qnvdcRX9vlgTTnC4Snrbx}X`e6{5{5^cELnvk93FkxeBj`S@UOL9 z7#2nXLroT`sS)Zq_!?)?az6Y#z&Qsfq;L-mfMjd~6G#ac*tjAK=3lR!^>8_`7p`=| z1i)2kvI}lNk^IH#lkXP4Tao1|+FV>CB|Na8*2#4Zn5MY|6k7Z-eB z7ehYSB%by`S>c|SN%tjk@svT{7x5b(G>Uf*!5&V7AYFYCT%fKcwWOX{NCOtVSF~3G zN3V01oLVfA!#Q>2v!{^-RE++=B9#nIfH>;`i!{*(9lLVza6(LL6InV6Zv$MUfnf3F Wh##)J0oOjw1@>mu8HcA8`S1^)6WY`O delta 1437 zcmY)uZA@EL^qkiRr5$Cp(DES&-NbDUmTi=YLuG|RIyY!16GLFx7_ylVY+0K<&=;v> zY|9cq$~8WI5Xa^+F)n1Y$sQ*AQ6rmM786YxTw*lS#H3N97}2oAQO~_?mwA%&&i6fE z_rA!KDKcfcd_j^|Q>j#JR$4&Il1rLj{^bT5fFL$1pE6kUiF;wcuhTOy6xcG!&K!Ejx-bb5Y3sDZ+2%jOeaDiaP zQpze#6)oJ)N^&mYwBZA8g6)K>)EU=vs3PP!@`y&NB)>$->WB|f?0#1n8#9#}R|2i1 znPX>7>)i>Z{4X1n{Qj;Qq)M|DpK-cW@*ppOcZkQkbaLk$eEpbiI4XauoYoTxmkF7{ z?A#D1{f3famD8WS#VWUPXeOT1ky|2`?J-wWXX3!$mYxW=XQ3v`u(!;Od|&LgxqB?z zE2ouWMyV8cj4a#eYlrQ|s2ZtQr>>CPci*9Y$QSU?h9ZKeXM| z7O>n$W9Eg#LThtSx(@6$YX`g8Rl}C8qq*tF!$OZtNZ@8~m>n^zZ7XV>KCCSik0&@0 z0(t-dEjxQ#ds(D#9Hp3{sMXD82InWc1`0CIFO!6Yy1sXw{?!Hrjef;@=#Z#{mtJ*l z_NUlaH&FO#!wPoB7G6r4aW&f47)u`Rxt=R7dzBV_5;yDNjd;(TDNYO3;RMS1y*m6v z77t&aZNT>p`g5=2xQqkLZEN~yS3TmzW|Z`J1W%%tXvIs~ALF>A#LPj=4#5AXO-yuQ z$p(6)4IAVf{vTPr($|7l_u>fRpg!7;U!v?8INr-T3d^+NZd|8Fd>A)rtQ%{!ligTU z(og^({SfA-UZRB*IXv*n(|6=68unndRDVE=cjGSYvJb8JsnFpL?Q9S3!&q8+N=O%b z5V1?c4y?7_kzXxO-#z+$7(UOT3+2cO0ZL2SxgPWt1j%}s(xD&ZTPUpk53CsE$38A^ zJpgHU9M-<+!)n6=`Iz?Rk%#4wwr%iXIh;Pgl?~8G4&t88xmZsr%hMZKK7-SUG^zkz TeH*{HmMi`{ri}4NWYOm diff --git a/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcp b/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcp index 62952f51b..c0b8b324b 100644 --- a/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcp +++ b/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcp @@ -36,6 +36,8 @@ file_016=no file_017=no file_018=no file_019=no +file_020=no +file_021=no [FILE_INFO] file_000=main.c file_001=..\..\source\list.c @@ -51,12 +53,14 @@ file_010=..\Common\Minimal\blocktim.c file_011=..\Common\Minimal\integer.c file_012=..\Common\Minimal\comtest.c file_013=serial\serial.c -file_014=..\..\source\include\semphr.h -file_015=..\..\source\include\task.h -file_016=..\..\source\include\croutine.h -file_017=..\..\source\include\queue.h -file_018=FreeRTOSConfig.h -file_019=p33FJ256GP710.gld +file_014=timertest.c +file_015=lcd.c +file_016=..\..\source\include\semphr.h +file_017=..\..\source\include\task.h +file_018=..\..\source\include\croutine.h +file_019=..\..\source\include\queue.h +file_020=FreeRTOSConfig.h +file_021=p33FJ256GP710.gld [SUITE_INFO] suite_guid={479DDE59-4D56-455E-855E-FFF59A3DB57E} suite_state= @@ -65,3 +69,7 @@ TS{7D9C6ECE-785D-44CB-BA22-17BF2E119622}=-g TS{25AC22BD-2378-4FDB-BFB6-7345A15512D3}=-g -Wall -DMPLAB_DSPIC_PORT -O2 -fomit-frame-pointer -fno-schedule-insns -fno-schedule-insns2 TS{7DAC9A1D-4C45-45D6-B25A-D117C74E8F5A}=--defsym=__ICD2RAM=1 -Map="$(TARGETBASE).map" -o"$(TARGETBASE).$(TARGETSUFFIX)" TS{509E5861-1E2A-483B-8B6B-CA8DB7F2DD78}= +[INSTRUMENTED_TRACE] +enable=0 +transport=0 +format=0 diff --git a/Demo/dsPIC_MPLAB/lcd.c b/Demo/dsPIC_MPLAB/lcd.c new file mode 100644 index 000000000..729735ecb --- /dev/null +++ b/Demo/dsPIC_MPLAB/lcd.c @@ -0,0 +1,332 @@ +/* + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along + with commercial development and support options. + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "lcd.h" + +/* + * The LCD is written to by more than one task so is controlled by this + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the LCD directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vLCDTask( void *pvParameters ); + +/* + * Setup the peripherals required to communicate with the LCD. + */ +static void prvSetupLCD( void ); + +/* + * Move to the first (0) or second (1) row of the LCD. + */ +static void prvLCDGotoRow( unsigned portSHORT usRow ); + +/* + * Write a string of text to the LCD. + */ +static void prvLCDPutString( portCHAR *pcString ); + +/* + * Clear the LCD. + */ +static void prvLCDClear( void ); + +/*-----------------------------------------------------------*/ + +/* Brief delay to permit the LCD to catch up with commands. */ +#define lcdVERY_SHORT_DELAY ( 1 ) +#define lcdSHORT_DELAY ( 4 / portTICK_RATE_MS ) +#define lcdLONG_DELAY ( 15 / portTICK_RATE_MS ) + +/* LCD commands. */ +#define lcdCLEAR ( 0x01 ) +#define lcdHOME ( 0x02 ) +#define lcdLINE2 ( 0xc0 ) + +/* SFR that seems to be missing from the standard header files. */ +#define PMAEN *( ( unsigned short * ) 0x60c ) + +/* LCD R/W signal. */ +#define lcdRW LATDbits.LATD5 + +/* LCD lcdRS signal. */ +#define lcdRS LATBbits.LATB15 + +/* LCD lcdE signal . */ +#define lcdE LATDbits.LATD4 + +/* Control signal pin direction. */ +#define RW_TRIS TRISDbits.TRISD5 +#define RS_TRIS TRISBbits.TRISB15 +#define E_TRIS TRISDbits.TRISD4 + +/* Port for LCD data */ +#define lcdDATA LATE +#define lcdDATAPORT PORTE + +/* I/O setup for data Port. */ +#define TRISDATA TRISE + +/* The length of the queue used to send messages to the LCD gatekeeper task. */ +#define lcdQUEUE_SIZE 3 +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the LCD task. */ +xQueueHandle xLCDQueue; + +static void prvLCDCommand( portCHAR cCommand ); +static void prvLCDData( portCHAR cChar ); + +/*-----------------------------------------------------------*/ + +xQueueHandle xStartLCDTask( void ) +{ + /* Create the queue used by the LCD task. Messages for display on the LCD + are received via this queue. */ + xLCDQueue = xQueueCreate( lcdQUEUE_SIZE, sizeof( xLCDMessage ) ); + + /* Start the task that will write to the LCD. The LCD hardware is + initialised from within the task itself so delays can be used. */ + xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL ); + + return xLCDQueue; +} +/*-----------------------------------------------------------*/ + +static void prvLCDGotoRow( unsigned portSHORT usRow ) +{ + if( usRow == 0 ) + { + prvLCDCommand( lcdHOME ); + } + else + { + prvLCDCommand( lcdLINE2 ); + } +} +/*-----------------------------------------------------------*/ + +static void prvLCDCommand( portCHAR cCommand ) +{ + /* Prepare RD0 - RD7. */ + lcdDATA &= 0xFF00; + + /* Command byte to lcd. */ + lcdDATA |= cCommand; + + /* Ensure lcdRW is 0. */ + lcdRW = 0; + lcdRS = 0; + + /* Toggle lcdE line. */ + lcdE = 1; + vTaskDelay( lcdVERY_SHORT_DELAY ); + lcdE = 0; + + vTaskDelay( lcdSHORT_DELAY ); +} +/*-----------------------------------------------------------*/ + +static void prvLCDData( portCHAR cChar ) +{ + /* ensure lcdRW is 0. */ + lcdRW = 0; + + /* Assert register select to 1. */ + lcdRS = 1; + + /* Prepare RD0 - RD7. */ + lcdDATA &= 0xFF00; + + /* Data byte to lcd. */ + lcdDATA |= cChar; + lcdE = 1; + Nop(); + Nop(); + Nop(); + + /* Toggle lcdE signal. */ + lcdE = 0; + + /* Negate register select to 0. */ + lcdRS = 0; + + vTaskDelay( lcdVERY_SHORT_DELAY ); +} +/*-----------------------------------------------------------*/ + +static void prvLCDPutString( portCHAR *pcString ) +{ + /* Write out each character with appropriate delay between each. */ + while( *pcString ) + { + prvLCDData( *pcString ); + pcString++; + vTaskDelay( lcdSHORT_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void prvLCDClear( void ) +{ + prvLCDCommand( lcdCLEAR ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupLCD( void ) +{ + /* Wait for proper power up. */ + vTaskDelay( lcdLONG_DELAY ); + + /* Set initial states for the data and control pins */ + LATE &= 0xFF00; + + /* R/W state set low. */ + lcdRW = 0; + + /* lcdRS state set low. */ + lcdRS = 0; + + /* lcdE state set low. */ + lcdE = 0; + + /* Set data and control pins to outputs */ + TRISE &= 0xFF00; + + /* lcdRW pin set as output. */ + RW_TRIS = 0; + + /* lcdRS pin set as output. */ + RS_TRIS = 0; + + /* lcdE pin set as output. */ + E_TRIS = 0; + + /* 1st LCD initialization sequence */ + lcdDATA &= 0xFF00; + lcdDATA |= 0x0038; + lcdE = 1; + Nop(); + Nop(); + Nop(); + + /* Toggle lcdE signal. */ + lcdE = 0; + + vTaskDelay( lcdSHORT_DELAY ); + vTaskDelay( lcdSHORT_DELAY ); + vTaskDelay( lcdSHORT_DELAY ); + + /* 2nd LCD initialization sequence */ + lcdDATA &= 0xFF00; + lcdDATA |= 0x0038; + lcdE = 1; + Nop(); + Nop(); + Nop(); + + /* Toggle lcdE signal. */ + lcdE = 0; + + vTaskDelay( lcdSHORT_DELAY ); + + /* 3rd LCD initialization sequence */ + lcdDATA &= 0xFF00; + lcdDATA |= 0x0038; + lcdE = 1; + Nop(); + Nop(); + Nop(); + + /* Toggle lcdE signal. */ + lcdE = 0; + + vTaskDelay( lcdSHORT_DELAY ); + + + /* Function set. */ + prvLCDCommand( 0x38 ); + + /* Display on/off control, cursor blink off (0x0C). */ + prvLCDCommand( 0x0C ); + + /* Entry mode set (0x06). */ + prvLCDCommand( 0x06 ); + + prvLCDCommand( lcdCLEAR ); +} +/*-----------------------------------------------------------*/ + +static void vLCDTask( void *pvParameters ) +{ +xLCDMessage xMessage; +unsigned portSHORT usRow = 0; + + /* Initialise the hardware. This uses delays so must not be called prior + to the scheduler being started. */ + prvSetupLCD(); + + /* Welcome message. */ + prvLCDPutString( "www.FreeRTOS.org" ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS ); + + /* Clear the current display value. */ + prvLCDClear(); + + /* Switch rows each time so we can see that the display is still being + updated. */ + prvLCDGotoRow( usRow & 0x01 ); + usRow++; + prvLCDPutString( xMessage.pcMessage ); + + /* Delay the requested amount of time to ensure the text just written + to the LCD is not overwritten. */ + vTaskDelay( xMessage.xMinDisplayTime ); + } +} + + + + diff --git a/Demo/dsPIC_MPLAB/lcd.h b/Demo/dsPIC_MPLAB/lcd.h new file mode 100644 index 000000000..e11c583ae --- /dev/null +++ b/Demo/dsPIC_MPLAB/lcd.h @@ -0,0 +1,57 @@ +/* + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along + with commercial development and support options. + *************************************************************************** +*/ + +#ifndef LCD_INC_H +#define LCD_INC_H + +/* Create the task that will control the LCD. Returned is a handle to the queue +on which messages to get written to the LCD should be written. */ +xQueueHandle xStartLCDTask( void ); + +typedef struct +{ + /* The minimum amount of time the message should remain on the LCD without + being overwritten. */ + portTickType xMinDisplayTime; + + /* A pointer to the string to be displayed. */ + portCHAR *pcMessage; + +} xLCDMessage; + + +#endif /* LCD_INC_H */ + + diff --git a/Demo/dsPIC_MPLAB/main.c b/Demo/dsPIC_MPLAB/main.c index 5e95286d2..c130cf182 100644 --- a/Demo/dsPIC_MPLAB/main.c +++ b/Demo/dsPIC_MPLAB/main.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. @@ -36,40 +36,42 @@ /* * Creates all the demo application tasks, then starts the scheduler. The WEB * documentation provides more details of the standard demo application tasks. - * In addition to the standard demo tasks, the following tasks are defined - * within this file: - * - * "Register test" tasks - These tasks first set all the general purpose - * registers to a known value (with each register containing a different value) - * then test each general purpose register to ensure it still contains the - * set value. There are two register test tasks, with different values being - * used by each. The register test tasks will be preempted frequently due to - * their low priority. Setting then testing the value of each register in this - * manner ensures the context of the tasks is being correctly saved and then - * restored as the preemptive context switches occur. An error is flagged - * should any register be found to contain an unexpected value. In addition - * the register test tasks maintain a count of the number of times they cycle, - * so an error can also be flagged should the cycle count not increment as - * expected (indicating the the tasks are not executing at all). + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt + * timing. The maximum measured jitter time is latched in the usMaxJitter + * variable, and displayed on the LCD by the 'Check' as described below. + * The fast interrupt is configured and handled in the timer_test.c source + * file. * + * "LCD" task - the LCD task is a 'gatekeeper' task. It is the only task that + * is permitted to access the LCD directly. Other tasks wishing to write a + * message to the LCD send the message on a queue to the LCD task instead of + * accessing the LCD themselves. The LCD task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. The LCD + * task is defined in lcd.c. + * * "Check" task - This only executes every three seconds but has the highest * priority so is guaranteed to get processor time. Its main function is to - * check that all the other tasks are still operational. Each task maintains a - * unique count that is incremented each time the task successfully completes - * its function. Should any error occur within such a task the count is - * permanently halted. The check task inspects the count of each task to - * ensure it has changed since the last time the check task executed. If all - * the count variables have changed all the tasks are still executing error - * free, and the check task toggles the onboard LED. Should any task contain - * an error at any time check task cycle frequency is increased to 500ms, - * causing the LED toggle rate to increase from 3 seconds to 500ms and in so - * doing providing visual feedback that an error has occurred. - * + * check that all the standard demo tasks are still operational. Should any + * unexpected behaviour within a demo task be discovered the 'check' task will + * write "FAIL #n" to the LCD (via the LCD task). If all the demo tasks are + * executing with their expected behaviour then the check task writes the max + * jitter time to the LCD (again via the LCD task), as described above. */ +/* Standard includes. */ +#include + /* Scheduler includes. */ #include "FreeRTOS.h" #include "task.h" +#include "queue.h" #include "croutine.h" /* Demo application includes. */ @@ -79,36 +81,45 @@ #include "integer.h" #include "comtest2.h" #include "partest.h" +#include "lcd.h" +#include "timertest.h" /* Demo task priorities. */ #define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) #define mainCOM_TEST_PRIORITY ( 2 ) -/* Delay between check task cycles when an error has/has not been detected. */ -#define mainNO_ERROR_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) +/* The check task may require a bit more stack as it calls sprintf(). */ +#define mainCHECK_TAKS_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) + +/* The execution period of the check task. */ +#define mainCHECK_TASK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) /* The number of flash co-routines to create. */ -#define mainNUM_FLASH_COROUTINES ( 3 ) +#define mainNUM_FLASH_COROUTINES ( 5 ) /* Baud rate used by the comtest tasks. */ #define mainCOM_TEST_BAUD_RATE ( 19200 ) /* The LED used by the comtest tasks. mainCOM_TEST_LED + 1 is also used. See the comtest.c file for more information. */ -#define mainCOM_TEST_LED ( 4 ) +#define mainCOM_TEST_LED ( 6 ) -/* The LED used by the check task. */ -#define mainCHECK_LED ( 7 ) +/* The frequency at which the "fast interrupt test" interrupt will occur. */ +#define mainTEST_INTERRUPT_FREQUENCY ( 20000 ) -/*-----------------------------------------------------------*/ +/* The number of processor clocks we expect to occur between each "fast +interrupt test" interrupt. */ +#define mainEXPECTED_CLOCKS_BETWEEN_INTERRUPTS ( configCPU_CLOCK_HZ / mainTEST_INTERRUPT_FREQUENCY ) -/* - * The register test tasks as described at the top of this file. - */ -void xRegisterTest1( void *pvParameters ); -void xRegisterTest2( void *pvParameters ); +/* The number of nano seconds between each processor clock. */ +#define mainNS_PER_CLOCK ( ( unsigned portSHORT ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + +/* Dimension the buffer used to hold the value of the maximum jitter time when +it is converted to a string. */ +#define mainMAX_STRING_LENGTH ( 20 ) + +/*-----------------------------------------------------------*/ /* * The check task as described at the top of this file. @@ -122,13 +133,8 @@ static void prvSetupHardware( void ); /*-----------------------------------------------------------*/ -/* Variables used to detect errors within the register test tasks. */ -static volatile unsigned portSHORT usTest1CycleCounter = 0, usTest2CycleCounter = 0; -static unsigned portSHORT usPreviousTest1Count = 0, usPreviousTest2Count = 0; - -/* Set to pdTRUE should an error be detected in any of the standard demo tasks -or tasks defined within this file. */ -static unsigned portSHORT usErrorDetected = pdFALSE; +/* The queue used to send messages to the LCD task. */ +static xQueueHandle xLCDQueue; /*-----------------------------------------------------------*/ @@ -148,9 +154,14 @@ int main( void ) vCreateBlockTimeTasks(); /* Create the test tasks defined within this file. */ - xTaskCreate( xRegisterTest1, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &usTest1CycleCounter, tskIDLE_PRIORITY, NULL ); - xTaskCreate( xRegisterTest2, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &usTest2CycleCounter, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TAKS_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the task that will control the LCD. This returns the handle + to the queue used to write text out to the task. */ + xLCDQueue = xStartLCDTask(); + + /* Start the high frequency interrupt test. */ + vSetupTimerTest( mainTEST_INTERRUPT_FREQUENCY ); /* Finally start the scheduler. */ vTaskStartScheduler(); @@ -169,11 +180,23 @@ static void prvSetupHardware( void ) static void vCheckTask( void *pvParameters ) { -portTickType xLastExecutionTime; +/* Used to wake the task at the correct frequency. */ +portTickType xLastExecutionTime; + +/* The maximum jitter time measured by the fast interrupt test. */ +extern unsigned portSHORT usMaxJitter ; -/* Start with the no error delay. The long delay will cause the LED to flash -slowly. */ -portTickType xDelay = mainNO_ERROR_DELAY; +/* Buffer into which the maximum jitter time is written as a string. */ +static portCHAR cStringBuffer[ mainMAX_STRING_LENGTH ]; + +/* The message that is sent on the queue to the LCD task. The first +parameter is the minimum time (in ticks) that the message should be +left on the LCD without being overwritten. The second parameter is a pointer +to the message to display itself. */ +xLCDMessage xMessage = { 0, cStringBuffer }; + +/* Set to pdTRUE should an error be detected in any of the standard demo tasks. */ +unsigned portSHORT usErrorDetected = pdFALSE; /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() works correctly. */ @@ -182,235 +205,43 @@ portTickType xDelay = mainNO_ERROR_DELAY; for( ;; ) { /* Wait until it is time for the next cycle. */ - vTaskDelayUntil( &xLastExecutionTime, xDelay ); + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_PERIOD ); /* Has an error been found in any of the standard demo tasks? */ if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) { usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #1" ); } if( xAreComTestTasksStillRunning() != pdTRUE ) { usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #2" ); } if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) { usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #3" ); } if( xAreBlockingQueuesStillRunning() != pdTRUE ) { usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #4" ); } - - /* Are the register test tasks still cycling? */ - - if( usTest1CycleCounter == usPreviousTest1Count ) - { - usErrorDetected = pdTRUE; - } - - if( usTest2CycleCounter == usPreviousTest2Count ) + if( usErrorDetected == pdFALSE ) { - usErrorDetected = pdTRUE; + /* No errors have been discovered, so display the maximum jitter + timer discovered by the "fast interrupt test". */ + sprintf( cStringBuffer, "%dns max jitter", ( portSHORT ) ( usMaxJitter - mainEXPECTED_CLOCKS_BETWEEN_INTERRUPTS ) * mainNS_PER_CLOCK ); } - usPreviousTest2Count = usTest2CycleCounter; - usPreviousTest1Count = usTest1CycleCounter; - - - /* If an error has been detected in any task then the delay will be - reduced to increase the cycle rate of this task. This has the effect - of causing the LED to flash much faster giving a visual indication of - the error condition. */ - if( usErrorDetected != pdFALSE ) - { - xDelay = mainERROR_DELAY; - } - - /* Finally, toggle the LED before returning to delay to wait for the - next cycle. */ - vParTestToggleLED( mainCHECK_LED ); - } -} -/*-----------------------------------------------------------*/ - -void xRegisterTest1( void *pvParameters ) -{ -/* This static so as not to use the frame pointer. They are volatile -also to avoid it being stored in a register that we clobber during the test. */ -static unsigned portSHORT * volatile pusParameter; - - /* The variable incremented by this task is passed in as the parameter - even though it is defined within this file. This is just to test the - parameter passing mechanism. */ - pusParameter = pvParameters; - - for( ;; ) - { - /* Increment the variable to show this task is still cycling. */ - ( *pusParameter )++; - - /* Set the w registers to known values, then check that each register - contains the expected value. See the explanation at the top of this - file for more information. */ - asm volatile( "mov.w #0x0101, W0 \n" \ - "mov.w #0x0102, W1 \n" \ - "mov.w #0x0103, W2 \n" \ - "mov.w #0x0104, W3 \n" \ - "mov.w #0x0105, W4 \n" \ - "mov.w #0x0106, W5 \n" \ - "mov.w #0x0107, W6 \n" \ - "mov.w #0x0108, W7 \n" \ - "mov.w #0x0109, W8 \n" \ - "mov.w #0x010a, W9 \n" \ - "mov.w #0x010b, W10 \n" \ - "mov.w #0x010c, W11 \n" \ - "mov.w #0x010d, W12 \n" \ - "mov.w #0x010e, W13 \n" \ - "mov.w #0x010f, W14 \n" \ - "sub #0x0101, W0 \n" \ - "cp0.w W0 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0102, W1 \n" \ - "cp0.w W1 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0103, W2 \n" \ - "cp0.w W2 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0104, W3 \n" \ - "cp0.w W3 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0105, W4 \n" \ - "cp0.w W4 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0106, W5 \n" \ - "cp0.w W5 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0107, W6 \n" \ - "cp0.w W6 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0108, W7 \n" \ - "cp0.w W7 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0109, W8 \n" \ - "cp0.w W8 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010a, W9 \n" \ - "cp0.w W9 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010b, W10 \n" \ - "cp0.w W10 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010c, W11 \n" \ - "cp0.w W11 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010d, W12 \n" \ - "cp0.w W12 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010e, W13 \n" \ - "cp0.w W13 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010f, W14 \n" \ - "cp0.w W14 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "bra NO_ERROR1 \n" \ - "ERROR_TEST1: \n" \ - "mov.w #1, W0 \n" \ - "mov.w W0, _usErrorDetected\n" \ - "NO_ERROR1: \n" ); - } -} -/*-----------------------------------------------------------*/ - -void xRegisterTest2( void *pvParameters ) -{ -/* This static so as not to use the frame pointer. They are volatile -also to avoid it being stored in a register that we clobber during the test. */ -static unsigned portSHORT * volatile pusParameter; - - /* The variable incremented by this task is passed in as the parameter - even though it is defined within this file. This is just to test the - parameter passing mechanism. */ - pusParameter = pvParameters; - - for( ;; ) - { - /* Increment the variable to show this task is still cycling. */ - ( *pusParameter )++; - - /* Set the w registers to known values, then check that each register - contains the expected value. See the explanation at the top of this - file for more information. */ - asm volatile( "mov.w #0x0100, W0 \n" \ - "mov.w #0x0101, W1 \n" \ - "mov.w #0x0102, W2 \n" \ - "mov.w #0x0103, W3 \n" \ - "mov.w #0x0104, W4 \n" \ - "mov.w #0x0105, W5 \n" \ - "mov.w #0x0106, W6 \n" \ - "mov.w #0x0107, W7 \n" \ - "mov.w #0x0108, W8 \n" \ - "mov.w #0x0109, W9 \n" \ - "mov.w #0x010a, W10 \n" \ - "mov.w #0x010b, W11 \n" \ - "mov.w #0x010c, W12 \n" \ - "mov.w #0x010d, W13 \n" \ - "mov.w #0x010e, W14 \n" \ - "sub #0x0100, W0 \n" \ - "cp0.w W0 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0101, W1 \n" \ - "cp0.w W1 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0102, W2 \n" \ - "cp0.w W2 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0103, W3 \n" \ - "cp0.w W3 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0104, W4 \n" \ - "cp0.w W4 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0105, W5 \n" \ - "cp0.w W5 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0106, W6 \n" \ - "cp0.w W6 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0107, W7 \n" \ - "cp0.w W7 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0108, W8 \n" \ - "cp0.w W8 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0109, W9 \n" \ - "cp0.w W9 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010a, W10 \n" \ - "cp0.w W10 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010b, W11 \n" \ - "cp0.w W11 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010c, W12 \n" \ - "cp0.w W12 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010d, W13 \n" \ - "cp0.w W13 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010e, W14 \n" \ - "cp0.w W14 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "bra NO_ERROR2 \n" \ - "ERROR_TEST2: \n" \ - "mov.w #1, W0 \n" \ - "mov.w W0, _usErrorDetected\n" \ - "NO_ERROR2: \n" ); + /* Send the message to the LCD gatekeeper for display. */ + xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY ); } } /*-----------------------------------------------------------*/ @@ -421,3 +252,4 @@ void vApplicationIdleHook( void ) vCoRoutineSchedule(); } /*-----------------------------------------------------------*/ + diff --git a/Demo/dsPIC_MPLAB/serial/serial.c b/Demo/dsPIC_MPLAB/serial/serial.c index ee2bd1298..a92d767e0 100644 --- a/Demo/dsPIC_MPLAB/serial/serial.c +++ b/Demo/dsPIC_MPLAB/serial/serial.c @@ -1,5 +1,5 @@ /* - FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry. + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. This file is part of the FreeRTOS.org distribution. @@ -116,8 +116,8 @@ portCHAR cChar; IFS1bits.U2RXIF = serCLEAR_FLAG; IFS1bits.U2TXIF = serCLEAR_FLAG; - IPC7bits.U2RXIP = portKERNEL_INTERRUPT_PRIORITY; - IPC7bits.U2TXIP = portKERNEL_INTERRUPT_PRIORITY; + IPC7bits.U2RXIP = configKERNEL_INTERRUPT_PRIORITY; + IPC7bits.U2TXIP = configKERNEL_INTERRUPT_PRIORITY; IEC1bits.U2TXIE = serINTERRUPT_ENABLE; IEC1bits.U2RXIE = serINTERRUPT_ENABLE; @@ -179,10 +179,7 @@ void vSerialClose( xComPortHandle xPort ) } /*-----------------------------------------------------------*/ -volatile short s = 0; -char c[80] = {0}; - -void __attribute__((__interrupt__)) _U2RXInterrupt( void ) +void __attribute__((__interrupt__, auto_psv)) _U2RXInterrupt( void ) { portCHAR cChar; portBASE_TYPE xYieldRequired = pdFALSE; @@ -204,7 +201,7 @@ portBASE_TYPE xYieldRequired = pdFALSE; } /*-----------------------------------------------------------*/ -void __attribute__((__interrupt__)) _U2TXInterrupt( void ) +void __attribute__((__interrupt__, auto_psv)) _U2TXInterrupt( void ) { signed portCHAR cChar; portBASE_TYPE xTaskWoken = pdFALSE; diff --git a/Demo/dsPIC_MPLAB/timertest.c b/Demo/dsPIC_MPLAB/timertest.c new file mode 100644 index 000000000..633c2d2f4 --- /dev/null +++ b/Demo/dsPIC_MPLAB/timertest.c @@ -0,0 +1,144 @@ +/* + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along + with commercial development and support options. + *************************************************************************** +*/ + +/* High speed timer test as described in main.c. */ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "partest.h" + +/* The number of interrupts to pass before we start looking at the jitter. */ +#define timerSETTLE_TIME 5 + +/* The maximum value the 16bit timer can contain. */ +#define timerMAX_COUNT 0xffff + +/*-----------------------------------------------------------*/ + +/* + * Measure the time between this interrupt and the previous interrupt to + * calculate the timing jitter. Remember the maximum value the jitter has + * ever been calculated to be. + */ +static void prvCalculateAndStoreJitter( void ); + +/*-----------------------------------------------------------*/ + +/* The maximum time (in processor clocks) between two consecutive timer +interrupts so far. */ +unsigned portSHORT usMaxJitter = 0; + +/*-----------------------------------------------------------*/ + +void vSetupTimerTest( unsigned portSHORT usFrequencyHz ) +{ + /* T2 is used to generate interrupts. T4 is used to provide an accurate + time measurement. */ + T2CON = 0; + T4CON = 0; + TMR2 = 0; + TMR4 = 0; + + /* Timer 2 is going to interrupt at usFrequencyHz Hz. */ + PR2 = ( unsigned portSHORT ) ( configCPU_CLOCK_HZ / ( unsigned portLONG ) usFrequencyHz ); + + /* Timer 4 is going to free run from minimum to maximum value. */ + PR4 = ( unsigned portSHORT ) timerMAX_COUNT; + + /* Setup timer 2 interrupt priority to be above the kernel priority so + the timer jitter is not effected by the kernel activity. */ + IPC1bits.T2IP = configKERNEL_INTERRUPT_PRIORITY + 1; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T2IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T2IE = 1; + + /* Start both timers. */ + T2CONbits.TON = 1; + T4CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +static void prvCalculateAndStoreJitter( void ) +{ +static unsigned portSHORT usLastCount = 0, usSettleCount = 0; +unsigned portSHORT usThisCount, usDifference; + + /* Capture the timer value as we enter the interrupt. */ + usThisCount = TMR4; + + if( usSettleCount >= timerSETTLE_TIME ) + { + /* What is the difference between the timer value in this interrupt + and the value from the last interrupt. */ + usDifference = usThisCount - usLastCount; + + /* Store the difference in the timer values if it is larger than the + currently stored largest value. The difference over and above the + expected difference will give the 'jitter' in the processing of these + interrupts. */ + if( usDifference > usMaxJitter ) + { + usMaxJitter = usDifference; + } + } + else + { + /* Don't bother storing any values for the first couple of + interrupts. */ + usSettleCount++; + } + + /* Remember what the timer value was this time through, so we can calculate + the difference the next time through. */ + usLastCount = usThisCount; +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) _T2Interrupt( void ) +{ + /* Work out the time between this and the previous interrupt. */ + prvCalculateAndStoreJitter(); + + /* Clear the timer interrupt. */ + IFS0bits.T2IF = 0; +} + + diff --git a/Demo/dsPIC_MPLAB/timertest.h b/Demo/dsPIC_MPLAB/timertest.h new file mode 100644 index 000000000..a4b0aeab0 --- /dev/null +++ b/Demo/dsPIC_MPLAB/timertest.h @@ -0,0 +1,45 @@ +/* + FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along + with commercial development and support options. + *************************************************************************** +*/ + +#ifndef TIMER_TEST_H +#define TIMER_TEST_H + +/* Setup the high frequency timer interrupt. */ +void vSetupTimerTest( unsigned portSHORT usFrequencyHz ); + +#endif /* TIMER_TEST_H */ + + + -- 2.39.5