From 6ef9d8978c0d3ad95ff9a9752c3dcda2c90f0806 Mon Sep 17 00:00:00 2001 From: rtel Date: Fri, 20 May 2016 12:18:59 +0000 Subject: [PATCH] Preparing for V9.0.0 formal release: + Update various projects to use the latest versions of their build tools. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2461 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewd | 1230 ++++- .../Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewp | 127 +- .../settings/RTOSDemo.dni | 5 + .../settings/RTOSDemo.wsdt | 6 +- .../RTOSDemo.cproj | 658 ++- .../RTOSDemo/RTOSDemo.cproj | 322 +- .../RTOSDemo/src/main.c | 2 +- .../RTOSDemo.cproj | 273 +- .../.vs/RTOSDemo/v14/.atsuo | Bin 74752 -> 74752 bytes .../RTE/RTE_Components.h | 6 + .../RTOSDemo.ewd | 992 +++- .../RTOSDemo.ewp | 116 +- .../RTOSDemo.ewt | 2144 ++++++++ .../RTOSDemo.uvoptx | 100 +- .../RTOSDemo.uvprojx | 88 +- .../settings/RTOSDemo.Debug.cspy.bat | 6 +- .../settings/RTOSDemo.dni | 1 + .../settings/RTOSDemo.wsdt | 10 +- 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105 - FreeRTOS/Demo/uIP_Demo_IAR_ARM7/main.c | 289 - .../Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac | 194 - .../uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac | 227 - .../resource/at91SAM7X256_FLASH.icf | 43 - .../resource/at91sam7x-ek-flash.mac | 73 - FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd | 1379 ----- FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp | 1696 ------ FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww | 10 - .../uIP_Demo_IAR_ARM7/settings/Basic.dbgdt | 71 - .../Demo/uIP_Demo_IAR_ARM7/settings/Basic.dni | 23 - .../uIP_Demo_IAR_ARM7/settings/BasicSAM7.wsdt | 80 - .../uIP_Demo_IAR_ARM7/settings/rtosdemo.dbgdt | 62 - .../uIP_Demo_IAR_ARM7/settings/rtosdemo.dni | 47 - .../uIP_Demo_IAR_ARM7/settings/rtosdemo.wsdt | 71 - FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c | 207 - FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h | 8 - FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/Makefile | 74 - FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c | 225 - FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h | 57 - 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-12,7 +12,7 @@ C-SPY 2 - 22 + 28 1 1 - + + + + + + + + + + + @@ -242,10 +282,10 @@ - GDBSERVER_ID + CMSISDAP_ID 2 - 0 + 4 1 1 - - - - - - IARROM_ID - 2 - - 1 - 1 - 1 - - - - - - JLINK_ID - 2 - - 13 - 1 - 1 - - - - - + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 - LMIFTDI_ID + IARROM_ID 2 - 2 + 1 1 1 - - + - MACRAIGOR_ID + IJET_ID 2 - 3 + 8 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + - PEMICRO_ID + STLINK_ID 2 - 0 + 3 1 1 + + + + + + + + + + - RDI_ID + THIRDPARTY_ID 2 - 2 + 0 1 1 + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + - STLINK_ID + XDS100_ID 2 - 2 + 5 1 1 + + + + - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin 0 @@ -825,19 +1539,19 @@ 0 - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin 0 @@ -849,28 +1563,20 @@ 0 - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin 0 - $EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin 0 - $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 diff --git a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewp index 18b54fbc0..af590ddc0 100644 --- a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewp @@ -12,7 +12,7 @@ General 3 - 21 + 24 1 1 - - - + + + + + + + ICCARM 2 - 28 + 31 1 1 + + + + AARM 2 - 8 + 9 1 1 + @@ -568,7 +606,7 @@ 1 @@ -614,7 +653,7 @@ ILINK 0 - 13 + 17 1 1 - + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dni index 5c96ed1be..12be697e9 100644 --- a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dni +++ b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dni @@ -55,6 +55,11 @@ SWOInfo_ITMPortsEnabled=0x00000001 SWOInfo_ITMPortsTermIO=0x00000001 SWOInfo_ITMPortsLogFile=0x00000000 SWOInfo_ITMLogFile=$PROJ_DIR$\ITM.log +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +CStepIntDis=_ 0 +LeaveTargetRunning=_ 0 [DataLog] LogEnabled=0 SumEnabled=0 diff --git a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.wsdt index d91c73877..c8ac51d79 100644 --- a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.wsdt +++ b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.wsdt @@ -12,7 +12,7 @@ - 258272727 + 306272727 2012163248120162258082994 @@ -35,14 +35,14 @@ - TextEditor$WS_DIR$\main.c0478010801000100000010000001 + TextEditor$WS_DIR$\main.c00000630000100000010000001 - iaridepm.enu1-2-2670332-2-2240200142857203666198810684318-2-22681682-2-216842701002381274949142857203666 + iaridepm.enu1-2-2780380-2-2274231142708203704198958689594-2-23101922-2-219243121002083275132142708203704 diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/RTOSDemo.cproj b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/RTOSDemo.cproj index 386dc42e9..2a07538de 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/RTOSDemo.cproj +++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/RTOSDemo.cproj @@ -2,7 +2,7 @@ 2.0 - 6.0 + 7.0 {1a1a7c6e-bd59-4e82-8371-7f51ae9a4bd9} $(MSBuildProjectName) $(MSBuildProjectName) @@ -10,163 +10,167 @@ 3.3.0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ATSAM3X8H sam3x C - com.Atmel.ARMGCC + com.Atmel.ARMGCC.C $(MSBuildProjectDirectory)\$(Configuration) $(MSBuildProjectName) @@ -207,210 +211,172 @@ + true + true + + + true + 2 - - - __SAM3X8H__ - True - True - True - True - - - BOARD=SAM3X_EK - __SAM3X8H__ - - - - - ../src - ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek - ../src/asf/common/boards - ../src/asf/common/services/gpio - ../src/asf/common/utils - ../src/asf/sam/boards - ../src/asf/sam/boards/sam3x_ek - ../src/asf/sam/drivers/pio - ../src/asf/sam/utils - ../src/asf/sam/utils/cmsis/sam3x/include - ../src/asf/sam/utils/cmsis/sam3x/source/templates - ../src/asf/sam/utils/header_files - ../src/asf/sam/utils/preprocessor - ../src/asf/thirdparty/CMSIS/Include - ../src/config - C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles - C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\CMSIS\Include - C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL - C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL\sam3xa\include - ../src/asf/sam/drivers/pmc - ../src/asf/common/services/clock - ../src/asf/sam/drivers/usart - - - Optimize for size (-Os) - -fdata-sections - True - True - -pipe -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -Dprintf=iprintf - - - - True - -T../src/asf/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld -Wl,--cref -Wl,--entry=Reset_Handler -mthumb - - - ../src - ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek - ../src/asf/common/boards - ../src/asf/common/services/gpio - ../src/asf/common/utils - ../src/asf/sam/boards - ../src/asf/sam/boards/sam3x_ek - ../src/asf/sam/drivers/pio - ../src/asf/sam/utils - ../src/asf/sam/utils/cmsis/sam3x/include - ../src/asf/sam/utils/cmsis/sam3x/source/templates - ../src/asf/sam/utils/header_files - ../src/asf/sam/utils/preprocessor - ../src/asf/thirdparty/CMSIS/Include - ../src/config - ../src/asf/sam/drivers/pmc - ../src/asf/common/services/clock - ../src/asf/sam/drivers/usart - - - -DBOARD=SAM3X_EK -D__SAM3X8H__ - - - ../src - ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek - ../src/asf/common/boards - ../src/asf/common/services/gpio - ../src/asf/common/utils - ../src/asf/sam/boards - ../src/asf/sam/boards/sam3x_ek - ../src/asf/sam/drivers/pio - ../src/asf/sam/utils - ../src/asf/sam/utils/cmsis/sam3x/include - ../src/asf/sam/utils/cmsis/sam3x/source/templates - ../src/asf/sam/utils/header_files - ../src/asf/sam/utils/preprocessor - ../src/asf/thirdparty/CMSIS/Include - ../src/config - ../src/asf/sam/drivers/pmc - ../src/asf/common/services/clock - ../src/asf/sam/drivers/usart - - - - True True True True - - - - __SAM3X8H__ - True - True - True - True - - - BOARD=SAM3X_EK - __SAM3X8H__ - - - - - ../src - ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek - ../src/asf/common/boards - ../src/asf/common/services/gpio - ../src/asf/common/utils - ../src/asf/sam/boards - ../src/asf/sam/boards/sam3x_ek - ../src/asf/sam/drivers/pio - ../src/asf/sam/utils - ../src/asf/sam/utils/cmsis/sam3x/include - ../src/asf/sam/utils/cmsis/sam3x/source/templates - ../src/asf/sam/utils/header_files - ../src/asf/sam/utils/preprocessor - ../src/asf/thirdparty/CMSIS/Include - ../src/config - ../src/asf/thirdparty/FreeRTOS/include - ../src/asf/thirdparty/FreeRTOS/portable/GCC/ARM_CM3 - ../src/Common-Demo-Source/include - C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles - C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\CMSIS\Include - C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL - C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL\sam3xa\include - ../src/asf/sam/drivers/pmc - ../src/asf/common/services/clock - ../src/asf/sam/drivers/usart - - - -fdata-sections - True - Maximum (-g3) - True - -pipe -Wall -Wextra -std=gnu99 -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -Dprintf=iprintf - True - -T../src/asf/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld -Wl,--cref -Wl,--entry=Reset_Handler -mthumb - - - ../src - ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek - ../src/asf/common/boards - ../src/asf/common/services/gpio - ../src/asf/common/utils - ../src/asf/sam/boards - ../src/asf/sam/boards/sam3x_ek - ../src/asf/sam/drivers/pio - ../src/asf/sam/utils - ../src/asf/sam/utils/cmsis/sam3x/include - ../src/asf/sam/utils/cmsis/sam3x/source/templates - ../src/asf/sam/utils/header_files - ../src/asf/sam/utils/preprocessor - ../src/asf/thirdparty/CMSIS/Include - ../src/config - ../src/asf/sam/drivers/pmc - ../src/asf/common/services/clock - ../src/asf/sam/drivers/usart - - - -DBOARD=SAM3X_EK -D__SAM3X8H__ - - - ../src - ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek - ../src/asf/common/boards - ../src/asf/common/services/gpio - ../src/asf/common/utils - ../src/asf/sam/boards - ../src/asf/sam/boards/sam3x_ek - ../src/asf/sam/drivers/pio - ../src/asf/sam/utils - ../src/asf/sam/utils/cmsis/sam3x/include - ../src/asf/sam/utils/cmsis/sam3x/source/templates - ../src/asf/sam/utils/header_files - ../src/asf/sam/utils/preprocessor - ../src/asf/thirdparty/CMSIS/Include - ../src/config - ../src/asf/sam/drivers/pmc - ../src/asf/common/services/clock - ../src/asf/sam/drivers/usart - - - + + True + True + True + True + True + + + BOARD=SAM3X_EK + __SAM3X8H__ + + + + + ../src + ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek + ../src/asf/common/boards + ../src/asf/common/services/gpio + ../src/asf/common/utils + ../src/asf/sam/boards + ../src/asf/sam/boards/sam3x_ek + ../src/asf/sam/drivers/pio + ../src/asf/sam/utils + ../src/asf/sam/utils/cmsis/sam3x/include + ../src/asf/sam/utils/cmsis/sam3x/source/templates + ../src/asf/sam/utils/header_files + ../src/asf/sam/utils/preprocessor + ../src/asf/thirdparty/CMSIS/Include + ../src/config + C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles + C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\CMSIS\Include + C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL + C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL\sam3xa\include + ../src/asf/sam/drivers/pmc + ../src/asf/common/services/clock + ../src/asf/sam/drivers/usart + + + Optimize for size (-Os) + -fdata-sections + True + True + -pipe -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -Dprintf=iprintf + + + + True + -T../src/asf/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld -Wl,--cref -Wl,--entry=Reset_Handler -mthumb + -DBOARD=SAM3X_EK -D__SAM3X8H__ + + + ../src + ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek + ../src/asf/common/boards + ../src/asf/common/services/gpio + ../src/asf/common/utils + ../src/asf/sam/boards + ../src/asf/sam/boards/sam3x_ek + ../src/asf/sam/drivers/pio + ../src/asf/sam/utils + ../src/asf/sam/utils/cmsis/sam3x/include + ../src/asf/sam/utils/cmsis/sam3x/source/templates + ../src/asf/sam/utils/header_files + ../src/asf/sam/utils/preprocessor + ../src/asf/thirdparty/CMSIS/Include + ../src/config + ../src/asf/sam/drivers/pmc + ../src/asf/common/services/clock + ../src/asf/sam/drivers/usart + + + + + True True True True + + + True + True + True + True + True + + + BOARD=SAM3X_EK + __SAM3X8H__ + + + + + ../src + ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek + ../src/asf/common/boards + ../src/asf/common/services/gpio + ../src/asf/common/utils + ../src/asf/sam/boards + ../src/asf/sam/boards/sam3x_ek + ../src/asf/sam/drivers/pio + ../src/asf/sam/utils + ../src/asf/sam/utils/cmsis/sam3x/include + ../src/asf/sam/utils/cmsis/sam3x/source/templates + ../src/asf/sam/utils/header_files + ../src/asf/sam/utils/preprocessor + ../src/asf/thirdparty/CMSIS/Include + ../src/config + ../src/asf/thirdparty/FreeRTOS/include + ../src/asf/thirdparty/FreeRTOS/portable/GCC/ARM_CM3 + ../src/Common-Demo-Source/include + C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles + C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\CMSIS\Include + C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL + C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL\sam3xa\include + ../src/asf/sam/drivers/pmc + ../src/asf/common/services/clock + ../src/asf/sam/drivers/usart + + + -fdata-sections + True + Maximum (-g3) + True + -pipe -Wall -Wextra -std=gnu99 -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -Dprintf=iprintf + True + -T../src/asf/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld -Wl,--cref -Wl,--entry=Reset_Handler -mthumb + -DBOARD=SAM3X_EK -D__SAM3X8H__ + + + ../src + ../src/asf/common/applications/user_application/sam3x8h_sam3x_ek + ../src/asf/common/boards + ../src/asf/common/services/gpio + ../src/asf/common/utils + ../src/asf/sam/boards + ../src/asf/sam/boards/sam3x_ek + ../src/asf/sam/drivers/pio + ../src/asf/sam/utils + ../src/asf/sam/utils/cmsis/sam3x/include + ../src/asf/sam/utils/cmsis/sam3x/source/templates + ../src/asf/sam/utils/header_files + ../src/asf/sam/utils/preprocessor + ../src/asf/thirdparty/CMSIS/Include + ../src/config + ../src/asf/sam/drivers/pmc + ../src/asf/common/services/clock + ../src/asf/sam/drivers/usart + + + + diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/RTOSDemo.cproj b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/RTOSDemo.cproj index 8f0de0298..0e475e7e3 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/RTOSDemo.cproj +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/RTOSDemo.cproj @@ -9,167 +9,167 @@ $(MSBuildProjectName) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ATSAMD20J18 samd20 diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main.c b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main.c index e8d195506..56fbe59e1 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main.c +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main.c @@ -98,7 +98,7 @@ /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/RTOSDemo.cproj b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/RTOSDemo.cproj index 922bb614c..daf4a9e43 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/RTOSDemo.cproj +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/RTOSDemo.cproj @@ -2,7 +2,7 @@ 2.0 - 6.2 + 7.0 {3d8959cd-73ca-4147-9c1b-cfcf2ee40326} $(MSBuildProjectName) $(MSBuildProjectName) @@ -10,141 +10,141 @@ 2.11.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ATSAM4S16C sam4s @@ -195,6 +195,7 @@ 0x20000000 2 + true True diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/.vs/RTOSDemo/v14/.atsuo b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/.vs/RTOSDemo/v14/.atsuo index 802b182e613bb0d4cf74bd0ef2aa153066e27fcb..777c177f03318c601454d1a52b0474900f159059 100644 GIT binary patch delta 1469 zcmd6nUuaWz6vyxH=GNS_v5i`r*y(!fT$^gDja_HrqGoB3%0!dZKdE+IJ8Sne)-W!U=B&>jgpZuA)>bbr9RZ2Ve`}1OZqd#ro=*e6MO%674{zFW?5R@R`}dJZ=<>y=WQWQ(5;d!|0=6=QY%G% zGL9M4pgP3?nk#M9)^P|8EmD*$8xSYuT-mhx`i(^=@tiK7ud%DNXUrtC=C>8!i+f*n zJx^vH&z8%fhn+zMEl(Y_>nQ2pTFp5l=XL>bwBO;VgAu*haB11D>9Xa zM#j#xt|ICB{DCM}vEQK-!CO^`^t%z^Ugf67q3dYQy-6BIcDWV0O3j=7lnYHe1UCjZ z41bn`XAfGzVcwHQLsn42?~*Rxtgs?cohOO^h{chP#PpSLc+5B;a}lSo!cl!W0z5K{ zyTZ5idN|yc94LxF3{vXjPjr59d0}5}hmQEcu^<@a~L@s2^dGT3% zFYGEr`s;?qL#ow+gYKRc<6)<@IZBgfLS&Y=Xgr3C&z0k2ZSXw*L{|Hxu`gSdX=xU8 zRrOQ@#1MQ1{Mk1i~_d^ccEO!IxC(6yQ1>zn20)74tC Q`*=HjeZ4~dc%w7%H(J2cVE_OC delta 1785 zcmcJP+fQ6o6vodwoH{dH2WEiMj?AHyOD)1sq)aI{ogo3sWd?}W*o#K{WK>#*7Njy$ zY-*xDbk3?dF_MT%Qf-WpIsbqun9!J%sh9XzwRUVti!EsvLsUE;{*5SyZ>YNc_sMT19ktRPCK zt+j$>b?d?bheB9ce8=h>xoL@s#_NZI9B4kuvwgMP)9g3;7aU3!9NWbyRk7M%$9nmD zj#Lmy-?ViqWETmfMpA}IbVQRx#$*q#dH1sJpR?ZsgJh+wuvY!Kl-Qwbth+0DL2cxS zd(c5r7?SAesP4hEr+9E1N$Ruyl+HdimsfYzS-QTGXY>VmvEIj#K71<&kYY`Lo3Ti# zrYw>E5C`2phy02JQ{v%DOZTl1|G@QD{j5Pwo>}q%Z1$`#k*~);nyK;TBd)etcH!RTEBGKa_@4=56RL8R=nm(54p|q9n@+jo#Zi{ z#Z+d-O2}iqz5PitKPjb<6&n4x)aVGLC6pRU3)ZomlHaFlJl=VT1AXmAPcU`QWgBaH zlA1g+8#fc_9dx9MTZ&x5O5< zXM7wx-dLZc0BYxm(hacDJe-m;=tyx6VTZv@C&;pH#tl+$DSYjXr1PI{9y<33-+Z~0 z6h1fInV3GN^4#JsD|SAX#VsYh+*{pZ{rrwYwXWUTO?mR*X4(`tUUso-I!=RT*zl?xT-1qV&jeh!b;m`8V#&73O0?fstnE(I) diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTE/RTE_Components.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTE/RTE_Components.h index d1d509ed5..a1663c2cb 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTE/RTE_Components.h +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTE/RTE_Components.h @@ -11,4 +11,10 @@ #define RTE_COMPONENTS_H +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "sam.h" + + #endif /* RTE_COMPONENTS_H */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewd index 7495986d0..46060692a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 26 + 28 1 1 - + + @@ -281,17 +285,13 @@ CMSISDAP_ID 2 - 2 + 4 1 1 - + + @@ -520,17 +528,13 @@ IJET_ID 2 - 5 + 8 1 1 - + + + JLINK_ID 2 - 15 + 16 1 1 - @@ -1189,7 +1154,7 @@ STLINK_ID 2 - 2 + 3 1 1 + + + + + + + + + + + + + + + + @@ -1249,10 +1279,10 @@ - XDS100_ID + TIFET_ID 2 - 2 + 1 1 1 - - - - - - - $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - 0 - - - - - Release - - ARM - - 0 - - C-SPY - 2 - - 26 - 1 - 0 - + + + + XDS100_ID + 2 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 28 + 1 + 0 + + + + + + + + + + - + + @@ -1644,17 +1863,13 @@ CMSISDAP_ID 2 - 2 + 4 1 0 - + + @@ -1883,17 +2106,13 @@ IJET_ID 2 - 5 + 8 1 0 - + + + @@ -2101,7 +2332,7 @@ JLINK_ID 2 - 15 + 16 1 0 - - XDS100_ID + TIFET_ID 2 - 2 + 1 1 0 + + + + + + + + + + + + + + + XDS100_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2658,6 +3088,10 @@ $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin 0 + + $TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin 0 @@ -2718,10 +3152,6 @@ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin 0 - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin 0 diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewp index 3e2aa4647..93c6f0236 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewp @@ -12,7 +12,7 @@ General 3 - 22 + 24 1 1 - - - + + + + + + @@ -595,8 +608,8 @@ 1 @@ -965,7 +982,7 @@ General 3 - 22 + 24 1 0 - - - + + + + + + @@ -1537,7 +1567,7 @@ 0 diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewt b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewt index cf404a77f..2779981fd 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewt +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewt @@ -8,6 +8,1078 @@ ARM 1 + + C-STAT + 259 + + 259 + + 0 + + 1 + 600 + 0 + 2 + 0 + 1 + 100 + + + 1.3.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RuntimeChecking 0 @@ -92,6 +1164,1078 @@ ARM 0 + + C-STAT + 259 + + 259 + + 0 + + 1 + 600 + 0 + 2 + 0 + 1 + 100 + + + 1.3.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RuntimeChecking 0 diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx index ce0173f72..16325826b 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx @@ -78,6 +78,43 @@ 1 16 + + + 0 + User Manual (SAMV71-XULTRA) + C:\devtools\Keil_v520\ARM\PACK\Keil\SAM-ESV7_SFP\2.3.1\Boards\Atmel\SAMV71-XULTRA\Documents\Atmel-42408-SAMV71-Xplained-Ultra_User-Guide.pdf + + + 1 + Blinky Lab (SAMV71-XULTRA) + C:\devtools\Keil_v520\ARM\PACK\Keil\SAM-ESV7_SFP\2.3.1\Boards\Atmel\SAMV71-XULTRA\Documents\Atmel_Blinky_Lab.pdf + + + 2 + Bill of Materials (SAMV71-XULTRA) + C:\devtools\Keil_v520\ARM\PACK\Keil\SAM-ESV7_SFP\2.3.1\Boards\Atmel\SAMV71-XULTRA\Documents\Bill of Materials Fitted- SAM V71 Xplained Ultra_release_rev3.zip + + + 3 + Gerber Files (SAMV71-XULTRA) + C:\devtools\Keil_v520\ARM\PACK\Keil\SAM-ESV7_SFP\2.3.1\Boards\Atmel\SAMV71-XULTRA\Documents\Gerber.zip + + + 4 + Quick Start Guide (SAMV71-XULTRA) + C:\devtools\Keil_v520\ARM\PACK\Keil\SAM-ESV7_SFP\2.3.1\Boards\Atmel\SAMV71-XULTRA\Documents\SAMV71_XUltra_QSG.pdf + + + 5 + Schematics (SAMV71-XULTRA) + C:\devtools\Keil_v520\ARM\PACK\Keil\SAM-ESV7_SFP\2.3.1\Boards\Atmel\SAMV71-XULTRA\Documents\SAM_V71_Xplained_Ultra_design_documentation_release_rev8.pdf + + + 6 + SAMV71 Xplained Ultra Web Page (SAMV71-XULTRA) + http://www.atmel.com/tools/ATSAMV71-XULT.aspx + + 0 1 @@ -100,7 +137,7 @@ 1 0 0 - 6 + 0 @@ -111,7 +148,7 @@ .\libboard_samv7-ek\resources\mdk\samv7-sram.ini - Segger\JL2CM3.dll + BIN\UL2CM3.DLL @@ -139,10 +176,6 @@ ARMDBGFLAGS -T0 - - 0 - DLGUARM - 0 CMSIS_AGDI @@ -151,7 +184,7 @@ 0 UL2CM3 - -S0 -C0 -P0 -FD20400000 -FC1000) + -S0 -C0 -P0 -FN1 -FC1000 -FD20400000 -FF0ATSAMV7x_2048 -FL0200000 -FS0400000 -FP0($$Device:ATSAMV71Q21$flash\ATSAMV7x_2048.FLM) @@ -193,6 +226,16 @@ + 0 + + + 0 + + 1 + 0 + 2 + 10000000 + @@ -207,7 +250,6 @@ 1 1 0 - 0 0 0 .\libboard_samv7-ek\source\board_lowlevel.c @@ -220,7 +262,6 @@ 2 1 0 - 0 0 0 .\libboard_samv7-ek\source\led.c @@ -233,7 +274,6 @@ 3 1 0 - 0 0 0 .\libboard_samv7-ek\resources\mdk\startup_sam.c @@ -246,7 +286,6 @@ 4 1 0 - 0 0 0 .\libboard_samv7-ek\source\dbg_console.c @@ -259,7 +298,6 @@ 5 2 0 - 0 0 0 .\libboard_samv7-ek\resources\mdk\workaround.s @@ -272,7 +310,6 @@ 6 1 0 - 0 0 0 .\libboard_samv7-ek\resources\system_sam.c @@ -284,7 +321,7 @@ Source - 1 + 0 0 0 0 @@ -293,7 +330,6 @@ 7 1 0 - 0 0 0 .\main.c @@ -306,7 +342,6 @@ 8 5 0 - 0 0 0 .\FreeRTOSConfig.h @@ -319,7 +354,6 @@ 9 1 0 - 0 0 0 .\Full_Demo\main_full.c @@ -332,7 +366,6 @@ 10 1 0 - 0 0 0 .\Blinky_Demo\main_blinky.c @@ -345,7 +378,6 @@ 11 1 0 - 0 0 0 .\Full_Demo\RegTest.c @@ -358,7 +390,6 @@ 12 1 0 - 0 0 0 .\Full_Demo\IntQueueTimer.c @@ -379,7 +410,6 @@ 13 1 0 - 0 0 0 .\libchip_samv7\source\pio.c @@ -392,7 +422,6 @@ 14 1 0 - 0 0 0 .\libchip_samv7\source\pmc.c @@ -405,7 +434,6 @@ 15 1 0 - 0 0 0 .\libchip_samv7\source\tc.c @@ -418,7 +446,6 @@ 16 1 0 - 0 0 0 .\libchip_samv7\source\wdt.c @@ -431,7 +458,6 @@ 17 1 0 - 0 0 0 .\libchip_samv7\source\supc.c @@ -444,7 +470,6 @@ 18 1 0 - 0 0 0 .\libchip_samv7\source\pio_capture.c @@ -465,7 +490,6 @@ 19 1 0 - 0 0 0 ..\..\Source\event_groups.c @@ -478,7 +502,6 @@ 20 1 0 - 0 0 0 ..\..\Source\list.c @@ -491,7 +514,6 @@ 21 1 0 - 0 0 0 ..\..\Source\queue.c @@ -504,7 +526,6 @@ 22 1 0 - 0 0 0 ..\..\Source\tasks.c @@ -517,7 +538,6 @@ 23 1 0 - 0 0 0 ..\..\Source\timers.c @@ -530,7 +550,6 @@ 24 1 0 - 0 0 0 ..\..\Source\portable\MemMang\heap_4.c @@ -543,7 +562,6 @@ 25 1 0 - 0 0 0 ..\..\Source\portable\RVDS\ARM_CM7\r0p1\port.c @@ -564,7 +582,6 @@ 26 1 0 - 0 0 0 ..\Common\Minimal\BlockQ.c @@ -577,7 +594,6 @@ 27 1 0 - 0 0 0 ..\Common\Minimal\blocktim.c @@ -590,7 +606,6 @@ 28 1 0 - 0 0 0 ..\Common\Minimal\countsem.c @@ -603,7 +618,6 @@ 29 1 0 - 0 0 0 ..\Common\Minimal\death.c @@ -616,7 +630,6 @@ 30 1 0 - 0 0 0 ..\Common\Minimal\dynamic.c @@ -629,7 +642,6 @@ 31 1 0 - 0 0 0 ..\Common\Minimal\EventGroupsDemo.c @@ -642,7 +654,6 @@ 32 1 0 - 0 0 0 ..\Common\Minimal\flop.c @@ -655,7 +666,6 @@ 33 1 0 - 0 0 0 ..\Common\Minimal\GenQTest.c @@ -668,7 +678,6 @@ 34 1 0 - 0 0 0 ..\Common\Minimal\QueueOverwrite.c @@ -681,7 +690,6 @@ 35 1 0 - 0 0 0 ..\Common\Minimal\QueueSet.c @@ -694,7 +702,6 @@ 36 1 0 - 0 0 0 ..\Common\Minimal\recmutex.c @@ -707,7 +714,6 @@ 37 1 0 - 0 0 0 ..\Common\Minimal\semtest.c @@ -720,7 +726,6 @@ 38 1 0 - 0 0 0 ..\Common\Minimal\TaskNotify.c @@ -733,7 +738,6 @@ 39 1 0 - 0 0 0 ..\Common\Minimal\TimerDemo.c @@ -746,7 +750,6 @@ 40 1 0 - 0 0 0 ..\Common\Minimal\IntQueue.c @@ -759,7 +762,6 @@ 41 1 0 - 0 0 0 ..\Common\Minimal\IntSemTest.c diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx index 25ddcf2e1..d06a3b2a5 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx @@ -10,17 +10,19 @@ SRAM 0x4 ARM-ADS + 5060183::V5.06 update 2 (build 183)::ARMCC - SAMV71Q21 + ATSAMV71Q21 Atmel - Atmel.SAMV7.1.0.0 - IROM(0x00000000,0x200000) IRAM(0x20400000,0x60000) CPUTYPE("Cortex-M7") FPU2 CLOCK(12000000) ELITTLE + Keil.SAM-V_DFP.2.3.0 + http://www.keil.com/pack/ + IRAM(0x20400000,0x00060000) IROM(0x00400000,0x00200000) IROM2(0x00800000,0x00004000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20400000 -FC1000) + UL2CM3(-S0 -C0 -P0 -FD20400000 -FC1000 -FN1 -FF0ATSAMV7x_2048 -FS0400000 -FL0200000 -FP0($$Device:ATSAMV71Q21$flash\ATSAMV7x_2048.FLM)) 0 - + $$Device:ATSAMV71Q21$SAMV71\include\sam.h @@ -30,7 +32,7 @@ - + $$Device:ATSAMV71Q21$svd\ATSAMV71Q21.svd 0 0 @@ -83,6 +85,8 @@ 0 0 + 0 + 0 0 @@ -105,11 +109,11 @@ SARMCM3.DLL - + -REMAP -MPU DCM.DLL -pCM7 SARMCM3.DLL - + -MPU TCM.DLL -pCM7 @@ -121,47 +125,6 @@ 0 16 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 6 - - - - - - - - - - - - - .\libboard_samv7-ek\resources\mdk\samv7-sram.ini - Segger\JL2CM3.dll - @@ -174,7 +137,7 @@ 1 BIN\UL2CM3.DLL - "" () + Source @@ -219,13 +182,14 @@ 1 0 0 - 2 + 3 0 - 0 + 1 8 1 0 0 + 0 3 3 0 @@ -283,7 +247,7 @@ 1 - 0x0 + 0x400000 0x200000 @@ -308,13 +272,13 @@ 1 - 0x0 + 0x400000 0x200000 1 - 0x0 - 0x0 + 0x800000 + 0x4000 0 @@ -334,7 +298,7 @@ 0 0x20400000 - 0x40000 + 0x60000 0 @@ -360,6 +324,12 @@ 0 1 0 + 1 + 1 + 1 + 1 + 0 + 0 __SAMV71Q21__, NDEBUG @@ -644,8 +614,8 @@ - - + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat index 031884d9e..c41e3c071 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat @@ -21,11 +21,11 @@ @echo off -if not "%1" == "" goto debugFile +if not "%~1" == "" goto debugFile @echo on -"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" +"C:\DevTools\IAR Systems\Embedded Workbench 7.4\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" @echo off goto end @@ -34,7 +34,7 @@ goto end @echo on -"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" +"C:\DevTools\IAR Systems\Embedded Workbench 7.4\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" @echo off :end \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.dni index 5a44c98b0..193f3ae47 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.dni +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.dni @@ -35,6 +35,7 @@ MultiCoreRunAll=0 EnableCache=1 [JLinkDriver] CStepIntDis=_ 0 +LeaveTargetRunning=_ 0 [SWOTraceHWSettings] OverrideDefaultClocks=0 CpuClock=72000000 diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt index 3646f8897..9e8aa4390 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt @@ -12,7 +12,7 @@ - 198272727 + 237272727 @@ -28,7 +28,7 @@ - + TabID-23288-9694 @@ -40,7 +40,7 @@ - 0 + 0 TabID-13649-20313 @@ -56,7 +56,7 @@ TabID-30315-19856Find in FilesFind-in-Files - 0 + 0 @@ -69,7 +69,7 @@ - iaridepm.enu1-2-2770272-2-2200174119048176829163095784553-2-21701682-2-216841721002381174797119048176829 + iaridepm.enu1-2-2894311-2-2229201119271177249163021790123-2-21961922-2-219241981002083174603119271177249 diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewd index b41c36ab4..3caaacbe6 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 26 + 28 1 1 - + + @@ -281,17 +285,13 @@ CMSISDAP_ID 2 - 2 + 4 1 1 - + + @@ -520,17 +528,13 @@ IJET_ID 2 - 5 + 8 1 1 - + + + JLINK_ID 2 - 15 + 16 1 1 - @@ -1189,7 +1154,7 @@ STLINK_ID 2 - 2 + 3 1 1 + + + + + + + + + + + + + + + + @@ -1249,10 +1279,10 @@ - XDS100_ID + TIFET_ID 2 - 2 + 1 1 1 - - - - - - - $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - 0 - - - - - Release - - ARM - - 0 - - C-SPY - 2 - - 26 - 1 - 0 - - + + + XDS100_ID + 2 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 28 + 1 + 0 + + + + + + + + + + + @@ -1454,10 +1669,6 @@ OCLastSavedByProductVersion - + + @@ -1644,17 +1863,13 @@ CMSISDAP_ID 2 - 2 + 4 1 0 - + + @@ -1883,17 +2106,13 @@ IJET_ID 2 - 5 + 8 1 0 - + + + @@ -2101,7 +2332,7 @@ JLINK_ID 2 - 15 + 16 1 0 - - XDS100_ID + TIFET_ID 2 - 2 + 1 1 0 + + + + + + + + + + + + + + + XDS100_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2658,6 +3088,10 @@ $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin 0 + + $TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin 0 @@ -2718,10 +3152,6 @@ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin 0 - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin 0 diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewp index 49159e030..13d94943b 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewp @@ -12,7 +12,7 @@ General 3 - 22 + 24 1 1 - - - + + + + + + @@ -594,8 +607,8 @@ 1 @@ -964,7 +981,7 @@ General 3 - 22 + 24 1 0 - - - + + + + + + @@ -1536,7 +1566,7 @@ 0 diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvproj b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvprojx similarity index 86% rename from FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvproj rename to FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvprojx index ac704bd38..ab7219037 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvproj +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvprojx @@ -1,7 +1,7 @@ - + - 1.1 + 2.1
### uVision Project, (C) Keil Software
@@ -10,16 +10,19 @@ STM32756G_EVAL 0x4 ARM-ADS + 5060183::V5.06 update 2 (build 183)::ARMCC - STM32F7x + STM32F756NGHx STMicroelectronics - IROM(0x08000000,0x100000) IRAM(0x20000000,0x10000) CLOCK(12000000) CPUTYPE("Pelican") ESEL ELITTLE FPU3(SFPU) + Keil.STM32F7xx_DFP.2.5.0 + http://www.keil.com/pack + IRAM(0x20010000,0x40000) IRAM2(0x20000000,0x10000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE - UL2CM3(-O207 -S8 -C0 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F7x -FS08000000 -FL100000) + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F756NGHx$CMSIS\Flash\STM32F7x_1024.FLM)) 0 - + $$Device:STM32F756NGHx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h @@ -29,14 +32,14 @@ - + $$Device:STM32F756NGHx$CMSIS\SVD\STM32F7x.svd 0 0 - ST\STM32F4xx\ - ST\STM32F4xx\ + + 0 0 @@ -82,6 +85,8 @@ 0 0 + 0 + 0 0 @@ -104,13 +109,13 @@ SARMCM3.DLL - - DARMCM1.DLL - -pCM4 + -REMAP -MPU + DCM.DLL + -pCM7 SARMCM3.DLL - - TARMCM1.DLL - -pCM4 + -MPU + TCM.DLL + -pCM7 @@ -120,47 +125,6 @@ 0 16 - - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - - 0 - 11 - - - - - - - - - - - - - - STLink\ST-LINKIII-KEIL_SWO.dll - @@ -173,7 +137,7 @@ 1 BIN\UL2CM3.DLL - "" () + @@ -209,7 +173,7 @@ 1 0 0 - "Pelican" + "Cortex-M7" 0 0 @@ -219,12 +183,13 @@ 0 0 2 - 0 - 0 + 1 + 1 8 1 - 1 + 0 0 + 0 3 3 0 @@ -277,8 +242,8 @@ 0 - 0x20000000 - 0x10000 + 0x20010000 + 0x40000 1 @@ -312,8 +277,8 @@ 1 - 0x0 - 0x0 + 0x200000 + 0x100000 0 @@ -332,13 +297,13 @@ 0 - 0x20000000 - 0xffff + 0x20010000 + 0x40000 0 - 0x0 - 0x0 + 0x20000000 + 0x10000 @@ -359,6 +324,12 @@ 0 0 0 + 1 + 1 + 1 + 1 + 0 + 0 STM32F756xx, CORE_CM7,USE_HAL_DRIVER @@ -643,8 +614,24 @@ + + ::CMSIS + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat index 4503386b2..6a01213e0 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat @@ -21,11 +21,11 @@ @echo off -if not "%1" == "" goto debugFile +if not "%~1" == "" goto debugFile @echo on -"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" +"C:\DevTools\IAR Systems\Embedded Workbench 7.4\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" @echo off goto end @@ -34,7 +34,7 @@ goto end @echo on -"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" +"C:\DevTools\IAR Systems\Embedded Workbench 7.4\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" @echo off :end \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.dni index cf2595eb3..fc17c8eb2 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.dni +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.dni @@ -58,6 +58,7 @@ CStepIntDis=_ 0 WatchCond=_ 0 Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +LeaveTargetRunning=_ 0 [Trace2] Enabled=0 ShowSource=0 diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.wsdt index c57c9bf00..5de027cf3 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.wsdt +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.wsdt @@ -12,7 +12,7 @@ - 303272727 + 357272727 @@ -29,7 +29,7 @@ - + TabID-18739-8840 @@ -41,7 +41,7 @@ - 0 + 0 TabID-19869-16187 @@ -57,7 +57,7 @@ - 0 + 0 @@ -70,7 +70,7 @@ - iaridepm.enu1-2-2619377-2-2200200119048203252225595631098-2-23211682-2-216843231002381328252119048203252 + iaridepm.enu1-2-2720431-2-2229230119271202822225521636684-2-23701922-2-219243721002083328042119271202822 diff --git a/FreeRTOS/Demo/Common/Minimal/blocktim.c b/FreeRTOS/Demo/Common/Minimal/blocktim.c index f06fe2454..883a1c5a8 100644 --- a/FreeRTOS/Demo/Common/Minimal/blocktim.c +++ b/FreeRTOS/Demo/Common/Minimal/blocktim.c @@ -99,6 +99,12 @@ #define bktDONT_BLOCK ( ( TickType_t ) 0 ) #define bktRUN_INDICATOR ( ( UBaseType_t ) 0x55 ) +/* In case the demo does not have software timers enabled, as this file uses +the configTIMER_TASK_PRIORITY setting. */ +#ifndef configTIMER_TASK_PRIORITY + #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#endif + /*-----------------------------------------------------------*/ /* diff --git a/FreeRTOS/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/.settings/org.eclipse.core.resources.prefs b/FreeRTOS/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/.settings/org.eclipse.core.resources.prefs index a9e5b95c6..efd217d75 100644 --- a/FreeRTOS/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/.settings/org.eclipse.core.resources.prefs +++ b/FreeRTOS/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/.settings/org.eclipse.core.resources.prefs @@ -45,26 +45,3 @@ encoding//Large_Data/objects.mk=UTF-8 encoding//Large_Data/sources.mk=UTF-8 encoding//Large_Data/subdir_rules.mk=UTF-8 encoding//Large_Data/subdir_vars.mk=UTF-8 -encoding//Small_Data/Blinky_Demo/subdir_rules.mk=UTF-8 -encoding//Small_Data/Blinky_Demo/subdir_vars.mk=UTF-8 -encoding//Small_Data/CCS_Only/subdir_rules.mk=UTF-8 -encoding//Small_Data/CCS_Only/subdir_vars.mk=UTF-8 -encoding//Small_Data/FreeRTOS_Source/portable/CCS/MSP430X/subdir_rules.mk=UTF-8 -encoding//Small_Data/FreeRTOS_Source/portable/CCS/MSP430X/subdir_vars.mk=UTF-8 -encoding//Small_Data/FreeRTOS_Source/portable/MemMang/subdir_rules.mk=UTF-8 -encoding//Small_Data/FreeRTOS_Source/portable/MemMang/subdir_vars.mk=UTF-8 -encoding//Small_Data/FreeRTOS_Source/subdir_rules.mk=UTF-8 -encoding//Small_Data/FreeRTOS_Source/subdir_vars.mk=UTF-8 -encoding//Small_Data/Full_Demo/FreeRTOS+CLI/subdir_rules.mk=UTF-8 -encoding//Small_Data/Full_Demo/FreeRTOS+CLI/subdir_vars.mk=UTF-8 -encoding//Small_Data/Full_Demo/Standard_Demo_Tasks/subdir_rules.mk=UTF-8 -encoding//Small_Data/Full_Demo/Standard_Demo_Tasks/subdir_vars.mk=UTF-8 -encoding//Small_Data/Full_Demo/subdir_rules.mk=UTF-8 -encoding//Small_Data/Full_Demo/subdir_vars.mk=UTF-8 -encoding//Small_Data/driverlib/MSP430FR5xx_6xx/subdir_rules.mk=UTF-8 -encoding//Small_Data/driverlib/MSP430FR5xx_6xx/subdir_vars.mk=UTF-8 -encoding//Small_Data/makefile=UTF-8 -encoding//Small_Data/objects.mk=UTF-8 -encoding//Small_Data/sources.mk=UTF-8 -encoding//Small_Data/subdir_rules.mk=UTF-8 -encoding//Small_Data/subdir_vars.mk=UTF-8 diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h deleted file mode 100644 index 6ef0bed68..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 250 ) -#define configCPU_CLOCK_HZ ( ( unsigned long ) 200000000 ) /* Clock setup from start.asm in the demo application. */ -#define configTICK_RATE_HZ ( (TickType_t) 1000 ) -#define configMAX_PRIORITIES ( 6 ) -#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) ) -#define configMAX_TASK_NAME_LEN ( 20 ) -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configUSE_TRACE_FACILITY 0 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_APPLICATION_TASK_TAG 1 -#define configUSE_FPU 1 - - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 4 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vResumeFromISR 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define configUSE_RECURSIVE_MUTEXES 1 - - -#if configUSE_FPU == 1 - /* Include the header that define the traceTASK_SWITCHED_IN() and - traceTASK_SWITCHED_OUT() macros to save and restore the floating - point registers for tasks that have requested this behaviour. */ - #include "FPU_Macros.h" -#endif - -#endif /* FREERTOS_CONFIG_H */ - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld deleted file mode 100644 index 0a5bdac6a..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld +++ /dev/null @@ -1,209 +0,0 @@ -/*******************************************************************/ -/* */ -/* This file is automatically generated by linker script generator.*/ -/* */ -/* Version: Xilinx EDK 10.1.01 EDK_K_SP1.3 */ -/* */ -/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */ -/* */ -/* Description : PowerPC405 Linker Script */ -/* */ -/*******************************************************************/ - -_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400; -_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x100; - -/* Define Memories in the system */ - -MEMORY -{ - SRAM_C_MEM0_BASEADDR : ORIGIN = 0xFFF00000, LENGTH = 0x000FFFEC -} - -/* Specify the default entry point to the program */ - -ENTRY(_boot) -STARTUP(boot.o) - -/* Define the sections, and where they are mapped in memory */ - -SECTIONS -{ -.vectors : { - __vectors_start = .; - *(.vectors) - __vectors_end = .; -} > SRAM_C_MEM0_BASEADDR - -.text : { - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) -} > SRAM_C_MEM0_BASEADDR - -.init : { - KEEP (*(.init)) -} > SRAM_C_MEM0_BASEADDR - -.fini : { - KEEP (*(.fini)) -} > SRAM_C_MEM0_BASEADDR - -.rodata : { - __rodata_start = .; - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - __rodata_end = .; -} > SRAM_C_MEM0_BASEADDR - -.sdata2 : { - __sdata2_start = .; - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - __sdata2_end = .; -} > SRAM_C_MEM0_BASEADDR - -.sbss2 : { - __sbss2_start = .; - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - __sbss2_end = .; -} > SRAM_C_MEM0_BASEADDR - -.data : { - __data_start = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - __data_end = .; -} > SRAM_C_MEM0_BASEADDR - -.got : { - *(.got) -} > SRAM_C_MEM0_BASEADDR - -.got1 : { - *(.got1) -} > SRAM_C_MEM0_BASEADDR - -.got2 : { - *(.got2) -} > SRAM_C_MEM0_BASEADDR - -.ctors : { - __CTOR_LIST__ = .; - ___CTORS_LIST___ = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - ___CTORS_END___ = .; -} > SRAM_C_MEM0_BASEADDR - -.dtors : { - __DTOR_LIST__ = .; - ___DTORS_LIST___ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - ___DTORS_END___ = .; -} > SRAM_C_MEM0_BASEADDR - -.fixup : { - __fixup_start = .; - *(.fixup) - __fixup_end = .; -} > SRAM_C_MEM0_BASEADDR - -.eh_frame : { - *(.eh_frame) -} > SRAM_C_MEM0_BASEADDR - -.jcr : { - *(.jcr) -} > SRAM_C_MEM0_BASEADDR - -.gcc_except_table : { - *(.gcc_except_table) -} > SRAM_C_MEM0_BASEADDR - -.sdata : { - __sdata_start = .; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - __sdata_end = .; -} > SRAM_C_MEM0_BASEADDR - -.sbss : { - __sbss_start = .; - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - __sbss_end = .; -} > SRAM_C_MEM0_BASEADDR - -.tdata : { - __tdata_start = .; - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - __tdata_end = .; -} > SRAM_C_MEM0_BASEADDR - -.tbss : { - __tbss_start = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - __tbss_end = .; -} > SRAM_C_MEM0_BASEADDR - -.bss : { - __bss_start = .; - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - __bss_end = .; -} > SRAM_C_MEM0_BASEADDR - -.boot0 0xFFFFFFEC : { - __boot0_start = .; - *(.boot0) - __boot0_end = .; -} - -.boot 0xFFFFFFFC : { - __boot_start = .; - *(.boot) - __boot_end = .; -} - -/* Generate Stack and Heap Sections */ - -.stack : { - _stack_end = .; - . += _STACK_SIZE; - . = ALIGN(16); - __stack = .; -} > SRAM_C_MEM0_BASEADDR - -.heap : { - . = ALIGN(16); - _heap_start = .; - . += _HEAP_SIZE; - . = ALIGN(16); - _heap_end = .; - _end = .; -} > SRAM_C_MEM0_BASEADDR - -} - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.c b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.c deleted file mode 100644 index 1d2d19d32..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * Tests the floating point context save and restore mechanism. - * - * Two tasks are created - each of which is allocated a buffer of - * portNO_FLOP_REGISTERS_TO_SAVE 32bit variables into which the flop context - * of the task is saved when the task is switched out, and from which the - * flop context of the task is restored when the task is switch in. Prior to - * the tasks being created each position in the two buffers is filled with a - * unique value - this way the flop context of each task is different. - * - * The two test tasks never block so are always in either the Running or - * Ready state. They execute at the lowest priority so will get pre-empted - * regularly, although the yield frequently so will not get much execution - * time. The lack of execution time is not a problem as its only the - * switching in and out that is being tested. - * - * Whenever a task is moved from the Ready to the Running state its flop - * context will be loaded from the buffer, but while the task is in the - * Running state the buffer is not used and can contain any value - in this - * case and for test purposes the task itself clears the buffer to zero. - * The next time the task is moved out of the Running state into the - * Ready state the flop context will once more get saved to the buffer - - * overwriting the zeros. - * - * Therefore whenever the task is not in the Running state its buffer contains - * the most recent values of its floating point registers - the zeroing out - * of the buffer while the task was executing being used to ensure the values - * the buffer contains are not stale. - * - * When neither test task is in the Running state the buffers should contain - * the unique values allocated before the tasks were created. If so then - * the floating point context has been maintained. This check is performed - * by the 'check' task (defined in main.c) by calling - * xAreFlopRegisterTestsStillRunning(). - * - * The test tasks also increment a value each time they execute. - * xAreFlopRegisterTestsStillRunning() also checks that this value has changed - * since it last ran to ensure the test tasks are still getting processing time. - */ - -/* Standard includes files. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/*-----------------------------------------------------------*/ - -#define flopNUMBER_OF_TASKS 2 -#define flopSTART_VALUE ( 0x1 ) - -/*-----------------------------------------------------------*/ - -/* The two test tasks as described at the top of this file. */ -static void vFlopTest1( void *pvParameters ); -static void vFlopTest2( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* Buffers into which the flop registers will be saved. There is a buffer for -both tasks. */ -static volatile unsigned long ulFlopRegisters[ flopNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ]; - -/* Variables that are incremented by the tasks to indicate that they are still -running. */ -static volatile unsigned long ulFlop1CycleCount = 0, ulFlop2CycleCount = 0; - -/*-----------------------------------------------------------*/ - -void vStartFlopRegTests( void ) -{ -TaskHandle_t xTaskJustCreated; -unsigned portBASE_TYPE x, y, z = flopSTART_VALUE; - - /* Fill the arrays into which the flop registers are to be saved with - known values. These are the values that will be written to the flop - registers when the tasks start, and as the tasks do not perform any - flop operations the values should never change. Each position in the - buffer contains a different value so the flop context of each task - will be different. */ - for( x = 0; x < flopNUMBER_OF_TASKS; x++ ) - { - for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1); y++ ) - { - ulFlopRegisters[ x ][ y ] = z; - z++; - } - } - - - /* Create the first task. */ - xTaskCreate( vFlopTest1, "flop1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated ); - - /* The task tag value is a value that can be associated with a task, but - is not used by the scheduler itself. Its use is down to the application so - it makes a convenient place in this case to store the pointer to the buffer - into which the flop context of the task will be stored. The first created - task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ]. */ - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) ); - - /* Do the same for the second task. */ - xTaskCreate( vFlopTest2, "flop2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) ); -} -/*-----------------------------------------------------------*/ - -static void vFlopTest1( void *pvParameters ) -{ - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - for( ;; ) - { - /* The values from the buffer should have now been written to the flop - registers. Clear the buffer to ensure the same values then get written - back the next time the task runs. Being preempted during this memset - could cause the test to fail, hence the critical section. */ - portENTER_CRITICAL(); - memset( ( void * ) ulFlopRegisters[ 0 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) ); - portEXIT_CRITICAL(); - - /* We don't have to do anything other than indicate that we are - still running. */ - ulFlop1CycleCount++; - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -static void vFlopTest2( void *pvParameters ) -{ - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - for( ;; ) - { - /* The values from the buffer should have now been written to the flop - registers. Clear the buffer to ensure the same values then get written - back the next time the task runs. */ - portENTER_CRITICAL(); - memset( ( void * ) ulFlopRegisters[ 1 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) ); - portEXIT_CRITICAL(); - - /* We don't have to do anything other than indicate that we are - still running. */ - ulFlop2CycleCount++; - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xAreFlopRegisterTestsStillRunning( void ) -{ -portBASE_TYPE xReturn = pdPASS; -unsigned portBASE_TYPE x, y, z = flopSTART_VALUE; -static unsigned long ulLastFlop1CycleCount = 0, ulLastFlop2CycleCount = 0; - - /* Called from the 'check' task. - - The flop tasks cannot be currently running, check their saved registers - are as expected. The tests tasks do not perform any flop operations so - their registers should be as per their initial setting. */ - for( x = 0; x < flopNUMBER_OF_TASKS; x++ ) - { - for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ ) - { - if( ulFlopRegisters[ x ][ y ] != z ) - { - xReturn = pdFAIL; - break; - } - - z++; - } - } - - /* Check both tasks have actually been swapped in and out since this function - last executed. */ - if( ulFlop1CycleCount == ulLastFlop1CycleCount ) - { - xReturn = pdFAIL; - } - - if( ulFlop2CycleCount == ulLastFlop2CycleCount ) - { - xReturn = pdFAIL; - } - - ulLastFlop1CycleCount = ulFlop1CycleCount; - ulLastFlop2CycleCount = ulFlop2CycleCount; - - return xReturn; -} - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.h b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.h deleted file mode 100644 index ee587f0c5..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#ifndef FLOP_REG_TEST_H -#define FLOP_REG_TEST_H - -void vStartFlopRegTests( void ); -portBASE_TYPE xAreFlopRegisterTestsStillRunning( void ); - -#endif diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop.c b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop.c deleted file mode 100644 index 32b4485e5..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop.c +++ /dev/null @@ -1,420 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * Creates eight tasks, each of which loops continuously performing a - * floating point calculation. - * - * All the tasks run at the idle priority and never block or yield. This causes - * all eight tasks to time slice with the idle task. Running at the idle priority - * means that these tasks will get pre-empted any time another task is ready to run - * or a time slice occurs. More often than not the pre-emption will occur mid - * calculation, creating a good test of the schedulers context switch mechanism - a - * calculation producing an unexpected result could be a symptom of a corruption in - * the context of a task. - * - * This file demonstrates the use of the task tag and traceTASK_SWITCHED_IN and - * traceTASK_SWITCHED_OUT macros to save and restore the floating point context. - */ - -#include -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "flop.h" - -/* Misc. definitions. */ -#define mathSTACK_SIZE configMINIMAL_STACK_SIZE -#define mathNUMBER_OF_TASKS ( 8 ) - -/* Four tasks, each of which performs a different floating point calculation. -Each of the four is created twice. */ -static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); -static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); -static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); -static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); - -/* These variables are used to check that all the tasks are still running. If a -task gets a calculation wrong it will stop incrementing its check variable. */ -static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; - -/* Buffers into which the flop registers will be saved. There is a buffer for -each task created within this file. Zeroing out this array is the normal and -safe option as this will cause the task to start with all zeros in its flop -context. */ -static unsigned long ulFlopRegisters[ mathNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ]; - -/*-----------------------------------------------------------*/ - -void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) -{ -TaskHandle_t xTaskJustCreated; -portBASE_TYPE x, y; - - /* Place known values into the buffers into which the flop registers are - to be saved. This is for debug purposes only, it is not normally - required. The last position in each array is left at zero as the status - register will be loaded from there. - - It is intended that these values can be viewed being loaded into the - flop registers when a task is started - however the Insight debugger - does not seem to want to show the flop register values. */ - for( x = 0; x < mathNUMBER_OF_TASKS; x++ ) - { - for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ ) - { - ulFlopRegisters[ x ][ y ] = ( x + 1 ); - } - } - - /* Create the first task - passing it the address of the check variable - that it is going to increment. This check variable is used as an - indication that the task is still running. */ - xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, &xTaskJustCreated ); - - /* The task tag value is a value that can be associated with a task, but - is not used by the scheduler itself. Its use is down to the application so - it makes a convenient place in this case to store the pointer to the buffer - into which the flop context of the task will be stored. The first created - task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ], etc. */ - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) ); - - /* Create another 7 tasks, allocating a buffer for each. */ - xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 2 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 3 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 4 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 5 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 6 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 7 ][ 0 ] ) ); -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) -{ -volatile portFLOAT ff1, ff2, ff3, ff4; -volatile unsigned short *pusTaskCheckVariable; -volatile portFLOAT fAnswer; -short sError = pdFALSE; - - ff1 = 123.4567F; - ff2 = 2345.6789F; - ff3 = -918.222F; - - fAnswer = ( ff1 + ff2 ) * ff3; - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned short * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for(;;) - { - ff1 = 123.4567F; - ff2 = 2345.6789F; - ff3 = -918.222F; - - ff4 = ( ff1 + ff2 ) * ff3; - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( fabs( ff4 - fAnswer ) > 0.001F ) - { - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) -{ -volatile portFLOAT ff1, ff2, ff3, ff4; -volatile unsigned short *pusTaskCheckVariable; -volatile portFLOAT fAnswer; -short sError = pdFALSE; - - ff1 = -389.38F; - ff2 = 32498.2F; - ff3 = -2.0001F; - - fAnswer = ( ff1 / ff2 ) * ff3; - - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned short * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for( ;; ) - { - ff1 = -389.38F; - ff2 = 32498.2F; - ff3 = -2.0001F; - - ff4 = ( ff1 / ff2 ) * ff3; - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( fabs( ff4 - fAnswer ) > 0.001F ) - { - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know - this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) -{ -volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference; -volatile unsigned short *pusTaskCheckVariable; -const size_t xArraySize = 10; -size_t xPosition; -short sError = pdFALSE; - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned short * ) pvParameters; - - pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) ); - - /* Keep filling an array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - fTotal1 = 0.0F; - fTotal2 = 0.0F; - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - pfArray[ xPosition ] = ( portFLOAT ) xPosition + 5.5F; - fTotal1 += ( portFLOAT ) xPosition + 5.5F; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - fTotal2 += pfArray[ xPosition ]; - } - - fDifference = fTotal1 - fTotal2; - if( fabs( fDifference ) > 0.001F ) - { - sError = pdTRUE; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) -{ -volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference; -volatile unsigned short *pusTaskCheckVariable; -const size_t xArraySize = 10; -size_t xPosition; -short sError = pdFALSE; - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned short * ) pvParameters; - - pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) ); - - /* Keep filling an array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - fTotal1 = 0.0F; - fTotal2 = 0.0F; - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - pfArray[ xPosition ] = ( portFLOAT ) xPosition * 12.123F; - fTotal1 += ( portFLOAT ) xPosition * 12.123F; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - fTotal2 += pfArray[ xPosition ]; - } - - fDifference = fTotal1 - fTotal2; - if( fabs( fDifference ) > 0.001F ) - { - sError = pdTRUE; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreMathsTaskStillRunning( void ) -{ -/* Keep a history of the check variables so we know if they have been incremented -since the last call. */ -static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; -portBASE_TYPE xReturn = pdTRUE, xTask; - - /* Check the maths tasks are still running by ensuring their check variables - are still incrementing. */ - for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) - { - if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) - { - /* The check has not incremented so an error exists. */ - xReturn = pdFALSE; - } - - usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; - } - - return xReturn; -} - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/main.c b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/main.c deleted file mode 100644 index 0e919aead..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/main.c +++ /dev/null @@ -1,719 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * In addition to the standard demo tasks, the follow demo specific tasks are - * create: - * - * The "Check" task. This only executes every three seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the other tasks are still operational. Most tasks maintain - * a unique count that is incremented each time the task successfully completes - * its function. Should any error occur within such a task the count is - * permanently halted. The check task inspects the count of each task to ensure - * it has changed since the last time the check task executed. If all the count - * variables have changed all the tasks are still executing error free, and the - * check task toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - * The "Register Check" tasks. These tasks fill the CPU registers with known - * values, then check that each register still contains the expected value, the - * discovery of an unexpected value being indicative of an error in the RTOS - * context switch mechanism. The register check tasks operate at low priority - * so are switched in and out frequently. - * - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Xilinx library includes. */ -#include "xcache_l.h" -#include "xintc.h" - -/* Demo application includes. */ -#include "flash.h" -#include "integer.h" -#include "comtest2.h" -#include "semtest.h" -#include "BlockQ.h" -#include "dynamic.h" -#include "GenQTest.h" -#include "QPeek.h" -#include "blocktim.h" -#include "death.h" -#include "partest.h" -#include "countsem.h" -#include "recmutex.h" -#include "flop.h" -#include "flop-reg-test.h" - -/* Priorities assigned to the demo tasks. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainFLOP_PRIORITY ( tskIDLE_PRIORITY ) - -/* The first LED used by the COM test and check tasks respectively. */ -#define mainCOM_TEST_LED ( 4 ) -#define mainCHECK_TEST_LED ( 3 ) - -/* The baud rate used by the comtest tasks is set by the hardware, so the -baud rate parameters passed into the comtest initialisation has no effect. */ -#define mainBAUD_SET_IN_HARDWARE ( 0 ) - -/* Delay periods used by the check task. If no errors have been found then -the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an -error has been found at any time then the toggle rate will increase to -mainERROR_CHECK_DELAY milliseconds. */ -#define mainNO_ERROR_CHECK_DELAY ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_CHECK_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) - - -/* - * The tasks defined within this file - described within the comments at the - * head of this page. - */ -static void prvRegTestTask1( void *pvParameters ); -static void prvRegTestTask2( void *pvParameters ); -static void prvErrorChecks( void *pvParameters ); - -/* - * Called by the 'check' task to inspect all the standard demo tasks within - * the system, as described within the comments at the head of this page. - */ -static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); - -/* - * Perform any hardware initialisation required by the demo application. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* xRegTestStatus will get set to pdFAIL by the regtest tasks if they -discover an unexpected value. */ -static volatile unsigned portBASE_TYPE xRegTestStatus = pdPASS; - -/* Counters used to ensure the regtest tasks are still running. */ -static volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - - /* Must be called prior to installing any interrupt handlers! */ - vPortSetupInterruptController(); - - /* In this case prvSetupHardware() just enables the caches and and - configures the IO ports for the LED outputs. */ - prvSetupHardware(); - - /* Start the standard demo application tasks. Note that the baud rate used - by the comtest tasks is set by the hardware, so the baud rate parameter - passed has no effect. */ - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); - vStartQueuePeekTasks(); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartRecursiveMutexTasks(); - - #if ( configUSE_FPU == 1 ) - vStartMathTasks( mainFLOP_PRIORITY ); - vStartFlopRegTests(); - #endif - - /* Create the tasks defined within this file. */ - xTaskCreate( prvRegTestTask1, "Regtest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTestTask2, "Regtest2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* The suicide tasks must be started last as they record the number of other - tasks that exist within the system. The value is then used to ensure at run - time the number of tasks that exists is within expected bounds. */ - vCreateSuicidalTasks( mainDEATH_PRIORITY ); - - /* Now start the scheduler. Following this call the created tasks should - be executing. */ - vTaskStartScheduler(); - - /* vTaskStartScheduler() will only return if an error occurs while the - idle task is being created. */ - for( ;; ); - - return 0; -} -/*-----------------------------------------------------------*/ - -static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) -{ -portBASE_TYPE lReturn = pdPASS; -static unsigned long ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL; - - /* The demo tasks maintain a count that increments every cycle of the task - provided that the task has never encountered an error. This function - checks the counts maintained by the tasks to ensure they are still being - incremented. A count remaining at the same value between calls therefore - indicates that an error has been detected. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - #if ( configUSE_FPU == 1 ) - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreFlopRegisterTestsStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - #endif - - /* Have the register test tasks found any errors? */ - if( xRegTestStatus != pdPASS ) - { - lReturn = pdFAIL; - } - - /* Are the register test tasks still looping? */ - if( ulLastRegTest1Counter == ulRegTest1Counter ) - { - lReturn = pdFAIL; - } - else - { - ulLastRegTest1Counter = ulRegTest1Counter; - } - - if( ulLastRegTest2Counter == ulRegTest2Counter ) - { - lReturn = pdFAIL; - } - else - { - ulLastRegTest2Counter = ulRegTest2Counter; - } - - return lReturn; -} -/*-----------------------------------------------------------*/ - -static void prvErrorChecks( void *pvParameters ) -{ -TickType_t xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime; -volatile unsigned portBASE_TYPE uxFreeStack; - - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* This call is just to demonstrate the use of the function - nothing is - done with the value. You would expect the stack high water mark to be - lower (the function to return a larger value) here at function entry than - later following calls to other functions. */ - uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Again just for demo purposes - uxFreeStack should have a lower value - here than following the call to uxTaskGetStackHighWaterMark() on the - task entry. */ - uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); - - /* Wait until it is time to check again. The time we wait here depends - on whether an error has been detected or not. When an error is - detected the time is shortened resulting in a faster LED flash rate. */ - vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); - - /* See if the other tasks are all ok. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error occurred in one of the tasks so shorten the delay - period - which has the effect of increasing the frequency of the - LED toggle. */ - xDelayPeriod = mainERROR_CHECK_DELAY; - } - - /* Flash! */ - vParTestToggleLED( mainCHECK_TEST_LED ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - XCache_EnableICache( 0x80000000 ); - XCache_EnableDCache( 0x80000000 ); - - /* Setup the IO port for use with the LED outputs. */ - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -void prvRegTest1Pass( void ) -{ - /* Called from the inline assembler - this cannot be static - otherwise it can get optimised away. */ - ulRegTest1Counter++; -} -/*-----------------------------------------------------------*/ - -void prvRegTest2Pass( void ) -{ - /* Called from the inline assembler - this cannot be static - otherwise it can get optimised away. */ - ulRegTest2Counter++; -} -/*-----------------------------------------------------------*/ - -void prvRegTestFail( void ) -{ - /* Called from the inline assembler - this cannot be static - otherwise it can get optimised away. */ - xRegTestStatus = pdFAIL; -} -/*-----------------------------------------------------------*/ - -static void prvRegTestTask1( void *pvParameters ) -{ - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* The first register test task as described at the top of this file. The - values used in the registers are different to those use in the second - register test task. Also, unlike the second register test task, this task - yields between setting the register values and subsequently checking the - register values. */ - asm volatile - ( - "RegTest1Start: \n\t" \ - " \n\t" \ - " li 0, 301 \n\t" \ - " mtspr 256, 0 #USPRG0 \n\t" \ - " li 0, 501 \n\t" \ - " mtspr 8, 0 #LR \n\t" \ - " li 0, 4 \n\t" \ - " mtspr 1, 0 #XER \n\t" \ - " \n\t" \ - " li 0, 1 \n\t" \ - " li 2, 2 \n\t" \ - " li 3, 3 \n\t" \ - " li 4, 4 \n\t" \ - " li 5, 5 \n\t" \ - " li 6, 6 \n\t" \ - " li 7, 7 \n\t" \ - " li 8, 8 \n\t" \ - " li 9, 9 \n\t" \ - " li 10, 10 \n\t" \ - " li 11, 11 \n\t" \ - " li 12, 12 \n\t" \ - " li 13, 13 \n\t" \ - " li 14, 14 \n\t" \ - " li 15, 15 \n\t" \ - " li 16, 16 \n\t" \ - " li 17, 17 \n\t" \ - " li 18, 18 \n\t" \ - " li 19, 19 \n\t" \ - " li 20, 20 \n\t" \ - " li 21, 21 \n\t" \ - " li 22, 22 \n\t" \ - " li 23, 23 \n\t" \ - " li 24, 24 \n\t" \ - " li 25, 25 \n\t" \ - " li 26, 26 \n\t" \ - " li 27, 27 \n\t" \ - " li 28, 28 \n\t" \ - " li 29, 29 \n\t" \ - " li 30, 30 \n\t" \ - " li 31, 31 \n\t" \ - " \n\t" \ - " sc \n\t" \ - " nop \n\t" \ - " \n\t" \ - " cmpwi 0, 1 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 2, 2 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 3, 3 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 4, 4 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 5, 5 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 6, 6 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 7, 7 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 8, 8 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 9, 9 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 10, 10 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 11, 11 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 12, 12 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 13, 13 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 14, 14 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 15, 15 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 16, 16 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 17, 17 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 18, 18 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 19, 19 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 20, 20 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 21, 21 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 22, 22 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 23, 23 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 24, 24 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 25, 25 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 26, 26 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 27, 27 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 28, 28 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 29, 29 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 30, 30 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 31, 31 \n\t" \ - " bne RegTest1Fail \n\t" \ - " \n\t" \ - " mfspr 0, 256 #USPRG0 \n\t" \ - " cmpwi 0, 301 \n\t" \ - " bne RegTest1Fail \n\t" \ - " mfspr 0, 8 #LR \n\t" \ - " cmpwi 0, 501 \n\t" \ - " bne RegTest1Fail \n\t" \ - " mfspr 0, 1 #XER \n\t" \ - " cmpwi 0, 4 \n\t" \ - " bne RegTest1Fail \n\t" \ - " \n\t" \ - " bl prvRegTest1Pass \n\t" \ - " b RegTest1Start \n\t" \ - " \n\t" \ - "RegTest1Fail: \n\t" \ - " \n\t" \ - " \n\t" \ - " bl prvRegTestFail \n\t" \ - " b RegTest1Start \n\t" \ - ); -} -/*-----------------------------------------------------------*/ - -static void prvRegTestTask2( void *pvParameters ) -{ - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* The second register test task as described at the top of this file. - Note that this task fills the registers with different values to the - first register test task. */ - asm volatile - ( - "RegTest2Start: \n\t" \ - " \n\t" \ - " li 0, 300 \n\t" \ - " mtspr 256, 0 #USPRG0 \n\t" \ - " li 0, 500 \n\t" \ - " mtspr 8, 0 #LR \n\t" \ - " li 0, 4 \n\t" \ - " mtspr 1, 0 #XER \n\t" \ - " \n\t" \ - " li 0, 11 \n\t" \ - " li 2, 12 \n\t" \ - " li 3, 13 \n\t" \ - " li 4, 14 \n\t" \ - " li 5, 15 \n\t" \ - " li 6, 16 \n\t" \ - " li 7, 17 \n\t" \ - " li 8, 18 \n\t" \ - " li 9, 19 \n\t" \ - " li 10, 110 \n\t" \ - " li 11, 111 \n\t" \ - " li 12, 112 \n\t" \ - " li 13, 113 \n\t" \ - " li 14, 114 \n\t" \ - " li 15, 115 \n\t" \ - " li 16, 116 \n\t" \ - " li 17, 117 \n\t" \ - " li 18, 118 \n\t" \ - " li 19, 119 \n\t" \ - " li 20, 120 \n\t" \ - " li 21, 121 \n\t" \ - " li 22, 122 \n\t" \ - " li 23, 123 \n\t" \ - " li 24, 124 \n\t" \ - " li 25, 125 \n\t" \ - " li 26, 126 \n\t" \ - " li 27, 127 \n\t" \ - " li 28, 128 \n\t" \ - " li 29, 129 \n\t" \ - " li 30, 130 \n\t" \ - " li 31, 131 \n\t" \ - " \n\t" \ - " cmpwi 0, 11 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 2, 12 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 3, 13 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 4, 14 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 5, 15 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 6, 16 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 7, 17 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 8, 18 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 9, 19 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 10, 110 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 11, 111 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 12, 112 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 13, 113 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 14, 114 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 15, 115 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 16, 116 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 17, 117 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 18, 118 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 19, 119 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 20, 120 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 21, 121 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 22, 122 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 23, 123 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 24, 124 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 25, 125 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 26, 126 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 27, 127 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 28, 128 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 29, 129 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 30, 130 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 31, 131 \n\t" \ - " bne RegTest2Fail \n\t" \ - " \n\t" \ - " mfspr 0, 256 #USPRG0 \n\t" \ - " cmpwi 0, 300 \n\t" \ - " bne RegTest2Fail \n\t" \ - " mfspr 0, 8 #LR \n\t" \ - " cmpwi 0, 500 \n\t" \ - " bne RegTest2Fail \n\t" \ - " mfspr 0, 1 #XER \n\t" \ - " cmpwi 0, 4 \n\t" \ - " bne RegTest2Fail \n\t" \ - " \n\t" \ - " bl prvRegTest2Pass \n\t" \ - " b RegTest2Start \n\t" \ - " \n\t" \ - "RegTest2Fail: \n\t" \ - " \n\t" \ - " \n\t" \ - " bl prvRegTestFail \n\t" \ - " b RegTest2Start \n\t" \ - ); -} -/*-----------------------------------------------------------*/ - -/* This hook function will get called if there is a suspected stack overflow. -An overflow can cause the task name to be corrupted, in which case the task -handle needs to be used to determine the offending task. */ -void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName ); -void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName ) -{ -/* To prevent the optimiser removing the variables. */ -volatile TaskHandle_t xTaskIn = xTask; -volatile signed char *pcTaskNameIn = pcTaskName; - - /* Remove compiler warnings. */ - ( void ) xTaskIn; - ( void ) pcTaskNameIn; - - /* The following three calls are simply to stop compiler warnings about the - functions not being used - they are called from the inline assembly. */ - prvRegTest1Pass(); - prvRegTest2Pass(); - prvRegTestFail(); - - for( ;; ); -} - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c deleted file mode 100644 index 6311f14f6..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Demo application includes. */ -#include "partest.h" - -/* Library includes. */ -#include "xparameters.h" -#include "xgpio_l.h" - -/* Misc hardware specific definitions. */ -#define partstALL_AS_OUTPUT 0x00 -#define partstCHANNEL_1 0x01 -#define partstMAX_4BIT_LED 0x03 - -/* The outputs are split into two IO sections, these variables maintain the -current value of either section. */ -static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit; - -/*-----------------------------------------------------------*/ -/* - * Setup the IO for the LED outputs. - */ -void vParTestInitialise( void ) -{ - /* Set both sets of LED's on the demo board to outputs. */ - XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); - XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); - - /* Start with all outputs off. */ - uxCurrentOutput4Bit = 0; - XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 ); - uxCurrentOutput5Bit = 0; - XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; - - portENTER_CRITICAL(); - { - /* Which IO section does the LED being set/cleared belong to? The - 4 bit or 5 bit outputs? */ - if( uxLED <= partstMAX_4BIT_LED ) - { - uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; - puxCurrentValue = &uxCurrentOutput5Bit; - } - else - { - uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; - puxCurrentValue = &uxCurrentOutput4Bit; - uxLED -= partstMAX_4BIT_LED; - } - - /* Setup the bit mask accordingly. */ - uxLED = 0x01 << uxLED; - - /* Maintain the current output value. */ - if( xValue ) - { - *puxCurrentValue |= uxLED; - } - else - { - *puxCurrentValue &= ~uxLED; - } - - /* Write the value to the port. */ - XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; - - portENTER_CRITICAL(); - { - /* Which IO section does the LED being toggled belong to? The - 4 bit or 5 bit outputs? */ - if( uxLED <= partstMAX_4BIT_LED ) - { - - uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; - puxCurrentValue = &uxCurrentOutput5Bit; - } - else - { - uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; - puxCurrentValue = &uxCurrentOutput4Bit; - uxLED -= partstMAX_4BIT_LED; - } - - /* Setup the bit mask accordingly. */ - uxLED = 0x01 << uxLED; - - /* Maintain the current output value. */ - if( *puxCurrentValue & uxLED ) - { - *puxCurrentValue &= ~uxLED; - } - else - { - *puxCurrentValue |= uxLED; - } - - /* Write the value to the port. */ - XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); - } - portEXIT_CRITICAL(); -} - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c deleted file mode 100644 index 5e390a62a..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" - -/* Library includes. */ -#include "xparameters.h" -#include "xuartlite.h" -#include "xuartlite_l.h" - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static QueueHandle_t xRxedChars; -static QueueHandle_t xCharsForTx; - -/* Structure that maintains information on the UART being used. */ -static XUartLite xUART; - -/* - * Sample UART interrupt handler. Note this is used to demonstrate the kernel - * features and test the port - it is not intended to represent an efficient - * implementation. - */ -static void vSerialISR( XUartLite *pxUART ); - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ - /* NOTE: The baud rate used by this driver is determined by the hardware - parameterization of the UART Lite peripheral, and the baud value passed to - this function has no effect. */ - ( void ) ulWantedBaud; - - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) ); - - /* Only initialise the UART if the queues were created correctly. */ - if( ( xRxedChars != NULL ) && ( xCharsForTx != NULL ) ) - { - - XUartLite_Initialize( &xUART, XPAR_RS232_UART_DEVICE_ID ); - XUartLite_ResetFifos( &xUART ); - XUartLite_DisableInterrupt( &xUART ); - - if( xPortInstallInterruptHandler( XPAR_XPS_INTC_0_RS232_UART_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS ) - { - /* xPortInstallInterruptHandler() could fail if - vPortSetupInterruptController() has not been called prior to this - function. */ - XUartLite_EnableInterrupt( &xUART ); - } - } - - /* There is only one port so the handle is not used. */ - return ( xComPortHandle ) 0; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime ) -{ - /* The port handle is not required as this driver only supports one UART. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime ) -{ -portBASE_TYPE xReturn = pdTRUE; - - /* Just to remove compiler warning. */ - ( void ) pxPort; - - portENTER_CRITICAL(); - { - /* If the UART FIFO is full we can block posting the new data on the - Tx queue. */ - if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) ) - { - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - xReturn = pdFAIL; - } - } - /* Otherwise, if there is data already in the queue we should add the - new data to the back of the queue to ensure the sequencing is - maintained. */ - else if( uxQueueMessagesWaiting( xCharsForTx ) ) - { - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - xReturn = pdFAIL; - } - } - /* If the UART FIFO is not full and there is no data already in the - queue we can write directly to the FIFO without disrupting the - sequence. */ - else - { - XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar ); - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ - ( void ) xPort; -} -/*-----------------------------------------------------------*/ - -static void vSerialISR( XUartLite *pxUART ) -{ -unsigned long ulISRStatus; -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, lDidSomething; -char cChar; - - /* Just to remove compiler warning. */ - ( void ) pxUART; - - do - { - lDidSomething = pdFALSE; - - ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); - - if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 ) - { - /* A character is available - place it in the queue of received - characters. This might wake a task that was blocked waiting for - data. */ - cChar = ( char ) XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET ); - xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken ); - lDidSomething = pdTRUE; - } - - if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 ) - { - /* There is space in the FIFO - if there are any characters queue for - transmission they can be sent to the UART now. This might unblock a - task that was waiting for space to become available on the Tx queue. */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE ) - { - XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar ); - lDidSomething = pdTRUE; - } - } - } while( lDidSomething == pdTRUE ); - - /* If we woke any tasks we may require a context switch. */ - if( xHigherPriorityTaskWoken ) - { - portYIELD_FROM_ISR(); - } -} - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/ReadMe.txt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/ReadMe.txt new file mode 100644 index 000000000..ad84b2770 --- /dev/null +++ b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/ReadMe.txt @@ -0,0 +1,3 @@ +If you need the demo that used to be in this directory then download FreeRTOS V8.2.3 +from http://sourceforge.net/projects/freertos/files/FreeRTOS/ + diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_BifShapes.xsl b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_BifShapes.xsl deleted file mode 100644 index e3f4c3fbc..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_BifShapes.xsl +++ /dev/null @@ -1,211 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Colors.xsl b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Colors.xsl deleted file mode 100644 index a4efce5f4..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Colors.xsl +++ /dev/null @@ -1,134 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Diagrams.css b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Diagrams.css deleted file mode 100644 index bde7995d7..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Diagrams.css +++ /dev/null @@ -1,329 +0,0 @@ - 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} - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_BusLaneSpaces.xsl b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_BusLaneSpaces.xsl deleted file mode 100644 index 90ba612d4..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_BusLaneSpaces.xsl +++ /dev/null @@ -1,2774 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IP - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - x - - - - - - - - - - - x - - - - - - - - y - - x - - - - - - - - - KEY - - - - SYMBOLS - - - bus interface - - - shared bus - - Bus connections - - - master or initiator - - - slave or target - - - master slave - - - monitor - - External Ports - - - input - - - output - - - inout - - - Interrupts - - - interrupt - controller - - - - interrupted - processor - - - - interrupt - source - - x = controller ID - - y = priority - - - - COLORS - - - Bus Standards - - - - - - - - - DCR - - - - - - - - - FCB - - - - - - - - - FSL - - - - - - - - - LMB - - - - - - - - - - OPB - - - - - - - - - PLB - - - - - - - - - - SOCM - - - - - - - - - - XIL (prefix) P2P - - - - - - - - - - GEN. P2P, USER, etc - - - - - - - - - - - - - - - - - SPECS - - - - EDK VERSION - - - - - - - ARCH - - - - - - - PART - - - - - - - GENERATED - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Peripherals.xsl b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Peripherals.xsl deleted file mode 100644 index 7498fe387..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Peripherals.xsl +++ /dev/null @@ -1,1499 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - unkmodule__ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - symbol_ - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 'UNK' - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MPMC Module Interface - - - - - - - - - - - - - - - - - - - - - - - - - - - 4.5 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - -symbol_STACK_ - - - - -symbol_GROUP_ - - - -symbol_SPACE_WEST__EAST_ -symbol_STACK_ -symbol_STACK__SHAPE_ - - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Processors.xsl b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Processors.xsl deleted file mode 100644 index 9e35694e5..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Processors.xsl +++ /dev/null @@ -1,390 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SLAVES OF - - - - - - - - - - - - - - - - - - - - - - - - PROCESSOR - - - - USER MODULE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - "_no_interrupt_cntlr_" - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css deleted file mode 100644 index c1b40cf88..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css +++ /dev/null @@ -1,119 +0,0 @@ - text.busintlabel { - fill: #810017; - stroke: none; - font-size: 7pt; - font-style: italic; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.buslabel { - fill: #CC3333; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.iplabel { - fill: #000000; - stroke: none; - font-size: 7pt; - font-style: italic; - font-weight: 900; - text-anchor: middle; - font-family: Arial Helvetica sans-serif; - } - - text.iptype { - fill: #AA0017; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.portlabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mmMHeader { - fill: #FFFFFF; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mmSHeader { - fill: #810017; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.proclabel { - fill: #810017; - stroke: none; - font-size: 14pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.opblabel { - fill: #339900; - stroke: none; - font-size: 11pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Arial Helvetica sans-serif; - } - - text.lmblabel { - fill: #9999FF; - stroke: none; - font-size: 11pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Arial Helvetica sans-serif; - } - - text.dbglabel { - fill: #555555; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Times Arial Helvetica sans-serif; - } - - text.iopnumb { - fill: #555555; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl deleted file mode 100644 index f91415383..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl +++ /dev/null @@ -1,1211 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Table of Contents - - - - - - - - - - - - - -EDK Project Report - - - - - - - - - - -Block Diagram - - - - - - - - - - - BlockDiagram - -

-

- -

- - - - - - - - - - EDK PROJECT REPORT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- Printable Version -
- - - - -

-

- -
- - - - -

-

- BlockDiagram -
- - - - -

-

- -
- - - - -

- - - - - - - - - - - - -
- -
- -
-
- - - - - - - - - - -
- -
-
- - - - - - - - - - -
- -
-
- - - - - - - - - - -
- -
-
-

- - - - - - - - - - -
- -
- -
- - - - - - - - - - - -
- -
-
- - - - - - - - - - - -
- -
-
- - - - - - - - - - - -
- -
-
- - - - -

- - - - - - - -
- -
-
- - - - -

-

- -
-

-

- - - - - -
line
- - - www.xilinx.com -

- 1-800-255-7778 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TABLE OF CONTENTS
-

- Overview - -

- Block Diagram - -

- External Ports - - - -

- - - Processors - - - Processor - - - - -

-     - -

-           memory map - - - - -

- Debuggers - - -

-     - - - - -

- Interrupt Controllers - - -

-     - - - - -

- Busses - - -

-     - - - - -

- Bridges - - -

-     - - - - -

- Memory - - -

-     - - - - -

- Memory Controllers - - -

-     - - - - -

- Peripherals - - -

-     - - - - -

- IP - - -

-     - - - -

- Timing Information -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- Overview -
- Generated on - - -
- Source - - - - - -
- EDK Version - - - - - - NA - -
- FPGA Family - - - - - - NA - -
- Device - - - - - - - - -
- # IP Instantiated - - -
- # Processors - - -
- # Busses - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
EXTERNAL PORTS
- - These are the external ports defined in the MHS file. - -
- Attributes Key -

- The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file -

- CLK -   indicates Clock ports, (SIGIS = CLK)  -

- INTR -   indicates Interrupt ports,(SIGIS = INTR)  -

- RESET -   indicates Reset ports, (SIGIS = RST)  -

- BUF or REG -   Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- - :1 -  CLK  -  RESET  -  INTR  -  BUF  -  REG  -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- - :1 -  CLK  -  RESET  -  INTR  -  BUF  -  REG  -
- 		-   - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- - :1 -  CLK  -  RESET  -  INTR  -  BUF  -  REG  -
 
- -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Post Synthesis Clock Limits
- - No clocks could be identified in the design. Run platgen to generate synthesis information. - - - - These are the post synthesis clock frequencies. The critical frequencies are marked with - - - green. - -

- - The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system. - -
MODULECLK PortMAX FREQ
- - - - - - - - - - - -
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-

-

- - - - - - - - -
TOCTOP
- - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl deleted file mode 100644 index 4e7beaa51..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl +++ /dev/null @@ -1,611 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - -    - - -

- - - - - -

-

-

-
- {@INSTANCE} IP Image - - -

-

-
- -
- -

-

- - - - - - - - - - - 1 - 0 - - - - - - - - - - 1 - 0 - - - - - - - 4 - 2 - - - - 2 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
General
IP Core - - - - - - - - - - -
Version
Driver - - API - -
License
TYPE - -
EXPIRES ON - -
Parameters
- - These are parameters set for this module. - - Refer to the IP documentation for complete information about module parameters. - - -

- - Parameters marked with - - yellow - - indicate parameters set by the user. - -

- - Parameters marked with - - blue - - indicate parameters set by the system. - -
NameValue
- - - - -
- - - - -
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
- - - - -
- - - - -
- 		- - -
 
- 		- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
- - - - -
- - - - -
 
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Post Synthesis Device Utilization
- - Device utilization information is not available for this IP. Run platgen to generate synthesis information. - -
Resource TypeUsedAvailablePercent
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NA - - - - - - - - NA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
- - The ports listed here are only those connected in the MHS file. - - Refer to the IP documentation for complete information about module ports. - - -
#NAMEDIR[LSB:MSB]SIGNAL
:1
- Bus Interfaces -
MASTERSHIPNAMESTDBUSP2P
Bus Connections
TYPENAMEBIF
- Interrupt Priorities -
PrioritySIGMODULE
- - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl deleted file mode 100644 index 96e9f0cc7..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl +++ /dev/null @@ -1,86 +0,0 @@ - - - - - -]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ■ -   - - - - - ■ - - -   - - - - - - - - - - - - -
- - MEMORY MAP -
D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE
DIBASEHIGHMODULE
- - : - -
- - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl deleted file mode 100644 index 862b7107b..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl +++ /dev/null @@ -1,235 +0,0 @@ - - - - - - -Table of Contents - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TABLE OF CONTENTS
-

- Overview - -

- Block Diagram - -

- External Ports - -

- - - -
- - Processors  - - - Processor  - - -
- - - - -    

- -           memory map

- - - - - - -
- Debuggers  - -
- - - - -    

- - - - - - -
- Interrupt Controllers  - -
- - - - -    

- - - - - -
- Busses  - -
- - - - -    

- - - - - -
- Bridges  - -
- - - -    

- - - - - -
- Memory  - -
- - - -    

- - - - - -
- Memory Controllers  - -
- - - -    

- - - - - -
- Peripherals  - -
- - - -    

- - - - - -
- IP  - -
- - - -    

- - - - - Timing Information

- - -
- - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd deleted file mode 100644 index 110f5ced5..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd +++ /dev/null @@ -1,1704 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/system_shapes.xml b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/system_shapes.xml deleted file mode 100644 index 132e36c9a..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/system_shapes.xml +++ /dev/null @@ -1,1821 +0,0 @@ - - - - - - PowerPC 405 Virtex-4 - A wrapper to instantiate the PowerPC 405 Processor Block primitive - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PowerPC JTAG Controller - JTAGPPC wrapper allows the PowerPC to connect to the JTAG chain of the FPGA. - - - - - - - - - - - - - - - - - - - - - - - - Processor Local Bus (PLB) 4.6 - 'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS UART (Lite) - Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus. - - - - - - - - - - - - - - - - - - Serial Data In - - - Serial Data Out - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS General Purpose IO - General Purpose Input/Output (GPIO) core for the PLBV46 bus. - - - - - - - - - - - - - - - - - - - - - - - - GPIO1 Data IO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS General Purpose IO - General Purpose Input/Output (GPIO) core for the PLBV46 bus. - - - - - - - - - - - - - - - - - - - - - - - - GPIO1 Data IO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS System ACE Interface Controller(Compact Flash) - Interface between the PLBV46 and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral - - - - - - - - - - - - - - Clock Input - - - Address Input - - - Data Input/Output - - - Active LOW Chip Enable - - - Active LOW Output Enable - - - Active LOW Write Enable - - - Active high Interrupt Output - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS Multi-Channel External Memory Controller(SRAM/Flash) - Xilinx Multi-CHannel (MCH) PLBV46 external memory controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Memory Address Bus - - - Memory Byte Enable - - - Memory Write Enable - - - Memory Data Bus - - - Memory Output Enable - - - Memory Chip Enable Active Low - - - Memory Advanced Burst Address/Load New Address - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Utility Bus Split - Bus splitting primitive - - - - - - - - - Clock Generator - Clock generator for processor system. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Processor System Reset Module - Reset management module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS Interrupt Controller - intc core attached to the PLBV46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Fabric Co-processor Bus (FCB) - Fabric Co-processor Bus (FCB) connects one or more FPGA fabric accelerator slaves to the Auxiliary Processor Unit (APU) controller in a Virtex-4 PowerPC 405. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - APU Floating Point Unit - Floating Point Unit via Auxilary Processor Unit. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/bitinit.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/bitinit.opt deleted file mode 100644 index 3645236a6..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/bitinit.opt +++ /dev/null @@ -1 +0,0 @@ - -pe ppc405_0 $(PPC405_0_BOOTLOOP) diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/libgen.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/libgen.opt deleted file mode 100644 index 77b154845..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/libgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p virtex4 diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/platgen.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/platgen.opt deleted file mode 100644 index 25299b7db..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/platgen.opt +++ /dev/null @@ -1,2 +0,0 @@ - -p xc4vfx12ff668-10 -lang vhdl - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt deleted file mode 100644 index 2979e4328..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt +++ /dev/null @@ -1,20 +0,0 @@ -ppc405_0 -RTOSDEMO_SOURCES = RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../Common/Minimal/countsem.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/recmutex.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/flop/flop.c RTOSDemo/flop/flop-reg-test.c -RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h -RTOSDEMO_CC = powerpc-eabi-gcc -RTOSDEMO_CC_SIZE = powerpc-eabi-size -RTOSDEMO_CC_OPT = -O0 -RTOSDEMO_CFLAGS = -I./RTOSDemo/flop -I../../Source/portable/GCC/PPC405_Xilinx -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -Wextra -RTOSDEMO_CC_SEARCH = # -B -RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L -RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ # -I -RTOSDEMO_LFLAGS = # -l -RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo_linker_script.ld -RTOSDEMO_CC_DEBUG_FLAG = -g -RTOSDEMO_CC_PROFILE_FLAG = # -pg -RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi -RTOSDEMO_CC_INFERRED_FLAGS= -mfpu=sp_full -RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= -RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= -RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= - $(RTOSDEMO_CC_INFERRED_FLAGS) \ diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/simgen.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/simgen.opt deleted file mode 100644 index 970a4ea82..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/simgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p virtex4 -lang vhdl -pe ppc405_0 $(PPC405_0_BOOTLOOP) -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/ -E C:/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/ diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system.gui b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system.gui deleted file mode 100644 index 9ccbebeab..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system.gui +++ /dev/null @@ -1,101 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system_routed b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system_routed deleted file mode 100644 index e69de29bb..000000000 diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt deleted file mode 100644 index 39ff0ed04..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt +++ /dev/null @@ -1,20 +0,0 @@ -ppc405_0 -TESTAPP_PERIPHERAL_SOURCES = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xintc_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_selftest_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_intr_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xgpio_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xsysace_selftest_example.c -TESTAPP_PERIPHERAL_HEADERS = /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/intc_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_intr_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/gpio_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/sysace_header.h -TESTAPP_PERIPHERAL_CC = powerpc-eabi-gcc -TESTAPP_PERIPHERAL_CC_SIZE = powerpc-eabi-size -TESTAPP_PERIPHERAL_CC_OPT = -O0 -TESTAPP_PERIPHERAL_CFLAGS = -TESTAPP_PERIPHERAL_CC_SEARCH = # -B -TESTAPP_PERIPHERAL_LIBPATH = -L./ppc405_0/lib/ # -L -TESTAPP_PERIPHERAL_INCLUDES = -I./ppc405_0/include/ -ITestApp_Peripheral/src/ # -I -TESTAPP_PERIPHERAL_LFLAGS = # -l -TESTAPP_PERIPHERAL_LINKER_SCRIPT = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld -TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g -TESTAPP_PERIPHERAL_CC_PROFILE_FLAG = # -pg -TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -msdata=eabi -TESTAPP_PERIPHERAL_CC_INFERRED_FLAGS= -mfpu=sp_full -TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= -TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= -TESTAPP_PERIPHERAL_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= - $(TESTAPP_PERIPHERAL_CC_INFERRED_FLAGS) \ diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/vpgen.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/vpgen.opt deleted file mode 100644 index 8ea8f6640..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/vpgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p xc4vfx12ff668-10 diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xplorer.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xplorer.opt deleted file mode 100644 index 37e5b1190..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xplorer.opt +++ /dev/null @@ -1 +0,0 @@ --device xc4vfx12ff668-10data/system.ucf7 0 diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt deleted file mode 100644 index 33391f035..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt +++ /dev/null @@ -1 +0,0 @@ --device xc4vfx12ff668-10data/system.ucf 0 diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd deleted file mode 100644 index 110f5ced5..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd +++ /dev/null @@ -1,1704 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.css b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.css deleted file mode 100644 index bde7995d7..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.css +++ /dev/null @@ -1,329 +0,0 @@ - text.busintlabel { - fill: #810017; - stroke: none; - font-size: 7pt; - font-style: italic; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mpmctitle { - fill: #FFFFFF; - stroke: none; - font-size: 16pt; - font-weight: bold; - text-anchor: middle; - font-family: Arial Verdana Helvetica sans-serif; - } - - text.mpmcbiflabel { - fill: #FFFFFF; - stroke: none; - font-size: 6pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - - } - - text.buslabel { - fill: #CC3333; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.iplabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: 800; - text-anchor: middle; - font-family: Courier Arial Helvetica sans-serif; - } - - text.iptype { - fill: #AA0017; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.ipclass { - fill: #000000; - stroke: none; - font-size: 7pt; - font-style: normal; - font-weight: bold; - text-anchor: start; - font-family: Times Arial Helvetica sans-serif; - } - - text.procclass { - fill: #000000; - stroke: none; - font-size: 7pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Times Arial Helvetica sans-serif; - } - - - text.portlabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.ipdbiflbl { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: bold; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mmMHeader { - fill: #FFFFFF; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mmSHeader { - fill: #810017; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - - - text.dbglabel { - fill: #555555; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Times Arial Helvetica sans-serif; - } - - text.iopnumb { - fill: #555555; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.ioplblgrp { - fill: #000088; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - - tspan.iopgrp { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - baseline-shift:super; - font-family: Arial Courier san-serif; - } - - - text.biflabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - - } - - text.p2pbuslabel { - fill: #000000; - stroke: none; - font-size: 10pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - writing-mode: tb; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mpbuslabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - writing-mode: tb; - font-family: Verdana Arial Helvetica sans-serif; - } - - - text.sharedbuslabel { - fill: #000000; - stroke: none; - font-size: 10pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - - text.bciplabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Courier Arial Helvetica sans-serif; - } - - text.bciptype { - fill: #AA0017; - stroke: none; - font-size: 6pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.splitbustxt { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: sans-serif; - } - - text.horizp2pbuslabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - - - text.keytitle { - fill: #AA0017; - stroke: none; - font-size: 12pt; - font-weight: bold; - text-anchor: middle; - font-family: Arial Helvetica sans-serif; - } - - text.keyheader { - fill: #000000; - stroke: none; - font-size: 10pt; - font-weight: bold; - text-anchor: middle; - font-family: Arial Helvetica sans-serif; - } - - text.keylabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.keylblul { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - text-decoration: underline; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.specsheader { - fill: #000000; - stroke: none; - font-size: 10pt; - font-weight: bold; - text-anchor: start; - font-family: Arial Helvetica sans-serif; - } - - text.specsvalue { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.specsvaluemid { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.intrsymbol { - fill: #000000; - stroke: none; - font-size: 8pt; - font-weight: bold; - text-anchor: start; - font-family: Arial Helvetica sans-serif; - } - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.html b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.html deleted file mode 100644 index 0f88d6224..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.html +++ /dev/null @@ -1,229 +0,0 @@ - - - -Block Diagram - - -

- - - - - - - - - -
EXTERNAL PORTS
- These are the external ports defined in the MHS file. -
-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- -fpga_0_RS232_Uart_RX_pinI1fpga_0_RS232_Uart_RX
- -fpga_0_RS232_Uart_TX_pinO1fpga_0_RS232_Uart_TX
- -fpga_0_LEDs_4Bit_GPIO_IO_pinIO0:3fpga_0_LEDs_4Bit_GPIO_IO
- -fpga_0_LEDs_Positions_GPIO_IO_pinIO0:4fpga_0_LEDs_Positions_GPIO_IO
- -fpga_0_SysACE_CompactFlash_SysACE_CLK_pinI1fpga_0_SysACE_CompactFlash_SysACE_CLK
- -fpga_0_SysACE_CompactFlash_SysACE_MPA_pinO6:1fpga_0_SysACE_CompactFlash_SysACE_MPA
- -fpga_0_SysACE_CompactFlash_SysACE_MPD_pinIO15:0fpga_0_SysACE_CompactFlash_SysACE_MPD
- -fpga_0_SysACE_CompactFlash_SysACE_CEN_pinO1fpga_0_SysACE_CompactFlash_SysACE_CEN
- -fpga_0_SysACE_CompactFlash_SysACE_OEN_pinO1fpga_0_SysACE_CompactFlash_SysACE_OEN
- -fpga_0_SysACE_CompactFlash_SysACE_WEN_pinO1fpga_0_SysACE_CompactFlash_SysACE_WEN
- -fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pinI1fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
  - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- -fpga_0_SRAM_Mem_A_pinO9:29fpga_0_SRAM_Mem_A
- -fpga_0_SRAM_Mem_BEN_pinO0:3fpga_0_SRAM_Mem_BEN
- -fpga_0_SRAM_Mem_WEN_pinO1fpga_0_SRAM_Mem_WEN
- -fpga_0_SRAM_Mem_DQ_pinIO0:31fpga_0_SRAM_Mem_DQ
- -fpga_0_SRAM_Mem_OEN_pinO0:0fpga_0_SRAM_Mem_OEN
- -fpga_0_SRAM_Mem_CEN_pinO0:0fpga_0_SRAM_Mem_CEN
- -fpga_0_SRAM_Mem_ADV_LDN_pinO1fpga_0_SRAM_Mem_ADV_LDN
- -fpga_0_SRAM_CLOCKO1sys_clk_s
- -sys_clk_pinI1dcm_clk_s CLK 
- -sys_rst_pinI1sys_rst_s RESET 
 
-
- - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.svg b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.svg deleted file mode 100644 index 5991ebf29..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.svg +++ /dev/null @@ -1,1473 +0,0 @@ - - - - - - - - - x - - - - - - x - - - - - y - x - - - - - KEY - - SYMBOLS - - bus interface - - shared bus - Bus connections - - master or initiator - - slave or target - - master slave - - monitor - External Ports - - input - - output - - inout - Interrupts - - interrupt - controller - - interrupted - processor - - interrupt - source - x = controller ID - y = priority - - COLORS - Bus Standards - - DCR - - FCB - - FSL - - LMB - - OPB - - PLB - - SOCM - - XIL (prefix) P2P - - GEN. P2P, USER, etc - - - - - SPECS - - EDK VERSION - 10.1.01 - - ARCH - virtex4 - - PART - xc4vfx12ff668-10 - - GENERATED - Sun May 11 14:31:02 2008 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - plb - - - - - - - - - - - A - xps_gpio - LEDs_4Bit - - - SPLB - - - - - - B - xps_gpio - LEDs_Positions - - - SPLB - - - - - - C - xps_uartlite - RS232_Uart - - - SPLB - - - 0 - 0 - - - - - - D - xps_mch_emc - SRAM - - - SPLB - - - - - - F - xps_sysace - SysACE_CompactFlash - - - SPLB - - - - - xps_intc - xps_intc_0 - - - SPLB - - - 0 - - - - - - - - - - - - - - - - - - - - - util_bus_split - SRAM_util_bus_split_0 - - E - - - - - clock_generator - clock_generator_0 - - G - - - - - - - - - - jtagppc_cntlr - jtagppc_0 - - - JTAG - - - - - proc_sys_reset - proc_sys_reset_0 - - H - - - RESE - - - - - apu_fpu - apu_fpu_0 - - - SFCB - - - - - ppc405_virtex4 - ppc405_0 - - - JTAG - - - IPLB0 - - - DPLB0 - - - RESE - - - MFCB - - - - 0 - - - - - - - - SLAVES OF plb - - PROCESSOR - - - - jtagppc_0_0 - - - - - - - - - - - - - - - - - - ppc_reset_bus - - - - - - - - fcb_v10_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IP - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/data/system.ucf b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/data/system.ucf deleted file mode 100644 index 0b81c8ff8..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/data/system.ucf +++ /dev/null @@ -1,398 +0,0 @@ -############################################################################ -## This system.ucf file is generated by Base System Builder based on the -## settings in the selected Xilinx Board Definition file. Please add other -## user constraints to this file based on customer design specifications. -############################################################################ - -Net sys_clk_pin LOC=AE14; -Net sys_clk_pin IOSTANDARD = LVCMOS33; -Net sys_rst_pin LOC=D6; -Net sys_rst_pin PULLUP; -## System level constraints -Net sys_clk_pin TNM_NET = sys_clk_pin; -TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; -Net sys_rst_pin TIG; -NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP"; -NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP"; -NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP"; -TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; -Net fpga_0_SRAM_CLOCK LOC=AF7; -Net fpga_0_SRAM_CLOCK SLEW = FAST; -Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_CLOCK DRIVE = 16; - -## IO Devices constraints - -#### Module RS232_Uart constraints - -Net fpga_0_RS232_Uart_RX_pin LOC=W2; -Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; -Net fpga_0_RS232_Uart_TX_pin LOC=W1; -Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; - -#### Module LEDs_4Bit constraints - -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; - -#### Module LEDs_Positions constraints - -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; - -#### Module SysACE_CompactFlash constraints - -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF11; -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=Y10; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AA10; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AC7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=Y7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AA9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=Y9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AB7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AC9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AB9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AE6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AD6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AF9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AE9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AD8; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AC8; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AF4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AD3; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AC3; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AF6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AF5; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AD5; -Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AA8; -Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=Y8; -Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin TIG; - -#### Module SRAM constraints - -Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1; -Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2; -Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1; -Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1; -Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2; -Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1; -Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2; -Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1; -Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2; -Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3; -Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3; -Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3; -Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6; -Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5; -Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3; -Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4; -Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3; -Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4; -Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4; -Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5; -Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5; -Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6; -Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5; -Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4; -Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3; -Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6; -Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST; -Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8; -Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13; -Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13; -Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15; -Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16; -Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11; -Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12; -Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14; -Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14; -Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13; -Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13; -Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15; -Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16; -Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11; -Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12; -Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14; -Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14; -Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12; -Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13; -Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16; -Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16; -Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11; -Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11; -Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14; -Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15; -Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13; -Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14; -Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15; -Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16; -Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11; -Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12; -Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13; -Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14; -Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12; -Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6; -Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7; -Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4; -Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST; -Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8; - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/bitgen.ut b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/bitgen.ut deleted file mode 100644 index 976536332..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/bitgen.ut +++ /dev/null @@ -1,20 +0,0 @@ --g CclkPin:PULLUP --g TdoPin:PULLNONE --g M1Pin:PULLDOWN --g DonePin:PULLUP --g DriveDone:No --g StartUpClk:JTAGCLK --g DONE_cycle:4 --g GTS_cycle:5 --g M0Pin:PULLUP --g M2Pin:PULLUP --g ProgPin:PULLUP --g TckPin:PULLUP --g TdiPin:PULLUP --g TmsPin:PULLUP --g DonePipe:No --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:NONE -#-m --g Persist:No diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/download.cmd b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/download.cmd deleted file mode 100644 index 15728dcff..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/download.cmd +++ /dev/null @@ -1,6 +0,0 @@ -setMode -bscan -setCable -p auto -identify -assignfile -p 3 -file implementation/download.bit -program -p 3 -quit diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/fast_runtime.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/fast_runtime.opt deleted file mode 100644 index 6cc2599ab..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/fast_runtime.opt +++ /dev/null @@ -1,82 +0,0 @@ -FLOWTYPE = FPGA; -############################################################### -## Filename: fast_runtime.opt -## -## Option File For Xilinx FPGA Implementation Flow for Fast -## Runtime. -## -## Version: 4.1.1 -############################################################### -# -# Options for Translator -# -# Type "ngdbuild -h" for a detailed list of ngdbuild command line options -# -Program ngdbuild --p ; # Partname to use - picked from xflow commandline --nt timestamp; # NGO File generation. Regenerate only when - # source netlist is newer than existing - # NGO file (default) --bm .bmm # Block RAM memory map file -; # User design - pick from xflow command line --uc .ucf; # ucf constraints -.ngd; # Name of NGD file. Filebase same as design filebase -End Program ngdbuild - -# -# Options for Mapper -# -# Type "map -h " for a detailed list of map command line options -# -Program map --o _map.ncd; # Output Mapped ncd file --pr b; # Pack internal FF/latches into IOBs -#-fp .mfp; # Floorplan file --ol high; --timing; -.ngd; # Input NGD file -.pcf; # Physical constraints file -END Program map - -# -# Options for Post Map Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_map_trce --e 3; # Produce error report limited to 3 items per constraint -#-o _map.twr; # Output trace report file --xml _map.twx; # Output XML version of the timing report -#-tsi _map.tsi; # Produce Timing Specification Interaction report -_map.ncd; # Input mapped ncd -.pcf; # Physical constraints file -END Program post_map_trce - -# -# Options for Place and Route -# -# Type "par -h" for a detailed list of par command line options -# -Program par --w; # Overwrite existing placed and routed ncd --ol high; # Overall effort level -_map.ncd; # Input mapped NCD file -.ncd; # Output placed and routed NCD -.pcf; # Input physical constraints file -END Program par - -# -# Options for Post Par Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_par_trce --e 3; # Produce error report limited to 3 items per constraint -#-o .twr; # Output trace report file --xml .twx; # Output XML version of the timing report -#-tsi .tsi; # Produce Timing Specification Interaction report -.ncd; # Input placed and routed ncd -.pcf; # Physical constraints file -END Program post_par_trce - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt deleted file mode 100644 index 7adb1c0c5..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt +++ /dev/null @@ -1 +0,0 @@ -connect ppc hw -cable type xilinx_parallel port LPT1 frequency 2500000 -debugdevice cpunr 1 fpuType sp diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/platgen.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/platgen.opt deleted file mode 100644 index 185473585..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/platgen.opt +++ /dev/null @@ -1,5 +0,0 @@ --p -xc4vfx12ff668-10 --lang -vhdl -system.mhs diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.bsb b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.bsb deleted file mode 100644 index 12d83ba87..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.bsb +++ /dev/null @@ -1 +0,0 @@ -„æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Db`\b\`bDvC„æÄ®Òôtt¦Êè„ÞÂäÈ@D°ÒØÒÜðD@D¬ÒäèÊð@h@š˜h`f@ŠìÂØêÂèÒÞÜ@ ØÂèÌÞäÚD@DbDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@D‚¤†’¨Š†¨ª¤ŠD@DìÒäèÊðhDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@DˆŠ¬’†Š¾¦’´ŠD@DðÆhìÌðbdDv%„æÄ®ÒôttªàÈÂèʌ Ž‚@D ‚†–‚ŽŠD@DÌÌllpDv&„æÄ®ÒôttªàÈÂèʌ Ž‚@D¦ ŠŠˆŽ¤‚ˆŠD@DZb`Dv3„æÄ®Òôtt¦Êè¦òæèÊÚ@DààÆh`j¾ìÒäèÊðh¾àØÄìhlD@Db\``\ÂDv,„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D„ª¦¾Œ¤Š¢D@Db``\``````Dv,„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D†˜–¾Œ¤Š¢D@Db``\``````Dv-„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D ¤ž†¾Œ¤Š¢D@Dd``\``````Dv(„æÄ®ÒôttªàÈÂèʦòæèÊÚ@D¤¦¨¾ ž˜‚¤’¨²D@D`Dv1„æÄ®Òôtt‚ÈÈ äÞÆÊææÞä@DààÆh`j¾`D@DààÆh`j¾ìÒäèÊðhDv/„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D†‚†ŠD@DbDv3„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D†¾ª¦Š¾Œ ªD@DbDv:„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@DˆŠ„ªŽ¾’ŒD@DŒ Ž‚@”¨‚ŽDv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@Dˆž†š@¦’´ŠD@DœžœŠDv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D’ž†š@¦’´ŠD@DœžœŠDv2„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@Dž†š¾žœ˜²D@D`Dv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäèD@Dðàæ¾êÂäèØÒèÊDv9„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾„‚ªˆ¤‚¨ŠD@Drl``Dv7„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ˆ‚¨‚¾„’¨¦D@DpDv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾žˆˆ¾ ‚¤’¨²D@D`Dv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ª¦Š¾ ‚¤’¨²D@D`Dv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D’ž¨² ŠD@D°’˜¾ª‚¤¨¾¬bDv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@Dª¦Š¾’œ¨Š¤¤ª ¨D@D¨¤ªŠDv-„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾h„ÒèD@Dðàæ¾ÎàÒÞDv;„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾h„ÒèD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾ ÞæÒèÒÞÜæD@Dðàæ¾ÎàÒÞDv@„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾ ÞæÒèÒÞÜæD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv9„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¦ò悆Š¾†ÞÚàÂÆèŒØÂæÐD@Dðàæ¾æòæÂÆÊDvG„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¦ò悆Š¾†ÞÚàÂÆèŒØÂæÐD@D’ž¨² ŠD@D°’˜¾¦²¦‚†Š¾¬bDv+„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¦¤‚šD@Dðàæ¾ÚÆоÊÚÆDv5„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¦¤‚šD@D’ž¨² ŠD@D°’˜¾Šš†¾¬bDv:„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†‚†Š¾†‚œˆ’ˆ‚¨Š¦D@D¦¤‚švDv8„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†¾†‚†Š¾„²¨Š¾¦’´ŠD@DblDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†¾ˆ†‚†Š¾„²¨Š¾¦’´ŠD@DblDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@Dˆ†‚†Š¾†ž¤Š˜’¦¨D@Dv¦¤‚šDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D’†‚†Š¾†ž¤Š˜’¦¨D@Dv¦¤‚šDv:„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D’œ¦¨‚œ†Š¾œ‚šŠD@DààÆh`j¾`Dv/„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾šŠš¨Š¦¨D@DŒ‚˜¦ŠDv1„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾ Š¤’ ¨Š¦¨D@D¨¤ªŠDv)„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾¦®‚  ¦D@DDv7„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D’œ¦¨‚œ†Š¾œ‚šŠD@DààÆh`j¾`Dv0„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾„žž¨šŠšD@D¦¤‚šDv.„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾¦¨ˆ’œD@DœÞÜÊDv/„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾¦¨ˆžª¨D@DœÞÜÊDv@„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ˆ‚¨‚¾’œ¦D@D¦¤‚šDvK„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ˆ‚¨‚¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvC„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ ¤žŽ¤‚š¾’œ¦D@D¦¤‚šDvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ ¤žŽ¤‚š¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvA„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¦¨‚†–¾’œ¦D@D¦¤‚šDvL„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¦¨‚†–¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvC„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¬Š†¨ž¤¦¾’œ¦D@D¦¤‚šDvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¬Š†¨ž¤¦¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤Dv \ No newline at end of file diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.make b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.make deleted file mode 100644 index 492fe8879..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.make +++ /dev/null @@ -1,269 +0,0 @@ -################################################################# -# Makefile generated by Xilinx Platform Studio -# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.xmp -# -# WARNING : This file will be re-generated every time a command -# to run a make target is invoked. So, any changes made to this -# file manually, will be lost when make is invoked next. -################################################################# - -# Name of the Microprocessor system -# The hardware specification of the system is in file : -# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.mhs -# The software specification of the system is in file : -# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.mss - -include system_incl.make - -################################################################# -# PHONY TARGETS -################################################################# -.PHONY: dummy -.PHONY: netlistclean -.PHONY: bitsclean -.PHONY: simclean -.PHONY: vpclean - -################################################################# -# EXTERNAL TARGETS -################################################################# -all: - @echo "Makefile to build a Microprocessor system :" - @echo "Run make with any of the following targets" - @echo " " - @echo " netlist : Generates the netlist for the given MHS " - @echo " bits : Runs Implementation tools to generate the bitstream" - @echo " " - @echo " libs : Configures the sw libraries for this system" - @echo " program : Compiles the program sources for all the processor instances" - @echo " " - @echo " init_bram: Initializes bitstream with BRAM data" - @echo " ace : Generate ace file from bitstream and elf" - @echo " download : Downloads the bitstream onto the board" - @echo " " - @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" - @echo " simmodel : Generates HDL simulation models for chosen simulation mode" - @echo " behavioral_model : Generates behavioral HDL models with BRAM initialization" - @echo " structural_model : Generates structural simulation HDL models with BRAM initialization" - @echo " timing : Generates timing simulation HDL models with BRAM initialization" - @echo " vp : Generates virtual platform model" - @echo " " - @echo " netlistclean: Deletes netlist" - @echo " bitsclean: Deletes bit, ncd, bmm files" - @echo " hwclean : Deletes implementation dir" - @echo " libsclean: Deletes sw libraries" - @echo " programclean: Deletes compiled ELF files" - @echo " swclean : Deletes sw libraries and ELF files" - @echo " simclean : Deletes simulation dir" - @echo " vpclean : Deletes virtualplatform dir" - @echo " clean : Deletes all generated files/directories" - @echo " " - @echo " make : (Default)" - @echo " Creates a Microprocessor system using default initializations" - @echo " specified for each processor in MSS file" - - -bits: $(SYSTEM_BIT) - -ace: $(SYSTEM_ACE) - -netlist: $(POSTSYN_NETLIST) - -libs: $(LIBRARIES) - -program: $(ALL_USER_ELF_FILES) - -download: $(DOWNLOAD_BIT) dummy - @echo "*********************************************" - @echo "Downloading Bitstream onto the target board" - @echo "*********************************************" - impact -batch etc/download.cmd - -init_bram: $(DOWNLOAD_BIT) - -sim: $(DEFAULT_SIM_SCRIPT) - cd simulation/behavioral; \ - $(SIM_CMD) & - -simmodel: $(DEFAULT_SIM_SCRIPT) - -behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) - -structural_model: $(STRUCTURAL_SIM_SCRIPT) - -vp: $(VPEXEC) - -clean: hwclean libsclean programclean simclean vpclean - rm -f _impact.cmd - rm -f *.log - -hwclean: netlistclean bitsclean - rm -rf implementation synthesis xst hdl - rm -rf xst.srp $(SYSTEM).srp - -netlistclean: - rm -f $(POSTSYN_NETLIST) - rm -f platgen.log - rm -f $(BMM_FILE) - -bitsclean: - rm -f $(SYSTEM_BIT) - rm -f implementation/$(SYSTEM).ncd - rm -f implementation/$(SYSTEM)_bd.bmm - rm -f implementation/$(SYSTEM)_map.ncd - -simclean: - rm -rf simulation/behavioral - rm -f simgen.log - -swclean: libsclean programclean - @echo "" - -libsclean: $(LIBSCLEAN_TARGETS) - rm -f libgen.log - -programclean: $(PROGRAMCLEAN_TARGETS) - -vpclean: - rm -rf virtualplatform - rm -f vpgen.log - -################################################################# -# SOFTWARE PLATFORM FLOW -################################################################# - - -$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt - @echo "*********************************************" - @echo "Creating software libraries..." - @echo "*********************************************" - libgen $(LIBGEN_OPTIONS) $(MSSFILE) - - -ppc405_0_libsclean: - rm -rf ppc405_0/ - -################################################################# -# SOFTWARE APPLICATION RTOSDEMO -################################################################# - -RTOSDemo_program: $(RTOSDEMO_OUTPUT) - -$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \ - $(LIBRARIES) __xps/rtosdemo_compiler.opt - @mkdir -p $(RTOSDEMO_OUTPUT_DIR) - $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \ - $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \ - $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) - $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) - @echo "" - -RTOSDemo_programclean: - rm -f $(RTOSDEMO_OUTPUT) - -################################################################# -# BOOTLOOP ELF FILES -################################################################# - - - -$(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP) - @mkdir -p $(BOOTLOOP_DIR) - cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP) - -################################################################# -# HARDWARE IMPLEMENTATION FLOW -################################################################# - - -$(BMM_FILE) \ -$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ - $(CORE_STATE_DEVELOPMENT_FILES) - @echo "****************************************************" - @echo "Creating system netlist for hardware specification.." - @echo "****************************************************" - platgen $(PLATGEN_OPTIONS) $(MHSFILE) - -$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) - @echo "Running synthesis..." - bash -c "cd synthesis; ./synthesis.sh" - -__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY) - @echo "*********************************************" - @echo "Running Xilinx Implementation tools.." - @echo "*********************************************" - @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf - xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/manage_fastruntime_opt.pl $(MANAGE_FASTRT_OPTIONS) - xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc - touch __xps/$(SYSTEM)_routed - -$(SYSTEM_BIT): __xps/$(SYSTEM)_routed - xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par - @echo "*********************************************" - @echo "Running Bitgen.." - @echo "*********************************************" - @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut - cd implementation; bitgen -w -f bitgen.ut $(SYSTEM) - -$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt - # @cp -f implementation/$(SYSTEM)_bd.bmm . - @echo "*********************************************" - @echo "Initializing BRAM contents of the bitstream" - @echo "*********************************************" - bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \ - -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) - @rm -f $(SYSTEM)_bd.bmm - -$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) - @echo "*********************************************" - @echo "Creating system ace file" - @echo "*********************************************" - xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE) - -################################################################# -# SIMULATION FLOW -################################################################# - - -################## BEHAVIORAL SIMULATION ################## - -$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ - $(BRAMINIT_ELF_FILES) - @echo "*********************************************" - @echo "Creating behavioral simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) - -################## STRUCTURAL SIMULATION ################## - -$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ - $(BRAMINIT_ELF_FILES) - @echo "*********************************************" - @echo "Creating structural simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) - - -################## TIMING SIMULATION ################## - -$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \ - $(BRAMINIT_ELF_FILES) - @echo "*********************************************" - @echo "Creating timing simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) - -################################################################# -# VIRTUAL PLATFORM FLOW -################################################################# - - -$(VPEXEC): $(MHSFILE) __xps/vpgen.opt - @echo "****************************************************" - @echo "Creating virtual platform for hardware specification.." - @echo "****************************************************" - vpgen $(VPGEN_OPTIONS) $(MHSFILE) - -dummy: - @echo "" - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mhs b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mhs deleted file mode 100644 index 640fae030..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mhs +++ /dev/null @@ -1,225 +0,0 @@ - -# ############################################################################## -# Created by Base System Builder Wizard for Xilinx EDK 10.1.01 Build EDK_K_SP1.3 -# Fri May 09 11:01:33 2008 -# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1 -# Family: virtex4 -# Device: xc4vfx12 -# Package: ff668 -# Speed Grade: -10 -# Processor: ppc405_0 -# Processor clock frequency: 200.00 MHz -# Bus clock frequency: 100.00 MHz -# Total Off Chip Memory : 1 MB -# - SRAM = 1 MB -# ############################################################################## - PARAMETER VERSION = 2.1.0 - - - PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I - PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O - PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3] - PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4] - PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I - PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1] - PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0] - PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O - PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O - PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O - PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I - PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [9:29] - PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3] - PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O - PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31] - PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0] - PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0] - PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O - PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O - PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 - PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST - - -BEGIN ppc405_virtex4 - PARAMETER INSTANCE = ppc405_0 - PARAMETER HW_VER = 2.01.a - PARAMETER C_FASTEST_PLB_CLOCK = DPLB0 - PARAMETER C_APU_CONTROL = 0b0000000000000001 - PARAMETER C_IDCR_BASEADDR = 0b0100000000 - PARAMETER C_IDCR_HIGHADDR = 0b0111111111 - BUS_INTERFACE JTAGPPC = jtagppc_0_0 - BUS_INTERFACE IPLB0 = plb - BUS_INTERFACE DPLB0 = plb - BUS_INTERFACE RESETPPC = ppc_reset_bus - BUS_INTERFACE MFCB = fcb_v10_0 - PORT CPMC405CLOCK = proc_clk_s - PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ -END - -BEGIN jtagppc_cntlr - PARAMETER INSTANCE = jtagppc_0 - PARAMETER HW_VER = 2.01.a - BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 -END - -BEGIN plb_v46 - PARAMETER INSTANCE = plb - PARAMETER C_DCR_INTFCE = 0 - PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100 - PARAMETER HW_VER = 1.02.a - PORT PLB_Clk = sys_clk_s - PORT SYS_Rst = sys_bus_reset -END - -BEGIN xps_uartlite - PARAMETER INSTANCE = RS232_Uart - PARAMETER HW_VER = 1.00.a - PARAMETER C_BAUDRATE = 9600 - PARAMETER C_DATA_BITS = 8 - PARAMETER C_ODD_PARITY = 0 - PARAMETER C_USE_PARITY = 0 - PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000 - PARAMETER C_BASEADDR = 0x84000000 - PARAMETER C_HIGHADDR = 0x8400ffff - BUS_INTERFACE SPLB = plb - PORT RX = fpga_0_RS232_Uart_RX - PORT TX = fpga_0_RS232_Uart_TX - PORT Interrupt = RS232_Uart_Interrupt -END - -BEGIN xps_gpio - PARAMETER INSTANCE = LEDs_4Bit - PARAMETER HW_VER = 1.00.a - PARAMETER C_GPIO_WIDTH = 4 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_IS_BIDIR = 1 - PARAMETER C_ALL_INPUTS = 0 - PARAMETER C_BASEADDR = 0x81400000 - PARAMETER C_HIGHADDR = 0x8140ffff - BUS_INTERFACE SPLB = plb - PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO -END - -BEGIN xps_gpio - PARAMETER INSTANCE = LEDs_Positions - PARAMETER HW_VER = 1.00.a - PARAMETER C_GPIO_WIDTH = 5 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_IS_BIDIR = 1 - PARAMETER C_ALL_INPUTS = 0 - PARAMETER C_BASEADDR = 0x81420000 - PARAMETER C_HIGHADDR = 0x8142ffff - BUS_INTERFACE SPLB = plb - PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO -END - -BEGIN xps_sysace - PARAMETER INSTANCE = SysACE_CompactFlash - PARAMETER HW_VER = 1.00.a - PARAMETER C_MEM_WIDTH = 16 - PARAMETER C_BASEADDR = 0x83600000 - PARAMETER C_HIGHADDR = 0x8360ffff - BUS_INTERFACE SPLB = plb - PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK - PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA - PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD - PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN - PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN - PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN - PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ -END - -BEGIN xps_mch_emc - PARAMETER INSTANCE = SRAM - PARAMETER HW_VER = 1.01.a - PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000 - PARAMETER C_NUM_BANKS_MEM = 1 - PARAMETER C_MAX_MEM_WIDTH = 32 - PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1 - PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 - PARAMETER C_MEM0_WIDTH = 32 - PARAMETER C_SYNCH_MEM_0 = 1 - PARAMETER C_TCEDV_PS_MEM_0 = 0 - PARAMETER C_TWC_PS_MEM_0 = 0 - PARAMETER C_TAVDV_PS_MEM_0 = 0 - PARAMETER C_TWP_PS_MEM_0 = 0 - PARAMETER C_THZCE_PS_MEM_0 = 0 - PARAMETER C_TLZWE_PS_MEM_0 = 0 - PARAMETER C_MEM0_BASEADDR = 0xfff00000 - PARAMETER C_MEM0_HIGHADDR = 0xffffffff - BUS_INTERFACE SPLB = plb - PORT Mem_A = fpga_0_SRAM_Mem_A_split - PORT Mem_BEN = fpga_0_SRAM_Mem_BEN - PORT Mem_WEN = fpga_0_SRAM_Mem_WEN - PORT Mem_DQ = fpga_0_SRAM_Mem_DQ - PORT Mem_OEN = fpga_0_SRAM_Mem_OEN - PORT Mem_CEN = fpga_0_SRAM_Mem_CEN - PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN - PORT RdClk = sys_clk_s -END - -BEGIN util_bus_split - PARAMETER INSTANCE = SRAM_util_bus_split_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_SIZE_IN = 32 - PARAMETER C_LEFT_POS = 9 - PARAMETER C_SPLIT = 30 - PORT Sig = fpga_0_SRAM_Mem_A_split - PORT Out1 = fpga_0_SRAM_Mem_A -END - -BEGIN clock_generator - PARAMETER INSTANCE = clock_generator_0 - PARAMETER HW_VER = 2.01.a - PARAMETER C_EXT_RESET_HIGH = 1 - PARAMETER C_CLKIN_FREQ = 100000000 - PARAMETER C_CLKOUT0_FREQ = 200000000 - PARAMETER C_CLKOUT0_BUF = TRUE - PARAMETER C_CLKOUT0_PHASE = 0 - PARAMETER C_CLKOUT0_GROUP = NONE - PARAMETER C_CLKOUT1_FREQ = 100000000 - PARAMETER C_CLKOUT1_BUF = TRUE - PARAMETER C_CLKOUT1_PHASE = 0 - PARAMETER C_CLKOUT1_GROUP = NONE - PORT CLKOUT0 = proc_clk_s - PORT CLKOUT1 = sys_clk_s - PORT CLKIN = dcm_clk_s - PORT LOCKED = Dcm_all_locked - PORT RST = net_gnd -END - -BEGIN proc_sys_reset - PARAMETER INSTANCE = proc_sys_reset_0 - PARAMETER HW_VER = 2.00.a - PARAMETER C_EXT_RESET_HIGH = 0 - BUS_INTERFACE RESETPPC0 = ppc_reset_bus - PORT Slowest_sync_clk = sys_clk_s - PORT Dcm_locked = Dcm_all_locked - PORT Ext_Reset_In = sys_rst_s - PORT Bus_Struct_Reset = sys_bus_reset - PORT Peripheral_Reset = sys_periph_reset -END - -BEGIN xps_intc - PARAMETER INSTANCE = xps_intc_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_BASEADDR = 0x81800000 - PARAMETER C_HIGHADDR = 0x8180ffff - BUS_INTERFACE SPLB = plb - PORT Irq = EICC405EXTINPUTIRQ - PORT Intr = RS232_Uart_Interrupt -END - -BEGIN fcb_v10 - PARAMETER INSTANCE = fcb_v10_0 - PARAMETER HW_VER = 1.00.a - PORT FCB_CLK = proc_clk_s - PORT SYS_RST = sys_bus_reset -END - -BEGIN apu_fpu - PARAMETER INSTANCE = apu_fpu_0 - PARAMETER HW_VER = 3.10.a - BUS_INTERFACE SFCB = fcb_v10_0 - PORT FPU_CLK = sys_clk_s -END - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mss b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mss deleted file mode 100644 index 737c30840..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mss +++ /dev/null @@ -1,88 +0,0 @@ - - PARAMETER VERSION = 2.2.0 - - -BEGIN OS - PARAMETER OS_NAME = standalone - PARAMETER OS_VER = 2.00.a - PARAMETER PROC_INSTANCE = ppc405_0 -END - - -BEGIN PROCESSOR - PARAMETER DRIVER_NAME = cpu_ppc405 - PARAMETER DRIVER_VER = 1.10.a - PARAMETER HW_INSTANCE = ppc405_0 - PARAMETER COMPILER = powerpc-eabi-gcc - PARAMETER ARCHIVER = powerpc-eabi-ar - PARAMETER CORE_CLOCK_FREQ_HZ = 200000000 -END - - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = jtagppc_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = uartlite - PARAMETER DRIVER_VER = 1.13.a - PARAMETER HW_INSTANCE = RS232_Uart -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = gpio - PARAMETER DRIVER_VER = 2.12.a - PARAMETER HW_INSTANCE = LEDs_4Bit -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = gpio - PARAMETER DRIVER_VER = 2.12.a - PARAMETER HW_INSTANCE = LEDs_Positions -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = sysace - PARAMETER DRIVER_VER = 1.11.a - PARAMETER HW_INSTANCE = SysACE_CompactFlash -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = emc - PARAMETER DRIVER_VER = 2.00.a - PARAMETER HW_INSTANCE = SRAM -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = SRAM_util_bus_split_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = clock_generator_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = proc_sys_reset_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = intc - PARAMETER DRIVER_VER = 1.11.a - PARAMETER HW_INSTANCE = xps_intc_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = apu_fpu - PARAMETER DRIVER_VER = 2.10.a - PARAMETER HW_INSTANCE = apu_fpu_0 -END - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.xmp b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.xmp deleted file mode 100644 index 4a7a93ca7..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.xmp +++ /dev/null @@ -1,74 +0,0 @@ -#Please do not modify this file by hand -XmpVersion: 10.1.01 -VerMgmt: 10.1.01 -IntStyle: default -MHS File: system.mhs -MSS File: system.mss -NPL File: projnav/system.ise -Architecture: virtex4 -Device: xc4vfx12 -Package: ff668 -SpeedGrade: -10 -UserCmd1: -UserCmd1Type: 0 -UserCmd2: -UserCmd2Type: 0 -TopInst: system_i -GenSimTB: 0 -InsertNoPads: 0 -WarnForEAArch: 1 -HdlLang: VHDL -Simulator: mti -SimModel: BEHAVIORAL -MixLangSim: 1 -UcfFile: data/system.ucf -FpgaImpMode: 0 -EnableParTimingError: 1 -EnableResetOptimization: 0 -ShowLicenseDialog: 1 -ICacheAddr: SRAM, -DCacheAddr: SRAM, -Processor: ppc405_0 -BootLoop: 1 -XmdStub: 0 -SwProj: RTOSDemo -Processor: ppc405_0 -Executable: RTOSDemo/executable.elf -Source: RTOSDemo/../../Common/Minimal/BlockQ.c -Source: RTOSDemo/../../Common/Minimal/blocktim.c -Source: RTOSDemo/../../Common/Minimal/comtest.c -Source: RTOSDemo/../../Common/Minimal/countsem.c -Source: RTOSDemo/../../Common/Minimal/death.c -Source: RTOSDemo/../../Common/Minimal/dynamic.c -Source: RTOSDemo/../../Common/Minimal/flash.c -Source: RTOSDemo/../../Common/Minimal/GenQTest.c -Source: RTOSDemo/../../Common/Minimal/integer.c -Source: RTOSDemo/../../Common/Minimal/QPeek.c -Source: RTOSDemo/../../Common/Minimal/recmutex.c -Source: RTOSDemo/../../Common/Minimal/semtest.c -Source: RTOSDemo/../../../Source/tasks.c -Source: RTOSDemo/../../../Source/list.c -Source: RTOSDemo/../../../Source/queue.c -Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c -Source: RTOSDemo/main.c -Source: RTOSDemo/serial/serial.c -Source: RTOSDemo/partest/partest.c -Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S -Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c -Source: RTOSDemo/flop/flop.c -Source: RTOSDemo/flop/flop-reg-test.c -Header: RTOSDemo/FreeRTOSConfig.h -DefaultInit: EXECUTABLE -InitBram: 0 -Active: 1 -CompilerOptLevel: 0 -GlobPtrOpt: 0 -DebugSym: 1 -ProfileFlag: 0 -ProgStart: -StackSize: -HeapSize: -LinkerScript: RTOSDemo/RTOSDemo_linker_script.ld -ProgCCFlags: -I./RTOSDemo/flop -I../../Source/portable/GCC/PPC405_Xilinx -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -CompileInXps: 1 -NonXpsApp: 0 diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system_incl.make b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system_incl.make deleted file mode 100644 index 7f558699b..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system_incl.make +++ /dev/null @@ -1,144 +0,0 @@ -################################################################# -# Makefile generated by Xilinx Platform Studio -# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.xmp -# -# WARNING : This file will be re-generated every time a command -# to run a make target is invoked. So, any changes made to this -# file manually, will be lost when make is invoked next. -################################################################# - -XILINX_EDK_DIR = /cygdrive/c/devtools/Xilinx/10.1/EDK -NON_CYG_XILINX_EDK_DIR = C:/devtools/Xilinx/10.1/EDK - -SYSTEM = system - -MHSFILE = system.mhs - -MSSFILE = system.mss - -FPGA_ARCH = virtex4 - -DEVICE = xc4vfx12ff668-10 - -LANGUAGE = vhdl - -SEARCHPATHOPT = - -SUBMODULE_OPT = - -PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) - -LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) - -VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT) - -MANAGE_FASTRT_OPTIONS = -reduce_fanout no - -OBSERVE_PAR_OPTIONS = -error yes - -RTOSDEMO_OUTPUT_DIR = RTOSDemo -RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf - -MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf -PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf -PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf -BOOTLOOP_DIR = bootloops - -PPC405_0_BOOTLOOP = $(BOOTLOOP_DIR)/ppc405_0.elf - -BRAMINIT_ELF_FILES = -BRAMINIT_ELF_FILE_ARGS = - -ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) - -SIM_CMD = vsim - -BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do - -STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do - -TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do - -DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) - -MIX_LANG_SIM_OPT = -mixed yes - -SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/ -E C:/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/ - - -LIBRARIES = \ - ppc405_0/lib/libxil.a -VPEXEC = virtualplatform/vpexec.exe - -LIBSCLEAN_TARGETS = ppc405_0_libsclean - -PROGRAMCLEAN_TARGETS = RTOSDemo_programclean - -CORE_STATE_DEVELOPMENT_FILES = - -WRAPPER_NGC_FILES = implementation/ppc405_0_wrapper.ngc \ -implementation/jtagppc_0_wrapper.ngc \ -implementation/plb_wrapper.ngc \ -implementation/rs232_uart_wrapper.ngc \ -implementation/leds_4bit_wrapper.ngc \ -implementation/leds_positions_wrapper.ngc \ -implementation/sysace_compactflash_wrapper.ngc \ -implementation/sram_wrapper.ngc \ -implementation/sram_util_bus_split_0_wrapper.ngc \ -implementation/clock_generator_0_wrapper.ngc \ -implementation/proc_sys_reset_0_wrapper.ngc \ -implementation/xps_intc_0_wrapper.ngc \ -implementation/fcb_v10_0_wrapper.ngc \ -implementation/apu_fpu_0_wrapper.ngc - -POSTSYN_NETLIST = implementation/$(SYSTEM).ngc - -SYSTEM_BIT = implementation/$(SYSTEM).bit - -DOWNLOAD_BIT = implementation/download.bit - -SYSTEM_ACE = implementation/$(SYSTEM).ace - -UCF_FILE = data/system.ucf - -BMM_FILE = implementation/$(SYSTEM).bmm - -BITGEN_UT_FILE = etc/bitgen.ut - -XFLOW_OPT_FILE = etc/fast_runtime.opt -XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE) - -XPLORER_DEPENDENCY = __xps/xplorer.opt -XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7 - -FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(BITGEN_UT_FILE) $(XFLOW_DEPENDENCY) - -################################################################# -# SOFTWARE APPLICATION RTOSDEMO -################################################################# - -RTOSDEMO_SOURCES = RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../Common/Minimal/countsem.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/recmutex.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/flop/flop.c RTOSDemo/flop/flop-reg-test.c - -RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h - -RTOSDEMO_CC = powerpc-eabi-gcc -RTOSDEMO_CC_SIZE = powerpc-eabi-size -RTOSDEMO_CC_OPT = -O0 -RTOSDEMO_CFLAGS = -I./RTOSDemo/flop -I../../Source/portable/GCC/PPC405_Xilinx -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -RTOSDEMO_CC_SEARCH = # -B -RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L -RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ # -I -RTOSDEMO_LFLAGS = # -l -RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo_linker_script.ld -RTOSDEMO_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) -RTOSDEMO_CC_DEBUG_FLAG = -g -RTOSDEMO_CC_PROFILE_FLAG = # -pg -RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi -RTOSDEMO_CC_INFERRED_FLAGS= -mfpu=sp_full -RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= -RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= -RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= -RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \ - $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) $(RTOSDEMO_CC_HEAP_SIZE_FLAG) \ - $(RTOSDEMO_CC_INFERRED_FLAGS) \ - $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) $(RTOSDEMO_CC_PROFILE_FLAG) diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/wizlog b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/wizlog deleted file mode 100644 index 3f4f48396..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/wizlog +++ /dev/null @@ -1,3 +0,0 @@ -WARNING:MDT - ppc405_virtex4 (ppc405_0) - - C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\dump.mhs - line 28 - ADDRESS specified by PARAMETER C_IDCR_BASEADDR is ignored diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h deleted file mode 100644 index f2072a23d..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 250 ) -#define configCPU_CLOCK_HZ ( ( unsigned long ) 200000000 ) /* Clock setup from start.asm in the demo application. */ -#define configTICK_RATE_HZ ( (TickType_t) 1000 ) -#define configMAX_PRIORITIES ( 6 ) -#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) ) -#define configMAX_TASK_NAME_LEN ( 20 ) -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configUSE_TRACE_FACILITY 0 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_APPLICATION_TASK_TAG 1 -#define configUSE_FPU 0 - - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 4 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vResumeFromISR 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define configUSE_RECURSIVE_MUTEXES 1 - - -#if configUSE_FPU == 1 - /* Include the header that define the traceTASK_SWITCHED_IN() and - traceTASK_SWITCHED_OUT() macros to save and restore the floating - point registers for tasks that have requested this behaviour. */ - #include "FPU_Macros.h" -#endif - -#endif /* FREERTOS_CONFIG_H */ - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld deleted file mode 100644 index 0a5bdac6a..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld +++ /dev/null @@ -1,209 +0,0 @@ -/*******************************************************************/ -/* */ -/* This file is automatically generated by linker script generator.*/ -/* */ -/* Version: Xilinx EDK 10.1.01 EDK_K_SP1.3 */ -/* */ -/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */ -/* */ -/* Description : PowerPC405 Linker Script */ -/* */ -/*******************************************************************/ - -_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400; -_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x100; - -/* Define Memories in the system */ - -MEMORY -{ - SRAM_C_MEM0_BASEADDR : ORIGIN = 0xFFF00000, LENGTH = 0x000FFFEC -} - -/* Specify the default entry point to the program */ - -ENTRY(_boot) -STARTUP(boot.o) - -/* Define the sections, and where they are mapped in memory */ - -SECTIONS -{ -.vectors : { - __vectors_start = .; - *(.vectors) - __vectors_end = .; -} > SRAM_C_MEM0_BASEADDR - -.text : { - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) -} > SRAM_C_MEM0_BASEADDR - -.init : { - KEEP (*(.init)) -} > SRAM_C_MEM0_BASEADDR - -.fini : { - KEEP (*(.fini)) -} > SRAM_C_MEM0_BASEADDR - -.rodata : { - __rodata_start = .; - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - __rodata_end = .; -} > SRAM_C_MEM0_BASEADDR - -.sdata2 : { - __sdata2_start = .; - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - __sdata2_end = .; -} > SRAM_C_MEM0_BASEADDR - -.sbss2 : { - __sbss2_start = .; - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - __sbss2_end = .; -} > SRAM_C_MEM0_BASEADDR - -.data : { - __data_start = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - __data_end = .; -} > SRAM_C_MEM0_BASEADDR - -.got : { - *(.got) -} > SRAM_C_MEM0_BASEADDR - -.got1 : { - *(.got1) -} > SRAM_C_MEM0_BASEADDR - -.got2 : { - *(.got2) -} > SRAM_C_MEM0_BASEADDR - -.ctors : { - __CTOR_LIST__ = .; - ___CTORS_LIST___ = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - ___CTORS_END___ = .; -} > SRAM_C_MEM0_BASEADDR - -.dtors : { - __DTOR_LIST__ = .; - ___DTORS_LIST___ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - ___DTORS_END___ = .; -} > SRAM_C_MEM0_BASEADDR - -.fixup : { - __fixup_start = .; - *(.fixup) - __fixup_end = .; -} > SRAM_C_MEM0_BASEADDR - -.eh_frame : { - *(.eh_frame) -} > SRAM_C_MEM0_BASEADDR - -.jcr : { - *(.jcr) -} > SRAM_C_MEM0_BASEADDR - -.gcc_except_table : { - *(.gcc_except_table) -} > SRAM_C_MEM0_BASEADDR - -.sdata : { - __sdata_start = .; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - __sdata_end = .; -} > SRAM_C_MEM0_BASEADDR - -.sbss : { - __sbss_start = .; - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - __sbss_end = .; -} > SRAM_C_MEM0_BASEADDR - -.tdata : { - __tdata_start = .; - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - __tdata_end = .; -} > SRAM_C_MEM0_BASEADDR - -.tbss : { - __tbss_start = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - __tbss_end = .; -} > SRAM_C_MEM0_BASEADDR - -.bss : { - __bss_start = .; - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - __bss_end = .; -} > SRAM_C_MEM0_BASEADDR - -.boot0 0xFFFFFFEC : { - __boot0_start = .; - *(.boot0) - __boot0_end = .; -} - -.boot 0xFFFFFFFC : { - __boot_start = .; - *(.boot) - __boot_end = .; -} - -/* Generate Stack and Heap Sections */ - -.stack : { - _stack_end = .; - . += _STACK_SIZE; - . = ALIGN(16); - __stack = .; -} > SRAM_C_MEM0_BASEADDR - -.heap : { - . = ALIGN(16); - _heap_start = .; - . += _HEAP_SIZE; - . = ALIGN(16); - _heap_end = .; - _end = .; -} > SRAM_C_MEM0_BASEADDR - -} - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.c b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.c deleted file mode 100644 index 1d2d19d32..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * Tests the floating point context save and restore mechanism. - * - * Two tasks are created - each of which is allocated a buffer of - * portNO_FLOP_REGISTERS_TO_SAVE 32bit variables into which the flop context - * of the task is saved when the task is switched out, and from which the - * flop context of the task is restored when the task is switch in. Prior to - * the tasks being created each position in the two buffers is filled with a - * unique value - this way the flop context of each task is different. - * - * The two test tasks never block so are always in either the Running or - * Ready state. They execute at the lowest priority so will get pre-empted - * regularly, although the yield frequently so will not get much execution - * time. The lack of execution time is not a problem as its only the - * switching in and out that is being tested. - * - * Whenever a task is moved from the Ready to the Running state its flop - * context will be loaded from the buffer, but while the task is in the - * Running state the buffer is not used and can contain any value - in this - * case and for test purposes the task itself clears the buffer to zero. - * The next time the task is moved out of the Running state into the - * Ready state the flop context will once more get saved to the buffer - - * overwriting the zeros. - * - * Therefore whenever the task is not in the Running state its buffer contains - * the most recent values of its floating point registers - the zeroing out - * of the buffer while the task was executing being used to ensure the values - * the buffer contains are not stale. - * - * When neither test task is in the Running state the buffers should contain - * the unique values allocated before the tasks were created. If so then - * the floating point context has been maintained. This check is performed - * by the 'check' task (defined in main.c) by calling - * xAreFlopRegisterTestsStillRunning(). - * - * The test tasks also increment a value each time they execute. - * xAreFlopRegisterTestsStillRunning() also checks that this value has changed - * since it last ran to ensure the test tasks are still getting processing time. - */ - -/* Standard includes files. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/*-----------------------------------------------------------*/ - -#define flopNUMBER_OF_TASKS 2 -#define flopSTART_VALUE ( 0x1 ) - -/*-----------------------------------------------------------*/ - -/* The two test tasks as described at the top of this file. */ -static void vFlopTest1( void *pvParameters ); -static void vFlopTest2( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* Buffers into which the flop registers will be saved. There is a buffer for -both tasks. */ -static volatile unsigned long ulFlopRegisters[ flopNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ]; - -/* Variables that are incremented by the tasks to indicate that they are still -running. */ -static volatile unsigned long ulFlop1CycleCount = 0, ulFlop2CycleCount = 0; - -/*-----------------------------------------------------------*/ - -void vStartFlopRegTests( void ) -{ -TaskHandle_t xTaskJustCreated; -unsigned portBASE_TYPE x, y, z = flopSTART_VALUE; - - /* Fill the arrays into which the flop registers are to be saved with - known values. These are the values that will be written to the flop - registers when the tasks start, and as the tasks do not perform any - flop operations the values should never change. Each position in the - buffer contains a different value so the flop context of each task - will be different. */ - for( x = 0; x < flopNUMBER_OF_TASKS; x++ ) - { - for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1); y++ ) - { - ulFlopRegisters[ x ][ y ] = z; - z++; - } - } - - - /* Create the first task. */ - xTaskCreate( vFlopTest1, "flop1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated ); - - /* The task tag value is a value that can be associated with a task, but - is not used by the scheduler itself. Its use is down to the application so - it makes a convenient place in this case to store the pointer to the buffer - into which the flop context of the task will be stored. The first created - task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ]. */ - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) ); - - /* Do the same for the second task. */ - xTaskCreate( vFlopTest2, "flop2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) ); -} -/*-----------------------------------------------------------*/ - -static void vFlopTest1( void *pvParameters ) -{ - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - for( ;; ) - { - /* The values from the buffer should have now been written to the flop - registers. Clear the buffer to ensure the same values then get written - back the next time the task runs. Being preempted during this memset - could cause the test to fail, hence the critical section. */ - portENTER_CRITICAL(); - memset( ( void * ) ulFlopRegisters[ 0 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) ); - portEXIT_CRITICAL(); - - /* We don't have to do anything other than indicate that we are - still running. */ - ulFlop1CycleCount++; - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -static void vFlopTest2( void *pvParameters ) -{ - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - for( ;; ) - { - /* The values from the buffer should have now been written to the flop - registers. Clear the buffer to ensure the same values then get written - back the next time the task runs. */ - portENTER_CRITICAL(); - memset( ( void * ) ulFlopRegisters[ 1 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) ); - portEXIT_CRITICAL(); - - /* We don't have to do anything other than indicate that we are - still running. */ - ulFlop2CycleCount++; - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xAreFlopRegisterTestsStillRunning( void ) -{ -portBASE_TYPE xReturn = pdPASS; -unsigned portBASE_TYPE x, y, z = flopSTART_VALUE; -static unsigned long ulLastFlop1CycleCount = 0, ulLastFlop2CycleCount = 0; - - /* Called from the 'check' task. - - The flop tasks cannot be currently running, check their saved registers - are as expected. The tests tasks do not perform any flop operations so - their registers should be as per their initial setting. */ - for( x = 0; x < flopNUMBER_OF_TASKS; x++ ) - { - for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ ) - { - if( ulFlopRegisters[ x ][ y ] != z ) - { - xReturn = pdFAIL; - break; - } - - z++; - } - } - - /* Check both tasks have actually been swapped in and out since this function - last executed. */ - if( ulFlop1CycleCount == ulLastFlop1CycleCount ) - { - xReturn = pdFAIL; - } - - if( ulFlop2CycleCount == ulLastFlop2CycleCount ) - { - xReturn = pdFAIL; - } - - ulLastFlop1CycleCount = ulFlop1CycleCount; - ulLastFlop2CycleCount = ulFlop2CycleCount; - - return xReturn; -} - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.h b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.h deleted file mode 100644 index ee587f0c5..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#ifndef FLOP_REG_TEST_H -#define FLOP_REG_TEST_H - -void vStartFlopRegTests( void ); -portBASE_TYPE xAreFlopRegisterTestsStillRunning( void ); - -#endif diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop.c b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop.c deleted file mode 100644 index 32b4485e5..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop.c +++ /dev/null @@ -1,420 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * Creates eight tasks, each of which loops continuously performing a - * floating point calculation. - * - * All the tasks run at the idle priority and never block or yield. This causes - * all eight tasks to time slice with the idle task. Running at the idle priority - * means that these tasks will get pre-empted any time another task is ready to run - * or a time slice occurs. More often than not the pre-emption will occur mid - * calculation, creating a good test of the schedulers context switch mechanism - a - * calculation producing an unexpected result could be a symptom of a corruption in - * the context of a task. - * - * This file demonstrates the use of the task tag and traceTASK_SWITCHED_IN and - * traceTASK_SWITCHED_OUT macros to save and restore the floating point context. - */ - -#include -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "flop.h" - -/* Misc. definitions. */ -#define mathSTACK_SIZE configMINIMAL_STACK_SIZE -#define mathNUMBER_OF_TASKS ( 8 ) - -/* Four tasks, each of which performs a different floating point calculation. -Each of the four is created twice. */ -static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); -static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); -static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); -static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); - -/* These variables are used to check that all the tasks are still running. If a -task gets a calculation wrong it will stop incrementing its check variable. */ -static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; - -/* Buffers into which the flop registers will be saved. There is a buffer for -each task created within this file. Zeroing out this array is the normal and -safe option as this will cause the task to start with all zeros in its flop -context. */ -static unsigned long ulFlopRegisters[ mathNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ]; - -/*-----------------------------------------------------------*/ - -void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) -{ -TaskHandle_t xTaskJustCreated; -portBASE_TYPE x, y; - - /* Place known values into the buffers into which the flop registers are - to be saved. This is for debug purposes only, it is not normally - required. The last position in each array is left at zero as the status - register will be loaded from there. - - It is intended that these values can be viewed being loaded into the - flop registers when a task is started - however the Insight debugger - does not seem to want to show the flop register values. */ - for( x = 0; x < mathNUMBER_OF_TASKS; x++ ) - { - for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ ) - { - ulFlopRegisters[ x ][ y ] = ( x + 1 ); - } - } - - /* Create the first task - passing it the address of the check variable - that it is going to increment. This check variable is used as an - indication that the task is still running. */ - xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, &xTaskJustCreated ); - - /* The task tag value is a value that can be associated with a task, but - is not used by the scheduler itself. Its use is down to the application so - it makes a convenient place in this case to store the pointer to the buffer - into which the flop context of the task will be stored. The first created - task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ], etc. */ - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) ); - - /* Create another 7 tasks, allocating a buffer for each. */ - xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 2 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 3 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 4 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 5 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 6 ][ 0 ] ) ); - - xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, &xTaskJustCreated ); - vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 7 ][ 0 ] ) ); -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) -{ -volatile portFLOAT ff1, ff2, ff3, ff4; -volatile unsigned short *pusTaskCheckVariable; -volatile portFLOAT fAnswer; -short sError = pdFALSE; - - ff1 = 123.4567F; - ff2 = 2345.6789F; - ff3 = -918.222F; - - fAnswer = ( ff1 + ff2 ) * ff3; - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned short * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for(;;) - { - ff1 = 123.4567F; - ff2 = 2345.6789F; - ff3 = -918.222F; - - ff4 = ( ff1 + ff2 ) * ff3; - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( fabs( ff4 - fAnswer ) > 0.001F ) - { - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) -{ -volatile portFLOAT ff1, ff2, ff3, ff4; -volatile unsigned short *pusTaskCheckVariable; -volatile portFLOAT fAnswer; -short sError = pdFALSE; - - ff1 = -389.38F; - ff2 = 32498.2F; - ff3 = -2.0001F; - - fAnswer = ( ff1 / ff2 ) * ff3; - - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned short * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for( ;; ) - { - ff1 = -389.38F; - ff2 = 32498.2F; - ff3 = -2.0001F; - - ff4 = ( ff1 / ff2 ) * ff3; - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( fabs( ff4 - fAnswer ) > 0.001F ) - { - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know - this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) -{ -volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference; -volatile unsigned short *pusTaskCheckVariable; -const size_t xArraySize = 10; -size_t xPosition; -short sError = pdFALSE; - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned short * ) pvParameters; - - pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) ); - - /* Keep filling an array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - fTotal1 = 0.0F; - fTotal2 = 0.0F; - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - pfArray[ xPosition ] = ( portFLOAT ) xPosition + 5.5F; - fTotal1 += ( portFLOAT ) xPosition + 5.5F; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - fTotal2 += pfArray[ xPosition ]; - } - - fDifference = fTotal1 - fTotal2; - if( fabs( fDifference ) > 0.001F ) - { - sError = pdTRUE; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) -{ -volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference; -volatile unsigned short *pusTaskCheckVariable; -const size_t xArraySize = 10; -size_t xPosition; -short sError = pdFALSE; - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned short * ) pvParameters; - - pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) ); - - /* Keep filling an array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - fTotal1 = 0.0F; - fTotal2 = 0.0F; - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - pfArray[ xPosition ] = ( portFLOAT ) xPosition * 12.123F; - fTotal1 += ( portFLOAT ) xPosition * 12.123F; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - fTotal2 += pfArray[ xPosition ]; - } - - fDifference = fTotal1 - fTotal2; - if( fabs( fDifference ) > 0.001F ) - { - sError = pdTRUE; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreMathsTaskStillRunning( void ) -{ -/* Keep a history of the check variables so we know if they have been incremented -since the last call. */ -static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; -portBASE_TYPE xReturn = pdTRUE, xTask; - - /* Check the maths tasks are still running by ensuring their check variables - are still incrementing. */ - for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) - { - if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) - { - /* The check has not incremented so an error exists. */ - xReturn = pdFALSE; - } - - usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; - } - - return xReturn; -} - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/main.c b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/main.c deleted file mode 100644 index 4b002dd3e..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/main.c +++ /dev/null @@ -1,725 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * In addition to the standard demo tasks, the follow demo specific tasks are - * create: - * - * The "Check" task. This only executes every three seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the other tasks are still operational. Most tasks maintain - * a unique count that is incremented each time the task successfully completes - * its function. Should any error occur within such a task the count is - * permanently halted. The check task inspects the count of each task to ensure - * it has changed since the last time the check task executed. If all the count - * variables have changed all the tasks are still executing error free, and the - * check task toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - * The "Register Check" tasks. These tasks fill the CPU registers with known - * values, then check that each register still contains the expected value, the - * discovery of an unexpected value being indicative of an error in the RTOS - * context switch mechanism. The register check tasks operate at low priority - * so are switched in and out frequently. - * - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Xilinx library includes. */ -#include "xcache_l.h" -#include "xintc.h" - -/* Demo application includes. */ -#include "flash.h" -#include "integer.h" -#include "comtest2.h" -#include "semtest.h" -#include "BlockQ.h" -#include "dynamic.h" -#include "GenQTest.h" -#include "QPeek.h" -#include "blocktim.h" -#include "death.h" -#include "partest.h" -#include "countsem.h" -#include "recmutex.h" -#include "flop.h" -#include "flop-reg-test.h" - -/* Priorities assigned to the demo tasks. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainFLOP_PRIORITY ( tskIDLE_PRIORITY ) - -/* The first LED used by the COM test and check tasks respectively. */ -#define mainCOM_TEST_LED ( 4 ) -#define mainCHECK_TEST_LED ( 3 ) - -/* The baud rate used by the comtest tasks is set by the hardware, so the -baud rate parameters passed into the comtest initialisation has no effect. */ -#define mainBAUD_SET_IN_HARDWARE ( 0 ) - -/* Delay periods used by the check task. If no errors have been found then -the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an -error has been found at any time then the toggle rate will increase to -mainERROR_CHECK_DELAY milliseconds. */ -#define mainNO_ERROR_CHECK_DELAY ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_CHECK_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) - - -/* - * The tasks defined within this file - described within the comments at the - * head of this page. - */ -static void prvRegTestTask1( void *pvParameters ); -static void prvRegTestTask2( void *pvParameters ); -static void prvErrorChecks( void *pvParameters ); - -/* - * Called by the 'check' task to inspect all the standard demo tasks within - * the system, as described within the comments at the head of this page. - */ -static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); - -/* - * Perform any hardware initialisation required by the demo application. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* xRegTestStatus will get set to pdFAIL by the regtest tasks if they -discover an unexpected value. */ -static volatile unsigned portBASE_TYPE xRegTestStatus = pdPASS; - -/* Counters used to ensure the regtest tasks are still running. */ -static volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - - /* Must be called prior to installing any interrupt handlers! */ - vPortSetupInterruptController(); - - /* In this case prvSetupHardware() just enables the caches and and - configures the IO ports for the LED outputs. */ - prvSetupHardware(); - - /* Start the standard demo application tasks. Note that the baud rate used - by the comtest tasks is set by the hardware, so the baud rate parameter - passed has no effect. */ - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); - vStartQueuePeekTasks(); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartRecursiveMutexTasks(); - - #if ( configUSE_FPU == 1 ) - { - /* A different project is provided that has configUSE_FPU set to 1 - in order to demonstrate all the settings required to use the floating - point unit. If you wish to use the floating point unit do not start - with this project. */ - vStartMathTasks( mainFLOP_PRIORITY ); - vStartFlopRegTests(); - } - #endif - - /* Create the tasks defined within this file. */ - xTaskCreate( prvRegTestTask1, "Regtest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTestTask2, "Regtest2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* The suicide tasks must be started last as they record the number of other - tasks that exist within the system. The value is then used to ensure at run - time the number of tasks that exists is within expected bounds. */ - vCreateSuicidalTasks( mainDEATH_PRIORITY ); - - /* Now start the scheduler. Following this call the created tasks should - be executing. */ - vTaskStartScheduler(); - - /* vTaskStartScheduler() will only return if an error occurs while the - idle task is being created. */ - for( ;; ); - - return 0; -} -/*-----------------------------------------------------------*/ - -static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) -{ -portBASE_TYPE lReturn = pdPASS; -static unsigned long ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL; - - /* The demo tasks maintain a count that increments every cycle of the task - provided that the task has never encountered an error. This function - checks the counts maintained by the tasks to ensure they are still being - incremented. A count remaining at the same value between calls therefore - indicates that an error has been detected. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - #if ( configUSE_FPU == 1 ) - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreFlopRegisterTestsStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - #endif - - /* Have the register test tasks found any errors? */ - if( xRegTestStatus != pdPASS ) - { - lReturn = pdFAIL; - } - - /* Are the register test tasks still looping? */ - if( ulLastRegTest1Counter == ulRegTest1Counter ) - { - lReturn = pdFAIL; - } - else - { - ulLastRegTest1Counter = ulRegTest1Counter; - } - - if( ulLastRegTest2Counter == ulRegTest2Counter ) - { - lReturn = pdFAIL; - } - else - { - ulLastRegTest2Counter = ulRegTest2Counter; - } - - return lReturn; -} -/*-----------------------------------------------------------*/ - -static void prvErrorChecks( void *pvParameters ) -{ -TickType_t xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime; -volatile unsigned portBASE_TYPE uxFreeStack; - - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* This call is just to demonstrate the use of the function - nothing is - done with the value. You would expect the stack high water mark to be - lower (the function to return a larger value) here at function entry than - later following calls to other functions. */ - uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Again just for demo purposes - uxFreeStack should have a lower value - here than following the call to uxTaskGetStackHighWaterMark() on the - task entry. */ - uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); - - /* Wait until it is time to check again. The time we wait here depends - on whether an error has been detected or not. When an error is - detected the time is shortened resulting in a faster LED flash rate. */ - vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); - - /* See if the other tasks are all ok. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error occurred in one of the tasks so shorten the delay - period - which has the effect of increasing the frequency of the - LED toggle. */ - xDelayPeriod = mainERROR_CHECK_DELAY; - } - - /* Flash! */ - vParTestToggleLED( mainCHECK_TEST_LED ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - XCache_EnableICache( 0x80000000 ); - XCache_EnableDCache( 0x80000000 ); - - /* Setup the IO port for use with the LED outputs. */ - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -void prvRegTest1Pass( void ) -{ - /* Called from the inline assembler - this cannot be static - otherwise it can get optimised away. */ - ulRegTest1Counter++; -} -/*-----------------------------------------------------------*/ - -void prvRegTest2Pass( void ) -{ - /* Called from the inline assembler - this cannot be static - otherwise it can get optimised away. */ - ulRegTest2Counter++; -} -/*-----------------------------------------------------------*/ - -void prvRegTestFail( void ) -{ - /* Called from the inline assembler - this cannot be static - otherwise it can get optimised away. */ - xRegTestStatus = pdFAIL; -} -/*-----------------------------------------------------------*/ - -static void prvRegTestTask1( void *pvParameters ) -{ - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* The first register test task as described at the top of this file. The - values used in the registers are different to those use in the second - register test task. Also, unlike the second register test task, this task - yields between setting the register values and subsequently checking the - register values. */ - asm volatile - ( - "RegTest1Start: \n\t" \ - " \n\t" \ - " li 0, 301 \n\t" \ - " mtspr 256, 0 #USPRG0 \n\t" \ - " li 0, 501 \n\t" \ - " mtspr 8, 0 #LR \n\t" \ - " li 0, 4 \n\t" \ - " mtspr 1, 0 #XER \n\t" \ - " \n\t" \ - " li 0, 1 \n\t" \ - " li 2, 2 \n\t" \ - " li 3, 3 \n\t" \ - " li 4, 4 \n\t" \ - " li 5, 5 \n\t" \ - " li 6, 6 \n\t" \ - " li 7, 7 \n\t" \ - " li 8, 8 \n\t" \ - " li 9, 9 \n\t" \ - " li 10, 10 \n\t" \ - " li 11, 11 \n\t" \ - " li 12, 12 \n\t" \ - " li 13, 13 \n\t" \ - " li 14, 14 \n\t" \ - " li 15, 15 \n\t" \ - " li 16, 16 \n\t" \ - " li 17, 17 \n\t" \ - " li 18, 18 \n\t" \ - " li 19, 19 \n\t" \ - " li 20, 20 \n\t" \ - " li 21, 21 \n\t" \ - " li 22, 22 \n\t" \ - " li 23, 23 \n\t" \ - " li 24, 24 \n\t" \ - " li 25, 25 \n\t" \ - " li 26, 26 \n\t" \ - " li 27, 27 \n\t" \ - " li 28, 28 \n\t" \ - " li 29, 29 \n\t" \ - " li 30, 30 \n\t" \ - " li 31, 31 \n\t" \ - " \n\t" \ - " sc \n\t" \ - " nop \n\t" \ - " \n\t" \ - " cmpwi 0, 1 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 2, 2 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 3, 3 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 4, 4 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 5, 5 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 6, 6 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 7, 7 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 8, 8 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 9, 9 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 10, 10 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 11, 11 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 12, 12 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 13, 13 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 14, 14 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 15, 15 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 16, 16 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 17, 17 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 18, 18 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 19, 19 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 20, 20 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 21, 21 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 22, 22 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 23, 23 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 24, 24 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 25, 25 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 26, 26 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 27, 27 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 28, 28 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 29, 29 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 30, 30 \n\t" \ - " bne RegTest1Fail \n\t" \ - " cmpwi 31, 31 \n\t" \ - " bne RegTest1Fail \n\t" \ - " \n\t" \ - " mfspr 0, 256 #USPRG0 \n\t" \ - " cmpwi 0, 301 \n\t" \ - " bne RegTest1Fail \n\t" \ - " mfspr 0, 8 #LR \n\t" \ - " cmpwi 0, 501 \n\t" \ - " bne RegTest1Fail \n\t" \ - " mfspr 0, 1 #XER \n\t" \ - " cmpwi 0, 4 \n\t" \ - " bne RegTest1Fail \n\t" \ - " \n\t" \ - " bl prvRegTest1Pass \n\t" \ - " b RegTest1Start \n\t" \ - " \n\t" \ - "RegTest1Fail: \n\t" \ - " \n\t" \ - " \n\t" \ - " bl prvRegTestFail \n\t" \ - " b RegTest1Start \n\t" \ - ); -} -/*-----------------------------------------------------------*/ - -static void prvRegTestTask2( void *pvParameters ) -{ - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* The second register test task as described at the top of this file. - Note that this task fills the registers with different values to the - first register test task. */ - asm volatile - ( - "RegTest2Start: \n\t" \ - " \n\t" \ - " li 0, 300 \n\t" \ - " mtspr 256, 0 #USPRG0 \n\t" \ - " li 0, 500 \n\t" \ - " mtspr 8, 0 #LR \n\t" \ - " li 0, 4 \n\t" \ - " mtspr 1, 0 #XER \n\t" \ - " \n\t" \ - " li 0, 11 \n\t" \ - " li 2, 12 \n\t" \ - " li 3, 13 \n\t" \ - " li 4, 14 \n\t" \ - " li 5, 15 \n\t" \ - " li 6, 16 \n\t" \ - " li 7, 17 \n\t" \ - " li 8, 18 \n\t" \ - " li 9, 19 \n\t" \ - " li 10, 110 \n\t" \ - " li 11, 111 \n\t" \ - " li 12, 112 \n\t" \ - " li 13, 113 \n\t" \ - " li 14, 114 \n\t" \ - " li 15, 115 \n\t" \ - " li 16, 116 \n\t" \ - " li 17, 117 \n\t" \ - " li 18, 118 \n\t" \ - " li 19, 119 \n\t" \ - " li 20, 120 \n\t" \ - " li 21, 121 \n\t" \ - " li 22, 122 \n\t" \ - " li 23, 123 \n\t" \ - " li 24, 124 \n\t" \ - " li 25, 125 \n\t" \ - " li 26, 126 \n\t" \ - " li 27, 127 \n\t" \ - " li 28, 128 \n\t" \ - " li 29, 129 \n\t" \ - " li 30, 130 \n\t" \ - " li 31, 131 \n\t" \ - " \n\t" \ - " cmpwi 0, 11 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 2, 12 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 3, 13 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 4, 14 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 5, 15 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 6, 16 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 7, 17 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 8, 18 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 9, 19 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 10, 110 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 11, 111 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 12, 112 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 13, 113 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 14, 114 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 15, 115 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 16, 116 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 17, 117 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 18, 118 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 19, 119 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 20, 120 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 21, 121 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 22, 122 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 23, 123 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 24, 124 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 25, 125 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 26, 126 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 27, 127 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 28, 128 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 29, 129 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 30, 130 \n\t" \ - " bne RegTest2Fail \n\t" \ - " cmpwi 31, 131 \n\t" \ - " bne RegTest2Fail \n\t" \ - " \n\t" \ - " mfspr 0, 256 #USPRG0 \n\t" \ - " cmpwi 0, 300 \n\t" \ - " bne RegTest2Fail \n\t" \ - " mfspr 0, 8 #LR \n\t" \ - " cmpwi 0, 500 \n\t" \ - " bne RegTest2Fail \n\t" \ - " mfspr 0, 1 #XER \n\t" \ - " cmpwi 0, 4 \n\t" \ - " bne RegTest2Fail \n\t" \ - " \n\t" \ - " bl prvRegTest2Pass \n\t" \ - " b RegTest2Start \n\t" \ - " \n\t" \ - "RegTest2Fail: \n\t" \ - " \n\t" \ - " \n\t" \ - " bl prvRegTestFail \n\t" \ - " b RegTest2Start \n\t" \ - ); -} -/*-----------------------------------------------------------*/ - -/* This hook function will get called if there is a suspected stack overflow. -An overflow can cause the task name to be corrupted, in which case the task -handle needs to be used to determine the offending task. */ -void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName ); -void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName ) -{ -/* To prevent the optimiser removing the variables. */ -volatile TaskHandle_t xTaskIn = xTask; -volatile signed char *pcTaskNameIn = pcTaskName; - - /* Remove compiler warnings. */ - ( void ) xTaskIn; - ( void ) pcTaskNameIn; - - /* The following three calls are simply to stop compiler warnings about the - functions not being used - they are called from the inline assembly. */ - prvRegTest1Pass(); - prvRegTest2Pass(); - prvRegTestFail(); - - for( ;; ); -} - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c deleted file mode 100644 index 6311f14f6..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Demo application includes. */ -#include "partest.h" - -/* Library includes. */ -#include "xparameters.h" -#include "xgpio_l.h" - -/* Misc hardware specific definitions. */ -#define partstALL_AS_OUTPUT 0x00 -#define partstCHANNEL_1 0x01 -#define partstMAX_4BIT_LED 0x03 - -/* The outputs are split into two IO sections, these variables maintain the -current value of either section. */ -static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit; - -/*-----------------------------------------------------------*/ -/* - * Setup the IO for the LED outputs. - */ -void vParTestInitialise( void ) -{ - /* Set both sets of LED's on the demo board to outputs. */ - XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); - XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); - - /* Start with all outputs off. */ - uxCurrentOutput4Bit = 0; - XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 ); - uxCurrentOutput5Bit = 0; - XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; - - portENTER_CRITICAL(); - { - /* Which IO section does the LED being set/cleared belong to? The - 4 bit or 5 bit outputs? */ - if( uxLED <= partstMAX_4BIT_LED ) - { - uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; - puxCurrentValue = &uxCurrentOutput5Bit; - } - else - { - uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; - puxCurrentValue = &uxCurrentOutput4Bit; - uxLED -= partstMAX_4BIT_LED; - } - - /* Setup the bit mask accordingly. */ - uxLED = 0x01 << uxLED; - - /* Maintain the current output value. */ - if( xValue ) - { - *puxCurrentValue |= uxLED; - } - else - { - *puxCurrentValue &= ~uxLED; - } - - /* Write the value to the port. */ - XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; - - portENTER_CRITICAL(); - { - /* Which IO section does the LED being toggled belong to? The - 4 bit or 5 bit outputs? */ - if( uxLED <= partstMAX_4BIT_LED ) - { - - uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; - puxCurrentValue = &uxCurrentOutput5Bit; - } - else - { - uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; - puxCurrentValue = &uxCurrentOutput4Bit; - uxLED -= partstMAX_4BIT_LED; - } - - /* Setup the bit mask accordingly. */ - uxLED = 0x01 << uxLED; - - /* Maintain the current output value. */ - if( *puxCurrentValue & uxLED ) - { - *puxCurrentValue &= ~uxLED; - } - else - { - *puxCurrentValue |= uxLED; - } - - /* Write the value to the port. */ - XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); - } - portEXIT_CRITICAL(); -} - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c deleted file mode 100644 index 5e390a62a..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" - -/* Library includes. */ -#include "xparameters.h" -#include "xuartlite.h" -#include "xuartlite_l.h" - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static QueueHandle_t xRxedChars; -static QueueHandle_t xCharsForTx; - -/* Structure that maintains information on the UART being used. */ -static XUartLite xUART; - -/* - * Sample UART interrupt handler. Note this is used to demonstrate the kernel - * features and test the port - it is not intended to represent an efficient - * implementation. - */ -static void vSerialISR( XUartLite *pxUART ); - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ - /* NOTE: The baud rate used by this driver is determined by the hardware - parameterization of the UART Lite peripheral, and the baud value passed to - this function has no effect. */ - ( void ) ulWantedBaud; - - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) ); - - /* Only initialise the UART if the queues were created correctly. */ - if( ( xRxedChars != NULL ) && ( xCharsForTx != NULL ) ) - { - - XUartLite_Initialize( &xUART, XPAR_RS232_UART_DEVICE_ID ); - XUartLite_ResetFifos( &xUART ); - XUartLite_DisableInterrupt( &xUART ); - - if( xPortInstallInterruptHandler( XPAR_XPS_INTC_0_RS232_UART_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS ) - { - /* xPortInstallInterruptHandler() could fail if - vPortSetupInterruptController() has not been called prior to this - function. */ - XUartLite_EnableInterrupt( &xUART ); - } - } - - /* There is only one port so the handle is not used. */ - return ( xComPortHandle ) 0; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime ) -{ - /* The port handle is not required as this driver only supports one UART. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime ) -{ -portBASE_TYPE xReturn = pdTRUE; - - /* Just to remove compiler warning. */ - ( void ) pxPort; - - portENTER_CRITICAL(); - { - /* If the UART FIFO is full we can block posting the new data on the - Tx queue. */ - if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) ) - { - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - xReturn = pdFAIL; - } - } - /* Otherwise, if there is data already in the queue we should add the - new data to the back of the queue to ensure the sequencing is - maintained. */ - else if( uxQueueMessagesWaiting( xCharsForTx ) ) - { - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - xReturn = pdFAIL; - } - } - /* If the UART FIFO is not full and there is no data already in the - queue we can write directly to the FIFO without disrupting the - sequence. */ - else - { - XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar ); - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ - ( void ) xPort; -} -/*-----------------------------------------------------------*/ - -static void vSerialISR( XUartLite *pxUART ) -{ -unsigned long ulISRStatus; -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, lDidSomething; -char cChar; - - /* Just to remove compiler warning. */ - ( void ) pxUART; - - do - { - lDidSomething = pdFALSE; - - ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); - - if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 ) - { - /* A character is available - place it in the queue of received - characters. This might wake a task that was blocked waiting for - data. */ - cChar = ( char ) XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET ); - xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken ); - lDidSomething = pdTRUE; - } - - if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 ) - { - /* There is space in the FIFO - if there are any characters queue for - transmission they can be sent to the UART now. This might unblock a - task that was waiting for space to become available on the Tx queue. */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE ) - { - XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar ); - lDidSomething = pdTRUE; - } - } - } while( lDidSomething == pdTRUE ); - - /* If we woke any tasks we may require a context switch. */ - if( xHigherPriorityTaskWoken ) - { - portYIELD_FROM_ISR(); - } -} - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/ReadMe.txt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/ReadMe.txt new file mode 100644 index 000000000..ad84b2770 --- /dev/null +++ b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/ReadMe.txt @@ -0,0 +1,3 @@ +If you need the demo that used to be in this directory then download FreeRTOS V8.2.3 +from http://sourceforge.net/projects/freertos/files/FreeRTOS/ + diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_BifShapes.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_BifShapes.xsl deleted file mode 100644 index e3f4c3fbc..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_BifShapes.xsl +++ /dev/null @@ -1,211 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Colors.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Colors.xsl deleted file mode 100644 index a4efce5f4..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Colors.xsl +++ /dev/null @@ -1,134 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Diagrams.css b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Diagrams.css deleted file mode 100644 index bde7995d7..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_Diagrams.css +++ /dev/null @@ -1,329 +0,0 @@ - text.busintlabel { - fill: #810017; - stroke: none; - font-size: 7pt; - font-style: italic; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mpmctitle { - fill: #FFFFFF; - stroke: none; - font-size: 16pt; - font-weight: bold; - text-anchor: middle; - font-family: Arial Verdana Helvetica sans-serif; - } - - text.mpmcbiflabel { - fill: #FFFFFF; - stroke: none; - font-size: 6pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - - } - - text.buslabel { - fill: #CC3333; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.iplabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: 800; - text-anchor: middle; - font-family: Courier Arial Helvetica sans-serif; - } - - text.iptype { - fill: #AA0017; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.ipclass { - fill: #000000; - stroke: none; - font-size: 7pt; - font-style: normal; - font-weight: bold; - text-anchor: start; - font-family: Times Arial Helvetica sans-serif; - } - - text.procclass { - fill: #000000; - stroke: none; - font-size: 7pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Times Arial Helvetica sans-serif; - } - - - text.portlabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.ipdbiflbl { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: bold; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mmMHeader { - fill: #FFFFFF; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mmSHeader { - fill: #810017; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - - - text.dbglabel { - fill: #555555; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Times Arial Helvetica sans-serif; - } - - text.iopnumb { - fill: #555555; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.ioplblgrp { - fill: #000088; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - - tspan.iopgrp { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - baseline-shift:super; - font-family: Arial Courier san-serif; - } - - - text.biflabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - - } - - text.p2pbuslabel { - fill: #000000; - stroke: none; - font-size: 10pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - writing-mode: tb; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mpbuslabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - writing-mode: tb; - font-family: Verdana Arial Helvetica sans-serif; - } - - - text.sharedbuslabel { - fill: #000000; - stroke: none; - font-size: 10pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - - text.bciplabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Courier Arial Helvetica sans-serif; - } - - text.bciptype { - fill: #AA0017; - stroke: none; - font-size: 6pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.splitbustxt { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: sans-serif; - } - - text.horizp2pbuslabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - - - text.keytitle { - fill: #AA0017; - stroke: none; - font-size: 12pt; - font-weight: bold; - text-anchor: middle; - font-family: Arial Helvetica sans-serif; - } - - text.keyheader { - fill: #000000; - stroke: none; - font-size: 10pt; - font-weight: bold; - text-anchor: middle; - font-family: Arial Helvetica sans-serif; - } - - text.keylabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.keylblul { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - text-decoration: underline; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.specsheader { - fill: #000000; - stroke: none; - font-size: 10pt; - font-weight: bold; - text-anchor: start; - font-family: Arial Helvetica sans-serif; - } - - text.specsvalue { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.specsvaluemid { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.intrsymbol { - fill: #000000; - stroke: none; - font-size: 8pt; - font-weight: bold; - text-anchor: start; - font-family: Arial Helvetica sans-serif; - } - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_BusLaneSpaces.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_BusLaneSpaces.xsl deleted file mode 100644 index 90ba612d4..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_BusLaneSpaces.xsl +++ /dev/null @@ -1,2774 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NONE - - - - - - - - NONE - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _unknown_ - - - - - - - - - - - - - - - _unknown_ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NONE - - - - - - - - NONE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Busses.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Busses.xsl deleted file mode 100644 index 41a472e2e..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Busses.xsl +++ /dev/null @@ -1,495 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BusArrowInitiator - BusArrowSouth - - - - - - BusArrowInitiator - BusArrowNorth - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BusArrowHInitiator - BusArrowWest - - - - - - BusArrowHInitiator - BusArrowEast - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BusArrowHInitiator - BusArrowEast - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Calculations.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Calculations.xsl deleted file mode 100644 index fcff09061..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Calculations.xsl +++ /dev/null @@ -1,1080 +0,0 @@ - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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0 - - - - - - - - - -2 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - O - B - I - - - - - - W - S - E - N - D - - - - - - - - - - 0 - - - - - - - - - - 0 - - - - - - - - - - 0 - - - - - - - 0 - -90 - 180 - 90 - - 180 - 90 - 0 - -90 - - 0 - 0 - 0 - 0 - 0 - - - - - - -14 - 8 - - 8 - 0 - - - - - - - - - -2 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Main.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Main.xsl deleted file mode 100644 index 55c9b85f6..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Main.xsl +++ /dev/null @@ -1,1391 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - 0 - - - - 0 - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - Generating Blkdiagram in TestMode - - - - - - - - - - - - - -href="" type="text/css" - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - 0> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NONE - - - - - - - - NONE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IP - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - x - - - - - - - - - - - x - - - - - - - - y - - x - - - - - - - - - KEY - - - - SYMBOLS - - - bus interface - - - shared bus - - Bus connections - - - master or initiator - - - slave or target - - - master slave - - - monitor - - External Ports - - - input - - - output - - - inout - - - Interrupts - - - interrupt - controller - - - - interrupted - processor - - - - interrupt - source - - x = controller ID - - y = priority - - - - COLORS - - - Bus Standards - - - - - - - - - DCR - - - - - - - - - FCB - - - - - - - - - FSL - - - - - - - - - LMB - - - - - - - - - - OPB - - - - - - - - - PLB - - - - - - - - - - SOCM - - - - - - - - - - XIL (prefix) P2P - - - - - - - - - - GEN. P2P, USER, etc - - - - - - - - - - - - - - - - - SPECS - - - - EDK VERSION - - - - - - - ARCH - - - - - - - PART - - - - - - - GENERATED - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Peripherals.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Peripherals.xsl deleted file mode 100644 index 7498fe387..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Peripherals.xsl +++ /dev/null @@ -1,1499 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - unkmodule__ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - symbol_ - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 'UNK' - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MPMC Module Interface - - - - - - - - - - - - - - - - - - - - - - - - - - - 4.5 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - -symbol_STACK_ - - - - -symbol_GROUP_ - - - -symbol_SPACE_WEST__EAST_ -symbol_STACK_ -symbol_STACK__SHAPE_ - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Processors.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Processors.xsl deleted file mode 100644 index 9e35694e5..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSvgBLKD_Processors.xsl +++ /dev/null @@ -1,390 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SLAVES OF - - - - - - - - - - - - - - - - - - - - - - - - PROCESSOR - - - - USER MODULE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - "_no_interrupt_cntlr_" - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css deleted file mode 100644 index c1b40cf88..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css +++ /dev/null @@ -1,119 +0,0 @@ - text.busintlabel { - fill: #810017; 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- 1-800-255-7778 -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TABLE OF CONTENTS
-

- Overview - -

- Block Diagram - -

- External Ports - - - -

- - - Processors - - - Processor - - - - -

-     - -

-           memory map - - - - -

- Debuggers - - -

-     - - - - -

- Interrupt Controllers - - -

-     - - - - -

- Busses - - -

-     - - - - -

- Bridges - - -

-     - - - - -

- Memory - - -

-     - - - - -

- Memory Controllers - - -

-     - - - - -

- Peripherals - - -

-     - - - - -

- IP - - -

-     - - - -

- Timing Information -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- Overview -
- Generated on - - -
- Source - - - - - -
- EDK Version - - - - - - NA - -
- FPGA Family - - - - - - NA - -
- Device - - - - - - - - -
- # IP Instantiated - - -
- # Processors - - -
- # Busses - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
EXTERNAL PORTS
- - These are the external ports defined in the MHS file. - -
- Attributes Key -

- The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file -

- CLK -   indicates Clock ports, (SIGIS = CLK)  -

- INTR -   indicates Interrupt ports,(SIGIS = INTR)  -

- RESET -   indicates Reset ports, (SIGIS = RST)  -

- BUF or REG -   Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- - :1 -  CLK  -  RESET  -  INTR  -  BUF  -  REG  -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- - :1 -  CLK  -  RESET  -  INTR  -  BUF  -  REG  -
- 		-   - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- - :1 -  CLK  -  RESET  -  INTR  -  BUF  -  REG  -
 
- -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Post Synthesis Clock Limits
- - No clocks could be identified in the design. Run platgen to generate synthesis information. - - - - These are the post synthesis clock frequencies. The critical frequencies are marked with - - - green. - -

- - The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system. - -
MODULECLK PortMAX FREQ
- - - - - - - - - - - -
- - - - - - -

-

-

- - - - - - - - -
TOCTOP
- - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl deleted file mode 100644 index 4e7beaa51..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl +++ /dev/null @@ -1,611 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - -    - - -

- - - - - -

-

-

-
- {@INSTANCE} IP Image - - -

-

-
- -
- -

-

- - - - - - - - - - - 1 - 0 - - - - - - - - - - 1 - 0 - - - - - - - 4 - 2 - - - - 2 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
General
IP Core - - - - - - - - - - -
Version
Driver - - API - -
License
TYPE - -
EXPIRES ON - -
Parameters
- - These are parameters set for this module. - - Refer to the IP documentation for complete information about module parameters. - - -

- - Parameters marked with - - yellow - - indicate parameters set by the user. - -

- - Parameters marked with - - blue - - indicate parameters set by the system. - -
NameValue
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
- - - - -
- - - - -
- 		- - -
 
- 		- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
- - - - -
- - - - -
 
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Post Synthesis Device Utilization
- - Device utilization information is not available for this IP. Run platgen to generate synthesis information. - -
Resource TypeUsedAvailablePercent
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NA - - - - - - - - NA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
- - The ports listed here are only those connected in the MHS file. - - Refer to the IP documentation for complete information about module ports. - - -
#NAMEDIR[LSB:MSB]SIGNAL
:1
- Bus Interfaces -
MASTERSHIPNAMESTDBUSP2P
Bus Connections
TYPENAMEBIF
- Interrupt Priorities -
PrioritySIGMODULE
- - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl deleted file mode 100644 index 96e9f0cc7..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl +++ /dev/null @@ -1,86 +0,0 @@ - - - - - -]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ■ -   - - - - - ■ - - -   - - - - - - - - - - - - -
- - MEMORY MAP -
D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE
DIBASEHIGHMODULE
- - : - -
- - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl deleted file mode 100644 index 862b7107b..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl +++ /dev/null @@ -1,235 +0,0 @@ - - - - - - -Table of Contents - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TABLE OF CONTENTS
-

- Overview - -

- Block Diagram - -

- External Ports - -

- - - -
- - Processors  - - - Processor  - - -
- - - - -    

- -           memory map

- - - - - - -
- Debuggers  - -
- - - - -    

- - - - - - -
- Interrupt Controllers  - -
- - - - -    

- - - - - -
- Busses  - -
- - - - -    

- - - - - -
- Bridges  - -
- - - -    

- - - - - -
- Memory  - -
- - - -    

- - - - - -
- Memory Controllers  - -
- - - -    

- - - - - -
- Peripherals  - -
- - - -    

- - - - - -
- IP  - -
- - - -    

- - - - - Timing Information

- - -
- - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd deleted file mode 100644 index 110f5ced5..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd +++ /dev/null @@ -1,1704 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/system_shapes.xml b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/system_shapes.xml deleted file mode 100644 index 1be0a7c85..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/system_shapes.xml +++ /dev/null @@ -1,1643 +0,0 @@ - - - - - - PowerPC 405 Virtex-4 - A wrapper to instantiate the PowerPC 405 Processor Block primitive - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PowerPC JTAG Controller - JTAGPPC wrapper allows the PowerPC to connect to the JTAG chain of the FPGA. - - - - - - - - - - - - - - - - - - - - - - - - Processor Local Bus (PLB) 4.6 - 'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS UART (Lite) - Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus. - - - - - - - - - - - - - - - - - - Serial Data In - - - Serial Data Out - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS General Purpose IO - General Purpose Input/Output (GPIO) core for the PLBV46 bus. - - - - - - - - - - - - - - - - - - - - - - - - GPIO1 Data IO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS General Purpose IO - General Purpose Input/Output (GPIO) core for the PLBV46 bus. - - - - - - - - - - - - - - - - - - - - - - - - GPIO1 Data IO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS System ACE Interface Controller(Compact Flash) - Interface between the PLBV46 and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral - - - - - - - - - - - - - - Clock Input - - - Address Input - - - Data Input/Output - - - Active LOW Chip Enable - - - Active LOW Output Enable - - - Active LOW Write Enable - - - Active high Interrupt Output - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS Multi-Channel External Memory Controller(SRAM/Flash) - Xilinx Multi-CHannel (MCH) PLBV46 external memory controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Memory Address Bus - - - Memory Byte Enable - - - Memory Write Enable - - - Memory Data Bus - - - Memory Output Enable - - - Memory Chip Enable Active Low - - - Memory Advanced Burst Address/Load New Address - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Utility Bus Split - Bus splitting primitive - - - - - - - - - Clock Generator - Clock generator for processor system. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Processor System Reset Module - Reset management module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XPS Interrupt Controller - intc core attached to the PLBV46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/bitinit.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/bitinit.opt deleted file mode 100644 index 3645236a6..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/bitinit.opt +++ /dev/null @@ -1 +0,0 @@ - -pe ppc405_0 $(PPC405_0_BOOTLOOP) diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/libgen.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/libgen.opt deleted file mode 100644 index 77b154845..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/libgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p virtex4 diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/platgen.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/platgen.opt deleted file mode 100644 index 25299b7db..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/platgen.opt +++ /dev/null @@ -1,2 +0,0 @@ - -p xc4vfx12ff668-10 -lang vhdl - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt deleted file mode 100644 index 1f68b9b39..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt +++ /dev/null @@ -1,20 +0,0 @@ -ppc405_0 -RTOSDEMO_SOURCES = RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../Common/Minimal/countsem.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/recmutex.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/flop/flop.c RTOSDemo/flop/flop-reg-test.c -RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h -RTOSDEMO_CC = powerpc-eabi-gcc -RTOSDEMO_CC_SIZE = powerpc-eabi-size -RTOSDEMO_CC_OPT = -O0 -RTOSDEMO_CFLAGS = -I./RTOSDemo/flop -I../../Source/portable/GCC/PPC405_Xilinx -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -Wextra -RTOSDEMO_CC_SEARCH = # -B -RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L -RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ # -I -RTOSDEMO_LFLAGS = # -l -RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo_linker_script.ld -RTOSDEMO_CC_DEBUG_FLAG = -g -RTOSDEMO_CC_PROFILE_FLAG = # -pg -RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi -RTOSDEMO_CC_INFERRED_FLAGS= -RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= -RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= -RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= - $(RTOSDEMO_CC_INFERRED_FLAGS) \ diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/simgen.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/simgen.opt deleted file mode 100644 index cbd523979..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/simgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p virtex4 -lang vhdl -pe ppc405_0 $(PPC405_0_BOOTLOOP) -s mti -X C:/E/temp/rc/3/V5.0.2/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/ -E C:/E/temp/rc/3/V5.0.2/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/ diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system.gui b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system.gui deleted file mode 100644 index 3de5c6af2..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system.gui +++ /dev/null @@ -1,100 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system_routed b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system_routed deleted file mode 100644 index e69de29bb..000000000 diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt deleted file mode 100644 index 39ff0ed04..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt +++ /dev/null @@ -1,20 +0,0 @@ -ppc405_0 -TESTAPP_PERIPHERAL_SOURCES = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xintc_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_selftest_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_intr_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xgpio_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xsysace_selftest_example.c -TESTAPP_PERIPHERAL_HEADERS = /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/intc_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_intr_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/gpio_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/sysace_header.h -TESTAPP_PERIPHERAL_CC = powerpc-eabi-gcc -TESTAPP_PERIPHERAL_CC_SIZE = powerpc-eabi-size -TESTAPP_PERIPHERAL_CC_OPT = -O0 -TESTAPP_PERIPHERAL_CFLAGS = -TESTAPP_PERIPHERAL_CC_SEARCH = # -B -TESTAPP_PERIPHERAL_LIBPATH = -L./ppc405_0/lib/ # -L -TESTAPP_PERIPHERAL_INCLUDES = -I./ppc405_0/include/ -ITestApp_Peripheral/src/ # -I -TESTAPP_PERIPHERAL_LFLAGS = # -l -TESTAPP_PERIPHERAL_LINKER_SCRIPT = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld -TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g -TESTAPP_PERIPHERAL_CC_PROFILE_FLAG = # -pg -TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -msdata=eabi -TESTAPP_PERIPHERAL_CC_INFERRED_FLAGS= -mfpu=sp_full -TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= -TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= -TESTAPP_PERIPHERAL_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= - $(TESTAPP_PERIPHERAL_CC_INFERRED_FLAGS) \ diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/vpgen.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/vpgen.opt deleted file mode 100644 index 8ea8f6640..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/vpgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p xc4vfx12ff668-10 diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xplorer.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xplorer.opt deleted file mode 100644 index 37e5b1190..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xplorer.opt +++ /dev/null @@ -1 +0,0 @@ --device xc4vfx12ff668-10data/system.ucf7 0 diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt deleted file mode 100644 index 33391f035..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt +++ /dev/null @@ -1 +0,0 @@ --device xc4vfx12ff668-10data/system.ucf 0 diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd deleted file mode 100644 index 110f5ced5..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd +++ /dev/null @@ -1,1704 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.css b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.css deleted file mode 100644 index bde7995d7..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.css +++ /dev/null @@ -1,329 +0,0 @@ - text.busintlabel { - fill: #810017; - stroke: none; - font-size: 7pt; - font-style: italic; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mpmctitle { - fill: #FFFFFF; - stroke: none; - font-size: 16pt; - font-weight: bold; - text-anchor: middle; - font-family: Arial Verdana Helvetica sans-serif; - } - - text.mpmcbiflabel { - fill: #FFFFFF; - stroke: none; - font-size: 6pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - - } - - text.buslabel { - fill: #CC3333; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.iplabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: 800; - text-anchor: middle; - font-family: Courier Arial Helvetica sans-serif; - } - - text.iptype { - fill: #AA0017; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.ipclass { - fill: #000000; - stroke: none; - font-size: 7pt; - font-style: normal; - font-weight: bold; - text-anchor: start; - font-family: Times Arial Helvetica sans-serif; - } - - text.procclass { - fill: #000000; - stroke: none; - font-size: 7pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Times Arial Helvetica sans-serif; - } - - - text.portlabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.ipdbiflbl { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: bold; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mmMHeader { - fill: #FFFFFF; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mmSHeader { - fill: #810017; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - - - text.dbglabel { - fill: #555555; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Times Arial Helvetica sans-serif; - } - - text.iopnumb { - fill: #555555; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.ioplblgrp { - fill: #000088; - stroke: none; - font-size: 10pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - - tspan.iopgrp { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - baseline-shift:super; - font-family: Arial Courier san-serif; - } - - - text.biflabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: normal; - font-weight: 900; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - - } - - text.p2pbuslabel { - fill: #000000; - stroke: none; - font-size: 10pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - writing-mode: tb; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.mpbuslabel { - fill: #000000; - stroke: none; - font-size: 6pt; - font-style: italic; - font-weight: bold; - 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} - - - - text.keytitle { - fill: #AA0017; - stroke: none; - font-size: 12pt; - font-weight: bold; - text-anchor: middle; - font-family: Arial Helvetica sans-serif; - } - - text.keyheader { - fill: #000000; - stroke: none; - font-size: 10pt; - font-weight: bold; - text-anchor: middle; - font-family: Arial Helvetica sans-serif; - } - - text.keylabel { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.keylblul { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - text-decoration: underline; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.specsheader { - fill: #000000; - stroke: none; - font-size: 10pt; - font-weight: bold; - text-anchor: start; - font-family: Arial Helvetica sans-serif; - } - - text.specsvalue { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: start; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.specsvaluemid { - fill: #000000; - stroke: none; - font-size: 8pt; - font-style: italic; - font-weight: bold; - text-anchor: middle; - font-family: Verdana Arial Helvetica sans-serif; - } - - text.intrsymbol { - fill: #000000; - stroke: none; - font-size: 8pt; - font-weight: bold; - text-anchor: start; - font-family: Arial Helvetica sans-serif; - } - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.html b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.html deleted file mode 100644 index ba4972b61..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.html +++ /dev/null @@ -1,229 +0,0 @@ - - - -Block Diagram - - -

- - - - - - - - - -
EXTERNAL PORTS
- These are the external ports defined in the MHS file. -
-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- -fpga_0_RS232_Uart_RX_pinI1fpga_0_RS232_Uart_RX
- -fpga_0_RS232_Uart_TX_pinO1fpga_0_RS232_Uart_TX
- -fpga_0_LEDs_4Bit_GPIO_IO_pinIO0:3fpga_0_LEDs_4Bit_GPIO_IO
- -fpga_0_LEDs_Positions_GPIO_IO_pinIO0:4fpga_0_LEDs_Positions_GPIO_IO
- -fpga_0_SysACE_CompactFlash_SysACE_CLK_pinI1fpga_0_SysACE_CompactFlash_SysACE_CLK
- -fpga_0_SysACE_CompactFlash_SysACE_MPA_pinO6:1fpga_0_SysACE_CompactFlash_SysACE_MPA
- -fpga_0_SysACE_CompactFlash_SysACE_MPD_pinIO15:0fpga_0_SysACE_CompactFlash_SysACE_MPD
- -fpga_0_SysACE_CompactFlash_SysACE_CEN_pinO1fpga_0_SysACE_CompactFlash_SysACE_CEN
- -fpga_0_SysACE_CompactFlash_SysACE_OEN_pinO1fpga_0_SysACE_CompactFlash_SysACE_OEN
- -fpga_0_SysACE_CompactFlash_SysACE_WEN_pinO1fpga_0_SysACE_CompactFlash_SysACE_WEN
- -fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pinI1fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
  - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
- -fpga_0_SRAM_Mem_A_pinO9:29fpga_0_SRAM_Mem_A
- -fpga_0_SRAM_Mem_BEN_pinO0:3fpga_0_SRAM_Mem_BEN
- -fpga_0_SRAM_Mem_WEN_pinO1fpga_0_SRAM_Mem_WEN
- -fpga_0_SRAM_Mem_DQ_pinIO0:31fpga_0_SRAM_Mem_DQ
- -fpga_0_SRAM_Mem_OEN_pinO0:0fpga_0_SRAM_Mem_OEN
- -fpga_0_SRAM_Mem_CEN_pinO0:0fpga_0_SRAM_Mem_CEN
- -fpga_0_SRAM_Mem_ADV_LDN_pinO1fpga_0_SRAM_Mem_ADV_LDN
- -fpga_0_SRAM_CLOCKO1sys_clk_s
- -sys_clk_pinI1dcm_clk_s CLK 
- -sys_rst_pinI1sys_rst_s RESET 
 
-
- - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg deleted file mode 100644 index 182a3ecff..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg +++ /dev/null @@ -1,1452 +0,0 @@ - - - - - - - - - x - - - - - - x - - - - - y - x - - - - - KEY - - SYMBOLS - - bus interface - - shared bus - Bus connections - - master or initiator - - slave or target - - master slave - - monitor - External Ports - - input - - output - - inout - Interrupts - - interrupt - controller - - interrupted - processor - - interrupt - source - x = controller ID - y = priority - - COLORS - Bus Standards - - DCR - - FCB - - FSL - - LMB - - OPB - - PLB - - SOCM - - XIL (prefix) P2P - - GEN. P2P, USER, etc - - - - - SPECS - - EDK VERSION - 10.1.01 - - ARCH - virtex4 - - PART - xc4vfx12ff668-10 - - GENERATED - Sun May 25 17:18:21 2008 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - plb - - - - - - - - - - - A - xps_gpio - LEDs_4Bit - - - SPLB - - - - - - B - xps_gpio - LEDs_Positions - - - SPLB - - - - - - C - xps_uartlite - RS232_Uart - - - SPLB - - - 0 - 0 - - - - - - D - xps_mch_emc - SRAM - - - SPLB - - - - - - F - xps_sysace - SysACE_CompactFlash - - - SPLB - - - - - xps_intc - xps_intc_0 - - - SPLB - - - 0 - - - - - - - - - - - - - - - - - - - - - util_bus_split - SRAM_util_bus_split_0 - - E - - - - - clock_generator - clock_generator_0 - - G - - - - - - - - - - jtagppc_cntlr - jtagppc_0 - - - JTAG - - - - - proc_sys_reset - proc_sys_reset_0 - - H - - - RESE - - - - - ppc405_virtex4 - ppc405_0 - - - JTAG - - - IPLB0 - - - DPLB0 - - - RESE - - - - 0 - - - - - - - SLAVES OF plb - - PROCESSOR - - - - jtagppc_0_0 - - - - - - - - - - - - - - - - - - ppc_reset_bus - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IP - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf deleted file mode 100644 index 0b81c8ff8..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf +++ /dev/null @@ -1,398 +0,0 @@ -############################################################################ -## This system.ucf file is generated by Base System Builder based on the -## settings in the selected Xilinx Board Definition file. Please add other -## user constraints to this file based on customer design specifications. -############################################################################ - -Net sys_clk_pin LOC=AE14; -Net sys_clk_pin IOSTANDARD = LVCMOS33; -Net sys_rst_pin LOC=D6; -Net sys_rst_pin PULLUP; -## System level constraints -Net sys_clk_pin TNM_NET = sys_clk_pin; -TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; -Net sys_rst_pin TIG; -NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP"; -NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP"; -NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP"; -TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; -Net fpga_0_SRAM_CLOCK LOC=AF7; -Net fpga_0_SRAM_CLOCK SLEW = FAST; -Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_CLOCK DRIVE = 16; - -## IO Devices constraints - -#### Module RS232_Uart constraints - -Net fpga_0_RS232_Uart_RX_pin LOC=W2; -Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; -Net fpga_0_RS232_Uart_TX_pin LOC=W1; -Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; - -#### Module LEDs_4Bit constraints - -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; - -#### Module LEDs_Positions constraints - -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; - -#### Module SysACE_CompactFlash constraints - -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF11; -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=Y10; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AA10; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AC7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=Y7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AA9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=Y9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AB7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AC9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AB9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AE6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AD6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AF9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AE9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AD8; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AC8; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AF4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AD3; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AC3; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AF6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AF5; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AD5; -Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AA8; -Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=Y8; -Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin TIG; - -#### Module SRAM constraints - -Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1; -Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2; -Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1; -Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1; -Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2; -Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1; -Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2; -Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1; -Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2; -Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3; -Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3; -Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3; -Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6; -Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5; -Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3; -Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4; -Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3; -Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4; -Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4; -Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5; -Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5; -Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6; -Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5; -Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4; -Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3; -Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6; -Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST; -Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8; -Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13; -Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13; -Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15; -Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16; -Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11; -Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12; -Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14; -Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14; -Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13; -Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13; -Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15; -Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16; -Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11; -Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12; -Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14; -Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14; -Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12; -Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13; -Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16; -Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16; -Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11; -Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11; -Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14; -Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15; -Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13; -Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14; -Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15; -Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16; -Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11; -Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12; -Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13; -Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14; -Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12; -Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6; -Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7; -Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4; -Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST; -Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8; - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut deleted file mode 100644 index 976536332..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut +++ /dev/null @@ -1,20 +0,0 @@ --g CclkPin:PULLUP --g TdoPin:PULLNONE --g M1Pin:PULLDOWN --g DonePin:PULLUP --g DriveDone:No --g StartUpClk:JTAGCLK --g DONE_cycle:4 --g GTS_cycle:5 --g M0Pin:PULLUP --g M2Pin:PULLUP --g ProgPin:PULLUP --g TckPin:PULLUP --g TdiPin:PULLUP --g TmsPin:PULLUP --g DonePipe:No --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:NONE -#-m --g Persist:No diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd deleted file mode 100644 index 15728dcff..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd +++ /dev/null @@ -1,6 +0,0 @@ -setMode -bscan -setCable -p auto -identify -assignfile -p 3 -file implementation/download.bit -program -p 3 -quit diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt deleted file mode 100644 index 6cc2599ab..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt +++ /dev/null @@ -1,82 +0,0 @@ -FLOWTYPE = FPGA; -############################################################### -## Filename: fast_runtime.opt -## -## Option File For Xilinx FPGA Implementation Flow for Fast -## Runtime. -## -## Version: 4.1.1 -############################################################### -# -# Options for Translator -# -# Type "ngdbuild -h" for a detailed list of ngdbuild command line options -# -Program ngdbuild --p ; # Partname to use - picked from xflow commandline --nt timestamp; # NGO File generation. Regenerate only when - # source netlist is newer than existing - # NGO file (default) --bm .bmm # Block RAM memory map file -; # User design - pick from xflow command line --uc .ucf; # ucf constraints -.ngd; # Name of NGD file. Filebase same as design filebase -End Program ngdbuild - -# -# Options for Mapper -# -# Type "map -h " for a detailed list of map command line options -# -Program map --o _map.ncd; # Output Mapped ncd file --pr b; # Pack internal FF/latches into IOBs -#-fp .mfp; # Floorplan file --ol high; --timing; -.ngd; # Input NGD file -.pcf; # Physical constraints file -END Program map - -# -# Options for Post Map Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_map_trce --e 3; # Produce error report limited to 3 items per constraint -#-o _map.twr; # Output trace report file --xml _map.twx; # Output XML version of the timing report -#-tsi _map.tsi; # Produce Timing Specification Interaction report -_map.ncd; # Input mapped ncd -.pcf; # Physical constraints file -END Program post_map_trce - -# -# Options for Place and Route -# -# Type "par -h" for a detailed list of par command line options -# -Program par --w; # Overwrite existing placed and routed ncd --ol high; # Overall effort level -_map.ncd; # Input mapped NCD file -.ncd; # Output placed and routed NCD -.pcf; # Input physical constraints file -END Program par - -# -# Options for Post Par Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_par_trce --e 3; # Produce error report limited to 3 items per constraint -#-o .twr; # Output trace report file --xml .twx; # Output XML version of the timing report -#-tsi .tsi; # Produce Timing Specification Interaction report -.ncd; # Input placed and routed ncd -.pcf; # Physical constraints file -END Program post_par_trce - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt deleted file mode 100644 index 982495f1f..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt +++ /dev/null @@ -1 +0,0 @@ -connect ppc hw -cable type xilinx_parallel port LPT1 frequency 5000000 -debugdevice cpunr 1 diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/platgen.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/platgen.opt deleted file mode 100644 index 185473585..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/platgen.opt +++ /dev/null @@ -1,5 +0,0 @@ --p -xc4vfx12ff668-10 --lang -vhdl -system.mhs diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.bsb b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.bsb deleted file mode 100644 index 12d83ba87..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.bsb +++ /dev/null @@ -1 +0,0 @@ -„æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Db`\b\`bDvC„æÄ®Òôtt¦Êè„ÞÂäÈ@D°ÒØÒÜðD@D¬ÒäèÊð@h@š˜h`f@ŠìÂØêÂèÒÞÜ@ ØÂèÌÞäÚD@DbDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@D‚¤†’¨Š†¨ª¤ŠD@DìÒäèÊðhDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@DˆŠ¬’†Š¾¦’´ŠD@DðÆhìÌðbdDv%„æÄ®ÒôttªàÈÂèʌ Ž‚@D ‚†–‚ŽŠD@DÌÌllpDv&„æÄ®ÒôttªàÈÂèʌ Ž‚@D¦ ŠŠˆŽ¤‚ˆŠD@DZb`Dv3„æÄ®Òôtt¦Êè¦òæèÊÚ@DààÆh`j¾ìÒäèÊðh¾àØÄìhlD@Db\``\ÂDv,„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D„ª¦¾Œ¤Š¢D@Db``\``````Dv,„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D†˜–¾Œ¤Š¢D@Db``\``````Dv-„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D ¤ž†¾Œ¤Š¢D@Dd``\``````Dv(„æÄ®ÒôttªàÈÂèʦòæèÊÚ@D¤¦¨¾ ž˜‚¤’¨²D@D`Dv1„æÄ®Òôtt‚ÈÈ äÞÆÊææÞä@DààÆh`j¾`D@DààÆh`j¾ìÒäèÊðhDv/„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D†‚†ŠD@DbDv3„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D†¾ª¦Š¾Œ ªD@DbDv:„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@DˆŠ„ªŽ¾’ŒD@DŒ Ž‚@”¨‚ŽDv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@Dˆž†š@¦’´ŠD@DœžœŠDv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D’ž†š@¦’´ŠD@DœžœŠDv2„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@Dž†š¾žœ˜²D@D`Dv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäèD@Dðàæ¾êÂäèØÒèÊDv9„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾„‚ªˆ¤‚¨ŠD@Drl``Dv7„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ˆ‚¨‚¾„’¨¦D@DpDv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾žˆˆ¾ ‚¤’¨²D@D`Dv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ª¦Š¾ ‚¤’¨²D@D`Dv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D’ž¨² ŠD@D°’˜¾ª‚¤¨¾¬bDv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@Dª¦Š¾’œ¨Š¤¤ª ¨D@D¨¤ªŠDv-„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾h„ÒèD@Dðàæ¾ÎàÒÞDv;„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾h„ÒèD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾ ÞæÒèÒÞÜæD@Dðàæ¾ÎàÒÞDv@„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾ ÞæÒèÒÞÜæD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv9„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¦ò悆Š¾†ÞÚàÂÆèŒØÂæÐD@Dðàæ¾æòæÂÆÊDvG„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¦ò悆Š¾†ÞÚàÂÆèŒØÂæÐD@D’ž¨² ŠD@D°’˜¾¦²¦‚†Š¾¬bDv+„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¦¤‚šD@Dðàæ¾ÚÆоÊÚÆDv5„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¦¤‚šD@D’ž¨² ŠD@D°’˜¾Šš†¾¬bDv:„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†‚†Š¾†‚œˆ’ˆ‚¨Š¦D@D¦¤‚švDv8„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†¾†‚†Š¾„²¨Š¾¦’´ŠD@DblDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†¾ˆ†‚†Š¾„²¨Š¾¦’´ŠD@DblDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@Dˆ†‚†Š¾†ž¤Š˜’¦¨D@Dv¦¤‚šDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D’†‚†Š¾†ž¤Š˜’¦¨D@Dv¦¤‚šDv:„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D’œ¦¨‚œ†Š¾œ‚šŠD@DààÆh`j¾`Dv/„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾šŠš¨Š¦¨D@DŒ‚˜¦ŠDv1„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾ Š¤’ ¨Š¦¨D@D¨¤ªŠDv)„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾¦®‚  ¦D@DDv7„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D’œ¦¨‚œ†Š¾œ‚šŠD@DààÆh`j¾`Dv0„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾„žž¨šŠšD@D¦¤‚šDv.„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾¦¨ˆ’œD@DœÞÜÊDv/„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾¦¨ˆžª¨D@DœÞÜÊDv@„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ˆ‚¨‚¾’œ¦D@D¦¤‚šDvK„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ˆ‚¨‚¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvC„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ ¤žŽ¤‚š¾’œ¦D@D¦¤‚šDvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ ¤žŽ¤‚š¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvA„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¦¨‚†–¾’œ¦D@D¦¤‚šDvL„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¦¨‚†–¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvC„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¬Š†¨ž¤¦¾’œ¦D@D¦¤‚šDvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¬Š†¨ž¤¦¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤Dv \ No newline at end of file diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.make b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.make deleted file mode 100644 index dd5ce8a3a..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.make +++ /dev/null @@ -1,269 +0,0 @@ -################################################################# -# Makefile generated by Xilinx Platform Studio -# Project:C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp -# -# WARNING : This file will be re-generated every time a command -# to run a make target is invoked. So, any changes made to this -# file manually, will be lost when make is invoked next. -################################################################# - -# Name of the Microprocessor system -# The hardware specification of the system is in file : -# C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.mhs -# The software specification of the system is in file : -# C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.mss - -include system_incl.make - -################################################################# -# PHONY TARGETS -################################################################# -.PHONY: dummy -.PHONY: netlistclean -.PHONY: bitsclean -.PHONY: simclean -.PHONY: vpclean - -################################################################# -# EXTERNAL TARGETS -################################################################# -all: - @echo "Makefile to build a Microprocessor system :" - @echo "Run make with any of the following targets" - @echo " " - @echo " netlist : Generates the netlist for the given MHS " - @echo " bits : Runs Implementation tools to generate the bitstream" - @echo " " - @echo " libs : Configures the sw libraries for this system" - @echo " program : Compiles the program sources for all the processor instances" - @echo " " - @echo " init_bram: Initializes bitstream with BRAM data" - @echo " ace : Generate ace file from bitstream and elf" - @echo " download : Downloads the bitstream onto the board" - @echo " " - @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" - @echo " simmodel : Generates HDL simulation models for chosen simulation mode" - @echo " behavioral_model : Generates behavioral HDL models with BRAM initialization" - @echo " structural_model : Generates structural simulation HDL models with BRAM initialization" - @echo " timing : Generates timing simulation HDL models with BRAM initialization" - @echo " vp : Generates virtual platform model" - @echo " " - @echo " netlistclean: Deletes netlist" - @echo " bitsclean: Deletes bit, ncd, bmm files" - @echo " hwclean : Deletes implementation dir" - @echo " libsclean: Deletes sw libraries" - @echo " programclean: Deletes compiled ELF files" - @echo " swclean : Deletes sw libraries and ELF files" - @echo " simclean : Deletes simulation dir" - @echo " vpclean : Deletes virtualplatform dir" - @echo " clean : Deletes all generated files/directories" - @echo " " - @echo " make : (Default)" - @echo " Creates a Microprocessor system using default initializations" - @echo " specified for each processor in MSS file" - - -bits: $(SYSTEM_BIT) - -ace: $(SYSTEM_ACE) - -netlist: $(POSTSYN_NETLIST) - -libs: $(LIBRARIES) - -program: $(ALL_USER_ELF_FILES) - -download: $(DOWNLOAD_BIT) dummy - @echo "*********************************************" - @echo "Downloading Bitstream onto the target board" - @echo "*********************************************" - impact -batch etc/download.cmd - -init_bram: $(DOWNLOAD_BIT) - -sim: $(DEFAULT_SIM_SCRIPT) - cd simulation/behavioral; \ - $(SIM_CMD) & - -simmodel: $(DEFAULT_SIM_SCRIPT) - -behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) - -structural_model: $(STRUCTURAL_SIM_SCRIPT) - -vp: $(VPEXEC) - -clean: hwclean libsclean programclean simclean vpclean - rm -f _impact.cmd - rm -f *.log - -hwclean: netlistclean bitsclean - rm -rf implementation synthesis xst hdl - rm -rf xst.srp $(SYSTEM).srp - -netlistclean: - rm -f $(POSTSYN_NETLIST) - rm -f platgen.log - rm -f $(BMM_FILE) - -bitsclean: - rm -f $(SYSTEM_BIT) - rm -f implementation/$(SYSTEM).ncd - rm -f implementation/$(SYSTEM)_bd.bmm - rm -f implementation/$(SYSTEM)_map.ncd - -simclean: - rm -rf simulation/behavioral - rm -f simgen.log - -swclean: libsclean programclean - @echo "" - -libsclean: $(LIBSCLEAN_TARGETS) - rm -f libgen.log - -programclean: $(PROGRAMCLEAN_TARGETS) - -vpclean: - rm -rf virtualplatform - rm -f vpgen.log - -################################################################# -# SOFTWARE PLATFORM FLOW -################################################################# - - -$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt - @echo "*********************************************" - @echo "Creating software libraries..." - @echo "*********************************************" - libgen $(LIBGEN_OPTIONS) $(MSSFILE) - - -ppc405_0_libsclean: - rm -rf ppc405_0/ - -################################################################# -# SOFTWARE APPLICATION RTOSDEMO -################################################################# - -RTOSDemo_program: $(RTOSDEMO_OUTPUT) - -$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \ - $(LIBRARIES) __xps/rtosdemo_compiler.opt - @mkdir -p $(RTOSDEMO_OUTPUT_DIR) - $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \ - $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \ - $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) - $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) - @echo "" - -RTOSDemo_programclean: - rm -f $(RTOSDEMO_OUTPUT) - -################################################################# -# BOOTLOOP ELF FILES -################################################################# - - - -$(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP) - @mkdir -p $(BOOTLOOP_DIR) - cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP) - -################################################################# -# HARDWARE IMPLEMENTATION FLOW -################################################################# - - -$(BMM_FILE) \ -$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ - $(CORE_STATE_DEVELOPMENT_FILES) - @echo "****************************************************" - @echo "Creating system netlist for hardware specification.." - @echo "****************************************************" - platgen $(PLATGEN_OPTIONS) $(MHSFILE) - -$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) - @echo "Running synthesis..." - bash -c "cd synthesis; ./synthesis.sh" - -__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY) - @echo "*********************************************" - @echo "Running Xilinx Implementation tools.." - @echo "*********************************************" - @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf - xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/manage_fastruntime_opt.pl $(MANAGE_FASTRT_OPTIONS) - xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc - touch __xps/$(SYSTEM)_routed - -$(SYSTEM_BIT): __xps/$(SYSTEM)_routed - xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par - @echo "*********************************************" - @echo "Running Bitgen.." - @echo "*********************************************" - @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut - cd implementation; bitgen -w -f bitgen.ut $(SYSTEM) - -$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt - # @cp -f implementation/$(SYSTEM)_bd.bmm . - @echo "*********************************************" - @echo "Initializing BRAM contents of the bitstream" - @echo "*********************************************" - bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \ - -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) - @rm -f $(SYSTEM)_bd.bmm - -$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) - @echo "*********************************************" - @echo "Creating system ace file" - @echo "*********************************************" - xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE) - -################################################################# -# SIMULATION FLOW -################################################################# - - -################## BEHAVIORAL SIMULATION ################## - -$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ - $(BRAMINIT_ELF_FILES) - @echo "*********************************************" - @echo "Creating behavioral simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) - -################## STRUCTURAL SIMULATION ################## - -$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ - $(BRAMINIT_ELF_FILES) - @echo "*********************************************" - @echo "Creating structural simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) - - -################## TIMING SIMULATION ################## - -$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \ - $(BRAMINIT_ELF_FILES) - @echo "*********************************************" - @echo "Creating timing simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) - -################################################################# -# VIRTUAL PLATFORM FLOW -################################################################# - - -$(VPEXEC): $(MHSFILE) __xps/vpgen.opt - @echo "****************************************************" - @echo "Creating virtual platform for hardware specification.." - @echo "****************************************************" - vpgen $(VPGEN_OPTIONS) $(MHSFILE) - -dummy: - @echo "" - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.mhs b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.mhs deleted file mode 100644 index 064842c7b..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.mhs +++ /dev/null @@ -1,210 +0,0 @@ - -# ############################################################################## -# Created by Base System Builder Wizard for Xilinx EDK 10.1.01 Build EDK_K_SP1.3 -# Fri May 09 11:01:33 2008 -# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1 -# Family: virtex4 -# Device: xc4vfx12 -# Package: ff668 -# Speed Grade: -10 -# Processor: ppc405_0 -# Processor clock frequency: 200.00 MHz -# Bus clock frequency: 100.00 MHz -# Total Off Chip Memory : 1 MB -# - SRAM = 1 MB -# ############################################################################## - PARAMETER VERSION = 2.1.0 - - - PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I - PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O - PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3] - PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4] - PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I - PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1] - PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0] - PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O - PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O - PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O - PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I - PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [9:29] - PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3] - PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O - PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31] - PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0] - PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0] - PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O - PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O - PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 - PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST - - -BEGIN ppc405_virtex4 - PARAMETER INSTANCE = ppc405_0 - PARAMETER HW_VER = 2.01.a - PARAMETER C_FASTEST_PLB_CLOCK = DPLB0 - PARAMETER C_APU_CONTROL = 0b0000000000000001 - PARAMETER C_IDCR_BASEADDR = 0b0100000000 - PARAMETER C_IDCR_HIGHADDR = 0b0111111111 - BUS_INTERFACE JTAGPPC = jtagppc_0_0 - BUS_INTERFACE IPLB0 = plb - BUS_INTERFACE DPLB0 = plb - BUS_INTERFACE RESETPPC = ppc_reset_bus - PORT CPMC405CLOCK = proc_clk_s - PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ -END - -BEGIN jtagppc_cntlr - PARAMETER INSTANCE = jtagppc_0 - PARAMETER HW_VER = 2.01.a - BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 -END - -BEGIN plb_v46 - PARAMETER INSTANCE = plb - PARAMETER C_DCR_INTFCE = 0 - PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100 - PARAMETER HW_VER = 1.02.a - PORT PLB_Clk = sys_clk_s - PORT SYS_Rst = sys_bus_reset -END - -BEGIN xps_uartlite - PARAMETER INSTANCE = RS232_Uart - PARAMETER HW_VER = 1.00.a - PARAMETER C_BAUDRATE = 9600 - PARAMETER C_DATA_BITS = 8 - PARAMETER C_ODD_PARITY = 0 - PARAMETER C_USE_PARITY = 0 - PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000 - PARAMETER C_BASEADDR = 0x84000000 - PARAMETER C_HIGHADDR = 0x8400ffff - BUS_INTERFACE SPLB = plb - PORT RX = fpga_0_RS232_Uart_RX - PORT TX = fpga_0_RS232_Uart_TX - PORT Interrupt = RS232_Uart_Interrupt -END - -BEGIN xps_gpio - PARAMETER INSTANCE = LEDs_4Bit - PARAMETER HW_VER = 1.00.a - PARAMETER C_GPIO_WIDTH = 4 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_IS_BIDIR = 1 - PARAMETER C_ALL_INPUTS = 0 - PARAMETER C_BASEADDR = 0x81400000 - PARAMETER C_HIGHADDR = 0x8140ffff - BUS_INTERFACE SPLB = plb - PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO -END - -BEGIN xps_gpio - PARAMETER INSTANCE = LEDs_Positions - PARAMETER HW_VER = 1.00.a - PARAMETER C_GPIO_WIDTH = 5 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_IS_BIDIR = 1 - PARAMETER C_ALL_INPUTS = 0 - PARAMETER C_BASEADDR = 0x81420000 - PARAMETER C_HIGHADDR = 0x8142ffff - BUS_INTERFACE SPLB = plb - PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO -END - -BEGIN xps_sysace - PARAMETER INSTANCE = SysACE_CompactFlash - PARAMETER HW_VER = 1.00.a - PARAMETER C_MEM_WIDTH = 16 - PARAMETER C_BASEADDR = 0x83600000 - PARAMETER C_HIGHADDR = 0x8360ffff - BUS_INTERFACE SPLB = plb - PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK - PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA - PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD - PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN - PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN - PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN - PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ -END - -BEGIN xps_mch_emc - PARAMETER INSTANCE = SRAM - PARAMETER HW_VER = 1.01.a - PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000 - PARAMETER C_NUM_BANKS_MEM = 1 - PARAMETER C_MAX_MEM_WIDTH = 32 - PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1 - PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 - PARAMETER C_MEM0_WIDTH = 32 - PARAMETER C_SYNCH_MEM_0 = 1 - PARAMETER C_TCEDV_PS_MEM_0 = 0 - PARAMETER C_TWC_PS_MEM_0 = 0 - PARAMETER C_TAVDV_PS_MEM_0 = 0 - PARAMETER C_TWP_PS_MEM_0 = 0 - PARAMETER C_THZCE_PS_MEM_0 = 0 - PARAMETER C_TLZWE_PS_MEM_0 = 0 - PARAMETER C_MEM0_BASEADDR = 0xfff00000 - PARAMETER C_MEM0_HIGHADDR = 0xffffffff - BUS_INTERFACE SPLB = plb - PORT Mem_A = fpga_0_SRAM_Mem_A_split - PORT Mem_BEN = fpga_0_SRAM_Mem_BEN - PORT Mem_WEN = fpga_0_SRAM_Mem_WEN - PORT Mem_DQ = fpga_0_SRAM_Mem_DQ - PORT Mem_OEN = fpga_0_SRAM_Mem_OEN - PORT Mem_CEN = fpga_0_SRAM_Mem_CEN - PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN - PORT RdClk = sys_clk_s -END - -BEGIN util_bus_split - PARAMETER INSTANCE = SRAM_util_bus_split_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_SIZE_IN = 32 - PARAMETER C_LEFT_POS = 9 - PARAMETER C_SPLIT = 30 - PORT Sig = fpga_0_SRAM_Mem_A_split - PORT Out1 = fpga_0_SRAM_Mem_A -END - -BEGIN clock_generator - PARAMETER INSTANCE = clock_generator_0 - PARAMETER HW_VER = 2.01.a - PARAMETER C_EXT_RESET_HIGH = 1 - PARAMETER C_CLKIN_FREQ = 100000000 - PARAMETER C_CLKOUT0_FREQ = 200000000 - PARAMETER C_CLKOUT0_BUF = TRUE - PARAMETER C_CLKOUT0_PHASE = 0 - PARAMETER C_CLKOUT0_GROUP = NONE - PARAMETER C_CLKOUT1_FREQ = 100000000 - PARAMETER C_CLKOUT1_BUF = TRUE - PARAMETER C_CLKOUT1_PHASE = 0 - PARAMETER C_CLKOUT1_GROUP = NONE - PORT CLKOUT0 = proc_clk_s - PORT CLKOUT1 = sys_clk_s - PORT CLKIN = dcm_clk_s - PORT LOCKED = Dcm_all_locked - PORT RST = net_gnd -END - -BEGIN proc_sys_reset - PARAMETER INSTANCE = proc_sys_reset_0 - PARAMETER HW_VER = 2.00.a - PARAMETER C_EXT_RESET_HIGH = 0 - BUS_INTERFACE RESETPPC0 = ppc_reset_bus - PORT Slowest_sync_clk = sys_clk_s - PORT Dcm_locked = Dcm_all_locked - PORT Ext_Reset_In = sys_rst_s - PORT Bus_Struct_Reset = sys_bus_reset - PORT Peripheral_Reset = sys_periph_reset -END - -BEGIN xps_intc - PARAMETER INSTANCE = xps_intc_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_BASEADDR = 0x81800000 - PARAMETER C_HIGHADDR = 0x8180ffff - BUS_INTERFACE SPLB = plb - PORT Irq = EICC405EXTINPUTIRQ - PORT Intr = RS232_Uart_Interrupt -END - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.mss b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.mss deleted file mode 100644 index f4320f371..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.mss +++ /dev/null @@ -1,82 +0,0 @@ - - PARAMETER VERSION = 2.2.0 - - -BEGIN OS - PARAMETER OS_NAME = standalone - PARAMETER OS_VER = 2.00.a - PARAMETER PROC_INSTANCE = ppc405_0 -END - - -BEGIN PROCESSOR - PARAMETER DRIVER_NAME = cpu_ppc405 - PARAMETER DRIVER_VER = 1.10.a - PARAMETER HW_INSTANCE = ppc405_0 - PARAMETER COMPILER = powerpc-eabi-gcc - PARAMETER ARCHIVER = powerpc-eabi-ar - PARAMETER CORE_CLOCK_FREQ_HZ = 200000000 -END - - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = jtagppc_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = uartlite - PARAMETER DRIVER_VER = 1.13.a - PARAMETER HW_INSTANCE = RS232_Uart -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = gpio - PARAMETER DRIVER_VER = 2.12.a - PARAMETER HW_INSTANCE = LEDs_4Bit -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = gpio - PARAMETER DRIVER_VER = 2.12.a - PARAMETER HW_INSTANCE = LEDs_Positions -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = sysace - PARAMETER DRIVER_VER = 1.11.a - PARAMETER HW_INSTANCE = SysACE_CompactFlash -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = emc - PARAMETER DRIVER_VER = 2.00.a - PARAMETER HW_INSTANCE = SRAM -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = SRAM_util_bus_split_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = clock_generator_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = proc_sys_reset_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = intc - PARAMETER DRIVER_VER = 1.11.a - PARAMETER HW_INSTANCE = xps_intc_0 -END - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.xmp b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.xmp deleted file mode 100644 index 4a7a93ca7..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system.xmp +++ /dev/null @@ -1,74 +0,0 @@ -#Please do not modify this file by hand -XmpVersion: 10.1.01 -VerMgmt: 10.1.01 -IntStyle: default -MHS File: system.mhs -MSS File: system.mss -NPL File: projnav/system.ise -Architecture: virtex4 -Device: xc4vfx12 -Package: ff668 -SpeedGrade: -10 -UserCmd1: -UserCmd1Type: 0 -UserCmd2: -UserCmd2Type: 0 -TopInst: system_i -GenSimTB: 0 -InsertNoPads: 0 -WarnForEAArch: 1 -HdlLang: VHDL -Simulator: mti -SimModel: BEHAVIORAL -MixLangSim: 1 -UcfFile: data/system.ucf -FpgaImpMode: 0 -EnableParTimingError: 1 -EnableResetOptimization: 0 -ShowLicenseDialog: 1 -ICacheAddr: SRAM, -DCacheAddr: SRAM, -Processor: ppc405_0 -BootLoop: 1 -XmdStub: 0 -SwProj: RTOSDemo -Processor: ppc405_0 -Executable: RTOSDemo/executable.elf -Source: RTOSDemo/../../Common/Minimal/BlockQ.c -Source: RTOSDemo/../../Common/Minimal/blocktim.c -Source: RTOSDemo/../../Common/Minimal/comtest.c -Source: RTOSDemo/../../Common/Minimal/countsem.c -Source: RTOSDemo/../../Common/Minimal/death.c -Source: RTOSDemo/../../Common/Minimal/dynamic.c -Source: RTOSDemo/../../Common/Minimal/flash.c -Source: RTOSDemo/../../Common/Minimal/GenQTest.c -Source: RTOSDemo/../../Common/Minimal/integer.c -Source: RTOSDemo/../../Common/Minimal/QPeek.c -Source: RTOSDemo/../../Common/Minimal/recmutex.c -Source: RTOSDemo/../../Common/Minimal/semtest.c -Source: RTOSDemo/../../../Source/tasks.c -Source: RTOSDemo/../../../Source/list.c -Source: RTOSDemo/../../../Source/queue.c -Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c -Source: RTOSDemo/main.c -Source: RTOSDemo/serial/serial.c -Source: RTOSDemo/partest/partest.c -Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S -Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c -Source: RTOSDemo/flop/flop.c -Source: RTOSDemo/flop/flop-reg-test.c -Header: RTOSDemo/FreeRTOSConfig.h -DefaultInit: EXECUTABLE -InitBram: 0 -Active: 1 -CompilerOptLevel: 0 -GlobPtrOpt: 0 -DebugSym: 1 -ProfileFlag: 0 -ProgStart: -StackSize: -HeapSize: -LinkerScript: RTOSDemo/RTOSDemo_linker_script.ld -ProgCCFlags: -I./RTOSDemo/flop -I../../Source/portable/GCC/PPC405_Xilinx -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -CompileInXps: 1 -NonXpsApp: 0 diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system_incl.make b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system_incl.make deleted file mode 100644 index fc6e11530..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/system_incl.make +++ /dev/null @@ -1,142 +0,0 @@ -################################################################# -# Makefile generated by Xilinx Platform Studio -# Project:C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp -# -# WARNING : This file will be re-generated every time a command -# to run a make target is invoked. So, any changes made to this -# file manually, will be lost when make is invoked next. -################################################################# - -XILINX_EDK_DIR = /cygdrive/c/devtools/Xilinx/10.1/EDK -NON_CYG_XILINX_EDK_DIR = C:/devtools/Xilinx/10.1/EDK - -SYSTEM = system - -MHSFILE = system.mhs - -MSSFILE = system.mss - -FPGA_ARCH = virtex4 - -DEVICE = xc4vfx12ff668-10 - -LANGUAGE = vhdl - -SEARCHPATHOPT = - -SUBMODULE_OPT = - -PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) - -LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) - -VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT) - -MANAGE_FASTRT_OPTIONS = -reduce_fanout no - -OBSERVE_PAR_OPTIONS = -error yes - -RTOSDEMO_OUTPUT_DIR = RTOSDemo -RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf - -MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf -PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf -PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf -BOOTLOOP_DIR = bootloops - -PPC405_0_BOOTLOOP = $(BOOTLOOP_DIR)/ppc405_0.elf - -BRAMINIT_ELF_FILES = -BRAMINIT_ELF_FILE_ARGS = - -ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) - -SIM_CMD = vsim - -BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do - -STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do - -TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do - -DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) - -MIX_LANG_SIM_OPT = -mixed yes - -SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti -X C:/E/temp/rc/3/V5.0.2/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/ -E C:/E/temp/rc/3/V5.0.2/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/ - - -LIBRARIES = \ - ppc405_0/lib/libxil.a -VPEXEC = virtualplatform/vpexec.exe - -LIBSCLEAN_TARGETS = ppc405_0_libsclean - -PROGRAMCLEAN_TARGETS = RTOSDemo_programclean - -CORE_STATE_DEVELOPMENT_FILES = - -WRAPPER_NGC_FILES = implementation/ppc405_0_wrapper.ngc \ -implementation/jtagppc_0_wrapper.ngc \ -implementation/plb_wrapper.ngc \ -implementation/rs232_uart_wrapper.ngc \ -implementation/leds_4bit_wrapper.ngc \ -implementation/leds_positions_wrapper.ngc \ -implementation/sysace_compactflash_wrapper.ngc \ -implementation/sram_wrapper.ngc \ -implementation/sram_util_bus_split_0_wrapper.ngc \ -implementation/clock_generator_0_wrapper.ngc \ -implementation/proc_sys_reset_0_wrapper.ngc \ -implementation/xps_intc_0_wrapper.ngc - -POSTSYN_NETLIST = implementation/$(SYSTEM).ngc - -SYSTEM_BIT = implementation/$(SYSTEM).bit - -DOWNLOAD_BIT = implementation/download.bit - -SYSTEM_ACE = implementation/$(SYSTEM).ace - -UCF_FILE = data/system.ucf - -BMM_FILE = implementation/$(SYSTEM).bmm - -BITGEN_UT_FILE = etc/bitgen.ut - -XFLOW_OPT_FILE = etc/fast_runtime.opt -XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE) - -XPLORER_DEPENDENCY = __xps/xplorer.opt -XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7 - -FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(BITGEN_UT_FILE) $(XFLOW_DEPENDENCY) - -################################################################# -# SOFTWARE APPLICATION RTOSDEMO -################################################################# - -RTOSDEMO_SOURCES = RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../Common/Minimal/countsem.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/recmutex.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/flop/flop.c RTOSDemo/flop/flop-reg-test.c - -RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h - -RTOSDEMO_CC = powerpc-eabi-gcc -RTOSDEMO_CC_SIZE = powerpc-eabi-size -RTOSDEMO_CC_OPT = -O0 -RTOSDEMO_CFLAGS = -I./RTOSDemo/flop -I../../Source/portable/GCC/PPC405_Xilinx -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -RTOSDEMO_CC_SEARCH = # -B -RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L -RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ # -I -RTOSDEMO_LFLAGS = # -l -RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo_linker_script.ld -RTOSDEMO_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) -RTOSDEMO_CC_DEBUG_FLAG = -g -RTOSDEMO_CC_PROFILE_FLAG = # -pg -RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi -RTOSDEMO_CC_INFERRED_FLAGS= -RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= -RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= -RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= -RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \ - $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) $(RTOSDEMO_CC_HEAP_SIZE_FLAG) \ - $(RTOSDEMO_CC_INFERRED_FLAGS) \ - $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) $(RTOSDEMO_CC_PROFILE_FLAG) diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/wizlog b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/wizlog deleted file mode 100644 index 3f4f48396..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/wizlog +++ /dev/null @@ -1,3 +0,0 @@ -WARNING:MDT - ppc405_virtex4 (ppc405_0) - - C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\dump.mhs - line 28 - ADDRESS specified by PARAMETER C_IDCR_BASEADDR is ignored diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79 b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79 deleted file mode 100644 index 48ae48ba4..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79 +++ /dev/null @@ -1,93 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - RSEG ICODE:CODE - CODE32 - - EXTERN vEMACISR - PUBLIC vEMACISREntry - -; Wrapper for the EMAC interrupt service routine. This can cause a -; context switch so requires an assembly wrapper. - -; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. -#include "ISR_Support.h" - -vEMACISREntry: - - portSAVE_CONTEXT ; Save the context of the current task. - - bl vEMACISR ; Call the ISR routine. - - portRESTORE_CONTEXT ; Restore the context of the current task - - ; which may be different to the task that - ; was interrupted. - - END - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c deleted file mode 100644 index 715da6933..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c +++ /dev/null @@ -1,738 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * Basic interrupt driven driver for the EMAC peripheral. This driver is not - * reentrant as with uIP the buffers are only ever accessed from a single task. - * - * The simple buffer management used within uIP allows the EMAC driver to also - * be simplistic. The driver contained within the lwIP demo is more - * comprehensive. - */ - - -/* -Changes from V3.2.2 - - + Corrected the byte order when writing the MAC address to the MAC. - + Support added for MII interfaces. Previously only RMII was supported. - -Changes from V3.2.3 - - + The MII interface is now the default. - + Modified the initialisation sequence slightly to allow auto init more - time to complete. - -Changes from V3.2.4 - - + Also read the EMAC_RSR register in the EMAC ISR as a work around the - the EMAC bug that can reset the RX bit in EMAC_ISR register before the - bit has been read. - -Changes from V4.0.4 - - + Corrected the Rx frame length mask when obtaining the length from the - rx descriptor. - -*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "semphr.h" -#include "task.h" - -/* uIP includes. */ -#include "uip.h" - -/* Hardware specific includes. */ -#include "Emac.h" -#include "mii.h" - - -/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0 -to use an MII interface. */ -#define USE_RMII_INTERFACE 0 - -/* The buffer addresses written into the descriptors must be aligned so the -last few bits are zero. These bits have special meaning for the EMAC -peripheral and cannot be used as part of the address. */ -#define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC ) - -/* Bit used within the address stored in the descriptor to mark the last -descriptor in the array. */ -#define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 ) - -/* Bit used within the Tx descriptor status to indicate whether the -descriptor is under the control of the EMAC or the software. */ -#define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 ) - -/* A short delay is used to wait for a buffer to become available, should -one not be immediately available when trying to transmit a frame. */ -#define emacBUFFER_WAIT_DELAY ( 2 ) -#define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 ) - -/* Misc defines. */ -#define emacINTERRUPT_LEVEL ( 5 ) -#define emacNO_DELAY ( 0 ) -#define emacTOTAL_FRAME_HEADER_SIZE ( 54 ) -#define emacPHY_INIT_DELAY ( 5000 / portTICK_PERIOD_MS ) -#define emacRESET_KEY ( ( unsigned long ) 0xA5000000 ) -#define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) ) - -/* The Atmel header file only defines the TX frame length mask. */ -#define emacRX_LENGTH_FRAME ( 0xfff ) - -/*-----------------------------------------------------------*/ - -/* - * Prototype for the EMAC interrupt asm wrapper. - */ -extern void vEMACISREntry( void ); - -/* - * Prototype for the EMAC interrupt function - called by the asm wrapper. - */ -__arm void vEMACISR( void ); - -/* - * Initialise both the Tx and Rx descriptors used by the EMAC. - */ -static void prvSetupDescriptors(void); - -/* - * Write our MAC address into the EMAC. The MAC address is set as one of the - * uip options. - */ -static void prvSetupMACAddress( void ); - -/* - * Configure the EMAC and AIC for EMAC interrupts. - */ -static void prvSetupEMACInterrupt( void ); - -/* - * Some initialisation functions taken from the Atmel EMAC sample code. - */ -static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue ); -#if USE_RMII_INTERFACE != 1 - static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue); -#endif -static portBASE_TYPE xGetLinkSpeed( void ); -static portBASE_TYPE prvProbePHY( void ); - -/*-----------------------------------------------------------*/ - -/* Buffer written to by the EMAC DMA. Must be aligned as described by the -comment above the emacADDRESS_MASK definition. */ -#pragma data_alignment=8 -static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ]; - -/* Buffer read by the EMAC DMA. Must be aligned as described by he comment -above the emacADDRESS_MASK definition. */ -#pragma data_alignment=8 -static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ]; - -/* Descriptors used to communicate between the program and the EMAC peripheral. -These descriptors hold the locations and state of the Rx and Tx buffers. */ -static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ]; -static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ]; - -/* The IP and Ethernet addresses are read from the uIP setup. */ -const char cMACAddress[ 6 ] = { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 }; -const unsigned char ucIPAddress[ 4 ] = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 }; - -/* The semaphore used by the EMAC ISR to wake the EMAC task. */ -static SemaphoreHandle_t xSemaphore = NULL; - -/*-----------------------------------------------------------*/ - -SemaphoreHandle_t xEMACInit( void ) -{ - /* Code supplied by Atmel (modified) --------------------*/ - - /* disable pull up on RXDV => PHY normal mode (not in test mode), - PHY has internal pull down. */ - AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15; - - #if USE_RMII_INTERFACE != 1 - /* PHY has internal pull down : set MII mode. */ - AT91C_BASE_PIOB->PIO_PPUDR= 1 << 16; - #endif - - /* clear PB18 <=> PHY powerdown. */ - AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 ) ; - AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, 1 << 18) ; - - /* After PHY power up, hardware reset. */ - AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH; - AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST; - - /* Wait for hardware reset end. */ - while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) ) - { - __asm( "NOP" ); - } - __asm( "NOP" ); - - /* EMAC IO init for EMAC-PHY com. Remove EF100 config. */ - AT91F_EMAC_CfgPIO(); - - /* Enable com between EMAC PHY. - - Enable management port. */ - AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; - - /* MDC = MCK/32. */ - AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10; - - /* Wait for PHY auto init end (rather crude delay!). */ - vTaskDelay( emacPHY_INIT_DELAY ); - - /* PHY configuration. */ - #if USE_RMII_INTERFACE != 1 - { - unsigned long ulControl; - - /* PHY has internal pull down : disable MII isolate. */ - vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl ); - vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl ); - ulControl &= ~BMCR_ISOLATE; - vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl ); - } - #endif - - /* Disable management port again. */ - AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; - - #if USE_RMII_INTERFACE != 1 - /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */ - AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ; - #else - /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator - on ERFCK). */ - AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ; - #endif - - /* End of code supplied by Atmel ------------------------*/ - - /* Setup the buffers and descriptors. */ - prvSetupDescriptors(); - - /* Load our MAC address into the EMAC. */ - prvSetupMACAddress(); - - /* Try to connect. */ - if( prvProbePHY() ) - { - /* Enable the interrupt! */ - prvSetupEMACInterrupt(); - } - - return xSemaphore; -} -/*-----------------------------------------------------------*/ - -long lEMACSend( void ) -{ -static unsigned portBASE_TYPE uxTxBufferIndex = 0; -portBASE_TYPE xWaitCycles = 0; -long lReturn = pdPASS; -char *pcBuffer; - - /* Is a buffer available? */ - while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) ) - { - /* There is no room to write the Tx data to the Tx buffer. Wait a - short while, then try again. */ - xWaitCycles++; - if( xWaitCycles > emacMAX_WAIT_CYCLES ) - { - /* Give up. */ - lReturn = pdFAIL; - break; - } - else - { - vTaskDelay( emacBUFFER_WAIT_DELAY ); - } - } - - /* lReturn will only be pdPASS if a buffer is available. */ - if( lReturn == pdPASS ) - { - /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */ - pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr; - memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE ); - if( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) - { - memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) ); - } - - /* Send. */ - portENTER_CRITICAL(); - { - if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) ) - { - /* Fill out the necessary in the descriptor to get the data sent. */ - xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME ) - | AT91C_LAST_BUFFER - | AT91C_TRANSMIT_WRAP; - uxTxBufferIndex = 0; - } - else - { - /* Fill out the necessary in the descriptor to get the data sent. */ - xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME ) - | AT91C_LAST_BUFFER; - uxTxBufferIndex++; - } - - AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART; - } - portEXIT_CRITICAL(); - } - - return lReturn; -} -/*-----------------------------------------------------------*/ - -unsigned long ulEMACPoll( void ) -{ -static unsigned portBASE_TYPE ulNextRxBuffer = 0; -unsigned long ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE; -char *pcSource; - - /* Skip any fragments. */ - while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) ) - { - /* Mark the buffer as free again. */ - xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT ); - ulNextRxBuffer++; - if( ulNextRxBuffer >= NB_RX_BUFFERS ) - { - ulNextRxBuffer = 0; - } - } - - /* Is there a packet ready? */ - - while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength ) - { - pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK ); - ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME; - - if( ulSectionLength == 0 ) - { - /* The frame is longer than the buffer pointed to by this - descriptor so copy the entire buffer to uIP - then move onto - the next descriptor to get the rest of the frame. */ - if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE ) - { - memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE ); - ulLengthSoFar += ETH_RX_BUFFER_SIZE; - } - } - else - { - /* This is the last section of the frame. Copy the section to - uIP. */ - if( ulSectionLength < UIP_BUFSIZE ) - { - /* The section length holds the length of the entire frame. - ulLengthSoFar holds the length of the frame sections already - copied to uIP, so the length of the final section is - ulSectionLength - ulLengthSoFar; */ - if( ulSectionLength > ulLengthSoFar ) - { - memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) ); - } - } - - /* Is this the last buffer for the frame? If not why? */ - ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF; - } - - /* Mark the buffer as free again. */ - xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT ); - - /* Increment to the next buffer, wrapping if necessary. */ - ulNextRxBuffer++; - if( ulNextRxBuffer >= NB_RX_BUFFERS ) - { - ulNextRxBuffer = 0; - } - } - - /* If we obtained data but for some reason did not find the end of the - frame then discard the data as it must contain an error. */ - if( !ulEOF ) - { - ulSectionLength = 0; - } - - return ulSectionLength; -} -/*-----------------------------------------------------------*/ - -static void prvSetupDescriptors(void) -{ -unsigned portBASE_TYPE xIndex; -unsigned long ulAddress; - - /* Initialise xRxDescriptors descriptor. */ - for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex ) - { - /* Calculate the address of the nth buffer within the array. */ - ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) ); - - /* Write the buffer address into the descriptor. The DMA will place - the data at this address when this descriptor is being used. Mask off - the bottom bits of the address as these have special meaning. */ - xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK; - } - - /* The last buffer has the wrap bit set so the EMAC knows to wrap back - to the first buffer. */ - xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT; - - /* Initialise xTxDescriptors. */ - for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex ) - { - /* Calculate the address of the nth buffer within the array. */ - ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) ); - - /* Write the buffer address into the descriptor. The DMA will read - data from here when the descriptor is being used. */ - xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK; - xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK; - } - - /* The last buffer has the wrap bit set so the EMAC knows to wrap back - to the first buffer. */ - xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK; - - /* Tell the EMAC where to find the descriptors. */ - AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors; - AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors; - - /* Clear all the bits in the receive status register. */ - AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA ); - - /* Enable the copy of data into the buffers, ignore broadcasts, - and don't copy FCS. */ - AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS); - - /* Enable Rx and Tx, plus the stats register. */ - AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupMACAddress( void ) -{ - /* Must be written SA1L then SA1H. */ - AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) | - ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) | - ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) | - cMACAddress[ 0 ]; - - AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) | - cMACAddress[ 4 ]; -} -/*-----------------------------------------------------------*/ - -static void prvSetupEMACInterrupt( void ) -{ - /* Create the semaphore used to trigger the EMAC task. */ - vSemaphoreCreateBinary( xSemaphore ); - if( xSemaphore ) - { - /* We start by 'taking' the semaphore so the ISR can 'give' it when the - first interrupt occurs. */ - xSemaphoreTake( xSemaphore, emacNO_DELAY ); - portENTER_CRITICAL(); - { - /* We want to interrupt on Rx events. */ - AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP; - - /* Enable the interrupts in the AIC. */ - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISREntry ); - AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_EMAC ); - } - portEXIT_CRITICAL(); - } -} -/*-----------------------------------------------------------*/ - -__arm void vEMACISR( void ) -{ -volatile unsigned long ulIntStatus, ulRxStatus; -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR; - ulRxStatus = AT91C_BASE_EMAC->EMAC_RSR; - - if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulRxStatus & AT91C_EMAC_REC ) ) - { - /* A frame has been received, signal the uIP task so it can process - the Rx descriptors. */ - xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken ); - AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC; - } - - /* If a task was woken by either a character being received or a character - being transmitted then we may need to switch to another task. */ - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); - - /* Clear the interrupt. */ - AT91C_BASE_AIC->AIC_EOICR = 0; -} -/*-----------------------------------------------------------*/ - - - -/* - * The following functions are initialisation functions taken from the Atmel - * EMAC sample code. - */ - -static portBASE_TYPE prvProbePHY( void ) -{ -unsigned long ulPHYId1, ulPHYId2, ulStatus; -portBASE_TYPE xReturn = pdPASS; - - /* Code supplied by Atmel (reformatted) -----------------*/ - - /* Enable management port */ - AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; - AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10; - - /* Read the PHY ID. */ - vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 ); - vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 ); - - /* AMD AM79C875: - PHY_ID1 = 0x0022 - PHY_ID2 = 0x5541 - Bits 3:0 Revision Number Four bit manufacturer’s revision number. - 0001 stands for Rev. A, etc. - */ - if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID ) - { - /* Did not expect this ID. */ - xReturn = pdFAIL; - } - else - { - ulStatus = xGetLinkSpeed(); - - if( ulStatus != pdPASS ) - { - xReturn = pdFAIL; - } - } - - /* Disable management port */ - AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; - - /* End of code supplied by Atmel ------------------------*/ - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue ) -{ - /* Code supplied by Atmel (reformatted) ----------------------*/ - - AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30)) - | (2 << 16) | (2 << 28) - | ((ucPHYAddress & 0x1f) << 23) - | (ucAddress << 18); - - /* Wait until IDLE bit in Network Status register is cleared. */ - while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) ) - { - __asm( "NOP" ); - } - - *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff ); - - /* End of code supplied by Atmel ------------------------*/ -} -/*-----------------------------------------------------------*/ - -#if USE_RMII_INTERFACE != 1 -static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue ) -{ - /* Code supplied by Atmel (reformatted) ----------------------*/ - - AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30)) - | (2 << 16) | (1 << 28) - | ((ucPHYAddress & 0x1f) << 23) - | (ucAddress << 18)) - | (ulValue & 0xffff); - - /* Wait until IDLE bit in Network Status register is cleared */ - while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) ) - { - __asm( "NOP" ); - }; - - /* End of code supplied by Atmel ------------------------*/ -} -#endif -/*-----------------------------------------------------------*/ - -static portBASE_TYPE xGetLinkSpeed( void ) -{ - unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex; - - /* Code supplied by Atmel (reformatted) -----------------*/ - - /* Link status is latched, so read twice to get current value */ - vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR); - vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR); - - if( !( ulBMSR & BMSR_LSTATUS ) ) - { - /* No Link. */ - return pdFAIL; - } - - vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR); - if (ulBMCR & BMCR_ANENABLE) - { - /* AutoNegotiation is enabled. */ - if (!(ulBMSR & BMSR_ANEGCOMPLETE)) - { - /* Auto-negotiation in progress. */ - return pdFAIL; - } - - vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA); - if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) ) - { - ulSpeed = SPEED_100; - } - else - { - ulSpeed = SPEED_10; - } - - if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) ) - { - ulDuplex = DUPLEX_FULL; - } - else - { - ulDuplex = DUPLEX_HALF; - } - } - else - { - ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10; - ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF; - } - - /* Update the MAC */ - ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD ); - if( ulSpeed == SPEED_100 ) - { - if( ulDuplex == DUPLEX_FULL ) - { - /* 100 Full Duplex */ - AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD; - } - else - { - /* 100 Half Duplex */ - AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD; - } - } - else - { - if (ulDuplex == DUPLEX_FULL) - { - /* 10 Full Duplex */ - AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD; - } - else - { - /* 10 Half Duplex */ - AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg; - } - } - - /* End of code supplied by Atmel ------------------------*/ - - return pdPASS; -} diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h deleted file mode 100644 index 2c54cae56..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef SAM_7_EMAC_H -#define SAM_7_EMAC_H - - -/* - * Initialise the EMAC driver. If successful a semaphore is returned that - * is used by the EMAC ISR to indicate that Rx packets have been received. - * If the initialisation fails then NULL is returned. - */ -SemaphoreHandle_t xEMACInit( void ); - -/* - * Send the current uIP buffer. This copies the uIP buffer to one of the - * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready. - */ -long lEMACSend( void ); - -/* - * Called in response to an EMAC Rx interrupt. Copies the received frame - * into the uIP buffer. - */ -unsigned long ulEMACPoll( void ); - -#endif diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h deleted file mode 100644 index bd77c64b9..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include -#include "Board.h" - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned long ) 47923200 ) -#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 22000 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configQUEUE_REGISTRY_SIZE 10 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - -/* This demo makes use of one or more example stats formatting functions. These -format the raw data provided by the uxTaskGetSystemState() function in to human -readable ASCII form. See the notes in the implementation of vTaskList() within -FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 - -#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c deleted file mode 100644 index 37e01e555..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#include "FreeRTOS.h" -#include "partest.h" -#include "board.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines for the LED's. LED's can be set, cleared - * or toggled. - *-----------------------------------------------------------*/ -const unsigned long ulLED_MASK[ NB_LED ]= { LED1, LED2, LED3, LED4 }; - -void vParTestInitialise( void ) -{ - /* Start with all LED's off. */ - AT91F_PIO_SetOutput( AT91C_BASE_PIOB, LED_MASK ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - if( uxLED < ( portBASE_TYPE ) NB_LED ) - { - if( xValue ) - { - AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] ); - } - else - { - AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]); - } - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - if( uxLED < ( portBASE_TYPE ) NB_LED ) - { - if( AT91F_PIO_GetInput( AT91C_BASE_PIOB ) & ulLED_MASK[ uxLED ] ) - { - AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]); - } - else - { - AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] ); - } - } -} - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/ReadMe.txt b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/ReadMe.txt new file mode 100644 index 000000000..add564283 --- /dev/null +++ b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/ReadMe.txt @@ -0,0 +1,5 @@ +If you need the demo that used to be in this directory then download FreeRTOS V8.2.3 +from http://sourceforge.net/projects/freertos/files/FreeRTOS/ + +FreeRTOS now uses its own TCP/IP stack: http://www.FreeRTOS.org/TCP + diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h deleted file mode 100644 index aba67274f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h +++ /dev/null @@ -1,69 +0,0 @@ -/*---------------------------------------------------------------------------- -* ATMEL Microcontroller Software Support - ROUSSET - -*---------------------------------------------------------------------------- -* The software is delivered "AS IS" without warranty or condition of any -* kind, either express, implied or statutory. This includes without -* limitation any warranty or condition with respect to merchantability or -* fitness for any particular purpose, or against the infringements of -* intellectual property rights of others. -*---------------------------------------------------------------------------- -* File Name : Board.h -* Object : AT91SAM7X Evaluation Board Features Definition File. -* -* Creation : JG 20/Jun/2005 -*---------------------------------------------------------------------------- -*/ -#ifndef Board_h -#define Board_h - -#include -#define __inline static inline -#include - -#define true -1 -#define false 0 - -/*-------------------------------*/ -/* SAM7Board Memories Definition */ -/*-------------------------------*/ -// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash - -#define FLASH_PAGE_NB 256 -#define FLASH_PAGE_SIZE 128 - -/*-----------------*/ -/* Leds Definition */ -/*-----------------*/ -#define LED1 (1<<19) // PB19 -#define LED2 (1<<20) // PB20 -#define LED3 (1<<21) // PB21 -#define LED4 (1<<22) // PB22 -#define NB_LED 4 - -#define LED_MASK (LED1|LED2|LED3|LED4) - -/*-------------------------*/ -/* Push Buttons Definition */ -/*-------------------------*/ - -#define SW1_MASK (1<<21) // PA21 -#define SW2_MASK (1<<22) // PA22 -#define SW3_MASK (1<<23) // PA23 -#define SW4_MASK (1<<24) // PA24 -#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK) - - -#define SW1 (1<<21) // PA21 -#define SW2 (1<<22) // PA22 -#define SW3 (1<<23) // PA23 -#define SW4 (1<<24) // PA24 - -/*--------------*/ -/* Master Clock */ -/*--------------*/ - -#define EXT_OC 18432000 // Exetrnal ocilator MAINCK -#define MCK 47923200 // MCK (PLLRC div by 2) -#define MCKKHz (MCK/1000) // - -#endif /* Board_h */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s deleted file mode 100644 index 12842e137..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s +++ /dev/null @@ -1,302 +0,0 @@ -;* ---------------------------------------------------------------------------- -;* ATMEL Microcontroller Software Support - ROUSSET - -;* ---------------------------------------------------------------------------- -;* Copyright (c) 2006, Atmel Corporation -; -;* All rights reserved. -;* -;* Redistribution and use in source and binary forms, with or without -;* modification, are permitted provided that the following conditions are met: -;* -;* - Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the disclaimer below. -;* -;* - Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the disclaimer below in the documentation and/or -;* other materials provided with the distribution. -;* -;* Atmel's name may not be used to endorse or promote products derived from -;* this software without specific prior written permission. -;* -;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* ---------------------------------------------------------------------------- - -;------------------------------------------------------------------------------ -; Include your AT91 Library files -;------------------------------------------------------------------------------ -#include "AT91SAM7X256_inc.h" -;------------------------------------------------------------------------------ - -#define TOP_OF_MEMORY (AT91C_ISRAM + AT91C_ISRAM_SIZE) -#define IRQ_STACK_SIZE 200 - ; 3 words to be saved per interrupt priority level - -; Mode, correspords to bits 0-5 in CPSR -MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR -USR_MODE DEFINE 0x10 ; User mode -FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode -IRQ_MODE DEFINE 0x12 ; Interrupt Request mode -SVC_MODE DEFINE 0x13 ; Supervisor mode -ABT_MODE DEFINE 0x17 ; Abort mode -UND_MODE DEFINE 0x1B ; Undefined Instruction mode -SYS_MODE DEFINE 0x1F ; System mode - -I_BIT DEFINE 0x80 -F_BIT DEFINE 0x40 - -;------------------------------------------------------------------------------ -; ?RESET -; Reset Vector. -; Normally, segment INTVEC is linked at address 0. -; For debugging purposes, INTVEC may be placed at other addresses. -; A debugger that honors the entry point will start the -; program in a normal way even if INTVEC is not at address 0. -;------------------------------------------------------------------------------ - SECTION .intvec:CODE:NOROOT(2) - PUBLIC __vector - PUBLIC __iar_program_start - EXTERN vPortYieldProcessor - - ARM -__vector: - ldr pc,[pc,#+24] ;; Reset -__und_handler: - ldr pc,[pc,#+24] ;; Undefined instructions -__swi_handler: - ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC) -__prefetch_handler: - ldr pc,[pc,#+24] ;; Prefetch abort -__data_handler: - ldr pc,[pc,#+24] ;; Data abort - DC32 0xFFFFFFFF ;; RESERVED -__irq_handler: - LDR PC, [PC, #-0xF20] -__fiq_handler: - ldr pc,[pc,#+24] ;; FIQ - - DC32 __iar_program_start - DC32 __und_handler - DC32 vPortYieldProcessor - DC32 __prefetch_handler - DC32 __data_handler - B . - DC32 IRQ_Handler_Entry - DC32 FIQ_Handler_Entry - -;------------------------------------------------------------------------------ -;- Manage exception: The exception must be ensure in ARM mode -;------------------------------------------------------------------------------ - SECTION text:CODE:NOROOT(2) - ARM -;------------------------------------------------------------------------------ -;- Function : FIQ_Handler_Entry -;- Treatments : FIQ Controller Interrupt Handler. -;- R8 is initialize in Cstartup -;- Called Functions : None only by FIQ -;------------------------------------------------------------------------------ -FIQ_Handler_Entry: - -;- Switch in SVC/User Mode to allow User Stack access for C code -; because the FIQ is not yet acknowledged - -;- Save and r0 in FIQ_Register - mov r9,r0 - ldr r0 , [r8, #AIC_FVR] - msr CPSR_c,#I_BIT | F_BIT | SVC_MODE -;- Save scratch/used registers and LR in User Stack - stmfd sp!, { r1-r3, r12, lr} - -;- Branch to the routine pointed by the AIC_FVR - mov r14, pc - bx r0 - -;- Restore scratch/used registers and LR from User Stack - ldmia sp!, { r1-r3, r12, lr} - -;- Leave Interrupts disabled and switch back in FIQ mode - msr CPSR_c, #I_BIT | F_BIT | FIQ_MODE - -;- Restore the R0 ARM_MODE_SVC register - mov r0,r9 - -;- Restore the Program Counter using the LR_fiq directly in the PC - subs pc,lr,#4 -;------------------------------------------------------------------------------ -;- Function : IRQ_Handler_Entry -;- Treatments : IRQ Controller Interrupt Handler. -;- Called Functions : AIC_IVR[interrupt] -;------------------------------------------------------------------------------ -IRQ_Handler_Entry: -;------------------------- -;- Manage Exception Entry -;------------------------- -;- Adjust and save LR_irq in IRQ stack - sub lr, lr, #4 - stmfd sp!, {lr} - -;- Save r0 and SPSR (need to be saved for nested interrupt) - mrs r14, SPSR - stmfd sp!, {r0,r14} - -;- Write in the IVR to support Protect Mode -;- No effect in Normal Mode -;- De-assert the NIRQ and clear the source in Protect Mode - ldr r14, =AT91C_BASE_AIC - ldr r0 , [r14, #AIC_IVR] - str r14, [r14, #AIC_IVR] - -;- Enable Interrupt and Switch in Supervisor Mode - msr CPSR_c, #SVC_MODE - -;- Save scratch/used registers and LR in User Stack - stmfd sp!, { r1-r3, r12, r14} - -;---------------------------------------------- -;- Branch to the routine pointed by the AIC_IVR -;---------------------------------------------- - mov r14, pc - bx r0 - -;---------------------------------------------- -;- Manage Exception Exit -;---------------------------------------------- -;- Restore scratch/used registers and LR from User Stack - ldmia sp!, { r1-r3, r12, r14} - -;- Disable Interrupt and switch back in IRQ mode - msr CPSR_c, #I_BIT | IRQ_MODE - -;- Mark the End of Interrupt on the AIC - ldr r14, =AT91C_BASE_AIC - str r14, [r14, #AIC_EOICR] - -;- Restore SPSR_irq and r0 from IRQ stack - ldmia sp!, {r0,r14} - msr SPSR_cxsf, r14 - -;- Restore adjusted LR_irq from IRQ stack directly in the PC - ldmia sp!, {pc}^ - -;------------------------------------------------------------------------------ -;- Exception Vectors -;------------------------------------------------------------------------------ - PUBLIC AT91F_Default_FIQ_handler - PUBLIC AT91F_Default_IRQ_handler - PUBLIC AT91F_Spurious_handler - - ARM ; Always ARM mode after exeption - -AT91F_Default_FIQ_handler - b AT91F_Default_FIQ_handler - -AT91F_Default_IRQ_handler - b AT91F_Default_IRQ_handler - -AT91F_Spurious_handler - b AT91F_Spurious_handler - - -;------------------------------------------------------------------------------ -; ?INIT -; Program entry. -;------------------------------------------------------------------------------ - - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION CSTACK:DATA:NOROOT(3) - SECTION text:CODE:NOROOT(2) - REQUIRE __vector - EXTERN ?main - PUBLIC __iar_program_start - EXTERN AT91F_LowLevelInit - - -__iar_program_start: - -;------------------------------------------------------------------------------ -;- Low level Init is performed in a C function: AT91F_LowLevelInit -;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit -;------------------------------------------------------------------------------ - -;- Retrieve end of RAM address - - ldr r13,=TOP_OF_MEMORY ;- Temporary stack in internal RAM for Low Level Init execution - ldr r0,=AT91F_LowLevelInit - mov lr, pc - bx r0 ;- Branch on C function (with interworking) - -; Initialize the stack pointers. -; The pattern below can be used for any of the exception stacks: -; FIQ, IRQ, SVC, ABT, UND, SYS. -; The USR mode uses the same stack as SYS. -; The stack segments must be defined in the linker command file, -; and be declared above. - - mrs r0,cpsr ; Original PSR value - bic r0,r0,#MODE_BITS ; Clear the mode bits - orr r0,r0,#SVC_MODE ; Set SVC mode bits - msr cpsr_c,r0 ; Change the mode - ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK - - bic r0,r0,#MODE_BITS ; Clear the mode bits - orr r0,r0,#UND_MODE ; Set UND mode bits - msr cpsr_c,r0 ; Change the mode - ldr sp,=SFE(UND_STACK) ; End of UND_STACK - - bic r0,r0,#MODE_BITS ; Clear the mode bits - orr r0,r0,#ABT_MODE ; Set ABT mode bits - msr cpsr_c,r0 ; Change the mode - ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK - - bic r0,r0,#MODE_BITS ; Clear the mode bits - orr r0,r0,#FIQ_MODE ; Set FIQ mode bits - msr cpsr_c,r0 ; Change the mode - ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK - ;- Init the FIQ register - ldr r8, =AT91C_BASE_AIC - - bic r0,r0,#MODE_BITS ; Clear the mode bits - orr r0,r0,#IRQ_MODE ; Set IRQ mode bits - msr cpsr_c,r0 ; Change the mode - ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK - - bic r0,r0,#MODE_BITS ; Clear the mode bits - orr r0,r0,#SYS_MODE ; Set System mode bits - msr cpsr_c,r0 ; Change the mode - ldr sp,=SFE(CSTACK) ; End of CSTACK - - -#ifdef __ARMVFP__ -; Enable the VFP coprocessor. - mov r0, #0x40000000 ; Set EN bit in VFP - fmxr fpexc, r0 ; FPEXC, clear others. - -; Disable underflow exceptions by setting flush to zero mode. -; For full IEEE 754 underflow compliance this code should be removed -; and the appropriate exception handler installed. - mov r0, #0x01000000 ; Set FZ bit in VFP - fmxr fpscr, r0 ; FPSCR, clear others. -#endif - -; Add more initialization here - msr CPSR_c,#I_BIT | F_BIT | SVC_MODE - - -; Continue to ?main for more IAR specific system startup - - ldr r0,=?main - bx r0 - - END ;- Terminates the assembly of the last module in a file diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c deleted file mode 100644 index 0b48391b3..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c +++ /dev/null @@ -1,97 +0,0 @@ -//----------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -//----------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//----------------------------------------------------------------------------- -// File Name : Cstartup_SAM7.c -// Object : Low level initialisations written in C for Tools -// For AT91SAM7X256 with 2 flash plane -// Creation : JPP 14-Sep-2006 -//----------------------------------------------------------------------------- - - -#include "Board.h" -// The following functions must be write in ARM mode this function called -// directly by exception vector -extern void AT91F_Spurious_handler(void); -extern void AT91F_Default_IRQ_handler(void); -extern void AT91F_Default_FIQ_handler(void); - -//*---------------------------------------------------------------------------- -//* \fn AT91F_LowLevelInit -//* \brief This function performs very low level HW initialization -//* this function can use a Stack, depending the compilation -//* optimization mode -//*---------------------------------------------------------------------------- -void AT91F_LowLevelInit(void) @ "ICODE" -{ - unsigned char i; - /////////////////////////////////////////////////////////////////////////// - // EFC Init - /////////////////////////////////////////////////////////////////////////// - AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ; - - /////////////////////////////////////////////////////////////////////////// - // Init PMC Step 1. Enable Main Oscillator - // Main Oscillator startup time is board specific: - // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms - // (0x40 for AT91C_CKGR_OSCOUNT field) - /////////////////////////////////////////////////////////////////////////// - AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN )); - // Wait Main Oscillator stabilization - while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); - - /////////////////////////////////////////////////////////////////////////// - // Init PMC Step 2. - // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz - // PLL Startup time depends on PLL RC filter: worst case is choosen - // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus - // Specification (+/- 0.25% for full speed) - /////////////////////////////////////////////////////////////////////////// - AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 | - (16 << 8) | - (AT91C_CKGR_MUL & (72 << 16)) | - (AT91C_CKGR_DIV & 14); - // Wait for PLL stabilization - while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ); - // Wait until the master clock is established for the case we already - // turn on the PLL - while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ); - - /////////////////////////////////////////////////////////////////////////// - // Init PMC Step 3. - // Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz - // The PMC_MCKR register must not be programmed in a single write operation - // (see. Product Errata Sheet) - /////////////////////////////////////////////////////////////////////////// - AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; - // Wait until the master clock is established - while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ); - - AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; - // Wait until the master clock is established - while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ); - - /////////////////////////////////////////////////////////////////////////// - // Disable Watchdog (write once register) - /////////////////////////////////////////////////////////////////////////// - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - /////////////////////////////////////////////////////////////////////////// - // Init AIC: assign corresponding handler for each interrupt source - /////////////////////////////////////////////////////////////////////////// - AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ; - for (i = 1; i < 31; i++) { - AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ; - } - AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler; -} diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h deleted file mode 100644 index 7551a3648..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h +++ /dev/null @@ -1,195 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : Emac.h -//* Object : Emac header file -//* Creation : Hi 11/18/2002 -//* -//*---------------------------------------------------------------------------- -#ifndef AT91C_EMAC_H -#define AT91C_EMAC_H - - -//* Allows to display all IP header in the main.c -//* If not defined, only ICMP packets are displayed -#define AT91C_DISPLAY_ALL_IPHEADER 0 - -#define NB_RX_BUFFERS 25 //* Number of receive buffers -#define ETH_RX_BUFFER_SIZE 128 //* - -#define NB_TX_BUFFERS 2 //* Number of Transmit buffers -#define ETH_TX_BUFFER_SIZE UIP_BUFSIZE //* - -#define AT91C_NO_IPPACKET 0 -#define AT91C_IPPACKET 1 - -#define ARP_REQUEST 0x0001 -#define ARP_REPLY 0x0002 -#define PROT_ARP 0x0806 -#define PROT_IP 0x0800 -#define PROT_ICMP 0x01 -#define ICMP_ECHO_REQUEST 0x08 -#define ICMP_ECHO_REPLY 0x00 - -#define AT91C_EMAC_CLKEN 0x2 -#define SWAP16(x) (((x & 0xff) << 8) | (x >> 8)) - -#if 0 -//* Transfer descriptor structure -typedef struct _AT91S_TdDescriptor { - unsigned int addr; - unsigned int status; -}AT91S_TdDescriptor, *AT91PS_TdDescriptor; -#endif - -//* Receive Transfer descriptor structure -typedef struct _AT91S_RxTdDescriptor { - unsigned int addr; - union - { - unsigned int status; - struct { - unsigned int Length:11; - unsigned int Res0:1; - unsigned int Rxbuf_off:2; - unsigned int StartOfFrame:1; - unsigned int EndOfFrame:1; - unsigned int Cfi:1; - unsigned int VlanPriority:3; - unsigned int PriorityTag:1; - unsigned int VlanTag:1; - unsigned int TypeID:1; - unsigned int Sa4Match:1; - unsigned int Sa3Match:1; - unsigned int Sa2Match:1; - unsigned int Sa1Match:1; - unsigned int Res1:1; - unsigned int ExternalAdd:1; - unsigned int UniCast:1; - unsigned int MultiCast:1; - unsigned int BroadCast:1; - }S_Status; - }U_Status; -}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor; - - -//* Transmit Transfer descriptor structure -typedef struct _AT91S_TxTdDescriptor { - unsigned int addr; - union - { - unsigned int status; - struct { - unsigned int Length:11; - unsigned int Res0:4; - unsigned int LastBuff:1; - unsigned int NoCrc:1; - unsigned int Res1:10; - unsigned int BufExhausted:1; - unsigned int TransmitUnderrun:1; - unsigned int TransmitError:1; - unsigned int Wrap:1; - unsigned int BuffUsed:1; - }S_Status; - }U_Status; -}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor; - -#define AT91C_OWNERSHIP_BIT 0x00000001 - -/* Receive status defintion */ -#define AT91C_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected -#define AT91C_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match -#define AT91C_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match -#define AT91C_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match -#define AT91C_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match -#define AT91C_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match -#define AT91C_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match -#define AT91C_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match -#define AT91C_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match -#define AT91C_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected -#define AT91C_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected -#define AT91C_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask -#define AT91C_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator -#define AT91C_EOF ((unsigned int) (1 << 15)) //* EOF -#define AT91C_SOF ((unsigned int) (1 << 14)) //* SOF -#define AT91C_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask -#define AT91C_LENGTH_FRAME ((unsigned int) 0x07FF) //* Length of frame - -/* Transmit Status definition */ -#define AT91C_TRANSMIT_OK ((unsigned int) (1 << 31)) //* -#define AT91C_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor -#define AT91C_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error -#define AT91C_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun -#define AT91C_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame -#define AT91C_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame -#define AT91C_LAST_BUFFER ((unsigned int) (1 << 15)) //* - -#define ARP_ETHER 1 /* Ethernet hardware address */ -#define ARPOP_REQUEST 1 /* Request to resolve address */ -#define ARPOP_REPLY 2 /* Response to previous request */ -#define RARPOP_REQUEST 3 /* Request to resolve address */ -#define RARPOP_REPLY 4 /* Response to previous request */ - - -typedef struct _AT91S_EthHdr -{ - unsigned char et_dest[6]; /* Destination node */ - unsigned char et_src[6]; /* Source node */ - unsigned short et_protlen; /* Protocol or length */ -} AT91S_EthHdr, *AT91PS_EthHdr; - -typedef struct _AT91S_ArpHdr -{ - unsigned short ar_hrd; /* Format of hardware address */ - unsigned short ar_pro; /* Format of protocol address */ - unsigned char ar_hln; /* Length of hardware address */ - unsigned char ar_pln; /* Length of protocol address */ - unsigned short ar_op; /* Operation */ - unsigned char ar_sha[6]; /* Sender hardware address */ - unsigned char ar_spa[4]; /* Sender protocol address */ - unsigned char ar_tha[6]; /* Target hardware address */ - unsigned char ar_tpa[4]; /* Target protocol address */ -} AT91S_ArpHdr, *AT91PS_ArpHdr; - -//* IP Header structure -typedef struct _AT91S_IPheader { - unsigned char ip_hl_v; /* header length and version */ - unsigned char ip_tos; /* type of service */ - unsigned short ip_len; /* total length */ - unsigned short ip_id; /* identification */ - unsigned short ip_off; /* fragment offset field */ - unsigned char ip_ttl; /* time to live */ - unsigned char ip_p; /* protocol */ - unsigned short ip_sum; /* checksum */ - unsigned char ip_src[4]; /* Source IP address */ - unsigned char ip_dst[4]; /* Destination IP address */ - unsigned short udp_src; /* UDP source port */ - unsigned short udp_dst; /* UDP destination port */ - unsigned short udp_len; /* Length of UDP packet */ - unsigned short udp_xsum; /* Checksum */ -} AT91S_IPheader, *AT91PS_IPheader; - -//* ICMP echo header structure -typedef struct _AT91S_IcmpEchoHdr { - unsigned char type; /* type of message */ - unsigned char code; /* type subcode */ - unsigned short cksum; /* ones complement cksum of struct */ - unsigned short id; /* identifier */ - unsigned short seq; /* sequence number */ -}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr; - - -typedef struct _AT91S_EthPack -{ - AT91S_EthHdr EthHdr; - AT91S_ArpHdr ArpHdr; -} AT91S_EthPack, *AT91PS_EthPack; - - -#endif //* AT91C_EMAC_H diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c deleted file mode 100644 index cee31b1d5..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c +++ /dev/null @@ -1,95 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : dbgu.c -//* Object : DBGU routines written in C -//* Creation : JG 16/Aug/2004 -//*---------------------------------------------------------------------------- - -// Include Standard files -#include "Board.h" - -//*--------------------------1-------------------------------------------------- -//* \fn AT91F_DBGU_Printk -//* \brief This function is used to send a string through the DBGU channel (Very low level debugging) -//*---------------------------------------------------------------------------- -void AT91F_DBGU_Printk( char *buffer) -{ - AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; - unsigned int temp; - - while(*buffer != '\0') - { - temp=0; - - while (temp==0) - { - if ( (pDbgu->DBGU_CSR & 0x0200) == 0) - temp=0; - else - temp=1; - } - - pDbgu->DBGU_THR = *buffer; - buffer++; - } -} - - -void Init_DBGU_CLK(void) -{ - AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, ((unsigned int) 1 << AT91C_ID_SYS)); -} - -void Init_DBGU_BGR(unsigned short baud) -{ - AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; - - pDbgu->DBGU_BRGR = (unsigned short)baud; -} - -void DBGU_TX_Enable(void) -{ - AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; - - pDbgu->DBGU_CR = 0x00000040; -} - -void DBGU_RX_Enable(void) -{ - AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; - - pDbgu->DBGU_CR = 0x00000010; -} - -void DBGU_RX_TX_RST_DIS(void) -{ - AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; - pDbgu->DBGU_CR = 0x000000AC; -} - -void DBGU_Parity_Cfg(unsigned int par) -{ - AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; - - pDbgu->DBGU_MR = par << 9; -} - - -void Init_DBGU(void) -{ - AT91F_DBGU_CfgPIO(); - DBGU_RX_TX_RST_DIS(); - Init_DBGU_BGR(26); //26 <=> 115kBd - DBGU_Parity_Cfg(4); - DBGU_TX_Enable(); - DBGU_RX_Enable(); -} - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h deleted file mode 100644 index 58f50a046..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h +++ /dev/null @@ -1,22 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : dbgu.c -//* Object : DBGU routines written in C -//* Creation : JG 16/Aug/2004 -//*---------------------------------------------------------------------------- - -// Include Standard files -extern void APPLI_DBGU(void); -extern void D1_TEST_REGISTER_RESET_VALUES(void); -extern void D2_CHIP_ID_VALUES(void); - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c deleted file mode 100644 index cbb1ee48e..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c +++ /dev/null @@ -1,31 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : init.c -//* Object : Low level initialisations written in C -//* Creation : ODi 06/26/2002 -//* -//*---------------------------------------------------------------------------- -#include "board.h" -//#include "init.h" -#include - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_Printk -//* \brief This function is used to send a string through the DBGU channel (Very low level debugging) -//*---------------------------------------------------------------------------- -void AT91F_DBGU_Printk( - char *buffer) // \arg pointer to a string ending by \0 -{ - while(*buffer != '\0') { - while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU)); - AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *buffer++); - } -} - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h deleted file mode 100644 index df9caccb5..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h +++ /dev/null @@ -1,4700 +0,0 @@ -// - ---------------------------------------------------------------------------- -// - ATMEL Microcontroller Software Support - ROUSSET - -// - ---------------------------------------------------------------------------- -// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// - ---------------------------------------------------------------------------- -// - File Name : AT91SAM7X128.h -// - Object : AT91SAM7X128 definitions -// - Generated : AT91 SW Application Group 05/20/2005 (16:22:23) -// - -// - CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// -// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// - ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X128_H -#define AT91SAM7X128_H - -#ifdef __IAR_SYSTEMS_ICC__ - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) -#endif /* __IAR_SYSTEMS_ICC__ */ - -#ifdef __IAR_SYSTEMS_ASM__ - -// - Hardware register definition - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR System Peripherals -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// - ***************************************************************************** -// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level -AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level -AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level -AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type -AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive -AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered -AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered -AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered -// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status -AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status -// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode -AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// - ***************************************************************************** -// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable -AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable -AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable -AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable -// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Debug Unit -// - ***************************************************************************** -// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver -AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter -AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable -AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable -AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable -AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable -AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits -// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type -AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity -AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity -AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) -AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) -AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity -AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode -AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode -AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt -AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt -AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt -AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt -AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt -AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt -AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt -AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt -AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt -AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt -AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt -AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt -// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Clock Generator Controler -// - ***************************************************************************** -// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable -AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass -AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time -// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency -AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready -// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter -AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range -AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier -AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks -AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output -AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 -AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Power Management Controler -// - ***************************************************************************** -// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock -AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock -AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output -// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection -AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected -AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected -AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected -AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler -AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock -AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 -AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 -AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 -AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 -AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 -AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 -// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask -AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask -AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask -// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Reset Controller Interface -// - ***************************************************************************** -// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset -AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset -AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset -AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password -// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status -AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status -AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type -AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. -AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. -AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. -AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. -AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level -AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. -// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable -AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable -AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable -AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// - ***************************************************************************** -// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value -AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable -AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable -AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart -// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value -// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value -// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status -AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// - ***************************************************************************** -// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value -AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled -AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable -// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status -// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value -AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter -// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// - ***************************************************************************** -// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart -AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password -// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable -AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable -AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable -AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value -AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt -AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt -// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow -AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// - ***************************************************************************** -// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Memory Controller Interface -// - ***************************************************************************** -// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit -// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status -AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status -AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status -AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte -AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word -AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word -AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status -AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read -AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write -AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch -AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source -AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source -AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source -AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source -// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready -AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error -AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error -AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming -AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State -AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations -AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations -AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations -AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations -AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number -// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command -AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. -AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. -AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. -AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. -AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. -AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number -AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key -// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status -AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status -AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status -AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status -AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status -AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status -AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status -AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status -AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status -AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status -AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status -AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status -AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status -AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status -AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status -AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status -AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status -AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status -AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status -AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status -AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status -AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status -AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Serial Parallel Interface -// - ***************************************************************************** -// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable -AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable -AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset -AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer -// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode -AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select -AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select -AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select -AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode -AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection -AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection -AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection -AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select -AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects -// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data -AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data -AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full -AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty -AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error -AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status -AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer -AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer -AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt -AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt -AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt -AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt -AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status -// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity -AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase -AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer -AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer -AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer -AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer -AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer -AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer -AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer -AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer -AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer -AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer -AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer -AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK -AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Usart -// - ***************************************************************************** -// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break -AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break -AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out -AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address -AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations -AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge -AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out -AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable -AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable -AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable -AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable -// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode -AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal -AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 -AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking -AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem -AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 -AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 -AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA -AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking -AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock -AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 -AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) -AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) -AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits -AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits -AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits -AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits -AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select -AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits -AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit -AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits -AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order -AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length -AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select -AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode -AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge -AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK -AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions -AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter -// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break -AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out -AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached -AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge -AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag -AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag -AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag -AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag -// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input -AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input -AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input -AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// - ***************************************************************************** -// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable -AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable -AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable -AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable -AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset -// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection -AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock -AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal -AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin -AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection -AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output -AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion -AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection -AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start -AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input -AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input -AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input -AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input -AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input -AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input -AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 -AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay -AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection -// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length -AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode -AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First -AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame -AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length -AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection -AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection -// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value -AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable -// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready -AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty -AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission -AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty -AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready -AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun -AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception -AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full -AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync -AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync -AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable -AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable -// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Two-wire Interface -// - ***************************************************************************** -// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition -AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition -AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled -AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled -AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset -// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size -AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address -AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address -AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address -AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address -AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction -AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address -// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider -AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider -AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider -// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed -AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY -AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY -AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error -AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error -AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged -// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR PWMC Channel Interface -// - ***************************************************************************** -// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) -AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment -AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity -AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period -// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle -// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period -// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter -// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// - ***************************************************************************** -// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. -AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A -AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) -AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. -AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B -AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) -// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 -AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 -AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 -AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 -// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR USB Device Interface -// - ***************************************************************************** -// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats -AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error -AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK -// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable -AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured -AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume -AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host -AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable -// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value -AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable -// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt -AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt -AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt -AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt -AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt -AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt -AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt -AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt -AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt -// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt -// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 -AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 -AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 -AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 -AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 -AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 -// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR -AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 -AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) -AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) -AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready -AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction -AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type -AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control -AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT -AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT -AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT -AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN -AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN -AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN -AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle -AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable -AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO -// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) -AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// - ***************************************************************************** -// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command -AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command -AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command -// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection -AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK -AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK -AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK -AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK -AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK -AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 -AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 -AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 -AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert -AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection -AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal -AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock -AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock -AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock -AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare -AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading -AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare -AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading -AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection -AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection -AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection -AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input -AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output -AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output -AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output -AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection -AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable -AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection -AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare -AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare -AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable -AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) -AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA -AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none -AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set -AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear -AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle -AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection -AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None -AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA -AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA -AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none -AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set -AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear -AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle -AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection -AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None -AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA -AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA -AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none -AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set -AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear -AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle -AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA -AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none -AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set -AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear -AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle -AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB -AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none -AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set -AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear -AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle -AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB -AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none -AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set -AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear -AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle -AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB -AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none -AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set -AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear -AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle -AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB -AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none -AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set -AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear -AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle -// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow -AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun -AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare -AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare -AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare -AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading -AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading -AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger -AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling -AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror -AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror -// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Interface -// - ***************************************************************************** -// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command -// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection -AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 -AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 -AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 -AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 -AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection -AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 -AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 -AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 -AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 -AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection -AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 -AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 -AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 -AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// - ***************************************************************************** -// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark -AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority -AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type -AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) -// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode -AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode -AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version -// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value -AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code -AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request -AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort -AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready -AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored -// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox -AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network Interface -// - ***************************************************************************** -// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable -AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode -AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode -AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame -AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame -AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode -AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze -AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat -// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag -AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag -AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag -AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag -AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag -AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag -AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag -AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag -AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag -AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag -AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag -AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag -AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag -AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag -AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag -AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag -AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag -AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag -AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag -AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag -AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag -AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag -AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag -AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag -AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error -AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error -AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error -AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error -AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error -// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy -AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy -AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy -// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment -AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment -AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment -AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment -AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler -AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode -// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field -// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter -AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter -// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field -// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// - ***************************************************************************** -// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. -AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. -AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. -AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. -AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. -AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. -AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. -AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. -AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. -AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. -AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. -AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame -AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame -// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. -AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. -AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. -AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. -AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. -AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable -AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. -AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. -AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. -AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) -AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8 -AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16 -AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32 -AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64 -AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) -AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) -AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer -AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable -AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS -AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) -AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS -// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go -AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame -AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) -// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) -AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) -AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) -AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) -AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) -AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) -AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) -AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) -// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) -AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) -AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) -AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) -AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) -// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII -// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address -AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable -AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable -AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable -// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// - ***************************************************************************** -// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset -AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion -// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable -AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. -AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection -AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 -AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 -AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 -AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 -AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 -AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 -AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger -AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. -AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution -AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution -AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode -AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection -AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time -AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time -// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 -AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 -AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 -AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 -AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 -AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 -AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 -AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 -// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion -AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion -AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion -AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion -AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion -AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion -AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion -AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion -AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error -AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error -AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error -AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error -AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error -AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error -AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error -AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error -AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready -AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun -AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer -AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt -// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted -// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data -// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// - ***************************************************************************** -// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- -AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing -AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset -AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading -// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode -AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay -AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode -AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet). -AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode -AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode. -AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode. -AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode. -AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode. -AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode. -AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode -AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size -AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit. -AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit. -AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit. -AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit. -AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit. -AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key -AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type -AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled. -AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled. -AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled. -AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled. -AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled. -// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY -AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End -AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End -AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full -AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty -AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection -// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status -AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode. -AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing. -AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing. -AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation. -AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation. -AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access. - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// - ***************************************************************************** -// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing -AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset -// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode -AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode -AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode -AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode -AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet). -AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode -AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode. -AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode. -AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode. -AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode. -AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode -AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size -AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit. -AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit. -AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit. -AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit. -// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY -AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End -AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End -AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full -AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty -AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection -// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status -AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode. -AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing. -AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing. -AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access. - -// - ***************************************************************************** -// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 -// - ***************************************************************************** -// - ========== Register definition for SYS peripheral ========== -// - ========== Register definition for AIC peripheral ========== -AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register -AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register -AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register -AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) -AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register -AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register -AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register -AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register -AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register -AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register -AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register -AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register -AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register -AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register -AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register -AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register -AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register -AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register -// - ========== Register definition for PDC_DBGU peripheral ========== -AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register -AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register -AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register -AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register -AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register -AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register -AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register -AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register -AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register -AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register -// - ========== Register definition for DBGU peripheral ========== -AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register -AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register -AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register -AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register -AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register -AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register -AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register -AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register -AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register -AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register -AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register -AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register -// - ========== Register definition for PIOA peripheral ========== -AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr -AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register -AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register -AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register -AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register -AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register -AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register -AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register -AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register -AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register -AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register -AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register -AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register -AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register -AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register -AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register -AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register -AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register -AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register -AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register -AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register -AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register -AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register -AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register -AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register -AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register -AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register -AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register -AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register -// - ========== Register definition for PIOB peripheral ========== -AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register -AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register -AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register -AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register -AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register -AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register -AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register -AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register -AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register -AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register -AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register -AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register -AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register -AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register -AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register -AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register -AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr -AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register -AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register -AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register -AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register -AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register -AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register -AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register -AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register -AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register -AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register -AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register -AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register -// - ========== Register definition for CKGR peripheral ========== -AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register -AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register -AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register -// - ========== Register definition for PMC peripheral ========== -AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register -AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register -AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register -AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register -AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register -AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register -AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register -AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register -AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register -AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register -AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register -AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register -AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register -AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register -AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register -// - ========== Register definition for RSTC peripheral ========== -AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register -AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register -AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register -// - ========== Register definition for RTTC peripheral ========== -AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register -AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register -AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register -AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register -// - ========== Register definition for PITC peripheral ========== -AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register -AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register -AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register -AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register -// - ========== Register definition for WDTC peripheral ========== -AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register -AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register -AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register -// - ========== Register definition for VREG peripheral ========== -AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register -// - ========== Register definition for MC peripheral ========== -AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register -AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register -AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register -AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register -AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register -AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register -// - ========== Register definition for PDC_SPI1 peripheral ========== -AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register -AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register -AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register -AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register -AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register -AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register -AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register -AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register -AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register -AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register -// - ========== Register definition for SPI1 peripheral ========== -AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register -AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register -AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register -AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register -AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register -AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register -AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register -AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register -AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register -// - ========== Register definition for PDC_SPI0 peripheral ========== -AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register -AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register -AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register -AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register -AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register -AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register -AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register -AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register -AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register -AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register -// - ========== Register definition for SPI0 peripheral ========== -AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register -AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register -AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register -AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register -AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register -AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register -AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register -AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register -AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register -// - ========== Register definition for PDC_US1 peripheral ========== -AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register -AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register -AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register -AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register -AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register -AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register -AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register -AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register -AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register -AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register -// - ========== Register definition for US1 peripheral ========== -AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register -AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register -AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register -AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register -AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register -AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register -AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register -AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register -AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register -AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register -AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register -AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register -AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register -AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register -// - ========== Register definition for PDC_US0 peripheral ========== -AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register -AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register -AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register -AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register -AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register -AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register -AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register -AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register -AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register -AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register -// - ========== Register definition for US0 peripheral ========== -AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register -AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register -AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register -AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register -AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register -AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register -AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register -AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register -AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register -AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register -AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register -AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register -AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register -AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register -// - ========== Register definition for PDC_SSC peripheral ========== -AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register -AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register -AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register -AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register -AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register -AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register -AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register -AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register -AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register -AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register -// - ========== Register definition for SSC peripheral ========== -AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register -AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register -AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register -AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register -AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register -AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister -AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register -AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register -AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register -AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register -AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register -AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register -AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register -AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register -// - ========== Register definition for TWI peripheral ========== -AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register -AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register -AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register -AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register -AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register -AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register -AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register -AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register -AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register -AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register -// - ========== Register definition for PWMC_CH3 peripheral ========== -AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register -AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved -AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register -AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register -AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register -AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register -// - ========== Register definition for PWMC_CH2 peripheral ========== -AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved -AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register -AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register -AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register -AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register -AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register -// - ========== Register definition for PWMC_CH1 peripheral ========== -AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved -AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register -AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register -AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register -AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register -AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register -// - ========== Register definition for PWMC_CH0 peripheral ========== -AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved -AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register -AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register -AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register -AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register -AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register -// - ========== Register definition for PWMC peripheral ========== -AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register -AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register -AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register -AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register -AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register -AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register -AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register -AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register -AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register -// - ========== Register definition for UDP peripheral ========== -AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register -AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register -AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register -AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register -AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register -AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register -AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register -AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register -AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register -AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register -AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register -AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register -// - ========== Register definition for TC0 peripheral ========== -AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register -AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C -AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B -AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register -AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register -AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A -AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register -AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value -AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register -// - ========== Register definition for TC1 peripheral ========== -AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B -AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register -AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register -AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register -AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register -AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A -AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C -AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register -AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value -// - ========== Register definition for TC2 peripheral ========== -AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register -AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value -AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A -AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B -AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register -AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register -AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C -AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register -AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register -// - ========== Register definition for TCB peripheral ========== -AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register -AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register -// - ========== Register definition for CAN_MB0 peripheral ========== -AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register -AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register -AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register -AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register -AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register -AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register -AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register -AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register -// - ========== Register definition for CAN_MB1 peripheral ========== -AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register -AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register -AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register -AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register -AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register -AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register -AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register -AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register -// - ========== Register definition for CAN_MB2 peripheral ========== -AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register -AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register -AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register -AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register -AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register -AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register -AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register -AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register -// - ========== Register definition for CAN_MB3 peripheral ========== -AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register -AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register -AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register -AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register -AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register -AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register -AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register -AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register -// - ========== Register definition for CAN_MB4 peripheral ========== -AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register -AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register -AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register -AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register -AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register -AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register -AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register -AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB5 peripheral ========== -AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register -AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register -AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register -AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register -AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register -AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register -AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register -AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB6 peripheral ========== -AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register -AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register -AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register -AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register -AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register -AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register -AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register -AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register -// - ========== Register definition for CAN_MB7 peripheral ========== -AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register -AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register -AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register -AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register -AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register -AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register -AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register -AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register -// - ========== Register definition for CAN peripheral ========== -AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register -AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register -AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register -AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register -AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register -AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register -AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register -AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register -AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register -AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register -AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register -AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register -// - ========== Register definition for EMAC peripheral ========== -AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register -AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes -AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes -AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register -AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register -AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register -AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register -AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register -AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register -AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register -AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes -AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register -AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes -AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register -AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register -AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register -AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register -AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register -AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0] -AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer -AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register -AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register -AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes -AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register -AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register -AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register -AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer -AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register -AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register -AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32] -AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register -AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register -AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register -AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register -AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register -AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register -AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register -AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register -AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register -AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register -AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register -AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes -AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register -AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register -AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes -AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register -AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes -AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register -AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register -// - ========== Register definition for PDC_ADC peripheral ========== -AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register -AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register -AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register -AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register -AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register -AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register -AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register -AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register -AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register -AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register -// - ========== Register definition for ADC peripheral ========== -AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 -AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 -AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 -AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 -AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register -AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register -AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 -AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 -AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register -AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register -AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register -AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 -AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 -AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register -AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register -AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register -AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register -AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register -// - ========== Register definition for PDC_AES peripheral ========== -AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register -AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register -AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register -AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register -AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register -AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register -AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register -AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register -AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register -AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register -// - ========== Register definition for AES peripheral ========== -AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register -AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register -AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register -AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register -AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register -AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register -AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register -AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register -AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register -AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register -AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register -// - ========== Register definition for PDC_TDES peripheral ========== -AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register -AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register -AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register -AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register -AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register -AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register -AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register -AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register -AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register -AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register -// - ========== Register definition for TDES peripheral ========== -AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register -AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register -AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register -AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register -AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register -AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register -AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register -AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register -AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register -AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register -AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register -AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register -AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register - -// - ***************************************************************************** -// - PIO DEFINITIONS FOR AT91SAM7X128 -// - ***************************************************************************** -AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 -AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data -AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 -AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data -AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 -AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data -AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 -AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock -AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 -AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0 -AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 -AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 -AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1 -AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 -AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input -AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 -AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave -AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 -AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave -AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 -AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock -AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 -AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive -AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 -AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock -AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 -AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit -AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 -AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync -AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0 -AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 -AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock -AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock -AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 -AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data -AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave -AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 -AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data -AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave -AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 -AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock -AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 -AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync -AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 -AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data -AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3 -AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 -AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data -AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 -AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input -AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 -AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send -AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 -AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0 -AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 -AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send -AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 -AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data -AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 -AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data -AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 -AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock -AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 -AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send -AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 -AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send -AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0 -AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock -AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1 -AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable -AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10 -AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2 -AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11 -AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3 -AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12 -AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error -AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input -AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13 -AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2 -AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14 -AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3 -AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15 -AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid -AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16 -AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected -AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17 -AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock -AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18 -AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec -AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger -AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19 -AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0 -AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input -AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2 -AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0 -AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20 -AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1 -AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21 -AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2 -AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22 -AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3 -AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23 -AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A -AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect -AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24 -AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B -AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready -AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25 -AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A -AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready -AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26 -AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B -AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator -AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27 -AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A -AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0 -AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28 -AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B -AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1 -AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29 -AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1 -AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2 -AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3 -AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1 -AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30 -AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2 -AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3 -AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4 -AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5 -AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0 -AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6 -AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1 -AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7 -AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error -AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8 -AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock -AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9 -AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output - -// - ***************************************************************************** -// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 -// - ***************************************************************************** -AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) -AT91C_ID_SYS EQU ( 1) ;- System Peripheral -AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A -AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B -AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0 -AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1 -AT91C_ID_US0 EQU ( 6) ;- USART 0 -AT91C_ID_US1 EQU ( 7) ;- USART 1 -AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller -AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface -AT91C_ID_PWMC EQU (10) ;- PWM Controller -AT91C_ID_UDP EQU (11) ;- USB Device Port -AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 -AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 -AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 -AT91C_ID_CAN EQU (15) ;- Control Area Network Controller -AT91C_ID_EMAC EQU (16) ;- Ethernet MAC -AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter -AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit -AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard -AT91C_ID_20_Reserved EQU (20) ;- Reserved -AT91C_ID_21_Reserved EQU (21) ;- Reserved -AT91C_ID_22_Reserved EQU (22) ;- Reserved -AT91C_ID_23_Reserved EQU (23) ;- Reserved -AT91C_ID_24_Reserved EQU (24) ;- Reserved -AT91C_ID_25_Reserved EQU (25) ;- Reserved -AT91C_ID_26_Reserved EQU (26) ;- Reserved -AT91C_ID_27_Reserved EQU (27) ;- Reserved -AT91C_ID_28_Reserved EQU (28) ;- Reserved -AT91C_ID_29_Reserved EQU (29) ;- Reserved -AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) -AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) - -// - ***************************************************************************** -// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 -// - ***************************************************************************** -AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address -AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address -AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address -AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address -AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address -AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address -AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address -AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address -AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address -AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address -AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address -AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address -AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address -AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address -AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address -AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address -AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address -AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address -AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address -AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address -AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address -AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address -AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address -AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address -AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address -AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address -AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address -AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address -AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address -AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address -AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address -AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address -AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address -AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address -AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address -AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address -AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address -AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address -AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address -AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address -AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address -AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address -AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address -AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address -AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address -AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address -AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address -AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address -AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address -AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address -AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address - -// - ***************************************************************************** -// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 -// - ***************************************************************************** -AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address -AT91C_ISRAM_SIZE EQU (0x00008000) ;- Internal SRAM size in byte (32 Kbyte) -AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address -AT91C_IFLASH_SIZE EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte) -#endif /* __IAR_SYSTEMS_ASM__ */ - - -#endif /* AT91SAM7X128_H */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h deleted file mode 100644 index 742f25c6c..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h +++ /dev/null @@ -1,4700 +0,0 @@ -// - ---------------------------------------------------------------------------- -// - ATMEL Microcontroller Software Support - ROUSSET - -// - ---------------------------------------------------------------------------- -// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// - ---------------------------------------------------------------------------- -// - File Name : AT91SAM7X256.h -// - Object : AT91SAM7X256 definitions -// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// - -// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// - ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -#ifdef __IAR_SYSTEMS_ICC__ - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) -#endif /* __IAR_SYSTEMS_ICC__ */ - -#ifdef __IAR_SYSTEMS_ASM__ - -// - Hardware register definition - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR System Peripherals -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// - ***************************************************************************** -// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level -AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level -AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level -AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type -AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive -AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered -AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered -AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered -// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status -AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status -// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode -AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// - ***************************************************************************** -// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable -AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable -AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable -AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable -// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Debug Unit -// - ***************************************************************************** -// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver -AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter -AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable -AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable -AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable -AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable -AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits -// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type -AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity -AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity -AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) -AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) -AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity -AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode -AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode -AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt -AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt -AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt -AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt -AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt -AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt -AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt -AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt -AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt -AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt -AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt -AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt -// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Clock Generator Controler -// - ***************************************************************************** -// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable -AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass -AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time -// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency -AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready -// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter -AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range -AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier -AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks -AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output -AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 -AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Power Management Controler -// - ***************************************************************************** -// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock -AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock -AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output -// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection -AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected -AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected -AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected -AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler -AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock -AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 -AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 -AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 -AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 -AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 -AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 -// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask -AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask -AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask -// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Reset Controller Interface -// - ***************************************************************************** -// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset -AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset -AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset -AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password -// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status -AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status -AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type -AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. -AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. -AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. -AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. -AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level -AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. -// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable -AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable -AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable -AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// - ***************************************************************************** -// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value -AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable -AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable -AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart -// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value -// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value -// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status -AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// - ***************************************************************************** -// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value -AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled -AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable -// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status -// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value -AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter -// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// - ***************************************************************************** -// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart -AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password -// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable -AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable -AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable -AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value -AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt -AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt -// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow -AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// - ***************************************************************************** -// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Memory Controller Interface -// - ***************************************************************************** -// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit -// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status -AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status -AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status -AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte -AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word -AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word -AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status -AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read -AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write -AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch -AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source -AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source -AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source -AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source -// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready -AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error -AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error -AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming -AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State -AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations -AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations -AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations -AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations -AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number -// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command -AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. -AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. -AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. -AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. -AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. -AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number -AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key -// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status -AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status -AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status -AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status -AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status -AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status -AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status -AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status -AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status -AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status -AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status -AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status -AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status -AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status -AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status -AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status -AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status -AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status -AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status -AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status -AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status -AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status -AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Serial Parallel Interface -// - ***************************************************************************** -// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable -AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable -AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset -AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer -// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode -AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select -AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select -AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select -AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode -AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection -AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection -AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection -AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select -AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects -// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data -AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data -AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full -AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty -AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error -AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status -AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer -AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer -AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt -AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt -AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt -AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt -AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status -// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity -AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase -AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer -AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer -AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer -AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer -AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer -AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer -AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer -AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer -AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer -AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer -AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer -AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK -AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Usart -// - ***************************************************************************** -// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break -AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break -AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out -AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address -AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations -AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge -AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out -AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable -AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable -AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable -AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable -// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode -AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal -AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 -AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking -AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem -AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 -AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 -AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA -AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking -AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock -AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 -AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) -AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) -AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits -AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits -AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits -AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits -AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select -AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits -AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit -AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits -AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order -AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length -AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select -AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode -AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge -AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK -AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions -AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter -// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break -AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out -AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached -AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge -AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag -AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag -AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag -AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag -// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input -AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input -AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input -AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// - ***************************************************************************** -// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable -AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable -AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable -AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable -AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset -// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection -AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock -AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal -AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin -AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection -AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output -AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion -AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection -AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start -AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input -AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input -AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input -AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input -AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input -AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input -AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 -AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay -AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection -// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length -AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode -AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First -AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame -AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length -AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection -AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection -// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value -AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable -// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready -AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty -AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission -AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty -AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready -AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun -AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception -AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full -AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync -AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync -AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable -AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable -// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Two-wire Interface -// - ***************************************************************************** -// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition -AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition -AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled -AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled -AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset -// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size -AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address -AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address -AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address -AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address -AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction -AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address -// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider -AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider -AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider -// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed -AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY -AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY -AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error -AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error -AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged -// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR PWMC Channel Interface -// - ***************************************************************************** -// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) -AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment -AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity -AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period -// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle -// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period -// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter -// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// - ***************************************************************************** -// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. -AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A -AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) -AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. -AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B -AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) -// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 -AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 -AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 -AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 -// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR USB Device Interface -// - ***************************************************************************** -// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats -AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error -AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK -// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable -AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured -AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume -AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host -AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable -// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value -AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable -// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt -AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt -AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt -AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt -AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt -AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt -AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt -AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt -AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt -// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt -// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 -AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 -AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 -AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 -AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 -AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 -// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR -AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 -AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) -AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) -AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready -AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction -AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type -AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control -AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT -AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT -AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT -AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN -AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN -AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN -AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle -AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable -AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO -// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) -AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// - ***************************************************************************** -// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command -AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command -AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command -// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection -AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK -AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK -AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK -AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK -AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK -AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 -AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 -AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 -AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert -AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection -AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal -AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock -AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock -AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock -AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare -AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading -AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare -AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading -AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection -AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection -AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection -AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input -AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output -AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output -AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output -AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection -AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable -AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection -AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare -AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare -AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable -AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) -AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA -AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none -AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set -AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear -AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle -AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection -AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None -AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA -AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA -AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none -AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set -AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear -AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle -AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection -AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None -AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA -AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA -AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none -AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set -AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear -AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle -AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA -AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none -AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set -AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear -AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle -AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB -AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none -AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set -AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear -AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle -AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB -AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none -AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set -AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear -AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle -AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB -AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none -AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set -AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear -AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle -AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB -AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none -AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set -AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear -AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle -// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow -AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun -AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare -AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare -AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare -AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading -AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading -AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger -AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling -AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror -AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror -// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Interface -// - ***************************************************************************** -// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command -// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection -AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 -AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 -AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 -AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 -AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection -AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 -AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 -AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 -AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 -AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection -AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 -AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 -AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 -AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// - ***************************************************************************** -// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark -AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority -AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type -AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) -// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode -AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode -AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version -// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value -AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code -AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request -AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort -AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready -AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored -// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox -AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network Interface -// - ***************************************************************************** -// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable -AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode -AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode -AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame -AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame -AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode -AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze -AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat -// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag -AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag -AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag -AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag -AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag -AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag -AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag -AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag -AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag -AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag -AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag -AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag -AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag -AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag -AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag -AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag -AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag -AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag -AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag -AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag -AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag -AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag -AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag -AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag -AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error -AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error -AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error -AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error -AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error -// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy -AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy -AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy -// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment -AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment -AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment -AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment -AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler -AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode -// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field -// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter -AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter -// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field -// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// - ***************************************************************************** -// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. -AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. -AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. -AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. -AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. -AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. -AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. -AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. -AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. -AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. -AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. -AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame -AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame -// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. -AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. -AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. -AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. -AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. -AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable -AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. -AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. -AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. -AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) -AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8 -AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16 -AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32 -AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64 -AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) -AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) -AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer -AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable -AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS -AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) -AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS -// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go -AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame -AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) -// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) -AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) -AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) -AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) -AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) -AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) -AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) -AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) -// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) -AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) -AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) -AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) -AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) -// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII -// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address -AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable -AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable -AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable -// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// - ***************************************************************************** -// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset -AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion -// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable -AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. -AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection -AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 -AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 -AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 -AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 -AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 -AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 -AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger -AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. -AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution -AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution -AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode -AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection -AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time -AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time -// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 -AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 -AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 -AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 -AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 -AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 -AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 -AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 -// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion -AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion -AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion -AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion -AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion -AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion -AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion -AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion -AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error -AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error -AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error -AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error -AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error -AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error -AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error -AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error -AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready -AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun -AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer -AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt -// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted -// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data -// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// - ***************************************************************************** -// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- -AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing -AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset -AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading -// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode -AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay -AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode -AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet). -AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode -AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode. -AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode. -AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode. -AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode. -AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode. -AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode -AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size -AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit. -AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit. -AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit. -AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit. -AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit. -AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key -AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type -AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled. -AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled. -AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled. -AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled. -AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled. -// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY -AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End -AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End -AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full -AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty -AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection -// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status -AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode. -AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing. -AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing. -AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation. -AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation. -AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access. - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// - ***************************************************************************** -// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing -AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset -// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode -AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode -AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode -AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode -AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet). -AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode -AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode. -AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode. -AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode. -AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode. -AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode -AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size -AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit. -AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit. -AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit. -AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit. -// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY -AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End -AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End -AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full -AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty -AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection -// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status -AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode. -AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing. -AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing. -AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access. - -// - ***************************************************************************** -// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// - ***************************************************************************** -// - ========== Register definition for SYS peripheral ========== -// - ========== Register definition for AIC peripheral ========== -AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register -AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register -AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register -AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) -AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register -AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register -AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register -AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register -AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register -AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register -AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register -AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register -AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register -AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register -AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register -AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register -AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register -AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register -// - ========== Register definition for PDC_DBGU peripheral ========== -AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register -AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register -AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register -AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register -AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register -AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register -AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register -AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register -AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register -AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register -// - ========== Register definition for DBGU peripheral ========== -AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register -AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register -AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register -AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register -AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register -AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register -AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register -AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register -AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register -AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register -AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register -AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register -// - ========== Register definition for PIOA peripheral ========== -AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr -AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register -AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register -AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register -AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register -AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register -AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register -AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register -AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register -AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register -AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register -AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register -AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register -AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register -AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register -AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register -AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register -AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register -AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register -AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register -AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register -AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register -AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register -AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register -AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register -AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register -AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register -AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register -AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register -// - ========== Register definition for PIOB peripheral ========== -AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register -AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register -AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register -AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register -AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register -AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register -AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register -AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register -AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register -AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register -AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register -AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register -AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register -AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register -AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register -AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register -AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr -AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register -AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register -AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register -AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register -AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register -AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register -AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register -AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register -AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register -AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register -AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register -AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register -// - ========== Register definition for CKGR peripheral ========== -AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register -AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register -AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register -// - ========== Register definition for PMC peripheral ========== -AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register -AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register -AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register -AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register -AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register -AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register -AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register -AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register -AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register -AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register -AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register -AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register -AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register -AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register -AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register -// - ========== Register definition for RSTC peripheral ========== -AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register -AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register -AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register -// - ========== Register definition for RTTC peripheral ========== -AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register -AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register -AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register -AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register -// - ========== Register definition for PITC peripheral ========== -AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register -AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register -AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register -AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register -// - ========== Register definition for WDTC peripheral ========== -AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register -AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register -AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register -// - ========== Register definition for VREG peripheral ========== -AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register -// - ========== Register definition for MC peripheral ========== -AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register -AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register -AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register -AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register -AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register -AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register -// - ========== Register definition for PDC_SPI1 peripheral ========== -AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register -AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register -AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register -AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register -AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register -AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register -AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register -AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register -AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register -AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register -// - ========== Register definition for SPI1 peripheral ========== -AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register -AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register -AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register -AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register -AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register -AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register -AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register -AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register -AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register -// - ========== Register definition for PDC_SPI0 peripheral ========== -AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register -AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register -AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register -AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register -AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register -AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register -AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register -AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register -AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register -AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register -// - ========== Register definition for SPI0 peripheral ========== -AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register -AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register -AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register -AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register -AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register -AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register -AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register -AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register -AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register -// - ========== Register definition for PDC_US1 peripheral ========== -AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register -AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register -AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register -AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register -AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register -AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register -AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register -AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register -AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register -AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register -// - ========== Register definition for US1 peripheral ========== -AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register -AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register -AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register -AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register -AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register -AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register -AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register -AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register -AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register -AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register -AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register -AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register -AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register -AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register -// - ========== Register definition for PDC_US0 peripheral ========== -AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register -AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register -AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register -AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register -AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register -AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register -AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register -AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register -AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register -AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register -// - ========== Register definition for US0 peripheral ========== -AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register -AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register -AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register -AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register -AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register -AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register -AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register -AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register -AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register -AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register -AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register -AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register -AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register -AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register -// - ========== Register definition for PDC_SSC peripheral ========== -AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register -AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register -AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register -AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register -AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register -AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register -AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register -AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register -AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register -AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register -// - ========== Register definition for SSC peripheral ========== -AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register -AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register -AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register -AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register -AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register -AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister -AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register -AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register -AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register -AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register -AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register -AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register -AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register -AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register -// - ========== Register definition for TWI peripheral ========== -AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register -AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register -AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register -AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register -AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register -AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register -AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register -AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register -AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register -AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register -// - ========== Register definition for PWMC_CH3 peripheral ========== -AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register -AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved -AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register -AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register -AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register -AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register -// - ========== Register definition for PWMC_CH2 peripheral ========== -AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved -AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register -AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register -AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register -AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register -AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register -// - ========== Register definition for PWMC_CH1 peripheral ========== -AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved -AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register -AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register -AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register -AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register -AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register -// - ========== Register definition for PWMC_CH0 peripheral ========== -AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved -AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register -AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register -AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register -AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register -AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register -// - ========== Register definition for PWMC peripheral ========== -AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register -AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register -AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register -AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register -AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register -AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register -AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register -AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register -AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register -// - ========== Register definition for UDP peripheral ========== -AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register -AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register -AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register -AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register -AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register -AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register -AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register -AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register -AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register -AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register -AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register -AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register -// - ========== Register definition for TC0 peripheral ========== -AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register -AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C -AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B -AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register -AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register -AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A -AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register -AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value -AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register -// - ========== Register definition for TC1 peripheral ========== -AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B -AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register -AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register -AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register -AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register -AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A -AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C -AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register -AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value -// - ========== Register definition for TC2 peripheral ========== -AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register -AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value -AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A -AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B -AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register -AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register -AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C -AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register -AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register -// - ========== Register definition for TCB peripheral ========== -AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register -AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register -// - ========== Register definition for CAN_MB0 peripheral ========== -AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register -AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register -AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register -AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register -AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register -AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register -AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register -AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register -// - ========== Register definition for CAN_MB1 peripheral ========== -AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register -AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register -AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register -AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register -AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register -AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register -AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register -AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register -// - ========== Register definition for CAN_MB2 peripheral ========== -AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register -AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register -AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register -AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register -AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register -AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register -AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register -AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register -// - ========== Register definition for CAN_MB3 peripheral ========== -AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register -AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register -AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register -AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register -AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register -AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register -AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register -AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register -// - ========== Register definition for CAN_MB4 peripheral ========== -AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register -AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register -AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register -AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register -AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register -AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register -AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register -AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB5 peripheral ========== -AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register -AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register -AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register -AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register -AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register -AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register -AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register -AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB6 peripheral ========== -AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register -AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register -AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register -AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register -AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register -AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register -AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register -AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register -// - ========== Register definition for CAN_MB7 peripheral ========== -AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register -AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register -AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register -AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register -AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register -AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register -AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register -AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register -// - ========== Register definition for CAN peripheral ========== -AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register -AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register -AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register -AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register -AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register -AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register -AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register -AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register -AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register -AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register -AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register -AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register -// - ========== Register definition for EMAC peripheral ========== -AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register -AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes -AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes -AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register -AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register -AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register -AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register -AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register -AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register -AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register -AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes -AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register -AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes -AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register -AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register -AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register -AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register -AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register -AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0] -AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer -AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register -AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register -AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes -AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register -AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register -AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register -AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer -AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register -AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register -AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32] -AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register -AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register -AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register -AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register -AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register -AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register -AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register -AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register -AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register -AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register -AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register -AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes -AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register -AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register -AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes -AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register -AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes -AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register -AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register -// - ========== Register definition for PDC_ADC peripheral ========== -AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register -AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register -AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register -AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register -AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register -AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register -AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register -AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register -AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register -AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register -// - ========== Register definition for ADC peripheral ========== -AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 -AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 -AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 -AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 -AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register -AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register -AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 -AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 -AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register -AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register -AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register -AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 -AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 -AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register -AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register -AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register -AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register -AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register -// - ========== Register definition for PDC_AES peripheral ========== -AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register -AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register -AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register -AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register -AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register -AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register -AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register -AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register -AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register -AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register -// - ========== Register definition for AES peripheral ========== -AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register -AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register -AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register -AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register -AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register -AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register -AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register -AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register -AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register -AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register -AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register -// - ========== Register definition for PDC_TDES peripheral ========== -AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register -AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register -AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register -AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register -AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register -AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register -AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register -AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register -AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register -AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register -// - ========== Register definition for TDES peripheral ========== -AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register -AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register -AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register -AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register -AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register -AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register -AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register -AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register -AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register -AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register -AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register -AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register -AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register - -// - ***************************************************************************** -// - PIO DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 -AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data -AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 -AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data -AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 -AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data -AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 -AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock -AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 -AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0 -AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 -AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 -AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1 -AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 -AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input -AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 -AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave -AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 -AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave -AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 -AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock -AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 -AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive -AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 -AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock -AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 -AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit -AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 -AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync -AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0 -AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 -AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock -AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock -AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 -AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data -AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave -AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 -AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data -AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave -AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 -AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock -AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 -AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync -AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 -AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data -AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3 -AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 -AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data -AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 -AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input -AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 -AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send -AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 -AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0 -AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 -AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send -AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 -AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data -AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 -AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data -AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 -AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock -AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 -AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send -AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 -AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send -AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0 -AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock -AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1 -AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable -AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10 -AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2 -AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11 -AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3 -AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12 -AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error -AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input -AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13 -AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2 -AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14 -AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3 -AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15 -AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid -AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16 -AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected -AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17 -AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock -AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18 -AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec -AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger -AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19 -AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0 -AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input -AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2 -AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0 -AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20 -AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1 -AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21 -AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2 -AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22 -AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3 -AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23 -AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A -AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect -AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24 -AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B -AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready -AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25 -AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A -AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready -AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26 -AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B -AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator -AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27 -AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A -AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0 -AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28 -AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B -AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1 -AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29 -AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1 -AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2 -AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3 -AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1 -AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30 -AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2 -AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3 -AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4 -AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5 -AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0 -AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6 -AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1 -AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7 -AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error -AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8 -AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock -AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9 -AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output - -// - ***************************************************************************** -// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) -AT91C_ID_SYS EQU ( 1) ;- System Peripheral -AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A -AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B -AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0 -AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1 -AT91C_ID_US0 EQU ( 6) ;- USART 0 -AT91C_ID_US1 EQU ( 7) ;- USART 1 -AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller -AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface -AT91C_ID_PWMC EQU (10) ;- PWM Controller -AT91C_ID_UDP EQU (11) ;- USB Device Port -AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 -AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 -AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 -AT91C_ID_CAN EQU (15) ;- Control Area Network Controller -AT91C_ID_EMAC EQU (16) ;- Ethernet MAC -AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter -AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit -AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard -AT91C_ID_20_Reserved EQU (20) ;- Reserved -AT91C_ID_21_Reserved EQU (21) ;- Reserved -AT91C_ID_22_Reserved EQU (22) ;- Reserved -AT91C_ID_23_Reserved EQU (23) ;- Reserved -AT91C_ID_24_Reserved EQU (24) ;- Reserved -AT91C_ID_25_Reserved EQU (25) ;- Reserved -AT91C_ID_26_Reserved EQU (26) ;- Reserved -AT91C_ID_27_Reserved EQU (27) ;- Reserved -AT91C_ID_28_Reserved EQU (28) ;- Reserved -AT91C_ID_29_Reserved EQU (29) ;- Reserved -AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) -AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) - -// - ***************************************************************************** -// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address -AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address -AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address -AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address -AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address -AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address -AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address -AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address -AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address -AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address -AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address -AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address -AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address -AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address -AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address -AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address -AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address -AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address -AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address -AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address -AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address -AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address -AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address -AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address -AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address -AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address -AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address -AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address -AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address -AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address -AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address -AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address -AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address -AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address -AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address -AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address -AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address -AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address -AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address -AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address -AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address -AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address -AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address -AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address -AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address -AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address -AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address -AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address -AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address -AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address -AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address - -// - ***************************************************************************** -// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address -AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte) -AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address -AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte) -#endif /* __IAR_SYSTEMS_ASM__ */ - - -#endif /* AT91SAM7X256_H */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h deleted file mode 100644 index 29b2f53d5..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h +++ /dev/null @@ -1,105 +0,0 @@ -/* Generic MII registers. */ - -#define MII_BMCR 0x00 /* Basic mode control register */ -#define MII_BMSR 0x01 /* Basic mode status register */ -#define MII_PHYSID1 0x02 /* PHYS ID 1 */ -#define MII_PHYSID2 0x03 /* PHYS ID 2 */ -#define MII_ADVERTISE 0x04 /* Advertisement control reg */ -#define MII_LPA 0x05 /* Link partner ability reg */ -#define MII_EXPANSION 0x06 /* Expansion register */ -#define MII_DCOUNTER 0x12 /* Disconnect counter */ -#define MII_FCSCOUNTER 0x13 /* False carrier counter */ -#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ -#define MII_RERRCOUNTER 0x15 /* Receive error counter */ -#define MII_SREVISION 0x16 /* Silicon revision */ -#define MII_RESV1 0x17 /* Reserved... */ -#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ -#define MII_PHYADDR 0x19 /* PHY address */ -#define MII_RESV2 0x1a /* Reserved... */ -#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ -#define MII_NCONFIG 0x1c /* Network interface config */ - -/* Basic mode control register. */ -#define BMCR_RESV 0x007f /* Unused... */ -#define BMCR_CTST 0x0080 /* Collision test */ -#define BMCR_FULLDPLX 0x0100 /* Full duplex */ -#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ -#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ -#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ -#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ -#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ -#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ -#define BMCR_RESET 0x8000 /* Reset the DP83840 */ - -/* Basic mode status register. */ -#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ -#define BMSR_JCD 0x0002 /* Jabber detected */ -#define BMSR_LSTATUS 0x0004 /* Link status */ -#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ -#define BMSR_RFAULT 0x0010 /* Remote fault detected */ -#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ -#define BMSR_RESV 0x07c0 /* Unused... */ -#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ -#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ -#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ -#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ -#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ - -/* Advertisement control register. */ -#define ADVERTISE_SLCT 0x001f /* Selector bits */ -#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ -#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ -#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ -#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ -#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ -#define ADVERTISE_RESV 0x1c00 /* Unused... */ -#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ - -#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) -#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) - -/* Link partner ability register. */ -#define LPA_SLCT 0x001f /* Same as advertise selector */ -#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ -#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ -#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ -#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ -#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ -#define LPA_RESV 0x1c00 /* Unused... */ -#define LPA_RFAULT 0x2000 /* Link partner faulted */ -#define LPA_LPACK 0x4000 /* Link partner acked us */ -#define LPA_NPAGE 0x8000 /* Next page bit */ - -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) - -/* Expansion register for auto-negotiation. */ -#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ -#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ -#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ -#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ -#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ -#define EXPANSION_RESV 0xffe0 /* Unused... */ - -/* N-way test register. */ -#define NWAYTEST_RESV1 0x00ff /* Unused... */ -#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ -#define NWAYTEST_RESV2 0xfe00 /* Unused... */ - -#define SPEED_10 10 -#define SPEED_100 100 - -/* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 - -/* PHY ID */ -#define MII_DM9161_ID 0x0181b8a0 -#define MII_AM79C875_ID 0x00225540 /* 0x00225541 */ - -#define AT91C_PHY_ADDR 31 diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/main.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/main.c deleted file mode 100644 index c1080e43f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/main.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * Creates all the application tasks, then starts the scheduler. - * - * A task is also created called "uIP". This executes the uIP stack and small - * WEB server sample. All the other tasks are from the set of standard - * demo tasks. The WEB documentation provides more details of the standard - * demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check the status of all the other demo application - * tasks. LED mainCHECK_LED is toggled every three seconds by the check task - * should no error conditions be detected in any of the standard demo tasks. - * The toggle rate increasing to 500ms indicates that at least one error has - * been detected. - */ - - -/* Standard includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "partest.h" -#include "PollQ.h" -#include "dynamic.h" -#include "semtest.h" -#include "flash.h" -#include "integer.h" -#include "flop.h" -#include "BlockQ.h" -#include "death.h" -#include "uip_task.h" - -/*-----------------------------------------------------------*/ - -/* Priorities/stacks for the demo application tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainUIP_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainUIP_TASK_STACK_SIZE ( 250 ) - -/* The rate at which the on board LED will toggle when there is/is not an -error. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) - -/* The LED used by the check task to indicate the system status. */ -#define mainCHECK_LED ( 3 ) -/*-----------------------------------------------------------*/ - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. - */ -static long prvCheckOtherTasksAreStillRunning( void ); - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Configure the processor for use with the Atmel demo board. This is very - * minimal as most of the setup is performed in the startup code. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -int main( void ) -{ - /* Configure the processor. */ - prvSetupHardware(); - - /* Setup the port used to flash the LED's. */ - vParTestInitialise(); - - /* Start the task that handles the TCP/IP and WEB server functionality. */ - xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL ); - - /* Start the demo/test application tasks. These are created in addition - to the TCP/IP task for demonstration and test purposes. */ - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartLEDFlashTasks( mainFLASH_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartMathTasks( tskIDLE_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Must be last to get created. */ - vCreateSuicidalTasks( mainDEATH_PRIORITY ); - - /* Now all the tasks have been started - start the scheduler. */ - vTaskStartScheduler(); - - /* Should never reach here because the tasks should now be executing! */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* When using the JTAG debugger the hardware is not always initialised to - the correct default state. This line just ensures that this does not - cause all interrupts to be masked at the start. */ - AT91C_BASE_AIC->AIC_EOICR = 0; - - /* Most setup is performed by the low level init function called from the - startup asm file. - - Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as - well as the UART Tx line. */ - AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, LED_MASK ); - - /* Enable the peripheral clock. */ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA ); - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOB ) ; - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_EMAC ) ; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; -TickType_t xLastWakeTime; - - /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() - functions correctly. */ - xLastWakeTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the Check LED flash rate will increase. */ - for( ;; ) - { - /* Delay until it is time to execute again. The delay period is - shorter following an error. */ - vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); - - /* Check all the standard demo application tasks are executing without - error. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - vParTestToggleLED( mainCHECK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static long prvCheckOtherTasksAreStillRunning( void ) -{ -long lReturn = ( long ) pdPASS; - - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - return lReturn; -} - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac deleted file mode 100644 index 277ca1f94..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac +++ /dev/null @@ -1,194 +0,0 @@ -// --------------------------------------------------------- -// Microcontroller Software Support - ROUSSET - -// --------------------------------------------------------- -// The software is delivered "AS IS" without warranty or -// condition of any kind, either express, implied or -// statutory. This includes without limitation any warranty -// or condition with respect to merchantability or fitness -// for any particular purpose, or against the infringements of -// intellectual property rights of others. -// --------------------------------------------------------- -// File: SAM7.mac -// -// 1.0 08/Mar/04 JPP : Creation -// 1.1 23/Mar/05 JPP : Change Variable name -// -// $Revision: 1.5 $ -// -// --------------------------------------------------------- - -__var __mac_i; -__var __mac_pt; - -execUserReset() -{ - AIC(); -//* Watchdog Disable - Watchdog(); -} - -execUserPreload() -{ -//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area - CheckRemap(); -//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R - __mac_i =__readMemory32(0xFFFFF240,"Memory"); - __message " ---------------------------------------- Chip ID 0x",__mac_i:%X; - __mac_i =__readMemory32(0xFFFFF244,"Memory"); - __message " ---------------------------------------- Extention 0x",__mac_i:%X; -//* Get the chip status - -//* Init AIC - AIC(); -//* Watchdog Disable - Watchdog(); - -} - - -//----------------------------------------------------------------------------- -// Watchdog -//------------------------------- -// Normally, the Watchdog is enable at the reset for load it's preferable to -// Disable. -//----------------------------------------------------------------------------- -Watchdog() -{ -//* Watchdog Disable -// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS; - __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); - __message "------------------------------- Watchdog Disable ----------------------------------------"; -} - - -//----------------------------------------------------------------------------- -// Check Remap -//------------- -//----------------------------------------------------------------------------- -CheckRemap() -{ -//* Read the value at 0x0 - __mac_i =__readMemory32(0x00000000,"Memory"); - __mac_i =__mac_i+1; - __writeMemory32(__mac_i,0x00,"Memory"); - __mac_pt =__readMemory32(0x00000000,"Memory"); - - if (__mac_i == __mac_pt) - { - __message "------------------------------- The Remap is done ----------------------------------------"; -//* Toggel RESET The remap - __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); - - } else { - __message "------------------------------- The Remap is NOT -----------------------------------------"; - } - -} - - -execUserSetup() -{ - ini(); - __message "-------------------------------Set PC ----------------------------------------"; - __writeMemory32(0x00000000,0xB4,"Register"); -} - -//----------------------------------------------------------------------------- -// Reset the Interrupt Controller -//------------------------------- -// Normally, the code is executed only if a reset has been actually performed. -// So, the AIC initialization resumes at setting up the default vectors. -//----------------------------------------------------------------------------- -AIC() -{ -// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; - __writeMemory32(0xffffffff,0xFFFFF124,"Memory"); - __writeMemory32(0xffffffff,0xFFFFF128,"Memory"); -// disable peripheral clock Peripheral Clock Disable Register - __writeMemory32(0xffffffff,0xFFFFFC14,"Memory"); - -// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register - __readMemory32(0xFFFA0020,"Memory"); - __readMemory32(0xFFFA0060,"Memory"); - __readMemory32(0xFFFA00A0,"Memory"); - - for (__mac_i=0;__mac_i < 8; __mac_i++) - { - // AT91C_BASE_AIC->AIC_EOICR - __mac_pt = __readMemory32(0xFFFFF130,"Memory"); - - } - __message "------------------------------- AIC 2 INIT ---------------------------------------------"; -} - -ini() -{ -__writeMemory32(0x0,0x00,"Register"); -__writeMemory32(0x0,0x04,"Register"); -__writeMemory32(0x0,0x08,"Register"); -__writeMemory32(0x0,0x0C,"Register"); -__writeMemory32(0x0,0x10,"Register"); -__writeMemory32(0x0,0x14,"Register"); -__writeMemory32(0x0,0x18,"Register"); -__writeMemory32(0x0,0x1C,"Register"); -__writeMemory32(0x0,0x20,"Register"); -__writeMemory32(0x0,0x24,"Register"); -__writeMemory32(0x0,0x28,"Register"); -__writeMemory32(0x0,0x2C,"Register"); -__writeMemory32(0x0,0x30,"Register"); -__writeMemory32(0x0,0x34,"Register"); -__writeMemory32(0x0,0x38,"Register"); - -// Set CPSR -__writeMemory32(0x0D3,0x98,"Register"); - - -} - -RG() -{ - -__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X; -__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X; -__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X; -__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X; -__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X; -__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X; -__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X; -__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X; -__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X; -__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X; -__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X; -__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X; -__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X; -__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X; -__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X; -__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X; -__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X; -__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X; -__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X; -__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X; -__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X; -__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X; -__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X; -__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X; -__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X; -__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X; -__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X; -__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X; -__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X; - -__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X; - -} - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac deleted file mode 100644 index 63228c346..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac +++ /dev/null @@ -1,227 +0,0 @@ -// --------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// --------------------------------------------------------- -// The software is delivered "AS IS" without warranty or -// condition of any kind, either express, implied or -// statutory. This includes without limitation any warranty -// or condition with respect to merchantability or fitness -// for any particular purpose, or against the infringements of -// intellectual property rights of others. -// --------------------------------------------------------- -// File: SAM7_RAM.mac -// -// 1.0 08/Mar/05 JPP : Creation -// 1.1 23/Mar/05 JPP : Change Variable name -// -// $Revision: 1.6 $ -// -// --------------------------------------------------------- - -__var __mac_i; -__var __mac_pt; -__var __mac_mem; -execUserReset() -{ - CheckNoRemap(); - ini(); - AIC(); - __message "-------------------------------Set PC Reset ----------------------------------"; - __writeMemory32(0x00000000,0xB4,"Register"); -} - -execUserPreload() -{ -//* __message "-------------------------------Set CPSR ----------------------------------"; - __writeMemory32(0xD3,0x98,"Register"); - __writeMemory32(0xffffffff,0xFFFFFC14,"Memory"); - PllSetting(); - //* Init AIC - AIC(); - -//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area - CheckNoRemap(); -//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R - __mac_i=__readMemory32(0xFFFFF240,"Memory"); - __message " ---------------------------------------- Chip ID 0x",__mac_i:%X; - __mac_i=__readMemory32(0xFFFFF244,"Memory"); - __message " ---------------------------------------- Extention 0x",__mac_i:%X; - __mac_i=__readMemory32(0xFFFFFF6C,"Memory"); - __message " ---------------------------------------- Flash Version 0x",__mac_i:%X; - -//* Watchdog Disable - Watchdog(); -//* RG(); -} -//----------------------------------------------------------------------------- -// PllSetting -//------------------------------- -// Set PLL -//----------------------------------------------------------------------------- -PllSetting() -{ -// -1- Enabling the Main Oscillator: -//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register - -//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600 -// AT91C_CKGR_MOSCEN )); //0x0000 0001 -__writeMemory32(0x00000601,0xFFFFFC20,"Memory"); - -// -2- Wait -// -3- Setting PLL and divider: -// - div by 5 Fin = 3,6864 =(18,432 / 5) -// - Mul 25+1: Fout = 95,8464 =(3,6864 *26) -// for 96 MHz the erroe is 0.16% -// Field out NOT USED = 0 -// PLLCOUNT pll startup time esrtimate at : 0.844 ms -// PLLCOUNT 28 = 0.000844 /(1/32768) -// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005 -// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00 -// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000 -__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory"); -// -2- Wait -// -5- Selection of Master Clock and Processor Clock -// select the PLL clock divided by 2 -// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003 -// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004 -__writeMemory32(0x00000007,0xFFFFFC30,"Memory"); - - - __message "------------------------------- PLL Enable ----------------------------------------"; -} - -//----------------------------------------------------------------------------- -// Watchdog -//------------------------------- -// Normally, the Watchdog is enable at the reset for load it's preferable to -// Disable. -//----------------------------------------------------------------------------- -Watchdog() -{ -//* Watchdog Disable -// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS; - __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); - __message "------------------------------- Watchdog Disable ----------------------------------------"; -} - -CheckNoRemap() -{ -//* Read the value at 0x0 - __mac_i =__readMemory32(0x00000000,"Memory"); - __mac_mem = __mac_i; - __mac_i=__mac_i+1; - __writeMemory32(__mac_i,0x00,"Memory"); - __mac_pt=__readMemory32(0x00000000,"Memory"); - - if (__mac_i == __mac_pt) - { - __message "------------------------------- The Remap is done ----------------------------------------"; - __writeMemory32( __mac_mem,0x00000000,"Memory"); - - } else { - __message "------------------------------- The Remap is NOT -----------------------------------------"; -//* Toggel RESET The remap - __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); - } - -} - -//----------------------------------------------------------------------------- -// Reset the Interrupt Controller -//------------------------------- -// Normally, the code is executed only if a reset has been actually performed. -// So, the AIC initialization resumes at setting up the default vectors. -//----------------------------------------------------------------------------- -AIC() -{ -// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; - __writeMemory32(0xffffffff,0xFFFFF124,"Memory"); - __writeMemory32(0xffffffff,0xFFFFF128,"Memory"); -// disable peripheral clock Peripheral Clock Disable Register - __writeMemory32(0xffffffff,0xFFFFFC14,"Memory"); - -// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register - __readMemory32(0xFFFA0020,"Memory"); - __readMemory32(0xFFFA0060,"Memory"); - __readMemory32(0xFFFA00A0,"Memory"); - for (__mac_i=0;__mac_i < 8; __mac_i++) - { - // AT91C_BASE_AIC->AIC_EOICR - __mac_pt = __readMemory32(0xFFFFF130,"Memory"); - - } - __message "------------------------------- AIC 2 INIT ---------------------------------------------"; -} - -ini() -{ -__writeMemory32(0x0,0x00,"Register"); -__writeMemory32(0x0,0x04,"Register"); -__writeMemory32(0x0,0x08,"Register"); -__writeMemory32(0x0,0x0C,"Register"); -__writeMemory32(0x0,0x10,"Register"); -__writeMemory32(0x0,0x14,"Register"); -__writeMemory32(0x0,0x18,"Register"); -__writeMemory32(0x0,0x1C,"Register"); -__writeMemory32(0x0,0x20,"Register"); -__writeMemory32(0x0,0x24,"Register"); -__writeMemory32(0x0,0x28,"Register"); -__writeMemory32(0x0,0x2C,"Register"); -__writeMemory32(0x0,0x30,"Register"); -__writeMemory32(0x0,0x34,"Register"); -__writeMemory32(0x0,0x38,"Register"); - -// Set CPSR -__writeMemory32(0x0D3,0x98,"Register"); - - -} - -RG() -{ - -__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X; -__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X; -__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X; -__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X; -__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X; -__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X; -__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X; -__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X; -__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X; -__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X; -__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X; -__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X; -__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X; -__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X; -__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X; -__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X; -__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X; -__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X; -__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X; -__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X; -__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X; -__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X; -__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X; -__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X; -__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X; -__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X; -__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X; -__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X; -__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X; -__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X; - -__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X; - -} - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_FLASH.icf b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_FLASH.icf deleted file mode 100644 index c9591f675..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_FLASH.icf +++ /dev/null @@ -1,43 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00100000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00100040; -define symbol __ICFEDIT_region_ROM_end__ = 0x0013FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x00200000; -define symbol __ICFEDIT_region_RAM_end__ = 0x0020FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x0; -define symbol __ICFEDIT_size_undstack__ = 0x0; -define symbol __ICFEDIT_size_abtstack__ = 0x0; -define symbol __ICFEDIT_size_heap__ = 0x0; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, - block UND_STACK, block ABT_STACK, block HEAP }; - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/at91sam7x-ek-flash.mac b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/at91sam7x-ek-flash.mac deleted file mode 100644 index 5d0997b1b..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/at91sam7x-ek-flash.mac +++ /dev/null @@ -1,73 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : SAM7_FLASH.mac -// Object : Generic Macro File for IAR -// 1.0 17/Aug/05 FBr : Creation -// ---------------------------------------------------------------------------- - -/********************************************************************* -* -* _InitRSTC() -* -* Function description -* Initializes the RSTC (Reset controller). -* This makes sense since the default is to not allow user resets, which makes it impossible to -* apply a second RESET via J-Link -*/ -_InitRSTC() { - __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset -} - -/********************************************************************* -* -* _InitPLL() -* Function description -* Initializes the PMC. -* 1. Enable the Main Oscillator -* 2. Configure PLL to 96MHz -* 3. Switch Master Clock (MCK) on PLL/2 = 48MHz -*/ -_InitPLL() { - - __message "Enable Main Oscillator"; - __writeMemory32(0x00000601,0xFFFFFc20,"Memory"); // MOSC - while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x1) ); - - __message "Set PLL to 96MHz"; - __writeMemory32(0x10191c05,0xFFFFFc2c,"Memory"); // LOCK - while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x4) ); - - __message "Set Master Clock to 48MHz"; - __writeMemory32(0x00000004,0xFFFFFc30,"Memory"); // MCKRDY - while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x8) ); - __writeMemory32(0x00000007,0xFFFFFc30,"Memory"); // MCKRDY - while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x8) ); - - // Set 1 WS for Flash accesses on each EFC - __writeMemory32(0x00480100,0xFFFFFF60,"Memory"); - __writeMemory32(0x00480100,0xFFFFFF70,"Memory"); -} - -/********************************************************************* -* -* execUserReset() : JTAG set initially to Full Speed -*/ -execUserReset() { - __message "execUserReset()"; - __hwReset(0); // Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz) - _InitPLL(); // Allow to debug at JTAG Full Speed - _InitRSTC(); // Enable User Reset to allow execUserReset() execution -} - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd deleted file mode 100644 index 98c02c31e..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd +++ /dev/null @@ -1,1379 +0,0 @@ - - - - 2 - - Flash Debug - - ARM - - 1 - - C-SPY - 2 - - 21 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 1 - - - - - - - - ANGEL_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - JLINK_ID - 2 - - 10 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - MACRAIGOR_ID - 2 - - 3 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - STLINK_ID - 2 - - 0 - 1 - 1 - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 - - - - - Flash Release - - ARM - - 0 - - C-SPY - 2 - - 21 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 0 - - - - - - - - ANGEL_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - JLINK_ID - 2 - - 10 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 2 - 1 - 0 - - - - - - - - - - MACRAIGOR_ID - 2 - - 3 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 0 - - - - - - - - - - - - - - - - - STLINK_ID - 2 - - 0 - 1 - 0 - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 0 - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 - - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp deleted file mode 100644 index 5a62fd664..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp +++ /dev/null @@ -1,1696 +0,0 @@ - - - - 2 - - Flash Debug - - ARM - - 1 - - General - 3 - - 17 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 21 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Flash Release - - ARM - - 0 - - General - 3 - - 17 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 21 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Demo Source - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - $PROJ_DIR$\..\Common\Minimal\death.c - - - $PROJ_DIR$\..\Common\Minimal\dynamic.c - - - $PROJ_DIR$\EMAC\EMAClISR.s79 - - - $PROJ_DIR$\..\Common\Minimal\flash.c - - - $PROJ_DIR$\..\Common\Minimal\flop.c - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\ParTest\ParTest.c - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - $PROJ_DIR$\EMAC\SAM7_EMAC.c - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - - - $PROJ_DIR$\uIP_Task.c - - - - FreeRTOS Source - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79 - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - - uIP Source - - http - - $PROJ_DIR$\uip\cgi.c - - - $PROJ_DIR$\uip\fs.c - - - $PROJ_DIR$\uip\httpd.c - - - - $PROJ_DIR$\uip\uip.c - - - $PROJ_DIR$\uip\uip_arch.c - - - $PROJ_DIR$\uip\uip_arp.c - - - - $PROJ_DIR$\SrcIAR\Cstartup.s - - - $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww deleted file mode 100644 index 2294aacb5..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\rtosdemo.ewp - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dbgdt b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dbgdt deleted file mode 100644 index 5085f2cdb..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dbgdt +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - 1892727 - - - - - - 200100 - - - 200188171100100010 - - - - - TabID-23416-30482 - Workspace - Workspace - - - rtosdemo - - - - 0 - - - - - TabID-12145-30489 - Debug Log - Debug-Log - - - - TabID-22894-30492 - Build - Build - - - - - 1 - TabID-18780-12821MemoryMemory2097764209776410000TabID-23506-14575WatchWatchpxCurrentTCBulCriticalNesting01761001001000TabID-4859-22480DisassemblyDisassembly0TabID-154-22568RegisterRegister0001CPSR0 - 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- - - - - rtosdemo/Flash Debug - - - - - - - - 288272727 - - 18115530877 - 221620 - - - - - - - - - - 010001055278946 - - - - - - - TabID-17425-14382 - Workspace - Workspace - - - rtosdemo - - - - 0 - - - TabID-4084-16269 - Build - Build - - - - TabID-23097-10324Debug LogDebug-LogTabID-27351-12303BreakpointsBreakpointsTabID-28796-16277Find in FilesFind-in-Files - - 0 - - - - - - TextEditorC:\E\temp\rc\1\FreeRTOS\Demo\uIP_Demo_IAR_ARM7\main.c000000100000010000001 - - - - - - - iaridepm.enu1-2-2774362-2-20000216667790224-2-21641682-2-21684166100238116904300 - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c deleted file mode 100644 index ddb648edd..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Modified from an original work that is Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $ - * - */ - -/* Standard includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "semphr.h" -#include "task.h" - -/* Demo app includes. */ -#include "SAM7_EMAC.h" - -/* uIP includes. */ -#undef HTONS -#include "uip.h" -#include "uip_arp.h" -#include "tapdev.h" -#include "httpd.h" - -/* The start of the uIP buffer, which will contain the frame headers. */ -#define pucUIP_Buffer ( ( struct uip_eth_hdr * ) &uip_buf[ 0 ] ) - -/* uIP update frequencies. */ -#define RT_CLOCK_SECOND ( configTICK_RATE_HZ ) -#define uipARP_FREQUENCY ( 20 ) -#define uipMAX_BLOCK_TIME ( RT_CLOCK_SECOND / 4 ) - -/*-----------------------------------------------------------*/ - -void vuIP_TASK( void *pvParameters ) -{ -/* The semaphore used by the EMAC ISR to indicate that an Rx frame is ready -for processing. */ -SemaphoreHandle_t xSemaphore = NULL; -portBASE_TYPE xARPTimer; -unsigned portBASE_TYPE uxPriority; -static volatile TickType_t xStartTime, xCurrentTime; - - /* Initialize the uIP TCP/IP stack. */ - uip_init(); - uip_arp_init(); - - /* Initialize the HTTP server. */ - httpd_init(); - - /* Initialise the local timers. */ - xStartTime = xTaskGetTickCount(); - xARPTimer = 0; - - /* Initialise the EMAC. A semaphore will be returned when this is - successful. This routine contains code that polls status bits. If the - Ethernet cable is not plugged in then this can take a considerable time. - To prevent this starving lower priority tasks of processing time we - lower our priority prior to the call, then raise it back again once the - initialisation is complete. */ - uxPriority = uxTaskPriorityGet( NULL ); - vTaskPrioritySet( NULL, tskIDLE_PRIORITY ); - while( xSemaphore == NULL ) - { - xSemaphore = xEMACInit(); - } - vTaskPrioritySet( NULL, uxPriority ); - - for( ;; ) - { - /* Let the network device driver read an entire IP packet - into the uip_buf. If it returns > 0, there is a packet in the - uip_buf buffer. */ - uip_len = ulEMACPoll(); - - /* Was a packet placed in the uIP buffer? */ - if( uip_len > 0 ) - { - /* A packet is present in the uIP buffer. We call the - appropriate ARP functions depending on what kind of packet we - have received. If the packet is an IP packet, we should call - uip_input() as well. */ - if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_IP ) ) - { - uip_arp_ipin(); - uip_input(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - lEMACSend(); - } - } - else if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_ARP ) ) - { - uip_arp_arpin(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - lEMACSend(); - } - } - } - else - { - /* The poll function returned 0, so no packet was - received. Instead we check if it is time that we do the - periodic processing. */ - xCurrentTime = xTaskGetTickCount(); - - if( ( xCurrentTime - xStartTime ) >= RT_CLOCK_SECOND ) - { - portBASE_TYPE i; - - /* Reset the timer. */ - xStartTime = xCurrentTime; - - /* Periodic check of all connections. */ - for( i = 0; i < UIP_CONNS; i++ ) - { - uip_periodic( i ); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - lEMACSend(); - } - } - - #if UIP_UDP - for( i = 0; i < UIP_UDP_CONNS; i++ ) - { - uip_udp_periodic( i ); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - tapdev_send(); - } - } - #endif /* UIP_UDP */ - - /* Periodically call the ARP timer function. */ - if( ++xARPTimer == uipARP_FREQUENCY ) - { - uip_arp_timer(); - xARPTimer = 0; - } - } - else - { - /* We did not receive a packet, and there was no periodic - processing to perform. Block for a fixed period. If a packet - is received during this period we will be woken by the ISR - giving us the Semaphore. */ - xSemaphoreTake( xSemaphore, uipMAX_BLOCK_TIME ); - } - } - } -} -/*-----------------------------------------------------------------------------------*/ - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h deleted file mode 100644 index aae424ba0..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef UIP_TASK_H -#define UIP_TASK_H - -/* The task that handles all uIP data. */ -void vuIP_TASK( void *pvParameters ); - -#endif - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/Makefile b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/Makefile deleted file mode 100644 index 61d3a06aa..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/Makefile +++ /dev/null @@ -1,74 +0,0 @@ -# Copyright (c) 2001, Adam Dunkels. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. All advertising materials mentioning features or use of this software -# must display the following acknowledgement: -# This product includes software developed by Adam Dunkels. -# 4. The name of the author may not be used to endorse or promote -# products derived from this software without specific prior -# written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# This file is part of the uIP TCP/IP stack. -# -# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $ -# - -CC=gcc -CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp -I../apps/telnet -fpack-struct - -%.o: - $(CC) $(CFLAGS) -c $(<:.o=.c) - - -uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o - -tapdev.o: tapdev.c uipopt.h -main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \ - tapdev.h -uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \ - ../apps/httpd/httpd.h -uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h - -uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \ - ../apps/httpd/httpd.h - $(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c - - -cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \ - ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h -fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \ - ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \ - ../apps/httpd/fsdata.c -fsdata.o: ../apps/httpd/fsdata.c -httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \ - ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \ - ../apps/httpd/fsdata.h ../apps/httpd/cgi.h - -clean: - rm -f *.o *~ *core uip - - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c deleted file mode 100644 index 748cc1b5d..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c +++ /dev/null @@ -1,225 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server script language C functions file. - * \author Adam Dunkels - * - * This file contains functions that are called by the web server - * scripts. The functions takes one argument, and the return value is - * interpreted as follows. A zero means that the function did not - * complete and should be invoked for the next packet as well. A - * non-zero value indicates that the function has completed and that - * the web server should move along to the next script line. - * - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $ - * - */ - -#include "uip.h" -#include "cgi.h" -#include "httpd.h" -#include "fs.h" - -#include -#include - -static u8_t print_stats(u8_t next); -static u8_t file_stats(u8_t next); -static u8_t tcp_stats(u8_t next); -static u8_t rtos_stats(u8_t next); - -cgifunction cgitab[] = { - print_stats, /* CGI function "a" */ - file_stats, /* CGI function "b" */ - tcp_stats, /* CGI function "c" */ - rtos_stats /* CGI function "d" */ -}; - -static const char closed[] = /* "CLOSED",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; -static const char syn_rcvd[] = /* "SYN-RCVD",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, - 0x44, 0}; -static const char syn_sent[] = /* "SYN-SENT",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, - 0x54, 0}; -static const char established[] = /* "ESTABLISHED",*/ -{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, - 0x45, 0x44, 0}; -static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x31, 0}; -static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x32, 0}; -static const char closing[] = /* "CLOSING",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x49, - 0x4e, 0x47, 0}; -static const char time_wait[] = /* "TIME-WAIT,"*/ -{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, - 0x49, 0x54, 0}; -static const char last_ack[] = /* "LAST-ACK"*/ -{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, - 0x4b, 0}; - -static const char *states[] = { - closed, - syn_rcvd, - syn_sent, - established, - fin_wait_1, - fin_wait_2, - closing, - time_wait, - last_ack}; - - -/*-----------------------------------------------------------------------------------*/ -/* print_stats: - * - * Prints out a part of the uIP statistics. The statistics data is - * written into the uip_appdata buffer. It overwrites any incoming - * packet. - */ -static u8_t -print_stats(u8_t next) -{ -#if UIP_STATISTICS - u16_t i, j; - u8_t *buf; - u16_t *databytes; - - if(next) { - /* If our last data has been acknowledged, we move on the next - chunk of statistics. */ - hs->count = hs->count + 4; - if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) { - /* We have printed out all statistics, so we return 1 to - indicate that we are done. */ - return 1; - } - } - - /* Write part of the statistics into the uip_appdata buffer. */ - databytes = (u16_t *)&uip_stat + hs->count; - buf = (u8_t *)uip_appdata; - - j = 4 + 1; - i = hs->count; - while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) { - sprintf((char *)buf, "%5u\r\n", *databytes); - ++databytes; - buf += 6; - ++i; - } - - /* Send the data. */ - uip_send(uip_appdata, buf - uip_appdata); - - return 0; -#else - return 1; -#endif /* UIP_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -static u8_t -file_stats(u8_t next) -{ - /* We use sprintf() to print the number of file accesses to a - particular file (given as an argument to the function in the - script). We then use uip_send() to actually send the data. */ - if(next) { - return 1; - } - uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4]))); - return 0; -} -/*-----------------------------------------------------------------------------------*/ -static u8_t -tcp_stats(u8_t next) -{ - struct uip_conn *conn; - - if(next) { - /* If the previously sent data has been acknowledged, we move - forward one connection. */ - if(++hs->count == UIP_CONNS) { - /* If all connections has been printed out, we are done and - return 1. */ - return 1; - } - } - - conn = &uip_conns[hs->count]; - if((conn->tcpstateflags & TS_MASK) == CLOSED) { - uip_send(uip_appdata, sprintf((char *)uip_appdata, - "--%u%u%c %c\r\n", - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' ')); - } else { - uip_send(uip_appdata, sprintf((char *)uip_appdata, - "%u.%u.%u.%u:%u%s%u%u%c %c\r\n", - htons(conn->ripaddr[0]) >> 8, - htons(conn->ripaddr[0]) & 0xff, - htons(conn->ripaddr[1]) >> 8, - htons(conn->ripaddr[1]) & 0xff, - htons(conn->rport), - states[conn->tcpstateflags & TS_MASK], - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' ')); - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ - -static u8_t -rtos_stats(u8_t next) -{ -static char cTraceBuffer[ 1024 ]; -extern void ( vTaskList )( char * ); - - vTaskList( cTraceBuffer ); - uip_send( ( void * ) cTraceBuffer, strlen( cTraceBuffer ) ); - - return 1; -} diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h deleted file mode 100644 index d85389b52..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP script language header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $ - * - */ - -#ifndef __CGI_H__ -#define __CGI_H__ - -typedef u8_t (* cgifunction)(u8_t next); - -/** - * A table containing pointers to C functions that can be called from - * a web server script. - */ -extern cgifunction cgitab[]; - -#endif /* __CGI_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm deleted file mode 100644 index ef91f42a8..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm +++ /dev/null @@ -1,66 +0,0 @@ -// Rowley C Compiler, runtime support. -// -// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited. -// -// This file may be distributed under the terms of the License Agreement -// provided with this software. -// -// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE -// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - -; Create sections - .data - .bss - -; Go to code section. - .code - -; Executed upon reset -__reset proc - -; Turn off watchdog. You can enable it in main() if required. - mov.w #0x5a80, &0x120 - -; Set up stack. - mov.w #RAM_Start_Address+RAM_Size, sp - -; Copy from initialised data section to data section. - mov.w #SFB(IDATA0), r15 - mov.w #data_init_begin, r14 - mov.w #data_init_end-data_init_begin, r13 - call #_memcpy - -; Zero the bss. Ensure the stack is not allocated in the bss! - mov.w #SFB(UDATA0), r15 - mov.w #0, r14 - mov.w #SFE(UDATA0)-SFB(UDATA0), r13 - call #_memset - -; Call user entry point void main(void). - call #_main - -; If main() returns, kick off again. - jmp __reset - endproc - -; Heap data structures; removed by the linker if the heap isn't used. - .break - .data - align WORD -___heap_start__:: - DW 0 - DW heap_size - DS heap_size-4 - -; Reset vector - .vectors - .keep - org 0x1e - dw __reset - -; Initialise the IDATA0 section by duplicating the contents into the -; CONST section and copying them on startup. - .const -data_init_begin: - .init "IDATA0" -data_init_end: diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs.c deleted file mode 100644 index a66eb8dc3..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs.c +++ /dev/null @@ -1,156 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server read-only file system code. - * \author Adam Dunkels - * - * A simple read-only filesystem. - */ - -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $ - */ - -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" - -#define NULL (void *)0 -#include "fsdata.c" - -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -static u16_t count[FS_NUMFILES]; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - -/*-----------------------------------------------------------------------------------*/ -static u8_t -fs_strcmp(const char *str1, const char *str2) -{ - u8_t i; - i = 0; - loop: - - if(str2[i] == 0 || - str1[i] == '\r' || - str1[i] == '\n') { - return 0; - } - - if(str1[i] != str2[i]) { - return 1; - } - - - ++i; - goto loop; -} -/*-----------------------------------------------------------------------------------*/ -int -fs_open(const char *name, struct fs_file *file) -{ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t i = 0; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - struct fsdata_file_noconst *f; - - for(f = (struct fsdata_file_noconst *)FS_ROOT; - f != NULL; - f = (struct fsdata_file_noconst *)f->next) { - - if(fs_strcmp(name, f->name) == 0) { - file->data = f->data; - file->len = f->len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - ++count[i]; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - - return 1; - } -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - ++i; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -void -fs_init(void) -{ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t i; - for(i = 0; i < FS_NUMFILES; i++) { - count[i] = 0; - } -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -u16_t fs_count -(char *name) -{ - struct fsdata_file_noconst *f; - u16_t i; - - i = 0; - for(f = (struct fsdata_file_noconst *)FS_ROOT; - f != NULL; - f = (struct fsdata_file_noconst *)f->next) { - - if(fs_strcmp(name, f->name) == 0) { - return count[i]; - } - ++i; - } - return 0; -} -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs.h deleted file mode 100644 index 65551ba41..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server read-only file system header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $ - */ -#ifndef __FS_H__ -#define __FS_H__ - -#include "uip.h" - -/** - * An open file in the read-only file system. - */ -struct fs_file { - char *data; /**< The actual file data. */ - int len; /**< The length of the file data. */ -}; - -/** - * Open a file in the read-only file system. - * - * \param name The name of the file. - * - * \param file The file pointer, which must be allocated by caller and - * will be filled in by the function. - */ -int fs_open(const char *name, struct fs_file *file); - -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -u16_t fs_count(char *name); -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - -/** - * Initialize the read-only file system. - */ -void fs_init(void); - -#endif /* __FS_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html deleted file mode 100644 index 8d6beec83..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html +++ /dev/null @@ -1 +0,0 @@ -

404 - file not found

\ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files deleted file mode 100644 index 58c45f30f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files +++ /dev/null @@ -1,26 +0,0 @@ -# This script shows the access statistics for different files on the -# web server. -# -# First, we include the HTML header. -i /files_header.html -# Print out the name of the file, and call the function that prints -# the access statistics of that file. -t /index.html -c b /index.html -t /control.html -c b /control.html -t /img/logo.png -c b /img/logo.png -t /404.html -c b /404.html -t /cgi/files -c b /cgi/files -t /cgi/stats -c b /cgi/stats -t /cgi/tcp -c b /cgi/tcp -t -# Include the HTML footer. -i /files_footer.plain -# End of script. -. \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos deleted file mode 100644 index 7772ea420..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos +++ /dev/null @@ -1,6 +0,0 @@ -t uIP Open Source Embedded TCP/IP Stack On FreeRTOS KernelFreeRTOS Homepage

AT91SAM7X Embedded WEB Server Demo
Using uIP and the FreeRTOS real time kernel

These pages are being served by an Atmel AT91SAM7X256 microcontroller, using Adam Dunkels open source uIP TCP/IP stack.

The uIP stack is executing from a single task under control of the FreeRTOS real time kernel. The table below shows the statistics for all the tasks in the demo applicaiton.

Task          State  Priority  Stack	#
************************************************

-c d
-t
-. - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats deleted file mode 100644 index 2c71c90dc..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats +++ /dev/null @@ -1,4 +0,0 @@ -i /stats_header.html -c a -i /stats_footer.plain -. diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp deleted file mode 100644 index 14efd3700..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp +++ /dev/null @@ -1,4 +0,0 @@ -i /tcp_header.html -c c -i /tcp_footer.plain -. \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html deleted file mode 100644 index 0d9352ce7..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html +++ /dev/null @@ -1,20 +0,0 @@ - - -AT91SAM7X Embedded WEB Server using uIP and FreeRTOS - - - - -Tasks | -Connections | -Files | -Statistics
-
- - - - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain deleted file mode 100644 index 0b6dceb4f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html deleted file mode 100644 index 20cf1c961..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html +++ /dev/null @@ -1,4 +0,0 @@ - - -
- diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/img/logo.png b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/img/logo.png deleted file mode 100644 index ef572dd381ab1341d77c9654fe1a1370c67b0bd0..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4373 zcmd^Dhd0}csL`0Un}?@HjH(7{ z8WH0~C^1^9_e|}cy1Kds1_nk(M#jd*=H}*> zmXRq{K@3X_jCe*SJQElX<{|L#6Zi!P0yn?i6ebFb5=F&{;!q+~jwGi*QqUl4 zXpyz_$a+R(BeOL#vvo6zbqmW4OY045hfN2^O-Hv)w@NFXu_h>8JXVu4r$0udh{pOlo8 znwpxPo}QJJm7SfPmzP&qSXfe0Qd(MCQBhGjj zRYWVw2C{R3++74Fn-mI#N~P}X?CkFDuAZ*0{azyhBr-tW_`R_XtZxFFlrsti zpis}KRDikz?ChTJ?gG0s8tvfV;OOY+=g*(}=le8(c6fex037@{|8aD2^z-89$;rv- z>FLSE$?3%@00Ny|oLyX8EaHX)|8(FY%*M(V`2P&h(lR(01Oktl8S2?Z;=h+&gK;lj z$E*yC$VNz2(P{CpGu#tf+oh*#pp?0CRSswRK^2*%UCy>d4=$HLd-v;0RCK6kV^TkS5u-^y2 z9TUI5-y7U}xpGVtQegr0gws^d%I0eY;~}sm+gE1+$UB!W?cmB`OFDz9t7(_w_jEpH zY=&^PN-8Q=stgEE_@#g=V3v8gRlf7V=m&H63AZF|P1}@~@2Lp2kD1+f%m_Op@j?1m z-TTA?&ivQv>!CMwPVCeem?0wDsP1NAc#ED|%CNu^vmH0PVFFWS4f-+95O4TfQ8s6R zbI+HMdJ~@}N)DNvkjlXsfO~5-DtbOVJwG*<_&s_LIrS~_T};bfen)!lB3O6ejIW`@ z8u{O?&A5uzPu06$=|P<+kXxyHJA;!fwV(&zTRlW1ax|v6qh2`hE6VI%(dWXQzx(VR zwVLz%cySSgzJa^s%qM-TcX~p2hMVV^(X30WK<&D*BK%|G^X2lJd(o52V~4V-MChQ8qAnP)Twk9f8${z- z?`mVmVd3{p479#vGMCn?8S&!IBc5Pdbj~>_@M8tp(Xk`#ZEwV}^vz3WBY*}xbX0Ja8t)}lZ&f2Z|CDj%GI-lh@N`{j6TQEw zzhb!K_dY_~M>3&ge0V1DLBlcS1(B7YBLGj9Qk`*FS7Ls&cuCfQRQ6hC{tDS!a(*aF zaygE`;SuHk6&w2xG7k*hacLiiCw z+9%Iy?M>fQz(TLczVW*Gr9~F@w#`8~@G#6iZU?<+?fWZB$gKH>Pfn-iFYbV4aSah& z2N=gnX?z`*kd)V9?jXNqSEIKB2?Hne&=v3?ur9?YKZz}!`0n0v@~qdhJ0gtQTGNXT+= z@@#wCs|(Ijd_b087~-r#Fn!wje%35kp0lqctefeYBg`VNz&edIpdz$Bqfi*a_MTn zdh*x@2cav7dsX9cnb#G@Vg_9?P+mS*6yeg+^kFVv;e*t1u!G8!=U*KE)-gqQ92vaM z$|zQ)Fn)Vkn$OdrDP~}yoi87-SwCJY}#qf-gHsxj|GVVmkDpIiNjYMoORLSYG!4 zDn@)P9+0yod#8JR5xfi2j0l+u*QdYT*LiSj-`db1eLT~bLwTBS?{xME>V8)UTYVQ^ zUaM;jRf0C$_JWx5zccgf$qj5a{N~Vt9f9kO7#N{{AqK2}du2S5G%Q>~kD$e!)Q>m;V4 zpO}h)gU?PVG!DL?55CEVZl>UA6q=jQ!_xMh zUn*DX=*v(W-hd=#F{g)^M>c3W$UwwX9GwK?kE5_vQfA_qjtN#0v*}emVf;zrlM$!i z*`YXVq7F#x3%rfjlS5EZ{4RlE~k;l?^6dg*Da8Rt57zOt>QVRc8UqeJcG=IqSAC&1H*v5>Qatx1btC^$ zSB*9~WBi*cg}2ZJd3ixVEZy4o0V%yCU2Evgv|dWvw~_mXFR(~Lrb*mytB>^48dV`} zm+8)>SziA-ykioRR%aq9(=m70(iGxU^7oZR_8Ct{rblq*Pt!)2e*1`VVN$qW%Px;a zH~ZJn(Z_!B&iot!jK`B<@+pSSY?KH8TrV`U2@8k5oxUA((sw=Bc`gXiG1%a`wt zBd&fg9bvqFH#?SKu8dr`mAkA>2$q~yG!Y^q`CrmoWNd;R{u+@p3##Pf-*qTXe|S(V z|8R+a`-c*3E5~3ook4jrXY^cpo~2YeKrbE3`d@0g;QgW5Pc$!K@5{OSS$aYp)~{UI z8G6#RAURFem>RgiD_hT74F1)q$omypAIG2EO5%D7S)gpbS2yXKBc3QU&RReS&n`G&S z`?4Y@^?fUjSGMQ8eA~7wUJBzPmx*9*$>{W~If)L1f}{^wz=SSSlUnf+ z$0XG2$nE8;Ch;;o8BVVqRAqqTf%=z%7N^3y zET=e|Z}Cw-jXM}bqk|P5OaCiq@hay{1#Y|Ixg@))Mlgp9T~7~g2EKCb%122X^3lgE z78cgP<)*qydfJ(ch{(DncXJxi8e-iiYOAF5_Cn>-6!lR&Ch_LbRk2iqV*s+J8*@Ed zu3>0!YfHg(&fZ%1&rH6oFC!H$?!OiatnoJ#oMi-iag6t8hse{5!73mxKD^p&>T z@&V*W$!Lngvn_U4Zkl406I0&f&nIl-Pv{DCbydA8M~mp|`IX%d&1)b9{))^w{%e1| zmNn0)m(9DZnHDY!?fLT1_RCBhx|eKTVdx-uRvZ_2R({ru{r7W%)tlm;)Ba^arf+9y zJNlz^8`|#?E)zTRMPEjs{WBsk7)u0D`_ zH%RsV6)5c%tE^$b&Wl+2Q1?n`r{{b(9D~137 diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/index.html b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/index.html deleted file mode 100644 index 626ff3780..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/index.html +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - -<body> -Your browser must support frames -</body> - - \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_footer.plain b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_footer.plain deleted file mode 100644 index 0b6dceb4f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_footer.plain +++ /dev/null @@ -1,3 +0,0 @@ -
- - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html deleted file mode 100644 index e819c3449..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html +++ /dev/null @@ -1,30 +0,0 @@ - - -
- -
-
-IP           Packets dropped
-             Packets received
-             Packets sent
-IP errors    IP version/header length
-             IP length, high byte
-             IP length, low byte
-             IP fragments
-             Header checksum
-             Wrong protocol
-ICMP	     Packets dropped
-             Packets received
-             Packets sent
-             Type errors
-TCP          Packets dropped
-             Packets received
-             Packets sent
-             Checksum errors
-             Data packets without ACKs
-             Resets
-             Retransmissions
-	     No connection avaliable
-	     Connection attempts to closed ports
-
-
\ No newline at end of file
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deleted file mode 100644
index 442c17a58..000000000
--- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain
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10}}; - -const struct fsdata_file file_control_html[] = {{file_404_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}}; - -const struct fsdata_file file_files_footer_plain[] = {{file_control_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}}; - -const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}}; - -const struct fsdata_file file_stats_footer_plain[] = {{file_files_header_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}}; - -const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}}; - -const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}}; - -const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}}; - -const struct fsdata_file file_img_logo_png[] = {{file_tcp_header_html, data_img_logo_png, data_img_logo_png + 14, sizeof(data_img_logo_png) - 14}}; - -const struct fsdata_file file_cgi_files[] = {{file_img_logo_png, data_cgi_files, data_cgi_files + 11, sizeof(data_cgi_files) - 11}}; - -const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}}; - -const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}}; - -const struct fsdata_file file_cgi_rtos[] = {{file_cgi_tcp, data_cgi_rtos, data_cgi_rtos + 10, sizeof(data_cgi_rtos) - 10}}; - -const struct fsdata_file file_index_html[] = {{file_cgi_rtos, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; - -#define FS_ROOT file_index_html - -#define FS_NUMFILES 14 diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h deleted file mode 100644 index 94086c4df..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $ - */ -#ifndef __FSDATA_H__ -#define __FSDATA_H__ - -#include "uipopt.h" - -struct fsdata_file { - const struct fsdata_file *next; - const char *name; - const char *data; - const int len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t count; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -}; - -struct fsdata_file_noconst { - struct fsdata_file *next; - char *name; - char *data; - int len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t count; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -}; - -#endif /* __FSDATA_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c deleted file mode 100644 index 108fa26e8..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c +++ /dev/null @@ -1,372 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \defgroup httpd Web server - * @{ - * - * The uIP web server is a very simplistic implementation of an HTTP - * server. It can serve web pages and files from a read-only ROM - * filesystem, and provides a very small scripting language. - * - * The script language is very simple and works as follows. Each - * script line starts with a command character, either "i", "t", "c", - * "#" or ".". The "i" command tells the script interpreter to - * "include" a file from the virtual file system and output it to the - * web browser. The "t" command should be followed by a line of text - * that is to be output to the browser. The "c" command is used to - * call one of the C functions from the httpd-cgi.c file. A line that - * starts with a "#" is ignored (i.e., the "#" denotes a comment), and - * the "." denotes the last script line. - * - * The script that produces the file statistics page looks somewhat - * like this: - * - \code -i /header.html -t

File statistics


RemoteStateRetransmissionsTimerFlags
-t
/index.html -c a /index.html -t
/cgi/files -c a /cgi/files -t
/cgi/tcp -c a /cgi/tcp -t
/404.html -c a /404.html -t
-i /footer.plain -. - \endcode - * - */ - - -/** - * \file - * HTTP server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $ - * - */ - - -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" -#include "cgi.h" - -#define NULL (void *)0 - -/* The HTTP server states: */ -#define HTTP_NOGET 0 -#define HTTP_FILE 1 -#define HTTP_TEXT 2 -#define HTTP_FUNC 3 -#define HTTP_END 4 - -#ifdef DEBUG -#include -#define PRINT(x) -#define PRINTLN(x) -#else /* DEBUG */ -#define PRINT(x) -#define PRINTLN(x) -#endif /* DEBUG */ - -struct httpd_state *hs; - -extern const struct fsdata_file file_index_html; -extern const struct fsdata_file file_404_html; - -static void next_scriptline(void); -static void next_scriptstate(void); - -#define ISO_G 0x47 -#define ISO_E 0x45 -#define ISO_T 0x54 -#define ISO_slash 0x2f -#define ISO_c 0x63 -#define ISO_g 0x67 -#define ISO_i 0x69 -#define ISO_space 0x20 -#define ISO_nl 0x0a -#define ISO_cr 0x0d -#define ISO_a 0x61 -#define ISO_t 0x74 -#define ISO_hash 0x23 -#define ISO_period 0x2e - -#define httpPORT 80 - -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the web server. - * - * Starts to listen for incoming connection requests on TCP port 80. - */ -/*-----------------------------------------------------------------------------------*/ -void -httpd_init(void) -{ - fs_init(); - - /* Listen to port 80. */ - uip_listen(HTONS(httpPORT)); -} -/*-----------------------------------------------------------------------------------*/ -void -httpd_appcall(void) -{ - struct fs_file fsfile; - - u8_t i; - - switch(uip_conn->lport) { - /* This is the web server: */ - case HTONS(httpPORT): - /* Pick out the application state from the uip_conn structure. */ - hs = (struct httpd_state *)(uip_conn->appstate); - - /* We use the uip_ test functions to deduce why we were - called. If uip_connected() is non-zero, we were called - because a remote host has connected to us. If - uip_newdata() is non-zero, we were called because the - remote host has sent us new data, and if uip_acked() is - non-zero, the remote host has acknowledged the data we - previously sent to it. */ - if(uip_connected()) { - /* Since we have just been connected with the remote host, we - reset the state for this connection. The ->count variable - contains the amount of data that is yet to be sent to the - remote host, and the ->state is set to HTTP_NOGET to signal - that we haven't received any HTTP GET request for this - connection yet. */ - - hs->state = HTTP_NOGET; - hs->count = 0; - return; - - } else if(uip_poll()) { - /* If we are polled ten times, we abort the connection. This is - because we don't want connections lingering indefinately in - the system. */ - if(hs->count++ >= 10) { - uip_abort(); - } - return; - } else if(uip_newdata() && hs->state == HTTP_NOGET) { - /* This is the first data we receive, and it should contain a - GET. */ - - /* Check for GET. */ - if(uip_appdata[0] != ISO_G || - uip_appdata[1] != ISO_E || - uip_appdata[2] != ISO_T || - uip_appdata[3] != ISO_space) { - /* If it isn't a GET, we abort the connection. */ - uip_abort(); - return; - } - - /* Find the file we are looking for. */ - for(i = 4; i < 40; ++i) { - if(uip_appdata[i] == ISO_space || - uip_appdata[i] == ISO_cr || - uip_appdata[i] == ISO_nl) { - uip_appdata[i] = 0; - break; - } - } - - PRINT("request for file "); - PRINTLN(&uip_appdata[4]); - - /* Check for a request for "/". */ - if(uip_appdata[4] == ISO_slash && - uip_appdata[5] == 0) { - fs_open(file_index_html.name, &fsfile); - } else { - if(!fs_open((const char *)&uip_appdata[4], &fsfile)) { - PRINTLN("couldn't open file"); - fs_open(file_404_html.name, &fsfile); - } - } - - - if(uip_appdata[4] == ISO_slash && - uip_appdata[5] == ISO_c && - uip_appdata[6] == ISO_g && - uip_appdata[7] == ISO_i && - uip_appdata[8] == ISO_slash) { - /* If the request is for a file that starts with "/cgi/", we - prepare for invoking a script. */ - hs->script = fsfile.data; - next_scriptstate(); - } else { - hs->script = NULL; - /* The web server is now no longer in the HTTP_NOGET state, but - in the HTTP_FILE state since is has now got the GET from - the client and will start transmitting the file. */ - hs->state = HTTP_FILE; - - /* Point the file pointers in the connection state to point to - the first byte of the file. */ - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - } - } - - - if(hs->state != HTTP_FUNC) { - /* Check if the client (remote end) has acknowledged any data that - we've previously sent. If so, we move the file pointer further - into the file and send back more data. If we are out of data to - send, we close the connection. */ - if(uip_acked()) { - if(hs->count >= uip_conn->len) { - hs->count -= uip_conn->len; - hs->dataptr += uip_conn->len; - } else { - hs->count = 0; - } - - if(hs->count == 0) { - if(hs->script != NULL) { - next_scriptline(); - next_scriptstate(); - } else { - uip_close(); - } - } - } - } else { - /* Call the CGI function. */ - if(cgitab[hs->script[2] - ISO_a](uip_acked())) { - /* If the function returns non-zero, we jump to the next line - in the script. */ - next_scriptline(); - next_scriptstate(); - } - } - - if(hs->state != HTTP_FUNC && !uip_poll()) { - /* Send a piece of data, but not more than the MSS of the - connection. */ - uip_send(( void * ) hs->dataptr, hs->count); - } - - /* Finally, return to uIP. Our outgoing packet will soon be on its - way... */ - return; - - default: - /* Should never happen. */ - uip_abort(); - break; - } -} -/*-----------------------------------------------------------------------------------*/ -/* next_scriptline(): - * - * Reads the script until it finds a newline. */ -static void -next_scriptline(void) -{ - /* Loop until we find a newline character. */ - do { - ++(hs->script); - } while(hs->script[0] != ISO_nl); - - /* Eat up the newline as well. */ - ++(hs->script); -} -/*-----------------------------------------------------------------------------------*/ -/* next_sciptstate: - * - * Reads one line of script and decides what to do next. - */ -static void -next_scriptstate(void) -{ - struct fs_file fsfile; - long i; - - again: - switch(hs->script[0]) { - case ISO_t: - /* Send a text string. */ - hs->state = HTTP_TEXT; - hs->dataptr = &hs->script[2]; - - /* Calculate length of string. */ - for(i = 0; hs->dataptr[i] != ISO_nl; ++i); - hs->count = i; - break; - case ISO_c: - /* Call a function. */ - hs->state = HTTP_FUNC; - hs->dataptr = NULL; - hs->count = 0; - cgitab[hs->script[2] - ISO_a](0); - break; - case ISO_i: - /* Include a file. */ - hs->state = HTTP_FILE; - if(!fs_open(&hs->script[2], &fsfile)) { - uip_abort(); - } - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - break; - case ISO_hash: - /* Comment line. */ - next_scriptline(); - goto again; - case ISO_period: - /* End of script. */ - hs->state = HTTP_END; - uip_close(); - break; - default: - uip_abort(); - break; - } -} -/*-----------------------------------------------------------------------------------*/ -/** @} */ -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ deleted file mode 100644 index fda240826..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ +++ /dev/null @@ -1,380 +0,0 @@ -/*$T httpd.c GC 1.138 07/23/05 13:10:49 */ - -/* - * \addtogroup exampleapps @{ £ - * \defgroup httpd Web server @{ The uIP web server is a very simplistic - * implementation of an HTTP server. It can serve web pages and files from a - * read-only ROM filesystem, and provides a very small scripting language. The - * script language is very simple and works as follows. Each script line starts - * with a command character, either "i", "t", "c", "#" or ".". The "i" command - * tells the script interpreter to "include" a file from the virtual file system - * and output it to the web browser. The "t" command should be followed by a line - * of text that is to be output to the browser. The "c" command is used to call - * one of the C functions from the httpd-cgi.c file. A line that starts with a "#" - * is ignored (i.e., the "#" denotes a comment), and the "." denotes the last - * script line. The script that produces the file statistics page looks somewhat - * like this: \code i /header.html t

File statistics


t
/index.html c a - * /index.html t
/cgi/files c - * a /cgi/files t
/cgi/tcp c a - * /cgi/tcp t
/404.html c a - * /404.html t
i /footer.plain . \endcode £ - * \file HTTP server. \author Adam Dunkels £ - * Copyright (c) 2001, Adam Dunkels. All rights reserved. Redistribution and use - * in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: 1. Redistributions of source - * code must retain the above copyright notice, this list of conditions and the - * following disclaimer. 2. Redistributions in binary form must reproduce the - * above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. 3. The - * name of the author may not be used to endorse or promote products derived from - * this software without specific prior written permission. THIS SOFTWARE IS - * PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * This file is part of the uIP TCP/IP stack. $Id: httpd.c,v 1.28.2.6 2003/10/07 - * 13:22:27 adam Exp $ - */ -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" -#include "cgi.h" - -#define NULL ( void * ) 0 - -/* The HTTP server states: */ -#define HTTP_NOGET 0 -#define HTTP_FILE 1 -#define HTTP_TEXT 2 -#define HTTP_FUNC 3 -#define HTTP_END 4 - -#ifdef DEBUG -#include -#define PRINT( x ) -#define PRINTLN( x ) -#else /* DEBUG */ -#define PRINT( x ) -#define PRINTLN( x ) -#endif /* DEBUG */ - -struct httpd_state *hs; - -extern const struct fsdata_file file_index_html; -extern const struct fsdata_file file_404_html; - -static void next_scriptline( void ); -static void next_scriptstate( void ); - -#define ISO_G 0x47 -#define ISO_E 0x45 -#define ISO_T 0x54 -#define ISO_slash 0x2f -#define ISO_c 0x63 -#define ISO_g 0x67 -#define ISO_i 0x69 -#define ISO_space 0x20 -#define ISO_nl 0x0a -#define ISO_cr 0x0d -#define ISO_a 0x61 -#define ISO_t 0x74 -#define ISO_hash 0x23 -#define ISO_period 0x2e - -#define httpPORT 80 - -/* - ======================================================================================================================= - Initialize the web server. Starts to listen for incoming connection requests on TCP port 80. - ======================================================================================================================= - */ -void httpd_init( void ) -{ - fs_init(); - - /* Listen to port 80. */ - uip_listen( HTONS( httpPORT ) ); -} - -/* - ======================================================================================================================= - ======================================================================================================================= - */ -void httpd_appcall( void ) -{ - /*~~~~~~~~~~~~~~~~~~~*/ - struct fs_file fsfile; - u8_t i; - /*~~~~~~~~~~~~~~~~~~~*/ - - switch( uip_conn->lport ) - { - /* This is the web server: */ - case HTONS( httpPORT ): - /* Pick out the application state from the uip_conn structure. */ - hs = ( struct httpd_state * ) ( uip_conn->appstate ); - - /* - * We use the uip_ test functions to deduce why we were called. If uip_connected() - * is non-zero, we were called because a remote host has connected to us. If - * uip_newdata() is non-zero, we were called because the remote host has sent us - * new data, and if uip_acked() is non-zero, the remote host has acknowledged the - * data we previously sent to it. - */ - if( uip_connected() ) - { - /* - * Since we have just been connected with the remote host, we reset the state for - * this connection. The ->count variable contains the amount of data that is yet - * to be sent to the remote host, and the ->state is set to HTTP_NOGET to signal - * that we haven't received any HTTP GET request for this connection yet. - */ - hs->state = HTTP_NOGET; - hs->count = 0; - return; - } - else if( uip_poll() ) - { - /* - * If we are polled ten times, we abort the connection. This is because we don't - * want connections lingering indefinately in the system. - */ - if( hs->count++ >= 10 ) - { - uip_abort(); - } - - return; - } - else if( uip_newdata() && hs->state == HTTP_NOGET ) - { - /* - * This is the first data we receive, and it should contain a GET. £ - * Check for GET. - */ - if - ( - uip_appdata[0] != ISO_G - || uip_appdata[1] != ISO_E - || uip_appdata[2] != ISO_T - || uip_appdata[3] != ISO_space - ) - { - /* If it isn't a GET, we abort the connection. */ - uip_abort(); - return; - } - - /* Find the file we are looking for. */ - for( i = 4; i < 40; ++i ) - { - if( uip_appdata[i] == ISO_space || uip_appdata[i] == ISO_cr || uip_appdata[i] == ISO_nl ) - { - uip_appdata[i] = 0; - break; - } - } - - PRINT( "request for file " ); - PRINTLN( &uip_appdata[4] ); - - /* Check for a request for "/". */ - if( uip_appdata[4] == ISO_slash && uip_appdata[5] == 0 ) - { - fs_open( file_index_html.name, &fsfile ); - } - else - { - if( !fs_open( ( const char * ) &uip_appdata[4], &fsfile ) ) - { - PRINTLN( "couldn't open file" ); - fs_open( file_404_html.name, &fsfile ); - } - } - - if - ( - uip_appdata[4] == ISO_slash - && uip_appdata[5] == ISO_c - && uip_appdata[6] == ISO_g - && uip_appdata[7] == ISO_i - && uip_appdata[8] == ISO_slash - ) - { - /* - * If the request is for a file that starts with "/cgi/", we prepare for invoking - * a script. - */ - hs->script = fsfile.data; - next_scriptstate(); - } - else - { - hs->script = NULL; - - /* - * The web server is now no longer in the HTTP_NOGET state, but in the HTTP_FILE - * state since is has now got the GET from the client and will start transmitting - * the file. - */ - hs->state = HTTP_FILE; - - /* - * Point the file pointers in the connection state to point to the first byte of - * the file. - */ - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - } - } - - if( hs->state != HTTP_FUNC ) - { - /* - * Check if the client (remote end) has acknowledged any data that we've - * previously sent. If so, we move the file pointer further into the file and send - * back more data. If we are out of data to send, we close the connection. - */ - if( uip_acked() ) - { - if( hs->count >= uip_conn->len ) - { - hs->count -= uip_conn->len; - hs->dataptr += uip_conn->len; - } - else - { - hs->count = 0; - } - - if( hs->count == 0 ) - { - if( hs->script != NULL ) - { - next_scriptline(); - next_scriptstate(); - } - else - { - uip_close(); - } - } - } - } - else - { - /* Call the CGI function. */ - if( cgitab[hs->script[2] - ISO_a](uip_acked()) ) - { - /* If the function returns non-zero, we jump to the next line in the script. */ - next_scriptline(); - next_scriptstate(); - } - } - - if( hs->state != HTTP_FUNC && !uip_poll() ) - { - /* Send a piece of data, but not more than the MSS of the connection. */ - uip_send( ( void * ) hs->dataptr, hs->count ); - } - - /* Finally, return to uIP. Our outgoing packet will soon be on its way... */ - return; - - default: - /* Should never happen. */ - uip_abort(); - break; - } -} - -/* - ======================================================================================================================= - next_scriptline(): Reads the script until it finds a newline. - ======================================================================================================================= - */ -static void next_scriptline( void ) -{ - /* Loop until we find a newline character. */ - do - { - ++( hs->script ); - } while( hs->script[0] != ISO_nl ); - - /* Eat up the newline as well. */ - ++( hs->script ); -} - -/* - ======================================================================================================================= - next_sciptstate: Reads one line of script and decides what to do next. - ======================================================================================================================= - */ -static void next_scriptstate( void ) -{ - /*~~~~~~~~~~~~~~~~~~~*/ - struct fs_file fsfile; - u8_t i; - /*~~~~~~~~~~~~~~~~~~~*/ - -again: - switch( hs->script[0] ) - { - case ISO_t: - /* Send a text string. */ - hs->state = HTTP_TEXT; - hs->dataptr = &hs->script[2]; - - /* Calculate length of string. */ - for( i = 0; hs->dataptr[i] != ISO_nl; ++i ); - hs->count = i; - break; - - case ISO_c: - /* Call a function. */ - hs->state = HTTP_FUNC; - hs->dataptr = NULL; - hs->count = 0; - cgitab[hs->script[2] - ISO_a]( 0 ); - break; - - case ISO_i: - /* Include a file. */ - hs->state = HTTP_FILE; - if( !fs_open( &hs->script[2], &fsfile ) ) - { - uip_abort(); - } - - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - break; - - case ISO_hash: - /* Comment line. */ - next_scriptline(); - goto again; - - case ISO_period: - /* End of script. */ - hs->state = HTTP_END; - uip_close(); - break; - - default: - uip_abort(); - break; - } -} - -/* - * @} £ - * @} - */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h deleted file mode 100644 index 34d6bb35f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $ - * - */ - -#ifndef __HTTPD_H__ -#define __HTTPD_H__ - -void httpd_init(void); -void httpd_appcall(void); - -/* UIP_APPCALL: the name of the application function. This function - must return void and take no arguments (i.e., C type "void - appfunc(void)"). */ -#ifndef UIP_APPCALL -#define UIP_APPCALL httpd_appcall -#endif - -struct httpd_state { - u8_t state; - u16_t count; - char *dataptr; - char *script; -}; - - -/* UIP_APPSTATE_SIZE: The size of the application-specific state - stored in the uip_conn structure. */ -#ifndef UIP_APPSTATE_SIZE -#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) -#endif - -#define FS_STATISTICS 1 - -extern struct httpd_state *hs; - -#endif /* __HTTPD_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/main_led b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/main_led deleted file mode 100644 index 8fe01ea6d..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/main_led +++ /dev/null @@ -1,67 +0,0 @@ -// Copyright (c) 2001-2004 Rowley Associates Limited. -// -// This file may be distributed under the terms of the License Agreement -// provided with this software. -// -// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE -// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. -// -//////////////////////////////////////////////////////////////////////////////// -// -// Olimex LPC-P1 LED Example -// -// Description -// ----------- -// This example demonstrates writing to the programmable peripheral interface. -// -//////////////////////////////////////////////////////////////////////////////// - -#include - -#define LED_RED (1<<8) -#define LED_GREEN (1<<10) -#define LED_YELLOW (1<<11) - -#define LED1 LED_YELLOW - -static void -ledInit() -{ - IODIR |= LED1; - IOSET = LED1; -} - -static void -ledOn(void) -{ - IOCLR = LED1; -} - -static void -ledOff(void) -{ - IOSET = LED1; -} - -void -delay(int d) -{ - for(; d; --d); -} - -int -main(void) -{ - MAMCR = 2; - ledInit(); - while (1) - { - ledOn(); - delay(100000); - ledOff(); - delay(100000); - } - return 0; -} - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata deleted file mode 100644 index f5f75f174..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata +++ /dev/null @@ -1,93 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> fsdata.c"); - -chdir("fs"); -open(FILES, "find . -type f |"); - -while($file = ) { - - # Do not include files in CVS directories nor backup files. - if($file =~ /(CVS|~)/) { - next; - } - - chop($file); - - open(HEADER, "> /tmp/header") || die $!; - if($file =~ /404.html/) { - print(HEADER "HTTP/1.0 404 File not found\r\n"); - } else { - print(HEADER "HTTP/1.0 200 OK\r\n"); - } - print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n"); - if($file =~ /\.html$/) { - print(HEADER "Content-type: text/html\r\n"); - } elsif($file =~ /\.gif$/) { - print(HEADER "Content-type: image/gif\r\n"); - } elsif($file =~ /\.png$/) { - print(HEADER "Content-type: image/png\r\n"); - } elsif($file =~ /\.jpg$/) { - print(HEADER "Content-type: image/jpeg\r\n"); - } else { - print(HEADER "Content-type: text/plain\r\n"); - } - print(HEADER "\r\n"); - close(HEADER); - - unless($file =~ /\.plain$/ || $file =~ /cgi/) { - system("cat /tmp/header $file > /tmp/file"); - } else { - system("cp $file /tmp/file"); - } - - open(FILE, "/tmp/file"); - unlink("/tmp/file"); - unlink("/tmp/header"); - - $file =~ s/\.//; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - print(OUTPUT "static const char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@files, $file); -} - -for($i = 0; $i < @fvars; $i++) { - $file = $files[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define FS_NUMFILES $i"); diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/memb.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/memb.c deleted file mode 100644 index 56e663446..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/memb.c +++ /dev/null @@ -1,152 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \file - * Memory block allocation routines. - * \author Adam Dunkels - * - * The memory block allocation routines provide a simple yet powerful - * set of functions for managing a set of memory blocks of fixed - * size. A set of memory blocks is statically declared with the - * MEMB() macro. Memory blocks are allocated from the declared - * memory by the memb_alloc() function, and are deallocated with the - * memb_free() function. - * - * \note Because of namespace clashes only one MEMB() can be - * declared per C module, and the name scope of a MEMB() memory - * block is local to each C module. - * - * The following example shows how to declare and use a memory block - * called "cmem" which has 8 chunks of memory with each memory chunk - * being 20 bytes large. - * - \code - MEMB(cmem, 20, 8); - - int main(int argc, char *argv[]) { - char *ptr; - - memb_init(&cmem); - - ptr = memb_alloc(&cmem); - - if(ptr != NULL) { - do_something(ptr); - } else { - printf("Could not allocate memory.\n"); - } - - if(memb_free(ptr) == 0) { - printf("Deallocation succeeded.\n"); - } - } - \endcode - * - */ - -#include - -#include "memb.h" - -/*------------------------------------------------------------------------------*/ -/** - * Initialize a memory block that was declared with MEMB(). - * - * \param m A memory block previosly declared with MEMB(). - */ -/*------------------------------------------------------------------------------*/ -void -memb_init(struct memb_blocks *m) -{ - memset(m->mem, (m->size + 1) * m->num, 0); -} -/*------------------------------------------------------------------------------*/ -/** - * Allocate a memory block from a block of memory declared with MEMB(). - * - * \param m A memory block previosly declared with MEMB(). - */ -/*------------------------------------------------------------------------------*/ -char * -memb_alloc(struct memb_blocks *m) -{ - int i; - char *ptr; - - ptr = m->mem; - for(i = 0; i < m->num; ++i) { - if(*ptr == 0) { - /* If this block was unused, we increase the reference count to - indicate that it now is used and return a pointer to the - first byte following the reference counter. */ - ++*ptr; - return ptr + 1; - } - ptr += m->size + 1; - } - - /* No free block was found, so we return NULL to indicate failure to - allocate block. */ - return NULL; -} -/*------------------------------------------------------------------------------*/ -/** - * Deallocate a memory block from a memory block previously declared - * with MEMB(). - * - * \param m m A memory block previosly declared with MEMB(). - * - * \param ptr A pointer to the memory block that is to be deallocated. - * - * \return The new reference count for the memory block (should be 0 - * if successfully deallocated) or -1 if the pointer "ptr" did not - * point to a legal memory block. - */ -/*------------------------------------------------------------------------------*/ -char -memb_free(struct memb_blocks *m, char *ptr) -{ - int i; - char *ptr2; - - /* Walk through the list of blocks and try to find the block to - which the pointer "ptr" points to. */ - ptr2 = m->mem; - for(i = 0; i < m->num; ++i) { - - if(ptr2 == ptr - 1) { - /* We've found to block to which "ptr" points so we decrease the - reference count and return the new value of it. */ - return --*ptr2; - } - ptr2 += m->size + 1; - } - return -1; -} -/*------------------------------------------------------------------------------*/ -/** - * Increase the reference count for a memory chunk. - * - * \note No sanity checks are currently made. - * - * \param m m A memory block previosly declared with MEMB(). - * - * \param ptr A pointer to the memory chunk for which the reference - * count should be increased. - * - * \return The new reference count. - */ -/*------------------------------------------------------------------------------*/ -char -memb_ref(struct memb_blocks *m, char *ptr) -{ - return ++*(ptr - 1); -} -/*------------------------------------------------------------------------------*/ - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/memb.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/memb.h deleted file mode 100644 index 505846f4d..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/memb.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \file - * Memory block allocation routines. - * \author Adam Dunkels - * - */ - -#ifndef __MEMB_H__ -#define __MEMB_H__ - -/** - * Declare a memory block. - * - * \param name The name of the memory block (later used with - * memb_init(), memb_alloc() and memb_free()). - * - * \param size The size of each memory chunk, in bytes. - * - * \param num The total number of memory chunks in the block. - * - */ -#define MEMB(name, size, num) \ - static char memb_mem[(size + 1) * num]; \ - static struct memb_blocks name = {size, num, memb_mem} - -struct memb_blocks { - unsigned short size; - unsigned short num; - char *mem; -}; - -void memb_init(struct memb_blocks *m); -char *memb_alloc(struct memb_blocks *m); -char memb_ref(struct memb_blocks *m, char *ptr); -char memb_free(struct memb_blocks *m, char *ptr); - - -#endif /* __MEMB_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat deleted file mode 100644 index 7f5babb3f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat +++ /dev/null @@ -1 +0,0 @@ -arp -s 172.25.218.210 00-bd-3b-33-05-72 diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c deleted file mode 100644 index fc968c82e..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c +++ /dev/null @@ -1,202 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup slip Serial Line IP (SLIP) protocol - * @{ - * - * The SLIP protocol is a very simple way to transmit IP packets over - * a serial line. It does not provide any framing or error control, - * and is therefore not very widely used today. - * - * This SLIP implementation requires two functions for accessing the - * serial device: slipdev_char_poll() and slipdev_char_put(). These - * must be implemented specifically for the system on which the SLIP - * protocol is to be run. - */ - -/** - * \file - * SLIP protocol implementation - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $ - * - */ - -/* - * This is a generic implementation of the SLIP protocol over an RS232 - * (serial) device. - * - * Huge thanks to Ullrich von Bassewitz of cc65 fame for - * and endless supply of bugfixes, insightsful comments and - * suggestions, and improvements to this code! - */ - -#include "uip.h" - -#define SLIP_END 0300 -#define SLIP_ESC 0333 -#define SLIP_ESC_END 0334 -#define SLIP_ESC_ESC 0335 - -static u8_t slip_buf[UIP_BUFSIZE]; - -static u16_t len, tmplen; -static u8_t lastc; - -/*-----------------------------------------------------------------------------------*/ -/** - * Send the packet in the uip_buf and uip_appdata buffers using the - * SLIP protocol. - * - * The first 40 bytes of the packet (the IP and TCP headers) are read - * from the uip_buf buffer, and the following bytes (the application - * data) are read from the uip_appdata buffer. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -slipdev_send(void) -{ - u16_t i; - u8_t *ptr; - u8_t c; - - slipdev_char_put(SLIP_END); - - ptr = uip_buf; - for(i = 0; i < uip_len; ++i) { - if(i == 40) { - ptr = (u8_t *)uip_appdata; - } - c = *ptr++; - switch(c) { - case SLIP_END: - slipdev_char_put(SLIP_ESC); - slipdev_char_put(SLIP_ESC_END); - break; - case SLIP_ESC: - slipdev_char_put(SLIP_ESC); - slipdev_char_put(SLIP_ESC_ESC); - break; - default: - slipdev_char_put(c); - break; - } - } - slipdev_char_put(SLIP_END); -} -/*-----------------------------------------------------------------------------------*/ -/** - * Poll the SLIP device for an available packet. - * - * This function will poll the SLIP device to see if a packet is - * available. It uses a buffer in which all avaliable bytes from the - * RS232 interface are read into. When a full packet has been read - * into the buffer, the packet is copied into the uip_buf buffer and - * the length of the packet is returned. - * - * \return The length of the packet placed in the uip_buf buffer, or - * zero if no packet is available. - */ -/*-----------------------------------------------------------------------------------*/ -u16_t -slipdev_poll(void) -{ - u8_t c; - - while(slipdev_char_poll(c)) { - switch(c) { - case SLIP_ESC: - lastc = c; - break; - - case SLIP_END: - lastc = c; - /* End marker found, we copy our input buffer to the uip_buf - buffer and return the size of the packet we copied. */ - memcpy(uip_buf, slip_buf, len); - tmplen = len; - len = 0; - return tmplen; - - default: - if(lastc == SLIP_ESC) { - lastc = c; - /* Previous read byte was an escape byte, so this byte will be - interpreted differently from others. */ - switch(c) { - case SLIP_ESC_END: - c = SLIP_END; - break; - case SLIP_ESC_ESC: - c = SLIP_ESC; - break; - } - } else { - lastc = c; - } - - slip_buf[len] = c; - ++len; - - if(len > UIP_BUFSIZE) { - len = 0; - } - - break; - } - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the SLIP module. - * - * This function does not initialize the underlying RS232 device, but - * only the SLIP part. - */ -/*-----------------------------------------------------------------------------------*/ -void -slipdev_init(void) -{ - lastc = len = 0; -} -/*-----------------------------------------------------------------------------------*/ - -/** @} */ -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h deleted file mode 100644 index 3fbfe2d2d..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \addtogroup slip - * @{ - */ - -/** - * \file - * SLIP header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $ - * - */ - -#ifndef __SLIPDEV_H__ -#define __SLIPDEV_H__ - -#include "uip.h" - -/** - * Put a character on the serial device. - * - * This function is used by the SLIP implementation to put a character - * on the serial device. It must be implemented specifically for the - * system on which the SLIP implementation is to be run. - * - * \param c The character to be put on the serial device. - */ -void slipdev_char_put(u8_t c); - -/** - * Poll the serial device for a character. - * - * This function is used by the SLIP implementation to poll the serial - * device for a character. It must be implemented specifically for the - * system on which the SLIP implementation is to be run. - * - * The function should return immediately regardless if a character is - * available or not. If a character is available it should be placed - * at the memory location pointed to by the pointer supplied by the - * arguement c. - * - * \param c A pointer to a byte that is filled in by the function with - * the received character, if available. - * - * \retval 0 If no character is available. - * \retval Non-zero If a character is available. - */ -u8_t slipdev_char_poll(u8_t *c); - -void slipdev_init(void); -void slipdev_send(void); -u16_t slipdev_poll(void); - -#endif /* __SLIPDEV_H__ */ - -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c deleted file mode 100644 index 0d23fc4d9..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * Author: Adam Dunkels - * - * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $ - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef linux -#include -#include -#include -#define DEVTAP "/dev/net/tun" -#else /* linux */ -#define DEVTAP "/dev/tap0" -#endif /* linux */ - -#include "uip.h" - -static int fd; - -static unsigned long lasttime; -static struct timezone tz; - -/*-----------------------------------------------------------------------------------*/ -void -tapdev_init(void) -{ - char buf[1024]; - - fd = open(DEVTAP, O_RDWR); - if(fd == -1) { - perror("tapdev: tapdev_init: open"); - exit(1); - } - -#ifdef linux - { - struct ifreq ifr; - memset(&ifr, 0, sizeof(ifr)); - ifr.ifr_flags = IFF_TAP|IFF_NO_PI; - if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) { - perror(buf); - exit(1); - } - } -#endif /* Linux */ - - snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d", - UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3); - system(buf); - - lasttime = 0; -} -/*-----------------------------------------------------------------------------------*/ -unsigned int -tapdev_read(void) -{ - fd_set fdset; - struct timeval tv, now; - int ret; - - if(lasttime >= 500000) { - lasttime = 0; - return 0; - } - - tv.tv_sec = 0; - tv.tv_usec = 500000 - lasttime; - - - FD_ZERO(&fdset); - FD_SET(fd, &fdset); - - gettimeofday(&now, &tz); - ret = select(fd + 1, &fdset, NULL, NULL, &tv); - if(ret == 0) { - lasttime = 0; - return 0; - } - ret = read(fd, uip_buf, UIP_BUFSIZE); - if(ret == -1) { - perror("tap_dev: tapdev_read: read"); - } - gettimeofday(&tv, &tz); - lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec); - - return ret; -} -/*-----------------------------------------------------------------------------------*/ -void -tapdev_send(void) -{ - int ret; - struct iovec iov[2]; - -#ifdef linux - { - char tmpbuf[UIP_BUFSIZE]; - int i; - - for(i = 0; i < 40 + UIP_LLH_LEN; i++) { - tmpbuf[i] = uip_buf[i]; - } - - for(; i < uip_len; i++) { - tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; - } - - ret = write(fd, tmpbuf, uip_len); - } -#else - - if(uip_len < 40 + UIP_LLH_LEN) { - ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN); - } else { - iov[0].iov_base = uip_buf; - iov[0].iov_len = 40 + UIP_LLH_LEN; - iov[1].iov_base = (char *)uip_appdata; - iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); - - ret = writev(fd, iov, 2); - } -#endif - if(ret == -1) { - perror("tap_dev: tapdev_send: writev"); - exit(1); - } -} -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h deleted file mode 100644 index 66f1a4a71..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $ - * - */ - -#ifndef __TAPDEV_H__ -#define __TAPDEV_H__ - -void tapdev_init(void); -unsigned int tapdev_read(void); -void tapdev_send(void); - -#endif /* __TAPDEV_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c deleted file mode 100644 index 7dff714ca..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c +++ /dev/null @@ -1,181 +0,0 @@ -/** - * \addtogroup telnetd - * @{ - */ - -/** - * \file - * An example telnet server shell - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the Contiki desktop OS. - * - * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $ - * - */ - -#include "uip.h" -#include "telnetd.h" -#include - -struct ptentry { - char c; - void (* pfunc)(struct telnetd_state *s, char *str); -}; - -/*-----------------------------------------------------------------------------------*/ -static void -parse(struct telnetd_state *s, register char *str, struct ptentry *t) -{ - register struct ptentry *p; - char *sstr; - - sstr = str; - - /* Loop over the parse table entries in t in order to find one that - matches the first character in str. */ - for(p = t; p->c != 0; ++p) { - if(*str == p->c) { - /* Skip rest of the characters up to the first space. */ - while(*str != ' ') { - ++str; - } - - /* Skip all spaces.*/ - while(*str == ' ') { - ++str; - } - - /* Call parse table entry function and return. */ - p->pfunc(s, str); - return; - } - } - - /* Did not find matching entry in parse table. We just call the - default handler supplied by the caller and return. */ - p->pfunc(s, str); -} -/*-----------------------------------------------------------------------------------*/ -static void -exitt(struct telnetd_state *s, char *str) -{ - telnetd_close(s); -} -/*-----------------------------------------------------------------------------------*/ -static void -inttostr(register char *str, unsigned int i) -{ - str[0] = '0' + i / 100; - if(str[0] == '0') { - str[0] = ' '; - } - str[1] = '0' + (i / 10) % 10; - if(str[1] == '0') { - str[1] = ' '; - } - str[2] = '0' + i % 10; - str[3] = ' '; - str[4] = 0; -} -/*-----------------------------------------------------------------------------------*/ -static void -stats(struct telnetd_state *s, char *strr) -{ - char str[10]; - - inttostr(str, uip_stat.ip.recv); - telnetd_output(s, "IP packets received ", str); - inttostr(str, uip_stat.ip.sent); - telnetd_output(s, "IP packets sent ", str); - inttostr(str, uip_stat.ip.drop); - telnetd_output(s, "IP packets dropped ", str); - - inttostr(str, uip_stat.icmp.recv); - telnetd_output(s, "ICMP packets received ", str); - inttostr(str, uip_stat.icmp.sent); - telnetd_output(s, "ICMP packets sent ", str); - inttostr(str, uip_stat.icmp.drop); - telnetd_output(s, "ICMP packets dropped ", str); - - inttostr(str, uip_stat.tcp.recv); - telnetd_output(s, "TCP packets received ", str); - inttostr(str, uip_stat.tcp.sent); - telnetd_output(s, "TCP packets sent ", str); - inttostr(str, uip_stat.tcp.drop); - telnetd_output(s, "TCP packets dropped ", str); - inttostr(str, uip_stat.tcp.rexmit); - telnetd_output(s, "TCP packets retransmitted ", str); - inttostr(str, uip_stat.tcp.synrst); - telnetd_output(s, "TCP connection attempts ", str); -} -/*-----------------------------------------------------------------------------------*/ -static void -help(struct telnetd_state *s, char *str) -{ - telnetd_output(s, "Available commands:", ""); - telnetd_output(s, "stats - show uIP statistics", ""); - telnetd_output(s, "exit - exit shell", ""); - telnetd_output(s, "? - show this help", ""); -} -/*-----------------------------------------------------------------------------------*/ -static void -none(struct telnetd_state *s, char *str) -{ - if(strlen(str) > 0) { - telnetd_output(s, "Unknown command", ""); - } -} -/*-----------------------------------------------------------------------------------*/ -static struct ptentry configparsetab[] = - {{'s', stats}, - {'e', exitt}, - {'?', help}, - - /* Default action */ - {0, none}}; -/*-----------------------------------------------------------------------------------*/ -void -telnetd_connected(struct telnetd_state *s) -{ - telnetd_output(s, "uIP command shell", ""); - telnetd_output(s, "Type '?' for help", ""); - telnetd_prompt(s, "uIP-0.9> "); -} -/*-----------------------------------------------------------------------------------*/ -void -telnetd_input(struct telnetd_state *s, char *cmd) -{ - parse(s, cmd, configparsetab); - telnetd_prompt(s, "uIP-0.9> "); -} -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c deleted file mode 100644 index dba522271..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c +++ /dev/null @@ -1,392 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \defgroup telnetd Telnet server - * @{ - * - * The uIP telnet server provides a command based interface to uIP. It - * allows using the "telnet" application to access uIP, and implements - * the required telnet option negotiation. - * - * The code is structured in a way which makes it possible to add - * commands without having to rewrite the main telnet code. The main - * telnet code calls two callback functions, telnetd_connected() and - * telnetd_input(), when a telnet connection has been established and - * when a line of text arrives on a telnet connection. These two - * functions can be implemented in a way which suits the particular - * application or environment in which the uIP system is intended to - * be run. - * - * The uIP distribution contains an example telnet shell - * implementation that provides a basic set of commands. - */ - -/** - * \file - * Implementation of the Telnet server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $ - * - */ - -#include "uip.h" -#include "memb.h" -#include "telnetd.h" -#include - -#define ISO_nl 0x0a -#define ISO_cr 0x0d - -MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES); - -static u8_t i; - -#define STATE_NORMAL 0 -#define STATE_IAC 1 -#define STATE_WILL 2 -#define STATE_WONT 3 -#define STATE_DO 4 -#define STATE_DONT 5 -#define STATE_CLOSE 6 - -#define TELNET_IAC 255 -#define TELNET_WILL 251 -#define TELNET_WONT 252 -#define TELNET_DO 253 -#define TELNET_DONT 254 -/*-----------------------------------------------------------------------------------*/ -static char * -alloc_line(void) -{ - return memb_alloc(&linemem); -} -/*-----------------------------------------------------------------------------------*/ -static void -dealloc_line(char *line) -{ - memb_free(&linemem, line); -} -/*-----------------------------------------------------------------------------------*/ -static void -sendline(struct telnetd_state *s, char *line) -{ - static unsigned int i; - for(i = 0; i < TELNETD_NUMLINES; ++i) { - if(s->lines[i] == NULL) { - s->lines[i] = line; - break; - } - } - if(i == TELNETD_NUMLINES) { - dealloc_line(line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Close a telnet session. - * - * This function can be called from a telnet command in order to close - * the connection. - * - * \param s The connection which is to be closed. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_close(struct telnetd_state *s) -{ - s->state = STATE_CLOSE; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Print a prompt on a telnet connection. - * - * This function can be called by the telnet command shell in order to - * print out a command prompt. - * - * \param s A telnet connection. - * - * \param str The command prompt. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_prompt(struct telnetd_state *s, char *str) -{ - char *line; - line = alloc_line(); - if(line != NULL) { - strncpy(line, str, TELNETD_LINELEN); - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Print out a string on a telnet connection. - * - * This function can be called from a telnet command parser in order - * to print out a string of text on the connection. The two strings - * given as arguments to the function will be concatenated, a carrige - * return and a new line character will be added, and the line is - * sent. - * - * \param s The telnet connection. - * - * \param str1 The first string. - * - * \param str2 The second string. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_output(struct telnetd_state *s, char *str1, char *str2) -{ - static unsigned len; - char *line; - - line = alloc_line(); - if(line != NULL) { - len = strlen(str1); - strncpy(line, str1, TELNETD_LINELEN); - if(len < TELNETD_LINELEN) { - strncpy(line + len, str2, TELNETD_LINELEN - len); - } - len = strlen(line); - if(len < TELNETD_LINELEN - 2) { - line[len] = ISO_cr; - line[len+1] = ISO_nl; - line[len+2] = 0; - } - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the telnet server. - * - * This function will perform the necessary initializations and start - * listening on TCP port 23. - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_init(void) -{ - memb_init(&linemem); - uip_listen(HTONS(23)); -} -/*-----------------------------------------------------------------------------------*/ -static void -acked(struct telnetd_state *s) -{ - dealloc_line(s->lines[0]); - for(i = 1; i < TELNETD_NUMLINES; ++i) { - s->lines[i - 1] = s->lines[i]; - } -} -/*-----------------------------------------------------------------------------------*/ -static void -senddata(struct telnetd_state *s) -{ - if(s->lines[0] != NULL) { - uip_send(s->lines[0], strlen(s->lines[0])); - } -} -/*-----------------------------------------------------------------------------------*/ -static void -getchar(struct telnetd_state *s, u8_t c) -{ - if(c == ISO_cr) { - return; - } - - s->buf[(int)s->bufptr] = c; - if(s->buf[(int)s->bufptr] == ISO_nl || - s->bufptr == sizeof(s->buf) - 1) { - if(s->bufptr > 0) { - s->buf[(int)s->bufptr] = 0; - } - telnetd_input(s, s->buf); - s->bufptr = 0; - } else { - ++s->bufptr; - } -} -/*-----------------------------------------------------------------------------------*/ -static void -sendopt(struct telnetd_state *s, u8_t option, u8_t value) -{ - char *line; - line = alloc_line(); - if(line != NULL) { - line[0] = TELNET_IAC; - line[1] = option; - line[2] = value; - line[3] = 0; - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -static void -newdata(struct telnetd_state *s) -{ - u16_t len; - u8_t c; - - - len = uip_datalen(); - - while(len > 0 && s->bufptr < sizeof(s->buf)) { - c = *uip_appdata; - ++uip_appdata; - --len; - switch(s->state) { - case STATE_IAC: - if(c == TELNET_IAC) { - getchar(s, c); - s->state = STATE_NORMAL; - } else { - switch(c) { - case TELNET_WILL: - s->state = STATE_WILL; - break; - case TELNET_WONT: - s->state = STATE_WONT; - break; - case TELNET_DO: - s->state = STATE_DO; - break; - case TELNET_DONT: - s->state = STATE_DONT; - break; - default: - s->state = STATE_NORMAL; - break; - } - } - break; - case STATE_WILL: - /* Reply with a DONT */ - sendopt(s, TELNET_DONT, c); - s->state = STATE_NORMAL; - break; - - case STATE_WONT: - /* Reply with a DONT */ - sendopt(s, TELNET_DONT, c); - s->state = STATE_NORMAL; - break; - case STATE_DO: - /* Reply with a WONT */ - sendopt(s, TELNET_WONT, c); - s->state = STATE_NORMAL; - break; - case STATE_DONT: - /* Reply with a WONT */ - sendopt(s, TELNET_WONT, c); - s->state = STATE_NORMAL; - break; - case STATE_NORMAL: - if(c == TELNET_IAC) { - s->state = STATE_IAC; - } else { - getchar(s, c); - } - break; - } - - - } - -} -/*-----------------------------------------------------------------------------------*/ -void -telnetd_app(void) -{ - struct telnetd_state *s; - - s = (struct telnetd_state *)uip_conn->appstate; - - if(uip_connected()) { - - for(i = 0; i < TELNETD_NUMLINES; ++i) { - s->lines[i] = NULL; - } - s->bufptr = 0; - s->state = STATE_NORMAL; - - telnetd_connected(s); - senddata(s); - return; - } - - if(s->state == STATE_CLOSE) { - s->state = STATE_NORMAL; - uip_close(); - return; - } - - if(uip_closed()) { - telnetd_output(s, "Connection closed", ""); - } - - - if(uip_aborted()) { - telnetd_output(s, "Connection reset", ""); - } - - if(uip_timedout()) { - telnetd_output(s, "Connection timed out", ""); - } - - if(uip_acked()) { - acked(s); - } - - if(uip_newdata()) { - newdata(s); - } - - if(uip_rexmit() || - uip_newdata() || - uip_acked()) { - senddata(s); - } else if(uip_poll()) { - senddata(s); - } -} -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h deleted file mode 100644 index 254e44ff1..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \addtogroup telnetd - * @{ - */ - -/** - * \file - * Header file for the telnet server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $ - * - */ -#ifndef __TELNETD_H__ -#define __TELNETD_H__ - -#include "uip.h" - -/** - * The maximum length of a telnet line. - * - * \hideinitializer - */ -#define TELNETD_LINELEN 36 - -/** - * The number of output lines being buffered for all telnet - * connections. - * - * \hideinitializer - */ -#define TELNETD_NUMLINES 2 - -/** - * A telnet connection structure. - */ -struct telnetd_state { - char *lines[TELNETD_NUMLINES]; - char buf[TELNETD_LINELEN]; - char bufptr; - u8_t state; -}; - - -/** - * Callback function that is called when a telnet connection has been - * established. - * - * \param s The telnet connection. - */ -void telnetd_connected(struct telnetd_state *s); - -/** - * Callback function that is called when a line of text has arrived on - * a telnet connection. - * - * \param s The telnet connection. - * - * \param cmd The line of text. - */ -void telnetd_input(struct telnetd_state *s, char *cmd); - - -void telnetd_close(struct telnetd_state *s); -void telnetd_output(struct telnetd_state *s, char *s1, char *s2); -void telnetd_prompt(struct telnetd_state *s, char *str); - -void telnetd_app(void); - -#ifndef UIP_APPCALL -#define UIP_APPCALL telnetd_app -#endif - -#ifndef UIP_APPSTATE_SIZE -#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state)) -#endif - -void telnetd_init(void); - - -#endif /* __TELNET_H__ */ - -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip.c deleted file mode 100644 index 37f64facc..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip.c +++ /dev/null @@ -1,1514 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \file - * The uIP TCP/IP stack code. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $ - * - */ - -/* -This is a small implementation of the IP and TCP protocols (as well as -some basic ICMP stuff). The implementation couples the IP, TCP and the -application layers very tightly. To keep the size of the compiled code -down, this code also features heavy usage of the goto statement. - -The principle is that we have a small buffer, called the uip_buf, in -which the device driver puts an incoming packet. The TCP/IP stack -parses the headers in the packet, and calls upon the application. If -the remote host has sent data to the application, this data is present -in the uip_buf and the application read the data from there. It is up -to the application to put this data into a byte stream if needed. The -application will not be fed with data that is out of sequence. - -If the application whishes to send data to the peer, it should put its -data into the uip_buf, 40 bytes from the start of the buffer. The -TCP/IP stack will calculate the checksums, and fill in the necessary -header fields and finally send the packet back to the peer. -*/ - -#include "uip.h" -#include "uipopt.h" -#include "uip_arch.h" - -/*-----------------------------------------------------------------------------------*/ -/* Variable definitions. */ - - -/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */ -#if UIP_FIXEDADDR > 0 -const u16_t uip_hostaddr[2] = - {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), - HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; -const u16_t uip_arp_draddr[2] = - {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), - HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; -const u16_t uip_arp_netmask[2] = - {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), - HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; -#else -u16_t uip_hostaddr[2]; -u16_t uip_arp_draddr[2], uip_arp_netmask[2]; -#endif /* UIP_FIXEDADDR */ - -u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains - incoming packets. */ -volatile u8_t *uip_appdata; /* The uip_appdata pointer points to - application data. */ -volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the - application data which is to be sent. */ -#if UIP_URGDATA > 0 -volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to - urgent data (out-of-band data), if - present. */ -volatile u8_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - -volatile u16_t uip_len, uip_slen; - /* The uip_len is either 8 or 16 bits, - depending on the maximum packet - size. */ - -volatile u8_t uip_flags; /* The uip_flags variable is used for - communication between the TCP/IP stack - and the application program. */ -struct uip_conn *uip_conn; /* uip_conn always points to the current - connection. */ - -struct uip_conn uip_conns[UIP_CONNS]; - /* The uip_conns array holds all TCP - connections. */ -u16_t uip_listenports[UIP_LISTENPORTS]; - /* The uip_listenports list all currently - listning ports. */ -#if UIP_UDP -struct uip_udp_conn *uip_udp_conn; -struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - - -static u16_t ipid; /* Ths ipid variable is an increasing - number that is used for the IP ID - field. */ - -static u8_t iss[4]; /* The iss variable is used for the TCP - initial sequence number. */ - -#if UIP_ACTIVE_OPEN -static u16_t lastport; /* Keeps track of the last port used for - a new connection. */ -#endif /* UIP_ACTIVE_OPEN */ - -/* Temporary variables. */ -volatile u8_t uip_acc32[4]; -static u8_t c, opt; -static u16_t tmp16; - -/* Structures and definitions. */ -#define TCP_FIN 0x01 -#define TCP_SYN 0x02 -#define TCP_RST 0x04 -#define TCP_PSH 0x08 -#define TCP_ACK 0x10 -#define TCP_URG 0x20 -#define TCP_CTL 0x3f - -#define ICMP_ECHO_REPLY 0 -#define ICMP_ECHO 8 - -/* Macros. */ -#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0]) -#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) - -#if UIP_STATISTICS == 1 -struct uip_stats uip_stat; -#define UIP_STAT(s) s -#else -#define UIP_STAT(s) -#endif /* UIP_STATISTICS == 1 */ - -#if UIP_LOGGING == 1 -#include -void uip_log(char *msg); -#define UIP_LOG(m) uip_log(m) -#else -#define UIP_LOG(m) -#endif /* UIP_LOGGING == 1 */ - -/*-----------------------------------------------------------------------------------*/ -void -uip_init(void) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - uip_listenports[c] = 0; - } - for(c = 0; c < UIP_CONNS; ++c) { - uip_conns[c].tcpstateflags = CLOSED; - } -#if UIP_ACTIVE_OPEN - lastport = 1024; -#endif /* UIP_ACTIVE_OPEN */ - -#if UIP_UDP - for(c = 0; c < UIP_UDP_CONNS; ++c) { - uip_udp_conns[c].lport = 0; - } -#endif /* UIP_UDP */ - - - /* IPv4 initialization. */ -#if UIP_FIXEDADDR == 0 - uip_hostaddr[0] = uip_hostaddr[1] = 0; -#endif /* UIP_FIXEDADDR */ - -} -/*-----------------------------------------------------------------------------------*/ -#if UIP_ACTIVE_OPEN -struct uip_conn * -uip_connect(u16_t *ripaddr, u16_t rport) -{ - register struct uip_conn *conn, *cconn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - /* Check if this port is already in use, and if so try to find - another one. */ - for(c = 0; c < UIP_CONNS; ++c) { - conn = &uip_conns[c]; - if(conn->tcpstateflags != CLOSED && - conn->lport == htons(lastport)) { - goto again; - } - } - - - conn = 0; - for(c = 0; c < UIP_CONNS; ++c) { - cconn = &uip_conns[c]; - if(cconn->tcpstateflags == CLOSED) { - conn = cconn; - break; - } - if(cconn->tcpstateflags == TIME_WAIT) { - if(conn == 0 || - cconn->timer > uip_conn->timer) { - conn = cconn; - } - } - } - - if(conn == 0) { - return 0; - } - - conn->tcpstateflags = SYN_SENT; - - conn->snd_nxt[0] = iss[0]; - conn->snd_nxt[1] = iss[1]; - conn->snd_nxt[2] = iss[2]; - conn->snd_nxt[3] = iss[3]; - - conn->initialmss = conn->mss = UIP_TCP_MSS; - - conn->len = 1; /* TCP length of the SYN is one. */ - conn->nrtx = 0; - conn->timer = 1; /* Send the SYN next time around. */ - conn->rto = UIP_RTO; - conn->sa = 0; - conn->sv = 16; - conn->lport = htons(lastport); - conn->rport = rport; - conn->ripaddr[0] = ripaddr[0]; - conn->ripaddr[1] = ripaddr[1]; - - return conn; -} -#endif /* UIP_ACTIVE_OPEN */ -/*-----------------------------------------------------------------------------------*/ -#if UIP_UDP -struct uip_udp_conn * -uip_udp_new(u16_t *ripaddr, u16_t rport) -{ - register struct uip_udp_conn *conn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == lastport) { - goto again; - } - } - - - conn = 0; - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == 0) { - conn = &uip_udp_conns[c]; - break; - } - } - - if(conn == 0) { - return 0; - } - - conn->lport = HTONS(lastport); - conn->rport = HTONS(rport); - conn->ripaddr[0] = ripaddr[0]; - conn->ripaddr[1] = ripaddr[1]; - - return conn; -} -#endif /* UIP_UDP */ -/*-----------------------------------------------------------------------------------*/ -void -uip_unlisten(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == port) { - uip_listenports[c] = 0; - return; - } - } -} -/*-----------------------------------------------------------------------------------*/ -void -uip_listen(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == 0) { - uip_listenports[c] = port; - return; - } - } -} -/*-----------------------------------------------------------------------------------*/ -/* XXX: IP fragment reassembly: not well-tested. */ - -#if UIP_REASSEMBLY -#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) -static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; -static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; -static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, - 0x0f, 0x07, 0x03, 0x01}; -static u16_t uip_reasslen; -static u8_t uip_reassflags; -#define UIP_REASS_FLAG_LASTFRAG 0x01 -static u8_t uip_reasstmr; - -#define IP_HLEN 20 -#define IP_MF 0x20 - -static u8_t -uip_reass(void) -{ - u16_t offset, len; - u16_t i; - - /* If ip_reasstmr is zero, no packet is present in the buffer, so we - write the IP header of the fragment into the reassembly - buffer. The timer is updated with the maximum age. */ - if(uip_reasstmr == 0) { - memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN); - uip_reasstmr = UIP_REASS_MAXAGE; - uip_reassflags = 0; - /* Clear the bitmap. */ - memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0); - } - - /* Check if the incoming fragment matches the one currently present - in the reasembly buffer. If so, we proceed with copying the - fragment into the buffer. */ - if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && - BUF->srcipaddr[1] == FBUF->srcipaddr[1] && - BUF->destipaddr[0] == FBUF->destipaddr[0] && - BUF->destipaddr[1] == FBUF->destipaddr[1] && - BUF->ipid[0] == FBUF->ipid[0] && - BUF->ipid[1] == FBUF->ipid[1]) { - - len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; - offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; - - /* If the offset or the offset + fragment length overflows the - reassembly buffer, we discard the entire packet. */ - if(offset > UIP_REASS_BUFSIZE || - offset + len > UIP_REASS_BUFSIZE) { - uip_reasstmr = 0; - goto nullreturn; - } - - /* Copy the fragment into the reassembly buffer, at the right - offset. */ - memcpy(&uip_reassbuf[IP_HLEN + offset], - (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), - len); - - /* Update the bitmap. */ - if(offset / (8 * 8) == (offset + len) / (8 * 8)) { - /* If the two endpoints are in the same byte, we only update - that byte. */ - - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7] & - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } else { - /* If the two endpoints are in different bytes, we update the - bytes in the endpoints and fill the stuff inbetween with - 0xff. */ - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7]; - for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { - uip_reassbitmap[i] = 0xff; - } - uip_reassbitmap[(offset + len) / (8 * 8)] |= - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } - - /* If this fragment has the More Fragments flag set to zero, we - know that this is the last fragment, so we can calculate the - size of the entire packet. We also set the - IP_REASS_FLAG_LASTFRAG flag to indicate that we have received - the final fragment. */ - - if((BUF->ipoffset[0] & IP_MF) == 0) { - uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; - uip_reasslen = offset + len; - } - - /* Finally, we check if we have a full packet in the buffer. We do - this by checking if we have the last fragment and if all bits - in the bitmap are set. */ - if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { - /* Check all bytes up to and including all but the last byte in - the bitmap. */ - for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { - if(uip_reassbitmap[i] != 0xff) { - goto nullreturn; - } - } - /* Check the last byte in the bitmap. It should contain just the - right amount of bits. */ - if(uip_reassbitmap[uip_reasslen / (8 * 8)] != - (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { - goto nullreturn; - } - - /* If we have come this far, we have a full packet in the - buffer, so we allocate a pbuf and copy the packet into it. We - also reset the timer. */ - uip_reasstmr = 0; - memcpy(BUF, FBUF, uip_reasslen); - - /* Pretend to be a "normal" (i.e., not fragmented) IP packet - from now on. */ - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - BUF->len[0] = uip_reasslen >> 8; - BUF->len[1] = uip_reasslen & 0xff; - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - - return uip_reasslen; - } - } - - nullreturn: - return 0; -} -#endif /* UIP_REASSEMBL */ -/*-----------------------------------------------------------------------------------*/ -static void -uip_add_rcv_nxt(u16_t n) -{ - uip_add32(uip_conn->rcv_nxt, n); - uip_conn->rcv_nxt[0] = uip_acc32[0]; - uip_conn->rcv_nxt[1] = uip_acc32[1]; - uip_conn->rcv_nxt[2] = uip_acc32[2]; - uip_conn->rcv_nxt[3] = uip_acc32[3]; -} -/*-----------------------------------------------------------------------------------*/ -void -uip_process(u8_t flag) -{ - register struct uip_conn *uip_connr = uip_conn; - - uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; - - - /* Check if we were invoked because of the perodic timer fireing. */ - if(flag == UIP_TIMER) { -#if UIP_REASSEMBLY - if(uip_reasstmr != 0) { - --uip_reasstmr; - } -#endif /* UIP_REASSEMBLY */ - /* Increase the initial sequence number. */ - if(++iss[3] == 0) { - if(++iss[2] == 0) { - if(++iss[1] == 0) { - ++iss[0]; - } - } - } - uip_len = 0; - if(uip_connr->tcpstateflags == TIME_WAIT || - uip_connr->tcpstateflags == FIN_WAIT_2) { - ++(uip_connr->timer); - if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { - uip_connr->tcpstateflags = CLOSED; - } - } else if(uip_connr->tcpstateflags != CLOSED) { - /* If the connection has outstanding data, we increase the - connection's timer and see if it has reached the RTO value - in which case we retransmit. */ - if(uip_outstanding(uip_connr)) { - if(uip_connr->timer-- == 0) { - if(uip_connr->nrtx == UIP_MAXRTX || - ((uip_connr->tcpstateflags == SYN_SENT || - uip_connr->tcpstateflags == SYN_RCVD) && - uip_connr->nrtx == UIP_MAXSYNRTX)) { - uip_connr->tcpstateflags = CLOSED; - - /* We call UIP_APPCALL() with uip_flags set to - UIP_TIMEDOUT to inform the application that the - connection has timed out. */ - uip_flags = UIP_TIMEDOUT; - UIP_APPCALL(); - - /* We also send a reset packet to the remote host. */ - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - /* Exponential backoff. */ - uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? - 4: - uip_connr->nrtx); - ++(uip_connr->nrtx); - - /* Ok, so we need to retransmit. We do this differently - depending on which state we are in. In ESTABLISHED, we - call upon the application so that it may prepare the - data for the retransmit. In SYN_RCVD, we resend the - SYNACK that we sent earlier and in LAST_ACK we have to - retransmit our FINACK. */ - UIP_STAT(++uip_stat.tcp.rexmit); - switch(uip_connr->tcpstateflags & TS_MASK) { - case SYN_RCVD: - /* In the SYN_RCVD state, we should retransmit our - SYNACK. */ - goto tcp_send_synack; - -#if UIP_ACTIVE_OPEN - case SYN_SENT: - /* In the SYN_SENT state, we retransmit out SYN. */ - BUF->flags = 0; - goto tcp_send_syn; -#endif /* UIP_ACTIVE_OPEN */ - - case ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application - to do the actual retransmit after which we jump into - the code for sending out the packet (the apprexmit - label). */ - uip_len = 0; - uip_slen = 0; - uip_flags = UIP_REXMIT; - UIP_APPCALL(); - goto apprexmit; - - case FIN_WAIT_1: - case CLOSING: - case LAST_ACK: - /* In all these states we should retransmit a FINACK. */ - goto tcp_send_finack; - - } - } - } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) { - /* If there was no need for a retransmission, we poll the - application for new data. */ - uip_len = 0; - uip_slen = 0; - uip_flags = UIP_POLL; - UIP_APPCALL(); - goto appsend; - } - } - goto drop; - } -#if UIP_UDP - if(flag == UIP_UDP_TIMER) { - if(uip_udp_conn->lport != 0) { - uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; - uip_len = uip_slen = 0; - uip_flags = UIP_POLL; - UIP_UDP_APPCALL(); - goto udp_send; - } else { - goto drop; - } - } -#endif - - /* This is where the input processing starts. */ - UIP_STAT(++uip_stat.ip.recv); - - - /* Start of IPv4 input header processing code. */ - - /* Check validity of the IP header. */ - if(BUF->vhl != 0x45) { /* IP version and header length. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.vhlerr); - UIP_LOG("ip: invalid version or header length."); - goto drop; - } - - /* Check the size of the packet. If the size reported to us in - uip_len doesn't match the size reported in the IP header, there - has been a transmission error and we drop the packet. */ - - if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */ - uip_len = (uip_len & 0xff) | (BUF->len[0] << 8); - } - if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */ - uip_len = (uip_len & 0xff00) | BUF->len[1]; - } - - /* Check the fragment flag. */ - if((BUF->ipoffset[0] & 0x3f) != 0 || - BUF->ipoffset[1] != 0) { -#if UIP_REASSEMBLY - uip_len = uip_reass(); - if(uip_len == 0) { - goto drop; - } -#else - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.fragerr); - UIP_LOG("ip: fragment dropped."); - goto drop; -#endif /* UIP_REASSEMBLY */ - } - - /* If we are configured to use ping IP address configuration and - hasn't been assigned an IP address yet, we accept all ICMP - packets. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { - if(BUF->proto == UIP_PROTO_ICMP) { - UIP_LOG("ip: possible ping config packet received."); - goto icmp_input; - } else { - UIP_LOG("ip: packet dropped since no address assigned."); - goto drop; - } - } -#endif /* UIP_PINGADDRCONF */ - - /* Check if the packet is destined for our IP address. */ - if(BUF->destipaddr[0] != uip_hostaddr[0]) { - UIP_STAT(++uip_stat.ip.drop); - UIP_LOG("ip: packet not for us."); - goto drop; - } - if(BUF->destipaddr[1] != uip_hostaddr[1]) { - UIP_STAT(++uip_stat.ip.drop); - UIP_LOG("ip: packet not for us."); - goto drop; - } - -#if 0 - // IP checksum is wrong through Netgear DSL router - if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header - checksum. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.chkerr); - UIP_LOG("ip: bad checksum."); - goto drop; - } -#endif - - if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump - to the tcp_input label. */ - goto tcp_input; - -#if UIP_UDP - if(BUF->proto == UIP_PROTO_UDP) - goto udp_input; -#endif /* UIP_UDP */ - - if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from - here. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.protoerr); - UIP_LOG("ip: neither tcp nor icmp."); - goto drop; - } - -#if UIP_PINGADDRCONF - icmp_input: -#endif - UIP_STAT(++uip_stat.icmp.recv); - - /* ICMP echo (i.e., ping) processing. This is simple, we only change - the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP - checksum before we return the packet. */ - if(ICMPBUF->type != ICMP_ECHO) { - UIP_STAT(++uip_stat.icmp.drop); - UIP_STAT(++uip_stat.icmp.typeerr); - UIP_LOG("icmp: not icmp echo."); - goto drop; - } - - /* If we are configured to use ping IP address assignment, we use - the destination IP address of this ping packet and assign it to - ourself. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { - uip_hostaddr[0] = BUF->destipaddr[0]; - uip_hostaddr[1] = BUF->destipaddr[1]; - } -#endif /* UIP_PINGADDRCONF */ - - ICMPBUF->type = ICMP_ECHO_REPLY; - - if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; - } else { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); - } - - /* Swap IP addresses. */ - tmp16 = BUF->destipaddr[0]; - BUF->destipaddr[0] = BUF->srcipaddr[0]; - BUF->srcipaddr[0] = tmp16; - tmp16 = BUF->destipaddr[1]; - BUF->destipaddr[1] = BUF->srcipaddr[1]; - BUF->srcipaddr[1] = tmp16; - - UIP_STAT(++uip_stat.icmp.sent); - goto send; - - /* End of IPv4 input header processing code. */ - - -#if UIP_UDP - /* UDP input processing. */ - udp_input: - /* UDP processing is really just a hack. We don't do anything to the - UDP/IP headers, but let the UDP application do all the hard - work. If the application sets uip_slen, it has a packet to - send. */ -#if UIP_UDP_CHECKSUMS - if(uip_udpchksum() != 0xffff) { - UIP_STAT(++uip_stat.udp.drop); - UIP_STAT(++uip_stat.udp.chkerr); - UIP_LOG("udp: bad checksum."); - goto drop; - } -#endif /* UIP_UDP_CHECKSUMS */ - - /* Demultiplex this UDP packet between the UDP "connections". */ - for(uip_udp_conn = &uip_udp_conns[0]; - uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; - ++uip_udp_conn) { - if(uip_udp_conn->lport != 0 && - UDPBUF->destport == uip_udp_conn->lport && - (uip_udp_conn->rport == 0 || - UDPBUF->srcport == uip_udp_conn->rport) && - BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] && - BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) { - goto udp_found; - } - } - goto drop; - - udp_found: - uip_len = uip_len - 28; - uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; - uip_flags = UIP_NEWDATA; - uip_slen = 0; - UIP_UDP_APPCALL(); - udp_send: - if(uip_slen == 0) { - goto drop; - } - uip_len = uip_slen + 28; - - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); - - BUF->proto = UIP_PROTO_UDP; - - UDPBUF->udplen = HTONS(uip_slen + 8); - UDPBUF->udpchksum = 0; -#if UIP_UDP_CHECKSUMS - /* Calculate UDP checksum. */ - UDPBUF->udpchksum = ~(uip_udpchksum()); - if(UDPBUF->udpchksum == 0) { - UDPBUF->udpchksum = 0xffff; - } -#endif /* UIP_UDP_CHECKSUMS */ - - BUF->srcport = uip_udp_conn->lport; - BUF->destport = uip_udp_conn->rport; - - BUF->srcipaddr[0] = uip_hostaddr[0]; - BUF->srcipaddr[1] = uip_hostaddr[1]; - BUF->destipaddr[0] = uip_udp_conn->ripaddr[0]; - BUF->destipaddr[1] = uip_udp_conn->ripaddr[1]; - - uip_appdata = &uip_buf[UIP_LLH_LEN + 40]; - goto ip_send_nolen; -#endif /* UIP_UDP */ - - /* TCP input processing. */ - tcp_input: - UIP_STAT(++uip_stat.tcp.recv); - - /* Start of TCP input header processing code. */ - -#if 1 // FIXME - if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP - checksum. */ - UIP_STAT(++uip_stat.tcp.drop); - UIP_STAT(++uip_stat.tcp.chkerr); - UIP_LOG("tcp: bad checksum."); - goto drop; - } -#endif - - /* Demultiplex this segment. */ - /* First check any active connections. */ - for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) { - if(uip_connr->tcpstateflags != CLOSED && - BUF->destport == uip_connr->lport && - BUF->srcport == uip_connr->rport && - BUF->srcipaddr[0] == uip_connr->ripaddr[0] && - BUF->srcipaddr[1] == uip_connr->ripaddr[1]) { - goto found; - } - } - - /* If we didn't find and active connection that expected the packet, - either this packet is an old duplicate, or this is a SYN packet - destined for a connection in LISTEN. If the SYN flag isn't set, - it is an old packet and we send a RST. */ - if((BUF->flags & TCP_CTL) != TCP_SYN) - goto reset; - - tmp16 = BUF->destport; - /* Next, check listening connections. */ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(tmp16 == uip_listenports[c]) - goto found_listen; - } - - /* No matching connection found, so we send a RST packet. */ - UIP_STAT(++uip_stat.tcp.synrst); - reset: - - /* We do not send resets in response to resets. */ - if(BUF->flags & TCP_RST) - goto drop; - - UIP_STAT(++uip_stat.tcp.rst); - - BUF->flags = TCP_RST | TCP_ACK; - uip_len = 40; - BUF->tcpoffset = 5 << 4; - - /* Flip the seqno and ackno fields in the TCP header. */ - c = BUF->seqno[3]; - BUF->seqno[3] = BUF->ackno[3]; - BUF->ackno[3] = c; - - c = BUF->seqno[2]; - BUF->seqno[2] = BUF->ackno[2]; - BUF->ackno[2] = c; - - c = BUF->seqno[1]; - BUF->seqno[1] = BUF->ackno[1]; - BUF->ackno[1] = c; - - c = BUF->seqno[0]; - BUF->seqno[0] = BUF->ackno[0]; - BUF->ackno[0] = c; - - /* We also have to increase the sequence number we are - acknowledging. If the least significant byte overflowed, we need - to propagate the carry to the other bytes as well. */ - if(++BUF->ackno[3] == 0) { - if(++BUF->ackno[2] == 0) { - if(++BUF->ackno[1] == 0) { - ++BUF->ackno[0]; - } - } - } - - /* Swap port numbers. */ - tmp16 = BUF->srcport; - BUF->srcport = BUF->destport; - BUF->destport = tmp16; - - /* Swap IP addresses. */ - tmp16 = BUF->destipaddr[0]; - BUF->destipaddr[0] = BUF->srcipaddr[0]; - BUF->srcipaddr[0] = tmp16; - tmp16 = BUF->destipaddr[1]; - BUF->destipaddr[1] = BUF->srcipaddr[1]; - BUF->srcipaddr[1] = tmp16; - - - /* And send out the RST packet! */ - goto tcp_send_noconn; - - /* This label will be jumped to if we matched the incoming packet - with a connection in LISTEN. In that case, we should create a new - connection and send a SYNACK in return. */ - found_listen: - /* First we check if there are any connections avaliable. Unused - connections are kept in the same table as used connections, but - unused ones have the tcpstate set to CLOSED. Also, connections in - TIME_WAIT are kept track of and we'll use the oldest one if no - CLOSED connections are found. Thanks to Eddie C. Dost for a very - nice algorithm for the TIME_WAIT search. */ - uip_connr = 0; - for(c = 0; c < UIP_CONNS; ++c) { - if(uip_conns[c].tcpstateflags == CLOSED) { - uip_connr = &uip_conns[c]; - break; - } - if(uip_conns[c].tcpstateflags == TIME_WAIT) { - if(uip_connr == 0 || - uip_conns[c].timer > uip_connr->timer) { - uip_connr = &uip_conns[c]; - } - } - } - - if(uip_connr == 0) { - /* All connections are used already, we drop packet and hope that - the remote end will retransmit the packet at a time when we - have more spare connections. */ - UIP_STAT(++uip_stat.tcp.syndrop); - UIP_LOG("tcp: found no unused connections."); - goto drop; - } - uip_conn = uip_connr; - - /* Fill in the necessary fields for the new connection. */ - uip_connr->rto = uip_connr->timer = UIP_RTO; - uip_connr->sa = 0; - uip_connr->sv = 4; - uip_connr->nrtx = 0; - uip_connr->lport = BUF->destport; - uip_connr->rport = BUF->srcport; - uip_connr->ripaddr[0] = BUF->srcipaddr[0]; - uip_connr->ripaddr[1] = BUF->srcipaddr[1]; - uip_connr->tcpstateflags = SYN_RCVD; - - uip_connr->snd_nxt[0] = iss[0]; - uip_connr->snd_nxt[1] = iss[1]; - uip_connr->snd_nxt[2] = iss[2]; - uip_connr->snd_nxt[3] = iss[3]; - uip_connr->len = 1; - - /* rcv_nxt should be the seqno from the incoming packet + 1. */ - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_add_rcv_nxt(1); - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; - if(opt == 0x00) { - /* End of options. */ - break; - } else if(opt == 0x01) { - ++c; - /* NOP option. */ - } else if(opt == 0x02 && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { - /* An MSS option with the right option length. */ - tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = uip_connr->mss = - tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - - /* Our response will be a SYNACK. */ -#if UIP_ACTIVE_OPEN - tcp_send_synack: - BUF->flags = TCP_ACK; - - tcp_send_syn: - BUF->flags |= TCP_SYN; -#else /* UIP_ACTIVE_OPEN */ - tcp_send_synack: - BUF->flags = TCP_SYN | TCP_ACK; -#endif /* UIP_ACTIVE_OPEN */ - - /* We send out the TCP Maximum Segment Size option with our - SYNACK. */ - BUF->optdata[0] = 2; - BUF->optdata[1] = 4; - BUF->optdata[2] = (UIP_TCP_MSS) / 256; - BUF->optdata[3] = (UIP_TCP_MSS) & 255; - uip_len = 44; - BUF->tcpoffset = 6 << 4; - goto tcp_send; - - /* This label will be jumped to if we found an active connection. */ - found: - uip_conn = uip_connr; - uip_flags = 0; - - /* We do a very naive form of TCP reset processing; we just accept - any RST and kill our connection. We should in fact check if the - sequence number of this reset is wihtin our advertised window - before we accept the reset. */ - if(BUF->flags & TCP_RST) { - uip_connr->tcpstateflags = CLOSED; - UIP_LOG("tcp: got reset, aborting connection."); - uip_flags = UIP_ABORT; - UIP_APPCALL(); - goto drop; - } - /* Calculated the length of the data, if the application has sent - any data to us. */ - c = (BUF->tcpoffset >> 4) << 2; - /* uip_len will contain the length of the actual TCP data. This is - calculated by subtracing the length of the TCP header (in - c) and the length of the IP header (20 bytes). */ - uip_len = uip_len - c - 20; - - /* First, check if the sequence number of the incoming packet is - what we're expecting next. If not, we send out an ACK with the - correct numbers in. */ - if(uip_len > 0 && - (BUF->seqno[0] != uip_connr->rcv_nxt[0] || - BUF->seqno[1] != uip_connr->rcv_nxt[1] || - BUF->seqno[2] != uip_connr->rcv_nxt[2] || - BUF->seqno[3] != uip_connr->rcv_nxt[3])) { - goto tcp_send_ack; - } - - /* Next, check if the incoming segment acknowledges any outstanding - data. If so, we update the sequence number, reset the length of - the outstanding data, calculate RTT estimations, and reset the - retransmission timer. */ - if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { - uip_add32(uip_connr->snd_nxt, uip_connr->len); - if(BUF->ackno[0] == uip_acc32[0] && - BUF->ackno[1] == uip_acc32[1] && - BUF->ackno[2] == uip_acc32[2] && - BUF->ackno[3] == uip_acc32[3]) { - /* Update sequence number. */ - uip_connr->snd_nxt[0] = uip_acc32[0]; - uip_connr->snd_nxt[1] = uip_acc32[1]; - uip_connr->snd_nxt[2] = uip_acc32[2]; - uip_connr->snd_nxt[3] = uip_acc32[3]; - - - /* Do RTT estimation, unless we have done retransmissions. */ - if(uip_connr->nrtx == 0) { - signed char m; - m = uip_connr->rto - uip_connr->timer; - /* This is taken directly from VJs original code in his paper */ - m = m - (uip_connr->sa >> 3); - uip_connr->sa += m; - if(m < 0) { - m = -m; - } - m = m - (uip_connr->sv >> 2); - uip_connr->sv += m; - uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; - - } - /* Set the acknowledged flag. */ - uip_flags = UIP_ACKDATA; - /* Reset the retransmission timer. */ - uip_connr->timer = uip_connr->rto; - } - - } - - /* Do different things depending on in what state the connection is. */ - switch(uip_connr->tcpstateflags & TS_MASK) { - /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not - implemented, since we force the application to close when the - peer sends a FIN (hence the application goes directly from - ESTABLISHED to LAST_ACK). */ - case SYN_RCVD: - /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and - we are waiting for an ACK that acknowledges the data we sent - out the last time. Therefore, we want to have the UIP_ACKDATA - flag set. If so, we enter the ESTABLISHED state. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = ESTABLISHED; - uip_flags = UIP_CONNECTED; - uip_connr->len = 0; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - goto drop; -#if UIP_ACTIVE_OPEN - case SYN_SENT: - /* In SYN_SENT, we wait for a SYNACK that is sent in response to - our SYN. The rcv_nxt is set to sequence number in the SYNACK - plus one, and we send an ACK. We move into the ESTABLISHED - state. */ - if((uip_flags & UIP_ACKDATA) && - BUF->flags == (TCP_SYN | TCP_ACK)) { - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[40 + UIP_LLH_LEN + c]; - if(opt == 0x00) { - /* End of options. */ - break; - } else if(opt == 0x01) { - ++c; - /* NOP option. */ - } else if(opt == 0x02 && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { - /* An MSS option with the right option length. */ - tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = - uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - uip_connr->tcpstateflags = ESTABLISHED; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_add_rcv_nxt(1); - uip_flags = UIP_CONNECTED | UIP_NEWDATA; - uip_connr->len = 0; - uip_len = 0; - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - goto reset; -#endif /* UIP_ACTIVE_OPEN */ - - case ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application to feed - data into the uip_buf. If the UIP_ACKDATA flag is set, the - application should put new data into the buffer, otherwise we are - retransmitting an old segment, and the application should put that - data into the buffer. - - If the incoming packet is a FIN, we should close the connection on - this side as well, and we send out a FIN and enter the LAST_ACK - state. We require that there is no outstanding data; otherwise the - sequence numbers will be screwed up. */ - - if(BUF->flags & TCP_FIN) { - if(uip_outstanding(uip_connr)) { - goto drop; - } - uip_add_rcv_nxt(1 + uip_len); - uip_flags = UIP_CLOSE; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - } - UIP_APPCALL(); - uip_connr->len = 1; - uip_connr->tcpstateflags = LAST_ACK; - uip_connr->nrtx = 0; - tcp_send_finack: - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* Check the URG flag. If this is set, the segment carries urgent - data that we must pass to the application. */ - if(BUF->flags & TCP_URG) { -#if UIP_URGDATA > 0 - uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; - if(uip_urglen > uip_len) { - /* There is more urgent data in the next segment to come. */ - uip_urglen = uip_len; - } - uip_add_rcv_nxt(uip_urglen); - uip_len -= uip_urglen; - uip_urgdata = uip_appdata; - uip_appdata += uip_urglen; - } else { - uip_urglen = 0; -#endif /* UIP_URGDATA > 0 */ - uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1]; - uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; - } - - - /* If uip_len > 0 we have TCP data in the packet, and we flag this - by setting the UIP_NEWDATA flag and update the sequence number - we acknowledge. If the application has stopped the dataflow - using uip_stop(), we must not accept any data packets from the - remote host. */ - if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - - /* Check if the available buffer space advertised by the other end - is smaller than the initial MSS for this connection. If so, we - set the current MSS to the window size to ensure that the - application does not send more data than the other end can - handle. - - If the remote host advertises a zero window, we set the MSS to - the initial MSS so that the application will send an entire MSS - of data. This data will not be acknowledged by the receiver, - and the application will retransmit it. This is called the - "persistent timer" and uses the retransmission mechanim. - */ - tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1]; - if(tmp16 > uip_connr->initialmss || - tmp16 == 0) { - tmp16 = uip_connr->initialmss; - } - uip_connr->mss = tmp16; - - /* If this packet constitutes an ACK for outstanding data (flagged - by the UIP_ACKDATA flag, we should call the application since it - might want to send more data. If the incoming packet had data - from the peer (as flagged by the UIP_NEWDATA flag), the - application must also be notified. - - When the application is called, the global variable uip_len - contains the length of the incoming data. The application can - access the incoming data through the global pointer - uip_appdata, which usually points 40 bytes into the uip_buf - array. - - If the application wishes to send any data, this data should be - put into the uip_appdata and the length of the data should be - put into uip_len. If the application don't have any data to - send, uip_len must be set to 0. */ - if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { - uip_slen = 0; - UIP_APPCALL(); - - appsend: - - if(uip_flags & UIP_ABORT) { - uip_slen = 0; - uip_connr->tcpstateflags = CLOSED; - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - if(uip_flags & UIP_CLOSE) { - uip_slen = 0; - uip_connr->len = 1; - uip_connr->tcpstateflags = FIN_WAIT_1; - uip_connr->nrtx = 0; - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* If uip_slen > 0, the application has data to be sent. */ - if(uip_slen > 0) { - - /* If the connection has acknowledged data, the contents of - the ->len variable should be discarded. */ - if((uip_flags & UIP_ACKDATA) != 0) { - uip_connr->len = 0; - } - - /* If the ->len variable is non-zero the connection has - already data in transit and cannot send anymore right - now. */ - if(uip_connr->len == 0) { - - /* The application cannot send more than what is allowed by - the mss (the minumum of the MSS and the available - window). */ - if(uip_slen > uip_connr->mss) { - uip_slen = uip_connr->mss; - } - - /* Remember how much data we send out now so that we know - when everything has been acknowledged. */ - uip_connr->len = uip_slen; - } else { - - /* If the application already had unacknowledged data, we - make sure that the application does not send (i.e., - retransmit) out more than it previously sent out. */ - uip_slen = uip_connr->len; - } - } else { - uip_connr->len = 0; - } - uip_connr->nrtx = 0; - apprexmit: - uip_appdata = uip_sappdata; - - /* If the application has data to be sent, or if the incoming - packet had new data in it, we must send out a packet. */ - if(uip_slen > 0 && uip_connr->len > 0) { - /* Add the length of the IP and TCP headers. */ - uip_len = uip_connr->len + UIP_TCPIP_HLEN; - /* We always set the ACK flag in response packets. */ - BUF->flags = TCP_ACK | TCP_PSH; - /* Send the packet. */ - goto tcp_send_noopts; - } - /* If there is no data to send, just send out a pure ACK if - there is newdata. */ - if(uip_flags & UIP_NEWDATA) { - uip_len = UIP_TCPIP_HLEN; - BUF->flags = TCP_ACK; - goto tcp_send_noopts; - } - } - goto drop; - case LAST_ACK: - /* We can close this connection if the peer has acknowledged our - FIN. This is indicated by the UIP_ACKDATA flag. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = CLOSED; - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - } - break; - - case FIN_WAIT_1: - /* The application has closed the connection, but the remote host - hasn't closed its end yet. Thus we do nothing but wait for a - FIN from the other side. */ - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - uip_connr->len = 0; - } else { - uip_connr->tcpstateflags = CLOSING; - } - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } else if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = FIN_WAIT_2; - uip_connr->len = 0; - goto drop; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case FIN_WAIT_2: - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case TIME_WAIT: - goto tcp_send_ack; - - case CLOSING: - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - } - } - goto drop; - - - /* We jump here when we are ready to send the packet, and just want - to set the appropriate TCP sequence numbers in the TCP header. */ - tcp_send_ack: - BUF->flags = TCP_ACK; - tcp_send_nodata: - uip_len = 40; - tcp_send_noopts: - BUF->tcpoffset = 5 << 4; - tcp_send: - /* We're done with the input processing. We are now ready to send a - reply. Our job is to fill in all the fields of the TCP and IP - headers before calculating the checksum and finally send the - packet. */ - BUF->ackno[0] = uip_connr->rcv_nxt[0]; - BUF->ackno[1] = uip_connr->rcv_nxt[1]; - BUF->ackno[2] = uip_connr->rcv_nxt[2]; - BUF->ackno[3] = uip_connr->rcv_nxt[3]; - - BUF->seqno[0] = uip_connr->snd_nxt[0]; - BUF->seqno[1] = uip_connr->snd_nxt[1]; - BUF->seqno[2] = uip_connr->snd_nxt[2]; - BUF->seqno[3] = uip_connr->snd_nxt[3]; - - BUF->proto = UIP_PROTO_TCP; - - BUF->srcport = uip_connr->lport; - BUF->destport = uip_connr->rport; - - BUF->srcipaddr[0] = uip_hostaddr[0]; - BUF->srcipaddr[1] = uip_hostaddr[1]; - BUF->destipaddr[0] = uip_connr->ripaddr[0]; - BUF->destipaddr[1] = uip_connr->ripaddr[1]; - - - if(uip_connr->tcpstateflags & UIP_STOPPED) { - /* If the connection has issued uip_stop(), we advertise a zero - window so that the remote host will stop sending data. */ - BUF->wnd[0] = BUF->wnd[1] = 0; - } else { - BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); - BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); - } - - tcp_send_noconn: - - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); - - /* Calculate TCP checksum. */ - BUF->tcpchksum = 0; - BUF->tcpchksum = ~(uip_tcpchksum()); - - -#if UIP_UDP - ip_send_nolen: -#endif - - BUF->vhl = 0x45; - BUF->tos = 0; - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - BUF->ttl = UIP_TTL; - ++ipid; - BUF->ipid[0] = ipid >> 8; - BUF->ipid[1] = ipid & 0xff; - - /* Calculate IP checksum. */ - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - - UIP_STAT(++uip_stat.tcp.sent); - send: - UIP_STAT(++uip_stat.ip.sent); - /* Return and let the caller do the actual transmission. */ - return; - drop: - uip_len = 0; - return; -} -/*-----------------------------------------------------------------------------------*/ -u16_t -htons(u16_t val) -{ - return HTONS(val); -} -/*-----------------------------------------------------------------------------------*/ -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip.h deleted file mode 100644 index 0ff1b2a79..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip.h +++ /dev/null @@ -1,1060 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \file - * Header file for the uIP TCP/IP stack. - * \author Adam Dunkels - * - * The uIP TCP/IP stack header file contains definitions for a number - * of C macros that are used by uIP programs as well as internal uIP - * structures, TCP/IP header structures and function declarations. - * - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $ - * - */ - -#ifndef __UIP_H__ -#define __UIP_H__ - -#include "uipopt.h" - -/*-----------------------------------------------------------------------------------*/ -/* First, the functions that should be called from the - * system. Initialization, the periodic timer and incoming packets are - * handled by the following three functions. - */ - -/** - * \defgroup uipconffunc uIP configuration functions - * @{ - * - * The uIP configuration functions are used for setting run-time - * parameters in uIP such as IP addresses. - */ - -/** - * Set the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * \param addr A pointer to a 4-byte representation of the IP address. - * - * \hideinitializer - */ -#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \ - uip_hostaddr[1] = addr[1]; } while(0) - -/** - * Get the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the currently configured IP address. - * - * \hideinitializer - */ -#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \ - addr[1] = uip_hostaddr[1]; } while(0) - -/** @} */ - -/** - * \defgroup uipinit uIP initialization functions - * @{ - * - * The uIP initialization functions are used for booting uIP. - */ - -/** - * uIP initialization function. - * - * This function should be called at boot up to initilize the uIP - * TCP/IP stack. - */ -void uip_init(void); - -/** @} */ - -/** - * \defgroup uipdevfunc uIP device driver functions - * @{ - * - * These functions are used by a network device driver for interacting - * with uIP. - */ - -/** - * Process an incoming packet. - * - * This function should be called when the device driver has received - * a packet from the network. The packet from the device driver must - * be present in the uip_buf buffer, and the length of the packet - * should be placed in the uip_len variable. - * - * When the function returns, there may be an outbound packet placed - * in the uip_buf packet buffer. If so, the uip_len variable is set to - * the length of the packet. If no packet is to be sent out, the - * uip_len variable is set to 0. - * - * The usual way of calling the function is presented by the source - * code below. - \code - uip_len = devicedriver_poll(); - if(uip_len > 0) { - uip_input(); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uIP ARP code before calling - * this function: - \code - #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) - uip_len = ethernet_devicedrver_poll(); - if(uip_len > 0) { - if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { - uip_arp_ipin(); - uip_input(); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { - uip_arp_arpin(); - if(uip_len > 0) { - ethernet_devicedriver_send(); - } - } - \endcode - * - * \hideinitializer - */ -#define uip_input() uip_process(UIP_DATA) - -/** - * Periodic processing for a connection identified by its number. - * - * This function does the necessary periodic processing (timers, - * polling) for a uIP TCP conneciton, and should be called when the - * periodic uIP timer goes off. It should be called for every - * connection, regardless of whether they are open of closed. - * - * When the function returns, it may have an outbound packet waiting - * for service in the uIP packet buffer, and if so the uip_len - * variable is set to a value larger than zero. The device driver - * should be called to send out the packet. - * - * The ususal way of calling the function is through a for() loop like - * this: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uip_arp_out() function before - * calling the device driver: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the connection which is to be periodically polled. - * - * \hideinitializer - */ -#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ - uip_process(UIP_TIMER); } while (0) - -/** - * Periodic processing for a connection identified by a pointer to its structure. - * - * Same as uip_periodic() but takes a pointer to the actual uip_conn - * struct instead of an integer as its argument. This function can be - * used to force periodic processing of a specific connection. - * - * \param conn A pointer to the uip_conn struct for the connection to - * be processed. - * - * \hideinitializer - */ -#define uip_periodic_conn(conn) do { uip_conn = conn; \ - uip_process(UIP_TIMER); } while (0) - -#if UIP_UDP -/** - * Periodic processing for a UDP connection identified by its number. - * - * This function is essentially the same as uip_prerioic(), but for - * UDP connections. It is called in a similar fashion as the - * uip_periodic() function: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note As for the uip_periodic() function, special care has to be - * taken when using uIP together with ARP and Ethernet: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the UDP connection to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ - uip_process(UIP_UDP_TIMER); } while (0) - -/** - * Periodic processing for a UDP connection identified by a pointer to - * its structure. - * - * Same as uip_udp_periodic() but takes a pointer to the actual - * uip_conn struct instead of an integer as its argument. This - * function can be used to force periodic processing of a specific - * connection. - * - * \param conn A pointer to the uip_udp_conn struct for the connection - * to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ - uip_process(UIP_UDP_TIMER); } while (0) - - -#endif /* UIP_UDP */ - -/** - * The uIP packet buffer. - * - * The uip_buf array is used to hold incoming and outgoing - * packets. The device driver should place incoming data into this - * buffer. When sending data, the device driver should read the link - * level headers and the TCP/IP headers from this buffer. The size of - * the link level headers is configured by the UIP_LLH_LEN define. - * - * \note The application data need not be placed in this buffer, so - * the device driver must read it from the place pointed to by the - * uip_appdata pointer as illustrated by the following example: - \code - void - devicedriver_send(void) - { - hwsend(&uip_buf[0], UIP_LLH_LEN); - hwsend(&uip_buf[UIP_LLH_LEN], 40); - hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN); - } - \endcode - */ -extern u8_t uip_buf[UIP_BUFSIZE+2]; /*_RB_ __attribute__ ((aligned (4)));*/ - -/** @} */ - -/*-----------------------------------------------------------------------------------*/ -/* Functions that are used by the uIP application program. Opening and - * closing connections, sending and receiving data, etc. is all - * handled by the functions below. -*/ -/** - * \defgroup uipappfunc uIP application functions - * @{ - * - * Functions used by an application running of top of uIP. - */ - -/** - * Start listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_listen(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_listen(u16_t port); - -/** - * Stop listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_unlisten(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_unlisten(u16_t port); - -/** - * Connect to a remote host using TCP. - * - * This function is used to start a new connection to the specified - * port on the specied host. It allocates a new connection identifier, - * sets the connection to the SYN_SENT state and sets the - * retransmission timer to 0. This will cause a TCP SYN segment to be - * sent out the next time this connection is periodically processed, - * which usually is done within 0.5 seconds after the call to - * uip_connect(). - * - * \note This function is avaliable only if support for active open - * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. - * - * \note Since this function requires the port number to be in network - * byte order, a convertion using HTONS() or htons() is necessary. - * - \code - u16_t ipaddr[2]; - - uip_ipaddr(ipaddr, 192,168,1,2); - uip_connect(ipaddr, HTONS(80)); - \endcode - * - * \param ripaddr A pointer to a 4-byte array representing the IP - * address of the remote hot. - * - * \param port A 16-bit port number in network byte order. - * - * \return A pointer to the uIP connection identifier for the new connection, - * or NULL if no connection could be allocated. - * - */ -struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port); - - - -/** - * \internal - * - * Check if a connection has outstanding (i.e., unacknowledged) data. - * - * \param conn A pointer to the uip_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_outstanding(conn) ((conn)->len) - -/** - * Send data on the current connection. - * - * This function is used to send out a single segment of TCP - * data. Only applications that have been invoked by uIP for event - * processing can send data. - * - * The amount of data that actually is sent out after a call to this - * funcion is determined by the maximum amount of data TCP allows. uIP - * will automatically crop the data so that only the appropriate - * amount of data is sent. The function uip_mss() can be used to query - * uIP for the amount of data that actually will be sent. - * - * \note This function does not guarantee that the sent data will - * arrive at the destination. If the data is lost in the network, the - * application will be invoked with the uip_rexmit() event being - * set. The application will then have to resend the data using this - * function. - * - * \param data A pointer to the data which is to be sent. - * - * \param len The maximum amount of data bytes to be sent. - * - * \hideinitializer - */ -#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0) - -/** - * The length of any incoming data that is currently avaliable (if avaliable) - * in the uip_appdata buffer. - * - * The test function uip_data() must first be used to check if there - * is any data available at all. - * - * \hideinitializer - */ -#define uip_datalen() uip_len - -/** - * The length of any out-of-band data (urgent data) that has arrived - * on the connection. - * - * \note The configuration parameter UIP_URGDATA must be set for this - * function to be enabled. - * - * \hideinitializer - */ -#define uip_urgdatalen() uip_urglen - -/** - * Close the current connection. - * - * This function will close the current connection in a nice way. - * - * \hideinitializer - */ -#define uip_close() (uip_flags = UIP_CLOSE) - -/** - * Abort the current connection. - * - * This function will abort (reset) the current connection, and is - * usually used when an error has occured that prevents using the - * uip_close() function. - * - * \hideinitializer - */ -#define uip_abort() (uip_flags = UIP_ABORT) - -/** - * Tell the sending host to stop sending data. - * - * This function will close our receiver's window so that we stop - * receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) - -/** - * Find out if the current connection has been previously stopped with - * uip_stop(). - * - * \hideinitializer - */ -#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) - -/** - * Restart the current connection, if is has previously been stopped - * with uip_stop(). - * - * This function will open the receiver's window again so that we - * start receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ - uip_conn->tcpstateflags &= ~UIP_STOPPED; \ - } while(0) - - -/* uIP tests that can be made to determine in what state the current - connection is, and what the application function should do. */ - -/** - * Is new incoming data available? - * - * Will reduce to non-zero if there is new data for the application - * present at the uip_appdata pointer. The size of the data is - * avaliable through the uip_len variable. - * - * \hideinitializer - */ -#define uip_newdata() (uip_flags & UIP_NEWDATA) - -/** - * Has previously sent data been acknowledged? - * - * Will reduce to non-zero if the previously sent data has been - * acknowledged by the remote host. This means that the application - * can send new data. - * - * \hideinitializer - */ -#define uip_acked() (uip_flags & UIP_ACKDATA) - -/** - * Has the connection just been connected? - * - * Reduces to non-zero if the current connection has been connected to - * a remote host. This will happen both if the connection has been - * actively opened (with uip_connect()) or passively opened (with - * uip_listen()). - * - * \hideinitializer - */ -#define uip_connected() (uip_flags & UIP_CONNECTED) - -/** - * Has the connection been closed by the other end? - * - * Is non-zero if the connection has been closed by the remote - * host. The application may then do the necessary clean-ups. - * - * \hideinitializer - */ -#define uip_closed() (uip_flags & UIP_CLOSE) - -/** - * Has the connection been aborted by the other end? - * - * Non-zero if the current connection has been aborted (reset) by the - * remote host. - * - * \hideinitializer - */ -#define uip_aborted() (uip_flags & UIP_ABORT) - -/** - * Has the connection timed out? - * - * Non-zero if the current connection has been aborted due to too many - * retransmissions. - * - * \hideinitializer - */ -#define uip_timedout() (uip_flags & UIP_TIMEDOUT) - -/** - * Do we need to retransmit previously data? - * - * Reduces to non-zero if the previously sent data has been lost in - * the network, and the application should retransmit it. The - * application should send the exact same data as it did the last - * time, using the uip_send() function. - * - * \hideinitializer - */ -#define uip_rexmit() (uip_flags & UIP_REXMIT) - -/** - * Is the connection being polled by uIP? - * - * Is non-zero if the reason the application is invoked is that the - * current connection has been idle for a while and should be - * polled. - * - * The polling event can be used for sending data without having to - * wait for the remote host to send data. - * - * \hideinitializer - */ -#define uip_poll() (uip_flags & UIP_POLL) - -/** - * Get the initial maxium segment size (MSS) of the current - * connection. - * - * \hideinitializer - */ -#define uip_initialmss() (uip_conn->initialmss) - -/** - * Get the current maxium segment size that can be sent on the current - * connection. - * - * The current maxiumum segment size that can be sent on the - * connection is computed from the receiver's window and the MSS of - * the connection (which also is available by calling - * uip_initialmss()). - * - * \hideinitializer - */ -#define uip_mss() (uip_conn->mss) - -/** - * Set up a new UDP connection. - * - * \param ripaddr A pointer to a 4-byte structure representing the IP - * address of the remote host. - * - * \param rport The remote port number in network byte order. - * - * \return The uip_udp_conn structure for the new connection or NULL - * if no connection could be allocated. - */ -struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport); - -/** - * Removed a UDP connection. - * - * \param conn A pointer to the uip_udp_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_udp_remove(conn) (conn)->lport = 0 - -/** - * Send a UDP datagram of length len on the current connection. - * - * This function can only be called in response to a UDP event (poll - * or newdata). The data must be present in the uip_buf buffer, at the - * place pointed to by the uip_appdata pointer. - * - * \param len The length of the data in the uip_buf buffer. - * - * \hideinitializer - */ -#define uip_udp_send(len) uip_slen = (len) - -/** @} */ - -/* uIP convenience and converting functions. */ - -/** - * \defgroup uipconvfunc uIP conversion functions - * @{ - * - * These functions can be used for converting between different data - * formats used by uIP. - */ - -/** - * Pack an IP address into a 4-byte array which is used by uIP to - * represent IP addresses. - * - * Example: - \code - u16_t ipaddr[2]; - - uip_ipaddr(&ipaddr, 192,168,1,2); - \endcode - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the IP addres. - * \param addr0 The first octet of the IP address. - * \param addr1 The second octet of the IP address. - * \param addr2 The third octet of the IP address. - * \param addr3 The forth octet of the IP address. - * - * \hideinitializer - */ -#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ - (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \ - (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \ - } while(0) - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This macro is primarily used for converting constants from host - * byte order to network byte order. For converting variables to - * network byte order, use the htons() function instead. - * - * \hideinitializer - */ -#ifndef HTONS -# if BYTE_ORDER == BIG_ENDIAN -# define HTONS(n) (n) -# else /* BYTE_ORDER == BIG_ENDIAN */ -# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8)) -# endif /* BYTE_ORDER == BIG_ENDIAN */ -#endif /* HTONS */ - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This function is primarily used for converting variables from host - * byte order to network byte order. For converting constants to - * network byte order, use the HTONS() macro instead. - */ -#ifndef htons -u16_t htons(u16_t val); -#endif /* htons */ - -/** @} */ - -/** - * Pointer to the application data in the packet buffer. - * - * This pointer points to the application data when the application is - * called. If the application wishes to send data, the application may - * use this space to write the data into before calling uip_send(). - */ -extern volatile u8_t *uip_appdata; -extern volatile u8_t *uip_sappdata; - -#if UIP_URGDATA > 0 -/* u8_t *uip_urgdata: - * - * This pointer points to any urgent data that has been received. Only - * present if compiled with support for urgent data (UIP_URGDATA). - */ -extern volatile u8_t *uip_urgdata; -#endif /* UIP_URGDATA > 0 */ - - -/* u[8|16]_t uip_len: - * - * When the application is called, uip_len contains the length of any - * new data that has been received from the remote host. The - * application should set this variable to the size of any data that - * the application wishes to send. When the network device driver - * output function is called, uip_len should contain the length of the - * outgoing packet. - */ -extern volatile u16_t uip_len, uip_slen; - -#if UIP_URGDATA > 0 -extern volatile u8_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - - -/** - * Representation of a uIP TCP connection. - * - * The uip_conn structure is used for identifying a connection. All - * but one field in the structure are to be considered read-only by an - * application. The only exception is the appstate field whos purpose - * is to let the application store application-specific state (e.g., - * file pointers) for the connection. The size of this field is - * configured in the "uipopt.h" header file. - */ -struct uip_conn { - u16_t ripaddr[2]; /**< The IP address of the remote host. */ - - u16_t lport; /**< The local TCP port, in network byte order. */ - u16_t rport; /**< The local remote TCP port, in network byte - order. */ - - u8_t rcv_nxt[4]; /**< The sequence number that we expect to - receive next. */ - u8_t snd_nxt[4]; /**< The sequence number that was last sent by - us. */ - u16_t len; /**< Length of the data that was previously sent. */ - u16_t mss; /**< Current maximum segment size for the - connection. */ - u16_t initialmss; /**< Initial maximum segment size for the - connection. */ - u8_t sa; /**< Retransmission time-out calculation state - variable. */ - u8_t sv; /**< Retransmission time-out calculation state - variable. */ - u8_t rto; /**< Retransmission time-out. */ - u8_t tcpstateflags; /**< TCP state and flags. */ - u8_t timer; /**< The retransmission timer. */ - u8_t nrtx; /**< The number of retransmissions for the last - segment sent. */ - - /** The application state. */ - u8_t appstate[UIP_APPSTATE_SIZE]; -}; - - -/* Pointer to the current connection. */ -extern struct uip_conn *uip_conn; -/* The array containing all uIP connections. */ -extern struct uip_conn uip_conns[UIP_CONNS]; -/** - * \addtogroup uiparch - * @{ - */ - -/** - * 4-byte array used for the 32-bit sequence number calculations. - */ -extern volatile u8_t uip_acc32[4]; - -/** @} */ - - -#if UIP_UDP -/** - * Representation of a uIP UDP connection. - */ -struct uip_udp_conn { - u16_t ripaddr[2]; /**< The IP address of the remote peer. */ - u16_t lport; /**< The local port number in network byte order. */ - u16_t rport; /**< The remote port number in network byte order. */ -}; - -extern struct uip_udp_conn *uip_udp_conn; -extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - -/** - * The structure holding the TCP/IP statistics that are gathered if - * UIP_STATISTICS is set to 1. - * - */ -struct uip_stats { - struct { - uip_stats_t drop; /**< Number of dropped packets at the IP - layer. */ - uip_stats_t recv; /**< Number of received packets at the IP - layer. */ - uip_stats_t sent; /**< Number of sent packets at the IP - layer. */ - uip_stats_t vhlerr; /**< Number of packets dropped due to wrong - IP version or header length. */ - uip_stats_t hblenerr; /**< Number of packets dropped due to wrong - IP length, high byte. */ - uip_stats_t lblenerr; /**< Number of packets dropped due to wrong - IP length, low byte. */ - uip_stats_t fragerr; /**< Number of packets dropped since they - were IP fragments. */ - uip_stats_t chkerr; /**< Number of packets dropped due to IP - checksum errors. */ - uip_stats_t protoerr; /**< Number of packets dropped since they - were neither ICMP, UDP nor TCP. */ - } ip; /**< IP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped ICMP packets. */ - uip_stats_t recv; /**< Number of received ICMP packets. */ - uip_stats_t sent; /**< Number of sent ICMP packets. */ - uip_stats_t typeerr; /**< Number of ICMP packets with a wrong - type. */ - } icmp; /**< ICMP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped TCP segments. */ - uip_stats_t recv; /**< Number of recived TCP segments. */ - uip_stats_t sent; /**< Number of sent TCP segments. */ - uip_stats_t chkerr; /**< Number of TCP segments with a bad - checksum. */ - uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK - number. */ - uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ - uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ - uip_stats_t syndrop; /**< Number of dropped SYNs due to too few - connections was avaliable. */ - uip_stats_t synrst; /**< Number of SYNs for closed ports, - triggering a RST. */ - } tcp; /**< TCP statistics. */ -}; - -/** - * The uIP TCP/IP statistics. - * - * This is the variable in which the uIP TCP/IP statistics are gathered. - */ -extern struct uip_stats uip_stat; - - -/*-----------------------------------------------------------------------------------*/ -/* All the stuff below this point is internal to uIP and should not be - * used directly by an application or by a device driver. - */ -/*-----------------------------------------------------------------------------------*/ -/* u8_t uip_flags: - * - * When the application is called, uip_flags will contain the flags - * that are defined in this file. Please read below for more - * infomation. - */ -extern volatile u8_t uip_flags; - -/* The following flags may be set in the global variable uip_flags - before calling the application callback. The UIP_ACKDATA and - UIP_NEWDATA flags may both be set at the same time, whereas the - others are mutualy exclusive. Note that these flags should *NOT* be - accessed directly, but through the uIP functions/macros. */ - -#define UIP_ACKDATA 1 /* Signifies that the outstanding data was - acked and the application should send - out new data instead of retransmitting - the last data. */ -#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent - us new data. */ -#define UIP_REXMIT 4 /* Tells the application to retransmit the - data that was last sent. */ -#define UIP_POLL 8 /* Used for polling the application, to - check if the application has data that - it wants to send. */ -#define UIP_CLOSE 16 /* The remote host has closed the - connection, thus the connection has - gone away. Or the application signals - that it wants to close the - connection. */ -#define UIP_ABORT 32 /* The remote host has aborted the - connection, thus the connection has - gone away. Or the application signals - that it wants to abort the - connection. */ -#define UIP_CONNECTED 64 /* We have got a connection from a remote - host and have set up a new connection - for it, or an active connection has - been successfully established. */ - -#define UIP_TIMEDOUT 128 /* The connection has been aborted due to - too many retransmissions. */ - - -/* uip_process(flag): - * - * The actual uIP function which does all the work. - */ -void uip_process(u8_t flag); - -/* The following flags are passed as an argument to the uip_process() - function. They are used to distinguish between the two cases where - uip_process() is called. It can be called either because we have - incoming data that should be processed, or because the periodic - timer has fired. */ - -#define UIP_DATA 1 /* Tells uIP that there is incoming data in - the uip_buf buffer. The length of the - data is stored in the global variable - uip_len. */ -#define UIP_TIMER 2 /* Tells uIP that the periodic timer has - fired. */ -#if UIP_UDP -#define UIP_UDP_TIMER 3 -#endif /* UIP_UDP */ - -/* The TCP states used in the uip_conn->tcpstateflags. */ -#define CLOSED 0 -#define SYN_RCVD 1 -#define SYN_SENT 2 -#define ESTABLISHED 3 -#define FIN_WAIT_1 4 -#define FIN_WAIT_2 5 -#define CLOSING 6 -#define TIME_WAIT 7 -#define LAST_ACK 8 -#define TS_MASK 15 - -#define UIP_STOPPED 16 - -#define UIP_TCPIP_HLEN 40 - -/* The TCP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - - /* TCP header. */ - u16_t srcport, - destport; - u8_t seqno[4], - ackno[4], - tcpoffset, - flags, - wnd[2]; - u16_t tcpchksum; - u8_t urgp[2]; - u8_t optdata[4]; -} uip_tcpip_hdr; - -/* The ICMP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - /* ICMP (echo) header. */ - u8_t type, icode; - u16_t icmpchksum; - u16_t id, seqno; -} uip_icmpip_hdr; - - -/* The UDP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - - /* UDP header. */ - u16_t srcport, - destport; - u16_t udplen; - u16_t udpchksum; -} uip_udpip_hdr; - -#define UIP_PROTO_ICMP 1 -#define UIP_PROTO_TCP 6 -#define UIP_PROTO_UDP 17 - -#if UIP_FIXEDADDR -extern const u16_t uip_hostaddr[2]; -#else /* UIP_FIXEDADDR */ -extern u16_t uip_hostaddr[2]; -#endif /* UIP_FIXEDADDR */ - -#endif /* __UIP_H__ */ - - -/** @} */ - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c deleted file mode 100644 index 9dad18cc5..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $ - * - */ - - -#include "uip.h" -#include "uip_arch.h" - -#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define IP_PROTO_TCP 6 - -/*-----------------------------------------------------------------------------------*/ -void -uip_add32(u8_t *op32, u16_t op16) -{ - - uip_acc32[3] = op32[3] + (op16 & 0xff); - uip_acc32[2] = op32[2] + (op16 >> 8); - uip_acc32[1] = op32[1]; - uip_acc32[0] = op32[0]; - - if(uip_acc32[2] < (op16 >> 8)) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - - - if(uip_acc32[3] < (op16 & 0xff)) { - ++uip_acc32[2]; - if(uip_acc32[2] == 0) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - } -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_chksum(u16_t *sdata, u16_t len) -{ - u16_t acc; - - for (acc = 0; len > 1; len -= 2) { - u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8); - if ((acc += u) < u) { - /* Overflow, so we add the carry to acc (i.e., increase by - one). */ - ++acc; - } - ++sdata; - } - - /* add up any odd byte */ - if(len == 1) { - acc += htons(((u16_t)(*(u8_t *)sdata)) << 8); - if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) { - ++acc; - } - } - - return acc; -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_ipchksum(void) -{ - return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20); -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_tcpchksum(void) -{ - u16_t hsum, sum; - - - /* Compute the checksum of the TCP header. */ - hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20); - - /* Compute the checksum of the data in the TCP packet and add it to - the TCP header checksum. */ - sum = uip_chksum((u16_t *)uip_appdata, - (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40))); - - if((sum += hsum) < hsum) { - ++sum; - } - - if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) { - ++sum; - } - if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) { - ++sum; - } - if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) { - ++sum; - } - if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) { - ++sum; - } - if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) { - ++sum; - } - - hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20); - - if((sum += hsum) < hsum) { - ++sum; - } - - return sum; -} -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h deleted file mode 100644 index b2d133f2e..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * \defgroup uiparch Architecture specific uIP functions - * @{ - * - * The functions in the architecture specific module implement the IP - * check sum and 32-bit additions. - * - * The IP checksum calculation is the most computationally expensive - * operation in the TCP/IP stack and it therefore pays off to - * implement this in efficient assembler. The purpose of the uip-arch - * module is to let the checksum functions to be implemented in - * architecture specific assembler. - * - */ - -/** - * \file - * Declarations of architecture specific functions. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $ - * - */ - -#ifndef __UIP_ARCH_H__ -#define __UIP_ARCH_H__ - -#include "uip.h" - -/** - * Carry out a 32-bit addition. - * - * Because not all architectures for which uIP is intended has native - * 32-bit arithmetic, uIP uses an external C function for doing the - * required 32-bit additions in the TCP protocol processing. This - * function should add the two arguments and place the result in the - * global variable uip_acc32. - * - * \note The 32-bit integer pointed to by the op32 parameter and the - * result in the uip_acc32 variable are in network byte order (big - * endian). - * - * \param op32 A pointer to a 4-byte array representing a 32-bit - * integer in network byte order (big endian). - * - * \param op16 A 16-bit integer in host byte order. - */ -void uip_add32(u8_t *op32, u16_t op16); - -/** - * Calculate the Internet checksum over a buffer. - * - * The Internet checksum is the one's complement of the one's - * complement sum of all 16-bit words in the buffer. - * - * See RFC1071. - * - * \note This function is not called in the current version of uIP, - * but future versions might make use of it. - * - * \param buf A pointer to the buffer over which the checksum is to be - * computed. - * - * \param len The length of the buffer over which the checksum is to - * be computed. - * - * \return The Internet checksum of the buffer. - */ -u16_t uip_chksum(u16_t *buf, u16_t len); - -/** - * Calculate the IP header checksum of the packet header in uip_buf. - * - * The IP header checksum is the Internet checksum of the 20 bytes of - * the IP header. - * - * \return The IP header checksum of the IP header in the uip_buf - * buffer. - */ -u16_t uip_ipchksum(void); - -/** - * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. - * - * The TCP checksum is the Internet checksum of data contents of the - * TCP segment, and a pseudo-header as defined in RFC793. - * - * \note The uip_appdata pointer that points to the packet data may - * point anywhere in memory, so it is not possible to simply calculate - * the Internet checksum of the contents of the uip_buf buffer. - * - * \return The TCP checksum of the TCP segment in uip_buf and pointed - * to by uip_appdata. - */ -u16_t uip_tcpchksum(void); - -/** @} */ - -#endif /* __UIP_ARCH_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c deleted file mode 100644 index db8d72d8c..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c +++ /dev/null @@ -1,429 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup uiparp uIP Address Resolution Protocol - * @{ - * - * The Address Resolution Protocol ARP is used for mapping between IP - * addresses and link level addresses such as the Ethernet MAC - * addresses. ARP uses broadcast queries to ask for the link level - * address of a known IP address and the host which is configured with - * the IP address for which the query was meant, will respond with its - * link level address. - * - * \note This ARP implementation only supports Ethernet. - */ - -/** - * \file - * Implementation of the ARP Address Resolution Protocol. - * \author Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $ - * - */ - - -#include "uip_arp.h" - -#include - -struct arp_hdr { - struct uip_eth_hdr ethhdr; - u16_t hwtype; - u16_t protocol; - u8_t hwlen; - u8_t protolen; - u16_t opcode; - struct uip_eth_addr shwaddr; - u16_t sipaddr[2]; - struct uip_eth_addr dhwaddr; - u16_t dipaddr[2]; -}; - -struct ethip_hdr { - struct uip_eth_hdr ethhdr; - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; -}; - -#define ARP_REQUEST 1 -#define ARP_REPLY 2 - -#define ARP_HWTYPE_ETH 1 - -struct arp_entry { - u16_t ipaddr[2]; - struct uip_eth_addr ethaddr; - u8_t time; -}; - -struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, - UIP_ETHADDR1, - UIP_ETHADDR2, - UIP_ETHADDR3, - UIP_ETHADDR4, - UIP_ETHADDR5}}; - -static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; -static u16_t ipaddr[2]; -static u8_t i, c; - -static u8_t arptime; -static u8_t tmpage; - -#define BUF ((struct arp_hdr *)&uip_buf[0]) -#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the ARP module. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_init(void) -{ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - memset(arp_table[i].ipaddr, 0, 4); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Periodic ARP processing function. - * - * This function performs periodic timer processing in the ARP module - * and should be called at regular intervals. The recommended interval - * is 10 seconds between the calls. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_timer(void) -{ - struct arp_entry *tabptr; - - ++arptime; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && - arptime - tabptr->time >= UIP_ARP_MAXAGE) { - memset(tabptr->ipaddr, 0, 4); - } - } - -} -/*-----------------------------------------------------------------------------------*/ -static void -uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) -{ - register struct arp_entry *tabptr; - /* Walk through the ARP mapping table and try to find an entry to - update. If none is found, the IP -> MAC address mapping is - inserted in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - - tabptr = &arp_table[i]; - /* Only check those entries that are actually in use. */ - if(tabptr->ipaddr[0] != 0 && - tabptr->ipaddr[1] != 0) { - - /* Check if the source IP address of the incoming packet matches - the IP address in this ARP table entry. */ - if(ipaddr[0] == tabptr->ipaddr[0] && - ipaddr[1] == tabptr->ipaddr[1]) { - - /* An old entry found, update this and return. */ - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; - - return; - } - } - } - - /* If we get here, no existing ARP table entry was found, so we - create one. */ - - /* First, we try to find an unused entry in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(tabptr->ipaddr[0] == 0 && - tabptr->ipaddr[1] == 0) { - break; - } - } - - /* If no unused entry is found, we try to find the oldest entry and - throw it away. */ - if(i == UIP_ARPTAB_SIZE) { - tmpage = 0; - c = 0; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(arptime - tabptr->time > tmpage) { - tmpage = arptime - tabptr->time; - c = i; - } - } - i = c; - } - - /* Now, i is the ARP table entry which we will fill with the new - information. */ - memcpy(tabptr->ipaddr, ipaddr, 4); - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; -} -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming IP packets - * - * This function should be called by the device driver when an IP - * packet has been received. The function will check if the address is - * in the ARP cache, and if so the ARP cache entry will be - * refreshed. If no ARP cache entry was found, a new one is created. - * - * This function expects an IP packet with a prepended Ethernet header - * in the uip_buf[] buffer, and the length of the packet in the global - * variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_ipin(void) -{ - uip_len -= sizeof(struct uip_eth_hdr); - - /* Only insert/update an entry if the source IP address of the - incoming IP packet comes from a host on the local network. */ - if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) != - (uip_hostaddr[0] & uip_arp_netmask[0])) { - return; - } - if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) != - (uip_hostaddr[1] & uip_arp_netmask[1])) { - return; - } - uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); - - return; -} -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming ARP packets. - * - * This function should be called by the device driver when an ARP - * packet has been received. The function will act differently - * depending on the ARP packet type: if it is a reply for a request - * that we previously sent out, the ARP cache will be filled in with - * the values from the ARP reply. If the incoming ARP packet is an ARP - * request for our IP address, an ARP reply packet is created and put - * into the uip_buf[] buffer. - * - * When the function returns, the value of the global variable uip_len - * indicates whether the device driver should send out a packet or - * not. If uip_len is zero, no packet should be sent. If uip_len is - * non-zero, it contains the length of the outbound packet that is - * present in the uip_buf[] buffer. - * - * This function expects an ARP packet with a prepended Ethernet - * header in the uip_buf[] buffer, and the length of the packet in the - * global variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -typedef struct arp_hdr aht; - -void -uip_arp_arpin(void) -{ - int ul; - - if(uip_len < sizeof(struct arp_hdr)) { - uip_len = 0; - return; - } - - uip_len = 0; - - switch(BUF->opcode) { - case HTONS(ARP_REQUEST): - /* ARP request. If it asked for our address, we send out a - reply. */ - if(BUF->dipaddr[0] == uip_hostaddr[0] && - BUF->dipaddr[1] == uip_hostaddr[1]) { - /* The reply opcode is 2. */ - BUF->opcode = HTONS(2); - - memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); - - BUF->dipaddr[0] = BUF->sipaddr[0]; - BUF->dipaddr[1] = BUF->sipaddr[1]; - BUF->sipaddr[0] = uip_hostaddr[0]; - BUF->sipaddr[1] = uip_hostaddr[1]; - - ul = BUF->hwlen; - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - uip_len = sizeof(struct arp_hdr); - } - break; - case HTONS(ARP_REPLY): - /* ARP reply. We insert or update the ARP table if it was meant - for us. */ - if(BUF->dipaddr[0] == uip_hostaddr[0] && - BUF->dipaddr[1] == uip_hostaddr[1]) { - - uip_arp_update(BUF->sipaddr, &BUF->shwaddr); - } - break; - } - - ( void ) ul; - - return; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Prepend Ethernet header to an outbound IP packet and see if we need - * to send out an ARP request. - * - * This function should be called before sending out an IP packet. The - * function checks the destination IP address of the IP packet to see - * what Ethernet MAC address that should be used as a destination MAC - * address on the Ethernet. - * - * If the destination IP address is in the local network (determined - * by logical ANDing of netmask and our IP address), the function - * checks the ARP cache to see if an entry for the destination IP - * address is found. If so, an Ethernet header is prepended and the - * function returns. If no ARP cache entry is found for the - * destination IP address, the packet in the uip_buf[] is replaced by - * an ARP request packet for the IP address. The IP packet is dropped - * and it is assumed that they higher level protocols (e.g., TCP) - * eventually will retransmit the dropped packet. - * - * If the destination IP address is not on the local network, the IP - * address of the default router is used instead. - * - * When the function returns, a packet is present in the uip_buf[] - * buffer, and the length of the packet is in the global variable - * uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_out(void) -{ - struct arp_entry *tabptr; - /* Find the destination IP address in the ARP table and construct - the Ethernet header. If the destination IP addres isn't on the - local network, we use the default router's IP address instead. - - If not ARP table entry is found, we overwrite the original IP - packet with an ARP request for the IP address. */ - - /* Check if the destination address is on the local network. */ - if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) != - (uip_hostaddr[0] & uip_arp_netmask[0]) || - (IPBUF->destipaddr[1] & uip_arp_netmask[1]) != - (uip_hostaddr[1] & uip_arp_netmask[1])) { - /* Destination address was not on the local network, so we need to - use the default router's IP address instead of the destination - address when determining the MAC address. */ - ipaddr[0] = uip_arp_draddr[0]; - ipaddr[1] = uip_arp_draddr[1]; - } else { - /* Else, we use the destination IP address. */ - ipaddr[0] = IPBUF->destipaddr[0]; - ipaddr[1] = IPBUF->destipaddr[1]; - } - - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(ipaddr[0] == tabptr->ipaddr[0] && - ipaddr[1] == tabptr->ipaddr[1]) - break; - } - - if(i == UIP_ARPTAB_SIZE) { - /* The destination address was not in our ARP table, so we - overwrite the IP packet with an ARP request. */ - - memset(BUF->ethhdr.dest.addr, 0xff, 6); - memset(BUF->dhwaddr.addr, 0x00, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - - BUF->dipaddr[0] = ipaddr[0]; - BUF->dipaddr[1] = ipaddr[1]; - BUF->sipaddr[0] = uip_hostaddr[0]; - BUF->sipaddr[1] = uip_hostaddr[1]; - BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ - BUF->hwtype = HTONS(ARP_HWTYPE_ETH); - BUF->protocol = HTONS(UIP_ETHTYPE_IP); - BUF->hwlen = 6; - BUF->protolen = 4; - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - - uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; - - uip_len = sizeof(struct arp_hdr); - return; - } - - /* Build an ethernet header. */ - memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); - memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - - IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); - - uip_len += sizeof(struct uip_eth_hdr); -} -/*-----------------------------------------------------------------------------------*/ - -/** @} */ -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h deleted file mode 100644 index fadad57bb..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \addtogroup uiparp - * @{ - */ - -/** - * \file - * Macros and definitions for the ARP module. - * \author Adam Dunkels - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $ - * - */ - -#ifndef __UIP_ARP_H__ -#define __UIP_ARP_H__ - -#include "uip.h" - - -/** - * Representation of a 48-bit Ethernet address. - */ -struct uip_eth_addr { - u8_t addr[6]; -} /*_RB_ __attribute__ ((packed, aligned (1))) */; - -extern struct uip_eth_addr uip_ethaddr; - -/** - * The Ethernet header. - */ -struct uip_eth_hdr { - struct uip_eth_addr dest; - struct uip_eth_addr src; - u16_t type; -} /*_RB_ __attribute__ ((packed)) */; - -#define UIP_ETHTYPE_ARP 0x0806 -#define UIP_ETHTYPE_IP 0x0800 -#define UIP_ETHTYPE_IP6 0x86dd - - -/* The uip_arp_init() function must be called before any of the other - ARP functions. */ -void uip_arp_init(void); - -/* The uip_arp_ipin() function should be called whenever an IP packet - arrives from the Ethernet. This function refreshes the ARP table or - inserts a new mapping if none exists. The function assumes that an - IP packet with an Ethernet header is present in the uip_buf buffer - and that the length of the packet is in the uip_len variable. */ -void uip_arp_ipin(void); - -/* The uip_arp_arpin() should be called when an ARP packet is received - by the Ethernet driver. This function also assumes that the - Ethernet frame is present in the uip_buf buffer. When the - uip_arp_arpin() function returns, the contents of the uip_buf - buffer should be sent out on the Ethernet if the uip_len variable - is > 0. */ -void uip_arp_arpin(void); - -/* The uip_arp_out() function should be called when an IP packet - should be sent out on the Ethernet. This function creates an - Ethernet header before the IP header in the uip_buf buffer. The - Ethernet header will have the correct Ethernet MAC destination - address filled in if an ARP table entry for the destination IP - address (or the IP address of the default router) is present. If no - such table entry is found, the IP packet is overwritten with an ARP - request and we rely on TCP to retransmit the packet that was - overwritten. In any case, the uip_len variable holds the length of - the Ethernet frame that should be transmitted. */ -void uip_arp_out(void); - -/* The uip_arp_timer() function should be called every ten seconds. It - is responsible for flushing old entries in the ARP table. */ -void uip_arp_timer(void); - -/** @} */ - -/** - * \addtogroup uipconffunc - * @{ - */ - -/** - * Set the default router's IP address. - * - * \param addr A pointer to a 4-byte array containing the IP address - * of the default router. - * - * \hideinitializer - */ -#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \ - uip_arp_draddr[1] = addr[1]; } while(0) - -/** - * Set the netmask. - * - * \param addr A pointer to a 4-byte array containing the IP address - * of the netmask. - * - * \hideinitializer - */ -#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \ - uip_arp_netmask[1] = addr[1]; } while(0) - - -/** - * Get the default router's IP address. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the IP address of the default router. - * - * \hideinitializer - */ -#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \ - addr[1] = uip_arp_draddr[1]; } while(0) - -/** - * Get the netmask. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the value of the netmask. - * - * \hideinitializer - */ -#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \ - addr[1] = uip_arp_netmask[1]; } while(0) - - -/** - * Specifiy the Ethernet MAC address. - * - * The ARP code needs to know the MAC address of the Ethernet card in - * order to be able to respond to ARP queries and to generate working - * Ethernet headers. - * - * \note This macro only specifies the Ethernet MAC address to the ARP - * code. It cannot be used to change the MAC address of the Ethernet - * card. - * - * \param eaddr A pointer to a struct uip_eth_addr containing the - * Ethernet MAC address of the Ethernet card. - * - * \hideinitializer - */ -#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ - uip_ethaddr.addr[1] = eaddr.addr[1];\ - uip_ethaddr.addr[2] = eaddr.addr[2];\ - uip_ethaddr.addr[3] = eaddr.addr[3];\ - uip_ethaddr.addr[4] = eaddr.addr[4];\ - uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) - -/** @} */ - -/** - * \internal Internal variables that are set using the macros - * uip_setdraddr and uip_setnetmask. - */ -extern u16_t uip_arp_draddr[2], uip_arp_netmask[2]; -#endif /* __UIP_ARP_H__ */ - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h deleted file mode 100644 index 18a578bd2..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h +++ /dev/null @@ -1,560 +0,0 @@ -/** - * \defgroup uipopt Configuration options for uIP - * @{ - * - * uIP is configured using the per-project configuration file - * "uipopt.h". This file contains all compile-time options for uIP and - * should be tweaked to match each specific project. The uIP - * distribution contains a documented example "uipopt.h" that can be - * copied and modified for each project. - */ - -/** - * \file - * Configuration options for uIP. - * \author Adam Dunkels - * - * This file is used for tweaking various configuration options for - * uIP. You should make a copy of this file into one of your project's - * directories instead of editing this example "uipopt.h" file that - * comes with the uIP distribution. - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $ - * - */ - -#ifndef __UIPOPT_H__ -#define __UIPOPT_H__ - -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipopttypedef uIP type definitions - * @{ - */ - -/** - * The 8-bit unsigned data type. - * - * This may have to be tweaked for your particular compiler. "unsigned - * char" works for most compilers. - */ -typedef unsigned char u8_t; - -/** - * The 16-bit unsigned data type. - * - * This may have to be tweaked for your particular compiler. "unsigned - * short" works for most compilers. - */ -typedef unsigned short u16_t; - -/** - * The statistics data type. - * - * This datatype determines how high the statistics counters are able - * to count. - */ -typedef unsigned short uip_stats_t; - -/** @} */ - -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptstaticconf Static configuration options - * @{ - * - * These configuration options can be used for setting the IP address - * settings statically, but only if UIP_FIXEDADDR is set to 1. The - * configuration options for a specific node includes IP address, - * netmask and default router as well as the Ethernet address. The - * netmask, default router and Ethernet address are appliciable only - * if uIP should be run over Ethernet. - * - * All of these should be changed to suit your project. -*/ - -/** - * Determines if uIP should use a fixed IP address or not. - * - * If uIP should use a fixed IP address, the settings are set in the - * uipopt.h file. If not, the macros uip_sethostaddr(), - * uip_setdraddr() and uip_setnetmask() should be used instead. - * - * \hideinitializer - */ -#define UIP_FIXEDADDR 1 - -/** - * Ping IP address asignment. - * - * uIP uses a "ping" packets for setting its own IP address if this - * option is set. If so, uIP will start with an empty IP address and - * the destination IP address of the first incoming "ping" (ICMP echo) - * packet will be used for setting the hosts IP address. - * - * \note This works only if UIP_FIXEDADDR is 0. - * - * \hideinitializer - */ -#define UIP_PINGADDRCONF 0 - - -#define UIP_IPADDR0 172U /**< The first octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR1 25U /**< The second octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR2 218U /**< The third octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR3 11U /**< The fourth octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_NETMASK0 255 /**< The first octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK1 255 /**< The second octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK2 0 /**< The third octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_DRIPADDR0 172 /**< The first octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR1 25 /**< The second octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR2 218 /**< The third octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR3 3 /**< The fourth octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ - - - -/** - * Specifies if the uIP ARP module should be compiled with a fixed - * Ethernet MAC address or not. - * - * If this configuration option is 0, the macro uip_setethaddr() can - * be used to specify the Ethernet address at run-time. - * - * \hideinitializer - */ -#define UIP_FIXEDETHADDR 0 - -#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR4 0x06 /**< The fifth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR5 0x65 /**< The sixth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptip IP configuration options - * @{ - * - */ -/** - * The IP TTL (time to live) of IP packets sent by uIP. - * - * This should normally not be changed. - */ -#define UIP_TTL 255 - -/** - * Turn on support for IP packet reassembly. - * - * uIP supports reassembly of fragmented IP packets. This features - * requires an additonal amount of RAM to hold the reassembly buffer - * and the reassembly code size is approximately 700 bytes. The - * reassembly buffer is of the same size as the uip_buf buffer - * (configured by UIP_BUFSIZE). - * - * \note IP packet reassembly is not heavily tested. - * - * \hideinitializer - */ -#define UIP_REASSEMBLY 0 - -/** - * The maximum time an IP fragment should wait in the reassembly - * buffer before it is dropped. - * - */ -#define UIP_REASS_MAXAGE 40 - -/** @} */ - -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptudp UDP configuration options - * @{ - * - * \note The UDP support in uIP is still not entirely complete; there - * is no support for sending or receiving broadcast or multicast - * packets, but it works well enough to support a number of vital - * applications such as DNS queries, though - */ - -/** - * Toggles wether UDP support should be compiled in or not. - * - * \hideinitializer - */ -#define UIP_UDP 0 - -/** - * Toggles if UDP checksums should be used or not. - * - * \note Support for UDP checksums is currently not included in uIP, - * so this option has no function. - * - * \hideinitializer - */ -#define UIP_UDP_CHECKSUMS 0 - -/** - * The maximum amount of concurrent UDP connections. - * - * \hideinitializer - */ -#define UIP_UDP_CONNS 2 - -/** - * The name of the function that should be called when UDP datagrams arrive. - * - * \hideinitializer - */ -#define UIP_UDP_APPCALL udp_appcall - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipopttcp TCP configuration options - * @{ - */ - -/** - * Determines if support for opening connections from uIP should be - * compiled in. - * - * If the applications that are running on top of uIP for this project - * do not need to open outgoing TCP connections, this configration - * option can be turned off to reduce the code size of uIP. - * - * \hideinitializer - */ -#define UIP_ACTIVE_OPEN 0 - -/** - * The maximum number of simultaneously open TCP connections. - * - * Since the TCP connections are statically allocated, turning this - * configuration knob down results in less RAM used. Each TCP - * connection requires approximatly 30 bytes of memory. - * - * \hideinitializer - */ -#define UIP_CONNS 25 - -/** - * The maximum number of simultaneously listening TCP ports. - * - * Each listening TCP port requires 2 bytes of memory. - * - * \hideinitializer - */ -#define UIP_LISTENPORTS 10 - -/** - * The size of the advertised receiver's window. - * - * Should be set low (i.e., to the size of the uip_buf buffer) is the - * application is slow to process incoming data, or high (32768 bytes) - * if the application processes data quickly. - * - * \hideinitializer - */ -#define UIP_RECEIVE_WINDOW 32768 - -/** - * Determines if support for TCP urgent data notification should be - * compiled in. - * - * Urgent data (out-of-band data) is a rarely used TCP feature that - * very seldom would be required. - * - * \hideinitializer - */ -#define UIP_URGDATA 1 - -/** - * The initial retransmission timeout counted in timer pulses. - * - * This should not be changed. - */ -#define UIP_RTO 3 - -/** - * The maximum number of times a segment should be retransmitted - * before the connection should be aborted. - * - * This should not be changed. - */ -#define UIP_MAXRTX 8 - -/** - * The maximum number of times a SYN segment should be retransmitted - * before a connection request should be deemed to have been - * unsuccessful. - * - * This should not need to be changed. - */ -#define UIP_MAXSYNRTX 3 - -/** - * The TCP maximum segment size. - * - * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40. - */ -#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40) - -/** - * How long a connection should stay in the TIME_WAIT state. - * - * This configiration option has no real implication, and it should be - * left untouched. - */ -#define UIP_TIME_WAIT_TIMEOUT 120 - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptarp ARP configuration options - * @{ - */ - -/** - * The size of the ARP table. - * - * This option should be set to a larger value if this uIP node will - * have many connections from the local network. - * - * \hideinitializer - */ -#define UIP_ARPTAB_SIZE 8 - -/** - * The maxium age of ARP table entries measured in 10ths of seconds. - * - * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD - * default). - */ -#define UIP_ARP_MAXAGE 120 - -/** @} */ - -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptgeneral General configuration options - * @{ - */ - -/** - * The size of the uIP packet buffer. - * - * The uIP packet buffer should not be smaller than 60 bytes, and does - * not need to be larger than 1500 bytes. Lower size results in lower - * TCP throughput, larger size results in higher TCP throughput. - * - * \hideinitializer - */ -#define UIP_BUFSIZE 1480 - - -/** - * Determines if statistics support should be compiled in. - * - * The statistics is useful for debugging and to show the user. - * - * \hideinitializer - */ -#define UIP_STATISTICS 1 - -/** - * Determines if logging of certain events should be compiled in. - * - * This is useful mostly for debugging. The function uip_log() - * must be implemented to suit the architecture of the project, if - * logging is turned on. - * - * \hideinitializer - */ -#define UIP_LOGGING 0 - -/** - * Print out a uIP log message. - * - * This function must be implemented by the module that uses uIP, and - * is called by uIP whenever a log message is generated. - */ -void uip_log(char *msg); - -/** - * The link level header length. - * - * This is the offset into the uip_buf where the IP header can be - * found. For Ethernet, this should be set to 14. For SLIP, this - * should be set to 0. - * - * \hideinitializer - */ -#define UIP_LLH_LEN 14 - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptcpu CPU architecture configuration - * @{ - * - * The CPU architecture configuration is where the endianess of the - * CPU on which uIP is to be run is specified. Most CPUs today are - * little endian, and the most notable exception are the Motorolas - * which are big endian. The BYTE_ORDER macro should be changed to - * reflect the CPU architecture on which uIP is to be run. - */ -#ifndef LITTLE_ENDIAN -#define LITTLE_ENDIAN 3412 -#endif /* LITTLE_ENDIAN */ -#ifndef BIG_ENDIAN -#define BIG_ENDIAN 1234 -#endif /* BIGE_ENDIAN */ - -/** - * The byte order of the CPU architecture on which uIP is to be run. - * - * This option can be either BIG_ENDIAN (Motorola byte order) or - * LITTLE_ENDIAN (Intel byte order). - * - * \hideinitializer - */ -#ifndef BYTE_ORDER -#define BYTE_ORDER LITTLE_ENDIAN -#endif /* BYTE_ORDER */ - -/** @} */ -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptapp Appication specific configurations - * @{ - * - * An uIP application is implemented using a single application - * function that is called by uIP whenever a TCP/IP event occurs. The - * name of this function must be registered with uIP at compile time - * using the UIP_APPCALL definition. - * - * uIP applications can store the application state within the - * uip_conn structure by specifying the size of the application - * structure with the UIP_APPSTATE_SIZE macro. - * - * The file containing the definitions must be included in the - * uipopt.h file. - * - * The following example illustrates how this can look. - \code - -void httpd_appcall(void); -#define UIP_APPCALL httpd_appcall - -struct httpd_state { - u8_t state; - u16_t count; - char *dataptr; - char *script; -}; -#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) - \endcode - */ - -/** - * \var #define UIP_APPCALL - * - * The name of the application function that uIP should call in - * response to TCP/IP events. - * - */ - -/** - * \var #define UIP_APPSTATE_SIZE - * - * The size of the application state that is to be stored in the - * uip_conn structure. - */ -/** @} */ - -/* Include the header file for the application program that should be - used. If you don't use the example web server, you should change - this. */ -#include "httpd.h" - - -#endif /* __UIPOPT_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h deleted file mode 100644 index 13c0232cc..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include -#define vPortYieldProcessor swi_handler - - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned long ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ -#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s deleted file mode 100644 index 47debb720..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s +++ /dev/null @@ -1,213 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2001, 2002 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - *****************************************************************************/ - -/***************************************************************************** - * Preprocessor Definitions - * ------------------------ - * - * VECTORED_IRQ_INTERRUPTS - * - * Enable vectored IRQ interrupts. If defined, the PC register will be loaded - * with the contents of the VICVectAddr register on an IRQ exception. - * - * USE_PLL - * - * If defined, connect PLL as processor clock source. If undefined, the - * oscillator clock will be used. - * - * PLLCFG_VAL - * - * Override the default PLL configuration (multiplier = 5, divider = 2) - * by defining PLLCFG_VAL. - * - * USE_MAM - * - * If defined then the memory accelerator module (MAM) will be enabled. - * - * MAMCR_VAL & MAMTIM_VAL - * - * Override the default MAM configuration (fully enabled, 3 fetch cycles) - * by defining MAMCR_VAL and MAMTIM_VAL. - * - * VPBDIV_VAL - * - * If defined then this value will be used to configure the VPB divider. - * - * SRAM_EXCEPTIONS - * - * If defined, enable copying and re-mapping of interrupt vectors from User - * FLASH to SRAM. If undefined, interrupt vectors will be mapped in User - * FLASH. - * - *****************************************************************************/ - -#ifndef PLLCFG_VAL -#define PLLCFG_VAL 0x24 -#endif - -#ifndef MAMCR_VAL -#define MAMCR_VAL 2 -#endif - -#ifndef MAMTIM_VAL -#define MAMTIM_VAL 3 -#endif - -#define MAMCR_OFFS 0x000 -#define MAMTIM_OFFS 0x004 - -#define PLLCON_OFFS 0x080 -#define PLLCFG_OFFS 0x084 -#define PLLSTAT_OFFS 0x088 -#define PLLFEED_OFFS 0x08C - -#define VPBDIV_OFFS 0x100 - - .section .vectors, "ax" - .code 32 - .align 0 - -/***************************************************************************** - * Exception Vectors * - *****************************************************************************/ -_vectors: - ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ - ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ - ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ - ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ - ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ -#ifdef VECTORED_IRQ_INTERRUPTS - .word 0xB9205F84 /* boot loader checksum */ - ldr pc, [pc, #-0xFF0] /* irq handler */ -#else - .word 0xB8A06F60 /* boot loader checksum */ - ldr pc, [pc, #irq_handler_address - . - 8] /* irq handler */ -#endif - ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq handler */ - -reset_handler_address: - .word reset_handler -undef_handler_address: - .word undef_handler -swi_handler_address: - .word swi_handler -pabort_handler_address: - .word pabort_handler -dabort_handler_address: - .word dabort_handler -irq_handler_address: - .word irq_handler -fiq_handler_address: - .word fiq_handler - - .section .init, "ax" - .code 32 - .align 0 - -/****************************************************************************** - * * - * Default exception handlers * - * * - ******************************************************************************/ - -reset_handler: -#if defined(USE_PLL) || defined(USE_MAM) || defined(VPBDIV_VAL) - ldr r0, =0xE01FC000 -#endif -#if defined(USE_PLL) - /* Configure PLL Multiplier/Divider */ - ldr r1, =PLLCFG_VAL - str r1, [r0, #PLLCFG_OFFS] - /* Enable PLL */ - mov r1, #0x1 - str r1, [r0, #PLLCON_OFFS] - mov r1, #0xAA - str r1, [r0, #PLLFEED_OFFS] - mov r1, #0x55 - str r1, [r0, #PLLFEED_OFFS] - /* Wait for PLL to lock */ -pll_lock_loop: - ldr r1, [r0, #PLLSTAT_OFFS] - tst r1, #0x400 - beq pll_lock_loop - /* PLL Locked, connect PLL as clock source */ - mov r1, #0x3 - str r1, [r0, #PLLCON_OFFS] - mov r1, #0xAA - str r1, [r0, #PLLFEED_OFFS] - mov r1, #0x55 - str r1, [r0, #PLLFEED_OFFS] -#endif - -#if defined(USE_MAM) - mov r1, #0 - str r1, [r0, #MAMCR_OFFS] - ldr r1, =MAMTIM_VAL - str r1, [r0, #MAMTIM_OFFS] - ldr r1, =MAMCR_VAL - str r1, [r0, #MAMCR_OFFS] -#endif - -#if defined(VPBDIV_VAL) - ldr r1, =VPBDIV_VAL - str r1, [r0, #VPBDIV_OFFS] -#endif - -#if defined(SRAM_EXCEPTIONS) - /* Copy exception vectors into SRAM */ - mov r8, #0x40000000 - ldr r9, =_vectors - ldmia r9!, {r0-r7} - stmia r8!, {r0-r7} - ldmia r9!, {r0-r6} - stmia r8!, {r0-r6} - - /* Re-map interrupt vectors from SRAM */ - ldr r0, MEMMAP - mov r1, #2 /* User RAM Mode. Interrupt vectors are re-mapped from SRAM */ - str r1, [r0] -#endif /* SRAM_EXCEPTIONS */ - - b _start - -#ifdef SRAM_EXCEPTIONS -MEMMAP: - .word 0xE01FC040 -#endif - -/****************************************************************************** - * * - * Default exception handlers * - * These are declared weak symbols so they can be redefined in user code. * - * * - ******************************************************************************/ - -undef_handler: - b undef_handler - -swi_handler: - b swi_handler - -pabort_handler: - b pabort_handler - -dabort_handler: - b dabort_handler - -irq_handler: - b irq_handler - -fiq_handler: - b fiq_handler - - .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler - - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/ReadMe.txt b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/ReadMe.txt new file mode 100644 index 000000000..add564283 --- /dev/null +++ b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/ReadMe.txt @@ -0,0 +1,5 @@ +If you need the demo that used to be in this directory then download FreeRTOS V8.2.3 +from http://sourceforge.net/projects/freertos/files/FreeRTOS/ + +FreeRTOS now uses its own TCP/IP stack: http://www.FreeRTOS.org/TCP + diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml deleted file mode 100644 index 449adf2e4..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml +++ /dev/null @@ -1,29 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h deleted file mode 100644 index 3f1e3042d..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h +++ /dev/null @@ -1,321 +0,0 @@ -#ifndef lpc210x_h -#define lpc210x_h -/******************************************************************************* -lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106 - - -THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, -EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY -WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY -PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS -OF OTHERS. - -This file may be freely used for commercial and non-commercial applications, -including being redistributed with any tools. - -If you find a problem with the file, please report it so that it can be fixed. - -Created by Sten Larsson (sten_larsson at yahoo com) - -Edited by Richard Barry. -*******************************************************************************/ - -#define REG8 (volatile unsigned char*) -#define REG16 (volatile unsigned short*) -#define REG32 (volatile unsigned int*) - - -/*############################################################################## -## MISC -##############################################################################*/ - - /* Constants for data to put in IRQ/FIQ Exception Vectors */ -#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */ -#define VECTDATA_FIQ /* __TODO */ - - -/*############################################################################## -## VECTORED INTERRUPT CONTROLLER -##############################################################################*/ - -#define VICIRQStatus (*(REG32 (0xFFFFF000))) -#define VICFIQStatus (*(REG32 (0xFFFFF004))) -#define VICRawIntr (*(REG32 (0xFFFFF008))) -#define VICIntSelect (*(REG32 (0xFFFFF00C))) -#define VICIntEnable (*(REG32 (0xFFFFF010))) -#define VICIntEnClear (*(REG32 (0xFFFFF014))) -#define VICSoftInt (*(REG32 (0xFFFFF018))) -#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) -#define VICProtection (*(REG32 (0xFFFFF020))) -#define VICVectAddr (*(REG32 (0xFFFFF030))) -#define VICDefVectAddr (*(REG32 (0xFFFFF034))) - -#define VICVectAddr0 (*(REG32 (0xFFFFF100))) -#define VICVectAddr1 (*(REG32 (0xFFFFF104))) -#define VICVectAddr2 (*(REG32 (0xFFFFF108))) -#define VICVectAddr3 (*(REG32 (0xFFFFF10C))) -#define VICVectAddr4 (*(REG32 (0xFFFFF110))) -#define VICVectAddr5 (*(REG32 (0xFFFFF114))) -#define VICVectAddr6 (*(REG32 (0xFFFFF118))) -#define VICVectAddr7 (*(REG32 (0xFFFFF11C))) -#define VICVectAddr8 (*(REG32 (0xFFFFF120))) -#define VICVectAddr9 (*(REG32 (0xFFFFF124))) -#define VICVectAddr10 (*(REG32 (0xFFFFF128))) -#define VICVectAddr11 (*(REG32 (0xFFFFF12C))) -#define VICVectAddr12 (*(REG32 (0xFFFFF130))) -#define VICVectAddr13 (*(REG32 (0xFFFFF134))) -#define VICVectAddr14 (*(REG32 (0xFFFFF138))) -#define VICVectAddr15 (*(REG32 (0xFFFFF13C))) - -#define VICVectCntl0 (*(REG32 (0xFFFFF200))) -#define VICVectCntl1 (*(REG32 (0xFFFFF204))) -#define VICVectCntl2 (*(REG32 (0xFFFFF208))) -#define VICVectCntl3 (*(REG32 (0xFFFFF20C))) -#define VICVectCntl4 (*(REG32 (0xFFFFF210))) -#define VICVectCntl5 (*(REG32 (0xFFFFF214))) -#define VICVectCntl6 (*(REG32 (0xFFFFF218))) -#define VICVectCntl7 (*(REG32 (0xFFFFF21C))) -#define VICVectCntl8 (*(REG32 (0xFFFFF220))) -#define VICVectCntl9 (*(REG32 (0xFFFFF224))) -#define VICVectCntl10 (*(REG32 (0xFFFFF228))) -#define VICVectCntl11 (*(REG32 (0xFFFFF22C))) -#define VICVectCntl12 (*(REG32 (0xFFFFF230))) -#define VICVectCntl13 (*(REG32 (0xFFFFF234))) -#define VICVectCntl14 (*(REG32 (0xFFFFF238))) -#define VICVectCntl15 (*(REG32 (0xFFFFF23C))) - -#define VICITCR (*(REG32 (0xFFFFF300))) -#define VICITIP1 (*(REG32 (0xFFFFF304))) -#define VICITIP2 (*(REG32 (0xFFFFF308))) -#define VICITOP1 (*(REG32 (0xFFFFF30C))) -#define VICITOP2 (*(REG32 (0xFFFFF310))) -#define VICPeriphID0 (*(REG32 (0xFFFFFFE0))) -#define VICPeriphID1 (*(REG32 (0xFFFFFFE4))) -#define VICPeriphID2 (*(REG32 (0xFFFFFFE8))) -#define VICPeriphID3 (*(REG32 (0xFFFFFFEC))) - -#define VICIntEnClr VICIntEnClear -#define VICSoftIntClr VICSoftIntClear - - -/*############################################################################## -## PCB - Pin Connect Block -##############################################################################*/ - -#define PCB_PINSEL0 (*(REG32 (0xE002C000))) -#define PCB_PINSEL1 (*(REG32 (0xE002C004))) - - -/*############################################################################## -## GPIO - General Purpose I/O -##############################################################################*/ - -#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ -#define GPIO_IOSET (*(REG32 (0xE0028004))) -#define GPIO_IODIR (*(REG32 (0xE0028008))) -#define GPIO_IOCLR (*(REG32 (0xE002800C))) - -#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ -#define GPIO0_IOSET (*(REG32 (0xE0028004))) -#define GPIO0_IODIR (*(REG32 (0xE0028008))) -#define GPIO0_IOCLR (*(REG32 (0xE002800C))) - - -/*############################################################################## -## UART0 / UART1 -##############################################################################*/ - -/* ---- UART 0 --------------------------------------------- */ -#define UART0_RBR (*(REG32 (0xE000C000))) -#define UART0_THR (*(REG32 (0xE000C000))) -#define UART0_IER (*(REG32 (0xE000C004))) -#define UART0_IIR (*(REG32 (0xE000C008))) -#define UART0_FCR (*(REG32 (0xE000C008))) -#define UART0_LCR (*(REG32 (0xE000C00C))) -#define UART0_LSR (*(REG32 (0xE000C014))) -#define UART0_SCR (*(REG32 (0xE000C01C))) -#define UART0_DLL (*(REG32 (0xE000C000))) -#define UART0_DLM (*(REG32 (0xE000C004))) - -/* ---- UART 1 --------------------------------------------- */ -#define UART1_RBR (*(REG32 (0xE0010000))) -#define UART1_THR (*(REG32 (0xE0010000))) -#define UART1_IER (*(REG32 (0xE0010004))) -#define UART1_IIR (*(REG32 (0xE0010008))) -#define UART1_FCR (*(REG32 (0xE0010008))) -#define UART1_LCR (*(REG32 (0xE001000C))) -#define UART1_LSR (*(REG32 (0xE0010014))) -#define UART1_SCR (*(REG32 (0xE001001C))) -#define UART1_DLL (*(REG32 (0xE0010000))) -#define UART1_DLM (*(REG32 (0xE0010004))) -#define UART1_MCR (*(REG32 (0xE0010010))) -#define UART1_MSR (*(REG32 (0xE0010018))) - - -/*############################################################################## -## I2C -##############################################################################*/ - -#define I2C_I2CONSET (*(REG32 (0xE001C000))) -#define I2C_I2STAT (*(REG32 (0xE001C004))) -#define I2C_I2DAT (*(REG32 (0xE001C008))) -#define I2C_I2ADR (*(REG32 (0xE001C00C))) -#define I2C_I2SCLH (*(REG32 (0xE001C010))) -#define I2C_I2SCLL (*(REG32 (0xE001C014))) -#define I2C_I2CONCLR (*(REG32 (0xE001C018))) - - -/*############################################################################## -## SPI - Serial Peripheral Interface -##############################################################################*/ - -#define SPI_SPCR (*(REG32 (0xE0020000))) -#define SPI_SPSR (*(REG32 (0xE0020004))) -#define SPI_SPDR (*(REG32 (0xE0020008))) -#define SPI_SPCCR (*(REG32 (0xE002000C))) -#define SPI_SPTCR (*(REG32 (0xE0020010))) -#define SPI_SPTSR (*(REG32 (0xE0020014))) -#define SPI_SPTOR (*(REG32 (0xE0020018))) -#define SPI_SPINT (*(REG32 (0xE002001C))) - - -/*############################################################################## -## Timer 0 and Timer 1 -##############################################################################*/ - -/* ---- Timer 0 -------------------------------------------- */ -#define T0_IR (*(REG32 (0xE0004000))) -#define T0_TCR (*(REG32 (0xE0004004))) -#define T0_TC (*(REG32 (0xE0004008))) -#define T0_PR (*(REG32 (0xE000400C))) -#define T0_PC (*(REG32 (0xE0004010))) -#define T0_MCR (*(REG32 (0xE0004014))) -#define T0_MR0 (*(REG32 (0xE0004018))) -#define T0_MR1 (*(REG32 (0xE000401C))) -#define T0_MR2 (*(REG32 (0xE0004020))) -#define T0_MR3 (*(REG32 (0xE0004024))) -#define T0_CCR (*(REG32 (0xE0004028))) -#define T0_CR0 (*(REG32 (0xE000402C))) -#define T0_CR1 (*(REG32 (0xE0004030))) -#define T0_CR2 (*(REG32 (0xE0004034))) -#define T0_CR3 (*(REG32 (0xE0004038))) -#define T0_EMR (*(REG32 (0xE000403C))) - -/* ---- Timer 1 -------------------------------------------- */ -#define T1_IR (*(REG32 (0xE0008000))) -#define T1_TCR (*(REG32 (0xE0008004))) -#define T1_TC (*(REG32 (0xE0008008))) -#define T1_PR (*(REG32 (0xE000800C))) -#define T1_PC (*(REG32 (0xE0008010))) -#define T1_MCR (*(REG32 (0xE0008014))) -#define T1_MR0 (*(REG32 (0xE0008018))) -#define T1_MR1 (*(REG32 (0xE000801C))) -#define T1_MR2 (*(REG32 (0xE0008020))) -#define T1_MR3 (*(REG32 (0xE0008024))) -#define T1_CCR (*(REG32 (0xE0008028))) -#define T1_CR0 (*(REG32 (0xE000802C))) -#define T1_CR1 (*(REG32 (0xE0008030))) -#define T1_CR2 (*(REG32 (0xE0008034))) -#define T1_CR3 (*(REG32 (0xE0008038))) -#define T1_EMR (*(REG32 (0xE000803C))) - - -/*############################################################################## -## PWM -##############################################################################*/ - -#define PWM_IR (*(REG32 (0xE0014000))) -#define PWM_TCR (*(REG32 (0xE0014004))) -#define PWM_TC (*(REG32 (0xE0014008))) -#define PWM_PR (*(REG32 (0xE001400C))) -#define PWM_PC (*(REG32 (0xE0014010))) -#define PWM_MCR (*(REG32 (0xE0014014))) -#define PWM_MR0 (*(REG32 (0xE0014018))) -#define PWM_MR1 (*(REG32 (0xE001401C))) -#define PWM_MR2 (*(REG32 (0xE0014020))) -#define PWM_MR3 (*(REG32 (0xE0014024))) -#define PWM_MR4 (*(REG32 (0xE0014040))) -#define PWM_MR5 (*(REG32 (0xE0014044))) -#define PWM_MR6 (*(REG32 (0xE0014048))) -#define PWM_EMR (*(REG32 (0xE001403C))) -#define PWM_PCR (*(REG32 (0xE001404C))) -#define PWM_LER (*(REG32 (0xE0014050))) -#define PWM_CCR (*(REG32 (0xE0014028))) -#define PWM_CR0 (*(REG32 (0xE001402C))) -#define PWM_CR1 (*(REG32 (0xE0014030))) -#define PWM_CR2 (*(REG32 (0xE0014034))) -#define PWM_CR3 (*(REG32 (0xE0014038))) - -/*############################################################################## -## RTC -##############################################################################*/ - -/* ---- RTC: Miscellaneous Register Group ------------------ */ -#define RTC_ILR (*(REG32 (0xE0024000))) -#define RTC_CTC (*(REG32 (0xE0024004))) -#define RTC_CCR (*(REG32 (0xE0024008))) -#define RTC_CIIR (*(REG32 (0xE002400C))) -#define RTC_AMR (*(REG32 (0xE0024010))) -#define RTC_CTIME0 (*(REG32 (0xE0024014))) -#define RTC_CTIME1 (*(REG32 (0xE0024018))) -#define RTC_CTIME2 (*(REG32 (0xE002401C))) - -/* ---- RTC: Timer Control Group --------------------------- */ -#define RTC_SEC (*(REG32 (0xE0024020))) -#define RTC_MIN (*(REG32 (0xE0024024))) -#define RTC_HOUR (*(REG32 (0xE0024028))) -#define RTC_DOM (*(REG32 (0xE002402C))) -#define RTC_DOW (*(REG32 (0xE0024030))) -#define RTC_DOY (*(REG32 (0xE0024034))) -#define RTC_MONTH (*(REG32 (0xE0024038))) -#define RTC_YEAR (*(REG32 (0xE002403C))) - -/* ---- RTC: Alarm Control Group --------------------------- */ -#define RTC_ALSEC (*(REG32 (0xE0024060))) -#define RTC_ALMIN (*(REG32 (0xE0024064))) -#define RTC_ALHOUR (*(REG32 (0xE0024068))) -#define RTC_ALDOM (*(REG32 (0xE002406C))) -#define RTC_ALDOW (*(REG32 (0xE0024070))) -#define RTC_ALDOY (*(REG32 (0xE0024074))) -#define RTC_ALMON (*(REG32 (0xE0024078))) -#define RTC_ALYEAR (*(REG32 (0xE002407C))) - -/* ---- RTC: Reference Clock Divider Group ----------------- */ -#define RTC_PREINT (*(REG32 (0xE0024080))) -#define RTC_PREFRAC (*(REG32 (0xE0024084))) - - -/*############################################################################## -## WD - Watchdog -##############################################################################*/ - -#define WD_WDMOD (*(REG32 (0xE0000000))) -#define WD_WDTC (*(REG32 (0xE0000004))) -#define WD_WDFEED (*(REG32 (0xE0000008))) -#define WD_WDTV (*(REG32 (0xE000000C))) - - -/*############################################################################## -## System Control Block -##############################################################################*/ - -#define SCB_EXTINT (*(REG32 (0xE01FC140))) -#define SCB_EXTWAKE (*(REG32 (0xE01FC144))) -#define SCB_MEMMAP (*(REG32 (0xE01FC040))) -#define SCB_PLLCON (*(REG32 (0xE01FC080))) -#define SCB_PLLCFG (*(REG32 (0xE01FC084))) -#define SCB_PLLSTAT (*(REG32 (0xE01FC088))) -#define SCB_PLLFEED (*(REG32 (0xE01FC08C))) -#define SCB_PCON (*(REG32 (0xE01FC0C0))) -#define SCB_PCONP (*(REG32 (0xE01FC0C4))) -#define SCB_VPBDIV (*(REG32 (0xE01FC100))) - -/*############################################################################## -## Memory Accelerator Module (MAM) -##############################################################################*/ - -#define MAM_TIM (*(REG32 (0xE01FC004))) -#define MAM_CR (*(REG32 (0xE01FC000))) - -#endif /* lpc210x_h */ - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/main.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/main.c deleted file mode 100644 index 62e3a7785..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/main.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ - - -/* - * Creates all the application tasks, then starts the scheduler. - * - * A task is created called "uIP". This executes the uIP stack and small - * WEB server sample. All the other tasks are from the set of standard - * demo tasks. The WEB documentation provides more details of the standard - * demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each standard demo task maintains a unique count that is incremented each - * time the task successfully completes its function. Should any error occur - * within such a task the count is permanently halted. The check task inspects - * the count of each task to ensure it has changed since the last time the - * check task executed. If all the count variables have changed all the tasks - * are still executing error free, and the check task toggles the yellow LED. - * Should any task contain an error at any time the LED toggle rate will change - * from 3 seconds to 500ms. - * - */ - - -/* Standard includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "PollQ.h" -#include "dynamic.h" -#include "semtest.h" - -/*-----------------------------------------------------------*/ - -/* Constants to setup the PLL. */ -#define mainPLL_MUL_4 ( ( unsigned char ) 0x0003 ) -#define mainPLL_DIV_1 ( ( unsigned char ) 0x0000 ) -#define mainPLL_ENABLE ( ( unsigned char ) 0x0001 ) -#define mainPLL_CONNECT ( ( unsigned char ) 0x0003 ) -#define mainPLL_FEED_BYTE1 ( ( unsigned char ) 0xaa ) -#define mainPLL_FEED_BYTE2 ( ( unsigned char ) 0x55 ) -#define mainPLL_LOCK ( ( unsigned long ) 0x0400 ) - -/* Constants to setup the MAM. */ -#define mainMAM_TIM_3 ( ( unsigned char ) 0x03 ) -#define mainMAM_MODE_FULL ( ( unsigned char ) 0x02 ) - -/* Constants to setup the peripheral bus. */ -#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) - -/* Priorities/stacks for the demo application tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainUIP_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainUIP_TASK_STACK_SIZE ( 150 ) - -/* The rate at which the on board LED will toggle when there is/is not an -error. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) -#define mainON_BOARD_LED_BIT ( ( unsigned long ) 0x80 ) -#define mainYELLOW_LED ( 1 << 11 ) - -/*-----------------------------------------------------------*/ - -/* - * This is the uIP task which is defined within the uip.c file. This has not - * been placed into a header file in order to minimise the changes to the uip - * code. - */ -extern void ( vuIP_TASK ) ( void *pvParameters ); - -/* - * The Yellow LED is under the control of the Check task. All the other LED's - * are under the control of the uIP task. - */ -void prvToggleOnBoardLED( void ); - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. - */ -static long prvCheckOtherTasksAreStillRunning( void ); - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Configure the processor for use with the Olimex demo board. This includes - * setup for the I/O, system clock, and access timings. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -int main( void ) -{ - /* Configure the processor. */ - prvSetupHardware(); - - /* Start the task that handles the TCP/IP functionality. */ - xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL ); - - /* Start the demo/test application tasks. These are created in addition - to the TCP/IP task for demonstration and test purposes. */ - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - vTaskStartScheduler(); - - /* Should never reach here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. */ - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Check all the standard demo application tasks are executing without - error. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - prvToggleOnBoardLED(); - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - #ifdef RUN_FROM_RAM - /* Remap the interrupt vectors to RAM if we are are running from RAM. */ - SCB_MEMMAP = 2; - #endif - - /* Setup the PLL to multiply the XTAL input by 4. */ - SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); - - /* Activate the PLL by turning it on then feeding the correct sequence of - bytes. */ - SCB_PLLCON = mainPLL_ENABLE; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Wait for the PLL to lock... */ - while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); - - /* ...before connecting it using the feed sequence again. */ - SCB_PLLCON = mainPLL_CONNECT; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Setup and turn on the MAM. Three cycle access is used due to the fast - PLL used. It is possible faster overall performance could be obtained by - tuning the MAM and PLL settings. */ - MAM_TIM = mainMAM_TIM_3; - MAM_CR = mainMAM_MODE_FULL; - - /* Setup the peripheral bus to be the same as the PLL output. */ - SCB_VPBDIV = mainBUS_CLK_FULL; -} -/*-----------------------------------------------------------*/ - -void prvToggleOnBoardLED( void ) -{ -unsigned long ulState; - - ulState = GPIO0_IOPIN; - if( ulState & mainYELLOW_LED ) - { - GPIO_IOCLR = mainYELLOW_LED; - } - else - { - GPIO_IOSET = mainYELLOW_LED; - } -} -/*-----------------------------------------------------------*/ - -static long prvCheckOtherTasksAreStillRunning( void ) -{ -long lReturn = ( long ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - return lReturn; -} - - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp deleted file mode 100644 index e5d235ed2..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp +++ /dev/null @@ -1,56 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs deleted file mode 100644 index 768dbc3fd..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs +++ /dev/null @@ -1,51 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile deleted file mode 100644 index 61d3a06aa..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile +++ /dev/null @@ -1,74 +0,0 @@ -# Copyright (c) 2001, Adam Dunkels. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. All advertising materials mentioning features or use of this software -# must display the following acknowledgement: -# This product includes software developed by Adam Dunkels. -# 4. The name of the author may not be used to endorse or promote -# products derived from this software without specific prior -# written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# This file is part of the uIP TCP/IP stack. -# -# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $ -# - -CC=gcc -CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp -I../apps/telnet -fpack-struct - -%.o: - $(CC) $(CFLAGS) -c $(<:.o=.c) - - -uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o - -tapdev.o: tapdev.c uipopt.h -main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \ - tapdev.h -uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \ - ../apps/httpd/httpd.h -uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h - -uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \ - ../apps/httpd/httpd.h - $(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c - - -cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \ - ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h -fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \ - ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \ - ../apps/httpd/fsdata.c -fsdata.o: ../apps/httpd/fsdata.c -httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \ - ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \ - ../apps/httpd/fsdata.h ../apps/httpd/cgi.h - -clean: - rm -f *.o *~ *core uip - - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c deleted file mode 100644 index 06574a156..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c +++ /dev/null @@ -1,211 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server script language C functions file. - * \author Adam Dunkels - * - * This file contains functions that are called by the web server - * scripts. The functions takes one argument, and the return value is - * interpreted as follows. A zero means that the function did not - * complete and should be invoked for the next packet as well. A - * non-zero value indicates that the function has completed and that - * the web server should move along to the next script line. - * - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $ - * - */ - -#include "uip.h" -#include "cgi.h" -#include "httpd.h" -#include "fs.h" - -#include -#include - -static u8_t print_stats(u8_t next); -static u8_t file_stats(u8_t next); -static u8_t tcp_stats(u8_t next); - -cgifunction cgitab[] = { - print_stats, /* CGI function "a" */ - file_stats, /* CGI function "b" */ - tcp_stats /* CGI function "c" */ -}; - -static const char closed[] = /* "CLOSED",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; -static const char syn_rcvd[] = /* "SYN-RCVD",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, - 0x44, 0}; -static const char syn_sent[] = /* "SYN-SENT",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, - 0x54, 0}; -static const char established[] = /* "ESTABLISHED",*/ -{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, - 0x45, 0x44, 0}; -static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x31, 0}; -static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x32, 0}; -static const char closing[] = /* "CLOSING",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x49, - 0x4e, 0x47, 0}; -static const char time_wait[] = /* "TIME-WAIT,"*/ -{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, - 0x49, 0x54, 0}; -static const char last_ack[] = /* "LAST-ACK"*/ -{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, - 0x4b, 0}; - -static const char *states[] = { - closed, - syn_rcvd, - syn_sent, - established, - fin_wait_1, - fin_wait_2, - closing, - time_wait, - last_ack}; - - -/*-----------------------------------------------------------------------------------*/ -/* print_stats: - * - * Prints out a part of the uIP statistics. The statistics data is - * written into the uip_appdata buffer. It overwrites any incoming - * packet. - */ -static u8_t -print_stats(u8_t next) -{ -#if UIP_STATISTICS - u16_t i, j; - u8_t *buf; - u16_t *databytes; - - if(next) { - /* If our last data has been acknowledged, we move on the next - chunk of statistics. */ - hs->count = hs->count + 4; - if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) { - /* We have printed out all statistics, so we return 1 to - indicate that we are done. */ - return 1; - } - } - - /* Write part of the statistics into the uip_appdata buffer. */ - databytes = (u16_t *)&uip_stat + hs->count; - buf = (u8_t *)uip_appdata; - - j = 4 + 1; - i = hs->count; - while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) { - sprintf((char *)buf, "%5u\r\n", *databytes); - ++databytes; - buf += 6; - ++i; - } - - /* Send the data. */ - uip_send(uip_appdata, buf - uip_appdata); - - return 0; -#else - return 1; -#endif /* UIP_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -static u8_t -file_stats(u8_t next) -{ - /* We use sprintf() to print the number of file accesses to a - particular file (given as an argument to the function in the - script). We then use uip_send() to actually send the data. */ - if(next) { - return 1; - } - uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4]))); - return 0; -} -/*-----------------------------------------------------------------------------------*/ -static u8_t -tcp_stats(u8_t next) -{ - struct uip_conn *conn; - - if(next) { - /* If the previously sent data has been acknowledged, we move - forward one connection. */ - if(++hs->count == UIP_CONNS) { - /* If all connections has been printed out, we are done and - return 1. */ - return 1; - } - } - - conn = &uip_conns[hs->count]; - if((conn->tcpstateflags & TS_MASK) == CLOSED) { - uip_send(uip_appdata, sprintf((char *)uip_appdata, - "--%u%u%c %c\r\n", - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' ')); - } else { - uip_send(uip_appdata, sprintf((char *)uip_appdata, - "%u.%u.%u.%u:%u%s%u%u%c %c\r\n", - htons(conn->ripaddr[0]) >> 8, - htons(conn->ripaddr[0]) & 0xff, - htons(conn->ripaddr[1]) >> 8, - htons(conn->ripaddr[1]) & 0xff, - htons(conn->rport), - states[conn->tcpstateflags & TS_MASK], - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' ')); - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h deleted file mode 100644 index d85389b52..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP script language header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $ - * - */ - -#ifndef __CGI_H__ -#define __CGI_H__ - -typedef u8_t (* cgifunction)(u8_t next); - -/** - * A table containing pointers to C functions that can be called from - * a web server script. - */ -extern cgifunction cgitab[]; - -#endif /* __CGI_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm deleted file mode 100644 index ef91f42a8..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm +++ /dev/null @@ -1,66 +0,0 @@ -// Rowley C Compiler, runtime support. -// -// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited. -// -// This file may be distributed under the terms of the License Agreement -// provided with this software. -// -// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE -// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - -; Create sections - .data - .bss - -; Go to code section. - .code - -; Executed upon reset -__reset proc - -; Turn off watchdog. You can enable it in main() if required. - mov.w #0x5a80, &0x120 - -; Set up stack. - mov.w #RAM_Start_Address+RAM_Size, sp - -; Copy from initialised data section to data section. - mov.w #SFB(IDATA0), r15 - mov.w #data_init_begin, r14 - mov.w #data_init_end-data_init_begin, r13 - call #_memcpy - -; Zero the bss. Ensure the stack is not allocated in the bss! - mov.w #SFB(UDATA0), r15 - mov.w #0, r14 - mov.w #SFE(UDATA0)-SFB(UDATA0), r13 - call #_memset - -; Call user entry point void main(void). - call #_main - -; If main() returns, kick off again. - jmp __reset - endproc - -; Heap data structures; removed by the linker if the heap isn't used. - .break - .data - align WORD -___heap_start__:: - DW 0 - DW heap_size - DS heap_size-4 - -; Reset vector - .vectors - .keep - org 0x1e - dw __reset - -; Initialise the IDATA0 section by duplicating the contents into the -; CONST section and copying them on startup. - .const -data_init_begin: - .init "IDATA0" -data_init_end: diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c deleted file mode 100644 index 6d06fd673..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c +++ /dev/null @@ -1,546 +0,0 @@ -// cs8900a.c: device driver for the CS8900a chip in 8-bit mode. - -#include - -#include "cs8900a.h" -#include "uip.h" -#include "uip_arp.h" - -#define IOR (1<<12) // CS8900's ISA-bus interface pins -#define IOW (1<<13) - -// definitions for Crystal CS8900 ethernet-controller -// based on linux-header by Russel Nelson - -#define PP_ChipID 0x0000 // offset 0h -> Corp-ID - - // offset 2h -> Model/Product Number -#define LED_RED (1<<8) -#define LED_GREEN (1<<10) -#define LED_YELLOW (1<<11) - -#define PP_ISAIOB 0x0020 // IO base address -#define PP_CS8900_ISAINT 0x0022 // ISA interrupt select -#define PP_CS8900_ISADMA 0x0024 // ISA Rec DMA channel -#define PP_ISASOF 0x0026 // ISA DMA offset -#define PP_DmaFrameCnt 0x0028 // ISA DMA Frame count -#define PP_DmaByteCnt 0x002A // ISA DMA Byte count -#define PP_CS8900_ISAMemB 0x002C // Memory base -#define PP_ISABootBase 0x0030 // Boot Prom base -#define PP_ISABootMask 0x0034 // Boot Prom Mask - -// EEPROM data and command registers -#define PP_EECMD 0x0040 // NVR Interface Command register -#define PP_EEData 0x0042 // NVR Interface Data Register - -// Configuration and control registers -#define PP_RxCFG 0x0102 // Rx Bus config -#define PP_RxCTL 0x0104 // Receive Control Register -#define PP_TxCFG 0x0106 // Transmit Config Register -#define PP_TxCMD 0x0108 // Transmit Command Register -#define PP_BufCFG 0x010A // Bus configuration Register -#define PP_LineCTL 0x0112 // Line Config Register -#define PP_SelfCTL 0x0114 // Self Command Register -#define PP_BusCTL 0x0116 // ISA bus control Register -#define PP_TestCTL 0x0118 // Test Register - -// Status and Event Registers -#define PP_ISQ 0x0120 // Interrupt Status -#define PP_RxEvent 0x0124 // Rx Event Register -#define PP_TxEvent 0x0128 // Tx Event Register -#define PP_BufEvent 0x012C // Bus Event Register -#define PP_RxMiss 0x0130 // Receive Miss Count -#define PP_TxCol 0x0132 // Transmit Collision Count -#define PP_LineST 0x0134 // Line State Register -#define PP_SelfST 0x0136 // Self State register -#define PP_BusST 0x0138 // Bus Status -#define PP_TDR 0x013C // Time Domain Reflectometry - -// Initiate Transmit Registers -#define PP_TxCommand 0x0144 // Tx Command -#define PP_TxLength 0x0146 // Tx Length - -// Adress Filter Registers -#define PP_LAF 0x0150 // Hash Table -#define PP_IA 0x0158 // Physical Address Register - -// Frame Location -#define PP_RxStatus 0x0400 // Receive start of frame -#define PP_RxLength 0x0402 // Receive Length of frame -#define PP_RxFrame 0x0404 // Receive frame pointer -#define PP_TxFrame 0x0A00 // Transmit frame pointer - -// Primary I/O Base Address. If no I/O base is supplied by the user, then this -// can be used as the default I/O base to access the PacketPage Area. -#define DEFAULTIOBASE 0x0300 - -// PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write -#define SKIP_1 0x0040 -#define RX_STREAM_ENBL 0x0080 -#define RX_OK_ENBL 0x0100 -#define RX_DMA_ONLY 0x0200 -#define AUTO_RX_DMA 0x0400 -#define BUFFER_CRC 0x0800 -#define RX_CRC_ERROR_ENBL 0x1000 -#define RX_RUNT_ENBL 0x2000 -#define RX_EXTRA_DATA_ENBL 0x4000 - -// PP_RxCTL - Receive Control bit definition - Read/write -#define RX_IA_HASH_ACCEPT 0x0040 -#define RX_PROM_ACCEPT 0x0080 -#define RX_OK_ACCEPT 0x0100 -#define RX_MULTCAST_ACCEPT 0x0200 -#define RX_IA_ACCEPT 0x0400 -#define RX_BROADCAST_ACCEPT 0x0800 -#define RX_BAD_CRC_ACCEPT 0x1000 -#define RX_RUNT_ACCEPT 0x2000 -#define RX_EXTRA_DATA_ACCEPT 0x4000 - -// PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write -#define TX_LOST_CRS_ENBL 0x0040 -#define TX_SQE_ERROR_ENBL 0x0080 -#define TX_OK_ENBL 0x0100 -#define TX_LATE_COL_ENBL 0x0200 -#define TX_JBR_ENBL 0x0400 -#define TX_ANY_COL_ENBL 0x0800 -#define TX_16_COL_ENBL 0x8000 - -// PP_TxCMD - Transmit Command bit definition - Read-only and -// PP_TxCommand - Write-only -#define TX_START_5_BYTES 0x0000 -#define TX_START_381_BYTES 0x0040 -#define TX_START_1021_BYTES 0x0080 -#define TX_START_ALL_BYTES 0x00C0 -#define TX_FORCE 0x0100 -#define TX_ONE_COL 0x0200 -#define TX_NO_CRC 0x1000 -#define TX_RUNT 0x2000 - -// PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write -#define GENERATE_SW_INTERRUPT 0x0040 -#define RX_DMA_ENBL 0x0080 -#define READY_FOR_TX_ENBL 0x0100 -#define TX_UNDERRUN_ENBL 0x0200 -#define RX_MISS_ENBL 0x0400 -#define RX_128_BYTE_ENBL 0x0800 -#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 -#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 -#define RX_DEST_MATCH_ENBL 0x8000 - -// PP_LineCTL - Line Control bit definition - Read/write -#define SERIAL_RX_ON 0x0040 -#define SERIAL_TX_ON 0x0080 -#define AUI_ONLY 0x0100 -#define AUTO_AUI_10BASET 0x0200 -#define MODIFIED_BACKOFF 0x0800 -#define NO_AUTO_POLARITY 0x1000 -#define TWO_PART_DEFDIS 0x2000 -#define LOW_RX_SQUELCH 0x4000 - -// PP_SelfCTL - Software Self Control bit definition - Read/write -#define POWER_ON_RESET 0x0040 -#define SW_STOP 0x0100 -#define SLEEP_ON 0x0200 -#define AUTO_WAKEUP 0x0400 -#define HCB0_ENBL 0x1000 -#define HCB1_ENBL 0x2000 -#define HCB0 0x4000 -#define HCB1 0x8000 - -// PP_BusCTL - ISA Bus Control bit definition - Read/write -#define RESET_RX_DMA 0x0040 -#define MEMORY_ON 0x0400 -#define DMA_BURST_MODE 0x0800 -#define IO_CHANNEL_READY_ON 0x1000 -#define RX_DMA_SIZE_64K 0x2000 -#define ENABLE_IRQ 0x8000 - -// PP_TestCTL - Test Control bit definition - Read/write -#define LINK_OFF 0x0080 -#define ENDEC_LOOPBACK 0x0200 -#define AUI_LOOPBACK 0x0400 -#define BACKOFF_OFF 0x0800 -#define FDX_8900 0x4000 - -// PP_RxEvent - Receive Event Bit definition - Read-only -#define RX_IA_HASHED 0x0040 -#define RX_DRIBBLE 0x0080 -#define RX_OK 0x0100 -#define RX_HASHED 0x0200 -#define RX_IA 0x0400 -#define RX_BROADCAST 0x0800 -#define RX_CRC_ERROR 0x1000 -#define RX_RUNT 0x2000 -#define RX_EXTRA_DATA 0x4000 -#define HASH_INDEX_MASK 0xFC00 // Hash-Table Index Mask (6 Bit) - -// PP_TxEvent - Transmit Event Bit definition - Read-only -#define TX_LOST_CRS 0x0040 -#define TX_SQE_ERROR 0x0080 -#define TX_OK 0x0100 -#define TX_LATE_COL 0x0200 -#define TX_JBR 0x0400 -#define TX_16_COL 0x8000 -#define TX_COL_COUNT_MASK 0x7800 - -// PP_BufEvent - Buffer Event Bit definition - Read-only -#define SW_INTERRUPT 0x0040 -#define RX_DMA 0x0080 -#define READY_FOR_TX 0x0100 -#define TX_UNDERRUN 0x0200 -#define RX_MISS 0x0400 -#define RX_128_BYTE 0x0800 -#define TX_COL_OVRFLW 0x1000 -#define RX_MISS_OVRFLW 0x2000 -#define RX_DEST_MATCH 0x8000 - -// PP_LineST - Ethernet Line Status bit definition - Read-only -#define LINK_OK 0x0080 -#define AUI_ON 0x0100 -#define TENBASET_ON 0x0200 -#define POLARITY_OK 0x1000 -#define CRS_OK 0x4000 - -// PP_SelfST - Chip Software Status bit definition -#define ACTIVE_33V 0x0040 -#define INIT_DONE 0x0080 -#define SI_BUSY 0x0100 -#define EEPROM_PRESENT 0x0200 -#define EEPROM_OK 0x0400 -#define EL_PRESENT 0x0800 -#define EE_SIZE_64 0x1000 - -// PP_BusST - ISA Bus Status bit definition -#define TX_BID_ERROR 0x0080 -#define READY_FOR_TX_NOW 0x0100 - -// The following block defines the ISQ event types -#define ISQ_RX_EVENT 0x0004 -#define ISQ_TX_EVENT 0x0008 -#define ISQ_BUFFER_EVENT 0x000C -#define ISQ_RX_MISS_EVENT 0x0010 -#define ISQ_TX_COL_EVENT 0x0012 - -#define ISQ_EVENT_MASK 0x003F // ISQ mask to find out type of event - -// Ports for I/O-Mode -#define RX_FRAME_PORT 0x0000 -#define TX_FRAME_PORT 0x0000 -#define TX_CMD_PORT 0x0004 -#define TX_LEN_PORT 0x0006 -#define ISQ_PORT 0x0008 -#define ADD_PORT 0x000A -#define DATA_PORT 0x000C - -#define AUTOINCREMENT 0x8000 // Bit mask to set Bit-15 for autoincrement - -// EEProm Commands -#define EEPROM_WRITE_EN 0x00F0 -#define EEPROM_WRITE_DIS 0x0000 -#define EEPROM_WRITE_CMD 0x0100 -#define EEPROM_READ_CMD 0x0200 - -// Receive Header of each packet in receive area of memory for DMA-Mode -#define RBUF_EVENT_LOW 0x0000 // Low byte of RxEvent -#define RBUF_EVENT_HIGH 0x0001 // High byte of RxEvent -#define RBUF_LEN_LOW 0x0002 // Length of received data - low byte -#define RBUF_LEN_HI 0x0003 // Length of received data - high byte -#define RBUF_HEAD_LEN 0x0004 // Length of this header - -// typedefs -typedef struct { // struct to store CS8900's - unsigned int Addr; // init-sequence - unsigned int Data; -} TInitSeq; - -unsigned short ticks; - -static void skip_frame(void); - -const TInitSeq InitSeq[] = -{ - PP_IA, UIP_ETHADDR0 + (UIP_ETHADDR1 << 8), // set our MAC as Individual Address - PP_IA + 2, UIP_ETHADDR2 + (UIP_ETHADDR3 << 8), - PP_IA + 4, UIP_ETHADDR4 + (UIP_ETHADDR5 << 8), - PP_LineCTL, SERIAL_RX_ON | SERIAL_TX_ON, // configure the Physical Interface - PP_RxCTL, RX_OK_ACCEPT | RX_IA_ACCEPT | RX_BROADCAST_ACCEPT -}; - -// Writes a word in little-endian byte order to a specified port-address -void -cs8900a_write(unsigned addr, unsigned int data) -{ - GPIO_IODIR |= 0xff << 16; // Data port to output - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = addr << 4; - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = data << 16; - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - __asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - __asm volatile ( "NOP" ); - - GPIO_IOCLR = 0xf << 4; - GPIO_IOSET = ((addr | 1) << 4); // And put next address on bus - - GPIO_IOCLR = 0xff << 16; // Write high order byte to data bus - GPIO_IOSET = data >> 8 << 16; - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - __asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - __asm volatile ( "NOP" ); -} - -// Reads a word in little-endian byte order from a specified port-address -unsigned -cs8900a_read(unsigned addr) -{ - unsigned int value; - - GPIO_IODIR &= ~(0xff << 16); // Data port to input - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = addr << 4; - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOR; // IOR-signal low - __asm volatile ( "NOP" ); - value = (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus - GPIO_IOSET = IOR; - - GPIO_IOSET = 1 << 4; // IOR high and put next address on bus - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOR; // IOR-signal low - __asm volatile ( "NOP" ); - value |= ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus - GPIO_IOSET = IOR; // IOR-signal low - - return value; -} - -// Reads a word in little-endian byte order from a specified port-address -unsigned -cs8900a_read_addr_high_first(unsigned addr) -{ - unsigned int value; - - GPIO_IODIR &= ~(0xff << 16); // Data port to input - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = (addr+1) << 4; - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOR; // IOR-signal low - __asm volatile ( "NOP" ); - value = ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus - GPIO_IOSET = IOR; // IOR-signal high - - GPIO_IOCLR = 1 << 4; // Put low address on bus - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOR; // IOR-signal low - __asm volatile ( "NOP" ); - value |= (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus - GPIO_IOSET = IOR; - - return value; -} - -void -cs8900a_init(void) -{ - int i; - - // Reset outputs, control lines high - GPIO_IOSET = IOR | IOW; - - // No LEDs on. - GPIO_IOSET = LED_RED | LED_YELLOW | LED_GREEN; - - // Port 3 as output (all pins but RS232) - GPIO_IODIR = ~0U; // everything to output. - - // Reset outputs - GPIO_IOCLR = 0xff << 16; // clear data outputs - - // Reset the CS8900A - cs8900a_write(ADD_PORT, PP_SelfCTL); - cs8900a_write(DATA_PORT, POWER_ON_RESET); - - // Wait until chip-reset is done - cs8900a_write(ADD_PORT, PP_SelfST); - while ((cs8900a_read(DATA_PORT) & INIT_DONE) == 0) - ; - - // Configure the CS8900A - for (i = 0; i < sizeof InitSeq / sizeof (TInitSeq); ++i) - { - cs8900a_write(ADD_PORT, InitSeq[i].Addr); - cs8900a_write(DATA_PORT, InitSeq[i].Data); - } -} - -void -cs8900a_send(void) -{ - unsigned u; - - GPIO_IOCLR = LED_RED; // Light RED LED when frame starting - - // Transmit command - cs8900a_write(TX_CMD_PORT, TX_START_ALL_BYTES); - cs8900a_write(TX_LEN_PORT, uip_len); - - // Maximum number of retries - u = 8; - for (;;) - { - // Check for avaliable buffer space - cs8900a_write(ADD_PORT, PP_BusST); - if (cs8900a_read(DATA_PORT) & READY_FOR_TX_NOW) - break; - if (u -- == 0) - { - GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame - return; - } - - // No space avaliable, skip a received frame and try again - skip_frame(); - } - - GPIO_IODIR |= 0xff << 16; // Data port to output - - // Send 40+14=54 bytes of header - for (u = 0; u < 54; u += 2) - { - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = TX_FRAME_PORT << 4; - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = uip_buf[u] << 16; // write low order byte to data bus - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - __asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = uip_buf[u+1] << 16; // write low order byte to data bus - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - __asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - } - - if (uip_len <= 54) - { - GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame - return; - } - - // Send remainder of packet, the application data - uip_len -= 54; - for (u = 0; u < uip_len; u += 2) - { - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = TX_FRAME_PORT << 4; - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = uip_appdata[u] << 16; // write low order byte to data bus - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - __asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = uip_appdata[u+1] << 16; // write low order byte to data bus - - __asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - __asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - } - - GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame -} - -static void -skip_frame(void) -{ - // No space avaliable, skip a received frame and try again - cs8900a_write(ADD_PORT, PP_RxCFG); - cs8900a_write(DATA_PORT, cs8900a_read(DATA_PORT) | SKIP_1); -} - -u8_t -cs8900a_poll(void) -{ - u16_t len, u; - - // Check receiver event register to see if there are any valid frames avaliable - cs8900a_write(ADD_PORT, PP_RxEvent); - if ((cs8900a_read(DATA_PORT) & 0xd00) == 0) - return 0; - - GPIO_IOCLR = LED_GREEN; // Light GREED LED when frame coming in. - - // Read receiver status and discard it. - cs8900a_read_addr_high_first(RX_FRAME_PORT); - - // Read frame length - len = cs8900a_read_addr_high_first(RX_FRAME_PORT); - - // If the frame is too big to handle, throw it away - if (len > UIP_BUFSIZE) - { - skip_frame(); - return 0; - } - - // Data port to input - GPIO_IODIR &= ~(0xff << 16); - - GPIO_IOCLR = 0xf << 4; // put address on bus - GPIO_IOSET = RX_FRAME_PORT << 4; - - // Read bytes into uip_buf - u = 0; - while (u < len) - { - GPIO_IOCLR = 1 << 4; // put address on bus - - GPIO_IOCLR = IOR; // IOR-signal low - uip_buf[u] = GPIO_IOPIN >> 16; // get high order byte from data bus - __asm volatile ( "NOP" ); - GPIO_IOSET = IOR; // IOR-signal high - - GPIO_IOSET = 1 << 4; // put address on bus - - GPIO_IOCLR = IOR; // IOR-signal low - __asm volatile ( "NOP" ); - uip_buf[u+1] = GPIO_IOPIN >> 16; // get high order byte from data bus - GPIO_IOSET = IOR; // IOR-signal high - u += 2; - } - - GPIO_IOSET = LED_GREEN; // Extinguish GREED LED when frame finished. - return len; -} - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h deleted file mode 100644 index 2d4b56fe0..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __CS8900A_H__ -#define __CS8900A_H__ - -#include "uip_arch.h" - -void cs8900a_init(void); -void cs8900a_send(void); -u8_t cs8900a_poll(void); - -#endif /* __CS8900A_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c deleted file mode 100644 index 7e15200b2..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c +++ /dev/null @@ -1,155 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server read-only file system code. - * \author Adam Dunkels - * - * A simple read-only filesystem. - */ - -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $ - */ - -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" - -#define NULL (void *)0 -#include "fsdata.c" - -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -static u16_t count[FS_NUMFILES]; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - -/*-----------------------------------------------------------------------------------*/ -static u8_t -fs_strcmp(const char *str1, const char *str2) -{ - u8_t i; - i = 0; - loop: - - if(str2[i] == 0 || - str1[i] == '\r' || - str1[i] == '\n') { - return 0; - } - - if(str1[i] != str2[i]) { - return 1; - } - - - ++i; - goto loop; -} -/*-----------------------------------------------------------------------------------*/ -int -fs_open(const char *name, struct fs_file *file) -{ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t i = 0; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - struct fsdata_file_noconst *f; - - for(f = (struct fsdata_file_noconst *)FS_ROOT; - f != NULL; - f = (struct fsdata_file_noconst *)f->next) { - - if(fs_strcmp(name, f->name) == 0) { - file->data = f->data; - file->len = f->len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - ++count[i]; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - return 1; - } -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - ++i; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -void -fs_init(void) -{ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t i; - for(i = 0; i < FS_NUMFILES; i++) { - count[i] = 0; - } -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -u16_t fs_count -(char *name) -{ - struct fsdata_file_noconst *f; - u16_t i; - - i = 0; - for(f = (struct fsdata_file_noconst *)FS_ROOT; - f != NULL; - f = (struct fsdata_file_noconst *)f->next) { - - if(fs_strcmp(name, f->name) == 0) { - return count[i]; - } - ++i; - } - return 0; -} -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h deleted file mode 100644 index 65551ba41..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server read-only file system header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $ - */ -#ifndef __FS_H__ -#define __FS_H__ - -#include "uip.h" - -/** - * An open file in the read-only file system. - */ -struct fs_file { - char *data; /**< The actual file data. */ - int len; /**< The length of the file data. */ -}; - -/** - * Open a file in the read-only file system. - * - * \param name The name of the file. - * - * \param file The file pointer, which must be allocated by caller and - * will be filled in by the function. - */ -int fs_open(const char *name, struct fs_file *file); - -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -u16_t fs_count(char *name); -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - -/** - * Initialize the read-only file system. - */ -void fs_init(void); - -#endif /* __FS_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html deleted file mode 100644 index 8d6beec83..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html +++ /dev/null @@ -1 +0,0 @@ -

404 - file not found

\ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html deleted file mode 100644 index 4c886897b..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html +++ /dev/null @@ -1,18 +0,0 @@ - - -
-
-

Welcome

-

-These web pages are served by the small web server running on top of -the uIP TCP/IP -stack. -

-

-Click on the links above to see some status information about the web -server and the TCP/IP stack. -

-
-
- - \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files deleted file mode 100644 index 64e0b5005..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files +++ /dev/null @@ -1,28 +0,0 @@ -# This script shows the access statistics for different files on the -# web server. -# -# First, we include the HTML header. -i /files_header.html -# Print out the name of the file, and call the function that prints -# the access statistics of that file. -t /index.html -c b /index.html -t /about.html -c b /about.html -t /control.html -c b /control.html -t /img/bg.png -c b /img/bg.png -t /404.html -c b /404.html -t /cgi/files -c b /cgi/files -t /cgi/stats -c b /cgi/stats -t /cgi/tcp -c b /cgi/tcp -t -# Include the HTML footer. -i /files_footer.plain -# End of script. -. \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats deleted file mode 100644 index 2c71c90dc..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats +++ /dev/null @@ -1,4 +0,0 @@ -i /stats_header.html -c a -i /stats_footer.plain -. diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp deleted file mode 100644 index 14efd3700..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp +++ /dev/null @@ -1,4 +0,0 @@ -i /tcp_header.html -c c -i /tcp_footer.plain -. \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html deleted file mode 100644 index ce28dbe7d..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html +++ /dev/null @@ -1,14 +0,0 @@ - - -
-
-

uIP web server test pages

-[ About | -Connections | -Files | -Statistics ] -
-
- - \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain deleted file mode 100644 index 0b6dceb4f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html deleted file mode 100644 index 25d86501e..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html +++ /dev/null @@ -1,4 +0,0 @@ - - -
- diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png deleted file mode 100644 index 18533b36947070d5721b7a8f39134a5368d72dff..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1084 zcmeAS@N?(olHy`uVBq!ia0y~yV3q~4<2cxWq}$%gGeC+h$=lt9;Xep2*t>i(P=vF< zBeIx*fm;ZK886+f`vVkYFY)wsWxveDDx_qrbfIPzP)N4KHKN2hKQ}iuuY|$5C^fMp zHASI3vm`?yBqLS9-P1SVeTr%x(9Q*(E{-7;x8B}8ST@T+q9IWIIBU+uRH-*FfA4pl zr+jsbccJ86-|1#uY%)y>-``DIVb7ECYoRS?{(AYsGPN^#qVvw}7k^ynvg7Z<$yalu z>kkXRmuuUs8=HIkQ}{HK^54HFl>C2se#_6@zPJ7?Iy33omZuiJD}p*26| ze?g6I)Rdne%Km1WSq9&E?)XPe;^BM8V;^f)+WJ3kmjAO+PW&_r14D)}&`%c`85lbF z7#JK%fE+ku5i?W-g&`ozAj>t4fx(3xDC_<3?N{Y%HNU^HuQ@qGqF?!t?D~|pYPGOO zb>+MAWaXQePUoP-}_I&lT>+gMk z>o#9z@*~UdDhvrmdoE)Qoql=QyZ?UPlvo@Jbmzr`DJ^~SdJ(|11_~Frv*8R-pu!#2 z0CLieT)y(T`(u}%1;*Ht-{Gde??3DJ6-(Xyb9sMk?ziXW9Uo6I*ZeE`ILW$`ae?A{ zP|Seh0T}#1M)I0lHRpgV7xo8{ybM2{b22bAyZ}moEQd3|mSZ@lp>aku(*v>FUl)G+ zt@y>be!JzC-Oe5J_r*-9y!7W)?ftwzCspS?+PVK{>G35$CIT&g(OV9Q1?S7xuhzU~ z0tNKGKEw4}z$pdpDL4Z&5ha*h6l`JzI_)B(vtke<*p&yupG{+sSiI;=)ZKqy9?!j+ zR$tdFvEIgE`|bU|cl+=9|47w;_W$J%|8W0~wRwJj-~WfFQa9Q?i?{tR^qkoT<|0U9 q#bdKWiHYzNQKU2tPu#*E`BfIitaiLHX$dgg7(8A5T-G@yGywp+{Ey54 diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html deleted file mode 100644 index 3429ef3af..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html +++ /dev/null @@ -1,14 +0,0 @@ - -uIP web server test page - - - - - - - -<body> -Your browser must support frames -</body> - - \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain deleted file mode 100644 index 0b6dceb4f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain +++ /dev/null @@ -1,3 +0,0 @@ -
- - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html deleted file mode 100644 index 4efaddf5b..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html +++ /dev/null @@ -1,30 +0,0 @@ - - -
- -
-
-IP           Packets dropped
-             Packets received
-             Packets sent
-IP errors    IP version/header length
-             IP length, high byte
-             IP length, low byte
-             IP fragments
-             Header checksum
-             Wrong protocol
-ICMP	     Packets dropped
-             Packets received
-             Packets sent
-             Type errors
-TCP          Packets dropped
-             Packets received
-             Packets sent
-             Checksum errors
-             Data packets without ACKs
-             Resets
-             Retransmissions
-	     No connection avaliable
-	     Connection attempts to closed ports
-
-
\ No newline at end of file
diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain
deleted file mode 100644
index 442c17a58..000000000
--- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
- - \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html deleted file mode 100644 index 1a5057167..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html +++ /dev/null @@ -1,6 +0,0 @@ - - -
- - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c deleted file mode 100644 index ff855e7dc..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c +++ /dev/null @@ -1,619 +0,0 @@ -static const char data_cgi_files[] = { - /* /cgi/files */ - 0x2f, 0x63, 0x67, 0x69, 0x2f, 0x66, 0x69, 0x6c, 0x65, 0x73, 0, - 0x23, 0x20, 0x54, 0x68, 0x69, 0x73, 0x20, 0x73, 0x63, 0x72, - 0x69, 0x70, 0x74, 0x20, 0x73, 0x68, 0x6f, 0x77, 0x73, 0x20, - 0x74, 0x68, 0x65, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, - 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 0x74, 0x69, 0x63, - 0x73, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x64, 0x69, 0x66, 0x66, - 0x65, 0x72, 0x65, 0x6e, 0x74, 0x20, 0x66, 0x69, 0x6c, 0x65, - 0x73, 0x20, 0x6f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0xa, 0x23, - 0x20, 0x77, 0x65, 0x62, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, - 0x72, 0x2e, 0xa, 0x23, 0xa, 0x23, 0x20, 0x46, 0x69, 0x72, - 0x73, 0x74, 0x2c, 0x20, 0x77, 0x65, 0x20, 0x69, 0x6e, 0x63, - 0x6c, 0x75, 0x64, 0x65, 0x20, 0x74, 0x68, 0x65, 0x20, 0x48, - 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11}}; - -const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}}; - -const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}}; - -const struct fsdata_file file_img_bg_png[] = {{file_cgi_tcp, data_img_bg_png, data_img_bg_png + 12, sizeof(data_img_bg_png) - 12}}; - -const struct fsdata_file file_about_html[] = {{file_img_bg_png, data_about_html, data_about_html + 12, sizeof(data_about_html) - 12}}; - -const struct fsdata_file file_control_html[] = {{file_about_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}}; - -const struct fsdata_file file_404_html[] = {{file_control_html, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; - -const struct fsdata_file file_files_footer_plain[] = {{file_404_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}}; - -const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}}; - -const struct fsdata_file file_index_html[] = {{file_files_header_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; - -const struct fsdata_file file_stats_footer_plain[] = {{file_index_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}}; - -const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}}; - -const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}}; - -const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}}; - -#define FS_ROOT file_tcp_header_html - -#define FS_NUMFILES 14 diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h deleted file mode 100644 index 94086c4df..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $ - */ -#ifndef __FSDATA_H__ -#define __FSDATA_H__ - -#include "uipopt.h" - -struct fsdata_file { - const struct fsdata_file *next; - const char *name; - const char *data; - const int len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t count; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -}; - -struct fsdata_file_noconst { - struct fsdata_file *next; - char *name; - char *data; - int len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t count; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -}; - -#endif /* __FSDATA_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c deleted file mode 100644 index 9d2c6e599..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c +++ /dev/null @@ -1,373 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \defgroup httpd Web server - * @{ - * - * The uIP web server is a very simplistic implementation of an HTTP - * server. It can serve web pages and files from a read-only ROM - * filesystem, and provides a very small scripting language. - * - * The script language is very simple and works as follows. Each - * script line starts with a command character, either "i", "t", "c", - * "#" or ".". The "i" command tells the script interpreter to - * "include" a file from the virtual file system and output it to the - * web browser. The "t" command should be followed by a line of text - * that is to be output to the browser. The "c" command is used to - * call one of the C functions from the httpd-cgi.c file. A line that - * starts with a "#" is ignored (i.e., the "#" denotes a comment), and - * the "." denotes the last script line. - * - * The script that produces the file statistics page looks somewhat - * like this: - * - \code -i /header.html -t

File statistics


RemoteStateRetransmissionsTimerFlags
-t
/index.html -c a /index.html -t
/cgi/files -c a /cgi/files -t
/cgi/tcp -c a /cgi/tcp -t
/404.html -c a /404.html -t
-i /footer.plain -. - \endcode - * - */ - - -/** - * \file - * HTTP server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $ - * - */ - - -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" -#include "cgi.h" - -#define NULL (void *)0 - -/* The HTTP server states: */ -#define HTTP_NOGET 0 -#define HTTP_FILE 1 -#define HTTP_TEXT 2 -#define HTTP_FUNC 3 -#define HTTP_END 4 - -#ifdef DEBUG -#include -#define PRINT(x) -#define PRINTLN(x) -#else /* DEBUG */ -#define PRINT(x) -#define PRINTLN(x) -#endif /* DEBUG */ - -struct httpd_state *hs; - -extern const struct fsdata_file file_index_html; -extern const struct fsdata_file file_404_html; - -static void next_scriptline(void); -static void next_scriptstate(void); - -#define ISO_G 0x47 -#define ISO_E 0x45 -#define ISO_T 0x54 -#define ISO_slash 0x2f -#define ISO_c 0x63 -#define ISO_g 0x67 -#define ISO_i 0x69 -#define ISO_space 0x20 -#define ISO_nl 0x0a -#define ISO_cr 0x0d -#define ISO_a 0x61 -#define ISO_t 0x74 -#define ISO_hash 0x23 -#define ISO_period 0x2e - -#define httpPORT 80 - -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the web server. - * - * Starts to listen for incoming connection requests on TCP port 80. - */ -/*-----------------------------------------------------------------------------------*/ -void -httpd_init(void) -{ - fs_init(); - - /* Listen to port 80. */ - uip_listen(HTONS(httpPORT)); -} -/*-----------------------------------------------------------------------------------*/ -void -httpd_appcall(void) -{ - struct fs_file fsfile; - - u8_t i; - - switch(uip_conn->lport) { - /* This is the web server: */ - case HTONS(httpPORT): - /* Pick out the application state from the uip_conn structure. */ - hs = (struct httpd_state *)(uip_conn->appstate); - - /* We use the uip_ test functions to deduce why we were - called. If uip_connected() is non-zero, we were called - because a remote host has connected to us. If - uip_newdata() is non-zero, we were called because the - remote host has sent us new data, and if uip_acked() is - non-zero, the remote host has acknowledged the data we - previously sent to it. */ - if(uip_connected()) { - /* Since we have just been connected with the remote host, we - reset the state for this connection. The ->count variable - contains the amount of data that is yet to be sent to the - remote host, and the ->state is set to HTTP_NOGET to signal - that we haven't received any HTTP GET request for this - connection yet. */ - - hs->state = HTTP_NOGET; - hs->count = 0; - return; - - } else if(uip_poll()) { - /* If we are polled ten times, we abort the connection. This is - because we don't want connections lingering indefinately in - the system. */ - if(hs->count++ >= 10) { - uip_abort(); - } - return; - } else if(uip_newdata() && hs->state == HTTP_NOGET) { - /* This is the first data we receive, and it should contain a - GET. */ - - /* Check for GET. */ - if(uip_appdata[0] != ISO_G || - uip_appdata[1] != ISO_E || - uip_appdata[2] != ISO_T || - uip_appdata[3] != ISO_space) { - /* If it isn't a GET, we abort the connection. */ - uip_abort(); - return; - } - - /* Find the file we are looking for. */ - for(i = 4; i < 40; ++i) { - if(uip_appdata[i] == ISO_space || - uip_appdata[i] == ISO_cr || - uip_appdata[i] == ISO_nl) { - uip_appdata[i] = 0; - break; - } - } - - PRINT("request for file "); - PRINTLN(&uip_appdata[4]); - - /* Check for a request for "/". */ - if(uip_appdata[4] == ISO_slash && - uip_appdata[5] == 0) { - fs_open(file_index_html.name, &fsfile); - } else { - if(!fs_open((const char *)&uip_appdata[4], &fsfile)) { - PRINTLN("couldn't open file"); - fs_open(file_404_html.name, &fsfile); - } - } - - - if(uip_appdata[4] == ISO_slash && - uip_appdata[5] == ISO_c && - uip_appdata[6] == ISO_g && - uip_appdata[7] == ISO_i && - uip_appdata[8] == ISO_slash) { - /* If the request is for a file that starts with "/cgi/", we - prepare for invoking a script. */ - hs->script = fsfile.data; - next_scriptstate(); - } else { - hs->script = NULL; - /* The web server is now no longer in the HTTP_NOGET state, but - in the HTTP_FILE state since is has now got the GET from - the client and will start transmitting the file. */ - hs->state = HTTP_FILE; - - /* Point the file pointers in the connection state to point to - the first byte of the file. */ - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - } - } - - - if(hs->state != HTTP_FUNC) { - /* Check if the client (remote end) has acknowledged any data that - we've previously sent. If so, we move the file pointer further - into the file and send back more data. If we are out of data to - send, we close the connection. */ - if(uip_acked()) { - if(hs->count >= uip_conn->len) { - hs->count -= uip_conn->len; - hs->dataptr += uip_conn->len; - } else { - hs->count = 0; - } - - if(hs->count == 0) { - if(hs->script != NULL) { - next_scriptline(); - next_scriptstate(); - } else { - uip_close(); - } - } - } - } else { - /* Call the CGI function. */ - if(cgitab[hs->script[2] - ISO_a](uip_acked())) { - /* If the function returns non-zero, we jump to the next line - in the script. */ - next_scriptline(); - next_scriptstate(); - } - } - - if(hs->state != HTTP_FUNC && !uip_poll()) { - /* Send a piece of data, but not more than the MSS of the - connection. */ - uip_send(hs->dataptr, hs->count); - } - - /* Finally, return to uIP. Our outgoing packet will soon be on its - way... */ - return; - - default: - /* Should never happen. */ - uip_abort(); - break; - } -} -/*-----------------------------------------------------------------------------------*/ -/* next_scriptline(): - * - * Reads the script until it finds a newline. */ -static void -next_scriptline(void) -{ - /* Loop until we find a newline character. */ - do { - ++(hs->script); - } while(hs->script[0] != ISO_nl); - - /* Eat up the newline as well. */ - ++(hs->script); -} -/*-----------------------------------------------------------------------------------*/ -/* next_sciptstate: - * - * Reads one line of script and decides what to do next. - */ -static void -next_scriptstate(void) -{ - struct fs_file fsfile; - u8_t i; - - again: - switch(hs->script[0]) { - case ISO_t: - /* Send a text string. */ - hs->state = HTTP_TEXT; - hs->dataptr = &hs->script[2]; - - /* Calculate length of string. */ - for(i = 0; hs->dataptr[i] != ISO_nl; ++i); - hs->count = i; - break; - case ISO_c: - /* Call a function. */ - hs->state = HTTP_FUNC; - hs->dataptr = NULL; - hs->count = 0; - cgitab[hs->script[2] - ISO_a](0); - break; - case ISO_i: - /* Include a file. */ - hs->state = HTTP_FILE; - if(!fs_open(&hs->script[2], &fsfile)) { - uip_abort(); - } - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - break; - case ISO_hash: - /* Comment line. */ - next_scriptline(); - goto again; - break; - case ISO_period: - /* End of script. */ - hs->state = HTTP_END; - uip_close(); - break; - default: - uip_abort(); - break; - } -} -/*-----------------------------------------------------------------------------------*/ -/** @} */ -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h deleted file mode 100644 index 34d6bb35f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $ - * - */ - -#ifndef __HTTPD_H__ -#define __HTTPD_H__ - -void httpd_init(void); -void httpd_appcall(void); - -/* UIP_APPCALL: the name of the application function. This function - must return void and take no arguments (i.e., C type "void - appfunc(void)"). */ -#ifndef UIP_APPCALL -#define UIP_APPCALL httpd_appcall -#endif - -struct httpd_state { - u8_t state; - u16_t count; - char *dataptr; - char *script; -}; - - -/* UIP_APPSTATE_SIZE: The size of the application-specific state - stored in the uip_conn structure. */ -#ifndef UIP_APPSTATE_SIZE -#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) -#endif - -#define FS_STATISTICS 1 - -extern struct httpd_state *hs; - -#endif /* __HTTPD_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/main_led b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/main_led deleted file mode 100644 index 8fe01ea6d..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/main_led +++ /dev/null @@ -1,67 +0,0 @@ -// Copyright (c) 2001-2004 Rowley Associates Limited. -// -// This file may be distributed under the terms of the License Agreement -// provided with this software. -// -// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE -// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. -// -//////////////////////////////////////////////////////////////////////////////// -// -// Olimex LPC-P1 LED Example -// -// Description -// ----------- -// This example demonstrates writing to the programmable peripheral interface. -// -//////////////////////////////////////////////////////////////////////////////// - -#include - -#define LED_RED (1<<8) -#define LED_GREEN (1<<10) -#define LED_YELLOW (1<<11) - -#define LED1 LED_YELLOW - -static void -ledInit() -{ - IODIR |= LED1; - IOSET = LED1; -} - -static void -ledOn(void) -{ - IOCLR = LED1; -} - -static void -ledOff(void) -{ - IOSET = LED1; -} - -void -delay(int d) -{ - for(; d; --d); -} - -int -main(void) -{ - MAMCR = 2; - ledInit(); - while (1) - { - ledOn(); - delay(100000); - ledOff(); - delay(100000); - } - return 0; -} - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata deleted file mode 100644 index f5f75f174..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata +++ /dev/null @@ -1,93 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> fsdata.c"); - -chdir("fs"); -open(FILES, "find . -type f |"); - -while($file = ) { - - # Do not include files in CVS directories nor backup files. - if($file =~ /(CVS|~)/) { - next; - } - - chop($file); - - open(HEADER, "> /tmp/header") || die $!; - if($file =~ /404.html/) { - print(HEADER "HTTP/1.0 404 File not found\r\n"); - } else { - print(HEADER "HTTP/1.0 200 OK\r\n"); - } - print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n"); - if($file =~ /\.html$/) { - print(HEADER "Content-type: text/html\r\n"); - } elsif($file =~ /\.gif$/) { - print(HEADER "Content-type: image/gif\r\n"); - } elsif($file =~ /\.png$/) { - print(HEADER "Content-type: image/png\r\n"); - } elsif($file =~ /\.jpg$/) { - print(HEADER "Content-type: image/jpeg\r\n"); - } else { - print(HEADER "Content-type: text/plain\r\n"); - } - print(HEADER "\r\n"); - close(HEADER); - - unless($file =~ /\.plain$/ || $file =~ /cgi/) { - system("cat /tmp/header $file > /tmp/file"); - } else { - system("cp $file /tmp/file"); - } - - open(FILE, "/tmp/file"); - unlink("/tmp/file"); - unlink("/tmp/header"); - - $file =~ s/\.//; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - print(OUTPUT "static const char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@files, $file); -} - -for($i = 0; $i < @fvars; $i++) { - $file = $files[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define FS_NUMFILES $i"); diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c deleted file mode 100644 index 56e663446..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c +++ /dev/null @@ -1,152 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \file - * Memory block allocation routines. - * \author Adam Dunkels - * - * The memory block allocation routines provide a simple yet powerful - * set of functions for managing a set of memory blocks of fixed - * size. A set of memory blocks is statically declared with the - * MEMB() macro. Memory blocks are allocated from the declared - * memory by the memb_alloc() function, and are deallocated with the - * memb_free() function. - * - * \note Because of namespace clashes only one MEMB() can be - * declared per C module, and the name scope of a MEMB() memory - * block is local to each C module. - * - * The following example shows how to declare and use a memory block - * called "cmem" which has 8 chunks of memory with each memory chunk - * being 20 bytes large. - * - \code - MEMB(cmem, 20, 8); - - int main(int argc, char *argv[]) { - char *ptr; - - memb_init(&cmem); - - ptr = memb_alloc(&cmem); - - if(ptr != NULL) { - do_something(ptr); - } else { - printf("Could not allocate memory.\n"); - } - - if(memb_free(ptr) == 0) { - printf("Deallocation succeeded.\n"); - } - } - \endcode - * - */ - -#include - -#include "memb.h" - -/*------------------------------------------------------------------------------*/ -/** - * Initialize a memory block that was declared with MEMB(). - * - * \param m A memory block previosly declared with MEMB(). - */ -/*------------------------------------------------------------------------------*/ -void -memb_init(struct memb_blocks *m) -{ - memset(m->mem, (m->size + 1) * m->num, 0); -} -/*------------------------------------------------------------------------------*/ -/** - * Allocate a memory block from a block of memory declared with MEMB(). - * - * \param m A memory block previosly declared with MEMB(). - */ -/*------------------------------------------------------------------------------*/ -char * -memb_alloc(struct memb_blocks *m) -{ - int i; - char *ptr; - - ptr = m->mem; - for(i = 0; i < m->num; ++i) { - if(*ptr == 0) { - /* If this block was unused, we increase the reference count to - indicate that it now is used and return a pointer to the - first byte following the reference counter. */ - ++*ptr; - return ptr + 1; - } - ptr += m->size + 1; - } - - /* No free block was found, so we return NULL to indicate failure to - allocate block. */ - return NULL; -} -/*------------------------------------------------------------------------------*/ -/** - * Deallocate a memory block from a memory block previously declared - * with MEMB(). - * - * \param m m A memory block previosly declared with MEMB(). - * - * \param ptr A pointer to the memory block that is to be deallocated. - * - * \return The new reference count for the memory block (should be 0 - * if successfully deallocated) or -1 if the pointer "ptr" did not - * point to a legal memory block. - */ -/*------------------------------------------------------------------------------*/ -char -memb_free(struct memb_blocks *m, char *ptr) -{ - int i; - char *ptr2; - - /* Walk through the list of blocks and try to find the block to - which the pointer "ptr" points to. */ - ptr2 = m->mem; - for(i = 0; i < m->num; ++i) { - - if(ptr2 == ptr - 1) { - /* We've found to block to which "ptr" points so we decrease the - reference count and return the new value of it. */ - return --*ptr2; - } - ptr2 += m->size + 1; - } - return -1; -} -/*------------------------------------------------------------------------------*/ -/** - * Increase the reference count for a memory chunk. - * - * \note No sanity checks are currently made. - * - * \param m m A memory block previosly declared with MEMB(). - * - * \param ptr A pointer to the memory chunk for which the reference - * count should be increased. - * - * \return The new reference count. - */ -/*------------------------------------------------------------------------------*/ -char -memb_ref(struct memb_blocks *m, char *ptr) -{ - return ++*(ptr - 1); -} -/*------------------------------------------------------------------------------*/ - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h deleted file mode 100644 index 505846f4d..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \file - * Memory block allocation routines. - * \author Adam Dunkels - * - */ - -#ifndef __MEMB_H__ -#define __MEMB_H__ - -/** - * Declare a memory block. - * - * \param name The name of the memory block (later used with - * memb_init(), memb_alloc() and memb_free()). - * - * \param size The size of each memory chunk, in bytes. - * - * \param num The total number of memory chunks in the block. - * - */ -#define MEMB(name, size, num) \ - static char memb_mem[(size + 1) * num]; \ - static struct memb_blocks name = {size, num, memb_mem} - -struct memb_blocks { - unsigned short size; - unsigned short num; - char *mem; -}; - -void memb_init(struct memb_blocks *m); -char *memb_alloc(struct memb_blocks *m); -char memb_ref(struct memb_blocks *m, char *ptr); -char memb_free(struct memb_blocks *m, char *ptr); - - -#endif /* __MEMB_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c deleted file mode 100644 index fc968c82e..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c +++ /dev/null @@ -1,202 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup slip Serial Line IP (SLIP) protocol - * @{ - * - * The SLIP protocol is a very simple way to transmit IP packets over - * a serial line. It does not provide any framing or error control, - * and is therefore not very widely used today. - * - * This SLIP implementation requires two functions for accessing the - * serial device: slipdev_char_poll() and slipdev_char_put(). These - * must be implemented specifically for the system on which the SLIP - * protocol is to be run. - */ - -/** - * \file - * SLIP protocol implementation - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $ - * - */ - -/* - * This is a generic implementation of the SLIP protocol over an RS232 - * (serial) device. - * - * Huge thanks to Ullrich von Bassewitz of cc65 fame for - * and endless supply of bugfixes, insightsful comments and - * suggestions, and improvements to this code! - */ - -#include "uip.h" - -#define SLIP_END 0300 -#define SLIP_ESC 0333 -#define SLIP_ESC_END 0334 -#define SLIP_ESC_ESC 0335 - -static u8_t slip_buf[UIP_BUFSIZE]; - -static u16_t len, tmplen; -static u8_t lastc; - -/*-----------------------------------------------------------------------------------*/ -/** - * Send the packet in the uip_buf and uip_appdata buffers using the - * SLIP protocol. - * - * The first 40 bytes of the packet (the IP and TCP headers) are read - * from the uip_buf buffer, and the following bytes (the application - * data) are read from the uip_appdata buffer. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -slipdev_send(void) -{ - u16_t i; - u8_t *ptr; - u8_t c; - - slipdev_char_put(SLIP_END); - - ptr = uip_buf; - for(i = 0; i < uip_len; ++i) { - if(i == 40) { - ptr = (u8_t *)uip_appdata; - } - c = *ptr++; - switch(c) { - case SLIP_END: - slipdev_char_put(SLIP_ESC); - slipdev_char_put(SLIP_ESC_END); - break; - case SLIP_ESC: - slipdev_char_put(SLIP_ESC); - slipdev_char_put(SLIP_ESC_ESC); - break; - default: - slipdev_char_put(c); - break; - } - } - slipdev_char_put(SLIP_END); -} -/*-----------------------------------------------------------------------------------*/ -/** - * Poll the SLIP device for an available packet. - * - * This function will poll the SLIP device to see if a packet is - * available. It uses a buffer in which all avaliable bytes from the - * RS232 interface are read into. When a full packet has been read - * into the buffer, the packet is copied into the uip_buf buffer and - * the length of the packet is returned. - * - * \return The length of the packet placed in the uip_buf buffer, or - * zero if no packet is available. - */ -/*-----------------------------------------------------------------------------------*/ -u16_t -slipdev_poll(void) -{ - u8_t c; - - while(slipdev_char_poll(c)) { - switch(c) { - case SLIP_ESC: - lastc = c; - break; - - case SLIP_END: - lastc = c; - /* End marker found, we copy our input buffer to the uip_buf - buffer and return the size of the packet we copied. */ - memcpy(uip_buf, slip_buf, len); - tmplen = len; - len = 0; - return tmplen; - - default: - if(lastc == SLIP_ESC) { - lastc = c; - /* Previous read byte was an escape byte, so this byte will be - interpreted differently from others. */ - switch(c) { - case SLIP_ESC_END: - c = SLIP_END; - break; - case SLIP_ESC_ESC: - c = SLIP_ESC; - break; - } - } else { - lastc = c; - } - - slip_buf[len] = c; - ++len; - - if(len > UIP_BUFSIZE) { - len = 0; - } - - break; - } - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the SLIP module. - * - * This function does not initialize the underlying RS232 device, but - * only the SLIP part. - */ -/*-----------------------------------------------------------------------------------*/ -void -slipdev_init(void) -{ - lastc = len = 0; -} -/*-----------------------------------------------------------------------------------*/ - -/** @} */ -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h deleted file mode 100644 index 3fbfe2d2d..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \addtogroup slip - * @{ - */ - -/** - * \file - * SLIP header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $ - * - */ - -#ifndef __SLIPDEV_H__ -#define __SLIPDEV_H__ - -#include "uip.h" - -/** - * Put a character on the serial device. - * - * This function is used by the SLIP implementation to put a character - * on the serial device. It must be implemented specifically for the - * system on which the SLIP implementation is to be run. - * - * \param c The character to be put on the serial device. - */ -void slipdev_char_put(u8_t c); - -/** - * Poll the serial device for a character. - * - * This function is used by the SLIP implementation to poll the serial - * device for a character. It must be implemented specifically for the - * system on which the SLIP implementation is to be run. - * - * The function should return immediately regardless if a character is - * available or not. If a character is available it should be placed - * at the memory location pointed to by the pointer supplied by the - * arguement c. - * - * \param c A pointer to a byte that is filled in by the function with - * the received character, if available. - * - * \retval 0 If no character is available. - * \retval Non-zero If a character is available. - */ -u8_t slipdev_char_poll(u8_t *c); - -void slipdev_init(void); -void slipdev_send(void); -u16_t slipdev_poll(void); - -#endif /* __SLIPDEV_H__ */ - -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c deleted file mode 100644 index 0d23fc4d9..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * Author: Adam Dunkels - * - * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $ - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef linux -#include -#include -#include -#define DEVTAP "/dev/net/tun" -#else /* linux */ -#define DEVTAP "/dev/tap0" -#endif /* linux */ - -#include "uip.h" - -static int fd; - -static unsigned long lasttime; -static struct timezone tz; - -/*-----------------------------------------------------------------------------------*/ -void -tapdev_init(void) -{ - char buf[1024]; - - fd = open(DEVTAP, O_RDWR); - if(fd == -1) { - perror("tapdev: tapdev_init: open"); - exit(1); - } - -#ifdef linux - { - struct ifreq ifr; - memset(&ifr, 0, sizeof(ifr)); - ifr.ifr_flags = IFF_TAP|IFF_NO_PI; - if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) { - perror(buf); - exit(1); - } - } -#endif /* Linux */ - - snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d", - UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3); - system(buf); - - lasttime = 0; -} -/*-----------------------------------------------------------------------------------*/ -unsigned int -tapdev_read(void) -{ - fd_set fdset; - struct timeval tv, now; - int ret; - - if(lasttime >= 500000) { - lasttime = 0; - return 0; - } - - tv.tv_sec = 0; - tv.tv_usec = 500000 - lasttime; - - - FD_ZERO(&fdset); - FD_SET(fd, &fdset); - - gettimeofday(&now, &tz); - ret = select(fd + 1, &fdset, NULL, NULL, &tv); - if(ret == 0) { - lasttime = 0; - return 0; - } - ret = read(fd, uip_buf, UIP_BUFSIZE); - if(ret == -1) { - perror("tap_dev: tapdev_read: read"); - } - gettimeofday(&tv, &tz); - lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec); - - return ret; -} -/*-----------------------------------------------------------------------------------*/ -void -tapdev_send(void) -{ - int ret; - struct iovec iov[2]; - -#ifdef linux - { - char tmpbuf[UIP_BUFSIZE]; - int i; - - for(i = 0; i < 40 + UIP_LLH_LEN; i++) { - tmpbuf[i] = uip_buf[i]; - } - - for(; i < uip_len; i++) { - tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; - } - - ret = write(fd, tmpbuf, uip_len); - } -#else - - if(uip_len < 40 + UIP_LLH_LEN) { - ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN); - } else { - iov[0].iov_base = uip_buf; - iov[0].iov_len = 40 + UIP_LLH_LEN; - iov[1].iov_base = (char *)uip_appdata; - iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); - - ret = writev(fd, iov, 2); - } -#endif - if(ret == -1) { - perror("tap_dev: tapdev_send: writev"); - exit(1); - } -} -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h deleted file mode 100644 index 66f1a4a71..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $ - * - */ - -#ifndef __TAPDEV_H__ -#define __TAPDEV_H__ - -void tapdev_init(void); -unsigned int tapdev_read(void); -void tapdev_send(void); - -#endif /* __TAPDEV_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c deleted file mode 100644 index 7dff714ca..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c +++ /dev/null @@ -1,181 +0,0 @@ -/** - * \addtogroup telnetd - * @{ - */ - -/** - * \file - * An example telnet server shell - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the Contiki desktop OS. - * - * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $ - * - */ - -#include "uip.h" -#include "telnetd.h" -#include - -struct ptentry { - char c; - void (* pfunc)(struct telnetd_state *s, char *str); -}; - -/*-----------------------------------------------------------------------------------*/ -static void -parse(struct telnetd_state *s, register char *str, struct ptentry *t) -{ - register struct ptentry *p; - char *sstr; - - sstr = str; - - /* Loop over the parse table entries in t in order to find one that - matches the first character in str. */ - for(p = t; p->c != 0; ++p) { - if(*str == p->c) { - /* Skip rest of the characters up to the first space. */ - while(*str != ' ') { - ++str; - } - - /* Skip all spaces.*/ - while(*str == ' ') { - ++str; - } - - /* Call parse table entry function and return. */ - p->pfunc(s, str); - return; - } - } - - /* Did not find matching entry in parse table. We just call the - default handler supplied by the caller and return. */ - p->pfunc(s, str); -} -/*-----------------------------------------------------------------------------------*/ -static void -exitt(struct telnetd_state *s, char *str) -{ - telnetd_close(s); -} -/*-----------------------------------------------------------------------------------*/ -static void -inttostr(register char *str, unsigned int i) -{ - str[0] = '0' + i / 100; - if(str[0] == '0') { - str[0] = ' '; - } - str[1] = '0' + (i / 10) % 10; - if(str[1] == '0') { - str[1] = ' '; - } - str[2] = '0' + i % 10; - str[3] = ' '; - str[4] = 0; -} -/*-----------------------------------------------------------------------------------*/ -static void -stats(struct telnetd_state *s, char *strr) -{ - char str[10]; - - inttostr(str, uip_stat.ip.recv); - telnetd_output(s, "IP packets received ", str); - inttostr(str, uip_stat.ip.sent); - telnetd_output(s, "IP packets sent ", str); - inttostr(str, uip_stat.ip.drop); - telnetd_output(s, "IP packets dropped ", str); - - inttostr(str, uip_stat.icmp.recv); - telnetd_output(s, "ICMP packets received ", str); - inttostr(str, uip_stat.icmp.sent); - telnetd_output(s, "ICMP packets sent ", str); - inttostr(str, uip_stat.icmp.drop); - telnetd_output(s, "ICMP packets dropped ", str); - - inttostr(str, uip_stat.tcp.recv); - telnetd_output(s, "TCP packets received ", str); - inttostr(str, uip_stat.tcp.sent); - telnetd_output(s, "TCP packets sent ", str); - inttostr(str, uip_stat.tcp.drop); - telnetd_output(s, "TCP packets dropped ", str); - inttostr(str, uip_stat.tcp.rexmit); - telnetd_output(s, "TCP packets retransmitted ", str); - inttostr(str, uip_stat.tcp.synrst); - telnetd_output(s, "TCP connection attempts ", str); -} -/*-----------------------------------------------------------------------------------*/ -static void -help(struct telnetd_state *s, char *str) -{ - telnetd_output(s, "Available commands:", ""); - telnetd_output(s, "stats - show uIP statistics", ""); - telnetd_output(s, "exit - exit shell", ""); - telnetd_output(s, "? - show this help", ""); -} -/*-----------------------------------------------------------------------------------*/ -static void -none(struct telnetd_state *s, char *str) -{ - if(strlen(str) > 0) { - telnetd_output(s, "Unknown command", ""); - } -} -/*-----------------------------------------------------------------------------------*/ -static struct ptentry configparsetab[] = - {{'s', stats}, - {'e', exitt}, - {'?', help}, - - /* Default action */ - {0, none}}; -/*-----------------------------------------------------------------------------------*/ -void -telnetd_connected(struct telnetd_state *s) -{ - telnetd_output(s, "uIP command shell", ""); - telnetd_output(s, "Type '?' for help", ""); - telnetd_prompt(s, "uIP-0.9> "); -} -/*-----------------------------------------------------------------------------------*/ -void -telnetd_input(struct telnetd_state *s, char *cmd) -{ - parse(s, cmd, configparsetab); - telnetd_prompt(s, "uIP-0.9> "); -} -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c deleted file mode 100644 index dba522271..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c +++ /dev/null @@ -1,392 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \defgroup telnetd Telnet server - * @{ - * - * The uIP telnet server provides a command based interface to uIP. It - * allows using the "telnet" application to access uIP, and implements - * the required telnet option negotiation. - * - * The code is structured in a way which makes it possible to add - * commands without having to rewrite the main telnet code. The main - * telnet code calls two callback functions, telnetd_connected() and - * telnetd_input(), when a telnet connection has been established and - * when a line of text arrives on a telnet connection. These two - * functions can be implemented in a way which suits the particular - * application or environment in which the uIP system is intended to - * be run. - * - * The uIP distribution contains an example telnet shell - * implementation that provides a basic set of commands. - */ - -/** - * \file - * Implementation of the Telnet server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $ - * - */ - -#include "uip.h" -#include "memb.h" -#include "telnetd.h" -#include - -#define ISO_nl 0x0a -#define ISO_cr 0x0d - -MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES); - -static u8_t i; - -#define STATE_NORMAL 0 -#define STATE_IAC 1 -#define STATE_WILL 2 -#define STATE_WONT 3 -#define STATE_DO 4 -#define STATE_DONT 5 -#define STATE_CLOSE 6 - -#define TELNET_IAC 255 -#define TELNET_WILL 251 -#define TELNET_WONT 252 -#define TELNET_DO 253 -#define TELNET_DONT 254 -/*-----------------------------------------------------------------------------------*/ -static char * -alloc_line(void) -{ - return memb_alloc(&linemem); -} -/*-----------------------------------------------------------------------------------*/ -static void -dealloc_line(char *line) -{ - memb_free(&linemem, line); -} -/*-----------------------------------------------------------------------------------*/ -static void -sendline(struct telnetd_state *s, char *line) -{ - static unsigned int i; - for(i = 0; i < TELNETD_NUMLINES; ++i) { - if(s->lines[i] == NULL) { - s->lines[i] = line; - break; - } - } - if(i == TELNETD_NUMLINES) { - dealloc_line(line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Close a telnet session. - * - * This function can be called from a telnet command in order to close - * the connection. - * - * \param s The connection which is to be closed. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_close(struct telnetd_state *s) -{ - s->state = STATE_CLOSE; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Print a prompt on a telnet connection. - * - * This function can be called by the telnet command shell in order to - * print out a command prompt. - * - * \param s A telnet connection. - * - * \param str The command prompt. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_prompt(struct telnetd_state *s, char *str) -{ - char *line; - line = alloc_line(); - if(line != NULL) { - strncpy(line, str, TELNETD_LINELEN); - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Print out a string on a telnet connection. - * - * This function can be called from a telnet command parser in order - * to print out a string of text on the connection. The two strings - * given as arguments to the function will be concatenated, a carrige - * return and a new line character will be added, and the line is - * sent. - * - * \param s The telnet connection. - * - * \param str1 The first string. - * - * \param str2 The second string. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_output(struct telnetd_state *s, char *str1, char *str2) -{ - static unsigned len; - char *line; - - line = alloc_line(); - if(line != NULL) { - len = strlen(str1); - strncpy(line, str1, TELNETD_LINELEN); - if(len < TELNETD_LINELEN) { - strncpy(line + len, str2, TELNETD_LINELEN - len); - } - len = strlen(line); - if(len < TELNETD_LINELEN - 2) { - line[len] = ISO_cr; - line[len+1] = ISO_nl; - line[len+2] = 0; - } - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the telnet server. - * - * This function will perform the necessary initializations and start - * listening on TCP port 23. - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_init(void) -{ - memb_init(&linemem); - uip_listen(HTONS(23)); -} -/*-----------------------------------------------------------------------------------*/ -static void -acked(struct telnetd_state *s) -{ - dealloc_line(s->lines[0]); - for(i = 1; i < TELNETD_NUMLINES; ++i) { - s->lines[i - 1] = s->lines[i]; - } -} -/*-----------------------------------------------------------------------------------*/ -static void -senddata(struct telnetd_state *s) -{ - if(s->lines[0] != NULL) { - uip_send(s->lines[0], strlen(s->lines[0])); - } -} -/*-----------------------------------------------------------------------------------*/ -static void -getchar(struct telnetd_state *s, u8_t c) -{ - if(c == ISO_cr) { - return; - } - - s->buf[(int)s->bufptr] = c; - if(s->buf[(int)s->bufptr] == ISO_nl || - s->bufptr == sizeof(s->buf) - 1) { - if(s->bufptr > 0) { - s->buf[(int)s->bufptr] = 0; - } - telnetd_input(s, s->buf); - s->bufptr = 0; - } else { - ++s->bufptr; - } -} -/*-----------------------------------------------------------------------------------*/ -static void -sendopt(struct telnetd_state *s, u8_t option, u8_t value) -{ - char *line; - line = alloc_line(); - if(line != NULL) { - line[0] = TELNET_IAC; - line[1] = option; - line[2] = value; - line[3] = 0; - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -static void -newdata(struct telnetd_state *s) -{ - u16_t len; - u8_t c; - - - len = uip_datalen(); - - while(len > 0 && s->bufptr < sizeof(s->buf)) { - c = *uip_appdata; - ++uip_appdata; - --len; - switch(s->state) { - case STATE_IAC: - if(c == TELNET_IAC) { - getchar(s, c); - s->state = STATE_NORMAL; - } else { - switch(c) { - case TELNET_WILL: - s->state = STATE_WILL; - break; - case TELNET_WONT: - s->state = STATE_WONT; - break; - case TELNET_DO: - s->state = STATE_DO; - break; - case TELNET_DONT: - s->state = STATE_DONT; - break; - default: - s->state = STATE_NORMAL; - break; - } - } - break; - case STATE_WILL: - /* Reply with a DONT */ - sendopt(s, TELNET_DONT, c); - s->state = STATE_NORMAL; - break; - - case STATE_WONT: - /* Reply with a DONT */ - sendopt(s, TELNET_DONT, c); - s->state = STATE_NORMAL; - break; - case STATE_DO: - /* Reply with a WONT */ - sendopt(s, TELNET_WONT, c); - s->state = STATE_NORMAL; - break; - case STATE_DONT: - /* Reply with a WONT */ - sendopt(s, TELNET_WONT, c); - s->state = STATE_NORMAL; - break; - case STATE_NORMAL: - if(c == TELNET_IAC) { - s->state = STATE_IAC; - } else { - getchar(s, c); - } - break; - } - - - } - -} -/*-----------------------------------------------------------------------------------*/ -void -telnetd_app(void) -{ - struct telnetd_state *s; - - s = (struct telnetd_state *)uip_conn->appstate; - - if(uip_connected()) { - - for(i = 0; i < TELNETD_NUMLINES; ++i) { - s->lines[i] = NULL; - } - s->bufptr = 0; - s->state = STATE_NORMAL; - - telnetd_connected(s); - senddata(s); - return; - } - - if(s->state == STATE_CLOSE) { - s->state = STATE_NORMAL; - uip_close(); - return; - } - - if(uip_closed()) { - telnetd_output(s, "Connection closed", ""); - } - - - if(uip_aborted()) { - telnetd_output(s, "Connection reset", ""); - } - - if(uip_timedout()) { - telnetd_output(s, "Connection timed out", ""); - } - - if(uip_acked()) { - acked(s); - } - - if(uip_newdata()) { - newdata(s); - } - - if(uip_rexmit() || - uip_newdata() || - uip_acked()) { - senddata(s); - } else if(uip_poll()) { - senddata(s); - } -} -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h deleted file mode 100644 index 254e44ff1..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \addtogroup telnetd - * @{ - */ - -/** - * \file - * Header file for the telnet server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $ - * - */ -#ifndef __TELNETD_H__ -#define __TELNETD_H__ - -#include "uip.h" - -/** - * The maximum length of a telnet line. - * - * \hideinitializer - */ -#define TELNETD_LINELEN 36 - -/** - * The number of output lines being buffered for all telnet - * connections. - * - * \hideinitializer - */ -#define TELNETD_NUMLINES 2 - -/** - * A telnet connection structure. - */ -struct telnetd_state { - char *lines[TELNETD_NUMLINES]; - char buf[TELNETD_LINELEN]; - char bufptr; - u8_t state; -}; - - -/** - * Callback function that is called when a telnet connection has been - * established. - * - * \param s The telnet connection. - */ -void telnetd_connected(struct telnetd_state *s); - -/** - * Callback function that is called when a line of text has arrived on - * a telnet connection. - * - * \param s The telnet connection. - * - * \param cmd The line of text. - */ -void telnetd_input(struct telnetd_state *s, char *cmd); - - -void telnetd_close(struct telnetd_state *s); -void telnetd_output(struct telnetd_state *s, char *s1, char *s2); -void telnetd_prompt(struct telnetd_state *s, char *str); - -void telnetd_app(void); - -#ifndef UIP_APPCALL -#define UIP_APPCALL telnetd_app -#endif - -#ifndef UIP_APPSTATE_SIZE -#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state)) -#endif - -void telnetd_init(void); - - -#endif /* __TELNET_H__ */ - -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c deleted file mode 100644 index fe79b5173..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $ - * - */ - - -#include /* For system(). */ -#include /* For printf(). */ - -#include "FreeRTOS.h" -#include "task.h" - -#undef HTONS - -#include "cs8900a.h" -#include "uip.h" -#include "uip_arp.h" -#include "tapdev.h" -#include "httpd.h" - -static const struct uip_eth_addr ethaddr = {{0x00,0x00,0xe2,0x58,0xb6,0x6b}}; - -#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) -#define uipSHORT_DELAY ( ( TickType_t ) 2 / portTICK_PERIOD_MS ) - -#ifndef NULL -#define NULL (void *)0 -#endif /* NULL */ - -static volatile TickType_t start, current; - -#define RT_CLOCK_SECOND ( configTICK_RATE_HZ / 2 ) - -/*-----------------------------------------------------------------------------------*/ -/** - * \internal - * A real-time clock. - * - * This example main() function uses polling of a real-time clock in - * order to know when the periodic processing should be - * performed. This is implemented using this function - rt_ticks(). In - * this example unix implementation, it simply calls the unix function - * gettimeofday() which returns the current wall clock time. - * - * For a micro-controller, a simple way to implement this function is - * by having a counter that is incremented by a timer interrupt and - * read by this function. - * - * The macro RT_CLOCK_SECOND should be defined as the approximate - * number of ticks that are elapsed during one second. - */ -#define rt_ticks xTaskGetTickCount - -/*-----------------------------------------------------------------------------------*/ -void vuIP_TASK( void *pvParameters ) -{ -u8_t i, arptimer; -u16_t addr[2]; -int z = 3; - - /* Initialize the uIP TCP/IP stack. */ - uip_init(); - uip_arp_init(); - - /* Initialize the device driver. */ - cs8900a_init(); - - /* Initialize the HTTP server. */ - httpd_init(); - - start = rt_ticks(); - arptimer = 0; - - while(1) - { - /* Let the network device driver read an entire IP packet - into the uip_buf. If it returns > 0, there is a packet in the - uip_buf buffer. */ - uip_len = cs8900a_poll(); - - if(uip_len > 0) - { - /* A packet is present in the packet buffer. We call the - appropriate ARP functions depending on what kind of packet we - have received. If the packet is an IP packet, we should call - uip_input() as well. */ - if(BUF->type == htons(UIP_ETHTYPE_IP)) - { - uip_arp_ipin(); - uip_input(); - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if(uip_len > 0) - { - uip_arp_out(); - cs8900a_send(); - } - } - else if(BUF->type == htons(UIP_ETHTYPE_ARP)) - { - uip_arp_arpin(); - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if(uip_len > 0) - { - cs8900a_send(); - } - } - } - else - { - /* The poll function returned 0, so no packet was - received. Instead we check if there is time that we do the - periodic processing. */ - current = rt_ticks(); - - if((u16_t)(current - start) >= (u16_t)RT_CLOCK_SECOND / 2) - { - start = current; - - for(i = 0; i < UIP_CONNS; i++) - { - uip_periodic(i); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - - if(uip_len > 0) - { - uip_arp_out(); - cs8900a_send(); - } - } - - #if UIP_UDP - for(i = 0; i < UIP_UDP_CONNS; i++) - { - uip_udp_periodic(i); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - - if(uip_len > 0) - { - uip_arp_out(); - tapdev_send(); - } - } - #endif /* UIP_UDP */ - - /* Call the ARP timer function every 10 seconds. */ - if(++arptimer == 20) - { - uip_arp_timer(); - arptimer = 0; - } - } - else - { - vTaskDelay( uipSHORT_DELAY ); - } } - } -} -/*-----------------------------------------------------------------------------------*/ - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c deleted file mode 100644 index 3ef7e8d6c..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c +++ /dev/null @@ -1,1509 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \file - * The uIP TCP/IP stack code. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $ - * - */ - -/* -This is a small implementation of the IP and TCP protocols (as well as -some basic ICMP stuff). The implementation couples the IP, TCP and the -application layers very tightly. To keep the size of the compiled code -down, this code also features heavy usage of the goto statement. - -The principle is that we have a small buffer, called the uip_buf, in -which the device driver puts an incoming packet. The TCP/IP stack -parses the headers in the packet, and calls upon the application. If -the remote host has sent data to the application, this data is present -in the uip_buf and the application read the data from there. It is up -to the application to put this data into a byte stream if needed. The -application will not be fed with data that is out of sequence. - -If the application whishes to send data to the peer, it should put its -data into the uip_buf, 40 bytes from the start of the buffer. The -TCP/IP stack will calculate the checksums, and fill in the necessary -header fields and finally send the packet back to the peer. -*/ - -#include "uip.h" -#include "uipopt.h" -#include "uip_arch.h" - -/*-----------------------------------------------------------------------------------*/ -/* Variable definitions. */ - - -/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */ -#if UIP_FIXEDADDR > 0 -const u16_t uip_hostaddr[2] = - {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), - HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; -const u16_t uip_arp_draddr[2] = - {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), - HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; -const u16_t uip_arp_netmask[2] = - {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), - HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; -#else -u16_t uip_hostaddr[2]; -u16_t uip_arp_draddr[2], uip_arp_netmask[2]; -#endif /* UIP_FIXEDADDR */ - -u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains - incoming packets. */ -volatile u8_t *uip_appdata; /* The uip_appdata pointer points to - application data. */ -volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the - application data which is to be sent. */ -#if UIP_URGDATA > 0 -volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to - urgent data (out-of-band data), if - present. */ -volatile u8_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - -volatile u16_t uip_len, uip_slen; - /* The uip_len is either 8 or 16 bits, - depending on the maximum packet - size. */ - -volatile u8_t uip_flags; /* The uip_flags variable is used for - communication between the TCP/IP stack - and the application program. */ -struct uip_conn *uip_conn; /* uip_conn always points to the current - connection. */ - -struct uip_conn uip_conns[UIP_CONNS]; - /* The uip_conns array holds all TCP - connections. */ -u16_t uip_listenports[UIP_LISTENPORTS]; - /* The uip_listenports list all currently - listning ports. */ -#if UIP_UDP -struct uip_udp_conn *uip_udp_conn; -struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - - -static u16_t ipid; /* Ths ipid variable is an increasing - number that is used for the IP ID - field. */ - -static u8_t iss[4]; /* The iss variable is used for the TCP - initial sequence number. */ - -#if UIP_ACTIVE_OPEN -static u16_t lastport; /* Keeps track of the last port used for - a new connection. */ -#endif /* UIP_ACTIVE_OPEN */ - -/* Temporary variables. */ -volatile u8_t uip_acc32[4]; -static u8_t c, opt; -static u16_t tmp16; - -/* Structures and definitions. */ -#define TCP_FIN 0x01 -#define TCP_SYN 0x02 -#define TCP_RST 0x04 -#define TCP_PSH 0x08 -#define TCP_ACK 0x10 -#define TCP_URG 0x20 -#define TCP_CTL 0x3f - -#define ICMP_ECHO_REPLY 0 -#define ICMP_ECHO 8 - -/* Macros. */ -#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0]) -#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) - -#if UIP_STATISTICS == 1 -struct uip_stats uip_stat; -#define UIP_STAT(s) s -#else -#define UIP_STAT(s) -#endif /* UIP_STATISTICS == 1 */ - -#if UIP_LOGGING == 1 -#include -void uip_log(char *msg); -#define UIP_LOG(m) uip_log(m) -#else -#define UIP_LOG(m) -#endif /* UIP_LOGGING == 1 */ - -/*-----------------------------------------------------------------------------------*/ -void -uip_init(void) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - uip_listenports[c] = 0; - } - for(c = 0; c < UIP_CONNS; ++c) { - uip_conns[c].tcpstateflags = CLOSED; - } -#if UIP_ACTIVE_OPEN - lastport = 1024; -#endif /* UIP_ACTIVE_OPEN */ - -#if UIP_UDP - for(c = 0; c < UIP_UDP_CONNS; ++c) { - uip_udp_conns[c].lport = 0; - } -#endif /* UIP_UDP */ - - - /* IPv4 initialization. */ -#if UIP_FIXEDADDR == 0 - uip_hostaddr[0] = uip_hostaddr[1] = 0; -#endif /* UIP_FIXEDADDR */ - -} -/*-----------------------------------------------------------------------------------*/ -#if UIP_ACTIVE_OPEN -struct uip_conn * -uip_connect(u16_t *ripaddr, u16_t rport) -{ - register struct uip_conn *conn, *cconn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - /* Check if this port is already in use, and if so try to find - another one. */ - for(c = 0; c < UIP_CONNS; ++c) { - conn = &uip_conns[c]; - if(conn->tcpstateflags != CLOSED && - conn->lport == htons(lastport)) { - goto again; - } - } - - - conn = 0; - for(c = 0; c < UIP_CONNS; ++c) { - cconn = &uip_conns[c]; - if(cconn->tcpstateflags == CLOSED) { - conn = cconn; - break; - } - if(cconn->tcpstateflags == TIME_WAIT) { - if(conn == 0 || - cconn->timer > uip_conn->timer) { - conn = cconn; - } - } - } - - if(conn == 0) { - return 0; - } - - conn->tcpstateflags = SYN_SENT; - - conn->snd_nxt[0] = iss[0]; - conn->snd_nxt[1] = iss[1]; - conn->snd_nxt[2] = iss[2]; - conn->snd_nxt[3] = iss[3]; - - conn->initialmss = conn->mss = UIP_TCP_MSS; - - conn->len = 1; /* TCP length of the SYN is one. */ - conn->nrtx = 0; - conn->timer = 1; /* Send the SYN next time around. */ - conn->rto = UIP_RTO; - conn->sa = 0; - conn->sv = 16; - conn->lport = htons(lastport); - conn->rport = rport; - conn->ripaddr[0] = ripaddr[0]; - conn->ripaddr[1] = ripaddr[1]; - - return conn; -} -#endif /* UIP_ACTIVE_OPEN */ -/*-----------------------------------------------------------------------------------*/ -#if UIP_UDP -struct uip_udp_conn * -uip_udp_new(u16_t *ripaddr, u16_t rport) -{ - register struct uip_udp_conn *conn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == lastport) { - goto again; - } - } - - - conn = 0; - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == 0) { - conn = &uip_udp_conns[c]; - break; - } - } - - if(conn == 0) { - return 0; - } - - conn->lport = HTONS(lastport); - conn->rport = HTONS(rport); - conn->ripaddr[0] = ripaddr[0]; - conn->ripaddr[1] = ripaddr[1]; - - return conn; -} -#endif /* UIP_UDP */ -/*-----------------------------------------------------------------------------------*/ -void -uip_unlisten(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == port) { - uip_listenports[c] = 0; - return; - } - } -} -/*-----------------------------------------------------------------------------------*/ -void -uip_listen(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == 0) { - uip_listenports[c] = port; - return; - } - } -} -/*-----------------------------------------------------------------------------------*/ -/* XXX: IP fragment reassembly: not well-tested. */ - -#if UIP_REASSEMBLY -#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) -static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; -static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; -static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, - 0x0f, 0x07, 0x03, 0x01}; -static u16_t uip_reasslen; -static u8_t uip_reassflags; -#define UIP_REASS_FLAG_LASTFRAG 0x01 -static u8_t uip_reasstmr; - -#define IP_HLEN 20 -#define IP_MF 0x20 - -static u8_t -uip_reass(void) -{ - u16_t offset, len; - u16_t i; - - /* If ip_reasstmr is zero, no packet is present in the buffer, so we - write the IP header of the fragment into the reassembly - buffer. The timer is updated with the maximum age. */ - if(uip_reasstmr == 0) { - memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN); - uip_reasstmr = UIP_REASS_MAXAGE; - uip_reassflags = 0; - /* Clear the bitmap. */ - memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0); - } - - /* Check if the incoming fragment matches the one currently present - in the reasembly buffer. If so, we proceed with copying the - fragment into the buffer. */ - if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && - BUF->srcipaddr[1] == FBUF->srcipaddr[1] && - BUF->destipaddr[0] == FBUF->destipaddr[0] && - BUF->destipaddr[1] == FBUF->destipaddr[1] && - BUF->ipid[0] == FBUF->ipid[0] && - BUF->ipid[1] == FBUF->ipid[1]) { - - len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; - offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; - - /* If the offset or the offset + fragment length overflows the - reassembly buffer, we discard the entire packet. */ - if(offset > UIP_REASS_BUFSIZE || - offset + len > UIP_REASS_BUFSIZE) { - uip_reasstmr = 0; - goto nullreturn; - } - - /* Copy the fragment into the reassembly buffer, at the right - offset. */ - memcpy(&uip_reassbuf[IP_HLEN + offset], - (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), - len); - - /* Update the bitmap. */ - if(offset / (8 * 8) == (offset + len) / (8 * 8)) { - /* If the two endpoints are in the same byte, we only update - that byte. */ - - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7] & - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } else { - /* If the two endpoints are in different bytes, we update the - bytes in the endpoints and fill the stuff inbetween with - 0xff. */ - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7]; - for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { - uip_reassbitmap[i] = 0xff; - } - uip_reassbitmap[(offset + len) / (8 * 8)] |= - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } - - /* If this fragment has the More Fragments flag set to zero, we - know that this is the last fragment, so we can calculate the - size of the entire packet. We also set the - IP_REASS_FLAG_LASTFRAG flag to indicate that we have received - the final fragment. */ - - if((BUF->ipoffset[0] & IP_MF) == 0) { - uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; - uip_reasslen = offset + len; - } - - /* Finally, we check if we have a full packet in the buffer. We do - this by checking if we have the last fragment and if all bits - in the bitmap are set. */ - if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { - /* Check all bytes up to and including all but the last byte in - the bitmap. */ - for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { - if(uip_reassbitmap[i] != 0xff) { - goto nullreturn; - } - } - /* Check the last byte in the bitmap. It should contain just the - right amount of bits. */ - if(uip_reassbitmap[uip_reasslen / (8 * 8)] != - (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { - goto nullreturn; - } - - /* If we have come this far, we have a full packet in the - buffer, so we allocate a pbuf and copy the packet into it. We - also reset the timer. */ - uip_reasstmr = 0; - memcpy(BUF, FBUF, uip_reasslen); - - /* Pretend to be a "normal" (i.e., not fragmented) IP packet - from now on. */ - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - BUF->len[0] = uip_reasslen >> 8; - BUF->len[1] = uip_reasslen & 0xff; - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - - return uip_reasslen; - } - } - - nullreturn: - return 0; -} -#endif /* UIP_REASSEMBL */ -/*-----------------------------------------------------------------------------------*/ -static void -uip_add_rcv_nxt(u16_t n) -{ - uip_add32(uip_conn->rcv_nxt, n); - uip_conn->rcv_nxt[0] = uip_acc32[0]; - uip_conn->rcv_nxt[1] = uip_acc32[1]; - uip_conn->rcv_nxt[2] = uip_acc32[2]; - uip_conn->rcv_nxt[3] = uip_acc32[3]; -} -/*-----------------------------------------------------------------------------------*/ -void -uip_process(u8_t flag) -{ - register struct uip_conn *uip_connr = uip_conn; - - uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; - - - /* Check if we were invoked because of the perodic timer fireing. */ - if(flag == UIP_TIMER) { -#if UIP_REASSEMBLY - if(uip_reasstmr != 0) { - --uip_reasstmr; - } -#endif /* UIP_REASSEMBLY */ - /* Increase the initial sequence number. */ - if(++iss[3] == 0) { - if(++iss[2] == 0) { - if(++iss[1] == 0) { - ++iss[0]; - } - } - } - uip_len = 0; - if(uip_connr->tcpstateflags == TIME_WAIT || - uip_connr->tcpstateflags == FIN_WAIT_2) { - ++(uip_connr->timer); - if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { - uip_connr->tcpstateflags = CLOSED; - } - } else if(uip_connr->tcpstateflags != CLOSED) { - /* If the connection has outstanding data, we increase the - connection's timer and see if it has reached the RTO value - in which case we retransmit. */ - if(uip_outstanding(uip_connr)) { - if(uip_connr->timer-- == 0) { - if(uip_connr->nrtx == UIP_MAXRTX || - ((uip_connr->tcpstateflags == SYN_SENT || - uip_connr->tcpstateflags == SYN_RCVD) && - uip_connr->nrtx == UIP_MAXSYNRTX)) { - uip_connr->tcpstateflags = CLOSED; - - /* We call UIP_APPCALL() with uip_flags set to - UIP_TIMEDOUT to inform the application that the - connection has timed out. */ - uip_flags = UIP_TIMEDOUT; - UIP_APPCALL(); - - /* We also send a reset packet to the remote host. */ - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - /* Exponential backoff. */ - uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? - 4: - uip_connr->nrtx); - ++(uip_connr->nrtx); - - /* Ok, so we need to retransmit. We do this differently - depending on which state we are in. In ESTABLISHED, we - call upon the application so that it may prepare the - data for the retransmit. In SYN_RCVD, we resend the - SYNACK that we sent earlier and in LAST_ACK we have to - retransmit our FINACK. */ - UIP_STAT(++uip_stat.tcp.rexmit); - switch(uip_connr->tcpstateflags & TS_MASK) { - case SYN_RCVD: - /* In the SYN_RCVD state, we should retransmit our - SYNACK. */ - goto tcp_send_synack; - -#if UIP_ACTIVE_OPEN - case SYN_SENT: - /* In the SYN_SENT state, we retransmit out SYN. */ - BUF->flags = 0; - goto tcp_send_syn; -#endif /* UIP_ACTIVE_OPEN */ - - case ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application - to do the actual retransmit after which we jump into - the code for sending out the packet (the apprexmit - label). */ - uip_len = 0; - uip_slen = 0; - uip_flags = UIP_REXMIT; - UIP_APPCALL(); - goto apprexmit; - - case FIN_WAIT_1: - case CLOSING: - case LAST_ACK: - /* In all these states we should retransmit a FINACK. */ - goto tcp_send_finack; - - } - } - } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) { - /* If there was no need for a retransmission, we poll the - application for new data. */ - uip_len = 0; - uip_slen = 0; - uip_flags = UIP_POLL; - UIP_APPCALL(); - goto appsend; - } - } - goto drop; - } -#if UIP_UDP - if(flag == UIP_UDP_TIMER) { - if(uip_udp_conn->lport != 0) { - uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; - uip_len = uip_slen = 0; - uip_flags = UIP_POLL; - UIP_UDP_APPCALL(); - goto udp_send; - } else { - goto drop; - } - } -#endif - - /* This is where the input processing starts. */ - UIP_STAT(++uip_stat.ip.recv); - - - /* Start of IPv4 input header processing code. */ - - /* Check validity of the IP header. */ - if(BUF->vhl != 0x45) { /* IP version and header length. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.vhlerr); - UIP_LOG("ip: invalid version or header length."); - goto drop; - } - - /* Check the size of the packet. If the size reported to us in - uip_len doesn't match the size reported in the IP header, there - has been a transmission error and we drop the packet. */ - - if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */ - uip_len = (uip_len & 0xff) | (BUF->len[0] << 8); - } - if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */ - uip_len = (uip_len & 0xff00) | BUF->len[1]; - } - - /* Check the fragment flag. */ - if((BUF->ipoffset[0] & 0x3f) != 0 || - BUF->ipoffset[1] != 0) { -#if UIP_REASSEMBLY - uip_len = uip_reass(); - if(uip_len == 0) { - goto drop; - } -#else - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.fragerr); - UIP_LOG("ip: fragment dropped."); - goto drop; -#endif /* UIP_REASSEMBLY */ - } - - /* If we are configured to use ping IP address configuration and - hasn't been assigned an IP address yet, we accept all ICMP - packets. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { - if(BUF->proto == UIP_PROTO_ICMP) { - UIP_LOG("ip: possible ping config packet received."); - goto icmp_input; - } else { - UIP_LOG("ip: packet dropped since no address assigned."); - goto drop; - } - } -#endif /* UIP_PINGADDRCONF */ - - /* Check if the packet is destined for our IP address. */ - if(BUF->destipaddr[0] != uip_hostaddr[0]) { - UIP_STAT(++uip_stat.ip.drop); - UIP_LOG("ip: packet not for us."); - goto drop; - } - if(BUF->destipaddr[1] != uip_hostaddr[1]) { - UIP_STAT(++uip_stat.ip.drop); - UIP_LOG("ip: packet not for us."); - goto drop; - } - -#if 0 - // IP checksum is wrong through Netgear DSL router - if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header - checksum. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.chkerr); - UIP_LOG("ip: bad checksum."); - goto drop; - } -#endif - - if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump - to the tcp_input label. */ - goto tcp_input; - -#if UIP_UDP - if(BUF->proto == UIP_PROTO_UDP) - goto udp_input; -#endif /* UIP_UDP */ - - if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from - here. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.protoerr); - UIP_LOG("ip: neither tcp nor icmp."); - goto drop; - } - - icmp_input: - UIP_STAT(++uip_stat.icmp.recv); - - /* ICMP echo (i.e., ping) processing. This is simple, we only change - the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP - checksum before we return the packet. */ - if(ICMPBUF->type != ICMP_ECHO) { - UIP_STAT(++uip_stat.icmp.drop); - UIP_STAT(++uip_stat.icmp.typeerr); - UIP_LOG("icmp: not icmp echo."); - goto drop; - } - - /* If we are configured to use ping IP address assignment, we use - the destination IP address of this ping packet and assign it to - ourself. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { - uip_hostaddr[0] = BUF->destipaddr[0]; - uip_hostaddr[1] = BUF->destipaddr[1]; - } -#endif /* UIP_PINGADDRCONF */ - - ICMPBUF->type = ICMP_ECHO_REPLY; - - if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; - } else { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); - } - - /* Swap IP addresses. */ - tmp16 = BUF->destipaddr[0]; - BUF->destipaddr[0] = BUF->srcipaddr[0]; - BUF->srcipaddr[0] = tmp16; - tmp16 = BUF->destipaddr[1]; - BUF->destipaddr[1] = BUF->srcipaddr[1]; - BUF->srcipaddr[1] = tmp16; - - UIP_STAT(++uip_stat.icmp.sent); - goto send; - - /* End of IPv4 input header processing code. */ - - -#if UIP_UDP - /* UDP input processing. */ - udp_input: - /* UDP processing is really just a hack. We don't do anything to the - UDP/IP headers, but let the UDP application do all the hard - work. If the application sets uip_slen, it has a packet to - send. */ -#if UIP_UDP_CHECKSUMS - if(uip_udpchksum() != 0xffff) { - UIP_STAT(++uip_stat.udp.drop); - UIP_STAT(++uip_stat.udp.chkerr); - UIP_LOG("udp: bad checksum."); - goto drop; - } -#endif /* UIP_UDP_CHECKSUMS */ - - /* Demultiplex this UDP packet between the UDP "connections". */ - for(uip_udp_conn = &uip_udp_conns[0]; - uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; - ++uip_udp_conn) { - if(uip_udp_conn->lport != 0 && - UDPBUF->destport == uip_udp_conn->lport && - (uip_udp_conn->rport == 0 || - UDPBUF->srcport == uip_udp_conn->rport) && - BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] && - BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) { - goto udp_found; - } - } - goto drop; - - udp_found: - uip_len = uip_len - 28; - uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; - uip_flags = UIP_NEWDATA; - uip_slen = 0; - UIP_UDP_APPCALL(); - udp_send: - if(uip_slen == 0) { - goto drop; - } - uip_len = uip_slen + 28; - - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); - - BUF->proto = UIP_PROTO_UDP; - - UDPBUF->udplen = HTONS(uip_slen + 8); - UDPBUF->udpchksum = 0; -#if UIP_UDP_CHECKSUMS - /* Calculate UDP checksum. */ - UDPBUF->udpchksum = ~(uip_udpchksum()); - if(UDPBUF->udpchksum == 0) { - UDPBUF->udpchksum = 0xffff; - } -#endif /* UIP_UDP_CHECKSUMS */ - - BUF->srcport = uip_udp_conn->lport; - BUF->destport = uip_udp_conn->rport; - - BUF->srcipaddr[0] = uip_hostaddr[0]; - BUF->srcipaddr[1] = uip_hostaddr[1]; - BUF->destipaddr[0] = uip_udp_conn->ripaddr[0]; - BUF->destipaddr[1] = uip_udp_conn->ripaddr[1]; - - uip_appdata = &uip_buf[UIP_LLH_LEN + 40]; - goto ip_send_nolen; -#endif /* UIP_UDP */ - - /* TCP input processing. */ - tcp_input: - UIP_STAT(++uip_stat.tcp.recv); - - /* Start of TCP input header processing code. */ - -#if 1 // FIXME - if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP - checksum. */ - UIP_STAT(++uip_stat.tcp.drop); - UIP_STAT(++uip_stat.tcp.chkerr); - UIP_LOG("tcp: bad checksum."); - goto drop; - } -#endif - - /* Demultiplex this segment. */ - /* First check any active connections. */ - for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) { - if(uip_connr->tcpstateflags != CLOSED && - BUF->destport == uip_connr->lport && - BUF->srcport == uip_connr->rport && - BUF->srcipaddr[0] == uip_connr->ripaddr[0] && - BUF->srcipaddr[1] == uip_connr->ripaddr[1]) { - goto found; - } - } - - /* If we didn't find and active connection that expected the packet, - either this packet is an old duplicate, or this is a SYN packet - destined for a connection in LISTEN. If the SYN flag isn't set, - it is an old packet and we send a RST. */ - if((BUF->flags & TCP_CTL) != TCP_SYN) - goto reset; - - tmp16 = BUF->destport; - /* Next, check listening connections. */ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(tmp16 == uip_listenports[c]) - goto found_listen; - } - - /* No matching connection found, so we send a RST packet. */ - UIP_STAT(++uip_stat.tcp.synrst); - reset: - - /* We do not send resets in response to resets. */ - if(BUF->flags & TCP_RST) - goto drop; - - UIP_STAT(++uip_stat.tcp.rst); - - BUF->flags = TCP_RST | TCP_ACK; - uip_len = 40; - BUF->tcpoffset = 5 << 4; - - /* Flip the seqno and ackno fields in the TCP header. */ - c = BUF->seqno[3]; - BUF->seqno[3] = BUF->ackno[3]; - BUF->ackno[3] = c; - - c = BUF->seqno[2]; - BUF->seqno[2] = BUF->ackno[2]; - BUF->ackno[2] = c; - - c = BUF->seqno[1]; - BUF->seqno[1] = BUF->ackno[1]; - BUF->ackno[1] = c; - - c = BUF->seqno[0]; - BUF->seqno[0] = BUF->ackno[0]; - BUF->ackno[0] = c; - - /* We also have to increase the sequence number we are - acknowledging. If the least significant byte overflowed, we need - to propagate the carry to the other bytes as well. */ - if(++BUF->ackno[3] == 0) { - if(++BUF->ackno[2] == 0) { - if(++BUF->ackno[1] == 0) { - ++BUF->ackno[0]; - } - } - } - - /* Swap port numbers. */ - tmp16 = BUF->srcport; - BUF->srcport = BUF->destport; - BUF->destport = tmp16; - - /* Swap IP addresses. */ - tmp16 = BUF->destipaddr[0]; - BUF->destipaddr[0] = BUF->srcipaddr[0]; - BUF->srcipaddr[0] = tmp16; - tmp16 = BUF->destipaddr[1]; - BUF->destipaddr[1] = BUF->srcipaddr[1]; - BUF->srcipaddr[1] = tmp16; - - - /* And send out the RST packet! */ - goto tcp_send_noconn; - - /* This label will be jumped to if we matched the incoming packet - with a connection in LISTEN. In that case, we should create a new - connection and send a SYNACK in return. */ - found_listen: - /* First we check if there are any connections avaliable. Unused - connections are kept in the same table as used connections, but - unused ones have the tcpstate set to CLOSED. Also, connections in - TIME_WAIT are kept track of and we'll use the oldest one if no - CLOSED connections are found. Thanks to Eddie C. Dost for a very - nice algorithm for the TIME_WAIT search. */ - uip_connr = 0; - for(c = 0; c < UIP_CONNS; ++c) { - if(uip_conns[c].tcpstateflags == CLOSED) { - uip_connr = &uip_conns[c]; - break; - } - if(uip_conns[c].tcpstateflags == TIME_WAIT) { - if(uip_connr == 0 || - uip_conns[c].timer > uip_connr->timer) { - uip_connr = &uip_conns[c]; - } - } - } - - if(uip_connr == 0) { - /* All connections are used already, we drop packet and hope that - the remote end will retransmit the packet at a time when we - have more spare connections. */ - UIP_STAT(++uip_stat.tcp.syndrop); - UIP_LOG("tcp: found no unused connections."); - goto drop; - } - uip_conn = uip_connr; - - /* Fill in the necessary fields for the new connection. */ - uip_connr->rto = uip_connr->timer = UIP_RTO; - uip_connr->sa = 0; - uip_connr->sv = 4; - uip_connr->nrtx = 0; - uip_connr->lport = BUF->destport; - uip_connr->rport = BUF->srcport; - uip_connr->ripaddr[0] = BUF->srcipaddr[0]; - uip_connr->ripaddr[1] = BUF->srcipaddr[1]; - uip_connr->tcpstateflags = SYN_RCVD; - - uip_connr->snd_nxt[0] = iss[0]; - uip_connr->snd_nxt[1] = iss[1]; - uip_connr->snd_nxt[2] = iss[2]; - uip_connr->snd_nxt[3] = iss[3]; - uip_connr->len = 1; - - /* rcv_nxt should be the seqno from the incoming packet + 1. */ - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_add_rcv_nxt(1); - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; - if(opt == 0x00) { - /* End of options. */ - break; - } else if(opt == 0x01) { - ++c; - /* NOP option. */ - } else if(opt == 0x02 && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { - /* An MSS option with the right option length. */ - tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = uip_connr->mss = - tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - - /* Our response will be a SYNACK. */ -#if UIP_ACTIVE_OPEN - tcp_send_synack: - BUF->flags = TCP_ACK; - - tcp_send_syn: - BUF->flags |= TCP_SYN; -#else /* UIP_ACTIVE_OPEN */ - tcp_send_synack: - BUF->flags = TCP_SYN | TCP_ACK; -#endif /* UIP_ACTIVE_OPEN */ - - /* We send out the TCP Maximum Segment Size option with our - SYNACK. */ - BUF->optdata[0] = 2; - BUF->optdata[1] = 4; - BUF->optdata[2] = (UIP_TCP_MSS) / 256; - BUF->optdata[3] = (UIP_TCP_MSS) & 255; - uip_len = 44; - BUF->tcpoffset = 6 << 4; - goto tcp_send; - - /* This label will be jumped to if we found an active connection. */ - found: - uip_conn = uip_connr; - uip_flags = 0; - - /* We do a very naive form of TCP reset processing; we just accept - any RST and kill our connection. We should in fact check if the - sequence number of this reset is wihtin our advertised window - before we accept the reset. */ - if(BUF->flags & TCP_RST) { - uip_connr->tcpstateflags = CLOSED; - UIP_LOG("tcp: got reset, aborting connection."); - uip_flags = UIP_ABORT; - UIP_APPCALL(); - goto drop; - } - /* Calculated the length of the data, if the application has sent - any data to us. */ - c = (BUF->tcpoffset >> 4) << 2; - /* uip_len will contain the length of the actual TCP data. This is - calculated by subtracing the length of the TCP header (in - c) and the length of the IP header (20 bytes). */ - uip_len = uip_len - c - 20; - - /* First, check if the sequence number of the incoming packet is - what we're expecting next. If not, we send out an ACK with the - correct numbers in. */ - if(uip_len > 0 && - (BUF->seqno[0] != uip_connr->rcv_nxt[0] || - BUF->seqno[1] != uip_connr->rcv_nxt[1] || - BUF->seqno[2] != uip_connr->rcv_nxt[2] || - BUF->seqno[3] != uip_connr->rcv_nxt[3])) { - goto tcp_send_ack; - } - - /* Next, check if the incoming segment acknowledges any outstanding - data. If so, we update the sequence number, reset the length of - the outstanding data, calculate RTT estimations, and reset the - retransmission timer. */ - if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { - uip_add32(uip_connr->snd_nxt, uip_connr->len); - if(BUF->ackno[0] == uip_acc32[0] && - BUF->ackno[1] == uip_acc32[1] && - BUF->ackno[2] == uip_acc32[2] && - BUF->ackno[3] == uip_acc32[3]) { - /* Update sequence number. */ - uip_connr->snd_nxt[0] = uip_acc32[0]; - uip_connr->snd_nxt[1] = uip_acc32[1]; - uip_connr->snd_nxt[2] = uip_acc32[2]; - uip_connr->snd_nxt[3] = uip_acc32[3]; - - - /* Do RTT estimation, unless we have done retransmissions. */ - if(uip_connr->nrtx == 0) { - signed char m; - m = uip_connr->rto - uip_connr->timer; - /* This is taken directly from VJs original code in his paper */ - m = m - (uip_connr->sa >> 3); - uip_connr->sa += m; - if(m < 0) { - m = -m; - } - m = m - (uip_connr->sv >> 2); - uip_connr->sv += m; - uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; - - } - /* Set the acknowledged flag. */ - uip_flags = UIP_ACKDATA; - /* Reset the retransmission timer. */ - uip_connr->timer = uip_connr->rto; - } - - } - - /* Do different things depending on in what state the connection is. */ - switch(uip_connr->tcpstateflags & TS_MASK) { - /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not - implemented, since we force the application to close when the - peer sends a FIN (hence the application goes directly from - ESTABLISHED to LAST_ACK). */ - case SYN_RCVD: - /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and - we are waiting for an ACK that acknowledges the data we sent - out the last time. Therefore, we want to have the UIP_ACKDATA - flag set. If so, we enter the ESTABLISHED state. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = ESTABLISHED; - uip_flags = UIP_CONNECTED; - uip_connr->len = 0; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - goto drop; -#if UIP_ACTIVE_OPEN - case SYN_SENT: - /* In SYN_SENT, we wait for a SYNACK that is sent in response to - our SYN. The rcv_nxt is set to sequence number in the SYNACK - plus one, and we send an ACK. We move into the ESTABLISHED - state. */ - if((uip_flags & UIP_ACKDATA) && - BUF->flags == (TCP_SYN | TCP_ACK)) { - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[40 + UIP_LLH_LEN + c]; - if(opt == 0x00) { - /* End of options. */ - break; - } else if(opt == 0x01) { - ++c; - /* NOP option. */ - } else if(opt == 0x02 && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { - /* An MSS option with the right option length. */ - tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = - uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - uip_connr->tcpstateflags = ESTABLISHED; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_add_rcv_nxt(1); - uip_flags = UIP_CONNECTED | UIP_NEWDATA; - uip_connr->len = 0; - uip_len = 0; - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - goto reset; -#endif /* UIP_ACTIVE_OPEN */ - - case ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application to feed - data into the uip_buf. If the UIP_ACKDATA flag is set, the - application should put new data into the buffer, otherwise we are - retransmitting an old segment, and the application should put that - data into the buffer. - - If the incoming packet is a FIN, we should close the connection on - this side as well, and we send out a FIN and enter the LAST_ACK - state. We require that there is no outstanding data; otherwise the - sequence numbers will be screwed up. */ - - if(BUF->flags & TCP_FIN) { - if(uip_outstanding(uip_connr)) { - goto drop; - } - uip_add_rcv_nxt(1 + uip_len); - uip_flags = UIP_CLOSE; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - } - UIP_APPCALL(); - uip_connr->len = 1; - uip_connr->tcpstateflags = LAST_ACK; - uip_connr->nrtx = 0; - tcp_send_finack: - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* Check the URG flag. If this is set, the segment carries urgent - data that we must pass to the application. */ - if(BUF->flags & TCP_URG) { -#if UIP_URGDATA > 0 - uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; - if(uip_urglen > uip_len) { - /* There is more urgent data in the next segment to come. */ - uip_urglen = uip_len; - } - uip_add_rcv_nxt(uip_urglen); - uip_len -= uip_urglen; - uip_urgdata = uip_appdata; - uip_appdata += uip_urglen; - } else { - uip_urglen = 0; -#endif /* UIP_URGDATA > 0 */ - uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1]; - uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; - } - - - /* If uip_len > 0 we have TCP data in the packet, and we flag this - by setting the UIP_NEWDATA flag and update the sequence number - we acknowledge. If the application has stopped the dataflow - using uip_stop(), we must not accept any data packets from the - remote host. */ - if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - - /* Check if the available buffer space advertised by the other end - is smaller than the initial MSS for this connection. If so, we - set the current MSS to the window size to ensure that the - application does not send more data than the other end can - handle. - - If the remote host advertises a zero window, we set the MSS to - the initial MSS so that the application will send an entire MSS - of data. This data will not be acknowledged by the receiver, - and the application will retransmit it. This is called the - "persistent timer" and uses the retransmission mechanim. - */ - tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1]; - if(tmp16 > uip_connr->initialmss || - tmp16 == 0) { - tmp16 = uip_connr->initialmss; - } - uip_connr->mss = tmp16; - - /* If this packet constitutes an ACK for outstanding data (flagged - by the UIP_ACKDATA flag, we should call the application since it - might want to send more data. If the incoming packet had data - from the peer (as flagged by the UIP_NEWDATA flag), the - application must also be notified. - - When the application is called, the global variable uip_len - contains the length of the incoming data. The application can - access the incoming data through the global pointer - uip_appdata, which usually points 40 bytes into the uip_buf - array. - - If the application wishes to send any data, this data should be - put into the uip_appdata and the length of the data should be - put into uip_len. If the application don't have any data to - send, uip_len must be set to 0. */ - if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { - uip_slen = 0; - UIP_APPCALL(); - - appsend: - - if(uip_flags & UIP_ABORT) { - uip_slen = 0; - uip_connr->tcpstateflags = CLOSED; - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - if(uip_flags & UIP_CLOSE) { - uip_slen = 0; - uip_connr->len = 1; - uip_connr->tcpstateflags = FIN_WAIT_1; - uip_connr->nrtx = 0; - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* If uip_slen > 0, the application has data to be sent. */ - if(uip_slen > 0) { - - /* If the connection has acknowledged data, the contents of - the ->len variable should be discarded. */ - if((uip_flags & UIP_ACKDATA) != 0) { - uip_connr->len = 0; - } - - /* If the ->len variable is non-zero the connection has - already data in transit and cannot send anymore right - now. */ - if(uip_connr->len == 0) { - - /* The application cannot send more than what is allowed by - the mss (the minumum of the MSS and the available - window). */ - if(uip_slen > uip_connr->mss) { - uip_slen = uip_connr->mss; - } - - /* Remember how much data we send out now so that we know - when everything has been acknowledged. */ - uip_connr->len = uip_slen; - } else { - - /* If the application already had unacknowledged data, we - make sure that the application does not send (i.e., - retransmit) out more than it previously sent out. */ - uip_slen = uip_connr->len; - } - } else { - uip_connr->len = 0; - } - uip_connr->nrtx = 0; - apprexmit: - uip_appdata = uip_sappdata; - - /* If the application has data to be sent, or if the incoming - packet had new data in it, we must send out a packet. */ - if(uip_slen > 0 && uip_connr->len > 0) { - /* Add the length of the IP and TCP headers. */ - uip_len = uip_connr->len + UIP_TCPIP_HLEN; - /* We always set the ACK flag in response packets. */ - BUF->flags = TCP_ACK | TCP_PSH; - /* Send the packet. */ - goto tcp_send_noopts; - } - /* If there is no data to send, just send out a pure ACK if - there is newdata. */ - if(uip_flags & UIP_NEWDATA) { - uip_len = UIP_TCPIP_HLEN; - BUF->flags = TCP_ACK; - goto tcp_send_noopts; - } - } - goto drop; - case LAST_ACK: - /* We can close this connection if the peer has acknowledged our - FIN. This is indicated by the UIP_ACKDATA flag. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = CLOSED; - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - } - break; - - case FIN_WAIT_1: - /* The application has closed the connection, but the remote host - hasn't closed its end yet. Thus we do nothing but wait for a - FIN from the other side. */ - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - uip_connr->len = 0; - } else { - uip_connr->tcpstateflags = CLOSING; - } - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } else if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = FIN_WAIT_2; - uip_connr->len = 0; - goto drop; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case FIN_WAIT_2: - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case TIME_WAIT: - goto tcp_send_ack; - - case CLOSING: - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - } - } - goto drop; - - - /* We jump here when we are ready to send the packet, and just want - to set the appropriate TCP sequence numbers in the TCP header. */ - tcp_send_ack: - BUF->flags = TCP_ACK; - tcp_send_nodata: - uip_len = 40; - tcp_send_noopts: - BUF->tcpoffset = 5 << 4; - tcp_send: - /* We're done with the input processing. We are now ready to send a - reply. Our job is to fill in all the fields of the TCP and IP - headers before calculating the checksum and finally send the - packet. */ - BUF->ackno[0] = uip_connr->rcv_nxt[0]; - BUF->ackno[1] = uip_connr->rcv_nxt[1]; - BUF->ackno[2] = uip_connr->rcv_nxt[2]; - BUF->ackno[3] = uip_connr->rcv_nxt[3]; - - BUF->seqno[0] = uip_connr->snd_nxt[0]; - BUF->seqno[1] = uip_connr->snd_nxt[1]; - BUF->seqno[2] = uip_connr->snd_nxt[2]; - BUF->seqno[3] = uip_connr->snd_nxt[3]; - - BUF->proto = UIP_PROTO_TCP; - - BUF->srcport = uip_connr->lport; - BUF->destport = uip_connr->rport; - - BUF->srcipaddr[0] = uip_hostaddr[0]; - BUF->srcipaddr[1] = uip_hostaddr[1]; - BUF->destipaddr[0] = uip_connr->ripaddr[0]; - BUF->destipaddr[1] = uip_connr->ripaddr[1]; - - - if(uip_connr->tcpstateflags & UIP_STOPPED) { - /* If the connection has issued uip_stop(), we advertise a zero - window so that the remote host will stop sending data. */ - BUF->wnd[0] = BUF->wnd[1] = 0; - } else { - BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); - BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); - } - - tcp_send_noconn: - - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); - - /* Calculate TCP checksum. */ - BUF->tcpchksum = 0; - BUF->tcpchksum = ~(uip_tcpchksum()); - - ip_send_nolen: - - BUF->vhl = 0x45; - BUF->tos = 0; - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - BUF->ttl = UIP_TTL; - ++ipid; - BUF->ipid[0] = ipid >> 8; - BUF->ipid[1] = ipid & 0xff; - - /* Calculate IP checksum. */ - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - - UIP_STAT(++uip_stat.tcp.sent); - send: - UIP_STAT(++uip_stat.ip.sent); - /* Return and let the caller do the actual transmission. */ - return; - drop: - uip_len = 0; - return; -} -/*-----------------------------------------------------------------------------------*/ -u16_t -htons(u16_t val) -{ - return HTONS(val); -} -/*-----------------------------------------------------------------------------------*/ -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h deleted file mode 100644 index f6367a261..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h +++ /dev/null @@ -1,1060 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \file - * Header file for the uIP TCP/IP stack. - * \author Adam Dunkels - * - * The uIP TCP/IP stack header file contains definitions for a number - * of C macros that are used by uIP programs as well as internal uIP - * structures, TCP/IP header structures and function declarations. - * - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $ - * - */ - -#ifndef __UIP_H__ -#define __UIP_H__ - -#include "uipopt.h" - -/*-----------------------------------------------------------------------------------*/ -/* First, the functions that should be called from the - * system. Initialization, the periodic timer and incoming packets are - * handled by the following three functions. - */ - -/** - * \defgroup uipconffunc uIP configuration functions - * @{ - * - * The uIP configuration functions are used for setting run-time - * parameters in uIP such as IP addresses. - */ - -/** - * Set the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * \param addr A pointer to a 4-byte representation of the IP address. - * - * \hideinitializer - */ -#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \ - uip_hostaddr[1] = addr[1]; } while(0) - -/** - * Get the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the currently configured IP address. - * - * \hideinitializer - */ -#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \ - addr[1] = uip_hostaddr[1]; } while(0) - -/** @} */ - -/** - * \defgroup uipinit uIP initialization functions - * @{ - * - * The uIP initialization functions are used for booting uIP. - */ - -/** - * uIP initialization function. - * - * This function should be called at boot up to initilize the uIP - * TCP/IP stack. - */ -void uip_init(void); - -/** @} */ - -/** - * \defgroup uipdevfunc uIP device driver functions - * @{ - * - * These functions are used by a network device driver for interacting - * with uIP. - */ - -/** - * Process an incoming packet. - * - * This function should be called when the device driver has received - * a packet from the network. The packet from the device driver must - * be present in the uip_buf buffer, and the length of the packet - * should be placed in the uip_len variable. - * - * When the function returns, there may be an outbound packet placed - * in the uip_buf packet buffer. If so, the uip_len variable is set to - * the length of the packet. If no packet is to be sent out, the - * uip_len variable is set to 0. - * - * The usual way of calling the function is presented by the source - * code below. - \code - uip_len = devicedriver_poll(); - if(uip_len > 0) { - uip_input(); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uIP ARP code before calling - * this function: - \code - #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) - uip_len = ethernet_devicedrver_poll(); - if(uip_len > 0) { - if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { - uip_arp_ipin(); - uip_input(); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { - uip_arp_arpin(); - if(uip_len > 0) { - ethernet_devicedriver_send(); - } - } - \endcode - * - * \hideinitializer - */ -#define uip_input() uip_process(UIP_DATA) - -/** - * Periodic processing for a connection identified by its number. - * - * This function does the necessary periodic processing (timers, - * polling) for a uIP TCP conneciton, and should be called when the - * periodic uIP timer goes off. It should be called for every - * connection, regardless of whether they are open of closed. - * - * When the function returns, it may have an outbound packet waiting - * for service in the uIP packet buffer, and if so the uip_len - * variable is set to a value larger than zero. The device driver - * should be called to send out the packet. - * - * The ususal way of calling the function is through a for() loop like - * this: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uip_arp_out() function before - * calling the device driver: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the connection which is to be periodically polled. - * - * \hideinitializer - */ -#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ - uip_process(UIP_TIMER); } while (0) - -/** - * Periodic processing for a connection identified by a pointer to its structure. - * - * Same as uip_periodic() but takes a pointer to the actual uip_conn - * struct instead of an integer as its argument. This function can be - * used to force periodic processing of a specific connection. - * - * \param conn A pointer to the uip_conn struct for the connection to - * be processed. - * - * \hideinitializer - */ -#define uip_periodic_conn(conn) do { uip_conn = conn; \ - uip_process(UIP_TIMER); } while (0) - -#if UIP_UDP -/** - * Periodic processing for a UDP connection identified by its number. - * - * This function is essentially the same as uip_prerioic(), but for - * UDP connections. It is called in a similar fashion as the - * uip_periodic() function: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note As for the uip_periodic() function, special care has to be - * taken when using uIP together with ARP and Ethernet: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the UDP connection to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ - uip_process(UIP_UDP_TIMER); } while (0) - -/** - * Periodic processing for a UDP connection identified by a pointer to - * its structure. - * - * Same as uip_udp_periodic() but takes a pointer to the actual - * uip_conn struct instead of an integer as its argument. This - * function can be used to force periodic processing of a specific - * connection. - * - * \param conn A pointer to the uip_udp_conn struct for the connection - * to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ - uip_process(UIP_UDP_TIMER); } while (0) - - -#endif /* UIP_UDP */ - -/** - * The uIP packet buffer. - * - * The uip_buf array is used to hold incoming and outgoing - * packets. The device driver should place incoming data into this - * buffer. When sending data, the device driver should read the link - * level headers and the TCP/IP headers from this buffer. The size of - * the link level headers is configured by the UIP_LLH_LEN define. - * - * \note The application data need not be placed in this buffer, so - * the device driver must read it from the place pointed to by the - * uip_appdata pointer as illustrated by the following example: - \code - void - devicedriver_send(void) - { - hwsend(&uip_buf[0], UIP_LLH_LEN); - hwsend(&uip_buf[UIP_LLH_LEN], 40); - hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN); - } - \endcode - */ -extern u8_t uip_buf[UIP_BUFSIZE+2] __attribute__ ((aligned (4))); - -/** @} */ - -/*-----------------------------------------------------------------------------------*/ -/* Functions that are used by the uIP application program. Opening and - * closing connections, sending and receiving data, etc. is all - * handled by the functions below. -*/ -/** - * \defgroup uipappfunc uIP application functions - * @{ - * - * Functions used by an application running of top of uIP. - */ - -/** - * Start listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_listen(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_listen(u16_t port); - -/** - * Stop listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_unlisten(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_unlisten(u16_t port); - -/** - * Connect to a remote host using TCP. - * - * This function is used to start a new connection to the specified - * port on the specied host. It allocates a new connection identifier, - * sets the connection to the SYN_SENT state and sets the - * retransmission timer to 0. This will cause a TCP SYN segment to be - * sent out the next time this connection is periodically processed, - * which usually is done within 0.5 seconds after the call to - * uip_connect(). - * - * \note This function is avaliable only if support for active open - * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. - * - * \note Since this function requires the port number to be in network - * byte order, a convertion using HTONS() or htons() is necessary. - * - \code - u16_t ipaddr[2]; - - uip_ipaddr(ipaddr, 192,168,1,2); - uip_connect(ipaddr, HTONS(80)); - \endcode - * - * \param ripaddr A pointer to a 4-byte array representing the IP - * address of the remote hot. - * - * \param port A 16-bit port number in network byte order. - * - * \return A pointer to the uIP connection identifier for the new connection, - * or NULL if no connection could be allocated. - * - */ -struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port); - - - -/** - * \internal - * - * Check if a connection has outstanding (i.e., unacknowledged) data. - * - * \param conn A pointer to the uip_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_outstanding(conn) ((conn)->len) - -/** - * Send data on the current connection. - * - * This function is used to send out a single segment of TCP - * data. Only applications that have been invoked by uIP for event - * processing can send data. - * - * The amount of data that actually is sent out after a call to this - * funcion is determined by the maximum amount of data TCP allows. uIP - * will automatically crop the data so that only the appropriate - * amount of data is sent. The function uip_mss() can be used to query - * uIP for the amount of data that actually will be sent. - * - * \note This function does not guarantee that the sent data will - * arrive at the destination. If the data is lost in the network, the - * application will be invoked with the uip_rexmit() event being - * set. The application will then have to resend the data using this - * function. - * - * \param data A pointer to the data which is to be sent. - * - * \param len The maximum amount of data bytes to be sent. - * - * \hideinitializer - */ -#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0) - -/** - * The length of any incoming data that is currently avaliable (if avaliable) - * in the uip_appdata buffer. - * - * The test function uip_data() must first be used to check if there - * is any data available at all. - * - * \hideinitializer - */ -#define uip_datalen() uip_len - -/** - * The length of any out-of-band data (urgent data) that has arrived - * on the connection. - * - * \note The configuration parameter UIP_URGDATA must be set for this - * function to be enabled. - * - * \hideinitializer - */ -#define uip_urgdatalen() uip_urglen - -/** - * Close the current connection. - * - * This function will close the current connection in a nice way. - * - * \hideinitializer - */ -#define uip_close() (uip_flags = UIP_CLOSE) - -/** - * Abort the current connection. - * - * This function will abort (reset) the current connection, and is - * usually used when an error has occured that prevents using the - * uip_close() function. - * - * \hideinitializer - */ -#define uip_abort() (uip_flags = UIP_ABORT) - -/** - * Tell the sending host to stop sending data. - * - * This function will close our receiver's window so that we stop - * receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) - -/** - * Find out if the current connection has been previously stopped with - * uip_stop(). - * - * \hideinitializer - */ -#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) - -/** - * Restart the current connection, if is has previously been stopped - * with uip_stop(). - * - * This function will open the receiver's window again so that we - * start receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ - uip_conn->tcpstateflags &= ~UIP_STOPPED; \ - } while(0) - - -/* uIP tests that can be made to determine in what state the current - connection is, and what the application function should do. */ - -/** - * Is new incoming data available? - * - * Will reduce to non-zero if there is new data for the application - * present at the uip_appdata pointer. The size of the data is - * avaliable through the uip_len variable. - * - * \hideinitializer - */ -#define uip_newdata() (uip_flags & UIP_NEWDATA) - -/** - * Has previously sent data been acknowledged? - * - * Will reduce to non-zero if the previously sent data has been - * acknowledged by the remote host. This means that the application - * can send new data. - * - * \hideinitializer - */ -#define uip_acked() (uip_flags & UIP_ACKDATA) - -/** - * Has the connection just been connected? - * - * Reduces to non-zero if the current connection has been connected to - * a remote host. This will happen both if the connection has been - * actively opened (with uip_connect()) or passively opened (with - * uip_listen()). - * - * \hideinitializer - */ -#define uip_connected() (uip_flags & UIP_CONNECTED) - -/** - * Has the connection been closed by the other end? - * - * Is non-zero if the connection has been closed by the remote - * host. The application may then do the necessary clean-ups. - * - * \hideinitializer - */ -#define uip_closed() (uip_flags & UIP_CLOSE) - -/** - * Has the connection been aborted by the other end? - * - * Non-zero if the current connection has been aborted (reset) by the - * remote host. - * - * \hideinitializer - */ -#define uip_aborted() (uip_flags & UIP_ABORT) - -/** - * Has the connection timed out? - * - * Non-zero if the current connection has been aborted due to too many - * retransmissions. - * - * \hideinitializer - */ -#define uip_timedout() (uip_flags & UIP_TIMEDOUT) - -/** - * Do we need to retransmit previously data? - * - * Reduces to non-zero if the previously sent data has been lost in - * the network, and the application should retransmit it. The - * application should send the exact same data as it did the last - * time, using the uip_send() function. - * - * \hideinitializer - */ -#define uip_rexmit() (uip_flags & UIP_REXMIT) - -/** - * Is the connection being polled by uIP? - * - * Is non-zero if the reason the application is invoked is that the - * current connection has been idle for a while and should be - * polled. - * - * The polling event can be used for sending data without having to - * wait for the remote host to send data. - * - * \hideinitializer - */ -#define uip_poll() (uip_flags & UIP_POLL) - -/** - * Get the initial maxium segment size (MSS) of the current - * connection. - * - * \hideinitializer - */ -#define uip_initialmss() (uip_conn->initialmss) - -/** - * Get the current maxium segment size that can be sent on the current - * connection. - * - * The current maxiumum segment size that can be sent on the - * connection is computed from the receiver's window and the MSS of - * the connection (which also is available by calling - * uip_initialmss()). - * - * \hideinitializer - */ -#define uip_mss() (uip_conn->mss) - -/** - * Set up a new UDP connection. - * - * \param ripaddr A pointer to a 4-byte structure representing the IP - * address of the remote host. - * - * \param rport The remote port number in network byte order. - * - * \return The uip_udp_conn structure for the new connection or NULL - * if no connection could be allocated. - */ -struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport); - -/** - * Removed a UDP connection. - * - * \param conn A pointer to the uip_udp_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_udp_remove(conn) (conn)->lport = 0 - -/** - * Send a UDP datagram of length len on the current connection. - * - * This function can only be called in response to a UDP event (poll - * or newdata). The data must be present in the uip_buf buffer, at the - * place pointed to by the uip_appdata pointer. - * - * \param len The length of the data in the uip_buf buffer. - * - * \hideinitializer - */ -#define uip_udp_send(len) uip_slen = (len) - -/** @} */ - -/* uIP convenience and converting functions. */ - -/** - * \defgroup uipconvfunc uIP conversion functions - * @{ - * - * These functions can be used for converting between different data - * formats used by uIP. - */ - -/** - * Pack an IP address into a 4-byte array which is used by uIP to - * represent IP addresses. - * - * Example: - \code - u16_t ipaddr[2]; - - uip_ipaddr(&ipaddr, 192,168,1,2); - \endcode - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the IP addres. - * \param addr0 The first octet of the IP address. - * \param addr1 The second octet of the IP address. - * \param addr2 The third octet of the IP address. - * \param addr3 The forth octet of the IP address. - * - * \hideinitializer - */ -#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ - (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \ - (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \ - } while(0) - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This macro is primarily used for converting constants from host - * byte order to network byte order. For converting variables to - * network byte order, use the htons() function instead. - * - * \hideinitializer - */ -#ifndef HTONS -# if BYTE_ORDER == BIG_ENDIAN -# define HTONS(n) (n) -# else /* BYTE_ORDER == BIG_ENDIAN */ -# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8)) -# endif /* BYTE_ORDER == BIG_ENDIAN */ -#endif /* HTONS */ - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This function is primarily used for converting variables from host - * byte order to network byte order. For converting constants to - * network byte order, use the HTONS() macro instead. - */ -#ifndef htons -u16_t htons(u16_t val); -#endif /* htons */ - -/** @} */ - -/** - * Pointer to the application data in the packet buffer. - * - * This pointer points to the application data when the application is - * called. If the application wishes to send data, the application may - * use this space to write the data into before calling uip_send(). - */ -extern volatile u8_t *uip_appdata; -extern volatile u8_t *uip_sappdata; - -#if UIP_URGDATA > 0 -/* u8_t *uip_urgdata: - * - * This pointer points to any urgent data that has been received. Only - * present if compiled with support for urgent data (UIP_URGDATA). - */ -extern volatile u8_t *uip_urgdata; -#endif /* UIP_URGDATA > 0 */ - - -/* u[8|16]_t uip_len: - * - * When the application is called, uip_len contains the length of any - * new data that has been received from the remote host. The - * application should set this variable to the size of any data that - * the application wishes to send. When the network device driver - * output function is called, uip_len should contain the length of the - * outgoing packet. - */ -extern volatile u16_t uip_len, uip_slen; - -#if UIP_URGDATA > 0 -extern volatile u8_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - - -/** - * Representation of a uIP TCP connection. - * - * The uip_conn structure is used for identifying a connection. All - * but one field in the structure are to be considered read-only by an - * application. The only exception is the appstate field whos purpose - * is to let the application store application-specific state (e.g., - * file pointers) for the connection. The size of this field is - * configured in the "uipopt.h" header file. - */ -struct uip_conn { - u16_t ripaddr[2]; /**< The IP address of the remote host. */ - - u16_t lport; /**< The local TCP port, in network byte order. */ - u16_t rport; /**< The local remote TCP port, in network byte - order. */ - - u8_t rcv_nxt[4]; /**< The sequence number that we expect to - receive next. */ - u8_t snd_nxt[4]; /**< The sequence number that was last sent by - us. */ - u16_t len; /**< Length of the data that was previously sent. */ - u16_t mss; /**< Current maximum segment size for the - connection. */ - u16_t initialmss; /**< Initial maximum segment size for the - connection. */ - u8_t sa; /**< Retransmission time-out calculation state - variable. */ - u8_t sv; /**< Retransmission time-out calculation state - variable. */ - u8_t rto; /**< Retransmission time-out. */ - u8_t tcpstateflags; /**< TCP state and flags. */ - u8_t timer; /**< The retransmission timer. */ - u8_t nrtx; /**< The number of retransmissions for the last - segment sent. */ - - /** The application state. */ - u8_t appstate[UIP_APPSTATE_SIZE]; -}; - - -/* Pointer to the current connection. */ -extern struct uip_conn *uip_conn; -/* The array containing all uIP connections. */ -extern struct uip_conn uip_conns[UIP_CONNS]; -/** - * \addtogroup uiparch - * @{ - */ - -/** - * 4-byte array used for the 32-bit sequence number calculations. - */ -extern volatile u8_t uip_acc32[4]; - -/** @} */ - - -#if UIP_UDP -/** - * Representation of a uIP UDP connection. - */ -struct uip_udp_conn { - u16_t ripaddr[2]; /**< The IP address of the remote peer. */ - u16_t lport; /**< The local port number in network byte order. */ - u16_t rport; /**< The remote port number in network byte order. */ -}; - -extern struct uip_udp_conn *uip_udp_conn; -extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - -/** - * The structure holding the TCP/IP statistics that are gathered if - * UIP_STATISTICS is set to 1. - * - */ -struct uip_stats { - struct { - uip_stats_t drop; /**< Number of dropped packets at the IP - layer. */ - uip_stats_t recv; /**< Number of received packets at the IP - layer. */ - uip_stats_t sent; /**< Number of sent packets at the IP - layer. */ - uip_stats_t vhlerr; /**< Number of packets dropped due to wrong - IP version or header length. */ - uip_stats_t hblenerr; /**< Number of packets dropped due to wrong - IP length, high byte. */ - uip_stats_t lblenerr; /**< Number of packets dropped due to wrong - IP length, low byte. */ - uip_stats_t fragerr; /**< Number of packets dropped since they - were IP fragments. */ - uip_stats_t chkerr; /**< Number of packets dropped due to IP - checksum errors. */ - uip_stats_t protoerr; /**< Number of packets dropped since they - were neither ICMP, UDP nor TCP. */ - } ip; /**< IP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped ICMP packets. */ - uip_stats_t recv; /**< Number of received ICMP packets. */ - uip_stats_t sent; /**< Number of sent ICMP packets. */ - uip_stats_t typeerr; /**< Number of ICMP packets with a wrong - type. */ - } icmp; /**< ICMP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped TCP segments. */ - uip_stats_t recv; /**< Number of recived TCP segments. */ - uip_stats_t sent; /**< Number of sent TCP segments. */ - uip_stats_t chkerr; /**< Number of TCP segments with a bad - checksum. */ - uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK - number. */ - uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ - uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ - uip_stats_t syndrop; /**< Number of dropped SYNs due to too few - connections was avaliable. */ - uip_stats_t synrst; /**< Number of SYNs for closed ports, - triggering a RST. */ - } tcp; /**< TCP statistics. */ -}; - -/** - * The uIP TCP/IP statistics. - * - * This is the variable in which the uIP TCP/IP statistics are gathered. - */ -extern struct uip_stats uip_stat; - - -/*-----------------------------------------------------------------------------------*/ -/* All the stuff below this point is internal to uIP and should not be - * used directly by an application or by a device driver. - */ -/*-----------------------------------------------------------------------------------*/ -/* u8_t uip_flags: - * - * When the application is called, uip_flags will contain the flags - * that are defined in this file. Please read below for more - * infomation. - */ -extern volatile u8_t uip_flags; - -/* The following flags may be set in the global variable uip_flags - before calling the application callback. The UIP_ACKDATA and - UIP_NEWDATA flags may both be set at the same time, whereas the - others are mutualy exclusive. Note that these flags should *NOT* be - accessed directly, but through the uIP functions/macros. */ - -#define UIP_ACKDATA 1 /* Signifies that the outstanding data was - acked and the application should send - out new data instead of retransmitting - the last data. */ -#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent - us new data. */ -#define UIP_REXMIT 4 /* Tells the application to retransmit the - data that was last sent. */ -#define UIP_POLL 8 /* Used for polling the application, to - check if the application has data that - it wants to send. */ -#define UIP_CLOSE 16 /* The remote host has closed the - connection, thus the connection has - gone away. Or the application signals - that it wants to close the - connection. */ -#define UIP_ABORT 32 /* The remote host has aborted the - connection, thus the connection has - gone away. Or the application signals - that it wants to abort the - connection. */ -#define UIP_CONNECTED 64 /* We have got a connection from a remote - host and have set up a new connection - for it, or an active connection has - been successfully established. */ - -#define UIP_TIMEDOUT 128 /* The connection has been aborted due to - too many retransmissions. */ - - -/* uip_process(flag): - * - * The actual uIP function which does all the work. - */ -void uip_process(u8_t flag); - -/* The following flags are passed as an argument to the uip_process() - function. They are used to distinguish between the two cases where - uip_process() is called. It can be called either because we have - incoming data that should be processed, or because the periodic - timer has fired. */ - -#define UIP_DATA 1 /* Tells uIP that there is incoming data in - the uip_buf buffer. The length of the - data is stored in the global variable - uip_len. */ -#define UIP_TIMER 2 /* Tells uIP that the periodic timer has - fired. */ -#if UIP_UDP -#define UIP_UDP_TIMER 3 -#endif /* UIP_UDP */ - -/* The TCP states used in the uip_conn->tcpstateflags. */ -#define CLOSED 0 -#define SYN_RCVD 1 -#define SYN_SENT 2 -#define ESTABLISHED 3 -#define FIN_WAIT_1 4 -#define FIN_WAIT_2 5 -#define CLOSING 6 -#define TIME_WAIT 7 -#define LAST_ACK 8 -#define TS_MASK 15 - -#define UIP_STOPPED 16 - -#define UIP_TCPIP_HLEN 40 - -/* The TCP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - - /* TCP header. */ - u16_t srcport, - destport; - u8_t seqno[4], - ackno[4], - tcpoffset, - flags, - wnd[2]; - u16_t tcpchksum; - u8_t urgp[2]; - u8_t optdata[4]; -} uip_tcpip_hdr; - -/* The ICMP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - /* ICMP (echo) header. */ - u8_t type, icode; - u16_t icmpchksum; - u16_t id, seqno; -} uip_icmpip_hdr; - - -/* The UDP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - - /* UDP header. */ - u16_t srcport, - destport; - u16_t udplen; - u16_t udpchksum; -} uip_udpip_hdr; - -#define UIP_PROTO_ICMP 1 -#define UIP_PROTO_TCP 6 -#define UIP_PROTO_UDP 17 - -#if UIP_FIXEDADDR -extern const u16_t uip_hostaddr[2]; -#else /* UIP_FIXEDADDR */ -extern u16_t uip_hostaddr[2]; -#endif /* UIP_FIXEDADDR */ - -#endif /* __UIP_H__ */ - - -/** @} */ - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c deleted file mode 100644 index 4cd08c3c7..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $ - * - */ - - -#include "uip.h" -#include "uip_arch.h" -#include <__cross_studio_io.h> - -#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define IP_PROTO_TCP 6 - -/*-----------------------------------------------------------------------------------*/ -void -uip_add32(u8_t *op32, u16_t op16) -{ - - uip_acc32[3] = op32[3] + (op16 & 0xff); - uip_acc32[2] = op32[2] + (op16 >> 8); - uip_acc32[1] = op32[1]; - uip_acc32[0] = op32[0]; - - if(uip_acc32[2] < (op16 >> 8)) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - - - if(uip_acc32[3] < (op16 & 0xff)) { - ++uip_acc32[2]; - if(uip_acc32[2] == 0) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - } -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_chksum(u16_t *sdata, u16_t len) -{ - u16_t acc; - - for (acc = 0; len > 1; len -= 2) { - u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8); - if ((acc += u) < u) { - /* Overflow, so we add the carry to acc (i.e., increase by - one). */ - ++acc; - } - ++sdata; - } - - /* add up any odd byte */ - if(len == 1) { - acc += htons(((u16_t)(*(u8_t *)sdata)) << 8); - if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) { - ++acc; - } - } - - return acc; -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_ipchksum(void) -{ - return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20); -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_tcpchksum(void) -{ - u16_t hsum, sum; - - - /* Compute the checksum of the TCP header. */ - hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20); - - /* Compute the checksum of the data in the TCP packet and add it to - the TCP header checksum. */ - sum = uip_chksum((u16_t *)uip_appdata, - (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40))); - - if((sum += hsum) < hsum) { - ++sum; - } - - if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) { - ++sum; - } - if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) { - ++sum; - } - if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) { - ++sum; - } - if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) { - ++sum; - } - if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) { - ++sum; - } - - hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20); - - if((sum += hsum) < hsum) { - ++sum; - } - - return sum; -} -/*-----------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h deleted file mode 100644 index b2d133f2e..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * \defgroup uiparch Architecture specific uIP functions - * @{ - * - * The functions in the architecture specific module implement the IP - * check sum and 32-bit additions. - * - * The IP checksum calculation is the most computationally expensive - * operation in the TCP/IP stack and it therefore pays off to - * implement this in efficient assembler. The purpose of the uip-arch - * module is to let the checksum functions to be implemented in - * architecture specific assembler. - * - */ - -/** - * \file - * Declarations of architecture specific functions. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $ - * - */ - -#ifndef __UIP_ARCH_H__ -#define __UIP_ARCH_H__ - -#include "uip.h" - -/** - * Carry out a 32-bit addition. - * - * Because not all architectures for which uIP is intended has native - * 32-bit arithmetic, uIP uses an external C function for doing the - * required 32-bit additions in the TCP protocol processing. This - * function should add the two arguments and place the result in the - * global variable uip_acc32. - * - * \note The 32-bit integer pointed to by the op32 parameter and the - * result in the uip_acc32 variable are in network byte order (big - * endian). - * - * \param op32 A pointer to a 4-byte array representing a 32-bit - * integer in network byte order (big endian). - * - * \param op16 A 16-bit integer in host byte order. - */ -void uip_add32(u8_t *op32, u16_t op16); - -/** - * Calculate the Internet checksum over a buffer. - * - * The Internet checksum is the one's complement of the one's - * complement sum of all 16-bit words in the buffer. - * - * See RFC1071. - * - * \note This function is not called in the current version of uIP, - * but future versions might make use of it. - * - * \param buf A pointer to the buffer over which the checksum is to be - * computed. - * - * \param len The length of the buffer over which the checksum is to - * be computed. - * - * \return The Internet checksum of the buffer. - */ -u16_t uip_chksum(u16_t *buf, u16_t len); - -/** - * Calculate the IP header checksum of the packet header in uip_buf. - * - * The IP header checksum is the Internet checksum of the 20 bytes of - * the IP header. - * - * \return The IP header checksum of the IP header in the uip_buf - * buffer. - */ -u16_t uip_ipchksum(void); - -/** - * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. - * - * The TCP checksum is the Internet checksum of data contents of the - * TCP segment, and a pseudo-header as defined in RFC793. - * - * \note The uip_appdata pointer that points to the packet data may - * point anywhere in memory, so it is not possible to simply calculate - * the Internet checksum of the contents of the uip_buf buffer. - * - * \return The TCP checksum of the TCP segment in uip_buf and pointed - * to by uip_appdata. - */ -u16_t uip_tcpchksum(void); - -/** @} */ - -#endif /* __UIP_ARCH_H__ */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c deleted file mode 100644 index f2804df95..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c +++ /dev/null @@ -1,427 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup uiparp uIP Address Resolution Protocol - * @{ - * - * The Address Resolution Protocol ARP is used for mapping between IP - * addresses and link level addresses such as the Ethernet MAC - * addresses. ARP uses broadcast queries to ask for the link level - * address of a known IP address and the host which is configured with - * the IP address for which the query was meant, will respond with its - * link level address. - * - * \note This ARP implementation only supports Ethernet. - */ - -/** - * \file - * Implementation of the ARP Address Resolution Protocol. - * \author Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $ - * - */ - - -#include "uip_arp.h" - -#include - -struct arp_hdr { - struct uip_eth_hdr ethhdr; - u16_t hwtype; - u16_t protocol; - u8_t hwlen; - u8_t protolen; - u16_t opcode; - struct uip_eth_addr shwaddr; - u16_t sipaddr[2]; - struct uip_eth_addr dhwaddr; - u16_t dipaddr[2]; -}; - -struct ethip_hdr { - struct uip_eth_hdr ethhdr; - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; -}; - -#define ARP_REQUEST 1 -#define ARP_REPLY 2 - -#define ARP_HWTYPE_ETH 1 - -struct arp_entry { - u16_t ipaddr[2]; - struct uip_eth_addr ethaddr; - u8_t time; -}; - -struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, - UIP_ETHADDR1, - UIP_ETHADDR2, - UIP_ETHADDR3, - UIP_ETHADDR4, - UIP_ETHADDR5}}; - -static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; -static u16_t ipaddr[2]; -static u8_t i, c; - -static u8_t arptime; -static u8_t tmpage; - -#define BUF ((struct arp_hdr *)&uip_buf[0]) -#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the ARP module. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_init(void) -{ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - memset(arp_table[i].ipaddr, 0, 4); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Periodic ARP processing function. - * - * This function performs periodic timer processing in the ARP module - * and should be called at regular intervals. The recommended interval - * is 10 seconds between the calls. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_timer(void) -{ - struct arp_entry *tabptr; - - ++arptime; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && - arptime - tabptr->time >= UIP_ARP_MAXAGE) { - memset(tabptr->ipaddr, 0, 4); - } - } - -} -/*-----------------------------------------------------------------------------------*/ -static void -uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) -{ - register struct arp_entry *tabptr; - /* Walk through the ARP mapping table and try to find an entry to - update. If none is found, the IP -> MAC address mapping is - inserted in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - - tabptr = &arp_table[i]; - /* Only check those entries that are actually in use. */ - if(tabptr->ipaddr[0] != 0 && - tabptr->ipaddr[1] != 0) { - - /* Check if the source IP address of the incoming packet matches - the IP address in this ARP table entry. */ - if(ipaddr[0] == tabptr->ipaddr[0] && - ipaddr[1] == tabptr->ipaddr[1]) { - - /* An old entry found, update this and return. */ - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; - - return; - } - } - } - - /* If we get here, no existing ARP table entry was found, so we - create one. */ - - /* First, we try to find an unused entry in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(tabptr->ipaddr[0] == 0 && - tabptr->ipaddr[1] == 0) { - break; - } - } - - /* If no unused entry is found, we try to find the oldest entry and - throw it away. */ - if(i == UIP_ARPTAB_SIZE) { - tmpage = 0; - c = 0; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(arptime - tabptr->time > tmpage) { - tmpage = arptime - tabptr->time; - c = i; - } - } - i = c; - } - - /* Now, i is the ARP table entry which we will fill with the new - information. */ - memcpy(tabptr->ipaddr, ipaddr, 4); - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; -} -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming IP packets - * - * This function should be called by the device driver when an IP - * packet has been received. The function will check if the address is - * in the ARP cache, and if so the ARP cache entry will be - * refreshed. If no ARP cache entry was found, a new one is created. - * - * This function expects an IP packet with a prepended Ethernet header - * in the uip_buf[] buffer, and the length of the packet in the global - * variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_ipin(void) -{ - uip_len -= sizeof(struct uip_eth_hdr); - - /* Only insert/update an entry if the source IP address of the - incoming IP packet comes from a host on the local network. */ - if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) != - (uip_hostaddr[0] & uip_arp_netmask[0])) { - return; - } - if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) != - (uip_hostaddr[1] & uip_arp_netmask[1])) { - return; - } - uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); - - return; -} -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming ARP packets. - * - * This function should be called by the device driver when an ARP - * packet has been received. The function will act differently - * depending on the ARP packet type: if it is a reply for a request - * that we previously sent out, the ARP cache will be filled in with - * the values from the ARP reply. If the incoming ARP packet is an ARP - * request for our IP address, an ARP reply packet is created and put - * into the uip_buf[] buffer. - * - * When the function returns, the value of the global variable uip_len - * indicates whether the device driver should send out a packet or - * not. If uip_len is zero, no packet should be sent. If uip_len is - * non-zero, it contains the length of the outbound packet that is - * present in the uip_buf[] buffer. - * - * This function expects an ARP packet with a prepended Ethernet - * header in the uip_buf[] buffer, and the length of the packet in the - * global variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -typedef struct arp_hdr aht; - -void -uip_arp_arpin(void) -{ - int ul; - - if(uip_len < sizeof(struct arp_hdr)) { - uip_len = 0; - return; - } - - uip_len = 0; - - switch(BUF->opcode) { - case HTONS(ARP_REQUEST): - /* ARP request. If it asked for our address, we send out a - reply. */ - if(BUF->dipaddr[0] == uip_hostaddr[0] && - BUF->dipaddr[1] == uip_hostaddr[1]) { - /* The reply opcode is 2. */ - BUF->opcode = HTONS(2); - - memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); - - BUF->dipaddr[0] = BUF->sipaddr[0]; - BUF->dipaddr[1] = BUF->sipaddr[1]; - BUF->sipaddr[0] = uip_hostaddr[0]; - BUF->sipaddr[1] = uip_hostaddr[1]; - - ul = BUF->hwlen; - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - uip_len = sizeof(struct arp_hdr); - } - break; - case HTONS(ARP_REPLY): - /* ARP reply. We insert or update the ARP table if it was meant - for us. */ - if(BUF->dipaddr[0] == uip_hostaddr[0] && - BUF->dipaddr[1] == uip_hostaddr[1]) { - - uip_arp_update(BUF->sipaddr, &BUF->shwaddr); - } - break; - } - - return; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Prepend Ethernet header to an outbound IP packet and see if we need - * to send out an ARP request. - * - * This function should be called before sending out an IP packet. The - * function checks the destination IP address of the IP packet to see - * what Ethernet MAC address that should be used as a destination MAC - * address on the Ethernet. - * - * If the destination IP address is in the local network (determined - * by logical ANDing of netmask and our IP address), the function - * checks the ARP cache to see if an entry for the destination IP - * address is found. If so, an Ethernet header is prepended and the - * function returns. If no ARP cache entry is found for the - * destination IP address, the packet in the uip_buf[] is replaced by - * an ARP request packet for the IP address. The IP packet is dropped - * and it is assumed that they higher level protocols (e.g., TCP) - * eventually will retransmit the dropped packet. - * - * If the destination IP address is not on the local network, the IP - * address of the default router is used instead. - * - * When the function returns, a packet is present in the uip_buf[] - * buffer, and the length of the packet is in the global variable - * uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_out(void) -{ - struct arp_entry *tabptr; - /* Find the destination IP address in the ARP table and construct - the Ethernet header. If the destination IP addres isn't on the - local network, we use the default router's IP address instead. - - If not ARP table entry is found, we overwrite the original IP - packet with an ARP request for the IP address. */ - - /* Check if the destination address is on the local network. */ - if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) != - (uip_hostaddr[0] & uip_arp_netmask[0]) || - (IPBUF->destipaddr[1] & uip_arp_netmask[1]) != - (uip_hostaddr[1] & uip_arp_netmask[1])) { - /* Destination address was not on the local network, so we need to - use the default router's IP address instead of the destination - address when determining the MAC address. */ - ipaddr[0] = uip_arp_draddr[0]; - ipaddr[1] = uip_arp_draddr[1]; - } else { - /* Else, we use the destination IP address. */ - ipaddr[0] = IPBUF->destipaddr[0]; - ipaddr[1] = IPBUF->destipaddr[1]; - } - - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(ipaddr[0] == tabptr->ipaddr[0] && - ipaddr[1] == tabptr->ipaddr[1]) - break; - } - - if(i == UIP_ARPTAB_SIZE) { - /* The destination address was not in our ARP table, so we - overwrite the IP packet with an ARP request. */ - - memset(BUF->ethhdr.dest.addr, 0xff, 6); - memset(BUF->dhwaddr.addr, 0x00, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - - BUF->dipaddr[0] = ipaddr[0]; - BUF->dipaddr[1] = ipaddr[1]; - BUF->sipaddr[0] = uip_hostaddr[0]; - BUF->sipaddr[1] = uip_hostaddr[1]; - BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ - BUF->hwtype = HTONS(ARP_HWTYPE_ETH); - BUF->protocol = HTONS(UIP_ETHTYPE_IP); - BUF->hwlen = 6; - BUF->protolen = 4; - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - - uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; - - uip_len = sizeof(struct arp_hdr); - return; - } - - /* Build an ethernet header. */ - memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); - memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - - IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); - - uip_len += sizeof(struct uip_eth_hdr); -} -/*-----------------------------------------------------------------------------------*/ - -/** @} */ -/** @} */ diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h deleted file mode 100644 index bf9049888..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \addtogroup uiparp - * @{ - */ - -/** - * \file - * Macros and definitions for the ARP module. - * \author Adam Dunkels - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $ - * - */ - -#ifndef __UIP_ARP_H__ -#define __UIP_ARP_H__ - -#include "uip.h" - - -/** - * Representation of a 48-bit Ethernet address. - */ -struct uip_eth_addr { - u8_t addr[6]; -} __attribute__ ((packed, aligned (1))); - -extern struct uip_eth_addr uip_ethaddr; - -/** - * The Ethernet header. - */ -struct uip_eth_hdr { - struct uip_eth_addr dest; - struct uip_eth_addr src; - u16_t type; -} __attribute__ ((packed)); - -#define UIP_ETHTYPE_ARP 0x0806 -#define UIP_ETHTYPE_IP 0x0800 -#define UIP_ETHTYPE_IP6 0x86dd - - -/* The uip_arp_init() function must be called before any of the other - ARP functions. */ -void uip_arp_init(void); - -/* The uip_arp_ipin() function should be called whenever an IP packet - arrives from the Ethernet. This function refreshes the ARP table or - inserts a new mapping if none exists. The function assumes that an - IP packet with an Ethernet header is present in the uip_buf buffer - and that the length of the packet is in the uip_len variable. */ -void uip_arp_ipin(void); - -/* The uip_arp_arpin() should be called when an ARP packet is received - by the Ethernet driver. This function also assumes that the - Ethernet frame is present in the uip_buf buffer. When the - uip_arp_arpin() function returns, the contents of the uip_buf - buffer should be sent out on the Ethernet if the uip_len variable - is > 0. */ -void uip_arp_arpin(void); - -/* The uip_arp_out() function should be called when an IP packet - should be sent out on the Ethernet. This function creates an - Ethernet header before the IP header in the uip_buf buffer. The - Ethernet header will have the correct Ethernet MAC destination - address filled in if an ARP table entry for the destination IP - address (or the IP address of the default router) is present. If no - such table entry is found, the IP packet is overwritten with an ARP - request and we rely on TCP to retransmit the packet that was - overwritten. In any case, the uip_len variable holds the length of - the Ethernet frame that should be transmitted. */ -void uip_arp_out(void); - -/* The uip_arp_timer() function should be called every ten seconds. It - is responsible for flushing old entries in the ARP table. */ -void uip_arp_timer(void); - -/** @} */ - -/** - * \addtogroup uipconffunc - * @{ - */ - -/** - * Set the default router's IP address. - * - * \param addr A pointer to a 4-byte array containing the IP address - * of the default router. - * - * \hideinitializer - */ -#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \ - uip_arp_draddr[1] = addr[1]; } while(0) - -/** - * Set the netmask. - * - * \param addr A pointer to a 4-byte array containing the IP address - * of the netmask. - * - * \hideinitializer - */ -#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \ - uip_arp_netmask[1] = addr[1]; } while(0) - - -/** - * Get the default router's IP address. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the IP address of the default router. - * - * \hideinitializer - */ -#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \ - addr[1] = uip_arp_draddr[1]; } while(0) - -/** - * Get the netmask. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the value of the netmask. - * - * \hideinitializer - */ -#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \ - addr[1] = uip_arp_netmask[1]; } while(0) - - -/** - * Specifiy the Ethernet MAC address. - * - * The ARP code needs to know the MAC address of the Ethernet card in - * order to be able to respond to ARP queries and to generate working - * Ethernet headers. - * - * \note This macro only specifies the Ethernet MAC address to the ARP - * code. It cannot be used to change the MAC address of the Ethernet - * card. - * - * \param eaddr A pointer to a struct uip_eth_addr containing the - * Ethernet MAC address of the Ethernet card. - * - * \hideinitializer - */ -#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ - uip_ethaddr.addr[1] = eaddr.addr[1];\ - uip_ethaddr.addr[2] = eaddr.addr[2];\ - uip_ethaddr.addr[3] = eaddr.addr[3];\ - uip_ethaddr.addr[4] = eaddr.addr[4];\ - uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) - -/** @} */ - -/** - * \internal Internal variables that are set using the macros - * uip_setdraddr and uip_setnetmask. - */ -extern u16_t uip_arp_draddr[2], uip_arp_netmask[2]; -#endif /* __UIP_ARP_H__ */ - - diff --git a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h b/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h deleted file mode 100644 index 9d274d534..000000000 --- a/FreeRTOS/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h +++ /dev/null @@ -1,602 +0,0 @@ -/** - * \defgroup uipopt Configuration options for uIP - * @{ - * - * uIP is configured using the per-project configuration file - * "uipopt.h". This file contains all compile-time options for uIP and - * should be tweaked to match each specific project. The uIP - * distribution contains a documented example "uipopt.h" that can be - * copied and modified for each project. - */ - -/** - * \file - * Configuration options for uIP. - * \author Adam Dunkels - * - * This file is used for tweaking various configuration options for - * uIP. You should make a copy of this file into one of your project's - * directories instead of editing this example "uipopt.h" file that - * comes with the uIP distribution. - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $ - * - */ - -#ifndef __UIPOPT_H__ -#define __UIPOPT_H__ - -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipopttypedef uIP type definitions - * @{ - */ - -/** - * The 8-bit unsigned data type. - * - * This may have to be tweaked for your particular compiler. "unsigned - * char" works for most compilers. - */ -typedef unsigned char u8_t; - -/** - * The 16-bit unsigned data type. - * - * This may have to be tweaked for your particular compiler. "unsigned - * short" works for most compilers. - */ -typedef unsigned short u16_t; - -/** - * The statistics data type. - * - * This datatype determines how high the statistics counters are able - * to count. - */ -typedef unsigned short uip_stats_t; - -/** @} */ - -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptstaticconf Static configuration options - * @{ - * - * These configuration options can be used for setting the IP address - * settings statically, but only if UIP_FIXEDADDR is set to 1. The - * configuration options for a specific node includes IP address, - * netmask and default router as well as the Ethernet address. The - * netmask, default router and Ethernet address are appliciable only - * if uIP should be run over Ethernet. - * - * All of these should be changed to suit your project. -*/ - -/** - * Determines if uIP should use a fixed IP address or not. - * - * If uIP should use a fixed IP address, the settings are set in the - * uipopt.h file. If not, the macros uip_sethostaddr(), - * uip_setdraddr() and uip_setnetmask() should be used instead. - * - * \hideinitializer - */ -#define UIP_FIXEDADDR 1 - -/** - * Ping IP address asignment. - * - * uIP uses a "ping" packets for setting its own IP address if this - * option is set. If so, uIP will start with an empty IP address and - * the destination IP address of the first incoming "ping" (ICMP echo) - * packet will be used for setting the hosts IP address. - * - * \note This works only if UIP_FIXEDADDR is 0. - * - * \hideinitializer - */ -#define UIP_PINGADDRCONF 0 - -#if 0 -#define UIP_IPADDR0 172U /**< The first octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR1 25U /**< The second octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR2 218U /**< The third octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR3 202U /**< The fourth octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_NETMASK0 255 /**< The first octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK1 255 /**< The second octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK2 255 /**< The third octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - - -#define UIP_DRIPADDR0 192 /**< The first octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR1 168 /**< The second octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR2 0 /**< The third octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR3 1 /**< The fourth octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#else - -#define UIP_IPADDR0 172U /**< The first octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR1 25U /**< The second octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR2 218U /**< The third octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR3 202U /**< The fourth octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_NETMASK0 255 /**< The first octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK1 255 /**< The second octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK2 255 /**< The third octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_DRIPADDR0 172 /**< The first octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR1 25 /**< The second octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR2 218 /**< The third octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR3 3 /**< The fourth octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#endif - -/** - * Specifies if the uIP ARP module should be compiled with a fixed - * Ethernet MAC address or not. - * - * If this configuration option is 0, the macro uip_setethaddr() can - * be used to specify the Ethernet address at run-time. - * - * \hideinitializer - */ -#define UIP_FIXEDETHADDR 0 - -#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR4 0x05 /**< The fifth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR5 0x71 /**< The sixth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptip IP configuration options - * @{ - * - */ -/** - * The IP TTL (time to live) of IP packets sent by uIP. - * - * This should normally not be changed. - */ -#define UIP_TTL 255 - -/** - * Turn on support for IP packet reassembly. - * - * uIP supports reassembly of fragmented IP packets. This features - * requires an additonal amount of RAM to hold the reassembly buffer - * and the reassembly code size is approximately 700 bytes. The - * reassembly buffer is of the same size as the uip_buf buffer - * (configured by UIP_BUFSIZE). - * - * \note IP packet reassembly is not heavily tested. - * - * \hideinitializer - */ -#define UIP_REASSEMBLY 0 - -/** - * The maximum time an IP fragment should wait in the reassembly - * buffer before it is dropped. - * - */ -#define UIP_REASS_MAXAGE 40 - -/** @} */ - -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptudp UDP configuration options - * @{ - * - * \note The UDP support in uIP is still not entirely complete; there - * is no support for sending or receiving broadcast or multicast - * packets, but it works well enough to support a number of vital - * applications such as DNS queries, though - */ - -/** - * Toggles wether UDP support should be compiled in or not. - * - * \hideinitializer - */ -#define UIP_UDP 0 - -/** - * Toggles if UDP checksums should be used or not. - * - * \note Support for UDP checksums is currently not included in uIP, - * so this option has no function. - * - * \hideinitializer - */ -#define UIP_UDP_CHECKSUMS 0 - -/** - * The maximum amount of concurrent UDP connections. - * - * \hideinitializer - */ -#define UIP_UDP_CONNS 2 - -/** - * The name of the function that should be called when UDP datagrams arrive. - * - * \hideinitializer - */ -#define UIP_UDP_APPCALL udp_appcall - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipopttcp TCP configuration options - * @{ - */ - -/** - * Determines if support for opening connections from uIP should be - * compiled in. - * - * If the applications that are running on top of uIP for this project - * do not need to open outgoing TCP connections, this configration - * option can be turned off to reduce the code size of uIP. - * - * \hideinitializer - */ -#define UIP_ACTIVE_OPEN 1 - -/** - * The maximum number of simultaneously open TCP connections. - * - * Since the TCP connections are statically allocated, turning this - * configuration knob down results in less RAM used. Each TCP - * connection requires approximatly 30 bytes of memory. - * - * \hideinitializer - */ -#define UIP_CONNS 20 - -/** - * The maximum number of simultaneously listening TCP ports. - * - * Each listening TCP port requires 2 bytes of memory. - * - * \hideinitializer - */ -#define UIP_LISTENPORTS 10 - -/** - * The size of the advertised receiver's window. - * - * Should be set low (i.e., to the size of the uip_buf buffer) is the - * application is slow to process incoming data, or high (32768 bytes) - * if the application processes data quickly. - * - * \hideinitializer - */ -#define UIP_RECEIVE_WINDOW 32768 - -/** - * Determines if support for TCP urgent data notification should be - * compiled in. - * - * Urgent data (out-of-band data) is a rarely used TCP feature that - * very seldom would be required. - * - * \hideinitializer - */ -#define UIP_URGDATA 1 - -/** - * The initial retransmission timeout counted in timer pulses. - * - * This should not be changed. - */ -#define UIP_RTO 3 - -/** - * The maximum number of times a segment should be retransmitted - * before the connection should be aborted. - * - * This should not be changed. - */ -#define UIP_MAXRTX 8 - -/** - * The maximum number of times a SYN segment should be retransmitted - * before a connection request should be deemed to have been - * unsuccessful. - * - * This should not need to be changed. - */ -#define UIP_MAXSYNRTX 3 - -/** - * The TCP maximum segment size. - * - * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40. - */ -#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40) - -/** - * How long a connection should stay in the TIME_WAIT state. - * - * This configiration option has no real implication, and it should be - * left untouched. - */ -#define UIP_TIME_WAIT_TIMEOUT 120 - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptarp ARP configuration options - * @{ - */ - -/** - * The size of the ARP table. - * - * This option should be set to a larger value if this uIP node will - * have many connections from the local network. - * - * \hideinitializer - */ -#define UIP_ARPTAB_SIZE 8 - -/** - * The maxium age of ARP table entries measured in 10ths of seconds. - * - * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD - * default). - */ -#define UIP_ARP_MAXAGE 120 - -/** @} */ - -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptgeneral General configuration options - * @{ - */ - -/** - * The size of the uIP packet buffer. - * - * The uIP packet buffer should not be smaller than 60 bytes, and does - * not need to be larger than 1500 bytes. Lower size results in lower - * TCP throughput, larger size results in higher TCP throughput. - * - * \hideinitializer - */ -#define UIP_BUFSIZE 2048 - - -/** - * Determines if statistics support should be compiled in. - * - * The statistics is useful for debugging and to show the user. - * - * \hideinitializer - */ -#define UIP_STATISTICS 1 - -/** - * Determines if logging of certain events should be compiled in. - * - * This is useful mostly for debugging. The function uip_log() - * must be implemented to suit the architecture of the project, if - * logging is turned on. - * - * \hideinitializer - */ -#define UIP_LOGGING 0 - -/** - * Print out a uIP log message. - * - * This function must be implemented by the module that uses uIP, and - * is called by uIP whenever a log message is generated. - */ -void uip_log(char *msg); - -/** - * The link level header length. - * - * This is the offset into the uip_buf where the IP header can be - * found. For Ethernet, this should be set to 14. For SLIP, this - * should be set to 0. - * - * \hideinitializer - */ -#define UIP_LLH_LEN 14 - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptcpu CPU architecture configuration - * @{ - * - * The CPU architecture configuration is where the endianess of the - * CPU on which uIP is to be run is specified. Most CPUs today are - * little endian, and the most notable exception are the Motorolas - * which are big endian. The BYTE_ORDER macro should be changed to - * reflect the CPU architecture on which uIP is to be run. - */ -#ifndef LITTLE_ENDIAN -#define LITTLE_ENDIAN 3412 -#endif /* LITTLE_ENDIAN */ -#ifndef BIG_ENDIAN -#define BIG_ENDIAN 1234 -#endif /* BIGE_ENDIAN */ - -/** - * The byte order of the CPU architecture on which uIP is to be run. - * - * This option can be either BIG_ENDIAN (Motorola byte order) or - * LITTLE_ENDIAN (Intel byte order). - * - * \hideinitializer - */ -#ifndef BYTE_ORDER -#define BYTE_ORDER LITTLE_ENDIAN -#endif /* BYTE_ORDER */ - -/** @} */ -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptapp Appication specific configurations - * @{ - * - * An uIP application is implemented using a single application - * function that is called by uIP whenever a TCP/IP event occurs. The - * name of this function must be registered with uIP at compile time - * using the UIP_APPCALL definition. - * - * uIP applications can store the application state within the - * uip_conn structure by specifying the size of the application - * structure with the UIP_APPSTATE_SIZE macro. - * - * The file containing the definitions must be included in the - * uipopt.h file. - * - * The following example illustrates how this can look. - \code - -void httpd_appcall(void); -#define UIP_APPCALL httpd_appcall - -struct httpd_state { - u8_t state; - u16_t count; - char *dataptr; - char *script; -}; -#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) - \endcode - */ - -/** - * \var #define UIP_APPCALL - * - * The name of the application function that uIP should call in - * response to TCP/IP events. - * - */ - -/** - * \var #define UIP_APPSTATE_SIZE - * - * The size of the application state that is to be stored in the - * uip_conn structure. - */ -/** @} */ - -/* Include the header file for the application program that should be - used. If you don't use the example web server, you should change - this. */ -#include "httpd.h" - - -#endif /* __UIPOPT_H__ */ -- 2.39.5