From 6f36ad75b3668b423d776bedc22efd6f7651487c Mon Sep 17 00:00:00 2001 From: rtel Date: Fri, 24 Feb 2017 02:12:27 +0000 Subject: [PATCH] Add SimpleLink CC3220SF demo. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2485 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../.ccsproject | 17 + .../.cproject | 195 + .../.launches/RTOSDemo.launch | 29 + .../.project | 178 + .../org.eclipse.cdt.codan.core.prefs | 3 + .../org.eclipse.cdt.debug.core.prefs | 2 + .../FreeRTOSConfig.h | 229 ++ .../Full_Demo/RegTest.asm | 224 ++ .../Full_Demo/main_full.c | 425 ++ .../Simply_Blinky_Demo/main_blinky.c | 301 ++ .../CORTEX_M4_SimpleLink_CC3220SF_CCS/main.c | 288 ++ .../targetConfigs/CC3220SF.ccxml | 14 + .../targetConfigs/readme.txt | 9 + .../ti/boards/CC3220SF_LAUNCHXL/Board.h | 135 + .../CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c | 728 ++++ .../CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h | 199 + .../CC3220SF_LAUNCHXL_FREERTOS.cmd | 75 + .../ti/devices/cc32xx/driverlib/adc.h | 122 + .../ti/devices/cc32xx/driverlib/aes.h | 223 ++ .../ti/devices/cc32xx/driverlib/camera.h | 136 + .../ti/devices/cc32xx/driverlib/cpu.c | 417 ++ .../ti/devices/cc32xx/driverlib/cpu.h | 80 + .../ti/devices/cc32xx/driverlib/crc.h | 103 + .../ti/devices/cc32xx/driverlib/debug.h | 72 + .../ti/devices/cc32xx/driverlib/des.h | 148 + .../ti/devices/cc32xx/driverlib/flash.c | 868 +++++ .../ti/devices/cc32xx/driverlib/flash.h | 120 + .../ti/devices/cc32xx/driverlib/gpio.c | 721 ++++ .../ti/devices/cc32xx/driverlib/gpio.h | 144 + .../ti/devices/cc32xx/driverlib/hwspinlock.c | 274 ++ .../ti/devices/cc32xx/driverlib/hwspinlock.h | 90 + .../ti/devices/cc32xx/driverlib/i2c.h | 366 ++ .../ti/devices/cc32xx/driverlib/i2s.h | 223 ++ .../ti/devices/cc32xx/driverlib/interrupt.c | 774 ++++ .../ti/devices/cc32xx/driverlib/interrupt.h | 125 + .../ti/devices/cc32xx/driverlib/pin.c | 888 +++++ .../ti/devices/cc32xx/driverlib/pin.h | 195 + .../ti/devices/cc32xx/driverlib/prcm.c | 2699 +++++++++++++ .../ti/devices/cc32xx/driverlib/prcm.h | 372 ++ .../ti/devices/cc32xx/driverlib/rom.h | 2797 +++++++++++++ .../ti/devices/cc32xx/driverlib/rom_map.h | 3325 ++++++++++++++++ .../ti/devices/cc32xx/driverlib/rom_patch.h | 115 + .../ti/devices/cc32xx/driverlib/sdhost.h | 209 + .../ti/devices/cc32xx/driverlib/shamd5.h | 125 + .../ti/devices/cc32xx/driverlib/spi.c | 1532 ++++++++ .../ti/devices/cc32xx/driverlib/spi.h | 168 + .../ti/devices/cc32xx/driverlib/systick.c | 280 ++ .../ti/devices/cc32xx/driverlib/systick.h | 83 + .../ti/devices/cc32xx/driverlib/timer.h | 215 + .../ti/devices/cc32xx/driverlib/uart.h | 239 ++ .../ti/devices/cc32xx/driverlib/udma.c | 1261 ++++++ .../ti/devices/cc32xx/driverlib/udma.h | 668 ++++ .../ti/devices/cc32xx/driverlib/utils.c | 109 + .../ti/devices/cc32xx/driverlib/utils.h | 76 + .../ti/devices/cc32xx/driverlib/version.h | 77 + .../ti/devices/cc32xx/driverlib/wdt.h | 87 + .../ti/devices/cc32xx/inc/asmdefs.h | 231 ++ .../ti/devices/cc32xx/inc/hw_adc.h | 890 +++++ .../ti/devices/cc32xx/inc/hw_aes.h | 804 ++++ .../ti/devices/cc32xx/inc/hw_apps_config.h | 749 ++++ .../ti/devices/cc32xx/inc/hw_apps_rcm.h | 1508 +++++++ .../ti/devices/cc32xx/inc/hw_camera.h | 521 +++ .../ti/devices/cc32xx/inc/hw_common_reg.h | 1119 ++++++ .../ti/devices/cc32xx/inc/hw_des.h | 341 ++ .../ti/devices/cc32xx/inc/hw_dthe.h | 394 ++ .../ti/devices/cc32xx/inc/hw_flash_ctrl.h | 1864 +++++++++ .../ti/devices/cc32xx/inc/hw_gpio.h | 1351 +++++++ .../ti/devices/cc32xx/inc/hw_gprcm.h | 3324 ++++++++++++++++ .../ti/devices/cc32xx/inc/hw_hib1p2.h | 1752 +++++++++ .../ti/devices/cc32xx/inc/hw_hib3p3.h | 1140 ++++++ .../ti/devices/cc32xx/inc/hw_i2c.h | 505 +++ .../ti/devices/cc32xx/inc/hw_ints.h | 119 + .../ti/devices/cc32xx/inc/hw_mcasp.h | 1708 ++++++++ .../ti/devices/cc32xx/inc/hw_mcspi.h | 1747 +++++++++ .../ti/devices/cc32xx/inc/hw_memmap.h | 86 + .../ti/devices/cc32xx/inc/hw_mmchs.h | 1921 +++++++++ .../ti/devices/cc32xx/inc/hw_nvic.h | 1712 ++++++++ .../ti/devices/cc32xx/inc/hw_ocp_shared.h | 3447 +++++++++++++++++ .../ti/devices/cc32xx/inc/hw_shamd5.h | 1244 ++++++ .../ti/devices/cc32xx/inc/hw_stack_die_ctrl.h | 766 ++++ .../ti/devices/cc32xx/inc/hw_timer.h | 780 ++++ .../ti/devices/cc32xx/inc/hw_types.h | 78 + .../ti/devices/cc32xx/inc/hw_uart.h | 419 ++ .../ti/devices/cc32xx/inc/hw_udma.h | 338 ++ .../ti/devices/cc32xx/inc/hw_wdt.h | 133 + .../ti/drivers/ADC.h | 423 ++ .../ti/drivers/ADCBuf.h | 602 +++ .../ti/drivers/Camera.h | 651 ++++ .../ti/drivers/Capture.h | 423 ++ .../ti/drivers/GPIO.h | 496 +++ .../ti/drivers/I2C.h | 812 ++++ .../ti/drivers/I2CSlave.h | 544 +++ .../ti/drivers/I2S.h | 764 ++++ .../ti/drivers/NVS.h | 499 +++ .../ti/drivers/PIN.h | 1058 +++++ .../ti/drivers/PWM.h | 591 +++ .../ti/drivers/Power.h | 578 +++ .../ti/drivers/SD.h | 490 +++ .../ti/drivers/SDFatFS.h | 171 + .../ti/drivers/SDSPI.h | 455 +++ .../ti/drivers/SPI.h | 846 ++++ .../ti/drivers/Timer.h | 437 +++ .../ti/drivers/UART.h | 966 +++++ .../ti/drivers/Watchdog.h | 538 +++ .../ti/drivers/adc/ADCCC32XX.h | 116 + .../ti/drivers/crypto/CryptoCC32XX.h | 512 +++ .../ti/drivers/dma/UDMACC32XX.h | 210 + .../ti/drivers/dpl/ClockP.h | 252 ++ .../ti/drivers/dpl/ClockP_freertos.c | 285 ++ .../ti/drivers/dpl/DebugP.h | 170 + .../ti/drivers/dpl/DebugP_freertos.c | 86 + .../ti/drivers/dpl/FreeRTOS_OSAL_issues.txt | 6 + .../ti/drivers/dpl/HwiP.h | 194 + .../ti/drivers/dpl/HwiPCC32XX_freertos.c | 315 ++ .../ti/drivers/dpl/MutexP.h | 176 + .../ti/drivers/dpl/MutexP_freertos.c | 102 + .../ti/drivers/dpl/PowerCC32XX_freertos.c | 216 ++ .../ti/drivers/dpl/SemaphoreP.h | 202 + .../ti/drivers/dpl/SemaphoreP_freertos.c | 165 + .../ti/drivers/dpl/SystemP.h | 59 + .../ti/drivers/dpl/SystemP_freertos.c | 412 ++ .../ti/drivers/gpio/GPIOCC32XX.c | 691 ++++ .../ti/drivers/gpio/GPIOCC32XX.h | 264 ++ .../ti/drivers/i2c/I2CCC32XX.h | 210 + .../ti/drivers/i2s/I2SCC32XXDMA.h | 309 ++ .../ti/drivers/power/PowerCC32XX.c | 1311 +++++++ .../ti/drivers/power/PowerCC32XX.h | 636 +++ .../ti/drivers/pwm/PWMTimerCC32XX.h | 342 ++ .../ti/drivers/sd/SDHostCC32XX.h | 202 + .../ti/drivers/spi/SPICC32XXDMA.h | 330 ++ .../ti/drivers/uart/UARTCC32XX.h | 352 ++ .../ti/drivers/uart/UARTCC32XXDMA.h | 277 ++ .../ti/drivers/utils/List.c | 200 + .../ti/drivers/utils/List.h | 255 ++ .../ti/drivers/utils/RingBuf.c | 142 + .../ti/drivers/utils/RingBuf.h | 149 + .../ti/drivers/watchdog/WatchdogCC32XX.h | 211 + .../ti/startup_cc32xx_ccs.c | 231 ++ 138 files changed, 75502 insertions(+) create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.ccsproject create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.cproject create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.launches/RTOSDemo.launch create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.project create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.settings/org.eclipse.cdt.debug.core.prefs create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/FreeRTOSConfig.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/RegTest.asm create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/main_full.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Simply_Blinky_Demo/main_blinky.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/main.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/targetConfigs/CC3220SF.ccxml create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/targetConfigs/readme.txt create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/Board.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL_FREERTOS.cmd create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/adc.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/aes.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/camera.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/cpu.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/cpu.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/crc.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/debug.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/des.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/flash.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/flash.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/gpio.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/gpio.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/hwspinlock.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/hwspinlock.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/i2c.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/i2s.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/interrupt.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/interrupt.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/pin.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/pin.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/prcm.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/prcm.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom_map.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom_patch.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/sdhost.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/shamd5.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/spi.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/spi.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/systick.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/systick.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/timer.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/uart.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/udma.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/udma.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/utils.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/utils.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/version.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/wdt.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/asmdefs.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_adc.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_aes.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_apps_config.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_apps_rcm.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_camera.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_common_reg.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_des.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_dthe.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_flash_ctrl.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_gpio.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_gprcm.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_hib1p2.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_hib3p3.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_i2c.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_ints.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mcasp.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mcspi.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_memmap.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mmchs.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_nvic.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_ocp_shared.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_shamd5.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_timer.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_types.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_uart.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_udma.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_wdt.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/ADC.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/ADCBuf.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Camera.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Capture.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/GPIO.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2C.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2CSlave.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2S.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/NVS.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/PIN.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/PWM.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Power.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SD.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SDFatFS.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SDSPI.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SPI.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Timer.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/UART.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Watchdog.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/adc/ADCCC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/crypto/CryptoCC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dma/UDMACC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/ClockP.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/ClockP_freertos.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/DebugP.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/DebugP_freertos.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/FreeRTOS_OSAL_issues.txt create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/HwiP.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/HwiPCC32XX_freertos.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/MutexP.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/MutexP_freertos.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/PowerCC32XX_freertos.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SemaphoreP.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SemaphoreP_freertos.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SystemP.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SystemP_freertos.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/gpio/GPIOCC32XX.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/gpio/GPIOCC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/i2c/I2CCC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/i2s/I2SCC32XXDMA.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/power/PowerCC32XX.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/power/PowerCC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/pwm/PWMTimerCC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/sd/SDHostCC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/spi/SPICC32XXDMA.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/uart/UARTCC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/uart/UARTCC32XXDMA.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/List.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/List.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/RingBuf.c create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/RingBuf.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/watchdog/WatchdogCC32XX.h create mode 100644 FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/startup_cc32xx_ccs.c diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.ccsproject b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.ccsproject new file mode 100644 index 000000000..f67b162c7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.ccsproject @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.cproject b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.cproject new file mode 100644 index 000000000..b37b32c53 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.cproject @@ -0,0 +1,195 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.launches/RTOSDemo.launch b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.launches/RTOSDemo.launch new file mode 100644 index 000000000..a960d9e0e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.launches/RTOSDemo.launch @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.project b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.project new file mode 100644 index 000000000..e4499324e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.project @@ -0,0 +1,178 @@ + + + RTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1486761015159 + FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1486761015165 + FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-CCS + + + + 1487441524146 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1487441524146 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1487441524146 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1487441524146 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1487441524162 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1487441524177 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1487441524177 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1487441524177 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1487441524193 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1487441524193 + Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-StaticAllocation.c + + + + 1486761851868 + FreeRTOS_Source/portable/CCS + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARM_CM3 + + + + 1486761032606 + FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.settings/org.eclipse.cdt.codan.core.prefs b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 000000000..98b635027 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.settings/org.eclipse.cdt.debug.core.prefs b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 000000000..58d4fb29d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/FreeRTOSConfig.h new file mode 100644 index 000000000..cdfdc821a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/FreeRTOSConfig.h @@ -0,0 +1,229 @@ +/* + FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/****************************************************************************** + See http://www.freertos.org/a00110.html for an explanation of the + definitions contained in this file. +******************************************************************************/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. + +The comprehensive demo uses FreeRTOS+CLI to create a simple command line +interface through a UART. + +The blinky demo uses FreeRTOS's tickless idle mode to reduce power consumption. +See the notes on the web page below regarding the difference in power saving +that can be achieved between using the generic tickless implementation (as used +by the blinky demo) and a tickless implementation that is tailored specifically +to the CC3220. + +See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for +instructions. */ +#define configCREATE_SIMPLE_TICKLESS_DEMO 0 + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* Constants related to the behaviour or the scheduler. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configMAX_PRIORITIES ( 5 ) +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */ + +/* Constants used to specify if only static allocation is to be supported (in +which case a heap_n.c file is not required), only dynamic allocation is to be +supported, or if both static and dynamic allocation are supported. */ +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Constants that describe the hardware and memory usage. */ +#define configCPU_CLOCK_HZ ( ( unsigned long ) 80000000 ) +#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 100 ) +#define configMAX_TASK_NAME_LEN ( 12 ) + +/* Note heap_5.c is used so this only defines the part of the heap that is in +the first block of RAM on the LPC device. See the initialisation of the heap +in main.c. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) ) + +/* Constants that build features in or out. */ +#define configUSE_MUTEXES 1 +#define configUSE_TICKLESS_IDLE 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TASK_NOTIFICATIONS 1 + +/* Constants that define which hook (callback) functions should be used. */ +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configUSE_MALLOC_FAILED_HOOK 1 + +/* Constants provided for debugging and optimisation assistance. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 +void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber ); +#define configASSERT( x ) if( ( x ) == 0 ) { vMainAssertCalled( __FILE__, __LINE__ ); } +#define configQUEUE_REGISTRY_SIZE 0 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 3 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is only +necessary if the linker does not automatically remove functions that are not +referenced anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xSemaphoreGetMutexHolder 0 +#define INCLUDE_xTimerPendFunctionCall 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Dimensions a buffer that can be used by the FreeRTOS+CLI command +interpreter. See the FreeRTOS+CLI documentation for more information: +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048 + + +/* Cortex-M3/4 interrupt priority configuration follows...................... */ + +/* Use the system definition, if there is one. */ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 8 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* The trace facility is turned on to make some functions available for use in +CLI commands. */ +#define configUSE_TRACE_FACILITY 1 + +/* Constants related to the generation of run time stats. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#define portGET_RUN_TIME_COUNTER_VALUE() 0 + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/RegTest.asm b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/RegTest.asm new file mode 100644 index 000000000..c7f973ca4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/RegTest.asm @@ -0,0 +1,224 @@ +;/* +; FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd. +; All rights reserved +; +; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. +; +; This file is part of the FreeRTOS distribution. +; +; FreeRTOS is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License (version 2) as published by the +; Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. +; +; *************************************************************************** +; >>! NOTE: The modification to the GPL is included to allow you to !<< +; >>! distribute a combined work that includes FreeRTOS without being !<< +; >>! obliged to provide the source code for proprietary components !<< +; >>! outside of the FreeRTOS kernel. !<< +; *************************************************************************** +; +; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +; FOR A PARTICULAR PURPOSE. Full license text is available on the following +; link: http://www.freertos.org/a00114.html +; +; *************************************************************************** +; * * +; * FreeRTOS provides completely free yet professionally developed, * +; * robust, strictly quality controlled, supported, and cross * +; * platform software that is more than just the market leader, it * +; * is the industry's de facto standard. * +; * * +; * Help yourself get started quickly while simultaneously helping * +; * to support the FreeRTOS project by purchasing a FreeRTOS * +; * tutorial book, reference manual, or both: * +; * http://www.FreeRTOS.org/Documentation * +; * * +; *************************************************************************** +; +; http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading +; the FAQ page "My application does not run, what could be wrong?". Have you +; defined configASSERT()? +; +; http://www.FreeRTOS.org/support - In return for receiving this top quality +; embedded software for free we request you assist our global community by +; participating in the support forum. +; +; http://www.FreeRTOS.org/training - Investing in training allows your team to +; be as productive as possible as early as possible. Now you can receive +; FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers +; Ltd, and the world's leading authority on the world's leading RTOS. +; +; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, +; including FreeRTOS+Trace - an indispensable productivity tool, a DOS +; compatible FAT file system, and our tiny thread aware UDP/IP stack. +; +; http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. +; Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. +; +; http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High +; Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS +; licenses offer ticketed support, indemnification and commercial middleware. +; +; http://www.SafeRTOS.com - High Integrity Systems also provide a safety +; engineered and independently SIL3 certified version for use in safety and +; mission critical applications that require provable dependability. +; +; 1 tab == 4 spaces! +;*/ + + + .thumb + + .ref ulRegTest1LoopCounter + .ref ulRegTest2LoopCounter + + .def vRegTest1Implementation + .def vRegTest2Implementation + +ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter +ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter +ulNVIC_INT_CTRL: .word 0xe000ed04 +;/*-----------------------------------------------------------*/ + .align 4 +vRegTest1Implementation: .asmfunc + + ;/* Fill the core registers with known values. */ + mov r0, #100 + mov r1, #101 + mov r2, #102 + mov r3, #103 + mov r4, #104 + mov r5, #105 + mov r6, #106 + mov r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + +reg1_loop: + + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + ;/* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, ulRegTest1LoopCounterConst + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + ;/* Start again. */ + b reg1_loop + +reg1_error_loop: + ;/* If this line is hit then there was an error in a core register value. + ;The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + .endasmfunc + +;/*-----------------------------------------------------------*/ + + .align 4 +vRegTest2Implementation: .asmfunc + + ;/* Set all the core registers to known values. */ + mov r0, #-1 + mov r1, #1 + mov r2, #2 + mov r3, #3 + mov r4, #4 + mov r5, #5 + mov r6, #6 + mov r7, #7 + mov r8, #8 + mov r9, #9 + mov r10, #10 + mov r11, #11 + mov r12, #12 + + +reg2_loop: + + cmp r0, #-1 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + ;/* Increment the loop counter to indicate this test is still functioning + ;correctly. */ + push { r0-r1 } + ldr r0, ulRegTest2LoopCounterConst + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + ;/* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, ulNVIC_INT_CTRL + lsl r0, r0, #28 ;/* Shift to PendSV bit */ + str r0, [r1] + dsb + + pop { r0-r1 } + + ;/* Start again. */ + b reg2_loop + +reg2_error_loop: + ;/* If this line is hit then there was an error in a core register value. + ;This loop ensures the loop counter variable stops incrementing. */ + b reg2_error_loop + +;/*-----------------------------------------------------------*/ + + .end diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/main_full.c new file mode 100644 index 000000000..d3d0698f1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/main_full.c @@ -0,0 +1,425 @@ +/* + FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * configCREATE_SIMPLE_TICKLESS_DEMO setting in FreeRTOSConfig.h is used to + * select between the two. See the notes on using + * configCREATE_SIMPLY_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + * See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for + * instructions. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill the core registers with known values, then + * check that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "semtest.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "partest.h" +#include "TimerDemo.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" +#include "StaticAllocation.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period of the check task, in ms, provided no errors have been reported by +any of the standard demo tasks. ms are converted to the equivalent in ticks +using the pdMS_TO_TICKS() macro constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 3000UL ) ) + +/* The period of the check task, in ms, if an error has been reported in one of +the standard demo tasks. ms are converted to the equivalent in ticks using the +pdMS_TO_TICKS() macro. */ +#define mainERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 200UL ) ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + + +/* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file, but the + * entry points are kept in the C file for the convenience of checking the task + * parameter. + */ +static void prvRegTestTaskEntry1( void *pvParameters ); +extern void vRegTest1Implementation( void ); +static void prvRegTestTaskEntry2( void *pvParameters ); +extern void vRegTest2Implementation( void ); + +/* + * Register commands that can be used with FreeRTOS+CLI. The commands are + * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively. + */ +extern void vRegisterSampleCLICommands( void ); + +/* + * The task that manages the FreeRTOS+CLI input and output. + */ +extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); + +/* + * When the full demo is build the idle hook is used to create some timers that + * cannot be created in main() because the timer demo tasks need the entire + * command queue. + */ +void vFullDemoIdleHook( void ); + +/* + * Toggles the LED built onto the Launchpad hardware. + */ +extern void vMainToggleLED( void ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + vStartStaticallyAllocatedTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the Idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details on the FreeRTOS heap + http://www.freertos.org/a00111.html. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks to ensure that they are all still running, + and that none have detected an error. */ + if( xAreStaticAllocationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + vMainToggleLED(); + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry1( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check task will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry2( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check task will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +#if( configCREATE_SIMPLE_TICKLESS_DEMO == 0 ) + + void vApplicationTickHook( void ) + { + /* This function will be called by each tick interrupt if + configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + added here, but the tick hook is called from an interrupt context, so + code must not attempt to block, and only the interrupt safe FreeRTOS API + functions can be used (those that end in FromISR()). */ + + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); + } + +#endif +/*-----------------------------------------------------------*/ + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Simply_Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Simply_Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..f153721db --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Simply_Blinky_Demo/main_blinky.c @@ -0,0 +1,301 @@ +/* + FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * configCREATE_SIMPLE_TICKLESS_DEMO setting in FreeRTOSConfig.h is used to + * select between the two. See the notes on using + * configCREATE_SIMPLE_TICKLESS_DEMO in main.c. This file implements the + * simply blinky style version. + * + * The blinky demo uses FreeRTOS's tickless idle mode to reduce power + * consumption. See the notes on the web page below regarding the difference + * in power saving that can be achieved between using the generic tickless + * implementation (as used by the blinky demo) and a tickless implementation + * that is tailored specifically to the CC3220. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + * See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for + * instructions. + * + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles the LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 1000UL ) ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* Values passed to the two tasks just to check the task parameter +functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) + +/*-----------------------------------------------------------*/ + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/* + * Called by main() to create the simply blinky style application if + * configCREATE_SIMPLE_TICKLESS_DEMO is set to 1. + */ +void main_blinky( void ); + +/* + * The full demo configures the clocks for maximum frequency, wheras this blinky + * demo uses a slower clock as it also uses low power features. + */ +static void prvConfigureClocks( void ); + +/* + * Toggles the LED built onto the Launchpad hardware. + */ +extern void vMainToggleLED( void ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for + instructions and notes regarding the difference in power saving that can be + achieved between using the generic tickless RTOS implementation (as used by + the blinky demo) and a tickless RTOS implementation that is tailored + specifically to the MSP432. */ + + /* The full demo configures the clocks for maximum frequency, wheras this + blinky demo uses a slower clock as it also uses low power features. */ + prvConfigureClocks(); + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. + The block time is specified in ticks, the constant used converts ticks + to ms. While in the Blocked state this task will not consume any CPU + time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +static const TickType_t xShortBlock = pdMS_TO_TICKS( 50 ); + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + /* Blip the LED for a short while so as not to use too much + power. */ + vMainToggleLED(); + vTaskDelay( xShortBlock ); + vMainToggleLED(); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvConfigureClocks( void ) +{ +} +/*-----------------------------------------------------------*/ + +void vPreSleepProcessing( uint32_t ulExpectedIdleTime ) +{ +} +/*-----------------------------------------------------------*/ + +#if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 ) + + void vApplicationTickHook( void ) + { + /* This function will be called by each tick interrupt if + configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + added here, but the tick hook is called from an interrupt context, so + code must not attempt to block, and only the interrupt safe FreeRTOS API + functions can be used (those that end in FromISR()). */ + + /* Only the full demo uses the tick hook so there is no code is + executed here. */ + } + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/main.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/main.c new file mode 100644 index 000000000..c9693ef07 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/main.c @@ -0,0 +1,288 @@ +/* + FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * configCREATE_SIMPLE_TICKLESS_DEMO setting (defined in FreeRTOSConfig.h) is + * used to select between the two. The simply blinky demo is implemented and + * described in main_blinky.c. The more comprehensive test and demo application + * is implemented and described in main_full.c. + * + * The blinky demo uses FreeRTOS's tickless idle mode to reduce power + * consumption. See the notes on the web page below regarding the difference + * in power saving that can be achieved between using the generic tickless + * implementation (as used by the blinky demo) and a tickless implementation + * that is tailored specifically to the CC3220. + * + * This file implements the code that is not demo specific. + * + * See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for + * instructions. + * + */ + +/* Standard includes. */ +#include + +/* TI includes. */ +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*-----------------------------------------------------------*/ + +/* + * Set up the hardware ready to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when configCREATE_SIMPLE_TICKLESS_DEMO is set to 1. + * main_full() is used when configCREATE_SIMPLE_TICKLESS_DEMO is set to 0. + */ +extern void main_blinky( void ); +extern void main_full( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for + instructions. */ + + + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top + of this file. */ + #if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Call board init functions */ + Board_initGeneral(); + Board_initGPIO(); + GPIO_write( Board_LED0, Board_GPIO_LED_OFF ); +} +/*-----------------------------------------------------------*/ + +void vMainToggleLED( void ) +{ +static uint32_t ulLEDState = Board_GPIO_LED_OFF; + + ulLEDState = !ulLEDState; + GPIO_write( Board_LED0, ulLEDState ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* vApplicationMallocFailedHook() will only be called if + configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + function that will get called if a call to pvPortMalloc() fails. + pvPortMalloc() is called internally by the kernel whenever a task, queue, + timer or semaphore is created. It is also called by various parts of the + demo application. If heap_1.c or heap_2.c are used, then the size of the + heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + to query the size of free heap space that remains (although it does not + provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + task. It is essential that code added to this hook function never attempts + to block in any way (for example, call xQueueReceive() with a block time + specified, or call vTaskDelay()). If the application makes use of the + vTaskDelete() API function (as this demo application does) then it is also + important that vApplicationIdleHook() is permitted to return to its calling + function, because it is the responsibility of the idle task to clean up + memory allocated by the kernel to any task that has since been deleted. */ +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void *malloc( size_t xSize ) +{ + /* There should not be a heap defined, so trap any attempts to call + malloc. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an +implementation of vApplicationGetIdleTaskMemory() to provide the memory that is +used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) +{ +/* If the buffers to be provided to the Idle task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xIdleTaskTCB; +static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the +application must provide an implementation of vApplicationGetTimerTaskMemory() +to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) +{ +/* If the buffers to be provided to the Timer task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xTimerTaskTCB; +static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} +/*-----------------------------------------------------------*/ + +/* Catch asserts so the file and line number of the assert can be viewed. */ +void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber ) +{ + taskENTER_CRITICAL(); + for( ;; ) + { + /* Use the variables to prevent compiler warnings and in an attempt to + ensure they can be viewed in the debugger. If the variables get + optimised away then set copy their values to file scope or globals then + view the variables they are copied to. */ + ( void ) pcFileName; + ( void ) ulLineNumber; + } +} +/*-----------------------------------------------------------*/ + +/* To enable the libraries to build. */ +void PowerCC32XX_enterLPDS( void *driverlibFunc ) +{ + ( void ) driverlibFunc; + + /* This function is not implemented so trap any calls to it by halting + here. */ + configASSERT( driverlibFunc == NULL ); +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/targetConfigs/CC3220SF.ccxml b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/targetConfigs/CC3220SF.ccxml new file mode 100644 index 000000000..f0194353f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/targetConfigs/CC3220SF.ccxml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/targetConfigs/readme.txt b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/targetConfigs/readme.txt new file mode 100644 index 000000000..af97b62d5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/Board.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/Board.h new file mode 100644 index 000000000..de890c268 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/Board.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOARD_H +#define __BOARD_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "CC3220SF_LAUNCHXL.h" + +#define Board_initGeneral CC3220SF_LAUNCHXL_initGeneral + +#define Board_ADC0 CC3220SF_LAUNCHXL_ADC0 +#define Board_ADC1 CC3220SF_LAUNCHXL_ADC1 + +#define Board_CRYPTO0 CC3220SF_LAUNCHXL_CRYPTO0 + +#define Board_GPIO_LED_ON CC3220SF_LAUNCHXL_GPIO_LED_ON +#define Board_GPIO_LED_OFF CC3220SF_LAUNCHXL_GPIO_LED_OFF +#define Board_GPIO_LED0 CC3220SF_LAUNCHXL_GPIO_LED_D7 +/* + * CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the I2C + * and PWM peripherals. In order for those examples to work, these LEDs are + * taken out of gpioPinCOnfig[] + */ +#define Board_GPIO_LED1 CC3220SF_LAUNCHXL_GPIO_LED_D7 +#define Board_GPIO_LED2 CC3220SF_LAUNCHXL_GPIO_LED_D7 + +#define Board_GPIO_BUTTON0 CC3220SF_LAUNCHXL_GPIO_SW2 +#define Board_GPIO_BUTTON1 CC3220SF_LAUNCHXL_GPIO_SW3 + +#define Board_I2C0 CC3220SF_LAUNCHXL_I2C0 +#define Board_I2C_TMP CC3220SF_LAUNCHXL_I2C0 + +#define Board_I2S0 CC3220SF_LAUNCHXL_I2S0 + +#define Board_PWM0 CC3220SF_LAUNCHXL_PWM6 +#define Board_PWM1 CC3220SF_LAUNCHXL_PWM7 + +#define Board_SDSPI0 CC3220SF_LAUNCHXL_SDSPI0 + +#define Board_SD0 CC3220SF_LAUNCHXL_SD0 + +#define Board_SDFatFS0 CC3220SF_LAUNCHXL_SD0 + +/* CC3220SF_LAUNCHXL_SPI0 is reserved for the NWP */ +#define Board_SPI0 CC3220SF_LAUNCHXL_SPI1 + +#define Board_UART0 CC3220SF_LAUNCHXL_UART0 +#define Board_UART1 CC3220SF_LAUNCHXL_UART1 + +#define Board_WATCHDOG0 CC3220SF_LAUNCHXL_WATCHDOG0 + +/* Board specific I2C addresses */ +#define Board_TMP_ADDR (0x41) +#define Board_SENSORS_BP_TMP_ADDR (0x40) + +/* + * These macros are provided for backwards compatibility. + * Please use the _init functions directly rather + * than Board_init. + */ +#define Board_initADC ADC_init +#define Board_initGPIO GPIO_init +#define Board_initI2C I2C_init +#define Board_initI2S I2S_init +#define Board_initPWM PWM_init +#define Board_initSDSPI SDSPI_init +#define Board_initSD SD_init +#define Board_initSDFatFS SDFatFS_init +#define Board_initSPI SPI_init +#define Board_initUART UART_init +#define Board_initWatchdog Watchdog_init + +/* + * These macros are provided for backwards compatibility. + * Please use the corresponding 'Board_GPIO_xxx' macros as the macros + * below are deprecated. + */ +#define Board_LED_ON Board_GPIO_LED_ON +#define Board_LED_OFF Board_GPIO_LED_OFF +#define Board_LED0 Board_GPIO_LED0 +#define Board_LED1 Board_GPIO_LED1 +#define Board_LED2 Board_GPIO_LED2 +#define Board_BUTTON0 Board_GPIO_BUTTON0 +#define Board_BUTTON1 Board_GPIO_BUTTON1 +#define Board_TMP006_ADDR Board_TMP_ADDR + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c new file mode 100644 index 000000000..ccff7f0c9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c @@ -0,0 +1,728 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== CC3220SF_LAUNCHXL.c ======== + * This file is responsible for setting up the board specific items for the + * CC3220SF_LAUNCHXL board. + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "CC3220SF_LAUNCHXL.h" + +/* + * This define determines whether to use the UARTCC32XXDMA driver + * or the UARTCC32XX (no DMA) driver. Set to 1 to use the UARTCC32XXDMA + * driver. + */ +#ifndef TI_DRIVERS_UART_DMA +#define TI_DRIVERS_UART_DMA 0 +#endif + +/* + * =============================== ADC =============================== + */ +#include +#include + +ADCCC32XX_Object adcCC3220SObjects[CC3220SF_LAUNCHXL_ADCCOUNT]; + +const ADCCC32XX_HWAttrsV1 adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADCCOUNT] = { + { + .adcPin = ADCCC32XX_PIN_59_CH_2 + }, + { + .adcPin = ADCCC32XX_PIN_60_CH_3 + } +}; + +const ADC_Config ADC_config[CC3220SF_LAUNCHXL_ADCCOUNT] = { + { + .fxnTablePtr = &ADCCC32XX_fxnTable, + .object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC0], + .hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC0] + }, + { + .fxnTablePtr = &ADCCC32XX_fxnTable, + .object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC1], + .hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC1] + } +}; + +const uint_least8_t ADC_count = CC3220SF_LAUNCHXL_ADCCOUNT; + +/* + * =============================== Crypto =============================== + */ +#include + +CryptoCC32XX_Object cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTOCOUNT]; + +const CryptoCC32XX_Config CryptoCC32XX_config[CC3220SF_LAUNCHXL_CRYPTOCOUNT] = { + { + .object = &cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTO0] + } +}; + +const uint_least8_t CryptoCC32XX_count = CC3220SF_LAUNCHXL_CRYPTOCOUNT; + +/* + * =============================== DMA =============================== + */ +#include + +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_ALIGN(dmaControlTable, 1024) +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_alignment=1024 +#elif defined(__GNUC__) +__attribute__ ((aligned (1024))) +#endif +static tDMAControlTable dmaControlTable[64]; + +/* + * ======== dmaErrorFxn ======== + * This is the handler for the uDMA error interrupt. + */ +static void dmaErrorFxn(uintptr_t arg) +{ + int status = MAP_uDMAErrorStatusGet(); + MAP_uDMAErrorStatusClear(); + + /* Suppress unused variable warning */ + (void)status; + + while (1); +} + +UDMACC32XX_Object udmaCC3220SObject; + +const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = { + .controlBaseAddr = (void *)dmaControlTable, + .dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn, + .intNum = INT_UDMAERR, + .intPriority = (~0) +}; + +const UDMACC32XX_Config UDMACC32XX_config = { + .object = &udmaCC3220SObject, + .hwAttrs = &udmaCC3220SHWAttrs +}; + +/* + * =============================== General =============================== + */ +/* + * ======== CC3220SF_LAUNCHXL_initGeneral ======== + */ +void CC3220SF_LAUNCHXL_initGeneral(void) +{ + PRCMCC3200MCUInit(); + Power_init(); +} + +/* + * =============================== GPIO =============================== + */ +#include +#include + +/* + * Array of Pin configurations + * NOTE: The order of the pin configurations must coincide with what was + * defined in CC3220SF_LAUNCHXL.h + * NOTE: Pins not used for interrupts should be placed at the end of the + * array. Callback entries can be omitted from callbacks array to + * reduce memory usage. + */ +GPIO_PinConfig gpioPinConfigs[] = { + /* input pins with callbacks */ + /* CC3220SF_LAUNCHXL_GPIO_SW2 */ + GPIOCC32XX_GPIO_22 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, + /* CC3220SF_LAUNCHXL_GPIO_SW3 */ + GPIOCC32XX_GPIO_13 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, + + /* output pins */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D7 */ + GPIOCC32XX_GPIO_09 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + + /* + * CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the + * I2C and PWM peripherals. In order for those examples to work, these + * LEDs are taken out of gpioPinCOnfig[] + */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D6 */ + //GPIOCC32XX_GPIO_10 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + /* CC3220SF_LAUNCHXL_GPIO_LED_D5 */ + //GPIOCC32XX_GPIO_11 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, +}; + +/* + * Array of callback function pointers + * NOTE: The order of the pin configurations must coincide with what was + * defined in CC3220SF_LAUNCHXL.h + * NOTE: Pins not used for interrupts can be omitted from callbacks array to + * reduce memory usage (if placed at end of gpioPinConfigs array). + */ +GPIO_CallbackFxn gpioCallbackFunctions[] = { + NULL, /* CC3220SF_LAUNCHXL_GPIO_SW2 */ + NULL /* CC3220SF_LAUNCHXL_GPIO_SW3 */ +}; + +/* The device-specific GPIO_config structure */ +const GPIOCC32XX_Config GPIOCC32XX_config = { + .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + .intPriority = (~0) +}; + +/* + * ============================= Display ============================= + */ +#if 0 /*_RB_*/ +#include +#include +#define MAXPRINTLEN 1024 + +DisplayUart_Object displayUartObject; + +static char displayBuf[MAXPRINTLEN]; + +const DisplayUart_HWAttrs displayUartHWAttrs = { + .uartIdx = 0, + .baudRate = 115200, + .mutexTimeout = (unsigned int)(-1), + .strBuf = displayBuf, + .strBufLen = MAXPRINTLEN +}; + +#ifndef BOARD_DISPLAY_USE_UART_ANSI +#define BOARD_DISPLAY_USE_UART_ANSI 0 +#endif + +const Display_Config Display_config[] = { + { +# if (BOARD_DISPLAY_USE_UART_ANSI) + .fxnTablePtr = &DisplayUartAnsi_fxnTable, +# else /* Default to minimal UART with no cursor placement */ + .fxnTablePtr = &DisplayUartMin_fxnTable, +# endif + .object = &displayUartObject, + .hwAttrs = &displayUartHWAttrs + } +}; + +const uint_least8_t Display_count = sizeof(Display_config) / sizeof(Display_Config); +#endif /* 0 _RB_ */ +/* + * =============================== I2C =============================== + */ +#include +#include + +I2CCC32XX_Object i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2CCOUNT]; + +const I2CCC32XX_HWAttrsV1 i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2CCOUNT] = { + { + .baseAddr = I2CA0_BASE, + .intNum = INT_I2CA0, + .intPriority = (~0), + .clkPin = I2CCC32XX_PIN_01_I2C_SCL, + .dataPin = I2CCC32XX_PIN_02_I2C_SDA + } +}; + +const I2C_Config I2C_config[CC3220SF_LAUNCHXL_I2CCOUNT] = { + { + .fxnTablePtr = &I2CCC32XX_fxnTable, + .object = &i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2C0], + .hwAttrs = &i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2C0] + } +}; + +const uint_least8_t I2C_count = CC3220SF_LAUNCHXL_I2CCOUNT; + +/* + * =============================== I2S =============================== + */ +#include +#include + +I2SCC32XXDMA_Object i2sCC3220SObjects[CC3220SF_LAUNCHXL_I2SCOUNT]; + +const I2SCC32XXDMA_HWAttrsV1 i2sCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2SCOUNT] = { + { + .baseAddr = I2S_BASE, + .intNum = INT_I2S, + .intPriority = (~0), + .rxChannelIndex = UDMA_CH4_I2S_RX, + .txChannelIndex = UDMA_CH5_I2S_TX, + .xr0Pin = I2SCC32XXDMA_PIN_64_McAXR0, + .xr1Pin = I2SCC32XXDMA_PIN_50_McAXR1, + .clkxPin = I2SCC32XXDMA_PIN_62_McACLKX, + .clkPin = I2SCC32XXDMA_PIN_53_McACLK, + .fsxPin = I2SCC32XXDMA_PIN_63_McAFSX, + } +}; + +const I2S_Config I2S_config[CC3220SF_LAUNCHXL_I2SCOUNT] = { + { + .fxnTablePtr = &I2SCC32XXDMA_fxnTable, + .object = &i2sCC3220SObjects[CC3220SF_LAUNCHXL_I2S0], + .hwAttrs = &i2sCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2S0] + } +}; + +const uint_least8_t I2S_count = CC3220SF_LAUNCHXL_I2SCOUNT; + +/* + * =============================== Power =============================== + */ +/* + * This table defines the parking state to be set for each parkable pin + * during LPDS. (Device pins must be parked during LPDS to achieve maximum + * power savings.) If the pin should be left unparked, specify the state + * PowerCC32XX_DONT_PARK. For example, for a UART TX pin, the device + * will automatically park the pin in a high state during transition to LPDS, + * so the Power Manager does not need to explictly park the pin. So the + * corresponding entries in this table should indicate PowerCC32XX_DONT_PARK. + */ +PowerCC32XX_ParkInfo parkInfo[] = { +/* PIN PARK STATE PIN ALIAS (FUNCTION) + ----------------- ------------------------------ -------------------- */ + {PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10 */ + {PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11 */ + {PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12 */ + {PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13 */ + {PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14 */ + {PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15 */ + {PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16 */ + {PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17 */ + {PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN */ + {PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22 */ + {PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG) */ + {PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG) */ + {PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG) */ + {PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG) */ + {PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28 */ + {PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2 */ + {PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1 */ + {PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2 */ + {PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P */ + {PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0 */ + {PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N */ + {PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30 */ + {PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO1 (UART0_TX) */ + {PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO2 */ + {PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3 */ + {PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4 */ + {PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5 */ + {PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6 */ + {PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7 */ + {PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8 */ + {PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9 */ +}; + +/* + * This structure defines the configuration for the Power Manager. + * + * In this configuration the Power policy is disabled by default (because + * enablePolicy is set to false). The Power policy can be enabled dynamically + * at runtime by calling Power_enablePolicy(), or at build time, by changing + * enablePolicy to true in this structure. + */ +const PowerCC32XX_ConfigV1 PowerCC32XX_config = { + .policyInitFxn = &PowerCC32XX_initPolicy, + .policyFxn = &PowerCC32XX_sleepPolicy, + .enterLPDSHookFxn = NULL, + .resumeLPDSHookFxn = NULL, + .enablePolicy = false, + .enableGPIOWakeupLPDS = true, + .enableGPIOWakeupShutdown = false, + .enableNetworkWakeupLPDS = true, + .wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13, + .wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE, + .wakeupGPIOFxnLPDS = NULL, + .wakeupGPIOFxnLPDSArg = 0, + .wakeupGPIOSourceShutdown = 0, + .wakeupGPIOTypeShutdown = 0, + .ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 | + PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4, + .keepDebugActiveDuringLPDS = false, + .ioRetentionShutdown = PRCM_IO_RET_GRP_1, + .pinParkDefs = parkInfo, + .numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo) +}; + +/* + * =============================== PWM =============================== + */ +#include +#include + +PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT]; + +const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = { + { /* CC3220SF_LAUNCHXL_PWM6 */ + .pwmPin = PWMTimerCC32XX_PIN_01 + }, + { /* CC3220SF_LAUNCHXL_PWM7 */ + .pwmPin = PWMTimerCC32XX_PIN_02 + } +}; + +const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = { + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6] + }, + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7] + } +}; + +const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT; + +/* + * =============================== SDFatFS =============================== + */ +#if 0 /*_RB_*/ +#include +#include + +/* Note: The SDFatFS and SD drivers must use the same count */ +SDFatFS_Object sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFSCOUNT]; + +const SDFatFS_Config SDFatFS_config[CC3220SF_LAUNCHXL_SDFatFSCOUNT] = { + { + .object = &sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFS0] + } +}; + +const uint_least8_t SDFatFS_count = CC3220SF_LAUNCHXL_SDFatFSCOUNT; + +/* + * =============================== SD =============================== + */ +#include +#include + +SDHostCC32XX_Object sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SDCOUNT]; + +/* SDHost configuration structure, describing which pins are to be used */ +const SDHostCC32XX_HWAttrsV1 sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SDCOUNT] = { + { + .clkRate = 8000000, + .intPriority = ~0, + .baseAddr = SDHOST_BASE, + .rxChIdx = UDMA_CH23_SDHOST_RX, + .txChIdx = UDMA_CH24_SDHOST_TX, + .dataPin = SDHostCC32XX_PIN_06_SDCARD_DATA, + .cmdPin = SDHostCC32XX_PIN_08_SDCARD_CMD, + .clkPin = SDHostCC32XX_PIN_07_SDCARD_CLK + } +}; + +const SD_Config SD_config[CC3220SF_LAUNCHXL_SDCOUNT] = { + { + .fxnTablePtr = &sdHostCC32XX_fxnTable, + .object = &sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SD0], + .hwAttrs = &sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SD0] + }, +}; + +const uint_least8_t SD_count = CC3220SF_LAUNCHXL_SDCOUNT; + +/* + * =============================== SDSPI =============================== + */ +#include +#include + +SDSPICC32XX_Object sdspiCC3220SObjects[CC3220SF_LAUNCHXL_SDSPICOUNT]; + +/* SDSPI configuration structure, describing which pins are to be used */ +const SDSPICC32XX_HWAttrsV1 sdspiCC3220SHWattrs[CC3220SF_LAUNCHXL_SDSPICOUNT] = { + { + .baseAddr = GSPI_BASE, + .spiPRCM = PRCM_GSPI, + .clkPin = SDSPICC32XX_PIN_05_CLK, + .mosiPin = SDSPICC32XX_PIN_07_MOSI, + .misoPin = SDSPICC32XX_PIN_06_MISO, + .csPin = SDSPICC32XX_PIN_62_GPIO + } +}; + +const SDSPI_Config SDSPI_config[CC3220SF_LAUNCHXL_SDSPICOUNT] = { + { + .fxnTablePtr = &SDSPICC32XX_fxnTable, + .object = &sdspiCC3220SObjects[CC3220SF_LAUNCHXL_SDSPI0], + .hwAttrs = &sdspiCC3220SHWattrs[CC3220SF_LAUNCHXL_SDSPI0] + }, +}; + +const uint_least8_t SDSPI_count = CC3220SF_LAUNCHXL_SDSPICOUNT; + +#endif /* 0 _RB_ */ +/* + * =============================== SPI =============================== + */ +#include +#include + +SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT]; + +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_ALIGN(spiCC3220SDMAscratchBuf, 32) +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_alignment=32 +#elif defined(__GNUC__) +__attribute__ ((aligned (32))) +#endif +uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT]; + +const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = { + /* index 0 is reserved for LSPI that links to the NWP */ + { + .baseAddr = LSPI_BASE, + .intNum = INT_LSPI, + .intPriority = (~0), + .spiPRCM = PRCM_LSPI, + .csControl = SPI_SW_CTRL_CS, + .csPolarity = SPI_CS_ACTIVEHIGH, + .pinMode = SPI_4PIN_MODE, + .turboMode = SPI_TURBO_OFF, + .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_CH12_LSPI_RX, + .txChannelIndex = UDMA_CH13_LSPI_TX, + .minDmaTransferSize = 100, + .mosiPin = SPICC32XXDMA_PIN_NO_CONFIG, + .misoPin = SPICC32XXDMA_PIN_NO_CONFIG, + .clkPin = SPICC32XXDMA_PIN_NO_CONFIG, + .csPin = SPICC32XXDMA_PIN_NO_CONFIG + }, + { + .baseAddr = GSPI_BASE, + .intNum = INT_GSPI, + .intPriority = (~0), + .spiPRCM = PRCM_GSPI, + .csControl = SPI_HW_CTRL_CS, + .csPolarity = SPI_CS_ACTIVELOW, + .pinMode = SPI_4PIN_MODE, + .turboMode = SPI_TURBO_OFF, + .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_CH6_GSPI_RX, + .txChannelIndex = UDMA_CH7_GSPI_TX, + .minDmaTransferSize = 100, + .mosiPin = SPICC32XXDMA_PIN_07_MOSI, + .misoPin = SPICC32XXDMA_PIN_06_MISO, + .clkPin = SPICC32XXDMA_PIN_05_CLK, + .csPin = SPICC32XXDMA_PIN_08_CS + } +}; + +const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = { + { + .fxnTablePtr = &SPICC32XXDMA_fxnTable, + .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0], + .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0] + }, + { + .fxnTablePtr = &SPICC32XXDMA_fxnTable, + .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1], + .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1] + } +}; + +const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT; + +/* + * =============================== UART =============================== + */ +#include +#if TI_DRIVERS_UART_DMA +#include + +UARTCC32XXDMA_Object uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UARTCOUNT]; + +/* UART configuration structure */ +const UARTCC32XXDMA_HWAttrsV1 uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .baseAddr = UARTA0_BASE, + .intNum = INT_UARTA0, + .intPriority = (~0), + .rxChannelIndex = UDMA_CH8_UARTA0_RX, + .txChannelIndex = UDMA_CH9_UARTA0_TX, + .rxPin = UARTCC32XXDMA_PIN_57_UART0_RX, + .txPin = UARTCC32XXDMA_PIN_55_UART0_TX + }, + { + .baseAddr = UARTA1_BASE, + .intNum = INT_UARTA1, + .intPriority = (~0), + .rxChannelIndex = UDMA_CH10_UARTA1_RX, + .txChannelIndex = UDMA_CH11_UARTA1_TX, + .rxPin = UARTCC32XXDMA_PIN_08_UART1_RX, + .txPin = UARTCC32XXDMA_PIN_07_UART1_TX + } +}; + +const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .fxnTablePtr = &UARTCC32XXDMA_fxnTable, + .object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART0], + .hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART0] + }, + { + .fxnTablePtr = &UARTCC32XXDMA_fxnTable, + .object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART1], + .hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART1] + } +}; + +#else +#include + +UARTCC32XX_Object uartCC3220SObjects[CC3220SF_LAUNCHXL_UARTCOUNT]; +unsigned char uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UARTCOUNT][32]; + +/* UART configuration structure */ +const UARTCC32XX_HWAttrsV1 uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .baseAddr = UARTA0_BASE, + .intNum = INT_UARTA0, + .intPriority = (~0), + .flowControl = UART_FLOWCONTROL_NONE, + .ringBufPtr = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0], + .ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0]), + .rxPin = UARTCC32XX_PIN_57_UART0_RX, + .txPin = UARTCC32XX_PIN_55_UART0_TX + }, + { + .baseAddr = UARTA1_BASE, + .intNum = INT_UARTA1, + .intPriority = (~0), + .flowControl = UART_FLOWCONTROL_NONE, + .ringBufPtr = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1], + .ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1]), + .rxPin = UARTCC32XX_PIN_08_UART1_RX, + .txPin = UARTCC32XX_PIN_07_UART1_TX + } +}; + +const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .fxnTablePtr = &UARTCC32XX_fxnTable, + .object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART0], + .hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART0] + }, + { + .fxnTablePtr = &UARTCC32XX_fxnTable, + .object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART1], + .hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART1] + } +}; +#endif /* TI_DRIVERS_UART_DMA */ + +const uint_least8_t UART_count = CC3220SF_LAUNCHXL_UARTCOUNT; + +/* + * =============================== Watchdog =============================== + */ +#include +#include + +WatchdogCC32XX_Object watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOGCOUNT]; + +const WatchdogCC32XX_HWAttrs watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = { + { + .baseAddr = WDT_BASE, + .intNum = INT_WDT, + .intPriority = (~0), + .reloadValue = 80000000 // 1 second period at default CPU clock freq + } +}; + +const Watchdog_Config Watchdog_config[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = { + { + .fxnTablePtr = &WatchdogCC32XX_fxnTable, + .object = &watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOG0], + .hwAttrs = &watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOG0] + } +}; + +const uint_least8_t Watchdog_count = CC3220SF_LAUNCHXL_WATCHDOGCOUNT; + +#if defined(__SF_DEBUG__) +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(ulDebugHeader, ".dbghdr") +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_location=".dbghdr" +#elif defined(__GNUC__) +__attribute__ ((section (".dbghdr"))) +#endif +const unsigned long ulDebugHeader[]= +{ + 0x5AA5A55A, + 0x000FF800, + 0xEFA3247D +}; +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h new file mode 100644 index 000000000..fe977ef02 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file C3220SF_LAUNCHXL.h + * + * @brief CC3220 Board Specific APIs + * + * The CC3220SF_LAUNCHXL header file should be included in an application as + * follows: + * @code + * #include + * @endcode + * + * ============================================================================ + */ +#ifndef __CC3220SF_LAUNCHXL_H +#define __CC3220SF_LAUNCHXL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define CC3220SF_LAUNCHXL_GPIO_LED_OFF (0) +#define CC3220SF_LAUNCHXL_GPIO_LED_ON (1) + +/*! + * @def CC3220SF_LAUNCHXL_ADCName + * @brief Enum of ADC names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_ADCName { + CC3220SF_LAUNCHXL_ADC0 = 0, + CC3220SF_LAUNCHXL_ADC1, + + CC3220SF_LAUNCHXL_ADCCOUNT +} CC3220SF_LAUNCHXL_ADCName; + +/*! + * @def CC3220SF_LAUNCHXL_CryptoName + * @brief Enum of Crypto names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_CryptoName { + CC3220SF_LAUNCHXL_CRYPTO0 = 0, + + CC3220SF_LAUNCHXL_CRYPTOCOUNT +} CC3220SF_LAUNCHXL_CryptoName; + +/*! + * @def CC3220SF_LAUNCHXL_GPIOName + * @brief Enum of GPIO names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_GPIOName { + CC3220SF_LAUNCHXL_GPIO_SW2 = 0, + CC3220SF_LAUNCHXL_GPIO_SW3, + CC3220SF_LAUNCHXL_GPIO_LED_D7, + + /* + * CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the + * I2C and PWM peripherals. In order for those examples to work, these + * LEDs are taken out of gpioPinCOnfig[] + */ + //CC3220SF_LAUNCHXL_GPIO_LED_D6, + //CC3220SF_LAUNCHXL_GPIO_LED_D5, + + CC3220SF_LAUNCHXL_GPIOCOUNT +} CC3220SF_LAUNCHXL_GPIOName; + +/*! + * @def CC3220SF_LAUNCHXL_I2CName + * @brief Enum of I2C names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_I2CName { + CC3220SF_LAUNCHXL_I2C0 = 0, + + CC3220SF_LAUNCHXL_I2CCOUNT +} CC3220SF_LAUNCHXL_I2CName; + +/*! + * @def CC3220SF_LAUNCHXL_I2SName + * @brief Enum of I2S names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_I2SName { + CC3220SF_LAUNCHXL_I2S0 = 0, + + CC3220SF_LAUNCHXL_I2SCOUNT +} CC3220SF_LAUNCHXL_I2SName; + +/*! + * @def CC3220SF_LAUNCHXL_PWMName + * @brief Enum of PWM names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_PWMName { + CC3220SF_LAUNCHXL_PWM6 = 0, + CC3220SF_LAUNCHXL_PWM7, + + CC3220SF_LAUNCHXL_PWMCOUNT +} CC3220SF_LAUNCHXL_PWMName; + +/*! + * @def CC3220SF_LAUNCHXL_SDFatFSName + * @brief Enum of SDFatFS names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SDFatFSName { + CC3220SF_LAUNCHXL_SDFatFS0 = 0, + + CC3220SF_LAUNCHXL_SDFatFSCOUNT +} CC3220SF_LAUNCHXL_SDFatFSName; + +/*! + * @def CC3220SF_LAUNCHXL_SDName + * @brief Enum of SD names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SDName { + CC3220SF_LAUNCHXL_SD0 = 0, + + CC3220SF_LAUNCHXL_SDCOUNT +} CC3220SF_LAUNCHXL_SDName; +/*! + * @def CC3220SF_LAUNCHXL_SDSPIName + * @brief Enum of SDSPI names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SDSPIName { + CC3220SF_LAUNCHXL_SDSPI0 = 0, + + CC3220SF_LAUNCHXL_SDSPICOUNT +} CC3220SF_LAUNCHXL_SDSPIName; + +/*! + * @def CC3220SF_LAUNCHXL_SPIName + * @brief Enum of SPI names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SPIName { + CC3220SF_LAUNCHXL_SPI0 = 0, + CC3220SF_LAUNCHXL_SPI1, + + CC3220SF_LAUNCHXL_SPICOUNT +} CC3220SF_LAUNCHXL_SPIName; + +/*! + * @def CC3220SF_LAUNCHXL_UARTName + * @brief Enum of UARTs on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_UARTName { + CC3220SF_LAUNCHXL_UART0 = 0, + CC3220SF_LAUNCHXL_UART1, + + CC3220SF_LAUNCHXL_UARTCOUNT +} CC3220SF_LAUNCHXL_UARTName; + +/*! + * @def CC3220SF_LAUNCHXL_WatchdogName + * @brief Enum of Watchdogs on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_WatchdogName { + CC3220SF_LAUNCHXL_WATCHDOG0 = 0, + + CC3220SF_LAUNCHXL_WATCHDOGCOUNT +} CC3220SF_LAUNCHXL_WatchdogName; + +/*! + * @brief Initialize the general board specific settings + * + * This function initializes the general board specific settings. + */ +extern void CC3220SF_LAUNCHXL_initGeneral(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CC3220SF_LAUNCHXL_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL_FREERTOS.cmd b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL_FREERTOS.cmd new file mode 100644 index 000000000..b2e4ed4ca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL_FREERTOS.cmd @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== CC3220SF_LAUNCHXL.cmd ======== + */ + +--stack_size=1024 +--heap_size=0 /* minimize heap since we are using heap_4.c */ +--entry_point=resetISR + +/* + * The starting address of the application. Normally the interrupt vectors + * must be located at the beginning of the application. + */ +#define SRAM_BASE 0x20000000 +#define FLASH_BASE 0x01000800 + +MEMORY +{ + /* Bootloader uses FLASH_HDR during initialization */ + FLASH_HDR (RX) : origin = 0x01000000, length = 0x7FF /* 2 KB */ + FLASH (RX) : origin = 0x01000800, length = 0x0FF800 /* 1022KB */ + SRAM (RWX) : origin = 0x20000000, length = 0x00040000 /* 256KB */ +} + +/* Section allocation in memory */ + +SECTIONS +{ + .dbghdr : > FLASH_HDR + .text : > FLASH + .TI.ramfunc : {} load=FLASH, run=SRAM, table(BINIT) + .const : > FLASH + .cinit : > FLASH + .pinit : > FLASH + .init_array : > FLASH + + .data : > SRAM + .bss : > SRAM + .sysmem : > SRAM + .stack : > SRAM(HIGH) + + /* these sections are used by FreeRTOS */ + .resetVecs : > FLASH_BASE + .ramVecs : > SRAM_BASE, type=NOLOAD +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/adc.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/adc.h new file mode 100644 index 000000000..88e848099 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/adc.h @@ -0,0 +1,122 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// adc.h +// +// Defines and Macros for the ADC. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// Values that can be passed to APIs as ulChannel parameter +//***************************************************************************** +#define ADC_CH_0 0x00000000 +#define ADC_CH_1 0x00000008 +#define ADC_CH_2 0x00000010 +#define ADC_CH_3 0x00000018 + + +//***************************************************************************** +// +// Values that can be passed to ADCIntEnable(), ADCIntDisable() +// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus() +// +//***************************************************************************** +#define ADC_DMA_DONE 0x00000010 +#define ADC_FIFO_OVERFLOW 0x00000008 +#define ADC_FIFO_UNDERFLOW 0x00000004 +#define ADC_FIFO_EMPTY 0x00000002 +#define ADC_FIFO_FULL 0x00000001 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void ADCEnable(unsigned long ulBase); +extern void ADCDisable(unsigned long ulBase); +extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel); +extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel); +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntFlags); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntFlags); +extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntFlags); +extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel); +extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel); +extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue); +extern void ADCTimerEnable(unsigned long ulBase); +extern void ADCTimerDisable(unsigned long ulBase); +extern void ADCTimerReset(unsigned long ulBase); +extern unsigned long ADCTimerValueGet(unsigned long ulBase); +extern unsigned char ADCFIFOLvlGet(unsigned long ulBase, + unsigned long ulChannel); +extern unsigned long ADCFIFORead(unsigned long ulBase, + unsigned long ulChannel); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/aes.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/aes.h new file mode 100644 index 000000000..b3ce79e59 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/aes.h @@ -0,0 +1,223 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// aes.h +// +// Defines and Macros for the AES module. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_AES_H__ +#define __DRIVERLIB_AES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used to specify the operation direction in the +// ui32Config argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_DIR_ENCRYPT 0x00000004 +#define AES_CFG_DIR_DECRYPT 0x00000000 + +//***************************************************************************** +// +// The following defines are used to specify the key size in the ui32Config +// argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_KEY_SIZE_128BIT 0x00000008 +#define AES_CFG_KEY_SIZE_192BIT 0x00000010 +#define AES_CFG_KEY_SIZE_256BIT 0x00000018 + +//***************************************************************************** +// +// The following defines are used to specify the mode of operation in the +// ui32Config argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_MODE_M 0x2007fe60 +#define AES_CFG_MODE_ECB 0x00000000 +#define AES_CFG_MODE_CBC 0x00000020 +#define AES_CFG_MODE_CTR 0x00000040 +#define AES_CFG_MODE_ICM 0x00000200 +#define AES_CFG_MODE_CFB 0x00000400 +#define AES_CFG_MODE_XTS_TWEAKJL \ + 0x00000800 +#define AES_CFG_MODE_XTS_K2IJL \ + 0x00001000 +#define AES_CFG_MODE_XTS_K2ILJ0 \ + 0x00001800 +#define AES_CFG_MODE_F8 0x00002000 +#define AES_CFG_MODE_F9 0x20004000 +#define AES_CFG_MODE_CBCMAC 0x20008000 +#define AES_CFG_MODE_GCM_HLY0ZERO \ + 0x20010040 +#define AES_CFG_MODE_GCM_HLY0CALC \ + 0x20020040 +#define AES_CFG_MODE_GCM_HY0CALC \ + 0x20030040 +#define AES_CFG_MODE_CCM 0x20040040 + +//***************************************************************************** +// +// The following defines are used to specify the counter width in the +// ui32Config argument in the AESConfig function. It is only required to +// be defined when using CTR, CCM, or GCM modes. Only one length is permitted. +// +//***************************************************************************** +#define AES_CFG_CTR_WIDTH_32 0x00000000 +#define AES_CFG_CTR_WIDTH_64 0x00000080 +#define AES_CFG_CTR_WIDTH_96 0x00000100 +#define AES_CFG_CTR_WIDTH_128 0x00000180 + +//***************************************************************************** +// +// The following defines are used to define the width of the length field for +// CCM operation through the ui32Config argument in the AESConfig function. +// This value is also known as L. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_CCM_L_2 0x00080000 +#define AES_CFG_CCM_L_4 0x00180000 +#define AES_CFG_CCM_L_8 0x00380000 + +//***************************************************************************** +// +// The following defines are used to define the length of the authentication +// field for CCM operations through the ui32Config argument in the AESConfig +// function. This value is also known as M. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_CCM_M_4 0x00400000 +#define AES_CFG_CCM_M_6 0x00800000 +#define AES_CFG_CCM_M_8 0x00c00000 +#define AES_CFG_CCM_M_10 0x01000000 +#define AES_CFG_CCM_M_12 0x01400000 +#define AES_CFG_CCM_M_14 0x01800000 +#define AES_CFG_CCM_M_16 0x01c00000 + +//***************************************************************************** +// +// Interrupt flags for use with the AESIntEnable, AESIntDisable, and +// AESIntStatus functions. +// +//***************************************************************************** +#define AES_INT_CONTEXT_IN 0x00000001 +#define AES_INT_CONTEXT_OUT 0x00000008 +#define AES_INT_DATA_IN 0x00000002 +#define AES_INT_DATA_OUT 0x00000004 +#define AES_INT_DMA_CONTEXT_IN 0x00010000 +#define AES_INT_DMA_CONTEXT_OUT 0x00020000 +#define AES_INT_DMA_DATA_IN 0x00040000 +#define AES_INT_DMA_DATA_OUT 0x00080000 + +//***************************************************************************** +// +// Defines used when enabling and disabling DMA requests in the +// AESEnableDMA and AESDisableDMA functions. +// +//***************************************************************************** +#define AES_DMA_DATA_IN 0x00000040 +#define AES_DMA_DATA_OUT 0x00000020 +#define AES_DMA_CONTEXT_IN 0x00000080 +#define AES_DMA_CONTEXT_OUT 0x00000100 + +//***************************************************************************** +// +// Function prototypes. +// +//***************************************************************************** +extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, + uint32_t ui32Keysize); +extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key, + uint32_t ui32Keysize); +extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key); +extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata); +extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata); +extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData); +extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length); +extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length); +extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, + uint8_t ui8Length); +extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, + uint8_t ui8Length); +extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t ui8Length); +extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t ui8Length); +extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t *pui8Dest, + uint32_t ui32Length); +extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src, + uint32_t ui32Length, + uint8_t *pui8Tag); +extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t *pui8Dest, uint32_t ui32Length, + uint8_t *pui8AuthSrc, uint32_t ui32AuthLength, + uint8_t *pui8Tag); +extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked); +extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern void AESIntUnregister(uint32_t ui32Base); +extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); +extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_AES_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/camera.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/camera.h new file mode 100644 index 000000000..6d4941695 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/camera.h @@ -0,0 +1,136 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// camera.h +// +// Prototypes and macros for the camera controller module. +// +//***************************************************************************** + +#ifndef __CAMERA_H__ +#define __CAMERA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// Macro defining Camera buffer address +//***************************************************************************** +#define CAM_BUFFER_ADDR 0x44018100 + + +//***************************************************************************** +// Value that can be passed to CameraXClkSet(). +//***************************************************************************** +#define CAM_XCLK_STABLE_LO 0x00 +#define CAM_XCLK_STABLE_HI 0x01 +#define CAM_XCLK_DIV_BYPASS 0x02 + + +//***************************************************************************** +// Value that can be passed to CameraIntEnable(), CameraIntDisable, +// CameraIntClear() or returned from CameraIntStatus(). +//***************************************************************************** +#define CAM_INT_DMA 0x80000000 +#define CAM_INT_FE 0x00010000 +#define CAM_INT_FIFO_NOEMPTY 0x00000010 +#define CAM_INT_FIFO_FULL 0x00000008 +#define CAM_INT_FIFO_THR 0x00000004 +#define CAM_INT_FIFO_OF 0x00000002 +#define CAN_INT_FIFO_UR 0x00000001 + + +//***************************************************************************** +// Value that can be passed to CameraXClkConfig(). +//***************************************************************************** +#define CAM_HS_POL_HI 0x00000000 +#define CAM_HS_POL_LO 0x00000200 +#define CAM_VS_POL_HI 0x00000000 +#define CAM_VS_POL_LO 0x00000100 + +#define CAM_PCLK_RISE_EDGE 0x00000000 +#define CAM_PCLK_FALL_EDGE 0x00000400 + +#define CAM_ORDERCAM_SWAP 0x00000800 +#define CAM_NOBT_SYNCHRO 0x00002000 +#define CAM_IF_SYNCHRO 0x00080000 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void CameraReset(unsigned long ulBase); +extern void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol, + unsigned long ulVSPol, unsigned long ulFlags); +extern void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn, + unsigned long ulXClk); +extern void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags); +extern void CameraDMAEnable(unsigned long ulBase); +extern void CameraDMADisable(unsigned long ulBase); +extern void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold); +extern void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void CameraIntUnregister(unsigned long ulBase); +extern void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long CameraIntStatus(unsigned long ulBase); +extern void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate); +extern void CameraCaptureStart(unsigned long ulBase); +extern void CameraBufferRead(unsigned long ulBase,unsigned long *pBuffer, + unsigned char ucSize); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif //__CAMERA_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/cpu.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/cpu.c new file mode 100644 index 000000000..7c8ecaec3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/cpu.c @@ -0,0 +1,417 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// cpu.c +// +// Instruction wrappers for special CPU instructions needed by the +// +// +//***************************************************************************** +#include "cpu.h" + +//***************************************************************************** +// +// Wrapper function for the CPSID instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(gcc) +unsigned long __attribute__((naked)) +CPUcpsid(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " dsb \n" + " isb \n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " dsb \n" + " isb \n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(ccs) +unsigned long +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " dsb \n" + " isb \n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function returning the state of PRIMASK (indicating whether +// interrupts are enabled or disabled). +// +//***************************************************************************** +#if defined(gcc) +unsigned long __attribute__((naked)) +CPUprimask(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUprimask(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(ccs) +unsigned long +CPUprimask(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(gcc) +unsigned long __attribute__((naked)) +CPUcpsie(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " dsb \n" + " isb \n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " dsb \n" + " isb \n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(ccs) +unsigned long +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " dsb \n" + " isb \n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function for the WFI instruction. +// +//***************************************************************************** +#if defined(gcc) +void __attribute__((naked)) +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" dsb \n" + " isb \n" + " wfi \n" + " bx lr\n"); +} +#endif +#if defined(ewarm) +void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" dsb \n" + " isb \n" + " wfi \n"); +} +#endif +#if defined(ccs) +void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" dsb \n" + " isb \n" + " wfi \n"); +} +#endif + +//***************************************************************************** +// +// Wrapper function for writing the BASEPRI register. +// +//***************************************************************************** +#if defined(gcc) +void __attribute__((naked)) +CPUbasepriSet(unsigned long ulNewBasepri) +{ + + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n" + " dsb \n" + " isb \n" + " bx lr\n"); +} +#endif +#if defined(ewarm) +void +CPUbasepriSet(unsigned long ulNewBasepri) +{ + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n" + " dsb \n" + " isb \n"); +} +#endif +#if defined(ccs) +void +CPUbasepriSet(unsigned long ulNewBasepri) +{ + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n" + " dsb \n" + " isb \n"); +} +#endif + +//***************************************************************************** +// +// Wrapper function for reading the BASEPRI register. +// +//***************************************************************************** +#if defined(gcc) +unsigned long __attribute__((naked)) +CPUbasepriGet(void) +{ + unsigned long ulRet; + + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(ccs) +unsigned long +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/cpu.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/cpu.h new file mode 100644 index 000000000..9d5bb520c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/cpu.h @@ -0,0 +1,80 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// cpu.h +// +// Prototypes for the CPU instruction wrapper functions. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern unsigned long CPUcpsid(void); +extern unsigned long CPUcpsie(void); +extern unsigned long CPUprimask(void); +extern void CPUwfi(void); +extern unsigned long CPUbasepriGet(void); +extern void CPUbasepriSet(unsigned long ulNewBasepri); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/crc.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/crc.h new file mode 100644 index 000000000..7d7aebb08 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/crc.h @@ -0,0 +1,103 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// crc.h +// +// Defines and Macros for CRC module. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_CRC_H__ +#define __DRIVERLIB_CRC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used in the ui32Config argument of the +// ECConfig function. +// +//***************************************************************************** +#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed +#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s' +#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s' +#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size +#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size +#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable +#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable +#define CRC_CFG_IBR 0x00000080 // Bit reverse enable +#define CRC_CFG_ENDIAN_SBHW 0x00000000 // Swap byte in half-word +#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word +#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005 +#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021 +#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7 +#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41 +#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum + +//***************************************************************************** +// +// Function prototypes. +// +//***************************************************************************** +extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig); +extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn, + uint32_t ui32DataLength, uint32_t ui32Config); +extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data); +extern uint32_t CRCResultRead(uint32_t ui32Base); +extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_CRC_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/debug.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/debug.h new file mode 100644 index 000000000..470ec9ea9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/debug.h @@ -0,0 +1,72 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// debug.h +// +// Macros for assisting debug of the driver library. +// +//***************************************************************************** +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/des.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/des.h new file mode 100644 index 000000000..547a37482 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/des.h @@ -0,0 +1,148 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// des.h +// +// Defines and Macros for the DES module. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_DES_H__ +#define __DRIVERLIB_DES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used to specify the direction with the +// ui32Config argument in the DESConfig() function. Only one is permitted. +// +//***************************************************************************** +#define DES_CFG_DIR_DECRYPT 0x00000000 +#define DES_CFG_DIR_ENCRYPT 0x00000004 + +//***************************************************************************** +// +// The following defines are used to specify the operational with the +// ui32Config argument in the DESConfig() function. Only one is permitted. +// +//***************************************************************************** +#define DES_CFG_MODE_ECB 0x00000000 +#define DES_CFG_MODE_CBC 0x00000010 +#define DES_CFG_MODE_CFB 0x00000020 + +//***************************************************************************** +// +// The following defines are used to select between single DES and triple DES +// with the ui32Config argument in the DESConfig() function. Only one is +// permitted. +// +//***************************************************************************** +#define DES_CFG_SINGLE 0x00000000 +#define DES_CFG_TRIPLE 0x00000008 + +//***************************************************************************** +// +// The following defines are used with the DESIntEnable(), DESIntDisable() and +// DESIntStatus() functions. +// +//***************************************************************************** +#define DES_INT_CONTEXT_IN 0x00000001 +#define DES_INT_DATA_IN 0x00000002 +#define DES_INT_DATA_OUT 0x00000004 +#define DES_INT_DMA_CONTEXT_IN 0x00010000 +#define DES_INT_DMA_DATA_IN 0x00020000 +#define DES_INT_DMA_DATA_OUT 0x00040000 + +//***************************************************************************** +// +// The following defines are used with the DESEnableDMA() and DESDisableDMA() +// functions. +// +//***************************************************************************** +#define DES_DMA_CONTEXT_IN 0x00000080 +#define DES_DMA_DATA_OUT 0x00000040 +#define DES_DMA_DATA_IN 0x00000020 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, + uint8_t ui8Length); +extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, + uint8_t ui8Length); +extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t *pui8Dest, uint32_t ui32Length); +extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t ui8Length); +extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t ui8Length); +extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); +extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); +extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked); +extern void DESIntUnregister(uint32_t ui32Base); +extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata); +extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key); +extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_DES_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/flash.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/flash.c new file mode 100644 index 000000000..cb9cb2f83 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/flash.c @@ -0,0 +1,868 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// flash.c +// +// Driver for programming the on-chip flash. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_flash_ctrl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ints.h" +#include "inc/hw_gprcm.h" +#include "inc/hw_hib1p2.h" +#include "inc/hw_hib3p3.h" +#include "inc/hw_common_reg.h" +#include "inc/hw_stack_die_ctrl.h" +#include "debug.h" +#include "flash.h" +#include "utils.h" +#include "interrupt.h" + +#define HAVE_WRITE_BUFFER 1 + + + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Program Enable (FMPPE) register. +// +//***************************************************************************** +static const unsigned long g_pulFMPPERegs[] = +{ + FLASH_FMPPE0, + FLASH_FMPPE1, + FLASH_FMPPE2, + FLASH_FMPPE3, + FLASH_FMPPE4, + FLASH_FMPPE5, + FLASH_FMPPE6, + FLASH_FMPPE7, + FLASH_FMPPE8, + FLASH_FMPPE9, + FLASH_FMPPE10, + FLASH_FMPPE11, + FLASH_FMPPE12, + FLASH_FMPPE13, + FLASH_FMPPE14, + FLASH_FMPPE15 + + +}; + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Read Enable (FMPRE) register. +// +//***************************************************************************** +static const unsigned long g_pulFMPRERegs[] = +{ + FLASH_FMPRE0, + FLASH_FMPRE1, + FLASH_FMPRE2, + FLASH_FMPRE3, + FLASH_FMPRE4, + FLASH_FMPRE5, + FLASH_FMPRE6, + FLASH_FMPRE7, + FLASH_FMPRE8, + FLASH_FMPRE9, + FLASH_FMPRE10, + FLASH_FMPRE11, + FLASH_FMPRE12, + FLASH_FMPRE13, + FLASH_FMPRE14, + FLASH_FMPRE15, +}; + +//***************************************************************************** +// +//! Flash Disable +//! +//! This function Disables the internal Flash. +//! +//! \return None. +// +//***************************************************************************** +void +FlashDisable() +{ + + // + // Wait for Flash Busy to get cleared + // + while((HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) + & GPRCM_TOP_DIE_ENABLE_FLASH_BUSY)) + { + + } + + // + // Assert reset + // + HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000; + + // + // 50 usec Delay Loop + // + UtilsDelay((50*80)/3); + + // + // Disable TDFlash + // + HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) = 0x0; + + // + // 50 usec Delay Loop + // + UtilsDelay((50*80)/3); + + HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; + + // + // 50 usec Delay Loop + // + UtilsDelay((50*80)/3); +} + + +//***************************************************************************** +// +//! Erases a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be erased. +//! +//! This function will erase a 2 kB block of the on-chip flash. After erasing, +//! the block will be filled with 0xFF bytes. Read-only and execute-only +//! blocks cannot be erased. +//! +//! This function will not return until the block has been erased. +//! +//! \return Returns 0 on success, or -1 if an invalid block address was +//! specified or the block is write-protected. +// +//***************************************************************************** +long +FlashErase(unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1))); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) + = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_ERMISC); + + // Erase the block. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) + = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE; + + // + // Wait until the block has been erased. + // + while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_ERASE) + { + } + + // + // Return an error if an access violation or erase error occurred. + // + if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) + & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | + FLASH_CTRL_FCRIS_ERRIS)) + + + { + return(-1); + } + + // + // Success. + // + return(0); +} + + +//***************************************************************************** +// +//! Erases a block of flash but does not wait for completion. +//! +//! \param ulAddress is the start address of the flash block to be erased. +//! +//! This function will erase a 2 kB block of the on-chip flash. After erasing, +//! the block will be filled with 0xFF bytes. Read-only and execute-only +//! blocks cannot be erased. +//! +//! This function will return immediately after commanding the erase operation. +//! Applications making use of the function can determine completion state by +//! using a flash interrupt handler or by polling FlashIntStatus. +//! +//! \return None. +// +//***************************************************************************** +void +FlashEraseNonBlocking(unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1))); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = + (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_ERMISC); + + // + // Command the flash controller to erase the block. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE; +} + + +//***************************************************************************** +// +//! Erases a complele flash at shot. +//! +//! This function erases a complele flash at shot +//! +//! \return Returns 0 on success, or -1 if the block is write-protected. +// +//***************************************************************************** +long +FlashMassErase() +{ + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = + (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_ERMISC); + + // + // Command the flash controller for mass erase. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = + FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1; + + // + // Wait until mass erase completes. + // + while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_MERASE1) + { + + } + + // + // Return an error if an access violation or erase error occurred. + // + if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) + & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | + FLASH_CTRL_FCRIS_ERRIS)) + { + return -1; + } + + // + // Success. + // + return 0; +} + +//***************************************************************************** +// +//! Erases a complele flash at shot but does not wait for completion. +//! +//! +//! This function will not return until the Flash has been erased. +//! +//! \return None. +// +//***************************************************************************** +void +FlashMassEraseNonBlocking() +{ + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = + (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_ERMISC); + + // + // Command the flash controller for mass erase. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = + FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1; + +} + +//***************************************************************************** +// +//! Programs flash. +//! +//! \param pulData is a pointer to the data to be programmed. +//! \param ulAddress is the starting address in flash to be programmed. Must +//! be a multiple of four. +//! \param ulCount is the number of bytes to be programmed. Must be a multiple +//! of four. +//! +//! This function will program a sequence of words into the on-chip flash. +//! Each word in a page of flash can only be programmed one time between an +//! erase of that page; programming a word multiple times will result in an +//! unpredictable value in that word of flash. +//! +//! Since the flash is programmed one word at a time, the starting address and +//! byte count must both be multiples of four. It is up to the caller to +//! verify the programmed contents, if such verification is required. +//! +//! This function will not return until the data has been programmed. +//! +//! \return Returns 0 on success, or -1 if a programming error is encountered. +// +//***************************************************************************** +long +FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & 3)); + ASSERT(!(ulCount & 3)); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) + = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC); + + + // + // See if this device has a write buffer. + // + +#if HAVE_WRITE_BUFFER + { + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Set the address of this block of words. for 1 MB + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F); + + // + // Loop over the words in this 32-word block. + // + while(((ulAddress & 0x7C) || + (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) && + (ulCount != 0)) + { + // + // Write this word into the write buffer. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + + (ulAddress & 0x7C)) = *pulData++; + ulAddress += 4; + ulCount -= 4; + } + + // + // Program the contents of the write buffer into flash. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) + = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF; + + // + // Wait until the write buffer has been programmed. + // + while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) & FLASH_CTRL_FMC2_WRBUF) + { + } + } + } +#else + { + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Program the next word. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE; + + // + // Wait until the word has been programmed. + // + while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_WRITE) + { + } + + // + // Increment to the next word. + // + pulData++; + ulAddress += 4; + ulCount -= 4; + } + } +#endif + // + // Return an error if an access violation occurred. + // + + if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | + FLASH_CTRL_FCRIS_INVDRIS | FLASH_CTRL_FCRIS_PROGRIS)) + + { + return(-1); + } + + // + // Success. + // + return(0); +} + + +//***************************************************************************** +// +//! Programs flash but does not poll for completion. +//! +//! \param pulData is a pointer to the data to be programmed. +//! \param ulAddress is the starting address in flash to be programmed. Must +//! be a multiple of four. +//! \param ulCount is the number of bytes to be programmed. Must be a multiple +//! of four. +//! +//! This function will start programming one or more words into the on-chip +//! flash and return immediately. The number of words that can be programmed +//! in a single call depends the part on which the function is running. For +//! parts without support for a flash write buffer, only a single word may be +//! programmed on each call to this function (\e ulCount must be 1). If a +//! write buffer is present, up to 32 words may be programmed on condition +//! that the block being programmed does not straddle a 32 word address +//! boundary. For example, wherease 32 words can be programmed if the address +//! passed is 0x100 (a multiple of 128 bytes or 32 words), only 31 words could +//! be programmed at 0x104 since attempting to write 32 would cross the 32 +//! word boundary at 0x180. +//! +//! Since the flash is programmed one word at a time, the starting address and +//! byte count must both be multiples of four. It is up to the caller to +//! verify the programmed contents, if such verification is required. +//! +//! This function will return immediately after commanding the erase operation. +//! Applications making use of the function can determine completion state by +//! using a flash interrupt handler or by polling FlashIntStatus. +//! +//! \return 0 if the write was started successfully, -1 if there was an error. +// +//***************************************************************************** +long +FlashProgramNonBlocking(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & 3)); + ASSERT(!(ulCount & 3)); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) + = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC); + + // + // See if this device has a write buffer. + // + +#if HAVE_WRITE_BUFFER + { + // + // Make sure the address/count specified doesn't straddle a 32 word + // boundary. + // + if(((ulAddress + (ulCount - 1)) & ~0x7F) != (ulAddress & ~0x7F)) + { + return(-1); + } + + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Set the address of this block of words. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F); + + // + // Loop over the words in this 32-word block. + // + while(((ulAddress & 0x7C) || (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) && + (ulCount != 0)) + { + // + // Write this word into the write buffer. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + (ulAddress & 0x7C)) = *pulData++; + ulAddress += 4; + ulCount -= 4; + } + + // + // Program the contents of the write buffer into flash. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF; + } + } +#else + { + // + // We don't have a write buffer so we can only write a single word. + // + if(ulCount > 1) + { + return(-1); + } + + // + // Write a single word. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE; + } +#endif + // + // Success. + // + return(0); +} + + +//***************************************************************************** +// +//! Gets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be queried. +//! +//! This function gets the current protection for the specified 2-kB block +//! of flash. Each block can be read/write, read-only, or execute-only. +//! Read/write blocks can be read, executed, erased, and programmed. Read-only +//! blocks can be read and executed. Execute-only blocks can only be executed; +//! processor and debugger data reads are not allowed. +//! +//! \return Returns the protection setting for this block. See +//! FlashProtectSet() for possible values. +// +//***************************************************************************** +tFlashProtection +FlashProtectGet(unsigned long ulAddress) +{ + unsigned long ulFMPRE, ulFMPPE; + unsigned long ulBank; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + + // + // Calculate the Flash Bank from Base Address, and mask off the Bank + // from ulAddress for subsequent reference. + // + ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 16); + ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1); + + // + // Read the appropriate flash protection registers for the specified + // flash bank. + // + ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]); + ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]); + + // + // Check the appropriate protection bits for the block of memory that + // is specified by the address. + // + switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & + FLASH_FMP_BLOCK_0) << 1) | + ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) + { + // + // This block is marked as execute only (that is, it can not be erased + // or programmed, and the only reads allowed are via the instruction + // fetch interface). + // + case 0: + case 1: + { + return(FlashExecuteOnly); + } + + // + // This block is marked as read only (that is, it can not be erased or + // programmed). + // + case 2: + { + return(FlashReadOnly); + } + + // + // This block is read/write; it can be read, erased, and programmed. + // + case 3: + default: + { + return(FlashReadWrite); + } + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the flash interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! This sets the handler to be called when the flash interrupt occurs. The +//! flash controller can generate an interrupt when an invalid flash access +//! occurs, such as trying to program or erase a read-only block, or trying to +//! read from an execute-only block. It can also generate an interrupt when a +//! program or erase operation has completed. The interrupt will be +//! automatically enabled when the handler is registered. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_FLASH, pfnHandler); + + // + // Enable the flash interrupt. + // + IntEnable(INT_FLASH); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the flash interrupt. +//! +//! This function will clear the handler to be called when the flash interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_FLASH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FLASH); +} + +//***************************************************************************** +// +//! Enables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values. +//! +//! Enables the indicated flash controller interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values. +//! +//! Disables the indicated flash controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the flash controller. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b FLASH_CTRL_PROGRAM and \b FLASH_CTRL_ACCESS. +// +//***************************************************************************** +unsigned long +FlashIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)); + } + else + { + return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)); + } +} + +//***************************************************************************** +// +//! Clears flash controller interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_AMISC values. +//! +//! The specified flash controller interrupt sources are cleared, so that they +//! no longer assert. This must be done in the interrupt handler to keep it +//! from being called again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/flash.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/flash.h new file mode 100644 index 000000000..b482a83f2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/flash.h @@ -0,0 +1,120 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// flash.h +// +// Prototypes for the flash driver. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and +// returned from FlashIntStatus(). +// +//***************************************************************************** +#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask +#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask +#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask +#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask +#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask +#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void FlashDisable(void); +extern long FlashErase(unsigned long ulAddress); +extern void FlashEraseNonBlocking(unsigned long ulAddress); +extern long FlashMassErase(void); +extern void FlashMassEraseNonBlocking(void); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern long FlashProgramNonBlocking(unsigned long *pulData, + unsigned long ulAddress, + unsigned long ulCount); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/gpio.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/gpio.c new file mode 100644 index 000000000..f0d721a88 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/gpio.c @@ -0,0 +1,721 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// gpio.c +// +// Driver for the GPIO module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup GPIO_General_Purpose_InputOutput_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_gpio.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_common_reg.h" +#include "debug.h" +#include "gpio.h" +#include "interrupt.h" + + +//***************************************************************************** +// +//! \internal +//! Checks a GPIO base address. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function determines if a GPIO port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +GPIOBaseValid(unsigned long ulPort) +{ + return((ulPort == GPIOA0_BASE) || + (ulPort == GPIOA1_BASE) || + (ulPort == GPIOA2_BASE) || + (ulPort == GPIOA3_BASE) || + (ulPort == GPIOA4_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the GPIO interrupt number. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! Given a GPIO base address, returns the corresponding interrupt number. +//! +//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +static long +GPIOGetIntNumber(unsigned long ulPort) +{ + unsigned int ulInt; + + // + // Determine the GPIO interrupt number for the given module. + // + switch(ulPort) + { + case GPIOA0_BASE: + { + ulInt = INT_GPIOA0; + break; + } + + case GPIOA1_BASE: + { + ulInt = INT_GPIOA1; + break; + } + + case GPIOA2_BASE: + { + ulInt = INT_GPIOA2; + break; + } + + case GPIOA3_BASE: + { + ulInt = INT_GPIOA3; + break; + } + + default: + { + return(-1); + } + } + + // + // Return GPIO interrupt number. + // + return(ulInt); +} + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulPinIO is the pin direction and/or mode. +//! +//! This function will set the specified pin(s) on the selected GPIO port +//! as either an input or output under software control, or it will set the +//! pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as +//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin +//! will be programmed as a software controlled output. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note GPIOPadConfigSet() must also be used to configure the corresponding +//! pad(s) in order for them to propagate the signal to/from the GPIO. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT)); + + // + // Set the pin direction and mode. + // + HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ? + (HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) : + (HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the direction and mode of a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input or +//! output under software control, or it can be under hardware control. The +//! type of control and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +unsigned long +GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulDir; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin direction and mode. + // + ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR); + return(((ulDir & ucPin) ? 1 : 0)); +} + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulIntType specifies the type of interrupt trigger mechanism. +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pin(s) on the selected GPIO port. +//! +//! The parameter \e ulIntType is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_FALLING_EDGE +//! - \b GPIO_RISING_EDGE +//! - \b GPIO_BOTH_EDGES +//! - \b GPIO_LOW_LEVEL +//! - \b GPIO_HIGH_LEVEL +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note In order to avoid any spurious interrupts, the user must +//! ensure that the GPIO inputs remain stable for the duration of +//! this function. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulIntType == GPIO_FALLING_EDGE) || + (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) || + (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL)); + + // + // Set the pin interrupt type. + // + HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ? + (HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) : + (HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins))); + HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ? + (HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) : + (HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins))); + HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ? + (HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) : + (HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the interrupt type for a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! +//! This function gets the interrupt type for a specified pin on the selected +//! GPIO port. The pin can be configured as a falling edge, rising edge, or +//! both edge detected interrupt, or it can be configured as a low level or +//! high level detected interrupt. The type of interrupt detection mechanism +//! is returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIOIntTypeSet(). +// +//***************************************************************************** +unsigned long +GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulIBE, ulIS, ulIEV; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin interrupt type. + // + ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE); + ulIS = HWREG(ulPort + GPIO_O_GPIO_IS); + ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV); + return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | + ((ulIEV & ucPin) ? 4 : 0)); +} + +//***************************************************************************** +// +//! Enables the specified GPIO interrupts. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ulIntFlags is the bit mask of the interrupt sources to enable. +//! +//! This function enables the indicated GPIO interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done +//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. +//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. +//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. +//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. +//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. +//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. +//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. +//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Enable the interrupts. + // + HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables the specified GPIO interrupts. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ulIntFlags is the bit mask of the interrupt sources to disable. +//! +//! This function disables the indicated GPIO interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done +//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. +//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. +//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. +//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. +//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. +//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. +//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. +//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Disable the interrupts. + // + HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets interrupt status for the specified GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in GPIOIntEnable(). +// +//***************************************************************************** +long +GPIOIntStatus(unsigned long ulPort, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Return the interrupt status. + // + if(bMasked) + { + return(HWREG(ulPort + GPIO_O_GPIO_MIS)); + } + else + { + return(HWREG(ulPort + GPIO_O_GPIO_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the interrupt for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! Clears the interrupt for the specified pin(s). +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to GPIOIntEnable(). +//! +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Clear the interrupts. + // + HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling +//! function. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected from the selected +//! GPIO port. This function will also enable the corresponding GPIO interrupt +//! in the interrupt controller; individual pin interrupts and interrupt +//! sources must be enabled with GPIOIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Register the interrupt handler. + // + IntRegister(ulPort, pfnIntHandler); + + // + // Enable the GPIO interrupt. + // + IntEnable(ulPort); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for a GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function will unregister the interrupt handler for the specified +//! GPIO port. This function will also disable the corresponding +//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts +//! and interrupt sources must be disabled with GPIOIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntUnregister(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Disable the GPIO interrupt. + // + IntDisable(ulPort); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulPort); +} + +//***************************************************************************** +// +//! Reads the values present of the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The values at the specified pin(s) are read, as specified by \e ucPins. +//! Values are returned for both input and output pin(s), and the value +//! for pin(s) that are not specified by \e ucPins are set to 0. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return Returns a bit-packed byte providing the state of the specified +//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins +//! is returned as a 0. Bits 31:8 should be ignored. +// +//***************************************************************************** +long +GPIOPinRead(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Return the pin value(s). + // + return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2)))); +} + +//***************************************************************************** +// +//! Writes a value to the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ucVal is the value to write to the pin(s). +//! +//! Writes the corresponding bit values to the output pin(s) specified by +//! \e ucPins. Writing to a pin configured as an input pin has no effect. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Write the pins. + // + HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal; +} + +//***************************************************************************** +// +//! Enables a GPIO port as a trigger to start a DMA transaction. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function enables a GPIO port to be used as a trigger to start a uDMA +//! transaction. The GPIO pin will still generate interrupts if the interrupt is +//! enabled for the selected pin. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerEnable(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + if(ulPort == GPIOA0_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1; + } + else if(ulPort == GPIOA1_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2; + } + else if(ulPort == GPIOA2_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4; + } + else if(ulPort == GPIOA3_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8; + } +} + +//***************************************************************************** +// +//! Disables a GPIO port as a trigger to start a DMA transaction. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function disables a GPIO port to be used as a trigger to start a uDMA +//! transaction. This function can be used to disable this feature if it was +//! enabled via a call to GPIODMATriggerEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerDisable(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + if(ulPort == GPIOA0_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1; + } + else if(ulPort == GPIOA1_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2; + } + else if(ulPort == GPIOA2_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4; + } + else if(ulPort == GPIOA3_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8; + } +} + + +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/gpio.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/gpio.h new file mode 100644 index 000000000..b1a229e42 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/gpio.h @@ -0,0 +1,144 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// gpio.h +// +// Defines and Macros for GPIO API. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions +// in the ulIntFlags parameter. +// +//***************************************************************************** +#define GPIO_INT_DMA 0x00000100 +#define GPIO_INT_PIN_0 0x00000001 +#define GPIO_INT_PIN_1 0x00000002 +#define GPIO_INT_PIN_2 0x00000004 +#define GPIO_INT_PIN_3 0x00000008 +#define GPIO_INT_PIN_4 0x00000010 +#define GPIO_INT_PIN_5 0x00000020 +#define GPIO_INT_PIN_6 0x00000040 +#define GPIO_INT_PIN_7 0x00000080 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern void GPIODMATriggerEnable(unsigned long ulPort); +extern void GPIODMATriggerDisable(unsigned long ulPort); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags); +extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags); +extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags); +extern void GPIOIntRegister(unsigned long ulPort, + void (*pfnIntHandler)(void)); +extern void GPIOIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/hwspinlock.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/hwspinlock.c new file mode 100644 index 000000000..6a94c1223 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/hwspinlock.c @@ -0,0 +1,274 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// hwspinlock.c +// +// Driver for the Apps-NWP spinlock +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup HwSpinLock_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ints.h" +#include "inc/hw_common_reg.h" +#include "hwspinlock.h" + +//***************************************************************************** +// Global semaphore register list +//***************************************************************************** +static const uint32_t HwSpinLock_RegLst[]= +{ + COMMON_REG_BASE + COMMON_REG_O_SPI_Properties_Register +}; + +//***************************************************************************** +// +//! Acquire specified spin lock. +//! +//! \param ui32LockID is one of the valid spin lock. +//! +//! This function acquires specified spin lock and will not retun util the +//! specified lock is acquired. +//! +//! The parameter \e ui32LockID should \b HWSPINLOCK_MCSPIS0. +//! +//! return None. +// +//***************************************************************************** +void HwSpinLockAcquire(uint32_t ui32LockID) +{ + uint32_t ui32BitPos; + uint32_t ui32SemVal; + uint32_t ui32RegAddr; + + // + // Extract the bit position from the + // LockID + // + ui32BitPos = ((ui32LockID >> 16) & 0x0FFF); + ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF]; + + // + // Set the corresponding + // ownership bits to 'b01 + // + ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos)); + + // + // Retry untill we succeed + // + do + { + HWREG(ui32RegAddr) = ui32SemVal; + } + while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) ); + +} + +//***************************************************************************** +// +//! Try to acquire specified spin lock. +//! +//! \param ui32LockID is one of the valid spin lock. +//! \param ui32Retry is the number of reties. +//! +//! This function tries acquire specified spin lock in \e ui32Retry retries. +//! +//! The parameter \e ui32Retry can be any value between 0 and 2^32. +//! +//! return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry) +{ + uint32_t ui32BitPos; + uint32_t ui32SemVal; + uint32_t ui32RegAddr; + + // + // Extract the bit position from the + // LockID + // + ui32BitPos = ((ui32LockID >> 16) & 0x0FFF); + ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF]; + + // + // Set the corresponding + // ownership bits to 'b01 + // + ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos)); + + // + // Check for 0 retry. + // + if(ui32Retry == 0) + { + ui32Retry = 1; + } + + // + // Retry the number of times specified + // + do + { + HWREG(ui32RegAddr) = ui32SemVal; + ui32Retry--; + } + while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) && ui32Retry ); + + + // + // Check the semaphore status + // + if(HWREG(ui32RegAddr) & (1 << ui32BitPos )) + { + return 0; + } + else + { + return -1; + } +} + +//***************************************************************************** +// +//! Release a previously owned spin lock +//! +//! \param ui32LockID is one of the valid spin lock. +//! +//! This function releases previously owned spin lock. +//! +//! \return None. +// +//***************************************************************************** +void HwSpinLockRelease(uint32_t ui32LockID) +{ + uint32_t ui32BitPos; + uint32_t ui32SemVal; + + // + // Extract the bit position from the + // lock id. + // + ui32BitPos = ((ui32LockID >> 16) & 0x00FF); + + // + // Release the spin lock, only if already owned + // + if(HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) & (1 << ui32BitPos )) + { + ui32SemVal = (0xFFFFFFFF & ~(0x3 << ui32BitPos)); + HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) = ui32SemVal; + } +} + +//***************************************************************************** +// +//! Get the current or previous ownership status. +//! +//! \param ui32LockID is one of the valid spin lock. +//! \param bCurrentStatus is \b true for current status, \b flase otherwise +//! +//! This function gets the current or previous ownership status of the +//! specified spin lock based on \e bCurrentStatus parameter. +//! +//! \return Returns \b HWSPINLOCK_OWNER_APPS, \b HWSPINLOCK_OWNER_NWP or +//! \b HWSPINLOCK_OWNER_NONE. +// +//***************************************************************************** +uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus) +{ + uint32_t ui32BitPos; + uint32_t ui32SemVal; + + if(bCurrentStatus) + { + // + // Extract the bit position from the + // lock id. + // + ui32BitPos = ((ui32LockID >> 16) & 0x00FF); + + // + // return semaphore + // + return((HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) >> ui32BitPos ) & 0x3 ); + } + else + { + // + // Extract the bit position + // + ui32BitPos = ((ui32LockID >> 24) & 0xFF); + + // + // Identify which register to read + // + if(ui32LockID & 0xF > 4) + { + ui32SemVal = ((HWREG(COMMON_REG_BASE + + COMMON_REG_O_SEMAPHORE_PREV_OWNER1) >> ui32BitPos ) & 0x3); + } + else + { + ui32SemVal = ((HWREG(COMMON_REG_BASE + + COMMON_REG_O_SEMAPHORE_PREV_OWNER2) >> ui32BitPos ) & 0x3); + } + + // + // return the owner + // + return ui32SemVal; + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/hwspinlock.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/hwspinlock.h new file mode 100644 index 000000000..47285da57 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/hwspinlock.h @@ -0,0 +1,90 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// hwspinlock.h +// +// Prototypes for the Apps-NWP spinlock. +// +//***************************************************************************** + +#ifndef __HWSPINLOCK_H__ +#define __HWSPINLOCK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// values that can be passed to API as ui32LockID parameter +//***************************************************************************** +#define HWSPINLOCK_SSPI 0x02000000 + +//***************************************************************************** +// Values that are returned from HwSpinLockTest() +//***************************************************************************** +#define HWSPINLOCK_OWNER_APPS 0x00000001 +#define HWSPINLOCK_OWNER_NWP 0x00000002 +#define HWSPINLOCK_OWNER_NONE 0x00000000 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void HwSpinLockAcquire(uint32_t ui32LockID); +extern int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry); +extern void HwSpinLockRelease(uint32_t ui32LockID); +extern uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HWSPINLOCK_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/i2c.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/i2c.h new file mode 100644 index 000000000..9216d65a6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/i2c.h @@ -0,0 +1,366 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// i2c.h +// +// Prototypes for the I2C Driver. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_I2C_H__ +#define __DRIVERLIB_I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_QUICK_COMMAND \ + 0x00000027 +#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ + 0x00000013 +#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ + 0x00000042 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ + 0x00000040 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ + 0x0000004a +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ + 0x00000048 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 + +//***************************************************************************** +// +// I2C Master glitch filter configuration. +// +//***************************************************************************** +#define I2C_MASTER_GLITCH_FILTER_DISABLED \ + 0 +#define I2C_MASTER_GLITCH_FILTER_1 \ + 0x00010000 +#define I2C_MASTER_GLITCH_FILTER_2 \ + 0x00020000 +#define I2C_MASTER_GLITCH_FILTER_3 \ + 0x00030000 +#define I2C_MASTER_GLITCH_FILTER_4 \ + 0x00040000 +#define I2C_MASTER_GLITCH_FILTER_8 \ + 0x00050000 +#define I2C_MASTER_GLITCH_FILTER_16 \ + 0x00060000 +#define I2C_MASTER_GLITCH_FILTER_32 \ + 0x00070000 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 +#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave +#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command +#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// I2C Master interrupts. +// +//***************************************************************************** +#define I2C_MASTER_INT_RX_FIFO_FULL \ + 0x00000800 // RX FIFO Full Interrupt +#define I2C_MASTER_INT_TX_FIFO_EMPTY \ + 0x00000400 // TX FIFO Empty Interrupt +#define I2C_MASTER_INT_RX_FIFO_REQ \ + 0x00000200 // RX FIFO Request Interrupt +#define I2C_MASTER_INT_TX_FIFO_REQ \ + 0x00000100 // TX FIFO Request Interrupt +#define I2C_MASTER_INT_ARB_LOST \ + 0x00000080 // Arb Lost Interrupt +#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt +#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt +#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt +#define I2C_MASTER_INT_TX_DMA_DONE \ + 0x00000008 // TX DMA Complete Interrupt +#define I2C_MASTER_INT_RX_DMA_DONE \ + 0x00000004 // RX DMA Complete Interrupt +#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt +#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave interrupts. +// +//***************************************************************************** +#define I2C_SLAVE_INT_RX_FIFO_FULL \ + 0x00000100 // RX FIFO Full Interrupt +#define I2C_SLAVE_INT_TX_FIFO_EMPTY \ + 0x00000080 // TX FIFO Empty Interrupt +#define I2C_SLAVE_INT_RX_FIFO_REQ \ + 0x00000040 // RX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_FIFO_REQ \ + 0x00000020 // TX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_DMA_DONE \ + 0x00000010 // TX DMA Complete Interrupt +#define I2C_SLAVE_INT_RX_DMA_DONE \ + 0x00000008 // RX DMA Complete Interrupt +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave FIFO configuration macros. +// +//***************************************************************************** +#define I2C_SLAVE_TX_FIFO_ENABLE \ + 0x00000002 +#define I2C_SLAVE_RX_FIFO_ENABLE \ + 0x00000004 + +//***************************************************************************** +// +// I2C FIFO configuration macros. +// +//***************************************************************************** +#define I2C_FIFO_CFG_TX_MASTER 0x00000000 +#define I2C_FIFO_CFG_TX_SLAVE 0x00008000 +#define I2C_FIFO_CFG_RX_MASTER 0x00000000 +#define I2C_FIFO_CFG_RX_SLAVE 0x80000000 +#define I2C_FIFO_CFG_TX_MASTER_DMA \ + 0x00002000 +#define I2C_FIFO_CFG_TX_SLAVE_DMA \ + 0x0000a000 +#define I2C_FIFO_CFG_RX_MASTER_DMA \ + 0x20000000 +#define I2C_FIFO_CFG_RX_SLAVE_DMA \ + 0xa0000000 +#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 +#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 +#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 +#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 +#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 +#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 +#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 +#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 +#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 +#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 +#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 +#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 +#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 +#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 +#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 +#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 + +//***************************************************************************** +// +// I2C FIFO status. +// +//***************************************************************************** +#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ + 0x00040000 +#define I2C_FIFO_RX_FULL 0x00020000 +#define I2C_FIFO_RX_EMPTY 0x00010000 +#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ + 0x00000004 +#define I2C_FIFO_TX_FULL 0x00000002 +#define I2C_FIFO_TX_EMPTY 0x00000001 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void)); +extern void I2CIntUnregister(uint32_t ui32Base); +extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CTxFIFOFlush(uint32_t ui32Base); +extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CRxFIFOFlush(uint32_t ui32Base); +extern uint32_t I2CFIFOStatus(uint32_t ui32Base); +extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data); +extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, + uint8_t ui8Data); +extern uint32_t I2CFIFODataGet(uint32_t ui32Base); +extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, + uint8_t *pui8Data); +extern void I2CMasterBurstLengthSet(uint32_t ui32Base, + uint8_t ui8Length); +extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base); +extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, + uint32_t ui32Config); +extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CSlaveFIFODisable(uint32_t ui32Base); +extern bool I2CMasterBusBusy(uint32_t ui32Base); +extern bool I2CMasterBusy(uint32_t ui32Base); +extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd); +extern uint32_t I2CMasterDataGet(uint32_t ui32Base); +extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CMasterDisable(uint32_t ui32Base); +extern void I2CMasterEnable(uint32_t ui32Base); +extern uint32_t I2CMasterErr(uint32_t ui32Base); +extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast); +extern void I2CMasterIntClear(uint32_t ui32Base); +extern void I2CMasterIntDisable(uint32_t ui32Base); +extern void I2CMasterIntEnable(uint32_t ui32Base); +extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked); +extern void I2CMasterIntEnableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern void I2CMasterIntClearEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value); +extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable); +extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK); +extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base); +extern void I2CMasterSlaveAddrSet(uint32_t ui32Base, + uint8_t ui8SlaveAddr, + bool bReceive); +extern uint32_t I2CSlaveDataGet(uint32_t ui32Base); +extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CSlaveDisable(uint32_t ui32Base); +extern void I2CSlaveEnable(uint32_t ui32Base); +extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr); +extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, + uint8_t ui8SlaveAddr); +extern void I2CSlaveIntClear(uint32_t ui32Base); +extern void I2CSlaveIntDisable(uint32_t ui32Base); +extern void I2CSlaveIntEnable(uint32_t ui32Base); +extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void I2CSlaveIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); +extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern uint32_t I2CSlaveStatus(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_I2C_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/i2s.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/i2s.h new file mode 100644 index 000000000..996d0d366 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/i2s.h @@ -0,0 +1,223 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// i2s.h +// +// Defines and Macros for the I2S. +// +//***************************************************************************** + +#ifndef __I2S_H__ +#define __I2S_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// I2S DMA ports. +// +//***************************************************************************** +#define I2S_TX_DMA_PORT 0x4401E200 +#define I2S_RX_DMA_PORT 0x4401E280 + +//***************************************************************************** +// +// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter. +// +//***************************************************************************** +#define I2S_SLOT_SIZE_8 0x00300032 +#define I2S_SLOT_SIZE_16 0x00700074 +#define I2S_SLOT_SIZE_24 0x00B000B6 + + +#define I2S_PORT_CPU 0x00080008 +#define I2S_PORT_DMA 0x00000000 + +#define I2S_MODE_MASTER 0x00000000 +#define I2S_MODE_SLAVE 0x00008000 + +//***************************************************************************** +// +// Values that can be passed as ulDataLine parameter. +// +//***************************************************************************** +#define I2S_DATA_LINE_0 0x00000001 +#define I2S_DATA_LINE_1 0x00000002 + +//***************************************************************************** +// +// Values that can be passed to I2SSerializerConfig() as the ulSerMode +// parameter. +// +//***************************************************************************** +#define I2S_SER_MODE_TX 0x00000001 +#define I2S_SER_MODE_RX 0x00000002 +#define I2S_SER_MODE_DISABLE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to I2SSerializerConfig() as the ulInActState +// parameter. +// +//***************************************************************************** +#define I2S_INACT_TRI_STATE 0x00000000 +#define I2S_INACT_LOW_LEVEL 0x00000008 +#define I2S_INACT_HIGH_LEVEL 0x0000000C + +//***************************************************************************** +// +// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the +// ulIntFlags parameter. +// +//***************************************************************************** +#define I2S_INT_XUNDRN 0x00000001 +#define I2S_INT_XSYNCERR 0x00000002 +#define I2S_INT_XLAST 0x00000010 +#define I2S_INT_XDATA 0x00000020 +#define I2S_INT_XSTAFRM 0x00000080 +#define I2S_INT_XDMA 0x80000000 +#define I2S_INT_ROVRN 0x00010000 +#define I2S_INT_RSYNCERR 0x00020000 +#define I2S_INT_RLAST 0x00100000 +#define I2S_INT_RDATA 0x00200000 +#define I2S_INT_RSTAFRM 0x00800000 +#define I2S_INT_RDMA 0x40000000 + + +//***************************************************************************** +// +// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet +// +//***************************************************************************** +#define I2S_ACT_SLOT_EVEN 0x00000001 +#define I2S_ACT_SLOT_ODD 0x00000002 + +//***************************************************************************** +// +// Values that can be passed to I2SIntClear() as the +// ulIntFlags parameter and returned from I2SIntStatus(). +// +//***************************************************************************** +#define I2S_STS_XERR 0x00000100 +#define I2S_STS_XDMAERR 0x00000080 +#define I2S_STS_XSTAFRM 0x00000040 +#define I2S_STS_XDATA 0x00000020 +#define I2S_STS_XLAST 0x00000010 +#define I2S_STS_XSYNCERR 0x00000002 +#define I2S_STS_XUNDRN 0x00000001 +#define I2S_STS_XDMA 0x80000000 +#define I2S_STS_RERR 0x01000000 +#define I2S_STS_RDMAERR 0x00800000 +#define I2S_STS_RSTAFRM 0x00400000 +#define I2S_STS_RDATA 0x00200000 +#define I2S_STS_RLAST 0x00100000 +#define I2S_STS_RSYNCERR 0x00020000 +#define I2S_STS_ROVERN 0x00010000 +#define I2S_STS_RDMA 0x40000000 + +//***************************************************************************** +// +// Values that can be passed to I2SEnable() as the ulMode parameter. +// +//***************************************************************************** +#define I2S_MODE_TX_ONLY 0x00000001 +#define I2S_MODE_TX_RX_SYNC 0x00000003 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void I2SEnable(unsigned long ulBase, unsigned long ulMode); +extern void I2SDisable(unsigned long ulBase); + +extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine, + unsigned long ulData); +extern long I2SDataPutNonBlocking(unsigned long ulBase, + unsigned long ulDataLine, unsigned long ulData); + +extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine, + unsigned long *pulData); +extern long I2SDataGetNonBlocking(unsigned long ulBase, + unsigned long ulDataLine, unsigned long *pulData); + +extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk, + unsigned long ulBitClk, unsigned long ulConfig); + +extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulWordsPerTransfer); +extern void I2STxFIFODisable(unsigned long ulBase); +extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel, + unsigned long ulWordsPerTransfer); +extern void I2SRxFIFODisable(unsigned long ulBase); +extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase); +extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase); + +extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine, + unsigned long ulSerMode, unsigned long ulInActState); + +extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long I2SIntStatus(unsigned long ulBase); +extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void I2SIntUnregister(unsigned long ulBase); +extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot); +extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif //__I2S_H__ + diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/interrupt.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/interrupt.c new file mode 100644 index 000000000..bd3e56b55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/interrupt.c @@ -0,0 +1,774 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// interrupt.c +// +// Driver for the NVIC Interrupt Controller. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// This is a mapping between priority grouping encodings and the number of +// preemption priority bits. +// +//***************************************************************************** +static const unsigned long g_pulPriority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number and the register that contains +// the priority encoding for that interrupt. +// +//***************************************************************************** +static const unsigned long g_pulRegs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13, + NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19, + NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25, + NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31, + NVIC_PRI32, NVIC_PRI33, NVIC_PRI34, NVIC_PRI35, NVIC_PRI36, NVIC_PRI37, + NVIC_PRI38, NVIC_PRI39, NVIC_PRI40, NVIC_PRI41, NVIC_PRI42, NVIC_PRI43, + NVIC_PRI44, NVIC_PRI45, NVIC_PRI46, NVIC_PRI47, NVIC_PRI48 + +}; + + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt enable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulEnRegs[] = +{ + NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4, NVIC_EN5 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt disable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulDisRegs[] = +{ + NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4, NVIC_DIS5 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt pend for that interrupt. +// +//***************************************************************************** +static const unsigned long g_pulPendRegs[] = +{ + NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4, NVIC_PEND5 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt unpend for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulUnpendRegs[] = +{ + NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4, + NVIC_UNPEND5 +}; + + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! Allows the processor to respond to interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! tBoolean, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +tBoolean +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + return(CPUcpsie()); +} + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! Prevents the processor from receiving interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! tBoolean, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +tBoolean +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + return(CPUcpsid()); +} +//***************************************************************************** +// +//! Sets the NVIC VTable base. +//! +//! \param ulVtableBase specifies the new base address of VTable +//! +//! This function is used to specify a new base address for the VTable. +//! This function must be called before using IntRegister() for registering +//! any interrupt handler. +//! +//! +//! \return None. +// +//***************************************************************************** +void +IntVTableBaseSet(unsigned long ulVtableBase) +{ + HWREG(NVIC_VTABLE) = ulVtableBase; +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function will be called in +//! interrupt context. Since the handler function can preempt other code, care +//! must be taken to protect memory or peripherals that are accessed by the +//! handler and other non-handler code. +//! +//! +//! \return None. +// +//***************************************************************************** +void +IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) +{ + unsigned long *ulNvicTbl; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE); + ulNvicTbl[ulInterrupt]= (unsigned long)pfnHandler; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source will be +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +IntUnregister(unsigned long ulInterrupt) +{ + unsigned long *ulNvicTbl; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE); + ulNvicTbl[ulInterrupt]= (unsigned long)IntDefaultHandler; +} + +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +//! +//! \param ulBits specifies the number of bits of preemptable priority. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. The range of +//! the grouping values are dependent upon the hardware implementation; on +//! the CC3200 , three bits are available for hardware interrupt +//! prioritization and therefore priority grouping values of three through +//! seven have the same effect. +//! +//! \return None. +// +//***************************************************************************** +void +IntPriorityGroupingSet(unsigned long ulBits) +{ + // + // Check the arguments. + // + ASSERT(ulBits < NUM_PRIORITY); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; +} + +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return The number of bits of preemptable priority. +// +//***************************************************************************** +unsigned long +IntPriorityGroupingGet(void) +{ + unsigned long ulLoop, ulValue; + + // + // Read the priority grouping. + // + ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++) + { + // + // Stop looping if this value matches. + // + if(ulValue == g_pulPriority[ulLoop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ulLoop); +} + +//***************************************************************************** +// +//! Sets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param ucPriority specifies the priority of the interrupt. +//! +//! This function is used to set the priority of an interrupt. When multiple +//! interrupts are asserted simultaneously, the ones with the highest priority +//! are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities; priority 0 is the highest +//! interrupt priority. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3), so any prioritization must be performed in +//! those bits. The remaining bits can be used to sub-prioritize the interrupt +//! sources, and may be used by the hardware priority mechanism on a future +//! part. This arrangement allows priorities to migrate to different NVIC +//! implementations without changing the gross prioritization of the +//! interrupts. +//! +//! The parameter \e ucPriority can be any one of the following +//! -\b INT_PRIORITY_LVL_0 +//! -\b INT_PRIORITY_LVL_1 +//! -\b INT_PRIORITY_LVL_2 +//! -\b INT_PRIORITY_LVL_3 +//! -\b INT_PRIORITY_LVL_4 +//! -\b INT_PRIORITY_LVL_5 +//! -\b INT_PRIORITY_LVL_6 +//! -\b INT_PRIORITY_LVL_7 +//! +//! \return None. +// +//***************************************************************************** +void +IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Set the interrupt priority. + // + ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); + ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); + ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); + HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function gets the priority of an interrupt. See IntPrioritySet() for +//! a definition of the priority value. +//! +//! \return Returns the interrupt priority, or -1 if an invalid interrupt was +//! specified. +// +//***************************************************************************** +long +IntPriorityGet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & + 0xFF); +} + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntEnable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt >= 16) + { + // + // Enable the general interrupt. + // + HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + __asm(" dsb "); + __asm(" isb "); + } +} + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntDisable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt >= 16) + { + // + // Disable the general interrupt. + // + HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + __asm(" dsb "); + __asm(" isb "); + } + +} + +//***************************************************************************** +// +//! Pends an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be pended. +//! +//! The specified interrupt is pended in the interrupt controller. This will +//! cause the interrupt controller to execute the corresponding interrupt +//! handler at the next available time, based on the current interrupt state +//! priorities. For example, if called by a higher priority interrupt handler, +//! the specified interrupt handler will not be called until after the current +//! interrupt handler has completed execution. The interrupt must have been +//! enabled for it to be called. +//! +//! \return None. +// +//***************************************************************************** +void +IntPendSet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to pend. + // + if(ulInterrupt == FAULT_NMI) + { + // + // Pend the NMI interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_PENDSV) + { + // + // Pend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Pend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt >= 16) + { + // + // Pend the general interrupt. + // + HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + __asm(" dsb "); + __asm(" isb "); + } + +} + +//***************************************************************************** +// +//! Unpends an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be unpended. +//! +//! The specified interrupt is unpended in the interrupt controller. This will +//! cause any previously generated interrupts that have not been handled yet +//! (due to higher priority interrupts or the interrupt no having been enabled +//! yet) to be discarded. +//! +//! \return None. +// +//***************************************************************************** +void +IntPendClear(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to unpend. + // + if(ulInterrupt == FAULT_PENDSV) + { + // + // Unpend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Unpend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if(ulInterrupt >= 16) + { + // + // Unpend the general interrupt. + // + HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Sets the priority masking level +//! +//! \param ulPriorityMask is the priority level that will be masked. +//! +//! This function sets the interrupt priority masking level so that all +//! interrupts at the specified or lesser priority level is masked. This +//! can be used to globally disable a set of interrupts with priority below +//! a predetermined threshold. A value of 0 disables priority +//! masking. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3), so any +//! prioritization must be performed in those bits. +//! +//! \return None. +// +//***************************************************************************** +void +IntPriorityMaskSet(unsigned long ulPriorityMask) +{ + CPUbasepriSet(ulPriorityMask); +} + +//***************************************************************************** +// +//! Gets the priority masking level +//! +//! This function gets the current setting of the interrupt priority masking +//! level. The value returned is the priority level such that all interrupts +//! of that and lesser priority are masked. A value of 0 means that priority +//! masking is disabled. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3), so any +//! prioritization must be performed in those bits. +//! +//! \return Returns the value of the interrupt priority level mask. +// +//***************************************************************************** +unsigned long +IntPriorityMaskGet(void) +{ + return(CPUbasepriGet()); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/interrupt.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/interrupt.h new file mode 100644 index 000000000..0dff66378 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/interrupt.h @@ -0,0 +1,125 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// interrupt.h +// +// Prototypes for the NVIC Interrupt Controller Driver. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + unsigned long ulPtr; +} +uVectorEntry; + + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. +// +//***************************************************************************** +#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) + +//***************************************************************************** +// Interrupt priority levels +//***************************************************************************** +#define INT_PRIORITY_LVL_0 0x00 +#define INT_PRIORITY_LVL_1 0x20 +#define INT_PRIORITY_LVL_2 0x40 +#define INT_PRIORITY_LVL_3 0x60 +#define INT_PRIORITY_LVL_4 0x80 +#define INT_PRIORITY_LVL_5 0xA0 +#define INT_PRIORITY_LVL_6 0xC0 +#define INT_PRIORITY_LVL_7 0xE0 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean IntMasterEnable(void); +extern tBoolean IntMasterDisable(void); +extern void IntVTableBaseSet(unsigned long ulVtableBase); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); +extern void IntPendSet(unsigned long ulInterrupt); +extern void IntPendClear(unsigned long ulInterrupt); +extern void IntPriorityMaskSet(unsigned long ulPriorityMask); +extern unsigned long IntPriorityMaskGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/pin.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/pin.c new file mode 100644 index 000000000..cac38236b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/pin.c @@ -0,0 +1,888 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// pin.c +// +// Mapping of peripherals to pins. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pin_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ocp_shared.h" +#include "pin.h" + +//***************************************************************************** +// Macros +//***************************************************************************** +#define PAD_MODE_MASK 0x0000000F +#define PAD_STRENGTH_MASK 0x000000E0 +#define PAD_TYPE_MASK 0x00000310 +#define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \ + OCP_SHARED_O_GPIO_PAD_CONFIG_0)) + +//***************************************************************************** +// PIN to PAD matrix +//***************************************************************************** +static const unsigned long g_ulPinToPadMap[64] = +{ + 10,11,12,13,14,15,16,17,255,255,18, + 19,20,21,22,23,24,40,28,29,25,255, + 255,255,255,255,255,255,255,255,255,255,255, + 255,255,255,255,255,255,255,255,255,255,255, + 31,255,255,255,255,0,255,32,30,255,1, + 255,2,3,4,5,6,7,8,9 +}; + + +//***************************************************************************** +// +//! Configures pin mux for the specified pin. +//! +//! \param ulPin is a valid pin. +//! \param ulPinMode is one of the valid mode +//! +//! This function configures the pin mux that selects the peripheral function +//! associated with a particular SOC pin. Only one peripheral function at a +//! time can be associated with a pin, and each peripheral function should +//! only be associated with a single pin at a time. +//! +//! \return none +// +//***************************************************************************** +void PinModeSet(unsigned long ulPin,unsigned long ulPinMode) +{ + + unsigned long ulPad; + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Set the mode. + // + HWREG(ulPad) = (((HWREG(ulPad) & ~PAD_MODE_MASK) | ulPinMode) & ~(3<<10)); + +} + +//***************************************************************************** +// +//! Gets current pin mux configuration of specified pin. +//! +//! \param ulPin is a valid pin. +//! +//! This function get the current configuration of the pin mux. +//! +//! \return Returns current pin mode if \e ulPin is valid, 0xFF otherwise. +// +//***************************************************************************** +unsigned long PinModeGet(unsigned long ulPin) +{ + + unsigned long ulPad; + + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE) ; + + // + // return the mode. + // + return (HWREG(ulPad) & PAD_MODE_MASK); + +} + +//***************************************************************************** +// +//! Sets the direction of the specified pin(s). +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinIO is the pin direction and/or mode. +//! +//! This function configures the specified pin(s) as either input only or +//! output only or it configures the pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b PIN_DIR_MODE_IN +//! - \b PIN_DIR_MODE_OUT +//! - \b PIN_DIR_MODE_HW +//! +//! where \b PIN_DIR_MODE_IN specifies that the pin is programmed as a +//! input only, \b PIN_DIR_MODE_OUT specifies that the pin is +//! programmed output only, and \b PIN_DIR_MODE_HW specifies that the pin is +//! placed under hardware control. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO) +{ + unsigned long ulPad; + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Set the direction + // + HWREG(ulPad) = ((HWREG(ulPad) & ~0xC00) | ulPinIO); +} + +//***************************************************************************** +// +//! Gets the direction of a pin. +//! +//! \param ulPin is one of the valid pin. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input only +//! or output only, or it can be under hardware control. The type of control +//! and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +unsigned long PinDirModeGet(unsigned long ulPin) +{ + unsigned long ulPad; + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Return the direction + // + return ((HWREG(ulPad) & 0xC00)); +} + +//***************************************************************************** +// +//! Gets Pin output drive strength and Type +//! +//! \param ulPin is one of the valid pin +//! \param pulPinStrength is pointer to storage for output drive strength +//! \param pulPinType is pinter to storage for pin type +//! +//! This function gets the pin type and output drive strength for the pin +//! specified by \e ulPin parameter. Parameters \e pulPinStrength and +//! \e pulPinType corresponds to the values used in PinConfigSet(). +//! +//! +//! \return None. +// +//***************************************************************************** +void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength, + unsigned long *pulPinType) +{ + + unsigned long ulPad; + + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + + // + // Get the type + // + *pulPinType = (HWREG(ulPad) & PAD_TYPE_MASK); + + // + // Get the output drive strength + // + *pulPinStrength = (HWREG(ulPad) & PAD_STRENGTH_MASK); + +} + +//***************************************************************************** +// +//! Configure Pin output drive strength and Type +//! +//! \param ulPin is one of the valid pin +//! \param ulPinStrength is logical OR of valid output drive strengths. +//! \param ulPinType is one of the valid pin type. +//! +//! This function sets the pin type and strength for the pin specified by +//! \e ulPin parameter. +//! +//! The parameter \e ulPinStrength should be one of the following +//! - \b PIN_STRENGTH_2MA +//! - \b PIN_STRENGTH_4MA +//! - \b PIN_STRENGTH_6MA +//! +//! +//! The parameter \e ulPinType should be one of the following +//! For standard type +//! +//! - \b PIN_TYPE_STD +//! - \b PIN_TYPE_STD_PU +//! - \b PIN_TYPE_STD_PD +//! +//! And for Open drain type +//! +//! - \b PIN_TYPE_OD +//! - \b PIN_TYPE_OD_PU +//! - \b PIN_TYPE_OD_PD +//! +//! \return None. +// +//***************************************************************************** +void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength, + unsigned long ulPinType) +{ + + unsigned long ulPad; + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Write the register + // + if(ulPinType == PIN_TYPE_ANALOG) + { + // + // Isolate the input + // + HWREG(0x4402E144) |= ((0x80 << ulPad) & (0x1E << 8)); + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Isolate the output + // + HWREG(ulPad) = 0xC00; + + } + else + { + // + // Enable the input + // + HWREG(0x4402E144) &= ~((0x80 << ulPad) & (0x1E << 8)); + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Write the configuration + // + HWREG(ulPad) = ((HWREG(ulPad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) | + (ulPinStrength | ulPinType )); + } + + +} + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by UART peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The UART pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! +//! \note This function cannot be used to turn any pin into a UART pin; it +//! only sets the pin mode and configures it for proper UART operation. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode) +{ + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD); +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by I2C peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The I2C pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! the pin. +//! +//! +//! \note This function cannot be used to turn any pin into a I2C pin; it +//! only sets the pin mode and configures it for proper I2C operation. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode) +{ + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for open-drain operation with a weak pull-up. + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_OD_PU); +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by SPI peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The SPI pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a SPI pin; it +//! only sets the pin mode and configures it for proper SPI operation. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode) +{ + + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); + +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by I2S peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The I2S pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a I2S pin; it +//! only sets the pin mode and configures it for proper I2S operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode) +{ + + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); + +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by Timer peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The timer PWM pins must be properly configured for the Timer peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin; other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! +//! \note This function cannot be used to turn any pin into a timer PWM pin; it +//! only sets the pin mode and configures it for proper timer PWM operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode) +{ + + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by Camera peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The Camera pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a Camera pin; it +//! only sets the pin mode and configures it for proper Camera operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode) +{ + + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); + +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by GPIO peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! \param bOpenDrain is one to decide either OpenDrain or STD +//! +//! The GPIO pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,tBoolean bOpenDrain) +{ + + // + // Set the pin for standard push-pull operation. + // + if(bOpenDrain) + { + PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_OD); + } + else + { + PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_STD); + } + + // + // Set the pin to specified mode + // + PinModeSet(ulPin, ulPinMode); + +} + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by ADC +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The ADC pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a ADC pin; it +//! only sets the pin mode and configures it for proper ADC operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode) +{ + // + // Configure the Pin + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by SD Host peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The MMC pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a SD Host pin; it +//! only sets the pin mode and configures it for proper SD Host operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode) +{ + // + // Set pin mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Configure the Pin + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD); + +} + + +//***************************************************************************** +// +//! Sets the hysteresis for all the pins +//! +//! \param ulHysteresis is one of the valid predefined hysterisys values +//! +//! This function sets the hysteresis vlaue for all the pins. The parameter +//! \e ulHysteresis can be on one the following: +//! -\b PIN_HYSTERESIS_OFF - To turn Off hysteresis, default on POR +//! -\b PIN_HYSTERESIS_10 - To turn On hysteresis, 10% +//! -\b PIN_HYSTERESIS_20 - To turn On hysteresis, 20% +//! -\b PIN_HYSTERESIS_30 - To turn On hysteresis, 30% +//! -\b PIN_HYSTERESIS_40 - To turn On hysteresis, 40% +//! +//! \return None. +// +//***************************************************************************** +void PinHysteresisSet(unsigned long ulHysteresis) +{ + unsigned long ulRegValue; + + // + // Read the current value + // + ulRegValue = (HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) + & ~(0x0000001C)); + + // + // Set the new Hysteresis + // + if( ulHysteresis != PIN_HYSTERESIS_OFF ) + { + ulRegValue |= (ulHysteresis & 0x0000001C); + } + + // + // Write the new value + // + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) = ulRegValue; +} + +//***************************************************************************** +// +//! Sets the level of the pin when locked +//! +//! \param ulPin is one of the valid pin. +//! \param ucLevel is the level the pin drives when locked +//! +//! This function sets the pin level when the pin is locked using +//! \sa PinLock() API. +//! +//! By default all pins are set to drive 0. +//! +//! \note Use case is to park the pins when entering LPDS +//! +//! \return None. +// +//***************************************************************************** +void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel) +{ + unsigned long ulPad; + + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Get the required bit + // + ulPad = 1 << ulPad; + + if(ucLevel) + { + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) |= ulPad; + } + else + { + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) &= ~ulPad; + } + } +} + +//***************************************************************************** +// +//! Locks all the pins to configured level(s). +//! +//! \param ulOutEnable the bit-packed representation of pins to be set as output +//! +//! This function locks all the pins to the pre-configure level. By default +//! the pins are set to drive 0. Default level can be changed using +//! \sa PinLockLevelSet() API. +//! +//! The \e ulOutEnable paramter is bit-packed representation of pins that +//! are required to be enabled as output. If a bit is set 1, the corresponding +//! pin (as shown below) are set and locked as output. +//! +//! |------|-----------------------------------------------| +//! | Bit |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |------|-----------------------------------------------| +//! | Pin |xx|xx|20|19|30|29|21|17|16|15|14|13|12|11|08|07| +//! |------|-----------------------------------------------| +//! +//! |------|-----------------------------------------------| +//! | Bit |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |------|-----------------------------------------------| +//! | Pin |06|05|04|03|02|01|64|63|62|61|60|59|58|57|55|50| +//! |------|-----------------------------------------------| +//! +//! +//! \note Use case is to park the pins when entering LPDS +//! +//! \return None. +// +//***************************************************************************** +void PinLock(unsigned long ulOutEnable) +{ + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Enable/disable the pin(s) output + // + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_7 ) = ~ulOutEnable; + + // + // Lock the pins to selected levels + // + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) |= (3 << 24); + } +} + +//***************************************************************************** +// +//! Unlocks all the pins. +//! +//! This function unlocks all the pins and can be used for peripheral function. +//! +//! By default all the pins are in unlocked state. +//! +//! \note Use case is to un-park the pins when exiting LPDS +//! +//! \return None. +// +//***************************************************************************** +void PinUnlock() +{ + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Unlock the pins + // + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) &= ~(3 << 24); + } +} + +//***************************************************************************** +// +// Gets pad number from pin number +// +// \param ulPin is a valid pin number +// +// This function return the pad corresponding to the specified pin +// +// \return Pad number on success, 0xFF otherwise +// +//***************************************************************************** +unsigned long PinToPadGet(unsigned long ulPin) +{ + // + // Return the corresponding Pad + // + return g_ulPinToPadMap[ulPin & 0x3F]; +} + + +//***************************************************************************** +// +// Gets pin number from pad number +// +// \param ulPad is a valid pad number +// +// This function return the pin corresponding to the specified pad +// +// \return Pin number on success, 0xFF otherwise +// +//***************************************************************************** +unsigned long PinFromPadGet(unsigned long ulPad) +{ + unsigned long ulPin; + + // + // search and return the pin number + // + for(ulPin=0; ulPin < sizeof(g_ulPinToPadMap)/4; ulPin++) + { + if(g_ulPinToPadMap[ulPin] == ulPad) + { + return ulPin; + } + } + + return 0xFF; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/pin.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/pin.h new file mode 100644 index 000000000..dc711c550 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/pin.h @@ -0,0 +1,195 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// pin.h +// +// Defines and Macros for the pin mux module +// +//***************************************************************************** + +#ifndef __PIN_H__ +#define __PIN_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// Macros Defining Pins +//***************************************************************************** + +#define PIN_01 0x00000000 +#define PIN_02 0x00000001 +#define PIN_03 0x00000002 +#define PIN_04 0x00000003 +#define PIN_05 0x00000004 +#define PIN_06 0x00000005 +#define PIN_07 0x00000006 +#define PIN_08 0x00000007 +#define PIN_11 0x0000000A +#define PIN_12 0x0000000B +#define PIN_13 0x0000000C +#define PIN_14 0x0000000D +#define PIN_15 0x0000000E +#define PIN_16 0x0000000F +#define PIN_17 0x00000010 +#define PIN_18 0x00000011 +#define PIN_19 0x00000012 +#define PIN_20 0x00000013 +#define PIN_21 0x00000014 +#define PIN_45 0x0000002C +#define PIN_46 0x0000002D +#define PIN_47 0x0000002E +#define PIN_48 0x0000002F +#define PIN_49 0x00000030 +#define PIN_50 0x00000031 +#define PIN_52 0x00000033 +#define PIN_53 0x00000034 +#define PIN_55 0x00000036 +#define PIN_56 0x00000037 +#define PIN_57 0x00000038 +#define PIN_58 0x00000039 +#define PIN_59 0x0000003A +#define PIN_60 0x0000003B +#define PIN_61 0x0000003C +#define PIN_62 0x0000003D +#define PIN_63 0x0000003E +#define PIN_64 0x0000003F + + + +//***************************************************************************** +// Macros that can be used with PinConfigSet(), PinTypeGet(), PinStrengthGet() +//***************************************************************************** + +#define PIN_MODE_0 0x00000000 +#define PIN_MODE_1 0x00000001 +#define PIN_MODE_2 0x00000002 +#define PIN_MODE_3 0x00000003 +#define PIN_MODE_4 0x00000004 +#define PIN_MODE_5 0x00000005 +#define PIN_MODE_6 0x00000006 +#define PIN_MODE_7 0x00000007 +#define PIN_MODE_8 0x00000008 +#define PIN_MODE_9 0x00000009 +#define PIN_MODE_10 0x0000000A +#define PIN_MODE_11 0x0000000B +#define PIN_MODE_12 0x0000000C +#define PIN_MODE_13 0x0000000D +#define PIN_MODE_14 0x0000000E +#define PIN_MODE_15 0x0000000F +// Note : PIN_MODE_255 is a dummy define for pinmux utility code generation +// PIN_MODE_255 should never be used in any user code. +#define PIN_MODE_255 0x000000FF + +//***************************************************************************** +// Macros that can be used with PinDirModeSet() and returned from +// PinDirModeGet(). +//***************************************************************************** +#define PIN_DIR_MODE_IN 0x00000C00 // Pin is input +#define PIN_DIR_MODE_OUT 0x00000800 // Pin is output +#define PIN_DIR_MODE_HW 0x00000000 // Pin is peripheral function + +//***************************************************************************** +// Macros that can be used with PinConfigSet() +//***************************************************************************** +#define PIN_STRENGTH_2MA 0x00000020 +#define PIN_STRENGTH_4MA 0x00000040 +#define PIN_STRENGTH_6MA 0x00000060 + +#define PIN_TYPE_STD 0x00000000 +#define PIN_TYPE_STD_PU 0x00000100 +#define PIN_TYPE_STD_PD 0x00000200 + +#define PIN_TYPE_OD 0x00000010 +#define PIN_TYPE_OD_PU 0x00000110 +#define PIN_TYPE_OD_PD 0x00000210 +#define PIN_TYPE_ANALOG 0x10000000 + +//***************************************************************************** +// Macros that can be used with PinHysteresisSet() +//***************************************************************************** +#define PIN_HYSTERESIS_OFF 0x00000000 +#define PIN_HYSTERESIS_10 0x00000004 +#define PIN_HYSTERESIS_20 0x0000000C +#define PIN_HYSTERESIS_30 0x00000014 +#define PIN_HYSTERESIS_40 0x0000001C + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PinModeSet(unsigned long ulPin, unsigned long ulPinMode); +extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO); +extern unsigned long PinDirModeGet(unsigned long ulPin); +extern unsigned long PinModeGet(unsigned long ulPin); +extern void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength, + unsigned long *pulPinType); +extern void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength, + unsigned long ulPinType); +extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode, + tBoolean bOpenDrain); +extern void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode); +extern void PinHysteresisSet(unsigned long ulHysteresis); +extern void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel); +extern void PinLock(unsigned long ulOutEnable); +extern void PinUnlock(void); +extern unsigned long PinToPadGet(unsigned long ulPin); +extern unsigned long PinFromPadGet(unsigned long ulPad); + +#ifdef __cplusplus +} +#endif + +#endif //__PIN_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/prcm.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/prcm.c new file mode 100644 index 000000000..ae6ad3f18 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/prcm.c @@ -0,0 +1,2699 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +//! \addtogroup PRCM_Power_Reset_Clock_Module_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_apps_rcm.h" +#include "inc/hw_gprcm.h" +#include "inc/hw_hib1p2.h" +#include "inc/hw_hib3p3.h" +#include "inc/hw_ocp_shared.h" +#include "inc/hw_common_reg.h" +#include "prcm.h" +#include "interrupt.h" +#include "cpu.h" +#include "flash.h" +#include "utils.h" + + +//***************************************************************************** +// Macro definition +//***************************************************************************** +#define PRCM_SOFT_RESET 0x00000001 +#define PRCM_ENABLE_STATUS 0x00000002 +#define SYS_CLK 80000000 +#define XTAL_CLK 40000000 + + +//***************************************************************************** +// CC3200 does not have a true RTC capability. However, API(s) in this file +// provide an effective mechanism to support RTC feature in the device. +// +// The implementation to support RTC has been kept very simple. A set of +// HIB Memory Registers in conjunction with Slow Clock Counter are used +// to render RTC information to users. Core principle of design involves +// two steps (a) establish an association between user provided wall-clock +// and slow clock counter. (b) store reference value of this associattion +// in HIB Registers. This reference value and SCC value are then combined +// to create real-world calendar time. +// +// Across HIB cycles, value stored in HIB Registers is retained and slow +// clock counter continues to tick, thereby, this arragement is relevant +// and valid as long as device has a (tickle) battery power. +// +// Further, provision also has been made to set an alarm. When it RTC value +// matches that of set for alarm, an interrupt is generated. +// +// HIB MEM REG0 and REG1 are reserved for TI. +// +// If RTC feature is not used, then HIB REG2 & REG3 are available to user. +// +// Lower half of REG0 is used for TI HW ECO. +//***************************************************************************** +#define RTC_U64MSEC_MK(u32Secs, u16Msec) (((unsigned long long)u32Secs << 10)|\ + (u16Msec & 0x3FF)) + +#define RTC_SECS_IN_U64MSEC(u64Msec) ((unsigned long)(u64Msec >> 10)) +#define RTC_MSEC_IN_U64MSEC(u64Msec) ((unsigned short)(u64Msec & 0x3FF)) + +#define RTC_SECS_U32_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG3) +#define RTC_MSEC_U16_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2+2) + +#define RTC_U32SECS_REG (HWREG(RTC_SECS_U32_REG_ADDR)) +#define RTC_U16MSEC_REG (*(unsigned short*)RTC_MSEC_U16_REG_ADDR) + +//***************************************************************************** +// Register Access and Updates +// +// Tick of SCC has a resolution of 32768Hz, meaning 1 sec is equal to 32768 +// clock ticks. Ideal way of getting time in millisecond will involve floating +// point arithmetic (division by 32.768). To avoid this, we simply divide it by +// 32, which will give a range from 0 -1023(instead of 0-999). To use this +// output correctly we have to take care of this inaccuracy externally. +// following wrapper can be used to convert the value from cycles to +// millisecond: +// +// CYCLES_U16MS(cycles) ((cycles *1000)/ 1024), +// +// Similarly, before setting the value, it must be first converted (from ms to +// cycles). +// +// U16MS_CYCLES(msec) ((msec *1024)/1000) +// +// Note: There is a precision loss of 1 ms with the above scheme. +// +//***************************************************************************** +#define SCC_U64MSEC_GET() (PRCMSlowClkCtrGet() >> 5) +#define SCC_U64MSEC_MATCH_SET(u64Msec) (PRCMSlowClkCtrMatchSet(u64Msec << 5)) +#define SCC_U64MSEC_MATCH_GET() (PRCMSlowClkCtrMatchGet() >> 5) + +//***************************************************************************** +// +// Bit: 31 is used to indicate use of RTC. If set as '1', RTC feature is used. +// Bits: 30 to 26 are reserved, available to software for use +// Bits: 25 to 16 are used to save millisecond part of RTC reference. +// Bits: 15 to 0 are being used for HW Changes / ECO +// +//***************************************************************************** + +//***************************************************************************** +// Set RTC USE Bit +//***************************************************************************** +static void RTCUseSet(void) +{ + unsigned short usRegValue; + + usRegValue = RTC_U16MSEC_REG | (1 << 15); + + UtilsDelay((80*200)/3); + + RTC_U16MSEC_REG = usRegValue; +} + +//***************************************************************************** +// Checks if RTC-USE bit is set +//***************************************************************************** +static tBoolean IsRTCUsed(void) +{ + unsigned short usRegValue; + + usRegValue = RTC_U16MSEC_REG; + + UtilsDelay((80*200)/3); + + return ((usRegValue & (1 << 15))? true : false); +} + +//***************************************************************************** +// Read 16-bit mSecs +//***************************************************************************** +static unsigned short RTCU16MSecRegRead(void) +{ + unsigned short usRegValue; + + usRegValue = RTC_U16MSEC_REG; + + UtilsDelay((80*200)/3); + + return (usRegValue & 0x3FF); +} + +//***************************************************************************** +// Write 16-bit mSecs +//***************************************************************************** +static void RTCU16MSecRegWrite(unsigned short u16Msec) +{ + unsigned short usRegValue; + + usRegValue = RTC_U16MSEC_REG; + + UtilsDelay((80*200)/3); + + RTC_U16MSEC_REG = ((usRegValue & ~0x3FF) |u16Msec); +} + +//***************************************************************************** +// Read 32-bit Secs +//***************************************************************************** +static unsigned long RTCU32SecRegRead(void) +{ + return (PRCMHIBRegRead(RTC_SECS_U32_REG_ADDR)); +} + +//***************************************************************************** +// Write 32-bit Secs +//***************************************************************************** +static void RTCU32SecRegWrite(unsigned long u32Msec) +{ + PRCMHIBRegWrite(RTC_SECS_U32_REG_ADDR, u32Msec); +} + +//***************************************************************************** +// Macros +//***************************************************************************** +#define IS_RTC_USED() IsRTCUsed() +#define RTC_USE_SET() RTCUseSet() + +#define RTC_U16MSEC_REG_RD() RTCU16MSecRegRead() +#define RTC_U16MSEC_REG_WR(u16Msec) RTCU16MSecRegWrite(u16Msec) + +#define RTC_U32SECS_REG_RD() RTCU32SecRegRead() +#define RTC_U32SECS_REG_WR(u32Secs) RTCU32SecRegWrite(u32Secs) + +#define SELECT_SCC_U42BITS(u64Msec) (u64Msec & 0x3ffffffffff) + +//***************************************************************************** +// Global Peripheral clock and rest Registers +//***************************************************************************** +static const PRCM_PeriphRegs_t PRCM_PeriphRegsList[] = +{ + + {APPS_RCM_O_CAMERA_CLK_GATING, APPS_RCM_O_CAMERA_SOFT_RESET }, + {APPS_RCM_O_MCASP_CLK_GATING, APPS_RCM_O_MCASP_SOFT_RESET }, + {APPS_RCM_O_MMCHS_CLK_GATING, APPS_RCM_O_MMCHS_SOFT_RESET }, + {APPS_RCM_O_MCSPI_A1_CLK_GATING, APPS_RCM_O_MCSPI_A1_SOFT_RESET }, + {APPS_RCM_O_MCSPI_A2_CLK_GATING, APPS_RCM_O_MCSPI_A2_SOFT_RESET }, + {APPS_RCM_O_UDMA_A_CLK_GATING, APPS_RCM_O_UDMA_A_SOFT_RESET }, + {APPS_RCM_O_GPIO_A_CLK_GATING, APPS_RCM_O_GPIO_A_SOFT_RESET }, + {APPS_RCM_O_GPIO_B_CLK_GATING, APPS_RCM_O_GPIO_B_SOFT_RESET }, + {APPS_RCM_O_GPIO_C_CLK_GATING, APPS_RCM_O_GPIO_C_SOFT_RESET }, + {APPS_RCM_O_GPIO_D_CLK_GATING, APPS_RCM_O_GPIO_D_SOFT_RESET }, + {APPS_RCM_O_GPIO_E_CLK_GATING, APPS_RCM_O_GPIO_E_SOFT_RESET }, + {APPS_RCM_O_WDOG_A_CLK_GATING, APPS_RCM_O_WDOG_A_SOFT_RESET }, + {APPS_RCM_O_UART_A0_CLK_GATING, APPS_RCM_O_UART_A0_SOFT_RESET }, + {APPS_RCM_O_UART_A1_CLK_GATING, APPS_RCM_O_UART_A1_SOFT_RESET }, + {APPS_RCM_O_GPT_A0_CLK_GATING , APPS_RCM_O_GPT_A0_SOFT_RESET }, + {APPS_RCM_O_GPT_A1_CLK_GATING, APPS_RCM_O_GPT_A1_SOFT_RESET }, + {APPS_RCM_O_GPT_A2_CLK_GATING, APPS_RCM_O_GPT_A2_SOFT_RESET }, + {APPS_RCM_O_GPT_A3_CLK_GATING, APPS_RCM_O_GPT_A3_SOFT_RESET }, + {APPS_RCM_O_CRYPTO_CLK_GATING, APPS_RCM_O_CRYPTO_SOFT_RESET }, + {APPS_RCM_O_MCSPI_S0_CLK_GATING, APPS_RCM_O_MCSPI_S0_SOFT_RESET }, + {APPS_RCM_O_I2C_CLK_GATING, APPS_RCM_O_I2C_SOFT_RESET } + +}; + +//***************************************************************************** +// +//! Performs a software reset of a MCU and associated peripherals +//! +//! \param bIncludeSubsystem is \b true to reset associated peripherals. +//! +//! This function performs a software reset of a MCU and associated peripherals. +//! To reset the associated peripheral, the parameter \e bIncludeSubsystem +//! should be set to \b true. +//! +//! \return None. +// +//***************************************************************************** +void PRCMMCUReset(tBoolean bIncludeSubsystem) +{ + if(bIncludeSubsystem) + { + // + // Reset Apps processor and associated peripheral + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x2; + } + else + { + // + // Reset Apps processor only + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x1; + } + + // + // Wait for system to enter hibernate + // + __asm(" wfi\n"); + + // + // Infinite loop + // + while(1) + { + + } +} + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function returns the reason(s) for a reset. The reset reason are:- +//! -\b PRCM_POWER_ON - Device is powering up. +//! -\b PRCM_LPDS_EXIT - Device is exiting from LPDS. +//! -\b PRCM_CORE_RESET - Device is exiting soft core only reset +//! -\b PRCM_MCU_RESET - Device is exiting soft subsystem reset. +//! -\b PRCM_WDT_RESET - Device was reset by watchdog. +//! -\b PRCM_SOC_RESET - Device is exting SOC reset. +//! -\b PRCM_HIB_EXIT - Device is exiting hibernate. +//! +//! \return Returns one of the cause defined above. +// +//***************************************************************************** +unsigned long PRCMSysResetCauseGet() +{ + unsigned long ulWakeupStatus; + + // + // Read the Reset status + // + ulWakeupStatus = (HWREG(GPRCM_BASE+ GPRCM_O_APPS_RESET_CAUSE) & 0xFF); + + // + // For hibernate do additional check. + // + if(ulWakeupStatus == PRCM_POWER_ON) + { + if(PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS) & 0x1) + { + ulWakeupStatus = PRCM_HIB_EXIT; + + if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000280)) == 0x00000280 ) + { + ulWakeupStatus = PRCM_WDT_RESET; + } + } + } + else if((ulWakeupStatus == PRCM_LPDS_EXIT) && + !(HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG1) & (1 <<2)) ) + { + if(HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x1<<8)) + { + ulWakeupStatus = PRCM_POWER_ON; + } + } + + // + // Return status. + // + return ulWakeupStatus; +} + +//***************************************************************************** +// +//! Enable clock(s) to peripheral. +//! +//! \param ulPeripheral is one of the valid peripherals +//! \param ulClkFlags are bitmask of clock(s) to be enabled. +//! +//! This function enables the clock for the specified peripheral. Peripherals +//! are by default clock gated (disabled) and generates a bus fault if +//! accessed. +//! +//! The parameter \e ulClkFlags can be logical OR of the following: +//! -\b PRCM_RUN_MODE_CLK - Ungates clock to the peripheral +//! -\b PRCM_SLP_MODE_CLK - Keeps the clocks ungated in sleep. +//! +//! \return None. +// +//***************************************************************************** +void +PRCMPeripheralClkEnable(unsigned long ulPeripheral, unsigned long ulClkFlags) +{ + // + // Enable the specified peripheral clocks, Nothing to be done for PRCM_ADC + // as it is a dummy define for pinmux utility code generation + // + if(ulPeripheral != PRCM_ADC) + { + HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags; + } + + // + // Checking ROM Version less than 2.x.x. + // Only for driverlib backward compatibility + // + if( (HWREG(0x00000400) & 0xFFFF) < 2 ) + { + // + // Set the default clock for camera + // + if(ulPeripheral == PRCM_CAMERA) + { + HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404; + } + } +} + +//***************************************************************************** +// +//! Disables clock(s) to peripheral. +//! +//! \param ulPeripheral is one of the valid peripherals +//! \param ulClkFlags are bitmask of clock(s) to be enabled. +//! +//! This function disable the clock for the specified peripheral. Peripherals +//! are by default clock gated (disabled) and generated a bus fault if +//! accessed. +//! +//! The parameter \e ulClkFlags can be logical OR bit fields as defined in +//! PRCMEnablePeripheral(). +//! +//! \return None. +// +//***************************************************************************** +void +PRCMPeripheralClkDisable(unsigned long ulPeripheral, unsigned long ulClkFlags) +{ + // + // Disable the specified peripheral clocks + // + HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) &= ~ulClkFlags; +} + +//***************************************************************************** +// +//! Gets the input clock for the specified peripheral. +//! +//! \param ulPeripheral is one of the valid peripherals. +//! +//! This function gets the input clock for the specified peripheral. +//! +//! The parameter \e ulPeripheral has the same definition as that in +//! PRCMPeripheralClkEnable(); +//! +//! \return Returns input clock frequency for specified peripheral. +// +//***************************************************************************** +unsigned long +PRCMPeripheralClockGet(unsigned long ulPeripheral) +{ + unsigned long ulClockFreq; + unsigned long ulHiPulseDiv; + unsigned long ulLoPulseDiv; + + // + // Get the clock based on specified peripheral. + // + if(((ulPeripheral == PRCM_SSPI) | (ulPeripheral == PRCM_LSPI) + | (ulPeripheral == PRCM_GSPI))) + { + return XTAL_CLK; + } + else if(ulPeripheral == PRCM_CAMERA) + { + ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) >> 8) & 0x07); + ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN)& 0xFF); + } + else if(ulPeripheral == PRCM_SDHOST) + { + ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) >> 8) & 0x07); + ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN)& 0xFF); + } + else + { + return SYS_CLK; + } + + // + // Compute the clock freq. from the divider value + // + ulClockFreq = (240000000/((ulHiPulseDiv + 1) + (ulLoPulseDiv + 1))); + + // + // Return the clock rate. + // + return ulClockFreq; +} + +//***************************************************************************** +// +//! Performs a software reset of a peripheral. +//! +//! \param ulPeripheral is one of the valid peripheral. +//! +//! This function does soft reset of the specified peripheral +//! +//! \return None. +// +//***************************************************************************** +void +PRCMPeripheralReset(unsigned long ulPeripheral) +{ + volatile unsigned long ulDelay; + + if( ulPeripheral != PRCM_DTHE) + { + // + // Assert the reset + // + HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg) + |= PRCM_SOFT_RESET; + // + // Delay a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Deassert the reset + // + HWREG(ARCM_BASE+PRCM_PeriphRegsList[ulPeripheral].ulRstReg) + &= ~PRCM_SOFT_RESET; + } +} + +//***************************************************************************** +// +//! Determines if a peripheral is ready. +//! +//! \param ulPeripheral is one of the valid modules +//! +//! This function determines if a particular peripheral is ready to be +//! accessed. The peripheral may be in a non-ready state if it is not enabled, +//! is being held in reset, or is in the process of becoming ready after being +//! enabled or taken out of reset. +//! +//! \return Returns \b true if the peripheral is ready, \b false otherwise. +// +//***************************************************************************** +tBoolean +PRCMPeripheralStatusGet(unsigned long ulPeripheral) +{ + unsigned long ReadyBit; + + // + // Read the ready bit status + // + ReadyBit = HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg); + ReadyBit = ReadyBit & PRCM_ENABLE_STATUS; + + if (ReadyBit) + { + // + // Module is ready + // + return(true); + } + else + { + // + // Module is not ready + // + return(false); + } +} + +//***************************************************************************** +// +//! Configure I2S fracactional divider +//! +//! \param ulI2CClkFreq is the required input clock for McAPS module +//! +//! This function configures I2S fractional divider. By default this +//! divider is set to output 24 Mhz clock to I2S module. +//! +//! The minimum frequency that can be obtained by configuring this divider is +//! +//! (240000KHz/1023.99) = 234.377 KHz +//! +//! \return None. +// +//***************************************************************************** +void +PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq) +{ + unsigned long long ullDiv; + unsigned short usInteger; + unsigned short usFrac; + + ullDiv = (((unsigned long long)240000000 * 65536)/ulI2CClkFreq); + + usInteger = (ullDiv/65536); + usFrac = (ullDiv%65536); + + HWREG(ARCM_BASE + APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0) = + ((usInteger & 0x3FF) << 16 | usFrac); +} + +//***************************************************************************** +// +//! Sets the LPDS exit PC and SP restore vlaues. +//! +//! \param ulStackPtr is the SP restore value. +//! \param ulProgCntr is the PC restore value +//! +//! This function sets the LPDS exit PC and SP restore vlaues. Setting +//! \e ulProgCntr to a non-zero value, forces bootloader to jump to that +//! address with Stack Pointer initialized to \e ulStackPtr on LPDS exit, +//! otherwise the application's vector table entries are used. +//! +//! \return None. +// +//***************************************************************************** +void +PRCMLPDSRestoreInfoSet(unsigned long ulStackPtr, unsigned long ulProgCntr) +{ + // + // ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Set The SP Value + // + HWREG(0x4402E160) = ulStackPtr; + + // + // Set The PC Value + // + HWREG(0x4402E198) = ulProgCntr; + + } + else + { + // + // Set The SP Value + // + HWREG(0x4402E18C) = ulStackPtr; + + // + // Set The PC Value + // + HWREG(0x4402E190) = ulProgCntr; + } +} + +//***************************************************************************** +// +//! Puts the system into Low Power Deel Sleep (LPDS) power mode. +//! +//! This function puts the system into Low Power Deel Sleep (LPDS) power mode. +//! A call to this function never returns and the execution starts from Reset. +//! \sa PRCMLPDSRestoreInfoSet(). +//! +//! \return None. +//! +//! \note External debugger will always disconnect whenever the system +//! enters LPDS and debug interface is shutdown until next POR reset. In order +//! to avoid this and allow for connecting back the debugger after waking up +//! from LPDS \sa PRCMLPDSEnterKeepDebugIf(). +//! +// +//***************************************************************************** +void +PRCMLPDSEnter() +{ + unsigned long ulChipId; + + // + // Read the Chip ID + // + ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); + + // + // Check if flash exists + // + if( (0x11 == ulChipId) || (0x19 == ulChipId)) + { + + // + // Disable the flash + // + FlashDisable(); + } + +#ifndef KEEP_TESTPD_ALIVE + + // + // Disable TestPD + // + HWREG(0x4402E168) |= (1<<9); +#endif + + // + // Set bandgap duty cycle to 1 + // + HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; + + // + // Request LPDS + // + HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) + = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ; + + // + // Wait for system to enter LPDS + // + __asm(" wfi\n"); + + // + // Infinite loop + // + while(1) + { + + } + +} + + +//***************************************************************************** +// +//! Puts the system into Low Power Deel Sleep (LPDS) power mode keeping +//! debug interface alive. +//! +//! This function puts the system into Low Power Deel Sleep (LPDS) power mode +//! keeping debug interface alive. A call to this function never returns and the +//! execution starts from Reset \sa PRCMLPDSRestoreInfoSet(). +//! +//! \return None. +//! +//! \note External debugger will always disconnect whenever the system +//! enters LPDS, using this API will allow connecting back the debugger after +//! waking up from LPDS. This API is recommended for development purposes +//! only as it adds to the current consumption of the system. +//! +// +//***************************************************************************** +void +PRCMLPDSEnterKeepDebugIf() +{ + unsigned long ulChipId; + + // + // Read the Chip ID + // + ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); + + // + // Check if flash exists + // + if( (0x11 == ulChipId) || (0x19 == ulChipId)) + { + + // + // Disable the flash + // + FlashDisable(); + } + + // + // Set bandgap duty cycle to 1 + // + HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; + + // + // Request LPDS + // + HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) + = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ; + + // + // Wait for system to enter LPDS + // + __asm(" wfi\n"); + + // + // Infinite loop + // + while(1) + { + + } + +} + +//***************************************************************************** +// +//! Enable the individual LPDS wakeup source(s). +//! +//! \param ulLpdsWakeupSrc is logical OR of wakeup sources. +//! +//! This function enable the individual LPDS wakeup source(s) and following +//! three wakeup sources (\e ulLpdsWakeupSrc ) are supported by the device. +//! -\b PRCM_LPDS_HOST_IRQ +//! -\b PRCM_LPDS_GPIO +//! -\b PRCM_LPDS_TIMER +//! +//! \return None. +// +//***************************************************************************** +void +PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc) +{ + unsigned long ulRegVal; + + // + // Read the current wakup sources + // + ulRegVal = HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG); + + // + // Enable individual wakeup source + // + ulRegVal = ((ulRegVal | ulLpdsWakeupSrc) & 0x91); + + // + // Set the configuration in the register + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) = ulRegVal; +} + +//***************************************************************************** +// +//! Disable the individual LPDS wakeup source(s). +//! +//! \param ulLpdsWakeupSrc is logical OR of wakeup sources. +//! +//! This function enable the individual LPDS wakeup source(s) and following +//! three wake up sources (\e ulLpdsWakeupSrc ) are supported by the device. +//! -\b PRCM_LPDS_HOST_IRQ +//! -\b PRCM_LPDS_GPIO +//! -\b PRCM_LPDS_TIMER +//! +//! \return None. +// +//***************************************************************************** +void +PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc) +{ + HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) &= ~ulLpdsWakeupSrc; +} + + +//***************************************************************************** +// +//! Get LPDS wakeup cause +//! +//! This function gets LPDS wakeup caouse +//! +//! \return Returns values enumerated as described in +//! PRCMLPDSWakeupSourceEnable(). +// +//***************************************************************************** +unsigned long +PRCMLPDSWakeupCauseGet() +{ + return (HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_SRC)); +} + +//***************************************************************************** +// +//! Sets LPDS wakeup Timer +//! +//! \param ulTicks is number of 32.768 KHz clocks +//! +//! This function sets internal LPDS wakeup timer running at 32.768 KHz. The +//! timer is only configured if the parameter \e ulTicks is in valid range i.e. +//! from 21 to 2^32. +//! +//! \return Returns \b true on success, \b false otherwise. +// +//***************************************************************************** +void +PRCMLPDSIntervalSet(unsigned long ulTicks) +{ + // + // Check sleep is atleast for 21 cycles + // If not set the sleep time to 21 cycles + // + if( ulTicks < 21) + { + ulTicks = 21; + } + + HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG) = ulTicks; + HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG) = ulTicks-20; +} + +//***************************************************************************** +// +//! Selects the GPIO for LPDS wakeup +//! +//! \param ulGPIOPin is one of the valid GPIO fro LPDS wakeup. +//! \param ulType is the wakeup trigger type. +//! +//! This function setects the wakeup GPIO for LPDS wakeup and can be +//! used to select one out of 7 pre-defined GPIO(s). +//! +//! The parameter \e ulLpdsGPIOSel should be one of the following:- +//! -\b PRCM_LPDS_GPIO2 +//! -\b PRCM_LPDS_GPIO4 +//! -\b PRCM_LPDS_GPIO13 +//! -\b PRCM_LPDS_GPIO17 +//! -\b PRCM_LPDS_GPIO11 +//! -\b PRCM_LPDS_GPIO24 +//! -\b PRCM_LPDS_GPIO26 +//! +//! The parameter \e ulType sets the trigger type and can be one of the +//! following: +//! - \b PRCM_LPDS_LOW_LEVEL +//! - \b PRCM_LPDS_HIGH_LEVEL +//! - \b PRCM_LPDS_FALL_EDGE +//! - \b PRCM_LPDS_RISE_EDGE +//! +//! \return None. +// +//***************************************************************************** +void +PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, unsigned long ulType) +{ + // + // Set the wakeup GPIO + // + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL, ulGPIOPin); + + // + // Set the trigger type. + // + HWREG(GPRCM_BASE + GPRCM_O_APPS_GPIO_WAKE_CONF) = (ulType & 0x3); +} + +//***************************************************************************** +// +//! Puts the system into Sleep. +//! +//! This function puts the system into sleep power mode. System exits the power +//! state on any one of the available interrupt. On exit from sleep mode the +//! function returns to the calling function with all the processor core +//! registers retained. +//! +//! \return None. +// +//***************************************************************************** +void +PRCMSleepEnter() +{ + // + // Request Sleep + // + CPUwfi(); +} + +//***************************************************************************** +// +//! Enable SRAM column retention during LPDS Power mode(s) +//! +//! \param ulSramColSel is bit mask of valid SRAM columns. +//! \param ulModeFlags is the bit mask of power modes. +//! +//! This functions enables the SRAM retention. The device supports configurable +//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is of +//! 64 KB size. +//! +//! The parameter \e ulSramColSel should be logical OR of the following:- +//! -\b PRCM_SRAM_COL_1 +//! -\b PRCM_SRAM_COL_2 +//! -\b PRCM_SRAM_COL_3 +//! -\b PRCM_SRAM_COL_4 +//! +//! The parameter \e ulModeFlags selects the power modes and sholud be logical +//! OR of one or more of the following +//! -\b PRCM_SRAM_LPDS_RET +//! +//! \return None. +// +//**************************************************************************** +void +PRCMSRAMRetentionEnable(unsigned long ulSramColSel, unsigned long ulModeFlags) +{ + if(ulModeFlags & PRCM_SRAM_LPDS_RET) + { + // + // Configure LPDS SRAM retention register + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) = (ulSramColSel & 0xF); + } +} + +//***************************************************************************** +// +//! Disable SRAM column retention during LPDS Power mode(s). +//! +//! \param ulSramColSel is bit mask of valid SRAM columns. +//! \param ulFlags is the bit mask of power modes. +//! +//! This functions disable the SRAM retention. The device supports configurable +//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is +//! of 64 KB size. +//! +//! The parameter \e ulSramColSel should be logical OR of the following:- +//! -\b PRCM_SRAM_COL_1 +//! -\b PRCM_SRAM_COL_2 +//! -\b PRCM_SRAM_COL_3 +//! -\b PRCM_SRAM_COL_4 +//! +//! The parameter \e ulFlags selects the power modes and sholud be logical OR +//! of one or more of the following +//! -\b PRCM_SRAM_LPDS_RET +//! +//! \return None. +// +//**************************************************************************** +void +PRCMSRAMRetentionDisable(unsigned long ulSramColSel, unsigned long ulFlags) +{ + if(ulFlags & PRCM_SRAM_LPDS_RET) + { + // + // Configure LPDS SRAM retention register + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) &= ~(ulSramColSel & 0xF); + } +} + + +//***************************************************************************** +// +//! Enables individual HIB wakeup source(s). +//! +//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources. +//! +//! This function enables individual HIB wakeup source(s). The paramter +//! \e ulHIBWakupSrc is the bit mask of HIB wakeup sources and should be +//! logical OR of one or more of the follwoing :- +//! -\b PRCM_HIB_SLOW_CLK_CTR +//! -\b PRCM_HIB_GPIO2 +//! -\b PRCM_HIB_GPIO4 +//! -\b PRCM_HIB_GPIO13 +//! -\b PRCM_HIB_GPIO17 +//! -\b PRCM_HIB_GPIO11 +//! -\b PRCM_HIB_GPIO24 +//! -\b PRCM_HIB_GPIO26 +//! +//! \return None. +// +//***************************************************************************** +void +PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc) +{ + unsigned long ulRegValue; + + // + // Read the RTC register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); + + // + // Enable the RTC as wakeup source if specified + // + ulRegValue |= (ulHIBWakupSrc & 0x1); + + // + // Enable HIB wakeup sources + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); + + // + // REad the GPIO wakeup configuration register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN); + + // + // Enable the specified GPIOs a wakeup sources + // + ulRegValue |= ((ulHIBWakupSrc>>16)&0xFF); + + // + // Write the new register configuration + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue); +} + +//***************************************************************************** +// +//! Disable individual HIB wakeup source(s). +//! +//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources. +//! +//! This function disable individual HIB wakeup source(s). The paramter +//! \e ulHIBWakupSrc is same as bit fileds defined in +//! PRCMEnableHibernateWakeupSource() +//! +//! \return None. +// +//***************************************************************************** +void +PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc) +{ + unsigned long ulRegValue; + + // + // Read the RTC register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); + + // + // Disable the RTC as wakeup source if specified + // + ulRegValue &= ~(ulHIBWakupSrc & 0x1); + + // + // Disable HIB wakeup sources + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); + + // + // Read the GPIO wakeup configuration register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN); + + // + // Enable the specified GPIOs a wakeup sources + // + ulRegValue &= ~((ulHIBWakupSrc>>16)&0xFF); + + // + // Write the new register configuration + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue); +} + + +//***************************************************************************** +// +//! Get hibernate wakeup cause +//! +//! This function gets the hibernate wakeup cause. +//! +//! \return Returns \b PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK or +//! \b PRCM_HIB_WAKEUP_CAUSE_GPIO +// +//***************************************************************************** +unsigned long +PRCMHibernateWakeupCauseGet() +{ + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + return ((PRCMHIBRegRead((OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8))>>2)&0xF); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Sets Hibernate wakeup Timer +//! +//! \param ullTicks is number of 32.768 KHz clocks +//! +//! This function sets internal hibernate wakeup timer running at 32.768 KHz. +//! +//! \return Returns \b true on success, \b false otherwise. +// +//***************************************************************************** +void +PRCMHibernateIntervalSet(unsigned long long ullTicks) +{ + unsigned long long ullRTCVal; + + // + // Latch the RTC vlaue + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1); + + // + // Read latched values as 2 32-bit vlaues + // + ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW); + ullRTCVal = ullRTCVal << 32; + ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW); + + // + // Add the interval + // + ullRTCVal = ullRTCVal + ullTicks; + + // + // Set RTC match value + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF, + (unsigned long)(ullRTCVal)); + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF, + (unsigned long)(ullRTCVal>>32)); +} + + +//***************************************************************************** +// +//! Selects the GPIO(s) for hibernate wakeup +//! +//! \param ulGPIOBitMap is the bit-map of valid hibernate wakeup GPIO. +//! \param ulType is the wakeup trigger type. +//! +//! This function setects the wakeup GPIO for hibernate and can be +//! used to select any combination of 7 pre-defined GPIO(s). +//! +//! This function enables individual HIB wakeup source(s). The paramter +//! \e ulGPIOBitMap should be one of the follwoing :- +//! -\b PRCM_HIB_GPIO2 +//! -\b PRCM_HIB_GPIO4 +//! -\b PRCM_HIB_GPIO13 +//! -\b PRCM_HIB_GPIO17 +//! -\b PRCM_HIB_GPIO11 +//! -\b PRCM_HIB_GPIO24 +//! -\b PRCM_HIB_GPIO26 +//! +//! The parameter \e ulType sets the trigger type and can be one of the +//! following: +//! - \b PRCM_HIB_LOW_LEVEL +//! - \b PRCM_HIB_HIGH_LEVEL +//! - \b PRCM_HIB_FALL_EDGE +//! - \b PRCM_HIB_RISE_EDGE +//! +//! \return None. +// +//***************************************************************************** +void +PRCMHibernateWakeUpGPIOSelect(unsigned long ulGPIOBitMap, unsigned long ulType) +{ + unsigned char ucLoop; + unsigned long ulRegValue; + + // + // Shift the bits to extract the GPIO selection + // + ulGPIOBitMap >>= 16; + + // + // Set the configuration for each GPIO + // + for(ucLoop=0; ucLoop < 7; ucLoop++) + { + if(ulGPIOBitMap & (1<>32)); +} + +//***************************************************************************** +// +//! Gets slow clock counter match value. +//! +//! This function gets the match value for slow clock counter. This is use +//! to interrupt the processor when RTC counts to the specified value. +//! +//! \return None. +// +//***************************************************************************** +unsigned long long PRCMSlowClkCtrMatchGet() +{ + unsigned long long ullValue; + + // + // Get RTC match value + // + ullValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF); + ullValue = ullValue<<32; + ullValue |= PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF); + + // + // Return the value + // + return ullValue; +} + + +//***************************************************************************** +// +//! Write to On-Chip Retention (OCR) register. +//! +//! This function writes to On-Chip retention register. The device supports two +//! 4-byte OCR register which are retained across all power mode. +//! +//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1. +//! +//! These registers are shared by the RTC implementation (if Driverlib RTC +//! APIs are used), ROM, and user application. +//! +//! When RTC APIs in use: +//! +//! |-----------------------------------------------| +//! | INDEX 1 | +//! |-----------------------------------------------| +//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |-----------------------------------------------| +//! | Reserved by RTC APIs - YY | +//! |-----------------------------------------------| +//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |-----------------------------------------------| +//! | Reserved by RTC APIs - YY | +//! |-----------------------------------------------| +//! +//! +//! |-----------------------------------------------| +//! | INDEX 0 | +//! |-----------------------------------------------| +//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |-----------------------------------------------| +//! | Reserved by RTC APIs - YY | +//! |-----------------------------------------------| +//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |-----------------------------------------------| +//! |YY| For User Application |XX| +//! |-----------------------------------------------| +//! +//! YY => Reserved by RTC APIs. If Driverlib RTC APIs are used +//! XX => Reserved by ROM +//! +//! +//! When RTC APIs are not in use: +//! +//! |-----------------------------------------------| +//! | INDEX 1 | +//! |-----------------------------------------------| +//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |-----------------------------------------------| +//! | For User Application | +//! |-----------------------------------------------| +//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |-----------------------------------------------| +//! | For User Application | +//! |-----------------------------------------------| +//! +//! +//! |-----------------------------------------------| +//! | INDEX 0 | +//! |-----------------------------------------------| +//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |-----------------------------------------------| +//! | For User Application | +//! |-----------------------------------------------| +//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |-----------------------------------------------| +//! | For User Application |XX| +//! |-----------------------------------------------| +//! +//! XX => Reserved by ROM +//! +//! +//! +//! \return None. +// +//***************************************************************************** +void PRCMOCRRegisterWrite(unsigned char ucIndex, unsigned long ulRegValue) +{ + unsigned long ulVal; + + // + // Compuitr the offset + // + ucIndex = ucIndex << 2; + + // + // If bit 0 is reserved + // + if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && + (ucIndex == 0) ) + { + ulVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex); + ulRegValue = ((ulRegValue << 0x1) | (ulVal & (0x1))); + } + + // + // Write thr value + // + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex,ulRegValue); + +} + +//***************************************************************************** +// +//! Read from On-Chip Retention (OCR) register. +//! +//! This function reads from On-Chip retention register. The device supports two +//! 4-byte OCR register which are retained across all power mode. +//! +//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1. +//! +//! \sa PRCMOCRRegisterWrite() for the register usage details. +//! +//! \return None. +// +//***************************************************************************** +unsigned long PRCMOCRRegisterRead(unsigned char ucIndex) +{ + unsigned long ulRet; + + // + // Read the OCR register + // + ulRet = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REG2 + (ucIndex << 2)); + + // + // If bit 0 is reserved + // + if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && + (ucIndex == 0) ) + { + ulRet = ulRet >> 0x1; + } + + // + // Return the read value. + // + return ulRet; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the PRCM. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; +//! +//! \return None. +// +//***************************************************************************** +void PRCMIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler. + // + IntRegister(INT_PRCM, pfnHandler); + + // + // Enable the PRCM interrupt. + // + IntEnable(INT_PRCM); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the PRCM. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a PRCM interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None. +// +//***************************************************************************** +void PRCMIntUnregister() +{ + // + // Enable the UART interrupt. + // + IntDisable(INT_PRCM); + + // + // Register the interrupt handler. + // + IntUnregister(INT_PRCM); +} + +//***************************************************************************** +// +//! Enables individual PRCM interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated ARCM interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! -\b PRCM_INT_SLOW_CLK_CTR +//! +// +//***************************************************************************** +void PRCMIntEnable(unsigned long ulIntFlags) +{ + unsigned long ulRegValue; + + if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR ) + { + // + // Enable PRCM interrupt + // + HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) |= 0x4; + + // + // Enable RTC interrupt + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE); + ulRegValue |= 0x1; + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue); + } +} + +//***************************************************************************** +// +//! Disables individual PRCM interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated ARCM interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to PRCMEnableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +void PRCMIntDisable(unsigned long ulIntFlags) +{ + unsigned long ulRegValue; + + if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR ) + { + // + // Disable PRCM interrupt + // + HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) &= ~0x4; + + // + // Disable RTC interrupt + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE); + ulRegValue &= ~0x1; + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue); + } +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! This function returns the PRCM interrupt status of interrupts that are +//! allowed to reflect to the processor. The interrupts are cleared on read. +//! +//! \return Returns the current interrupt status. +// +//***************************************************************************** +unsigned long PRCMIntStatus() +{ + return HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS); +} + +//***************************************************************************** +// +//! Mark the function of RTC as being used +//! +//! This function marks in HW that feature to maintain calendar time in device +//! is being used. +//! +//! Specifically, this feature reserves user's HIB Register-1 accessed through +//! PRCMOCRRegisterWrite(1) for internal work / purpose, therefore, the stated +//! register is not available to user. Also, users must not excercise the Slow +//! Clock Counter API(s), if RTC has been set for use. +//! +//! The RTC feature, if set or marked, can be only reset either through reboot +//! or power cycle. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCInUseSet() +{ + RTC_USE_SET(); + return; +} + +//***************************************************************************** +// +//! Ascertain whether function of RTC is being used +//! +//! This function indicates whether function of RTC is being used on the device +//! or not. +//! +//! This routine should be utilized by the application software, when returning +//! from low-power, to confirm that RTC has been put to use and may not need to +//! set the value of the RTC. +//! +//! The RTC feature, if set or marked, can be only reset either through reboot +//! or power cycle. +//! +//! \return None. +// +//***************************************************************************** +tBoolean PRCMRTCInUseGet() +{ + return IS_RTC_USED()? true : false; +} + +//***************************************************************************** +// +//! Set the calendar time in the device. +//! +//! \param ulSecs refers to the seconds part of the calendar time +//! \param usMsec refers to the fractional (ms) part of the second +//! +//! This function sets the specified calendar time in the device. The calendar +//! time is outlined in terms of seconds and milliseconds. However, the device +//! makes no assumption about the origin or reference of the calendar time. +//! +//! The device uses the indicated calendar value to update and maintain the +//! wall-clock time across active and low power states. +//! +//! The function PRCMRTCInUseSet() must be invoked prior to use of this feature. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec) +{ + unsigned long long ullMsec = 0; + + if(IS_RTC_USED()) { + ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec) - SCC_U64MSEC_GET(); + + RTC_U32SECS_REG_WR(RTC_SECS_IN_U64MSEC(ullMsec)); + RTC_U16MSEC_REG_WR(RTC_MSEC_IN_U64MSEC(ullMsec)); + } + + return; +} + +//***************************************************************************** +// +//! Get the instantaneous calendar time from the device. +//! +//! \param ulSecs refers to the seconds part of the calendar time +//! \param usMsec refers to the fractional (ms) part of the second +//! +//! This function fetches the instantaneous value of the ticking calendar time +//! from the device. The calendar time is outlined in terms of seconds and +//! milliseconds. +//! +//! The device provides the calendar value that has been maintained across +//! active and low power states. +//! +//! The function PRCMRTCSet() must have been invoked once to set a reference. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec) +{ + unsigned long long ullMsec = 0; + + if(IS_RTC_USED()) { + ullMsec = RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), + RTC_U16MSEC_REG_RD()); + ullMsec += SCC_U64MSEC_GET(); + } + + *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec); + *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec); + + return; +} + +//***************************************************************************** +// +//! Set a calendar time alarm. +//! +//! \param ulSecs refers to the seconds part of the calendar time +//! \param usMsec refers to the fractional (ms) part of the second +//! +//! This function sets an wall-clock alarm in the device to be reported for a +//! futuristic calendar time. The calendar time is outlined in terms of seconds +//! and milliseconds. +//! +//! The device provides uses the calendar value that has been maintained across +//! active and low power states to report attainment of alarm time. +//! +//! The function PRCMRTCSet() must have been invoked once to set a reference. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec) +{ + unsigned long long ullMsec = 0; + + if(IS_RTC_USED()) { + ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec); + ullMsec -= RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), + RTC_U16MSEC_REG_RD()); + SCC_U64MSEC_MATCH_SET(SELECT_SCC_U42BITS(ullMsec)); + } + + return; +} + +//***************************************************************************** +// +//! Get a previously set calendar time alarm. +//! +//! \param ulSecs refers to the seconds part of the calendar time +//! \param usMsec refers to the fractional (ms) part of the second +//! +//! This function fetches from the device a wall-clock alarm that would have +//! been previously set in the device. The calendar time is outlined in terms +//! of seconds and milliseconds. +//! +//! If no alarm was set in the past, then this function would fetch a random +//! information. +//! +//! The function PRCMRTCMatchSet() must have been invoked once to set an alarm. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec) +{ + unsigned long long ullMsec = 0; + + if(IS_RTC_USED()) { + ullMsec = SCC_U64MSEC_MATCH_GET(); + ullMsec += RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), + RTC_U16MSEC_REG_RD()); + } + + *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec); + *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec); + + return; +} + +//***************************************************************************** +// +//! MCU Initialization Routine +//! +//! This function contains all the mandatory bug fixes, ECO enables, +//! initializations for both CC3200 and CC3220. +//! +//! \note \b ###IMPORTANT### : This is a routine which should be one of the +//! first things to be executed after control comes to MCU Application code. +//! +//! \return None +// +//***************************************************************************** +void PRCMCC3200MCUInit() +{ + + if( PRCMSysResetCauseGet() != PRCM_LPDS_EXIT ) + { + if( 0x00010001 == HWREG(0x00000400) ) + { + +#ifndef REMOVE_CC3200_ES_1_2_1_CODE + + unsigned long ulRegVal; + + // + // DIG DCDC NFET SEL and COT mode disable + // + HWREG(0x4402F010) = 0x30031820; + HWREG(0x4402F00C) = 0x04000000; + + UtilsDelay(32000); + + // + // ANA DCDC clock config + // + HWREG(0x4402F11C) = 0x099; + HWREG(0x4402F11C) = 0x0AA; + HWREG(0x4402F11C) = 0x1AA; + + // + // PA DCDC clock config + // + HWREG(0x4402F124) = 0x099; + HWREG(0x4402F124) = 0x0AA; + HWREG(0x4402F124) = 0x1AA; + + // + // TD Flash timing configurations in case of MCU WDT reset + // + if((HWREG(0x4402D00C) & 0xFF) == 0x00000005) + { + HWREG(0x400F707C) |= 0x01840082; + HWREG(0x400F70C4)= 0x1; + HWREG(0x400F70C4)= 0x0; + } + + // + // Take I2C semaphore + // + ulRegVal = HWREG(0x400F7000); + ulRegVal = (ulRegVal & ~0x3) | 0x1; + HWREG(0x400F7000) = ulRegVal; + + // + // Take GPIO semaphore + // + ulRegVal = HWREG(0x400F703C); + ulRegVal = (ulRegVal & ~0x3FF) | 0x155; + HWREG(0x400F703C) = ulRegVal; + + // + // Enable 32KHz internal RC oscillator + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_INT_OSC_CONF, 0x00000101); + + // + // Delay for a little bit. + // + UtilsDelay(8000); + + // + // Enable 16MHz clock + // + HWREG(HIB1P2_BASE+HIB1P2_O_CM_OSC_16M_CONFIG) = 0x00010008; + + // + // Delay for a little bit. + // + UtilsDelay(8000); + +#endif // REMOVE_CC3200_ES_1_2_1_CODE + + } + else + { + + unsigned long ulRegValue; + + // + // DIG DCDC LPDS ECO Enable + // + HWREG(0x4402F064) |= 0x800000; + + // + // Enable hibernate ECO for PG 1.32 devices only. With this ECO enabled, + // any hibernate wakeup source will be kept maked until the device enters + // hibernate completely (analog + digital) + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0, ulRegValue | (1<<4)); + + // + // Handling the clock switching (for 1.32 only) + // + HWREG(0x4402E16C) |= 0x3C; + } + + + // + // Enable uDMA + // + PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK); + + // + // Reset uDMA + // + PRCMPeripheralReset(PRCM_UDMA); + + // + // Disable uDMA + // + PRCMPeripheralClkDisable(PRCM_UDMA,PRCM_RUN_MODE_CLK); + + // + // Enable RTC + // + if(PRCMSysResetCauseGet()== PRCM_POWER_ON) + { + PRCMHIBRegWrite(0x4402F804,0x1); + } + + // + // SWD mode + // + if(((HWREG(0x4402F0C8) & 0xFF) == 0x2)) + { + HWREG(0x4402E110) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2); + HWREG(0x4402E114) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2); + } + + // + // Override JTAG mux + // + HWREG(0x4402E184) |= 0x2; + + // + // Change UART pins(55,57) mode to PIN_MODE_0 if they are in PIN_MODE_1 + // + if( (HWREG(0x4402E0A4) & 0xF) == 0x1) + { + HWREG(0x4402E0A4) = ((HWREG(0x4402E0A4) & ~0xF)); + } + + if( (HWREG(0x4402E0A8) & 0xF) == 0x1) + { + HWREG(0x4402E0A8) = ((HWREG(0x4402E0A8) & ~0xF)); + } + + // + // DIG DCDC VOUT trim settings based on PROCESS INDICATOR + // + if(((HWREG(0x4402DC78) >> 22) & 0xF) == 0xE) + { + HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x32 << 18)); + } + else + { + HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x29 << 18)); + } + + // + // Enable SOFT RESTART in case of DIG DCDC collapse + // + HWREG(0x4402FC74) &= ~(0x10000000); + + // + // Required only if ROM version is lower than 2.x.x + // + if( (HWREG(0x00000400) & 0xFFFF) < 2 ) + { + // + // Disable the sleep for ANA DCDC + // + HWREG(0x4402F0A8) |= 0x00000004 ; + } + else if( (HWREG(0x00000400) >> 16) >= 1 ) + { + // + // Enable NWP force reset and HIB on WDT reset + // Enable direct boot path for flash + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= ((7<<5) | 0x1); + if((HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) & 0x1) ) + { + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) &= ~0x1; + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= (1<<9); + + // + // Clear the RTC hib wake up source + // + HWREG(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN) &= ~0x1; + + // + // Reset RTC match value + // + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF) = 0; + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF) = 0; + + } + } + + unsigned long efuse_reg2; + unsigned long ulDevMajorVer, ulDevMinorVer; + // + // Read the device identification register + // + efuse_reg2= HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); + + // + // Read the ROM mojor and minor version + // + ulDevMajorVer = ((efuse_reg2 >> 28) & 0xF); + ulDevMinorVer = ((efuse_reg2 >> 24) & 0xF); + + if(((ulDevMajorVer == 0x3) && (ulDevMinorVer == 0)) || (ulDevMajorVer < 0x3)) + { + unsigned int Scratch, PreRegulatedMode; + + // 0x4402F840 => 6th bit “1” indicates device is in pre-regulated mode. + PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; + + if( PreRegulatedMode) + { + Scratch = HWREG(0x4402F028); + Scratch &= 0xFFFFFF7F; // <7:7> = 0 + HWREG(0x4402F028) = Scratch; + + Scratch = HWREG(0x4402F010); + Scratch &= 0x0FFFFFFF; // <31:28> = 0 + Scratch |= 0x10000000; // <31:28> = 1 + HWREG(0x4402F010) = Scratch; + } + else + { + Scratch = HWREG(0x4402F024); + + Scratch &= 0xFFFFFFF0; // <3:0> = 0 + Scratch |= 0x00000001; // <3:0> = 1 + Scratch &= 0xFFFFF0FF; // <11:8> = 0000 + Scratch |= 0x00000500; // <11:8> = 0101 + Scratch &= 0xFFFE7FFF; // <16:15> = 0000 + Scratch |= 0x00010000; // <16:15> = 10 + + HWREG(0x4402F024) = Scratch; + + Scratch = HWREG(0x4402F028); + + Scratch &= 0xFFFFFF7F; // <7:7> = 0 + Scratch &= 0x0FFFFFFF; // <31:28> = 0 + Scratch &= 0xFF0FFFFF; // <23:20> = 0 + Scratch |= 0x00300000; // <23:20> = 0011 + Scratch &= 0xFFF0FFFF; // <19:16> = 0 + Scratch |= 0x00030000; // <19:16> = 0011 + + HWREG(0x4402F028) = Scratch; + HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 + } + } + else + { + unsigned int Scratch, PreRegulatedMode; + + // 0x4402F840 => 6th bit “1” indicates device is in pre-regulated mode. + PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; + + Scratch = HWREG(0x4402F028); + Scratch &= 0xFFFFFF7F; // <7:7> = 0 + HWREG(0x4402F028) = Scratch; + + HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 + if( PreRegulatedMode) + { + HWREG(0x4402F010) |= 0x10000000; // <31:28> = 1 + } + } + } + else + { + unsigned long ulRegVal; + + // + // I2C Configuration + // + ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register); + ulRegVal = (ulRegVal & ~0x3) | 0x1; + HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register) = ulRegVal; + + // + // GPIO configuration + // + ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register); + ulRegVal = (ulRegVal & ~0x3FF) | 0x155; + HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register) = ulRegVal; + + } +} + +//***************************************************************************** +// +//! Reads 32-bit value from register at specified address +//! +//! \param ulRegAddr is the address of register to be read. +//! +//! This function reads 32-bit value from the register as specified by +//! \e ulRegAddr. +//! +//! \return Return the value of the register. +// +//***************************************************************************** +unsigned long PRCMHIBRegRead(unsigned long ulRegAddr) +{ + unsigned long ulValue; + + // + // Read the Reg value + // + ulValue = HWREG(ulRegAddr); + + // + // Wait for 200 uSec + // + UtilsDelay((80*200)/3); + + // + // Return the value + // + return ulValue; +} + +//***************************************************************************** +// +//! Writes 32-bit value to register at specified address +//! +//! \param ulRegAddr is the address of register to be read. +//! \param ulValue is the 32-bit value to be written. +//! +//! This function writes 32-bit value passed as \e ulValue to the register as +//! specified by \e ulRegAddr +//! +//! \return None +// +//***************************************************************************** +void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue) +{ + // + // Read the Reg value + // + HWREG(ulRegAddr) = ulValue; + + // + // Wait for 200 uSec + // + UtilsDelay((80*200)/3); +} + +//***************************************************************************** +// +//! \param ulDivider is clock frequency divider value +//! \param ulWidth is the width of the high pulse +//! +//! This function sets the input frequency for camera module. +//! +//! The frequency is calculated as follows: +//! +//! f_out = 240MHz/ulDivider; +//! +//! The parameter \e ulWidth sets the width of the high pulse. +//! +//! For e.g.: +//! +//! ulDivider = 4; +//! ulWidth = 2; +//! +//! f_out = 30 MHz and 50% duty cycle +//! +//! And, +//! +//! ulDivider = 4; +//! ulWidth = 1; +//! +//! f_out = 30 MHz and 25% duty cycle +//! +//! \return 0 on success, 1 on error +// +//***************************************************************************** +unsigned long PRCMCameraFreqSet(unsigned char ulDivider, unsigned char ulWidth) +{ + if(ulDivider > ulWidth && ulWidth != 0 ) + { + // + // Set the hifh pulse width + // + HWREG(ARCM_BASE + + APPS_RCM_O_CAMERA_CLK_GEN) = (((ulWidth & 0x07) -1) << 8); + + // + // Set the low pulse width + // + HWREG(ARCM_BASE + + APPS_RCM_O_CAMERA_CLK_GEN) = ((ulDivider - ulWidth - 1) & 0x07); + // + // Return success + // + return 0; + } + + // + // Success; + // + return 1; +} + +//***************************************************************************** +// +//! Enable the IO value retention +//! +//! \param ulIORetGrpFlags is one of the valid IO groups. +//! +//! This function enables the IO retention for group of pins as specified by +//! \e ulIORetGrpFlags parameter. Enabling retention will immediately lock the +//! digital pins, in the specified group, to their current state (0 or 1). +//! Output pins can only be driven when retention is disabled. +//! +//! The parameter \e ulIORetGrpFlags can be logical OR of one or +//! more of the following: +//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface +//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 +//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 +//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 +//! +//! \note Use case is to park the pins when entering HIB. +//! +//! \return None. +// +//***************************************************************************** +void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags) +{ + + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Disable IO Pad to ODI Path + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00001F00; + + // + // 0b'0 in bit 5 for JTAG PADS + // 0b'0 in bit 0 for all other IOs + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00000023); + + // + // Enable retention for GRP0 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 ) + { + HWREG(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF) |= 0x5; + } + + // + // Enable retention for GRP1 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 ) + { + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0) |= ((0x3<<5)); + } + + // + // Enable retention for GRP2 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 ) + { + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF) |= 0x00000101; + } + + // + // Enable retention for GRP3 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 ) + { + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF) |= 0x00000204; + } + } +} + +//***************************************************************************** +// +//! Disable the IO value retention +//! +//! \param ulIORetGrpFlags is one of the valid IO groups. +//! +//! This function disable the IO retention for group of pins as specified by +//! \e ulIORetGrpFlags parameter. Disabling retention will unlock the +//! digital pins in the specified group. Output pins can only be driven when +//! retention is disabled. +//! +//! The parameter \e ulIORetGrpFlags can be logical OR of one or +//! more of the following: +//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface +//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 +//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 +//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 +//! +//! \note Use case is to un-park the pins when exiting HIB +//! +//! \return None. +// +//***************************************************************************** +void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags) +{ + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + + // + // Enable IO Pad to ODI Path + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00001F00); + + // + // 0b'1 in bit 5 for JTAG PADS + // 0b'1 in bit 0 for all other IOs + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00000023; + + // + // Disable retention for GRP0 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 ) + { + HWREG(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF) &= ~0x5; + } + + // + // Disable retention for GRP1 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 ) + { + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0) &= ~((0x3<<5)); + } + + // + // Disable retention for GRP2 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 ) + { + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF) &= ~0x00000101; + } + + // + // Disable retention for GRP3 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 ) + { + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF) &= ~0x00000204; + } + + } +} + +//***************************************************************************** +// +//! Gets the device type +//! +//! This function returns bit-packed value representing the device type +//! +//! The returned value is logical OR of one or more of the following:- +//! +//! -\b PRCM_DEV_TYPE_FLAG_R - R variant +//! -\b PRCM_DEV_TYPE_FLAG_F - F variant +//! -\b PRCM_DEV_TYPE_FLAG_Z - Z variant +//! -\b PRCM_DEV_TYPE_FLAG_SECURE - Device is secure +//! -\b PRCM_DEV_TYPE_FLAG_PRE_PROD - Device is a pre-production part +//! -\b PRCM_DEV_TYPE_FLAG_3200 - Device is CC3200 +//! -\b PRCM_DEV_TYPE_FLAG_3220 - Device is CC3220 +//! -\b PRCM_DEV_TYPE_FLAG_REV1 - Device Rev 1 +//! -\b PRCM_DEV_TYPE_FLAG_REV2 - Device Rev 2 +//! +//! Pre-defined helper macros:- +//! +//! -\b PRCM_DEV_TYPE_PRE_CC3200R - Pre-Production CC3200R +//! -\b PRCM_DEV_TYPE_PRE_CC3200F - Pre-Production CC3200F +//! -\b PRCM_DEV_TYPE_PRE_CC3200Z - Pre-Production CC3200Z +//! -\b PRCM_DEV_TYPE_CC3200R - Production CC3200R +//! -\b PRCM_DEV_TYPE_PRE_CC3220R - Pre-Production CC3220R +//! -\b PRCM_DEV_TYPE_PRE_CC3220F - Pre-Production CC3220F +//! -\b PRCM_DEV_TYPE_PRE_CC3220Z - Pre-Production CC3220Z +//! -\b PRCM_DEV_TYPE_CC3220R - Production CC3220R +//! -\b PRCM_DEV_TYPE_PRE_CC3220RS - Pre-Production CC3220RS +//! -\b PRCM_DEV_TYPE_PRE_CC3220FS - Pre-Production CC3220FS +//! -\b PRCM_DEV_TYPE_PRE_CC3220ZS - Pre-Production CC3220ZS +//! -\b PRCM_DEV_TYPE_CC3220RS - Production CC3220RS +//! -\b PRCM_DEV_TYPE_CC3220FS - Production CC3220FS +//! +//! \return Returns, bit-packed value representing the device type, +//! or 0 if device is unknown +// +//***************************************************************************** +unsigned long PRCMDeviceTypeGet() +{ + unsigned long ulDevType; + unsigned long ulChipId; + unsigned long ulDevMajorVer; + unsigned long ulDevMinorVer; + + // + // Read the device identification register + // + ulChipId = HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); + + // + // Read the ROM mojor and minor version + // + ulDevMajorVer = ((ulChipId >> 28) & 0xF); + ulDevMinorVer = ((ulChipId >> 24) & 0xF); + + + ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); + + // + // Get the device variant from the chip id + // + switch((ulChipId & 0xF)) + { + // + // It is R variant + // + case 0x0: + ulDevType = PRCM_DEV_TYPE_FLAG_R; + break; + + // + // It is F variant, non secure F variant is always Pre-Production + // + case 0x1: + ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_PRE_PROD; + break; + + // + // It is Z variant and is always Pre-Production + // + case 0x3: + ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_PRE_PROD; + break; + + // + // It is Secure R + // + case 0x8: + ulDevType = PRCM_DEV_TYPE_FLAG_R|PRCM_DEV_TYPE_FLAG_SECURE; + break; + + // + // It is Secure F + // + case 0x9: + ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_SECURE; + break; + + // + // It is secure Z variant and variant is always Pre-Production + // + case 0xB: + ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_SECURE| + PRCM_DEV_TYPE_FLAG_PRE_PROD; + break; + + // + // Undefined variant + // + default: + ulDevType = 0x0; + } + + if( ulDevType != 0 ) + { + if( ulDevMajorVer == 0x3 ) + { + ulDevType |= PRCM_DEV_TYPE_FLAG_3220; + } + else if( ulDevMajorVer == 0x2 ) + { + ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220); + + if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0) ) + { + if((ulDevMinorVer == 0x0)) + { + ulDevType |= PRCM_DEV_TYPE_FLAG_REV1; + } + else + { + ulDevType |= PRCM_DEV_TYPE_FLAG_REV2; + } + } + else + { + if((ulDevMinorVer == 0x1)) + { + ulDevType |= PRCM_DEV_TYPE_FLAG_REV1; + } + } + } + else + { + if( (ulDevMinorVer == 0x4)) + { + if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0)) + { + ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220); + } + else + { + ulDevType |= PRCM_DEV_TYPE_FLAG_3200; + } + } + else + { + ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3200); + } + } + } + + + return ulDevType; +} + + + +//**************************************************************************** +// +//! Used to trigger a hibernate cycle for the device using RTC +//! +//! This API can be used to do a clean reboot of device. +//! +//! \note This routine should only be exercised after all the network processing +//! has been stopped. To stop network processing use \b sl_stop API from +//! simplelink library. +//! +//! \return None +// +//**************************************************************************** +void PRCMHibernateCycleTrigger() +{ + unsigned long ulRegValue; + unsigned long long ullRTCVal; + + // + // Read the RTC register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); + + // + // Enable the RTC as wakeup source if specified + // + ulRegValue |= (PRCM_HIB_SLOW_CLK_CTR & 0x1); + + // + // Enable HIB wakeup sources + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); + + // + // Latch the RTC vlaue + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1); + + // + // Read latched values as 2 32-bit vlaues + // + ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW); + ullRTCVal = ullRTCVal << 32; + ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW); + + // + //Considering worst case execution times of ROM,RAM,Flash value of 160 is used + // + ullRTCVal = ullRTCVal + 160; + + // + // Set RTC match value + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF, + (unsigned long)(ullRTCVal)); + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF, + (unsigned long)(ullRTCVal>>32)); + // + // Note : Any addition of code after this line would need a change in + // ullTicks Interval currently set to 160 + // + + // + // Request hibernate. + // + PRCMHIBRegWrite((HIB3P3_BASE+HIB3P3_O_MEM_HIB_REQ),0x1); + + // + // Wait for system to enter hibernate + // + __asm(" wfi\n"); + + // + // Infinite loop + // + while(1) + { + + } +} + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/prcm.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/prcm.h new file mode 100644 index 000000000..e01b03614 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/prcm.h @@ -0,0 +1,372 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// prcm.h +// +// Prototypes for the PRCM control driver. +// +//***************************************************************************** + +#ifndef __PRCM_H__ +#define __PRCM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Peripheral clock and reset control registers +// +//***************************************************************************** +typedef struct _PRCM_PeripheralRegs_ +{ + +unsigned long ulClkReg; +unsigned long ulRstReg; + +}PRCM_PeriphRegs_t; + +//***************************************************************************** +// Values that can be passed to PRCMPeripheralEnable() and +// PRCMPeripheralDisable() +//***************************************************************************** +#define PRCM_RUN_MODE_CLK 0x00000001 +#define PRCM_SLP_MODE_CLK 0x00000100 + +//***************************************************************************** +// Values that can be passed to PRCMSRAMRetentionEnable() and +// PRCMSRAMRetentionDisable() as ulSramColSel. +//***************************************************************************** +#define PRCM_SRAM_COL_1 0x00000001 +#define PRCM_SRAM_COL_2 0x00000002 +#define PRCM_SRAM_COL_3 0x00000004 +#define PRCM_SRAM_COL_4 0x00000008 + +//***************************************************************************** +// Values that can be passed to PRCMSRAMRetentionEnable() and +// PRCMSRAMRetentionDisable() as ulModeFlags. +//***************************************************************************** +#define PRCM_SRAM_LPDS_RET 0x00000002 + +//***************************************************************************** +// Values that can be passed to PRCMLPDSWakeupSourceEnable(), +// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable(). +//***************************************************************************** +#define PRCM_LPDS_HOST_IRQ 0x00000080 +#define PRCM_LPDS_GPIO 0x00000010 +#define PRCM_LPDS_TIMER 0x00000001 + +//***************************************************************************** +// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type +//***************************************************************************** +#define PRCM_LPDS_LOW_LEVEL 0x00000002 +#define PRCM_LPDS_HIGH_LEVEL 0x00000000 +#define PRCM_LPDS_FALL_EDGE 0x00000001 +#define PRCM_LPDS_RISE_EDGE 0x00000003 + +//***************************************************************************** +// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() +//***************************************************************************** +#define PRCM_LPDS_GPIO2 0x00000000 +#define PRCM_LPDS_GPIO4 0x00000001 +#define PRCM_LPDS_GPIO13 0x00000002 +#define PRCM_LPDS_GPIO17 0x00000003 +#define PRCM_LPDS_GPIO11 0x00000004 +#define PRCM_LPDS_GPIO24 0x00000005 +#define PRCM_LPDS_GPIO26 0x00000006 + +//***************************************************************************** +// Values that can be passed to PRCMHibernateWakeupSourceEnable(), +// PRCMHibernateWakeupSourceDisable(). +//***************************************************************************** +#define PRCM_HIB_SLOW_CLK_CTR 0x00000001 + +//***************************************************************************** +// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType +//***************************************************************************** +#define PRCM_HIB_LOW_LEVEL 0x00000000 +#define PRCM_HIB_HIGH_LEVEL 0x00000001 +#define PRCM_HIB_FALL_EDGE 0x00000002 +#define PRCM_HIB_RISE_EDGE 0x00000003 + +//***************************************************************************** +// Values that can be passed to PRCMHibernateWakeupSourceEnable(), +// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect() +//***************************************************************************** +#define PRCM_HIB_GPIO2 0x00010000 +#define PRCM_HIB_GPIO4 0x00020000 +#define PRCM_HIB_GPIO13 0x00040000 +#define PRCM_HIB_GPIO17 0x00080000 +#define PRCM_HIB_GPIO11 0x00100000 +#define PRCM_HIB_GPIO24 0x00200000 +#define PRCM_HIB_GPIO26 0x00400000 + +//***************************************************************************** +// Values that will be returned from PRCMSysResetCauseGet(). +//***************************************************************************** +#define PRCM_POWER_ON 0x00000000 +#define PRCM_LPDS_EXIT 0x00000001 +#define PRCM_CORE_RESET 0x00000003 +#define PRCM_MCU_RESET 0x00000004 +#define PRCM_WDT_RESET 0x00000005 +#define PRCM_SOC_RESET 0x00000006 +#define PRCM_HIB_EXIT 0x00000007 + +//***************************************************************************** +// Values that can be passed to PRCMHibernateWakeupCauseGet(). +//***************************************************************************** +#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002 +#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004 + +//***************************************************************************** +// Values that can be passed to PRCMSEnableInterrupt +//***************************************************************************** +#define PRCM_INT_SLOW_CLK_CTR 0x00004000 + +//***************************************************************************** +// Values that can be passed to PRCMPeripheralClkEnable(), +// PRCMPeripheralClkDisable(), PRCMPeripheralReset() +//***************************************************************************** +#define PRCM_CAMERA 0x00000000 +#define PRCM_I2S 0x00000001 +#define PRCM_SDHOST 0x00000002 +#define PRCM_GSPI 0x00000003 +#define PRCM_LSPI 0x00000004 +#define PRCM_UDMA 0x00000005 +#define PRCM_GPIOA0 0x00000006 +#define PRCM_GPIOA1 0x00000007 +#define PRCM_GPIOA2 0x00000008 +#define PRCM_GPIOA3 0x00000009 +#define PRCM_GPIOA4 0x0000000A +#define PRCM_WDT 0x0000000B +#define PRCM_UARTA0 0x0000000C +#define PRCM_UARTA1 0x0000000D +#define PRCM_TIMERA0 0x0000000E +#define PRCM_TIMERA1 0x0000000F +#define PRCM_TIMERA2 0x00000010 +#define PRCM_TIMERA3 0x00000011 +#define PRCM_DTHE 0x00000012 +#define PRCM_SSPI 0x00000013 +#define PRCM_I2CA0 0x00000014 +// Note : PRCM_ADC is a dummy define for pinmux utility code generation +// PRCM_ADC should never be used in any user code. +#define PRCM_ADC 0x000000FF + + +//***************************************************************************** +// Values that can be passed to PRCMIORetEnable() and PRCMIORetDisable() +//***************************************************************************** +#define PRCM_IO_RET_GRP_0 0x00000001 +#define PRCM_IO_RET_GRP_1 0x00000002 +#define PRCM_IO_RET_GRP_2 0x00000004 +#define PRCM_IO_RET_GRP_3 0x00000008 + +//***************************************************************************** +// Macros definig the device type +//***************************************************************************** +#define PRCM_DEV_TYPE_FLAG_R 0x00000001 +#define PRCM_DEV_TYPE_FLAG_F 0x00000002 +#define PRCM_DEV_TYPE_FLAG_Z 0x00000004 +#define PRCM_DEV_TYPE_FLAG_SECURE 0x00000008 +#define PRCM_DEV_TYPE_FLAG_PRE_PROD 0x00000010 +#define PRCM_DEV_TYPE_FLAG_3200 0x00000020 +#define PRCM_DEV_TYPE_FLAG_3220 0x00000040 +#define PRCM_DEV_TYPE_FLAG_REV1 0x00010000 +#define PRCM_DEV_TYPE_FLAG_REV2 0x00020000 + +//***************************************************************************** +// Pre-defined helper macros +//***************************************************************************** +#define PRCM_DEV_TYPE_PRE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3200| \ + PRCM_DEV_TYPE_FLAG_R) + +#define PRCM_DEV_TYPE_PRE_CC3200F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3200| \ + PRCM_DEV_TYPE_FLAG_F) + +#define PRCM_DEV_TYPE_PRE_CC3200Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3200| \ + PRCM_DEV_TYPE_FLAG_Z) + +#define PRCM_DEV_TYPE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3200| \ + PRCM_DEV_TYPE_FLAG_R) + +#define PRCM_DEV_TYPE_PRE_CC3220R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_R) + +#define PRCM_DEV_TYPE_PRE_CC3220F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_F) + +#define PRCM_DEV_TYPE_PRE_CC3220Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_Z) + +#define PRCM_DEV_TYPE_CC3220R (PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_R) + + +#define PRCM_DEV_TYPE_PRE_CC3220RS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_R| \ + PRCM_DEV_TYPE_FLAG_SECURE) + +#define PRCM_DEV_TYPE_PRE_CC3220FS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_F| \ + PRCM_DEV_TYPE_FLAG_SECURE) + +#define PRCM_DEV_TYPE_PRE_CC3220ZS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_Z| \ + PRCM_DEV_TYPE_FLAG_SECURE) + +#define PRCM_DEV_TYPE_CC3220RS (PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_R| \ + PRCM_DEV_TYPE_FLAG_SECURE) + +#define PRCM_DEV_TYPE_CC3220FS (PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_F| \ + PRCM_DEV_TYPE_FLAG_SECURE) + + +#define PRCM_DEV_TYPE_PRE_CC3220Z1 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_Z| \ + PRCM_DEV_TYPE_FLAG_REV1) + +#define PRCM_DEV_TYPE_PRE_CC3220Z2 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_Z| \ + PRCM_DEV_TYPE_FLAG_REV2) + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PRCMMCUReset(tBoolean bIncludeSubsystem); +extern unsigned long PRCMSysResetCauseGet(void); + +extern void PRCMPeripheralClkEnable(unsigned long ulPeripheral, + unsigned long ulClkFlags); +extern void PRCMPeripheralClkDisable(unsigned long ulPeripheral, + unsigned long ulClkFlags); +extern void PRCMPeripheralReset(unsigned long ulPeripheral); +extern tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral); + +extern void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq); +extern unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral); + +extern void PRCMSleepEnter(void); + +extern void PRCMSRAMRetentionEnable(unsigned long ulSramColSel, + unsigned long ulFlags); +extern void PRCMSRAMRetentionDisable(unsigned long ulSramColSel, + unsigned long ulFlags); +extern void PRCMLPDSRestoreInfoSet(unsigned long ulRestoreSP, + unsigned long ulRestorePC); +extern void PRCMLPDSEnter(void); +extern void PRCMLPDSIntervalSet(unsigned long ulTicks); +extern void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc); +extern unsigned long PRCMLPDSWakeupCauseGet(void); +extern void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, + unsigned long ulType); +extern void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc); + +extern void PRCMHibernateEnter(void); +extern void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc); +extern unsigned long PRCMHibernateWakeupCauseGet(void); +extern void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap, + unsigned long ulType); +extern void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc); +extern void PRCMHibernateIntervalSet(unsigned long long ullTicks); + +extern unsigned long long PRCMSlowClkCtrGet(void); +extern unsigned long long PRCMSlowClkCtrFastGet(void); +extern void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks); +extern unsigned long long PRCMSlowClkCtrMatchGet(void); + +extern void PRCMOCRRegisterWrite(unsigned char ucIndex, + unsigned long ulRegValue); +extern unsigned long PRCMOCRRegisterRead(unsigned char ucIndex); + +extern void PRCMIntRegister(void (*pfnHandler)(void)); +extern void PRCMIntUnregister(void); +extern void PRCMIntEnable(unsigned long ulIntFlags); +extern void PRCMIntDisable(unsigned long ulIntFlags); +extern unsigned long PRCMIntStatus(void); +extern void PRCMRTCInUseSet(void); +extern tBoolean PRCMRTCInUseGet(void); +extern void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec); +extern void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec); +extern void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec); +extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec); +extern void PRCMCC3200MCUInit(void); +extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr); +extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue); +extern unsigned long PRCMCameraFreqSet(unsigned char ulDivider, + unsigned char ulWidth); +extern void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags); +extern void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags); +extern unsigned long PRCMDeviceTypeGet(void); +extern void PRCMLPDSEnterKeepDebugIf(void); +extern void PRCMHibernateCycleTrigger(void); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PRCM_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom.h new file mode 100644 index 000000000..a0b1b7192 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom.h @@ -0,0 +1,2797 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// +//***************************************************************************** +// +// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND. +// +//***************************************************************************** + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// For backward compatibility with older Driverlib versions +// +//***************************************************************************** +#ifdef TARGET_IS_CC3200 +#define USE_CC3200_ROM_DRV_API +#endif + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_APITABLE ((unsigned long *)0x0000040C) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1])) +#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[2])) +#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[3])) +#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[4])) +#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[5])) +#define ROM_PRCMTABLE ((unsigned long *)(ROM_APITABLE[6])) +#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[7])) +#define ROM_SPITABLE ((unsigned long *)(ROM_APITABLE[8])) +#define ROM_CAMERATABLE ((unsigned long *)(ROM_APITABLE[9])) +#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[10])) +#define ROM_PINTABLE ((unsigned long *)(ROM_APITABLE[11])) +#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[12])) +#define ROM_UTILSTABLE ((unsigned long *)(ROM_APITABLE[13])) +#define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[14])) +#define ROM_HWSPINLOCKTABLE ((unsigned long *)(ROM_APITABLE[15])) +#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[16])) +#define ROM_AESTABLE ((unsigned long *)(ROM_APITABLE[17])) +#define ROM_DESTABLE ((unsigned long *)(ROM_APITABLE[18])) +#define ROM_SHAMD5TABLE ((unsigned long *)(ROM_APITABLE[19])) +#define ROM_CRCTABLE ((unsigned long *)(ROM_APITABLE[20])) +#define ROM_SDHOSTTABLE ((unsigned long *)(ROM_APITABLE[21])) +#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[22])) +#define ROM_CPUTABLE ((unsigned long *)(ROM_APITABLE[23])) + +//***************************************************************************** +// +// Macros for calling ROM functions in the Interrupt API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntEnable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntMasterEnable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntMasterDisable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntDisable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityGroupingGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPrioritySet \ + ((void (*)(unsigned long ulInterrupt, \ + unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityGet \ + ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPendSet \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPendClear \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityMaskSet \ + ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityMaskGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntRegister \ + ((void (*)(unsigned long ulInterrupt, \ + void (*pfnHandler)(void)))ROM_INTERRUPTTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntUnregister \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntVTableBaseSet \ + ((void (*)(unsigned long ulVtableBase))ROM_INTERRUPTTABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Timer API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_TIMERTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerControlLevel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bInvert))ROM_TIMERTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerControlEvent \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulEvent))ROM_TIMERTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerControlStall \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bStall))ROM_TIMERTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerPrescaleSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerPrescaleGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerPrescaleMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerPrescaleMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerLoadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerLoadGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerValueGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntRegister \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + void (*pfnHandler)(void)))ROM_TIMERTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntUnregister \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_TIMERTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerValueSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[22]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerDMAEventSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAEvent))ROM_TIMERTABLE[23]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerDMAEventGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_TIMERTABLE[24]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UART API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTParityModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulParity))ROM_UARTTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTParityModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulRxLevel))ROM_UARTTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulTxLevel, \ + unsigned long *pulRxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long ulBaud, \ + unsigned long ulConfig))ROM_UARTTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long *pulBaud, \ + unsigned long *pulConfig))ROM_UARTTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTDisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFIFOEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFIFODisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharsAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTSpaceAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharGetNonBlocking \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharGet \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharPutNonBlocking \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTBreakCtl \ + ((void (*)(unsigned long ulBase, \ + tBoolean bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntRegister \ + ((void (*)(unsigned long ulBase, \ + void(*pfnHandler)(void)))ROM_UARTTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_UARTTABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[23]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[24]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[25]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTRxErrorGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[26]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTRxErrorClear \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[27]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTModemControlSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulControl))ROM_UARTTABLE[28]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTModemControlClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulControl))ROM_UARTTABLE[29]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTModemControlGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[30]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTModemStatusGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[31]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFlowControlSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_UARTTABLE[32]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFlowControlGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[33]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTTxIntModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_UARTTABLE[34]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTTxIntModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[35]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the uDMA API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelTransferSet \ + ((void (*)(unsigned long ulChannelStructIndex, \ + unsigned long ulMode, \ + void *pvSrcAddr, \ + void *pvDstAddr, \ + unsigned long ulTransferSize))ROM_UDMATABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAEnable \ + ((void (*)(void))ROM_UDMATABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMADisable \ + ((void (*)(void))ROM_UDMATABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAErrorStatusGet \ + ((unsigned long (*)(void))ROM_UDMATABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAErrorStatusClear \ + ((void (*)(void))ROM_UDMATABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelEnable \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelDisable \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelIsEnabled \ + ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAControlBaseSet \ + ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAControlBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelRequest \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned long ulAttr))ROM_UDMATABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned long ulAttr))ROM_UDMATABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelAttributeGet \ + ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelControlSet \ + ((void (*)(unsigned long ulChannelStructIndex, \ + unsigned long ulControl))ROM_UDMATABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelSizeGet \ + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelModeGet \ + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAIntStatus \ + ((unsigned long (*)(void))ROM_UDMATABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAIntClear \ + ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAControlAlternateBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned ulTaskCount, \ + void *pvTaskList, \ + unsigned long ulIsPeriphSG))ROM_UDMATABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelAssign \ + ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAIntRegister \ + ((void (*)(unsigned long ulIntChannel, \ + void (*pfnHandler)(void)))ROM_UDMATABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAIntUnregister \ + ((void (*)(unsigned long ulIntChannel))ROM_UDMATABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Watchdog API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogIntClear \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogRunning \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogLock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogUnlock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogLockState \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogReloadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLoadVal))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogReloadGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogValueGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogStallEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogStallDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogIntRegister \ + ((void (*)(unsigned long ulBase, \ + void(*pfnHandler)(void)))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2C API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CIntRegister \ + ((void (*)(uint32_t ui32Base, \ + void(pfnHandler)(void)))ROM_I2CTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CIntUnregister \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CTxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CTxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CRxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CRxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFOStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFODataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFODataPutNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFODataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFODataGetNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t *pui8Data))ROM_I2CTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterBurstLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Length))ROM_I2CTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterBurstCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterGlitchFilterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveFIFOEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterBusBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Cmd))ROM_I2CTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[24]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[25]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[26]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[27]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[28]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[29]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[30]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[31]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterTimeoutSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Value))ROM_I2CTABLE[32]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveACKOverride \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_I2CTABLE[33]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveACKValueSet \ + ((void (*)(uint32_t ui32Base, \ + bool bACK))ROM_I2CTABLE[34]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterLineStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[35]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr, \ + bool bReceive))ROM_I2CTABLE[36]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[37]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[38]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[39]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveInit \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[41]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8AddrNum, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[42]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[44]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[45]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[46]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[47]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[48]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[49]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[50]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[51]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32I2CClk, \ + bool bFast))ROM_I2CTABLE[52]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SPI API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIEnable \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDisable \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIReset \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSPIClk, \ + unsigned long ulBitRate, \ + unsigned long ulMode, \ + unsigned long ulSubMode, \ + unsigned long ulConfig))ROM_SPITABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long * pulData))ROM_SPITABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SPITABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SPITABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SPITABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIFIFOEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_SPITABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIFIFODisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_SPITABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIFIFOLevelSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulRxLevel))ROM_SPITABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIFIFOLevelGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulTxLevel, \ + unsigned long *pulRxLevel))ROM_SPITABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIWordCountSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulWordCount))ROM_SPITABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntRegister \ + ((void (*)(unsigned long ulBase, \ + void(*pfnHandler)(void)))ROM_SPITABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SPITABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SPITABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_SPITABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SPITABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDmaEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_SPITABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDmaDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_SPITABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPICSEnable \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPICSDisable \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPITransfer \ + ((long (*)(unsigned long ulBase, \ + unsigned char *ucDout, \ + unsigned char *ucDin, \ + unsigned long ulSize, \ + unsigned long ulFlags))ROM_SPITABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CAM API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraReset \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraParamsConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulHSPol, \ + unsigned long ulVSPol, \ + unsigned long ulFlags))ROM_CAMERATABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraXClkConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulCamClkIn, \ + unsigned long ulXClk))ROM_CAMERATABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraXClkSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char bXClkFlags))ROM_CAMERATABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraDMAEnable \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraDMADisable \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraThresholdSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulThreshold))ROM_CAMERATABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntRegister \ + ((void (*)(unsigned long ulBase, \ + void (*pfnHandler)(void)))ROM_CAMERATABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CAMERATABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CAMERATABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_CAMERATABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CAMERATABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraCaptureStop \ + ((void (*)(unsigned long ulBase, \ + tBoolean bImmediate))ROM_CAMERATABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraCaptureStart \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraBufferRead \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pBuffer, \ + unsigned char ucSize))ROM_CAMERATABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the FLASH API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashDisable \ + ((void (*)(void))ROM_FLASHTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashErase \ + ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashMassErase \ + ((long (*)(void))ROM_FLASHTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashMassEraseNonBlocking \ + ((void (*)(void))ROM_FLASHTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashEraseNonBlocking \ + ((void (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashProgram \ + ((long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_FLASHTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashProgramNonBlocking \ + ((long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_FLASHTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntRegister \ + ((void (*)(void (*pfnHandler)(void)))ROM_FLASHTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntUnregister \ + ((void (*)(void))ROM_FLASHTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Pin API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinModeSet \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinDirModeSet \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinIO))ROM_PINTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinDirModeGet \ + ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinModeGet \ + ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinConfigGet \ + ((void (*)(unsigned long ulPin, \ + unsigned long *pulPinStrength, \ + unsigned long *pulPinType))ROM_PINTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinConfigSet \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinStrength, \ + unsigned long ulPinType))ROM_PINTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeUART \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeI2C \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeSPI \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeI2S \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeTimer \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeCamera \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeGPIO \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode, \ + tBoolean bOpenDrain))ROM_PINTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeADC \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeSDHost \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[14]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinHysteresisSet \ + ((void (*)(unsigned long ulHysteresis))ROM_PINTABLE[15]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinLockLevelSet \ + ((void (*)(unsigned long ulPin, \ + unsigned char ucLevel))ROM_PINTABLE[16]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinLock \ + ((void (*)(unsigned long ulOutEnable))ROM_PINTABLE[17]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinUnlock \ + ((void (*)(void))ROM_PINTABLE[18]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SYSTICK API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickIntRegister \ + ((void (*)(void (*pfnHandler)(void)))ROM_SYSTICKTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickIntUnregister \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickPeriodSet \ + ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickPeriodGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickValueGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[8]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UTILS API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UtilsDelay \ + ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2S API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_I2STABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long ulData))ROM_I2STABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long ulData))ROM_I2STABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long *pulData))ROM_I2STABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long *pulData))ROM_I2STABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulI2SClk, \ + unsigned long ulBitClk, \ + unsigned long ulConfig))ROM_I2STABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2STxFIFOEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulWordsPerTransfer))ROM_I2STABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2STxFIFODisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SRxFIFOEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRxLevel, \ + unsigned long ulWordsPerTransfer))ROM_I2STABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SRxFIFODisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2STxFIFOStatusGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SRxFIFOStatusGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SSerializerConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long ulSerMode, \ + unsigned long ulInActState))ROM_I2STABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntRegister \ + ((void (*)(unsigned long ulBase, \ + void (*pfnHandler)(void)))ROM_I2STABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[19]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2STxActiveSlotSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulActSlot))ROM_I2STABLE[20]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SRxActiveSlotSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulActSlot))ROM_I2STABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the GPIO API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIODirModeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulPinIO))ROM_GPIOTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIODirModeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntTypeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulIntType))ROM_GPIOTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIODMATriggerEnable \ + ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIODMATriggerDisable \ + ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntTypeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned long ulIntFlags))ROM_GPIOTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned long ulIntFlags))ROM_GPIOTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntStatus \ + ((long (*)(unsigned long ulPort, \ + tBoolean bMasked))ROM_GPIOTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntClear \ + ((void (*)(unsigned long ulPort, \ + unsigned long ulIntFlags))ROM_GPIOTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntRegister \ + ((void (*)(unsigned long ulPort, \ + void (*pfnIntHandler)(void)))ROM_GPIOTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntUnregister \ + ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOPinRead \ + ((long (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOPinWrite \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned char ucVal))ROM_GPIOTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the AES API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_AESTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESKey1Set \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESKey2Set \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESKey3Set \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key))ROM_AESTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIVSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8IVdata))ROM_AESTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESTagRead \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8TagData))ROM_AESTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Length))ROM_AESTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESAuthDataLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_AESTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest, \ + uint8_t ui8Length))ROM_AESTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest, \ + uint8_t ui8Length))ROM_AESTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t ui8Length))ROM_AESTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t ui8Length))ROM_AESTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t *pui8Dest, \ + uint32_t ui32Length))ROM_AESTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataMAC \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint32_t ui32Length, \ + uint8_t *pui8Tag))ROM_AESTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataProcessAE \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t *pui8Dest, \ + uint32_t ui32Length, \ + uint8_t *pui8AuthSrc, \ + uint32_t ui32AuthLength, \ + uint8_t *pui8Tag))ROM_AESTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_AESTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntRegister \ + ((void (*)(uint32_t ui32Base, \ + void(*pfnHandler)(void)))ROM_AESTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntUnregister \ + ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[22]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIVGet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8IVdata))ROM_AESTABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the DES API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_DESTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest, \ + uint8_t ui8Length))ROM_DESTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest, \ + uint8_t ui8Length))ROM_DESTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t *pui8Dest, \ + uint32_t ui32Length))ROM_DESTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t ui8Length))ROM_DESTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t ui8Length))ROM_DESTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntRegister \ + ((void (*)(uint32_t ui32Base, \ + void(*pfnHandler)(void)))ROM_DESTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_DESTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntUnregister \ + ((void (*)(uint32_t ui32Base))ROM_DESTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIVSet \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8IVdata))ROM_DESTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key))ROM_DESTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_DESTABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SHAMD5 API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5ConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SHAMD5TABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8DataSrc, \ + uint32_t ui32DataLength, \ + uint8_t *pui8HashResult))ROM_SHAMD5TABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src))ROM_SHAMD5TABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src))ROM_SHAMD5TABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DMADisable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DMAEnable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DataLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_SHAMD5TABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5HMACKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src))ROM_SHAMD5TABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5HMACPPKeyGenerate \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key, \ + uint8_t *pui8PPKey))ROM_SHAMD5TABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5HMACPPKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src))ROM_SHAMD5TABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5HMACProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8DataSrc, \ + uint32_t ui32DataLength, \ + uint8_t *pui8HashResult))ROM_SHAMD5TABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntRegister \ + ((void (*)(uint32_t ui32Base, \ + void(*pfnHandler)(void)))ROM_SHAMD5TABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SHAMD5TABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntUnregister \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5ResultRead \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest))ROM_SHAMD5TABLE[17]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CRC API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCDataProcess \ + ((uint32_t (*)(uint32_t ui32Base, \ + void *puiDataIn, \ + uint32_t ui32DataLength, \ + uint32_t ui32Config))ROM_CRCTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_CRCTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCResultRead \ + ((uint32_t (*)(uint32_t ui32Base))ROM_CRCTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCSeedSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seed))ROM_CRCTABLE[4]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SDHOST API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostCmdReset \ + ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostInit \ + ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostCmdSend \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulCmd, \ + unsigned ulArg))ROM_SDHOSTTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntRegister \ + ((void (*)(unsigned long ulBase, \ + void (*pfnHandler)(void)))ROM_SDHOSTTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SDHOSTTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SDHOSTTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SDHOSTTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostRespGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRespnse[4]))ROM_SDHOSTTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostBlockSizeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned short ulBlkSize))ROM_SDHOSTTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostBlockCountSet \ + ((void (*)(unsigned long ulBase, \ + unsigned short ulBlkCount))ROM_SDHOSTTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostDataNonBlockingWrite \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SDHOSTTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostDataNonBlockingRead \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SDHOSTTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostDataWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SDHOSTTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostDataRead \ + ((void (*)(unsigned long ulBase, \ + unsigned long *ulData))ROM_SDHOSTTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSDHostClk, \ + unsigned long ulCardClk))ROM_SDHOSTTABLE[17]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostCardErrorMaskSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulErrMask))ROM_SDHOSTTABLE[18]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostCardErrorMaskGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[19]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PRCM API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMMCUReset \ + ((void (*)(tBoolean bIncludeSubsystem))ROM_PRCMTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSysResetCauseGet \ + ((unsigned long (*)(void))ROM_PRCMTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralClkEnable \ + ((void (*)(unsigned long ulPeripheral, \ + unsigned long ulClkFlags))ROM_PRCMTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralClkDisable \ + ((void (*)(unsigned long ulPeripheral, \ + unsigned long ulClkFlags))ROM_PRCMTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralReset \ + ((void (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralStatusGet \ + ((tBoolean (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMI2SClockFreqSet \ + ((void (*)(unsigned long ulI2CClkFreq))ROM_PRCMTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralClockGet \ + ((unsigned long (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSleepEnter \ + ((void (*)(void))ROM_PRCMTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSRAMRetentionEnable \ + ((void (*)(unsigned long ulSramColSel, \ + unsigned long ulFlags))ROM_PRCMTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSRAMRetentionDisable \ + ((void (*)(unsigned long ulSramColSel, \ + unsigned long ulFlags))ROM_PRCMTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSEnter \ + ((void (*)(void))ROM_PRCMTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSIntervalSet \ + ((void (*)(unsigned long ulTicks))ROM_PRCMTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSWakeupSourceEnable \ + ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSWakeupCauseGet \ + ((unsigned long (*)(void))ROM_PRCMTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSWakeUpGPIOSelect \ + ((void (*)(unsigned long ulGPIOPin, \ + unsigned long ulType))ROM_PRCMTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSWakeupSourceDisable \ + ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateEnter \ + ((void (*)(void))ROM_PRCMTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateWakeupSourceEnable \ + ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateWakeupCauseGet \ + ((unsigned long (*)(void))ROM_PRCMTABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateWakeUpGPIOSelect \ + ((void (*)(unsigned long ulMultiGPIOBitMap, \ + unsigned long ulType))ROM_PRCMTABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateWakeupSourceDisable \ + ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[23]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateIntervalSet \ + ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[24]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSlowClkCtrGet \ + ((unsigned long long (*)(void))ROM_PRCMTABLE[25]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSlowClkCtrMatchSet \ + ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[26]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSlowClkCtrMatchGet \ + ((unsigned long long (*)(void))ROM_PRCMTABLE[27]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMOCRRegisterWrite \ + ((void (*)(unsigned char ucIndex, \ + unsigned long ulRegValue))ROM_PRCMTABLE[28]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMOCRRegisterRead \ + ((unsigned long (*)(unsigned char ucIndex))ROM_PRCMTABLE[29]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntRegister \ + ((void (*)(void (*pfnHandler)(void)))ROM_PRCMTABLE[30]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntUnregister \ + ((void (*)(void))ROM_PRCMTABLE[31]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[32]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[33]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntStatus \ + ((unsigned long (*)(void))ROM_PRCMTABLE[34]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCInUseSet \ + ((void (*)(void))ROM_PRCMTABLE[35]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCInUseGet \ + ((tBoolean (*)(void))ROM_PRCMTABLE[36]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCSet \ + ((void (*)(unsigned long ulSecs, \ + unsigned short usMsec))ROM_PRCMTABLE[37]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCGet \ + ((void (*)(unsigned long *ulSecs, \ + unsigned short *usMsec))ROM_PRCMTABLE[38]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCMatchSet \ + ((void (*)(unsigned long ulSecs, \ + unsigned short usMsec))ROM_PRCMTABLE[39]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCMatchGet \ + ((void (*)(unsigned long *ulSecs, \ + unsigned short *usMsec))ROM_PRCMTABLE[40]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSRestoreInfoSet \ + ((void (*)(unsigned long ulRestoreSP, \ + unsigned long ulRestorePC))ROM_PRCMTABLE[41]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSlowClkCtrFastGet \ + ((unsigned long long (*)(void))ROM_PRCMTABLE[42]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMCC3200MCUInit \ + ((void (*)(void))ROM_PRCMTABLE[43]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHIBRegRead \ + ((unsigned long (*)(unsigned long ulRegAddr))ROM_PRCMTABLE[44]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHIBRegWrite \ + ((void (*)(unsigned long ulRegAddr, \ + unsigned long ulValue))ROM_PRCMTABLE[45]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMCameraFreqSet \ + ((unsigned long (*)(unsigned char ulDivider, \ + unsigned char ulWidth))ROM_PRCMTABLE[46]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIORetentionEnable \ + ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[47]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIORetentionDisable \ + ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[48]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMDeviceTypeGet \ + ((unsigned long (*)(void))ROM_PRCMTABLE[49]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSEnterKeepDebugIf \ + ((void (*)(void))ROM_PRCMTABLE[50]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateCycleTrigger \ + ((void (*)(void))ROM_PRCMTABLE[51]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the HWSPINLOCK API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_HwSpinLockAcquire \ + ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_HwSpinLockTryAcquire \ + ((int32_t (*)(uint32_t ui32LockID, \ + uint32_t ui32Retry))ROM_HWSPINLOCKTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_HwSpinLockRelease \ + ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_HwSpinLockTest \ + ((uint32_t (*)(uint32_t ui32LockID, \ + bool bCurrentStatus))ROM_HWSPINLOCKTABLE[3]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the ADC API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCEnable \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCDisable \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCChannelEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCChannelDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntRegister \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + void (*pfnHandler)(void)))ROM_ADCTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntUnregister \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulIntFlags))ROM_ADCTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulIntFlags))ROM_ADCTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulIntFlags))ROM_ADCTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulValue))ROM_ADCTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerEnable \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerDisable \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerReset \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerValueGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCFIFOLvlGet \ + ((unsigned char (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCFIFORead \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[20]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CPU API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUcpsid \ + ((unsigned long (*)(void))ROM_CPUTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUcpsie \ + ((unsigned long (*)(void))ROM_CPUTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUprimask \ + ((unsigned long (*)(void))ROM_CPUTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUwfi \ + ((void (*)(void))ROM_CPUTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUbasepriGet \ + ((unsigned long (*)(void))ROM_CPUTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUbasepriSet \ + ((void (*)(unsigned long ulNewBasepri))ROM_CPUTABLE[5]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions Directly. +// +//***************************************************************************** +#define ROM_UtilsDelayDirect \ + ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0]) + +#define ROM_PRCMLPDSEnterDirect \ + ((void (*)(void))ROM_PRCMTABLE[13]) + +#define ROM_PRCMLPDSEnterKeepDebugIfDirect \ + ((void (*)(void))ROM_PRCMTABLE[50]) + +#endif // __ROM_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom_map.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom_map.h new file mode 100644 index 000000000..54af2db10 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom_map.h @@ -0,0 +1,3325 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// rom_map.h - Macros to facilitate calling functions in the ROM when they are +// available. +// +//***************************************************************************** +//***************************************************************************** +// +// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND. +// +//***************************************************************************** + +#ifndef __ROM_MAP_H__ +#define __ROM_MAP_H__ + +//***************************************************************************** +// Patched ROM APIs +//***************************************************************************** +#include "rom_patch.h" + +//***************************************************************************** +// +// Macros for the Interrupt API. +// +//***************************************************************************** +#ifdef ROM_IntEnable +#define MAP_IntEnable \ + ROM_IntEnable +#else +#define MAP_IntEnable \ + IntEnable +#endif +#ifdef ROM_IntMasterEnable +#define MAP_IntMasterEnable \ + ROM_IntMasterEnable +#else +#define MAP_IntMasterEnable \ + IntMasterEnable +#endif +#ifdef ROM_IntMasterDisable +#define MAP_IntMasterDisable \ + ROM_IntMasterDisable +#else +#define MAP_IntMasterDisable \ + IntMasterDisable +#endif +#ifdef ROM_IntDisable +#define MAP_IntDisable \ + ROM_IntDisable +#else +#define MAP_IntDisable \ + IntDisable +#endif +#ifdef ROM_IntPriorityGroupingSet +#define MAP_IntPriorityGroupingSet \ + ROM_IntPriorityGroupingSet +#else +#define MAP_IntPriorityGroupingSet \ + IntPriorityGroupingSet +#endif +#ifdef ROM_IntPriorityGroupingGet +#define MAP_IntPriorityGroupingGet \ + ROM_IntPriorityGroupingGet +#else +#define MAP_IntPriorityGroupingGet \ + IntPriorityGroupingGet +#endif +#ifdef ROM_IntPrioritySet +#define MAP_IntPrioritySet \ + ROM_IntPrioritySet +#else +#define MAP_IntPrioritySet \ + IntPrioritySet +#endif +#ifdef ROM_IntPriorityGet +#define MAP_IntPriorityGet \ + ROM_IntPriorityGet +#else +#define MAP_IntPriorityGet \ + IntPriorityGet +#endif +#ifdef ROM_IntPendSet +#define MAP_IntPendSet \ + ROM_IntPendSet +#else +#define MAP_IntPendSet \ + IntPendSet +#endif +#ifdef ROM_IntPendClear +#define MAP_IntPendClear \ + ROM_IntPendClear +#else +#define MAP_IntPendClear \ + IntPendClear +#endif +#ifdef ROM_IntPriorityMaskSet +#define MAP_IntPriorityMaskSet \ + ROM_IntPriorityMaskSet +#else +#define MAP_IntPriorityMaskSet \ + IntPriorityMaskSet +#endif +#ifdef ROM_IntPriorityMaskGet +#define MAP_IntPriorityMaskGet \ + ROM_IntPriorityMaskGet +#else +#define MAP_IntPriorityMaskGet \ + IntPriorityMaskGet +#endif +#ifdef ROM_IntRegister +#define MAP_IntRegister \ + ROM_IntRegister +#else +#define MAP_IntRegister \ + IntRegister +#endif +#ifdef ROM_IntUnregister +#define MAP_IntUnregister \ + ROM_IntUnregister +#else +#define MAP_IntUnregister \ + IntUnregister +#endif +#ifdef ROM_IntVTableBaseSet +#define MAP_IntVTableBaseSet \ + ROM_IntVTableBaseSet +#else +#define MAP_IntVTableBaseSet \ + IntVTableBaseSet +#endif + +//***************************************************************************** +// +// Macros for the Timer API. +// +//***************************************************************************** +#ifdef ROM_TimerEnable +#define MAP_TimerEnable \ + ROM_TimerEnable +#else +#define MAP_TimerEnable \ + TimerEnable +#endif +#ifdef ROM_TimerDisable +#define MAP_TimerDisable \ + ROM_TimerDisable +#else +#define MAP_TimerDisable \ + TimerDisable +#endif +#ifdef ROM_TimerConfigure +#define MAP_TimerConfigure \ + ROM_TimerConfigure +#else +#define MAP_TimerConfigure \ + TimerConfigure +#endif +#ifdef ROM_TimerControlLevel +#define MAP_TimerControlLevel \ + ROM_TimerControlLevel +#else +#define MAP_TimerControlLevel \ + TimerControlLevel +#endif +#ifdef ROM_TimerControlEvent +#define MAP_TimerControlEvent \ + ROM_TimerControlEvent +#else +#define MAP_TimerControlEvent \ + TimerControlEvent +#endif +#ifdef ROM_TimerControlStall +#define MAP_TimerControlStall \ + ROM_TimerControlStall +#else +#define MAP_TimerControlStall \ + TimerControlStall +#endif +#ifdef ROM_TimerPrescaleSet +#define MAP_TimerPrescaleSet \ + ROM_TimerPrescaleSet +#else +#define MAP_TimerPrescaleSet \ + TimerPrescaleSet +#endif +#ifdef ROM_TimerPrescaleGet +#define MAP_TimerPrescaleGet \ + ROM_TimerPrescaleGet +#else +#define MAP_TimerPrescaleGet \ + TimerPrescaleGet +#endif +#ifdef ROM_TimerPrescaleMatchSet +#define MAP_TimerPrescaleMatchSet \ + ROM_TimerPrescaleMatchSet +#else +#define MAP_TimerPrescaleMatchSet \ + TimerPrescaleMatchSet +#endif +#ifdef ROM_TimerPrescaleMatchGet +#define MAP_TimerPrescaleMatchGet \ + ROM_TimerPrescaleMatchGet +#else +#define MAP_TimerPrescaleMatchGet \ + TimerPrescaleMatchGet +#endif +#ifdef ROM_TimerLoadSet +#define MAP_TimerLoadSet \ + ROM_TimerLoadSet +#else +#define MAP_TimerLoadSet \ + TimerLoadSet +#endif +#ifdef ROM_TimerLoadGet +#define MAP_TimerLoadGet \ + ROM_TimerLoadGet +#else +#define MAP_TimerLoadGet \ + TimerLoadGet +#endif +#ifdef ROM_TimerValueGet +#define MAP_TimerValueGet \ + ROM_TimerValueGet +#else +#define MAP_TimerValueGet \ + TimerValueGet +#endif +#ifdef ROM_TimerMatchSet +#define MAP_TimerMatchSet \ + ROM_TimerMatchSet +#else +#define MAP_TimerMatchSet \ + TimerMatchSet +#endif +#ifdef ROM_TimerMatchGet +#define MAP_TimerMatchGet \ + ROM_TimerMatchGet +#else +#define MAP_TimerMatchGet \ + TimerMatchGet +#endif +#ifdef ROM_TimerIntRegister +#define MAP_TimerIntRegister \ + ROM_TimerIntRegister +#else +#define MAP_TimerIntRegister \ + TimerIntRegister +#endif +#ifdef ROM_TimerIntUnregister +#define MAP_TimerIntUnregister \ + ROM_TimerIntUnregister +#else +#define MAP_TimerIntUnregister \ + TimerIntUnregister +#endif +#ifdef ROM_TimerIntEnable +#define MAP_TimerIntEnable \ + ROM_TimerIntEnable +#else +#define MAP_TimerIntEnable \ + TimerIntEnable +#endif +#ifdef ROM_TimerIntDisable +#define MAP_TimerIntDisable \ + ROM_TimerIntDisable +#else +#define MAP_TimerIntDisable \ + TimerIntDisable +#endif +#ifdef ROM_TimerIntStatus +#define MAP_TimerIntStatus \ + ROM_TimerIntStatus +#else +#define MAP_TimerIntStatus \ + TimerIntStatus +#endif +#ifdef ROM_TimerIntClear +#define MAP_TimerIntClear \ + ROM_TimerIntClear +#else +#define MAP_TimerIntClear \ + TimerIntClear +#endif +#ifdef ROM_TimerValueSet +#define MAP_TimerValueSet \ + ROM_TimerValueSet +#else +#define MAP_TimerValueSet \ + TimerValueSet +#endif +#ifdef ROM_TimerDMAEventSet +#define MAP_TimerDMAEventSet \ + ROM_TimerDMAEventSet +#else +#define MAP_TimerDMAEventSet \ + TimerDMAEventSet +#endif +#ifdef ROM_TimerDMAEventGet +#define MAP_TimerDMAEventGet \ + ROM_TimerDMAEventGet +#else +#define MAP_TimerDMAEventGet \ + TimerDMAEventGet +#endif + +//***************************************************************************** +// +// Macros for the UART API. +// +//***************************************************************************** +#ifdef ROM_UARTParityModeSet +#define MAP_UARTParityModeSet \ + ROM_UARTParityModeSet +#else +#define MAP_UARTParityModeSet \ + UARTParityModeSet +#endif +#ifdef ROM_UARTParityModeGet +#define MAP_UARTParityModeGet \ + ROM_UARTParityModeGet +#else +#define MAP_UARTParityModeGet \ + UARTParityModeGet +#endif +#ifdef ROM_UARTFIFOLevelSet +#define MAP_UARTFIFOLevelSet \ + ROM_UARTFIFOLevelSet +#else +#define MAP_UARTFIFOLevelSet \ + UARTFIFOLevelSet +#endif +#ifdef ROM_UARTFIFOLevelGet +#define MAP_UARTFIFOLevelGet \ + ROM_UARTFIFOLevelGet +#else +#define MAP_UARTFIFOLevelGet \ + UARTFIFOLevelGet +#endif +#ifdef ROM_UARTConfigSetExpClk +#define MAP_UARTConfigSetExpClk \ + ROM_UARTConfigSetExpClk +#else +#define MAP_UARTConfigSetExpClk \ + UARTConfigSetExpClk +#endif +#ifdef ROM_UARTConfigGetExpClk +#define MAP_UARTConfigGetExpClk \ + ROM_UARTConfigGetExpClk +#else +#define MAP_UARTConfigGetExpClk \ + UARTConfigGetExpClk +#endif +#ifdef ROM_UARTEnable +#define MAP_UARTEnable \ + ROM_UARTEnable +#else +#define MAP_UARTEnable \ + UARTEnable +#endif +#ifdef ROM_UARTDisable +#define MAP_UARTDisable \ + ROM_UARTDisable +#else +#define MAP_UARTDisable \ + UARTDisable +#endif +#ifdef ROM_UARTFIFOEnable +#define MAP_UARTFIFOEnable \ + ROM_UARTFIFOEnable +#else +#define MAP_UARTFIFOEnable \ + UARTFIFOEnable +#endif +#ifdef ROM_UARTFIFODisable +#define MAP_UARTFIFODisable \ + ROM_UARTFIFODisable +#else +#define MAP_UARTFIFODisable \ + UARTFIFODisable +#endif +#ifdef ROM_UARTCharsAvail +#define MAP_UARTCharsAvail \ + ROM_UARTCharsAvail +#else +#define MAP_UARTCharsAvail \ + UARTCharsAvail +#endif +#ifdef ROM_UARTSpaceAvail +#define MAP_UARTSpaceAvail \ + ROM_UARTSpaceAvail +#else +#define MAP_UARTSpaceAvail \ + UARTSpaceAvail +#endif +#ifdef ROM_UARTCharGetNonBlocking +#define MAP_UARTCharGetNonBlocking \ + ROM_UARTCharGetNonBlocking +#else +#define MAP_UARTCharGetNonBlocking \ + UARTCharGetNonBlocking +#endif +#ifdef ROM_UARTCharGet +#define MAP_UARTCharGet \ + ROM_UARTCharGet +#else +#define MAP_UARTCharGet \ + UARTCharGet +#endif +#ifdef ROM_UARTCharPutNonBlocking +#define MAP_UARTCharPutNonBlocking \ + ROM_UARTCharPutNonBlocking +#else +#define MAP_UARTCharPutNonBlocking \ + UARTCharPutNonBlocking +#endif +#ifdef ROM_UARTCharPut +#define MAP_UARTCharPut \ + ROM_UARTCharPut +#else +#define MAP_UARTCharPut \ + UARTCharPut +#endif +#ifdef ROM_UARTBreakCtl +#define MAP_UARTBreakCtl \ + ROM_UARTBreakCtl +#else +#define MAP_UARTBreakCtl \ + UARTBreakCtl +#endif +#ifdef ROM_UARTBusy +#define MAP_UARTBusy \ + ROM_UARTBusy +#else +#define MAP_UARTBusy \ + UARTBusy +#endif +#ifdef ROM_UARTIntRegister +#define MAP_UARTIntRegister \ + ROM_UARTIntRegister +#else +#define MAP_UARTIntRegister \ + UARTIntRegister +#endif +#ifdef ROM_UARTIntUnregister +#define MAP_UARTIntUnregister \ + ROM_UARTIntUnregister +#else +#define MAP_UARTIntUnregister \ + UARTIntUnregister +#endif +#ifdef ROM_UARTIntEnable +#define MAP_UARTIntEnable \ + ROM_UARTIntEnable +#else +#define MAP_UARTIntEnable \ + UARTIntEnable +#endif +#ifdef ROM_UARTIntDisable +#define MAP_UARTIntDisable \ + ROM_UARTIntDisable +#else +#define MAP_UARTIntDisable \ + UARTIntDisable +#endif +#ifdef ROM_UARTIntStatus +#define MAP_UARTIntStatus \ + ROM_UARTIntStatus +#else +#define MAP_UARTIntStatus \ + UARTIntStatus +#endif +#ifdef ROM_UARTIntClear +#define MAP_UARTIntClear \ + ROM_UARTIntClear +#else +#define MAP_UARTIntClear \ + UARTIntClear +#endif +#ifdef ROM_UARTDMAEnable +#define MAP_UARTDMAEnable \ + ROM_UARTDMAEnable +#else +#define MAP_UARTDMAEnable \ + UARTDMAEnable +#endif +#ifdef ROM_UARTDMADisable +#define MAP_UARTDMADisable \ + ROM_UARTDMADisable +#else +#define MAP_UARTDMADisable \ + UARTDMADisable +#endif +#ifdef ROM_UARTRxErrorGet +#define MAP_UARTRxErrorGet \ + ROM_UARTRxErrorGet +#else +#define MAP_UARTRxErrorGet \ + UARTRxErrorGet +#endif +#ifdef ROM_UARTRxErrorClear +#define MAP_UARTRxErrorClear \ + ROM_UARTRxErrorClear +#else +#define MAP_UARTRxErrorClear \ + UARTRxErrorClear +#endif +#ifdef ROM_UARTModemControlSet +#define MAP_UARTModemControlSet \ + ROM_UARTModemControlSet +#else +#define MAP_UARTModemControlSet \ + UARTModemControlSet +#endif +#ifdef ROM_UARTModemControlClear +#define MAP_UARTModemControlClear \ + ROM_UARTModemControlClear +#else +#define MAP_UARTModemControlClear \ + UARTModemControlClear +#endif +#ifdef ROM_UARTModemControlGet +#define MAP_UARTModemControlGet \ + ROM_UARTModemControlGet +#else +#define MAP_UARTModemControlGet \ + UARTModemControlGet +#endif +#ifdef ROM_UARTModemStatusGet +#define MAP_UARTModemStatusGet \ + ROM_UARTModemStatusGet +#else +#define MAP_UARTModemStatusGet \ + UARTModemStatusGet +#endif +#ifdef ROM_UARTFlowControlSet +#define MAP_UARTFlowControlSet \ + ROM_UARTFlowControlSet +#else +#define MAP_UARTFlowControlSet \ + UARTFlowControlSet +#endif +#ifdef ROM_UARTFlowControlGet +#define MAP_UARTFlowControlGet \ + ROM_UARTFlowControlGet +#else +#define MAP_UARTFlowControlGet \ + UARTFlowControlGet +#endif +#ifdef ROM_UARTTxIntModeSet +#define MAP_UARTTxIntModeSet \ + ROM_UARTTxIntModeSet +#else +#define MAP_UARTTxIntModeSet \ + UARTTxIntModeSet +#endif +#ifdef ROM_UARTTxIntModeGet +#define MAP_UARTTxIntModeGet \ + ROM_UARTTxIntModeGet +#else +#define MAP_UARTTxIntModeGet \ + UARTTxIntModeGet +#endif + +//***************************************************************************** +// +// Macros for the uDMA API. +// +//***************************************************************************** +#ifdef ROM_uDMAChannelTransferSet +#define MAP_uDMAChannelTransferSet \ + ROM_uDMAChannelTransferSet +#else +#define MAP_uDMAChannelTransferSet \ + uDMAChannelTransferSet +#endif +#ifdef ROM_uDMAEnable +#define MAP_uDMAEnable \ + ROM_uDMAEnable +#else +#define MAP_uDMAEnable \ + uDMAEnable +#endif +#ifdef ROM_uDMADisable +#define MAP_uDMADisable \ + ROM_uDMADisable +#else +#define MAP_uDMADisable \ + uDMADisable +#endif +#ifdef ROM_uDMAErrorStatusGet +#define MAP_uDMAErrorStatusGet \ + ROM_uDMAErrorStatusGet +#else +#define MAP_uDMAErrorStatusGet \ + uDMAErrorStatusGet +#endif +#ifdef ROM_uDMAErrorStatusClear +#define MAP_uDMAErrorStatusClear \ + ROM_uDMAErrorStatusClear +#else +#define MAP_uDMAErrorStatusClear \ + uDMAErrorStatusClear +#endif +#ifdef ROM_uDMAChannelEnable +#define MAP_uDMAChannelEnable \ + ROM_uDMAChannelEnable +#else +#define MAP_uDMAChannelEnable \ + uDMAChannelEnable +#endif +#ifdef ROM_uDMAChannelDisable +#define MAP_uDMAChannelDisable \ + ROM_uDMAChannelDisable +#else +#define MAP_uDMAChannelDisable \ + uDMAChannelDisable +#endif +#ifdef ROM_uDMAChannelIsEnabled +#define MAP_uDMAChannelIsEnabled \ + ROM_uDMAChannelIsEnabled +#else +#define MAP_uDMAChannelIsEnabled \ + uDMAChannelIsEnabled +#endif +#ifdef ROM_uDMAControlBaseSet +#define MAP_uDMAControlBaseSet \ + ROM_uDMAControlBaseSet +#else +#define MAP_uDMAControlBaseSet \ + uDMAControlBaseSet +#endif +#ifdef ROM_uDMAControlBaseGet +#define MAP_uDMAControlBaseGet \ + ROM_uDMAControlBaseGet +#else +#define MAP_uDMAControlBaseGet \ + uDMAControlBaseGet +#endif +#ifdef ROM_uDMAChannelRequest +#define MAP_uDMAChannelRequest \ + ROM_uDMAChannelRequest +#else +#define MAP_uDMAChannelRequest \ + uDMAChannelRequest +#endif +#ifdef ROM_uDMAChannelAttributeEnable +#define MAP_uDMAChannelAttributeEnable \ + ROM_uDMAChannelAttributeEnable +#else +#define MAP_uDMAChannelAttributeEnable \ + uDMAChannelAttributeEnable +#endif +#ifdef ROM_uDMAChannelAttributeDisable +#define MAP_uDMAChannelAttributeDisable \ + ROM_uDMAChannelAttributeDisable +#else +#define MAP_uDMAChannelAttributeDisable \ + uDMAChannelAttributeDisable +#endif +#ifdef ROM_uDMAChannelAttributeGet +#define MAP_uDMAChannelAttributeGet \ + ROM_uDMAChannelAttributeGet +#else +#define MAP_uDMAChannelAttributeGet \ + uDMAChannelAttributeGet +#endif +#ifdef ROM_uDMAChannelControlSet +#define MAP_uDMAChannelControlSet \ + ROM_uDMAChannelControlSet +#else +#define MAP_uDMAChannelControlSet \ + uDMAChannelControlSet +#endif +#ifdef ROM_uDMAChannelSizeGet +#define MAP_uDMAChannelSizeGet \ + ROM_uDMAChannelSizeGet +#else +#define MAP_uDMAChannelSizeGet \ + uDMAChannelSizeGet +#endif +#ifdef ROM_uDMAChannelModeGet +#define MAP_uDMAChannelModeGet \ + ROM_uDMAChannelModeGet +#else +#define MAP_uDMAChannelModeGet \ + uDMAChannelModeGet +#endif +#ifdef ROM_uDMAIntStatus +#define MAP_uDMAIntStatus \ + ROM_uDMAIntStatus +#else +#define MAP_uDMAIntStatus \ + uDMAIntStatus +#endif +#ifdef ROM_uDMAIntClear +#define MAP_uDMAIntClear \ + ROM_uDMAIntClear +#else +#define MAP_uDMAIntClear \ + uDMAIntClear +#endif +#ifdef ROM_uDMAControlAlternateBaseGet +#define MAP_uDMAControlAlternateBaseGet \ + ROM_uDMAControlAlternateBaseGet +#else +#define MAP_uDMAControlAlternateBaseGet \ + uDMAControlAlternateBaseGet +#endif +#ifdef ROM_uDMAChannelScatterGatherSet +#define MAP_uDMAChannelScatterGatherSet \ + ROM_uDMAChannelScatterGatherSet +#else +#define MAP_uDMAChannelScatterGatherSet \ + uDMAChannelScatterGatherSet +#endif +#ifdef ROM_uDMAChannelAssign +#define MAP_uDMAChannelAssign \ + ROM_uDMAChannelAssign +#else +#define MAP_uDMAChannelAssign \ + uDMAChannelAssign +#endif +#ifdef ROM_uDMAIntRegister +#define MAP_uDMAIntRegister \ + ROM_uDMAIntRegister +#else +#define MAP_uDMAIntRegister \ + uDMAIntRegister +#endif +#ifdef ROM_uDMAIntUnregister +#define MAP_uDMAIntUnregister \ + ROM_uDMAIntUnregister +#else +#define MAP_uDMAIntUnregister \ + uDMAIntUnregister +#endif + +//***************************************************************************** +// +// Macros for the Watchdog API. +// +//***************************************************************************** +#ifdef ROM_WatchdogIntClear +#define MAP_WatchdogIntClear \ + ROM_WatchdogIntClear +#else +#define MAP_WatchdogIntClear \ + WatchdogIntClear +#endif +#ifdef ROM_WatchdogRunning +#define MAP_WatchdogRunning \ + ROM_WatchdogRunning +#else +#define MAP_WatchdogRunning \ + WatchdogRunning +#endif +#ifdef ROM_WatchdogEnable +#define MAP_WatchdogEnable \ + ROM_WatchdogEnable +#else +#define MAP_WatchdogEnable \ + WatchdogEnable +#endif +#ifdef ROM_WatchdogLock +#define MAP_WatchdogLock \ + ROM_WatchdogLock +#else +#define MAP_WatchdogLock \ + WatchdogLock +#endif +#ifdef ROM_WatchdogUnlock +#define MAP_WatchdogUnlock \ + ROM_WatchdogUnlock +#else +#define MAP_WatchdogUnlock \ + WatchdogUnlock +#endif +#ifdef ROM_WatchdogLockState +#define MAP_WatchdogLockState \ + ROM_WatchdogLockState +#else +#define MAP_WatchdogLockState \ + WatchdogLockState +#endif +#ifdef ROM_WatchdogReloadSet +#define MAP_WatchdogReloadSet \ + ROM_WatchdogReloadSet +#else +#define MAP_WatchdogReloadSet \ + WatchdogReloadSet +#endif +#ifdef ROM_WatchdogReloadGet +#define MAP_WatchdogReloadGet \ + ROM_WatchdogReloadGet +#else +#define MAP_WatchdogReloadGet \ + WatchdogReloadGet +#endif +#ifdef ROM_WatchdogValueGet +#define MAP_WatchdogValueGet \ + ROM_WatchdogValueGet +#else +#define MAP_WatchdogValueGet \ + WatchdogValueGet +#endif +#ifdef ROM_WatchdogIntStatus +#define MAP_WatchdogIntStatus \ + ROM_WatchdogIntStatus +#else +#define MAP_WatchdogIntStatus \ + WatchdogIntStatus +#endif +#ifdef ROM_WatchdogStallEnable +#define MAP_WatchdogStallEnable \ + ROM_WatchdogStallEnable +#else +#define MAP_WatchdogStallEnable \ + WatchdogStallEnable +#endif +#ifdef ROM_WatchdogStallDisable +#define MAP_WatchdogStallDisable \ + ROM_WatchdogStallDisable +#else +#define MAP_WatchdogStallDisable \ + WatchdogStallDisable +#endif +#ifdef ROM_WatchdogIntRegister +#define MAP_WatchdogIntRegister \ + ROM_WatchdogIntRegister +#else +#define MAP_WatchdogIntRegister \ + WatchdogIntRegister +#endif +#ifdef ROM_WatchdogIntUnregister +#define MAP_WatchdogIntUnregister \ + ROM_WatchdogIntUnregister +#else +#define MAP_WatchdogIntUnregister \ + WatchdogIntUnregister +#endif + +//***************************************************************************** +// +// Macros for the I2C API. +// +//***************************************************************************** +#ifdef ROM_I2CIntRegister +#define MAP_I2CIntRegister \ + ROM_I2CIntRegister +#else +#define MAP_I2CIntRegister \ + I2CIntRegister +#endif +#ifdef ROM_I2CIntUnregister +#define MAP_I2CIntUnregister \ + ROM_I2CIntUnregister +#else +#define MAP_I2CIntUnregister \ + I2CIntUnregister +#endif +#ifdef ROM_I2CTxFIFOConfigSet +#define MAP_I2CTxFIFOConfigSet \ + ROM_I2CTxFIFOConfigSet +#else +#define MAP_I2CTxFIFOConfigSet \ + I2CTxFIFOConfigSet +#endif +#ifdef ROM_I2CTxFIFOFlush +#define MAP_I2CTxFIFOFlush \ + ROM_I2CTxFIFOFlush +#else +#define MAP_I2CTxFIFOFlush \ + I2CTxFIFOFlush +#endif +#ifdef ROM_I2CRxFIFOConfigSet +#define MAP_I2CRxFIFOConfigSet \ + ROM_I2CRxFIFOConfigSet +#else +#define MAP_I2CRxFIFOConfigSet \ + I2CRxFIFOConfigSet +#endif +#ifdef ROM_I2CRxFIFOFlush +#define MAP_I2CRxFIFOFlush \ + ROM_I2CRxFIFOFlush +#else +#define MAP_I2CRxFIFOFlush \ + I2CRxFIFOFlush +#endif +#ifdef ROM_I2CFIFOStatus +#define MAP_I2CFIFOStatus \ + ROM_I2CFIFOStatus +#else +#define MAP_I2CFIFOStatus \ + I2CFIFOStatus +#endif +#ifdef ROM_I2CFIFODataPut +#define MAP_I2CFIFODataPut \ + ROM_I2CFIFODataPut +#else +#define MAP_I2CFIFODataPut \ + I2CFIFODataPut +#endif +#ifdef ROM_I2CFIFODataPutNonBlocking +#define MAP_I2CFIFODataPutNonBlocking \ + ROM_I2CFIFODataPutNonBlocking +#else +#define MAP_I2CFIFODataPutNonBlocking \ + I2CFIFODataPutNonBlocking +#endif +#ifdef ROM_I2CFIFODataGet +#define MAP_I2CFIFODataGet \ + ROM_I2CFIFODataGet +#else +#define MAP_I2CFIFODataGet \ + I2CFIFODataGet +#endif +#ifdef ROM_I2CFIFODataGetNonBlocking +#define MAP_I2CFIFODataGetNonBlocking \ + ROM_I2CFIFODataGetNonBlocking +#else +#define MAP_I2CFIFODataGetNonBlocking \ + I2CFIFODataGetNonBlocking +#endif +#ifdef ROM_I2CMasterBurstLengthSet +#define MAP_I2CMasterBurstLengthSet \ + ROM_I2CMasterBurstLengthSet +#else +#define MAP_I2CMasterBurstLengthSet \ + I2CMasterBurstLengthSet +#endif +#ifdef ROM_I2CMasterBurstCountGet +#define MAP_I2CMasterBurstCountGet \ + ROM_I2CMasterBurstCountGet +#else +#define MAP_I2CMasterBurstCountGet \ + I2CMasterBurstCountGet +#endif +#ifdef ROM_I2CMasterGlitchFilterConfigSet +#define MAP_I2CMasterGlitchFilterConfigSet \ + ROM_I2CMasterGlitchFilterConfigSet +#else +#define MAP_I2CMasterGlitchFilterConfigSet \ + I2CMasterGlitchFilterConfigSet +#endif +#ifdef ROM_I2CSlaveFIFOEnable +#define MAP_I2CSlaveFIFOEnable \ + ROM_I2CSlaveFIFOEnable +#else +#define MAP_I2CSlaveFIFOEnable \ + I2CSlaveFIFOEnable +#endif +#ifdef ROM_I2CSlaveFIFODisable +#define MAP_I2CSlaveFIFODisable \ + ROM_I2CSlaveFIFODisable +#else +#define MAP_I2CSlaveFIFODisable \ + I2CSlaveFIFODisable +#endif +#ifdef ROM_I2CMasterBusBusy +#define MAP_I2CMasterBusBusy \ + ROM_I2CMasterBusBusy +#else +#define MAP_I2CMasterBusBusy \ + I2CMasterBusBusy +#endif +#ifdef ROM_I2CMasterBusy +#define MAP_I2CMasterBusy \ + ROM_I2CMasterBusy +#else +#define MAP_I2CMasterBusy \ + I2CMasterBusy +#endif +#ifdef ROM_I2CMasterControl +#define MAP_I2CMasterControl \ + ROM_I2CMasterControl +#else +#define MAP_I2CMasterControl \ + I2CMasterControl +#endif +#ifdef ROM_I2CMasterDataGet +#define MAP_I2CMasterDataGet \ + ROM_I2CMasterDataGet +#else +#define MAP_I2CMasterDataGet \ + I2CMasterDataGet +#endif +#ifdef ROM_I2CMasterDataPut +#define MAP_I2CMasterDataPut \ + ROM_I2CMasterDataPut +#else +#define MAP_I2CMasterDataPut \ + I2CMasterDataPut +#endif +#ifdef ROM_I2CMasterDisable +#define MAP_I2CMasterDisable \ + ROM_I2CMasterDisable +#else +#define MAP_I2CMasterDisable \ + I2CMasterDisable +#endif +#ifdef ROM_I2CMasterEnable +#define MAP_I2CMasterEnable \ + ROM_I2CMasterEnable +#else +#define MAP_I2CMasterEnable \ + I2CMasterEnable +#endif +#ifdef ROM_I2CMasterErr +#define MAP_I2CMasterErr \ + ROM_I2CMasterErr +#else +#define MAP_I2CMasterErr \ + I2CMasterErr +#endif +#ifdef ROM_I2CMasterIntClear +#define MAP_I2CMasterIntClear \ + ROM_I2CMasterIntClear +#else +#define MAP_I2CMasterIntClear \ + I2CMasterIntClear +#endif +#ifdef ROM_I2CMasterIntDisable +#define MAP_I2CMasterIntDisable \ + ROM_I2CMasterIntDisable +#else +#define MAP_I2CMasterIntDisable \ + I2CMasterIntDisable +#endif +#ifdef ROM_I2CMasterIntEnable +#define MAP_I2CMasterIntEnable \ + ROM_I2CMasterIntEnable +#else +#define MAP_I2CMasterIntEnable \ + I2CMasterIntEnable +#endif +#ifdef ROM_I2CMasterIntStatus +#define MAP_I2CMasterIntStatus \ + ROM_I2CMasterIntStatus +#else +#define MAP_I2CMasterIntStatus \ + I2CMasterIntStatus +#endif +#ifdef ROM_I2CMasterIntEnableEx +#define MAP_I2CMasterIntEnableEx \ + ROM_I2CMasterIntEnableEx +#else +#define MAP_I2CMasterIntEnableEx \ + I2CMasterIntEnableEx +#endif +#ifdef ROM_I2CMasterIntDisableEx +#define MAP_I2CMasterIntDisableEx \ + ROM_I2CMasterIntDisableEx +#else +#define MAP_I2CMasterIntDisableEx \ + I2CMasterIntDisableEx +#endif +#ifdef ROM_I2CMasterIntStatusEx +#define MAP_I2CMasterIntStatusEx \ + ROM_I2CMasterIntStatusEx +#else +#define MAP_I2CMasterIntStatusEx \ + I2CMasterIntStatusEx +#endif +#ifdef ROM_I2CMasterIntClearEx +#define MAP_I2CMasterIntClearEx \ + ROM_I2CMasterIntClearEx +#else +#define MAP_I2CMasterIntClearEx \ + I2CMasterIntClearEx +#endif +#ifdef ROM_I2CMasterTimeoutSet +#define MAP_I2CMasterTimeoutSet \ + ROM_I2CMasterTimeoutSet +#else +#define MAP_I2CMasterTimeoutSet \ + I2CMasterTimeoutSet +#endif +#ifdef ROM_I2CSlaveACKOverride +#define MAP_I2CSlaveACKOverride \ + ROM_I2CSlaveACKOverride +#else +#define MAP_I2CSlaveACKOverride \ + I2CSlaveACKOverride +#endif +#ifdef ROM_I2CSlaveACKValueSet +#define MAP_I2CSlaveACKValueSet \ + ROM_I2CSlaveACKValueSet +#else +#define MAP_I2CSlaveACKValueSet \ + I2CSlaveACKValueSet +#endif +#ifdef ROM_I2CMasterLineStateGet +#define MAP_I2CMasterLineStateGet \ + ROM_I2CMasterLineStateGet +#else +#define MAP_I2CMasterLineStateGet \ + I2CMasterLineStateGet +#endif +#ifdef ROM_I2CMasterSlaveAddrSet +#define MAP_I2CMasterSlaveAddrSet \ + ROM_I2CMasterSlaveAddrSet +#else +#define MAP_I2CMasterSlaveAddrSet \ + I2CMasterSlaveAddrSet +#endif +#ifdef ROM_I2CSlaveDataGet +#define MAP_I2CSlaveDataGet \ + ROM_I2CSlaveDataGet +#else +#define MAP_I2CSlaveDataGet \ + I2CSlaveDataGet +#endif +#ifdef ROM_I2CSlaveDataPut +#define MAP_I2CSlaveDataPut \ + ROM_I2CSlaveDataPut +#else +#define MAP_I2CSlaveDataPut \ + I2CSlaveDataPut +#endif +#ifdef ROM_I2CSlaveDisable +#define MAP_I2CSlaveDisable \ + ROM_I2CSlaveDisable +#else +#define MAP_I2CSlaveDisable \ + I2CSlaveDisable +#endif +#ifdef ROM_I2CSlaveEnable +#define MAP_I2CSlaveEnable \ + ROM_I2CSlaveEnable +#else +#define MAP_I2CSlaveEnable \ + I2CSlaveEnable +#endif +#ifdef ROM_I2CSlaveInit +#define MAP_I2CSlaveInit \ + ROM_I2CSlaveInit +#else +#define MAP_I2CSlaveInit \ + I2CSlaveInit +#endif +#ifdef ROM_I2CSlaveAddressSet +#define MAP_I2CSlaveAddressSet \ + ROM_I2CSlaveAddressSet +#else +#define MAP_I2CSlaveAddressSet \ + I2CSlaveAddressSet +#endif +#ifdef ROM_I2CSlaveIntClear +#define MAP_I2CSlaveIntClear \ + ROM_I2CSlaveIntClear +#else +#define MAP_I2CSlaveIntClear \ + I2CSlaveIntClear +#endif +#ifdef ROM_I2CSlaveIntDisable +#define MAP_I2CSlaveIntDisable \ + ROM_I2CSlaveIntDisable +#else +#define MAP_I2CSlaveIntDisable \ + I2CSlaveIntDisable +#endif +#ifdef ROM_I2CSlaveIntEnable +#define MAP_I2CSlaveIntEnable \ + ROM_I2CSlaveIntEnable +#else +#define MAP_I2CSlaveIntEnable \ + I2CSlaveIntEnable +#endif +#ifdef ROM_I2CSlaveIntClearEx +#define MAP_I2CSlaveIntClearEx \ + ROM_I2CSlaveIntClearEx +#else +#define MAP_I2CSlaveIntClearEx \ + I2CSlaveIntClearEx +#endif +#ifdef ROM_I2CSlaveIntDisableEx +#define MAP_I2CSlaveIntDisableEx \ + ROM_I2CSlaveIntDisableEx +#else +#define MAP_I2CSlaveIntDisableEx \ + I2CSlaveIntDisableEx +#endif +#ifdef ROM_I2CSlaveIntEnableEx +#define MAP_I2CSlaveIntEnableEx \ + ROM_I2CSlaveIntEnableEx +#else +#define MAP_I2CSlaveIntEnableEx \ + I2CSlaveIntEnableEx +#endif +#ifdef ROM_I2CSlaveIntStatus +#define MAP_I2CSlaveIntStatus \ + ROM_I2CSlaveIntStatus +#else +#define MAP_I2CSlaveIntStatus \ + I2CSlaveIntStatus +#endif +#ifdef ROM_I2CSlaveIntStatusEx +#define MAP_I2CSlaveIntStatusEx \ + ROM_I2CSlaveIntStatusEx +#else +#define MAP_I2CSlaveIntStatusEx \ + I2CSlaveIntStatusEx +#endif +#ifdef ROM_I2CSlaveStatus +#define MAP_I2CSlaveStatus \ + ROM_I2CSlaveStatus +#else +#define MAP_I2CSlaveStatus \ + I2CSlaveStatus +#endif +#ifdef ROM_I2CMasterInitExpClk +#define MAP_I2CMasterInitExpClk \ + ROM_I2CMasterInitExpClk +#else +#define MAP_I2CMasterInitExpClk \ + I2CMasterInitExpClk +#endif + +//***************************************************************************** +// +// Macros for the SPI API. +// +//***************************************************************************** +#ifdef ROM_SPIEnable +#define MAP_SPIEnable \ + ROM_SPIEnable +#else +#define MAP_SPIEnable \ + SPIEnable +#endif +#ifdef ROM_SPIDisable +#define MAP_SPIDisable \ + ROM_SPIDisable +#else +#define MAP_SPIDisable \ + SPIDisable +#endif +#ifdef ROM_SPIReset +#define MAP_SPIReset \ + ROM_SPIReset +#else +#define MAP_SPIReset \ + SPIReset +#endif +#ifdef ROM_SPIConfigSetExpClk +#define MAP_SPIConfigSetExpClk \ + ROM_SPIConfigSetExpClk +#else +#define MAP_SPIConfigSetExpClk \ + SPIConfigSetExpClk +#endif +#ifdef ROM_SPIDataGetNonBlocking +#define MAP_SPIDataGetNonBlocking \ + ROM_SPIDataGetNonBlocking +#else +#define MAP_SPIDataGetNonBlocking \ + SPIDataGetNonBlocking +#endif +#ifdef ROM_SPIDataGet +#define MAP_SPIDataGet \ + ROM_SPIDataGet +#else +#define MAP_SPIDataGet \ + SPIDataGet +#endif +#ifdef ROM_SPIDataPutNonBlocking +#define MAP_SPIDataPutNonBlocking \ + ROM_SPIDataPutNonBlocking +#else +#define MAP_SPIDataPutNonBlocking \ + SPIDataPutNonBlocking +#endif +#ifdef ROM_SPIDataPut +#define MAP_SPIDataPut \ + ROM_SPIDataPut +#else +#define MAP_SPIDataPut \ + SPIDataPut +#endif +#ifdef ROM_SPIFIFOEnable +#define MAP_SPIFIFOEnable \ + ROM_SPIFIFOEnable +#else +#define MAP_SPIFIFOEnable \ + SPIFIFOEnable +#endif +#ifdef ROM_SPIFIFODisable +#define MAP_SPIFIFODisable \ + ROM_SPIFIFODisable +#else +#define MAP_SPIFIFODisable \ + SPIFIFODisable +#endif +#ifdef ROM_SPIFIFOLevelSet +#define MAP_SPIFIFOLevelSet \ + ROM_SPIFIFOLevelSet +#else +#define MAP_SPIFIFOLevelSet \ + SPIFIFOLevelSet +#endif +#ifdef ROM_SPIFIFOLevelGet +#define MAP_SPIFIFOLevelGet \ + ROM_SPIFIFOLevelGet +#else +#define MAP_SPIFIFOLevelGet \ + SPIFIFOLevelGet +#endif +#ifdef ROM_SPIWordCountSet +#define MAP_SPIWordCountSet \ + ROM_SPIWordCountSet +#else +#define MAP_SPIWordCountSet \ + SPIWordCountSet +#endif +#ifdef ROM_SPIIntRegister +#define MAP_SPIIntRegister \ + ROM_SPIIntRegister +#else +#define MAP_SPIIntRegister \ + SPIIntRegister +#endif +#ifdef ROM_SPIIntUnregister +#define MAP_SPIIntUnregister \ + ROM_SPIIntUnregister +#else +#define MAP_SPIIntUnregister \ + SPIIntUnregister +#endif +#ifdef ROM_SPIIntEnable +#define MAP_SPIIntEnable \ + ROM_SPIIntEnable +#else +#define MAP_SPIIntEnable \ + SPIIntEnable +#endif +#ifdef ROM_SPIIntDisable +#define MAP_SPIIntDisable \ + ROM_SPIIntDisable +#else +#define MAP_SPIIntDisable \ + SPIIntDisable +#endif +#ifdef ROM_SPIIntStatus +#define MAP_SPIIntStatus \ + ROM_SPIIntStatus +#else +#define MAP_SPIIntStatus \ + SPIIntStatus +#endif +#ifdef ROM_SPIIntClear +#define MAP_SPIIntClear \ + ROM_SPIIntClear +#else +#define MAP_SPIIntClear \ + SPIIntClear +#endif +#ifdef ROM_SPIDmaEnable +#define MAP_SPIDmaEnable \ + ROM_SPIDmaEnable +#else +#define MAP_SPIDmaEnable \ + SPIDmaEnable +#endif +#ifdef ROM_SPIDmaDisable +#define MAP_SPIDmaDisable \ + ROM_SPIDmaDisable +#else +#define MAP_SPIDmaDisable \ + SPIDmaDisable +#endif +#ifdef ROM_SPICSEnable +#define MAP_SPICSEnable \ + ROM_SPICSEnable +#else +#define MAP_SPICSEnable \ + SPICSEnable +#endif +#ifdef ROM_SPICSDisable +#define MAP_SPICSDisable \ + ROM_SPICSDisable +#else +#define MAP_SPICSDisable \ + SPICSDisable +#endif +#ifdef ROM_SPITransfer +#define MAP_SPITransfer \ + ROM_SPITransfer +#else +#define MAP_SPITransfer \ + SPITransfer +#endif + +//***************************************************************************** +// +// Macros for the CAM API. +// +//***************************************************************************** +#ifdef ROM_CameraReset +#define MAP_CameraReset \ + ROM_CameraReset +#else +#define MAP_CameraReset \ + CameraReset +#endif +#ifdef ROM_CameraParamsConfig +#define MAP_CameraParamsConfig \ + ROM_CameraParamsConfig +#else +#define MAP_CameraParamsConfig \ + CameraParamsConfig +#endif +#ifdef ROM_CameraXClkConfig +#define MAP_CameraXClkConfig \ + ROM_CameraXClkConfig +#else +#define MAP_CameraXClkConfig \ + CameraXClkConfig +#endif +#ifdef ROM_CameraXClkSet +#define MAP_CameraXClkSet \ + ROM_CameraXClkSet +#else +#define MAP_CameraXClkSet \ + CameraXClkSet +#endif +#ifdef ROM_CameraDMAEnable +#define MAP_CameraDMAEnable \ + ROM_CameraDMAEnable +#else +#define MAP_CameraDMAEnable \ + CameraDMAEnable +#endif +#ifdef ROM_CameraDMADisable +#define MAP_CameraDMADisable \ + ROM_CameraDMADisable +#else +#define MAP_CameraDMADisable \ + CameraDMADisable +#endif +#ifdef ROM_CameraThresholdSet +#define MAP_CameraThresholdSet \ + ROM_CameraThresholdSet +#else +#define MAP_CameraThresholdSet \ + CameraThresholdSet +#endif +#ifdef ROM_CameraIntRegister +#define MAP_CameraIntRegister \ + ROM_CameraIntRegister +#else +#define MAP_CameraIntRegister \ + CameraIntRegister +#endif +#ifdef ROM_CameraIntUnregister +#define MAP_CameraIntUnregister \ + ROM_CameraIntUnregister +#else +#define MAP_CameraIntUnregister \ + CameraIntUnregister +#endif +#ifdef ROM_CameraIntEnable +#define MAP_CameraIntEnable \ + ROM_CameraIntEnable +#else +#define MAP_CameraIntEnable \ + CameraIntEnable +#endif +#ifdef ROM_CameraIntDisable +#define MAP_CameraIntDisable \ + ROM_CameraIntDisable +#else +#define MAP_CameraIntDisable \ + CameraIntDisable +#endif +#ifdef ROM_CameraIntStatus +#define MAP_CameraIntStatus \ + ROM_CameraIntStatus +#else +#define MAP_CameraIntStatus \ + CameraIntStatus +#endif +#ifdef ROM_CameraIntClear +#define MAP_CameraIntClear \ + ROM_CameraIntClear +#else +#define MAP_CameraIntClear \ + CameraIntClear +#endif +#ifdef ROM_CameraCaptureStop +#define MAP_CameraCaptureStop \ + ROM_CameraCaptureStop +#else +#define MAP_CameraCaptureStop \ + CameraCaptureStop +#endif +#ifdef ROM_CameraCaptureStart +#define MAP_CameraCaptureStart \ + ROM_CameraCaptureStart +#else +#define MAP_CameraCaptureStart \ + CameraCaptureStart +#endif +#ifdef ROM_CameraBufferRead +#define MAP_CameraBufferRead \ + ROM_CameraBufferRead +#else +#define MAP_CameraBufferRead \ + CameraBufferRead +#endif + +//***************************************************************************** +// +// Macros for the FLASH API. +// +//***************************************************************************** +#ifdef ROM_FlashDisable +#define MAP_FlashDisable \ + ROM_FlashDisable +#else +#define MAP_FlashDisable \ + FlashDisable +#endif +#ifdef ROM_FlashErase +#define MAP_FlashErase \ + ROM_FlashErase +#else +#define MAP_FlashErase \ + FlashErase +#endif +#ifdef ROM_FlashMassErase +#define MAP_FlashMassErase \ + ROM_FlashMassErase +#else +#define MAP_FlashMassErase \ + FlashMassErase +#endif +#ifdef ROM_FlashMassEraseNonBlocking +#define MAP_FlashMassEraseNonBlocking \ + ROM_FlashMassEraseNonBlocking +#else +#define MAP_FlashMassEraseNonBlocking \ + FlashMassEraseNonBlocking +#endif +#ifdef ROM_FlashEraseNonBlocking +#define MAP_FlashEraseNonBlocking \ + ROM_FlashEraseNonBlocking +#else +#define MAP_FlashEraseNonBlocking \ + FlashEraseNonBlocking +#endif +#ifdef ROM_FlashProgram +#define MAP_FlashProgram \ + ROM_FlashProgram +#else +#define MAP_FlashProgram \ + FlashProgram +#endif +#ifdef ROM_FlashProgramNonBlocking +#define MAP_FlashProgramNonBlocking \ + ROM_FlashProgramNonBlocking +#else +#define MAP_FlashProgramNonBlocking \ + FlashProgramNonBlocking +#endif +#ifdef ROM_FlashIntRegister +#define MAP_FlashIntRegister \ + ROM_FlashIntRegister +#else +#define MAP_FlashIntRegister \ + FlashIntRegister +#endif +#ifdef ROM_FlashIntUnregister +#define MAP_FlashIntUnregister \ + ROM_FlashIntUnregister +#else +#define MAP_FlashIntUnregister \ + FlashIntUnregister +#endif +#ifdef ROM_FlashIntEnable +#define MAP_FlashIntEnable \ + ROM_FlashIntEnable +#else +#define MAP_FlashIntEnable \ + FlashIntEnable +#endif +#ifdef ROM_FlashIntDisable +#define MAP_FlashIntDisable \ + ROM_FlashIntDisable +#else +#define MAP_FlashIntDisable \ + FlashIntDisable +#endif +#ifdef ROM_FlashIntStatus +#define MAP_FlashIntStatus \ + ROM_FlashIntStatus +#else +#define MAP_FlashIntStatus \ + FlashIntStatus +#endif +#ifdef ROM_FlashIntClear +#define MAP_FlashIntClear \ + ROM_FlashIntClear +#else +#define MAP_FlashIntClear \ + FlashIntClear +#endif +#ifdef ROM_FlashProtectGet +#define MAP_FlashProtectGet \ + ROM_FlashProtectGet +#else +#define MAP_FlashProtectGet \ + FlashProtectGet +#endif + +//***************************************************************************** +// +// Macros for the Pin API. +// +//***************************************************************************** +#ifdef ROM_PinModeSet +#define MAP_PinModeSet \ + ROM_PinModeSet +#else +#define MAP_PinModeSet \ + PinModeSet +#endif +#ifdef ROM_PinDirModeSet +#define MAP_PinDirModeSet \ + ROM_PinDirModeSet +#else +#define MAP_PinDirModeSet \ + PinDirModeSet +#endif +#ifdef ROM_PinDirModeGet +#define MAP_PinDirModeGet \ + ROM_PinDirModeGet +#else +#define MAP_PinDirModeGet \ + PinDirModeGet +#endif +#ifdef ROM_PinModeGet +#define MAP_PinModeGet \ + ROM_PinModeGet +#else +#define MAP_PinModeGet \ + PinModeGet +#endif +#ifdef ROM_PinConfigGet +#define MAP_PinConfigGet \ + ROM_PinConfigGet +#else +#define MAP_PinConfigGet \ + PinConfigGet +#endif +#ifdef ROM_PinConfigSet +#define MAP_PinConfigSet \ + ROM_PinConfigSet +#else +#define MAP_PinConfigSet \ + PinConfigSet +#endif +#ifdef ROM_PinTypeUART +#define MAP_PinTypeUART \ + ROM_PinTypeUART +#else +#define MAP_PinTypeUART \ + PinTypeUART +#endif +#ifdef ROM_PinTypeI2C +#define MAP_PinTypeI2C \ + ROM_PinTypeI2C +#else +#define MAP_PinTypeI2C \ + PinTypeI2C +#endif +#ifdef ROM_PinTypeSPI +#define MAP_PinTypeSPI \ + ROM_PinTypeSPI +#else +#define MAP_PinTypeSPI \ + PinTypeSPI +#endif +#ifdef ROM_PinTypeI2S +#define MAP_PinTypeI2S \ + ROM_PinTypeI2S +#else +#define MAP_PinTypeI2S \ + PinTypeI2S +#endif +#ifdef ROM_PinTypeTimer +#define MAP_PinTypeTimer \ + ROM_PinTypeTimer +#else +#define MAP_PinTypeTimer \ + PinTypeTimer +#endif +#ifdef ROM_PinTypeCamera +#define MAP_PinTypeCamera \ + ROM_PinTypeCamera +#else +#define MAP_PinTypeCamera \ + PinTypeCamera +#endif +#ifdef ROM_PinTypeGPIO +#define MAP_PinTypeGPIO \ + ROM_PinTypeGPIO +#else +#define MAP_PinTypeGPIO \ + PinTypeGPIO +#endif +#ifdef ROM_PinTypeADC +#define MAP_PinTypeADC \ + ROM_PinTypeADC +#else +#define MAP_PinTypeADC \ + PinTypeADC +#endif +#ifdef ROM_PinTypeSDHost +#define MAP_PinTypeSDHost \ + ROM_PinTypeSDHost +#else +#define MAP_PinTypeSDHost \ + PinTypeSDHost +#endif +#ifdef ROM_PinHysteresisSet +#define MAP_PinHysteresisSet \ + ROM_PinHysteresisSet +#else +#define MAP_PinHysteresisSet \ + PinHysteresisSet +#endif +#ifdef ROM_PinLockLevelSet +#define MAP_PinLockLevelSet \ + ROM_PinLockLevelSet +#else +#define MAP_PinLockLevelSet \ + PinLockLevelSet +#endif +#ifdef ROM_PinLock +#define MAP_PinLock \ + ROM_PinLock +#else +#define MAP_PinLock \ + PinLock +#endif +#ifdef ROM_PinUnlock +#define MAP_PinUnlock \ + ROM_PinUnlock +#else +#define MAP_PinUnlock \ + PinUnlock +#endif + +//***************************************************************************** +// +// Macros for the SYSTICK API. +// +//***************************************************************************** +#ifdef ROM_SysTickEnable +#define MAP_SysTickEnable \ + ROM_SysTickEnable +#else +#define MAP_SysTickEnable \ + SysTickEnable +#endif +#ifdef ROM_SysTickDisable +#define MAP_SysTickDisable \ + ROM_SysTickDisable +#else +#define MAP_SysTickDisable \ + SysTickDisable +#endif +#ifdef ROM_SysTickIntRegister +#define MAP_SysTickIntRegister \ + ROM_SysTickIntRegister +#else +#define MAP_SysTickIntRegister \ + SysTickIntRegister +#endif +#ifdef ROM_SysTickIntUnregister +#define MAP_SysTickIntUnregister \ + ROM_SysTickIntUnregister +#else +#define MAP_SysTickIntUnregister \ + SysTickIntUnregister +#endif +#ifdef ROM_SysTickIntEnable +#define MAP_SysTickIntEnable \ + ROM_SysTickIntEnable +#else +#define MAP_SysTickIntEnable \ + SysTickIntEnable +#endif +#ifdef ROM_SysTickIntDisable +#define MAP_SysTickIntDisable \ + ROM_SysTickIntDisable +#else +#define MAP_SysTickIntDisable \ + SysTickIntDisable +#endif +#ifdef ROM_SysTickPeriodSet +#define MAP_SysTickPeriodSet \ + ROM_SysTickPeriodSet +#else +#define MAP_SysTickPeriodSet \ + SysTickPeriodSet +#endif +#ifdef ROM_SysTickPeriodGet +#define MAP_SysTickPeriodGet \ + ROM_SysTickPeriodGet +#else +#define MAP_SysTickPeriodGet \ + SysTickPeriodGet +#endif +#ifdef ROM_SysTickValueGet +#define MAP_SysTickValueGet \ + ROM_SysTickValueGet +#else +#define MAP_SysTickValueGet \ + SysTickValueGet +#endif + +//***************************************************************************** +// +// Macros for the UTILS API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define MAP_UtilsDelay \ + ROM_UtilsDelay +#else +#define MAP_UtilsDelay \ + UtilsDelay +#endif + +//***************************************************************************** +// +// Macros for the I2S API. +// +//***************************************************************************** +#ifdef ROM_I2SEnable +#define MAP_I2SEnable \ + ROM_I2SEnable +#else +#define MAP_I2SEnable \ + I2SEnable +#endif +#ifdef ROM_I2SDisable +#define MAP_I2SDisable \ + ROM_I2SDisable +#else +#define MAP_I2SDisable \ + I2SDisable +#endif +#ifdef ROM_I2SDataPut +#define MAP_I2SDataPut \ + ROM_I2SDataPut +#else +#define MAP_I2SDataPut \ + I2SDataPut +#endif +#ifdef ROM_I2SDataPutNonBlocking +#define MAP_I2SDataPutNonBlocking \ + ROM_I2SDataPutNonBlocking +#else +#define MAP_I2SDataPutNonBlocking \ + I2SDataPutNonBlocking +#endif +#ifdef ROM_I2SDataGet +#define MAP_I2SDataGet \ + ROM_I2SDataGet +#else +#define MAP_I2SDataGet \ + I2SDataGet +#endif +#ifdef ROM_I2SDataGetNonBlocking +#define MAP_I2SDataGetNonBlocking \ + ROM_I2SDataGetNonBlocking +#else +#define MAP_I2SDataGetNonBlocking \ + I2SDataGetNonBlocking +#endif +#ifdef ROM_I2SConfigSetExpClk +#define MAP_I2SConfigSetExpClk \ + ROM_I2SConfigSetExpClk +#else +#define MAP_I2SConfigSetExpClk \ + I2SConfigSetExpClk +#endif +#ifdef ROM_I2STxFIFOEnable +#define MAP_I2STxFIFOEnable \ + ROM_I2STxFIFOEnable +#else +#define MAP_I2STxFIFOEnable \ + I2STxFIFOEnable +#endif +#ifdef ROM_I2STxFIFODisable +#define MAP_I2STxFIFODisable \ + ROM_I2STxFIFODisable +#else +#define MAP_I2STxFIFODisable \ + I2STxFIFODisable +#endif +#ifdef ROM_I2SRxFIFOEnable +#define MAP_I2SRxFIFOEnable \ + ROM_I2SRxFIFOEnable +#else +#define MAP_I2SRxFIFOEnable \ + I2SRxFIFOEnable +#endif +#ifdef ROM_I2SRxFIFODisable +#define MAP_I2SRxFIFODisable \ + ROM_I2SRxFIFODisable +#else +#define MAP_I2SRxFIFODisable \ + I2SRxFIFODisable +#endif +#ifdef ROM_I2STxFIFOStatusGet +#define MAP_I2STxFIFOStatusGet \ + ROM_I2STxFIFOStatusGet +#else +#define MAP_I2STxFIFOStatusGet \ + I2STxFIFOStatusGet +#endif +#ifdef ROM_I2SRxFIFOStatusGet +#define MAP_I2SRxFIFOStatusGet \ + ROM_I2SRxFIFOStatusGet +#else +#define MAP_I2SRxFIFOStatusGet \ + I2SRxFIFOStatusGet +#endif +#ifdef ROM_I2SSerializerConfig +#define MAP_I2SSerializerConfig \ + ROM_I2SSerializerConfig +#else +#define MAP_I2SSerializerConfig \ + I2SSerializerConfig +#endif +#ifdef ROM_I2SIntEnable +#define MAP_I2SIntEnable \ + ROM_I2SIntEnable +#else +#define MAP_I2SIntEnable \ + I2SIntEnable +#endif +#ifdef ROM_I2SIntDisable +#define MAP_I2SIntDisable \ + ROM_I2SIntDisable +#else +#define MAP_I2SIntDisable \ + I2SIntDisable +#endif +#ifdef ROM_I2SIntStatus +#define MAP_I2SIntStatus \ + ROM_I2SIntStatus +#else +#define MAP_I2SIntStatus \ + I2SIntStatus +#endif +#ifdef ROM_I2SIntClear +#define MAP_I2SIntClear \ + ROM_I2SIntClear +#else +#define MAP_I2SIntClear \ + I2SIntClear +#endif +#ifdef ROM_I2SIntRegister +#define MAP_I2SIntRegister \ + ROM_I2SIntRegister +#else +#define MAP_I2SIntRegister \ + I2SIntRegister +#endif +#ifdef ROM_I2SIntUnregister +#define MAP_I2SIntUnregister \ + ROM_I2SIntUnregister +#else +#define MAP_I2SIntUnregister \ + I2SIntUnregister +#endif +#ifdef ROM_I2STxActiveSlotSet +#define MAP_I2STxActiveSlotSet \ + ROM_I2STxActiveSlotSet +#else +#define MAP_I2STxActiveSlotSet \ + I2STxActiveSlotSet +#endif +#ifdef ROM_I2SRxActiveSlotSet +#define MAP_I2SRxActiveSlotSet \ + ROM_I2SRxActiveSlotSet +#else +#define MAP_I2SRxActiveSlotSet \ + I2SRxActiveSlotSet +#endif + +//***************************************************************************** +// +// Macros for the GPIO API. +// +//***************************************************************************** +#ifdef ROM_GPIODirModeSet +#define MAP_GPIODirModeSet \ + ROM_GPIODirModeSet +#else +#define MAP_GPIODirModeSet \ + GPIODirModeSet +#endif +#ifdef ROM_GPIODirModeGet +#define MAP_GPIODirModeGet \ + ROM_GPIODirModeGet +#else +#define MAP_GPIODirModeGet \ + GPIODirModeGet +#endif +#ifdef ROM_GPIOIntTypeSet +#define MAP_GPIOIntTypeSet \ + ROM_GPIOIntTypeSet +#else +#define MAP_GPIOIntTypeSet \ + GPIOIntTypeSet +#endif +#ifdef ROM_GPIODMATriggerEnable +#define MAP_GPIODMATriggerEnable \ + ROM_GPIODMATriggerEnable +#else +#define MAP_GPIODMATriggerEnable \ + GPIODMATriggerEnable +#endif +#ifdef ROM_GPIODMATriggerDisable +#define MAP_GPIODMATriggerDisable \ + ROM_GPIODMATriggerDisable +#else +#define MAP_GPIODMATriggerDisable \ + GPIODMATriggerDisable +#endif +#ifdef ROM_GPIOIntTypeGet +#define MAP_GPIOIntTypeGet \ + ROM_GPIOIntTypeGet +#else +#define MAP_GPIOIntTypeGet \ + GPIOIntTypeGet +#endif +#ifdef ROM_GPIOIntEnable +#define MAP_GPIOIntEnable \ + ROM_GPIOIntEnable +#else +#define MAP_GPIOIntEnable \ + GPIOIntEnable +#endif +#ifdef ROM_GPIOIntDisable +#define MAP_GPIOIntDisable \ + ROM_GPIOIntDisable +#else +#define MAP_GPIOIntDisable \ + GPIOIntDisable +#endif +#ifdef ROM_GPIOIntStatus +#define MAP_GPIOIntStatus \ + ROM_GPIOIntStatus +#else +#define MAP_GPIOIntStatus \ + GPIOIntStatus +#endif +#ifdef ROM_GPIOIntClear +#define MAP_GPIOIntClear \ + ROM_GPIOIntClear +#else +#define MAP_GPIOIntClear \ + GPIOIntClear +#endif +#ifdef ROM_GPIOIntRegister +#define MAP_GPIOIntRegister \ + ROM_GPIOIntRegister +#else +#define MAP_GPIOIntRegister \ + GPIOIntRegister +#endif +#ifdef ROM_GPIOIntUnregister +#define MAP_GPIOIntUnregister \ + ROM_GPIOIntUnregister +#else +#define MAP_GPIOIntUnregister \ + GPIOIntUnregister +#endif +#ifdef ROM_GPIOPinRead +#define MAP_GPIOPinRead \ + ROM_GPIOPinRead +#else +#define MAP_GPIOPinRead \ + GPIOPinRead +#endif +#ifdef ROM_GPIOPinWrite +#define MAP_GPIOPinWrite \ + ROM_GPIOPinWrite +#else +#define MAP_GPIOPinWrite \ + GPIOPinWrite +#endif + +//***************************************************************************** +// +// Macros for the AES API. +// +//***************************************************************************** +#ifdef ROM_AESConfigSet +#define MAP_AESConfigSet \ + ROM_AESConfigSet +#else +#define MAP_AESConfigSet \ + AESConfigSet +#endif +#ifdef ROM_AESKey1Set +#define MAP_AESKey1Set \ + ROM_AESKey1Set +#else +#define MAP_AESKey1Set \ + AESKey1Set +#endif +#ifdef ROM_AESKey2Set +#define MAP_AESKey2Set \ + ROM_AESKey2Set +#else +#define MAP_AESKey2Set \ + AESKey2Set +#endif +#ifdef ROM_AESKey3Set +#define MAP_AESKey3Set \ + ROM_AESKey3Set +#else +#define MAP_AESKey3Set \ + AESKey3Set +#endif +#ifdef ROM_AESIVSet +#define MAP_AESIVSet \ + ROM_AESIVSet +#else +#define MAP_AESIVSet \ + AESIVSet +#endif +#ifdef ROM_AESTagRead +#define MAP_AESTagRead \ + ROM_AESTagRead +#else +#define MAP_AESTagRead \ + AESTagRead +#endif +#ifdef ROM_AESDataLengthSet +#define MAP_AESDataLengthSet \ + ROM_AESDataLengthSet +#else +#define MAP_AESDataLengthSet \ + AESDataLengthSet +#endif +#ifdef ROM_AESAuthDataLengthSet +#define MAP_AESAuthDataLengthSet \ + ROM_AESAuthDataLengthSet +#else +#define MAP_AESAuthDataLengthSet \ + AESAuthDataLengthSet +#endif +#ifdef ROM_AESDataReadNonBlocking +#define MAP_AESDataReadNonBlocking \ + ROM_AESDataReadNonBlocking +#else +#define MAP_AESDataReadNonBlocking \ + AESDataReadNonBlocking +#endif +#ifdef ROM_AESDataRead +#define MAP_AESDataRead \ + ROM_AESDataRead +#else +#define MAP_AESDataRead \ + AESDataRead +#endif +#ifdef ROM_AESDataWriteNonBlocking +#define MAP_AESDataWriteNonBlocking \ + ROM_AESDataWriteNonBlocking +#else +#define MAP_AESDataWriteNonBlocking \ + AESDataWriteNonBlocking +#endif +#ifdef ROM_AESDataWrite +#define MAP_AESDataWrite \ + ROM_AESDataWrite +#else +#define MAP_AESDataWrite \ + AESDataWrite +#endif +#ifdef ROM_AESDataProcess +#define MAP_AESDataProcess \ + ROM_AESDataProcess +#else +#define MAP_AESDataProcess \ + AESDataProcess +#endif +#ifdef ROM_AESDataMAC +#define MAP_AESDataMAC \ + ROM_AESDataMAC +#else +#define MAP_AESDataMAC \ + AESDataMAC +#endif +#ifdef ROM_AESDataProcessAE +#define MAP_AESDataProcessAE \ + ROM_AESDataProcessAE +#else +#define MAP_AESDataProcessAE \ + AESDataProcessAE +#endif +#ifdef ROM_AESIntStatus +#define MAP_AESIntStatus \ + ROM_AESIntStatus +#else +#define MAP_AESIntStatus \ + AESIntStatus +#endif +#ifdef ROM_AESIntEnable +#define MAP_AESIntEnable \ + ROM_AESIntEnable +#else +#define MAP_AESIntEnable \ + AESIntEnable +#endif +#ifdef ROM_AESIntDisable +#define MAP_AESIntDisable \ + ROM_AESIntDisable +#else +#define MAP_AESIntDisable \ + AESIntDisable +#endif +#ifdef ROM_AESIntClear +#define MAP_AESIntClear \ + ROM_AESIntClear +#else +#define MAP_AESIntClear \ + AESIntClear +#endif +#ifdef ROM_AESIntRegister +#define MAP_AESIntRegister \ + ROM_AESIntRegister +#else +#define MAP_AESIntRegister \ + AESIntRegister +#endif +#ifdef ROM_AESIntUnregister +#define MAP_AESIntUnregister \ + ROM_AESIntUnregister +#else +#define MAP_AESIntUnregister \ + AESIntUnregister +#endif +#ifdef ROM_AESDMAEnable +#define MAP_AESDMAEnable \ + ROM_AESDMAEnable +#else +#define MAP_AESDMAEnable \ + AESDMAEnable +#endif +#ifdef ROM_AESDMADisable +#define MAP_AESDMADisable \ + ROM_AESDMADisable +#else +#define MAP_AESDMADisable \ + AESDMADisable +#endif +#ifdef ROM_AESIVGet +#define MAP_AESIVGet \ + ROM_AESIVGet +#else +#define MAP_AESIVGet \ + AESIVGet +#endif + +//***************************************************************************** +// +// Macros for the DES API. +// +//***************************************************************************** +#ifdef ROM_DESConfigSet +#define MAP_DESConfigSet \ + ROM_DESConfigSet +#else +#define MAP_DESConfigSet \ + DESConfigSet +#endif +#ifdef ROM_DESDataRead +#define MAP_DESDataRead \ + ROM_DESDataRead +#else +#define MAP_DESDataRead \ + DESDataRead +#endif +#ifdef ROM_DESDataReadNonBlocking +#define MAP_DESDataReadNonBlocking \ + ROM_DESDataReadNonBlocking +#else +#define MAP_DESDataReadNonBlocking \ + DESDataReadNonBlocking +#endif +#ifdef ROM_DESDataProcess +#define MAP_DESDataProcess \ + ROM_DESDataProcess +#else +#define MAP_DESDataProcess \ + DESDataProcess +#endif +#ifdef ROM_DESDataWrite +#define MAP_DESDataWrite \ + ROM_DESDataWrite +#else +#define MAP_DESDataWrite \ + DESDataWrite +#endif +#ifdef ROM_DESDataWriteNonBlocking +#define MAP_DESDataWriteNonBlocking \ + ROM_DESDataWriteNonBlocking +#else +#define MAP_DESDataWriteNonBlocking \ + DESDataWriteNonBlocking +#endif +#ifdef ROM_DESDMADisable +#define MAP_DESDMADisable \ + ROM_DESDMADisable +#else +#define MAP_DESDMADisable \ + DESDMADisable +#endif +#ifdef ROM_DESDMAEnable +#define MAP_DESDMAEnable \ + ROM_DESDMAEnable +#else +#define MAP_DESDMAEnable \ + DESDMAEnable +#endif +#ifdef ROM_DESIntClear +#define MAP_DESIntClear \ + ROM_DESIntClear +#else +#define MAP_DESIntClear \ + DESIntClear +#endif +#ifdef ROM_DESIntDisable +#define MAP_DESIntDisable \ + ROM_DESIntDisable +#else +#define MAP_DESIntDisable \ + DESIntDisable +#endif +#ifdef ROM_DESIntEnable +#define MAP_DESIntEnable \ + ROM_DESIntEnable +#else +#define MAP_DESIntEnable \ + DESIntEnable +#endif +#ifdef ROM_DESIntRegister +#define MAP_DESIntRegister \ + ROM_DESIntRegister +#else +#define MAP_DESIntRegister \ + DESIntRegister +#endif +#ifdef ROM_DESIntStatus +#define MAP_DESIntStatus \ + ROM_DESIntStatus +#else +#define MAP_DESIntStatus \ + DESIntStatus +#endif +#ifdef ROM_DESIntUnregister +#define MAP_DESIntUnregister \ + ROM_DESIntUnregister +#else +#define MAP_DESIntUnregister \ + DESIntUnregister +#endif +#ifdef ROM_DESIVSet +#define MAP_DESIVSet \ + ROM_DESIVSet +#else +#define MAP_DESIVSet \ + DESIVSet +#endif +#ifdef ROM_DESKeySet +#define MAP_DESKeySet \ + ROM_DESKeySet +#else +#define MAP_DESKeySet \ + DESKeySet +#endif +#ifdef ROM_DESDataLengthSet +#define MAP_DESDataLengthSet \ + ROM_DESDataLengthSet +#else +#define MAP_DESDataLengthSet \ + DESDataLengthSet +#endif + +//***************************************************************************** +// +// Macros for the SHAMD5 API. +// +//***************************************************************************** +#ifdef ROM_SHAMD5ConfigSet +#define MAP_SHAMD5ConfigSet \ + ROM_SHAMD5ConfigSet +#else +#define MAP_SHAMD5ConfigSet \ + SHAMD5ConfigSet +#endif +#ifdef ROM_SHAMD5DataProcess +#define MAP_SHAMD5DataProcess \ + ROM_SHAMD5DataProcess +#else +#define MAP_SHAMD5DataProcess \ + SHAMD5DataProcess +#endif +#ifdef ROM_SHAMD5DataWrite +#define MAP_SHAMD5DataWrite \ + ROM_SHAMD5DataWrite +#else +#define MAP_SHAMD5DataWrite \ + SHAMD5DataWrite +#endif +#ifdef ROM_SHAMD5DataWriteNonBlocking +#define MAP_SHAMD5DataWriteNonBlocking \ + ROM_SHAMD5DataWriteNonBlocking +#else +#define MAP_SHAMD5DataWriteNonBlocking \ + SHAMD5DataWriteNonBlocking +#endif +#ifdef ROM_SHAMD5DMADisable +#define MAP_SHAMD5DMADisable \ + ROM_SHAMD5DMADisable +#else +#define MAP_SHAMD5DMADisable \ + SHAMD5DMADisable +#endif +#ifdef ROM_SHAMD5DMAEnable +#define MAP_SHAMD5DMAEnable \ + ROM_SHAMD5DMAEnable +#else +#define MAP_SHAMD5DMAEnable \ + SHAMD5DMAEnable +#endif +#ifdef ROM_SHAMD5DataLengthSet +#define MAP_SHAMD5DataLengthSet \ + ROM_SHAMD5DataLengthSet +#else +#define MAP_SHAMD5DataLengthSet \ + SHAMD5DataLengthSet +#endif +#ifdef ROM_SHAMD5HMACKeySet +#define MAP_SHAMD5HMACKeySet \ + ROM_SHAMD5HMACKeySet +#else +#define MAP_SHAMD5HMACKeySet \ + SHAMD5HMACKeySet +#endif +#ifdef ROM_SHAMD5HMACPPKeyGenerate +#define MAP_SHAMD5HMACPPKeyGenerate \ + ROM_SHAMD5HMACPPKeyGenerate +#else +#define MAP_SHAMD5HMACPPKeyGenerate \ + SHAMD5HMACPPKeyGenerate +#endif +#ifdef ROM_SHAMD5HMACPPKeySet +#define MAP_SHAMD5HMACPPKeySet \ + ROM_SHAMD5HMACPPKeySet +#else +#define MAP_SHAMD5HMACPPKeySet \ + SHAMD5HMACPPKeySet +#endif +#ifdef ROM_SHAMD5HMACProcess +#define MAP_SHAMD5HMACProcess \ + ROM_SHAMD5HMACProcess +#else +#define MAP_SHAMD5HMACProcess \ + SHAMD5HMACProcess +#endif +#ifdef ROM_SHAMD5IntClear +#define MAP_SHAMD5IntClear \ + ROM_SHAMD5IntClear +#else +#define MAP_SHAMD5IntClear \ + SHAMD5IntClear +#endif +#ifdef ROM_SHAMD5IntDisable +#define MAP_SHAMD5IntDisable \ + ROM_SHAMD5IntDisable +#else +#define MAP_SHAMD5IntDisable \ + SHAMD5IntDisable +#endif +#ifdef ROM_SHAMD5IntEnable +#define MAP_SHAMD5IntEnable \ + ROM_SHAMD5IntEnable +#else +#define MAP_SHAMD5IntEnable \ + SHAMD5IntEnable +#endif +#ifdef ROM_SHAMD5IntRegister +#define MAP_SHAMD5IntRegister \ + ROM_SHAMD5IntRegister +#else +#define MAP_SHAMD5IntRegister \ + SHAMD5IntRegister +#endif +#ifdef ROM_SHAMD5IntStatus +#define MAP_SHAMD5IntStatus \ + ROM_SHAMD5IntStatus +#else +#define MAP_SHAMD5IntStatus \ + SHAMD5IntStatus +#endif +#ifdef ROM_SHAMD5IntUnregister +#define MAP_SHAMD5IntUnregister \ + ROM_SHAMD5IntUnregister +#else +#define MAP_SHAMD5IntUnregister \ + SHAMD5IntUnregister +#endif +#ifdef ROM_SHAMD5ResultRead +#define MAP_SHAMD5ResultRead \ + ROM_SHAMD5ResultRead +#else +#define MAP_SHAMD5ResultRead \ + SHAMD5ResultRead +#endif + +//***************************************************************************** +// +// Macros for the CRC API. +// +//***************************************************************************** +#ifdef ROM_CRCConfigSet +#define MAP_CRCConfigSet \ + ROM_CRCConfigSet +#else +#define MAP_CRCConfigSet \ + CRCConfigSet +#endif +#ifdef ROM_CRCDataProcess +#define MAP_CRCDataProcess \ + ROM_CRCDataProcess +#else +#define MAP_CRCDataProcess \ + CRCDataProcess +#endif +#ifdef ROM_CRCDataWrite +#define MAP_CRCDataWrite \ + ROM_CRCDataWrite +#else +#define MAP_CRCDataWrite \ + CRCDataWrite +#endif +#ifdef ROM_CRCResultRead +#define MAP_CRCResultRead \ + ROM_CRCResultRead +#else +#define MAP_CRCResultRead \ + CRCResultRead +#endif +#ifdef ROM_CRCSeedSet +#define MAP_CRCSeedSet \ + ROM_CRCSeedSet +#else +#define MAP_CRCSeedSet \ + CRCSeedSet +#endif + +//***************************************************************************** +// +// Macros for the SDHOST API. +// +//***************************************************************************** +#ifdef ROM_SDHostCmdReset +#define MAP_SDHostCmdReset \ + ROM_SDHostCmdReset +#else +#define MAP_SDHostCmdReset \ + SDHostCmdReset +#endif +#ifdef ROM_SDHostInit +#define MAP_SDHostInit \ + ROM_SDHostInit +#else +#define MAP_SDHostInit \ + SDHostInit +#endif +#ifdef ROM_SDHostCmdSend +#define MAP_SDHostCmdSend \ + ROM_SDHostCmdSend +#else +#define MAP_SDHostCmdSend \ + SDHostCmdSend +#endif +#ifdef ROM_SDHostIntRegister +#define MAP_SDHostIntRegister \ + ROM_SDHostIntRegister +#else +#define MAP_SDHostIntRegister \ + SDHostIntRegister +#endif +#ifdef ROM_SDHostIntUnregister +#define MAP_SDHostIntUnregister \ + ROM_SDHostIntUnregister +#else +#define MAP_SDHostIntUnregister \ + SDHostIntUnregister +#endif +#ifdef ROM_SDHostIntEnable +#define MAP_SDHostIntEnable \ + ROM_SDHostIntEnable +#else +#define MAP_SDHostIntEnable \ + SDHostIntEnable +#endif +#ifdef ROM_SDHostIntDisable +#define MAP_SDHostIntDisable \ + ROM_SDHostIntDisable +#else +#define MAP_SDHostIntDisable \ + SDHostIntDisable +#endif +#ifdef ROM_SDHostIntStatus +#define MAP_SDHostIntStatus \ + ROM_SDHostIntStatus +#else +#define MAP_SDHostIntStatus \ + SDHostIntStatus +#endif +#ifdef ROM_SDHostIntClear +#define MAP_SDHostIntClear \ + ROM_SDHostIntClear +#else +#define MAP_SDHostIntClear \ + SDHostIntClear +#endif +#ifdef ROM_SDHostRespGet +#define MAP_SDHostRespGet \ + ROM_SDHostRespGet +#else +#define MAP_SDHostRespGet \ + SDHostRespGet +#endif +#ifdef ROM_SDHostBlockSizeSet +#define MAP_SDHostBlockSizeSet \ + ROM_SDHostBlockSizeSet +#else +#define MAP_SDHostBlockSizeSet \ + SDHostBlockSizeSet +#endif +#ifdef ROM_SDHostBlockCountSet +#define MAP_SDHostBlockCountSet \ + ROM_SDHostBlockCountSet +#else +#define MAP_SDHostBlockCountSet \ + SDHostBlockCountSet +#endif +#ifdef ROM_SDHostDataNonBlockingWrite +#define MAP_SDHostDataNonBlockingWrite \ + ROM_SDHostDataNonBlockingWrite +#else +#define MAP_SDHostDataNonBlockingWrite \ + SDHostDataNonBlockingWrite +#endif +#ifdef ROM_SDHostDataNonBlockingRead +#define MAP_SDHostDataNonBlockingRead \ + ROM_SDHostDataNonBlockingRead +#else +#define MAP_SDHostDataNonBlockingRead \ + SDHostDataNonBlockingRead +#endif +#ifdef ROM_SDHostDataWrite +#define MAP_SDHostDataWrite \ + ROM_SDHostDataWrite +#else +#define MAP_SDHostDataWrite \ + SDHostDataWrite +#endif +#ifdef ROM_SDHostDataRead +#define MAP_SDHostDataRead \ + ROM_SDHostDataRead +#else +#define MAP_SDHostDataRead \ + SDHostDataRead +#endif +#ifdef ROM_SDHostSetExpClk +#define MAP_SDHostSetExpClk \ + ROM_SDHostSetExpClk +#else +#define MAP_SDHostSetExpClk \ + SDHostSetExpClk +#endif +#ifdef ROM_SDHostCardErrorMaskSet +#define MAP_SDHostCardErrorMaskSet \ + ROM_SDHostCardErrorMaskSet +#else +#define MAP_SDHostCardErrorMaskSet \ + SDHostCardErrorMaskSet +#endif +#ifdef ROM_SDHostCardErrorMaskGet +#define MAP_SDHostCardErrorMaskGet \ + ROM_SDHostCardErrorMaskGet +#else +#define MAP_SDHostCardErrorMaskGet \ + SDHostCardErrorMaskGet +#endif + +//***************************************************************************** +// +// Macros for the PRCM API. +// +//***************************************************************************** +#ifdef ROM_PRCMMCUReset +#define MAP_PRCMMCUReset \ + ROM_PRCMMCUReset +#else +#define MAP_PRCMMCUReset \ + PRCMMCUReset +#endif +#ifdef ROM_PRCMSysResetCauseGet +#define MAP_PRCMSysResetCauseGet \ + ROM_PRCMSysResetCauseGet +#else +#define MAP_PRCMSysResetCauseGet \ + PRCMSysResetCauseGet +#endif +#ifdef ROM_PRCMPeripheralClkEnable +#define MAP_PRCMPeripheralClkEnable \ + ROM_PRCMPeripheralClkEnable +#else +#define MAP_PRCMPeripheralClkEnable \ + PRCMPeripheralClkEnable +#endif +#ifdef ROM_PRCMPeripheralClkDisable +#define MAP_PRCMPeripheralClkDisable \ + ROM_PRCMPeripheralClkDisable +#else +#define MAP_PRCMPeripheralClkDisable \ + PRCMPeripheralClkDisable +#endif +#ifdef ROM_PRCMPeripheralReset +#define MAP_PRCMPeripheralReset \ + ROM_PRCMPeripheralReset +#else +#define MAP_PRCMPeripheralReset \ + PRCMPeripheralReset +#endif +#ifdef ROM_PRCMPeripheralStatusGet +#define MAP_PRCMPeripheralStatusGet \ + ROM_PRCMPeripheralStatusGet +#else +#define MAP_PRCMPeripheralStatusGet \ + PRCMPeripheralStatusGet +#endif +#ifdef ROM_PRCMI2SClockFreqSet +#define MAP_PRCMI2SClockFreqSet \ + ROM_PRCMI2SClockFreqSet +#else +#define MAP_PRCMI2SClockFreqSet \ + PRCMI2SClockFreqSet +#endif +#ifdef ROM_PRCMPeripheralClockGet +#define MAP_PRCMPeripheralClockGet \ + ROM_PRCMPeripheralClockGet +#else +#define MAP_PRCMPeripheralClockGet \ + PRCMPeripheralClockGet +#endif +#ifdef ROM_PRCMSleepEnter +#define MAP_PRCMSleepEnter \ + ROM_PRCMSleepEnter +#else +#define MAP_PRCMSleepEnter \ + PRCMSleepEnter +#endif +#ifdef ROM_PRCMSRAMRetentionEnable +#define MAP_PRCMSRAMRetentionEnable \ + ROM_PRCMSRAMRetentionEnable +#else +#define MAP_PRCMSRAMRetentionEnable \ + PRCMSRAMRetentionEnable +#endif +#ifdef ROM_PRCMSRAMRetentionDisable +#define MAP_PRCMSRAMRetentionDisable \ + ROM_PRCMSRAMRetentionDisable +#else +#define MAP_PRCMSRAMRetentionDisable \ + PRCMSRAMRetentionDisable +#endif +#ifdef ROM_PRCMLPDSEnter +#define MAP_PRCMLPDSEnter \ + ROM_PRCMLPDSEnter +#else +#define MAP_PRCMLPDSEnter \ + PRCMLPDSEnter +#endif +#ifdef ROM_PRCMLPDSIntervalSet +#define MAP_PRCMLPDSIntervalSet \ + ROM_PRCMLPDSIntervalSet +#else +#define MAP_PRCMLPDSIntervalSet \ + PRCMLPDSIntervalSet +#endif +#ifdef ROM_PRCMLPDSWakeupSourceEnable +#define MAP_PRCMLPDSWakeupSourceEnable \ + ROM_PRCMLPDSWakeupSourceEnable +#else +#define MAP_PRCMLPDSWakeupSourceEnable \ + PRCMLPDSWakeupSourceEnable +#endif +#ifdef ROM_PRCMLPDSWakeupCauseGet +#define MAP_PRCMLPDSWakeupCauseGet \ + ROM_PRCMLPDSWakeupCauseGet +#else +#define MAP_PRCMLPDSWakeupCauseGet \ + PRCMLPDSWakeupCauseGet +#endif +#ifdef ROM_PRCMLPDSWakeUpGPIOSelect +#define MAP_PRCMLPDSWakeUpGPIOSelect \ + ROM_PRCMLPDSWakeUpGPIOSelect +#else +#define MAP_PRCMLPDSWakeUpGPIOSelect \ + PRCMLPDSWakeUpGPIOSelect +#endif +#ifdef ROM_PRCMLPDSWakeupSourceDisable +#define MAP_PRCMLPDSWakeupSourceDisable \ + ROM_PRCMLPDSWakeupSourceDisable +#else +#define MAP_PRCMLPDSWakeupSourceDisable \ + PRCMLPDSWakeupSourceDisable +#endif +#ifdef ROM_PRCMHibernateEnter +#define MAP_PRCMHibernateEnter \ + ROM_PRCMHibernateEnter +#else +#define MAP_PRCMHibernateEnter \ + PRCMHibernateEnter +#endif +#ifdef ROM_PRCMHibernateWakeupSourceEnable +#define MAP_PRCMHibernateWakeupSourceEnable \ + ROM_PRCMHibernateWakeupSourceEnable +#else +#define MAP_PRCMHibernateWakeupSourceEnable \ + PRCMHibernateWakeupSourceEnable +#endif +#ifdef ROM_PRCMHibernateWakeupCauseGet +#define MAP_PRCMHibernateWakeupCauseGet \ + ROM_PRCMHibernateWakeupCauseGet +#else +#define MAP_PRCMHibernateWakeupCauseGet \ + PRCMHibernateWakeupCauseGet +#endif +#ifdef ROM_PRCMHibernateWakeUpGPIOSelect +#define MAP_PRCMHibernateWakeUpGPIOSelect \ + ROM_PRCMHibernateWakeUpGPIOSelect +#else +#define MAP_PRCMHibernateWakeUpGPIOSelect \ + PRCMHibernateWakeUpGPIOSelect +#endif +#ifdef ROM_PRCMHibernateWakeupSourceDisable +#define MAP_PRCMHibernateWakeupSourceDisable \ + ROM_PRCMHibernateWakeupSourceDisable +#else +#define MAP_PRCMHibernateWakeupSourceDisable \ + PRCMHibernateWakeupSourceDisable +#endif +#ifdef ROM_PRCMHibernateIntervalSet +#define MAP_PRCMHibernateIntervalSet \ + ROM_PRCMHibernateIntervalSet +#else +#define MAP_PRCMHibernateIntervalSet \ + PRCMHibernateIntervalSet +#endif +#ifdef ROM_PRCMSlowClkCtrGet +#define MAP_PRCMSlowClkCtrGet \ + ROM_PRCMSlowClkCtrGet +#else +#define MAP_PRCMSlowClkCtrGet \ + PRCMSlowClkCtrGet +#endif +#ifdef ROM_PRCMSlowClkCtrMatchSet +#define MAP_PRCMSlowClkCtrMatchSet \ + ROM_PRCMSlowClkCtrMatchSet +#else +#define MAP_PRCMSlowClkCtrMatchSet \ + PRCMSlowClkCtrMatchSet +#endif +#ifdef ROM_PRCMSlowClkCtrMatchGet +#define MAP_PRCMSlowClkCtrMatchGet \ + ROM_PRCMSlowClkCtrMatchGet +#else +#define MAP_PRCMSlowClkCtrMatchGet \ + PRCMSlowClkCtrMatchGet +#endif +#ifdef ROM_PRCMOCRRegisterWrite +#define MAP_PRCMOCRRegisterWrite \ + ROM_PRCMOCRRegisterWrite +#else +#define MAP_PRCMOCRRegisterWrite \ + PRCMOCRRegisterWrite +#endif +#ifdef ROM_PRCMOCRRegisterRead +#define MAP_PRCMOCRRegisterRead \ + ROM_PRCMOCRRegisterRead +#else +#define MAP_PRCMOCRRegisterRead \ + PRCMOCRRegisterRead +#endif +#ifdef ROM_PRCMIntRegister +#define MAP_PRCMIntRegister \ + ROM_PRCMIntRegister +#else +#define MAP_PRCMIntRegister \ + PRCMIntRegister +#endif +#ifdef ROM_PRCMIntUnregister +#define MAP_PRCMIntUnregister \ + ROM_PRCMIntUnregister +#else +#define MAP_PRCMIntUnregister \ + PRCMIntUnregister +#endif +#ifdef ROM_PRCMIntEnable +#define MAP_PRCMIntEnable \ + ROM_PRCMIntEnable +#else +#define MAP_PRCMIntEnable \ + PRCMIntEnable +#endif +#ifdef ROM_PRCMIntDisable +#define MAP_PRCMIntDisable \ + ROM_PRCMIntDisable +#else +#define MAP_PRCMIntDisable \ + PRCMIntDisable +#endif +#ifdef ROM_PRCMIntStatus +#define MAP_PRCMIntStatus \ + ROM_PRCMIntStatus +#else +#define MAP_PRCMIntStatus \ + PRCMIntStatus +#endif +#ifdef ROM_PRCMRTCInUseSet +#define MAP_PRCMRTCInUseSet \ + ROM_PRCMRTCInUseSet +#else +#define MAP_PRCMRTCInUseSet \ + PRCMRTCInUseSet +#endif +#ifdef ROM_PRCMRTCInUseGet +#define MAP_PRCMRTCInUseGet \ + ROM_PRCMRTCInUseGet +#else +#define MAP_PRCMRTCInUseGet \ + PRCMRTCInUseGet +#endif +#ifdef ROM_PRCMRTCSet +#define MAP_PRCMRTCSet \ + ROM_PRCMRTCSet +#else +#define MAP_PRCMRTCSet \ + PRCMRTCSet +#endif +#ifdef ROM_PRCMRTCGet +#define MAP_PRCMRTCGet \ + ROM_PRCMRTCGet +#else +#define MAP_PRCMRTCGet \ + PRCMRTCGet +#endif +#ifdef ROM_PRCMRTCMatchSet +#define MAP_PRCMRTCMatchSet \ + ROM_PRCMRTCMatchSet +#else +#define MAP_PRCMRTCMatchSet \ + PRCMRTCMatchSet +#endif +#ifdef ROM_PRCMRTCMatchGet +#define MAP_PRCMRTCMatchGet \ + ROM_PRCMRTCMatchGet +#else +#define MAP_PRCMRTCMatchGet \ + PRCMRTCMatchGet +#endif +#ifdef ROM_PRCMLPDSRestoreInfoSet +#define MAP_PRCMLPDSRestoreInfoSet \ + ROM_PRCMLPDSRestoreInfoSet +#else +#define MAP_PRCMLPDSRestoreInfoSet \ + PRCMLPDSRestoreInfoSet +#endif +#ifdef ROM_PRCMSlowClkCtrFastGet +#define MAP_PRCMSlowClkCtrFastGet \ + ROM_PRCMSlowClkCtrFastGet +#else +#define MAP_PRCMSlowClkCtrFastGet \ + PRCMSlowClkCtrFastGet +#endif +#ifdef ROM_PRCMCC3200MCUInit +#define MAP_PRCMCC3200MCUInit \ + ROM_PRCMCC3200MCUInit +#else +#define MAP_PRCMCC3200MCUInit \ + PRCMCC3200MCUInit +#endif +#ifdef ROM_PRCMHIBRegRead +#define MAP_PRCMHIBRegRead \ + ROM_PRCMHIBRegRead +#else +#define MAP_PRCMHIBRegRead \ + PRCMHIBRegRead +#endif +#ifdef ROM_PRCMHIBRegWrite +#define MAP_PRCMHIBRegWrite \ + ROM_PRCMHIBRegWrite +#else +#define MAP_PRCMHIBRegWrite \ + PRCMHIBRegWrite +#endif +#ifdef ROM_PRCMCameraFreqSet +#define MAP_PRCMCameraFreqSet \ + ROM_PRCMCameraFreqSet +#else +#define MAP_PRCMCameraFreqSet \ + PRCMCameraFreqSet +#endif +#ifdef ROM_PRCMIORetentionEnable +#define MAP_PRCMIORetentionEnable \ + ROM_PRCMIORetentionEnable +#else +#define MAP_PRCMIORetentionEnable \ + PRCMIORetentionEnable +#endif +#ifdef ROM_PRCMIORetentionDisable +#define MAP_PRCMIORetentionDisable \ + ROM_PRCMIORetentionDisable +#else +#define MAP_PRCMIORetentionDisable \ + PRCMIORetentionDisable +#endif +#ifdef ROM_PRCMDeviceTypeGet +#define MAP_PRCMDeviceTypeGet \ + ROM_PRCMDeviceTypeGet +#else +#define MAP_PRCMDeviceTypeGet \ + PRCMDeviceTypeGet +#endif +#ifdef ROM_PRCMLPDSEnterKeepDebugIf +#define MAP_PRCMLPDSEnterKeepDebugIf \ + ROM_PRCMLPDSEnterKeepDebugIf +#else +#define MAP_PRCMLPDSEnterKeepDebugIf \ + PRCMLPDSEnterKeepDebugIf +#endif +#ifdef ROM_PRCMHibernateCycleTrigger +#define MAP_PRCMHibernateCycleTrigger \ + ROM_PRCMHibernateCycleTrigger +#else +#define MAP_PRCMHibernateCycleTrigger \ + PRCMHibernateCycleTrigger +#endif + +//***************************************************************************** +// +// Macros for the HWSPINLOCK API. +// +//***************************************************************************** +#ifdef ROM_HwSpinLockAcquire +#define MAP_HwSpinLockAcquire \ + ROM_HwSpinLockAcquire +#else +#define MAP_HwSpinLockAcquire \ + HwSpinLockAcquire +#endif +#ifdef ROM_HwSpinLockTryAcquire +#define MAP_HwSpinLockTryAcquire \ + ROM_HwSpinLockTryAcquire +#else +#define MAP_HwSpinLockTryAcquire \ + HwSpinLockTryAcquire +#endif +#ifdef ROM_HwSpinLockRelease +#define MAP_HwSpinLockRelease \ + ROM_HwSpinLockRelease +#else +#define MAP_HwSpinLockRelease \ + HwSpinLockRelease +#endif +#ifdef ROM_HwSpinLockTest +#define MAP_HwSpinLockTest \ + ROM_HwSpinLockTest +#else +#define MAP_HwSpinLockTest \ + HwSpinLockTest +#endif + +//***************************************************************************** +// +// Macros for the ADC API. +// +//***************************************************************************** +#ifdef ROM_ADCEnable +#define MAP_ADCEnable \ + ROM_ADCEnable +#else +#define MAP_ADCEnable \ + ADCEnable +#endif +#ifdef ROM_ADCDisable +#define MAP_ADCDisable \ + ROM_ADCDisable +#else +#define MAP_ADCDisable \ + ADCDisable +#endif +#ifdef ROM_ADCChannelEnable +#define MAP_ADCChannelEnable \ + ROM_ADCChannelEnable +#else +#define MAP_ADCChannelEnable \ + ADCChannelEnable +#endif +#ifdef ROM_ADCChannelDisable +#define MAP_ADCChannelDisable \ + ROM_ADCChannelDisable +#else +#define MAP_ADCChannelDisable \ + ADCChannelDisable +#endif +#ifdef ROM_ADCIntRegister +#define MAP_ADCIntRegister \ + ROM_ADCIntRegister +#else +#define MAP_ADCIntRegister \ + ADCIntRegister +#endif +#ifdef ROM_ADCIntUnregister +#define MAP_ADCIntUnregister \ + ROM_ADCIntUnregister +#else +#define MAP_ADCIntUnregister \ + ADCIntUnregister +#endif +#ifdef ROM_ADCIntEnable +#define MAP_ADCIntEnable \ + ROM_ADCIntEnable +#else +#define MAP_ADCIntEnable \ + ADCIntEnable +#endif +#ifdef ROM_ADCIntDisable +#define MAP_ADCIntDisable \ + ROM_ADCIntDisable +#else +#define MAP_ADCIntDisable \ + ADCIntDisable +#endif +#ifdef ROM_ADCIntStatus +#define MAP_ADCIntStatus \ + ROM_ADCIntStatus +#else +#define MAP_ADCIntStatus \ + ADCIntStatus +#endif +#ifdef ROM_ADCIntClear +#define MAP_ADCIntClear \ + ROM_ADCIntClear +#else +#define MAP_ADCIntClear \ + ADCIntClear +#endif +#ifdef ROM_ADCDMAEnable +#define MAP_ADCDMAEnable \ + ROM_ADCDMAEnable +#else +#define MAP_ADCDMAEnable \ + ADCDMAEnable +#endif +#ifdef ROM_ADCDMADisable +#define MAP_ADCDMADisable \ + ROM_ADCDMADisable +#else +#define MAP_ADCDMADisable \ + ADCDMADisable +#endif +#ifdef ROM_ADCTimerConfig +#define MAP_ADCTimerConfig \ + ROM_ADCTimerConfig +#else +#define MAP_ADCTimerConfig \ + ADCTimerConfig +#endif +#ifdef ROM_ADCTimerEnable +#define MAP_ADCTimerEnable \ + ROM_ADCTimerEnable +#else +#define MAP_ADCTimerEnable \ + ADCTimerEnable +#endif +#ifdef ROM_ADCTimerDisable +#define MAP_ADCTimerDisable \ + ROM_ADCTimerDisable +#else +#define MAP_ADCTimerDisable \ + ADCTimerDisable +#endif +#ifdef ROM_ADCTimerReset +#define MAP_ADCTimerReset \ + ROM_ADCTimerReset +#else +#define MAP_ADCTimerReset \ + ADCTimerReset +#endif +#ifdef ROM_ADCTimerValueGet +#define MAP_ADCTimerValueGet \ + ROM_ADCTimerValueGet +#else +#define MAP_ADCTimerValueGet \ + ADCTimerValueGet +#endif +#ifdef ROM_ADCFIFOLvlGet +#define MAP_ADCFIFOLvlGet \ + ROM_ADCFIFOLvlGet +#else +#define MAP_ADCFIFOLvlGet \ + ADCFIFOLvlGet +#endif +#ifdef ROM_ADCFIFORead +#define MAP_ADCFIFORead \ + ROM_ADCFIFORead +#else +#define MAP_ADCFIFORead \ + ADCFIFORead +#endif + +//***************************************************************************** +// +// Macros for the CPU API. +// +//***************************************************************************** +#ifdef ROM_CPUcpsid +#define MAP_CPUcpsid \ + ROM_CPUcpsid +#else +#define MAP_CPUcpsid \ + CPUcpsid +#endif +#ifdef ROM_CPUcpsie +#define MAP_CPUcpsie \ + ROM_CPUcpsie +#else +#define MAP_CPUcpsie \ + CPUcpsie +#endif +#ifdef ROM_CPUprimask +#define MAP_CPUprimask \ + ROM_CPUprimask +#else +#define MAP_CPUprimask \ + CPUprimask +#endif +#ifdef ROM_CPUwfi +#define MAP_CPUwfi \ + ROM_CPUwfi +#else +#define MAP_CPUwfi \ + CPUwfi +#endif +#ifdef ROM_CPUbasepriGet +#define MAP_CPUbasepriGet \ + ROM_CPUbasepriGet +#else +#define MAP_CPUbasepriGet \ + CPUbasepriGet +#endif +#ifdef ROM_CPUbasepriSet +#define MAP_CPUbasepriSet \ + ROM_CPUbasepriSet +#else +#define MAP_CPUbasepriSet \ + CPUbasepriSet +#endif + +#endif // __ROM_MAP_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom_patch.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom_patch.h new file mode 100644 index 000000000..b15f73cc0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/rom_patch.h @@ -0,0 +1,115 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// rom_patch.h - Macros to facilitate patching driverlib API's in the ROM. +// +// + +//***************************************************************************** +// +// List of API's in the ROM that need to be patched. +// For e.g. to patch ROM_UARTCharPut add the line #undef ROM_UARTCharPut +//***************************************************************************** + +#ifndef __ROM_PATCH_H__ +#define __ROM_PATCH_H__ + +#if defined(TARGET_IS_CC3200) || defined(USE_CC3200_ROM_DRV_API) +#undef ROM_ADCIntClear +#undef ROM_IntEnable +#undef ROM_IntDisable +#undef ROM_IntPendSet +#undef ROM_SDHostCardErrorMaskSet +#undef ROM_SDHostCardErrorMaskGet +#undef ROM_TimerConfigure +#undef ROM_TimerDMAEventSet +#undef ROM_TimerDMAEventGet +#undef ROM_SDHostDataNonBlockingWrite +#undef ROM_SDHostDataWrite +#undef ROM_SDHostDataRead +#undef ROM_SDHostDataNonBlockingRead +#undef ROM_PRCMSysResetCauseGet +#undef ROM_PRCMPeripheralClkEnable +#undef ROM_PRCMLPDSWakeUpGPIOSelect +#undef ROM_PRCMHibernateWakeupSourceEnable +#undef ROM_PRCMHibernateWakeupSourceDisable +#undef ROM_PRCMHibernateWakeupCauseGet +#undef ROM_PRCMHibernateIntervalSet +#undef ROM_PRCMHibernateWakeUpGPIOSelect +#undef ROM_PRCMHibernateEnter +#undef ROM_PRCMSlowClkCtrGet +#undef ROM_PRCMSlowClkCtrMatchSet +#undef ROM_PRCMSlowClkCtrMatchGet +#undef ROM_PRCMOCRRegisterWrite +#undef ROM_PRCMOCRRegisterRead +#undef ROM_PRCMIntEnable +#undef ROM_PRCMIntDisable +#undef ROM_PRCMRTCInUseSet +#undef ROM_PRCMRTCInUseGet +#undef ROM_PRCMRTCSet +#undef ROM_PRCMRTCGet +#undef ROM_PRCMRTCMatchSet +#undef ROM_PRCMRTCMatchGet +#undef ROM_PRCMPeripheralClkDisable +#undef ROM_PRCMPeripheralReset +#undef ROM_PRCMPeripheralStatusGet +#undef ROM_SPIConfigSetExpClk +#undef ROM_AESDataProcess +#undef ROM_DESDataProcess +#undef ROM_I2SEnable +#undef ROM_I2SConfigSetExpClk +#undef ROM_PinConfigSet +#undef ROM_PRCMLPDSEnter +#undef ROM_PRCMCC3200MCUInit +#undef ROM_SDHostIntStatus +#undef ROM_SDHostBlockCountSet +#undef ROM_UARTModemControlSet +#undef ROM_UARTModemControlClear +#undef ROM_CameraXClkSet +#undef ROM_PRCMMCUReset +#undef ROM_PRCMPeripheralClkEnable +#undef ROM_SPIDmaDisable +#endif + +#if defined(USE_CC3220_ROM_DRV_API) +#undef ROM_PRCMDeviceTypeGet +#undef ROM_SDHostDataNonBlockingRead +#undef ROM_PRCMCC3200MCUInit +#endif + +#endif // __ROM_PATCH_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/sdhost.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/sdhost.h new file mode 100644 index 000000000..cb5851807 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/sdhost.h @@ -0,0 +1,209 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// sdhost.h +// +// Defines and Macros for the SDHost. +// +//***************************************************************************** + +#ifndef __SDHOST_H__ +#define __SDHOST_H__ + + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +//{ +#endif + + +//***************************************************************************** +// Values that can be passed to SDHostRespGet(). +//***************************************************************************** +#define SDHOST_RESP_10 0x00000003 +#define SDHOST_RESP_32 0x00000002 +#define SDHOST_RESP_54 0x00000001 +#define SDHOST_RESP_76 0x00000000 + + +//***************************************************************************** +// Values that can be passed to SDHostIntEnable(), SDHostIntDisable(), +// SDHostIntClear() ,and returned from SDHostIntStatus(). +//***************************************************************************** +#define SDHOST_INT_CC 0x00000001 +#define SDHOST_INT_TC 0x00000002 +#define SDHOST_INT_BWR 0x00000010 +#define SDHOST_INT_BRR 0x00000020 +#define SDHOST_INT_ERRI 0x00008000 +#define SDHOST_INT_CTO 0x00010000 +#define SDHOST_INT_CEB 0x00040000 +#define SDHOST_INT_DTO 0x00100000 +#define SDHOST_INT_DCRC 0x00200000 +#define SDHOST_INT_DEB 0x00400000 +#define SDHOST_INT_CERR 0x10000000 +#define SDHOST_INT_BADA 0x20000000 +#define SDHOST_INT_DMARD 0x40000000 +#define SDHOST_INT_DMAWR 0x80000000 + +//***************************************************************************** +// Values that can be passed to SDHostCmdSend(). +//***************************************************************************** +#define SDHOST_CMD_0 0x00000000 +#define SDHOST_CMD_1 0x01000000 +#define SDHOST_CMD_2 0x02000000 +#define SDHOST_CMD_3 0x03000000 +#define SDHOST_CMD_4 0x04000000 +#define SDHOST_CMD_5 0x05000000 +#define SDHOST_CMD_6 0x06000000 +#define SDHOST_CMD_7 0x07000000 +#define SDHOST_CMD_8 0x08000000 +#define SDHOST_CMD_9 0x09000000 +#define SDHOST_CMD_10 0x0A000000 +#define SDHOST_CMD_11 0x0B000000 +#define SDHOST_CMD_12 0x0C000000 +#define SDHOST_CMD_13 0x0D000000 +#define SDHOST_CMD_14 0x0E000000 +#define SDHOST_CMD_15 0x0F000000 +#define SDHOST_CMD_16 0x10000000 +#define SDHOST_CMD_17 0x11000000 +#define SDHOST_CMD_18 0x12000000 +#define SDHOST_CMD_19 0x13000000 +#define SDHOST_CMD_20 0x14000000 +#define SDHOST_CMD_21 0x15000000 +#define SDHOST_CMD_22 0x16000000 +#define SDHOST_CMD_23 0x17000000 +#define SDHOST_CMD_24 0x18000000 +#define SDHOST_CMD_25 0x19000000 +#define SDHOST_CMD_26 0x1A000000 +#define SDHOST_CMD_27 0x1B000000 +#define SDHOST_CMD_28 0x1C000000 +#define SDHOST_CMD_29 0x1D000000 +#define SDHOST_CMD_30 0x1E000000 +#define SDHOST_CMD_31 0x1F000000 +#define SDHOST_CMD_32 0x20000000 +#define SDHOST_CMD_33 0x21000000 +#define SDHOST_CMD_34 0x22000000 +#define SDHOST_CMD_35 0x23000000 +#define SDHOST_CMD_36 0x24000000 +#define SDHOST_CMD_37 0x25000000 +#define SDHOST_CMD_38 0x26000000 +#define SDHOST_CMD_39 0x27000000 +#define SDHOST_CMD_40 0x28000000 +#define SDHOST_CMD_41 0x29000000 +#define SDHOST_CMD_42 0x2A000000 +#define SDHOST_CMD_43 0x2B000000 +#define SDHOST_CMD_44 0x2C000000 +#define SDHOST_CMD_45 0x2D000000 +#define SDHOST_CMD_46 0x2E000000 +#define SDHOST_CMD_47 0x2F000000 +#define SDHOST_CMD_48 0x30000000 +#define SDHOST_CMD_49 0x31000000 +#define SDHOST_CMD_50 0x32000000 +#define SDHOST_CMD_51 0x33000000 +#define SDHOST_CMD_52 0x34000000 +#define SDHOST_CMD_53 0x35000000 +#define SDHOST_CMD_54 0x36000000 +#define SDHOST_CMD_55 0x37000000 +#define SDHOST_CMD_56 0x38000000 +#define SDHOST_CMD_57 0x39000000 +#define SDHOST_CMD_58 0x3A000000 +#define SDHOST_CMD_59 0x3B000000 +#define SDHOST_CMD_60 0x3C000000 +#define SDHOST_CMD_61 0x3D000000 +#define SDHOST_CMD_62 0x3E000000 +#define SDHOST_CMD_63 0x3F000000 + +//***************************************************************************** +// Values that can be logically ORed with ulCmd parameter for SDHostCmdSend(). +//***************************************************************************** +#define SDHOST_MULTI_BLK 0x00000022 +#define SDHOST_DMA_EN 0x00000001 +#define SDHOST_WR_CMD 0x00200000 +#define SDHOST_RD_CMD 0x00200010 +#define SDHOST_RESP_LEN_136 0x00010000 +#define SDHOST_RESP_LEN_48 0x00020000 +#define SDHOST_RESP_LEN_48B 0x00030000 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void SDHostCmdReset(unsigned long ulBase); +extern void SDHostInit(unsigned long ulBase); +extern long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd, + unsigned ulArg); +extern void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void SDHostIntUnregister(unsigned long ulBase); +extern void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags); +extern void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags); +extern unsigned long SDHostIntStatus(unsigned long ulBase); +extern void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags); +extern void SDHostCardErrorMaskSet(unsigned long ulBase, + unsigned long ulErrMask); +extern unsigned long SDHostCardErrorMaskGet(unsigned long ulBase); +extern void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk, + unsigned long ulCardClk); +extern void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]); +extern void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize); +extern void SDHostBlockCountSet(unsigned long ulBase, + unsigned short ulBlkCount); +extern tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase, + unsigned long ulData); +extern tBoolean SDHostDataNonBlockingRead(unsigned long ulBase, + unsigned long *pulData); +extern void SDHostDataWrite(unsigned long ulBase, unsigned long ulData); +extern void SDHostDataRead(unsigned long ulBase, unsigned long *ulData); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +//} +#endif + +#endif // __SDHOST_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/shamd5.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/shamd5.h new file mode 100644 index 000000000..628737916 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/shamd5.h @@ -0,0 +1,125 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// shamd5.h +// +// Defines and Macros for the SHA/MD5. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SHAMD5_H__ +#define __DRIVERLIB_SHAMD5_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used to specify the algorithm in use in the +// SHA/MD5 module. +// +//***************************************************************************** +#define SHAMD5_ALGO_MD5 0x00000018 // MD5 +#define SHAMD5_ALGO_SHA1 0x0000001a // SHA-1 +#define SHAMD5_ALGO_SHA224 0x0000001c // SHA-224 +#define SHAMD5_ALGO_SHA256 0x0000001e // SHA-256 +#define SHAMD5_ALGO_HMAC_MD5 0x00000000 // HMAC-MD5 +#define SHAMD5_ALGO_HMAC_SHA1 0x00000002 // HMAC-SHA-1 +#define SHAMD5_ALGO_HMAC_SHA224 0x00000004 // HMAC-SHA-224 +#define SHAMD5_ALGO_HMAC_SHA256 0x00000006 // HMAC-SHA-256 + +//***************************************************************************** +// +// The following defines are used to represent the different interrupt sources +// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and +// SHAMD5BlockOnIntStatus() functions. +// +//***************************************************************************** +#define SHAMD5_INT_CONTEXT_READY 0x00000008 +#define SHAMD5_INT_PARTHASH_READY 0x00000004 +#define SHAMD5_INT_INPUT_READY 0x00000002 +#define SHAMD5_INT_OUTPUT_READY 0x00000001 +#define SHAMD5_INT_DMA_CONTEXT_IN 0x00010000 +#define SHAMD5_INT_DMA_DATA_IN 0x00020000 +#define SHAMD5_INT_DMA_CONTEXT_OUT 0x00040000 + +//***************************************************************************** +// +// Function prototypes +// +//***************************************************************************** +extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode); +extern bool SHAMD5DataProcess(uint32_t ui32Base, uint8_t *pui8DataSrc, + uint32_t ui32DataLength, uint8_t *pui8HashResult); +extern void SHAMD5DataWrite(uint32_t ui32Base, uint8_t *pui8Src); +extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src); +extern void SHAMD5DMADisable(uint32_t ui32Base); +extern void SHAMD5DMAEnable(uint32_t ui32Base); +extern void SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length); +extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint8_t *pui8Src); +extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint8_t *pui8Key, + uint8_t *pui8PPKey); +extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint8_t *pui8Src); +extern bool SHAMD5HMACProcess(uint32_t ui32Base, uint8_t *pui8DataSrc, + uint32_t ui32DataLength, uint8_t *pui8HashResult); +extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked); +extern void SHAMD5IntUnregister(uint32_t ui32Base); +extern void SHAMD5ResultRead(uint32_t ui32Base, uint8_t *pui8Dest); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SHAMD5_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/spi.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/spi.c new file mode 100644 index 000000000..06f403c88 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/spi.c @@ -0,0 +1,1532 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// spi.c +// +// Driver for the SPI. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup SPI_Serial_Peripheral_Interface_api +//! @{ +// +//***************************************************************************** + + +#include "inc/hw_ints.h" +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_mcspi.h" +#include "inc/hw_apps_config.h" +#include "interrupt.h" +#include "spi.h" + + +//***************************************************************************** +// +// A mapping of SPI base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulSPIIntMap[][3] = +{ + { SSPI_BASE, INT_SSPI }, // Shared SPI + { GSPI_BASE, INT_GSPI }, // Generic SPI + { LSPI_BASE, INT_LSPI }, // LINK SPI +}; + +//***************************************************************************** +// +// A mapping of SPI base address to DMA done interrupt mask bit(s). +// +//***************************************************************************** +static const unsigned long g_ulSPIDmaMaskMap[][2]= +{ + {SSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK}, + {LSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK}, + {GSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK}, +}; + +//***************************************************************************** +// +//! \internal +//! Transfer bytes over SPI channel +//! +//! \param ulBase is the base address of SPI module +//! \param ucDout is the pointer to Tx data buffer or 0. +//! \param ucDin is pointer to Rx data buffer or 0 +//! \param ulCount is the size of data in bytes. +//! +//! This function transfers \e ulCount bytes of data over SPI channel. +//! +//! The function will not return until data has been transmitted +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout, + unsigned char *ucDin, unsigned long ulCount, + unsigned long ulFlags) +{ + unsigned long ulReadReg; + unsigned long ulWriteReg; + unsigned long ulStatReg; + unsigned long ulOutIncr; + unsigned long ulInIncr; + unsigned long ulTxDummy; + unsigned long ulRxDummy; + + // + // Initialize the variables + // + ulOutIncr = 1; + ulInIncr = 1; + + // + // Check if output buffer pointer is 0 + // + if(ucDout == 0) + { + ulOutIncr = 0; + ulTxDummy = 0xFFFFFFFF; + ucDout = (unsigned char *)&ulTxDummy; + } + + // + // Check if input buffer pointer is 0 + // + if(ucDin == 0) + { + ulInIncr = 0; + ucDin = (unsigned char *)&ulRxDummy; + } + + // + // Load the register addresses. + // + ulReadReg = (ulBase + MCSPI_O_RX0); + ulWriteReg = (ulBase + MCSPI_O_TX0); + ulStatReg = (ulBase + MCSPI_O_CH0STAT); + + // + // Enable CS based on Flag + // + if( ulFlags & SPI_CS_ENABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; + } + + while(ulCount) + { + // + // Wait for space in output register/FIFO. + // + while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) + { + } + + // + // Write the data + // + HWREG(ulWriteReg) = *ucDout; + + // + // Wait for data in input register/FIFO. + // + while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) + { + } + + // + // Read the data + // + *ucDin = HWREG(ulReadReg); + + // + // Increment pointers. + // + ucDout = ucDout + ulOutIncr; + ucDin = ucDin + ulInIncr; + + // + // Decrement the count. + // + ulCount--; + } + + // + // Disable CS based on Flag + // + if( ulFlags & SPI_CS_DISABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; + } + + return 0; +} + +//***************************************************************************** +// +//! \internal +//! Transfer half-words over SPI channel +//! +//! \param ulBase is the base address of SPI module +//! \param usDout is the pointer to Tx data buffer or 0. +//! \param usDin is pointer to Rx data buffer or 0 +//! \param ulCount is the size of data in bytes. +//! +//! This function transfers \e ulCount bytes of data over SPI channel. Since +//! the API sends a half-word at a time \e ulCount should be a multiple +//! of two. +//! +//! The function will not return until data has been transmitted +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +static long SPITransfer16(unsigned long ulBase, unsigned short *usDout, + unsigned short *usDin, unsigned long ulCount, + unsigned long ulFlags) +{ + unsigned long ulReadReg; + unsigned long ulWriteReg; + unsigned long ulStatReg; + unsigned long ulOutIncr; + unsigned long ulInIncr; + unsigned long ulTxDummy; + unsigned long ulRxDummy; + + // + // Initialize the variables. + // + ulOutIncr = 1; + ulInIncr = 1; + + // + // Check if count is multiple of half-word + // + if(ulCount%2) + { + return -1; + } + + // + // Compute number of half words. + // + ulCount = ulCount/2; + + // + // Check if output buffer pointer is 0 + // + if(usDout == 0) + { + ulOutIncr = 0; + ulTxDummy = 0xFFFFFFFF; + usDout = (unsigned short *)&ulTxDummy; + } + + // + // Check if input buffer pointer is 0 + // + if(usDin == 0) + { + ulInIncr = 0; + usDin = (unsigned short *)&ulRxDummy; + } + + // + // Load the register addresses. + // + ulReadReg = (ulBase + MCSPI_O_RX0); + ulWriteReg = (ulBase + MCSPI_O_TX0); + ulStatReg = (ulBase + MCSPI_O_CH0STAT); + + // + // Enable CS based on Flag + // + if( ulFlags & SPI_CS_ENABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; + } + + while(ulCount) + { + // + // Wait for space in output register/FIFO. + // + while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) + { + } + + // + // Write the data + // + HWREG(ulWriteReg) = *usDout; + + // + // Wait for data in input register/FIFO. + // + while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) + { + } + + // + // Read the data + // + *usDin = HWREG(ulReadReg); + + // + // Increment pointers. + // + usDout = usDout + ulOutIncr; + usDin = usDin + ulInIncr; + + // + // Decrement the count. + // + ulCount--; + } + + // + // Disable CS based on Flag + // + if( ulFlags & SPI_CS_DISABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; + } + + return 0; +} + +//***************************************************************************** +// +//! \internal +//! Transfer words over SPI channel +//! +//! \param ulBase is the base address of SPI module +//! \param ulDout is the pointer to Tx data buffer or 0. +//! \param ulDin is pointer to Rx data buffer or 0 +//! \param ulCount is the size of data in bytes. +//! +//! This function transfers \e ulCount bytes of data over SPI channel. Since +//! the API sends a word at a time \e ulCount should be a multiple of four. +//! +//! The function will not return until data has been transmitted +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout, + unsigned long *ulDin, unsigned long ulCount, + unsigned long ulFlags) +{ + unsigned long ulReadReg; + unsigned long ulWriteReg; + unsigned long ulStatReg; + unsigned long ulOutIncr; + unsigned long ulInIncr; + unsigned long ulTxDummy; + unsigned long ulRxDummy; + + // + // Initialize the variables. + // + ulOutIncr = 1; + ulInIncr = 1; + + // + // Check if count is multiple of word + // + if(ulCount%4) + { + return -1; + } + + // + // Compute the number of words to be transferd + // + ulCount = ulCount/4; + + // + // Check if output buffer pointer is 0 + // + if(ulDout == 0) + { + ulOutIncr = 0; + ulTxDummy = 0xFFFFFFFF; + ulDout = &ulTxDummy; + } + + // + // Check if input buffer pointer is 0 + // + if(ulDin == 0) + { + ulInIncr = 0; + ulDin = &ulRxDummy; + } + + + // + // Load the register addresses. + // + ulReadReg = (ulBase + MCSPI_O_RX0); + ulWriteReg = (ulBase + MCSPI_O_TX0); + ulStatReg = (ulBase + MCSPI_O_CH0STAT); + + // + // Enable CS based on Flag + // + if( ulFlags & SPI_CS_ENABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; + } + + while(ulCount) + { + // + // Wait for space in output register/FIFO. + // + while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) + { + } + + // + // Write the data + // + HWREG(ulWriteReg) = *ulDout; + + // + // Wait for data in input register/FIFO. + // + while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) + { + } + + // + // Read the data + // + *ulDin = HWREG(ulReadReg); + + // + // Increment pointers. + // + ulDout = ulDout + ulOutIncr; + ulDin = ulDin + ulInIncr; + + // + // Decrement the count. + // + ulCount--; + } + + // + // Disable CS based on Flag + // + if( ulFlags & SPI_CS_DISABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; + } + + return 0; +} + +//***************************************************************************** +// +//! \internal +//! Gets the SPI interrupt number. +//! +//! \param ulBase is the base address of the SPI module +//! +//! Given a SPI base address, returns the corresponding interrupt number. +//! +//! \return Returns a SPI interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +SPIIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps SPI base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulSPIIntMap) / + sizeof(g_ppulSPIIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulSPIIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulSPIIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + +//***************************************************************************** +// +//! \internal +//! Gets the SPI DMA interrupt mask bit. +//! +//! \param ulBase is the base address of the SPI module +//! +//! Given a SPI base address, DMA interrupt mask bit. +//! +//! \return Returns a DMA interrupt mask bit, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +SPIDmaMaskGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps SPI base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ulSPIDmaMaskMap) / + sizeof(g_ulSPIDmaMaskMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ulSPIDmaMaskMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ulSPIDmaMaskMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ulBase is the base address of the SPI module +//! +//! This function enables the SPI channel for transmitting and receiving. +//! +//! \return None +//! +// +//***************************************************************************** +void +SPIEnable(unsigned long ulBase) +{ + // + // Set Channel Enable Bit + // + HWREG(ulBase + MCSPI_O_CH0CTRL) |= MCSPI_CH0CTRL_EN; +} + +//***************************************************************************** +// +//! Disables the transmitting and receiving. +//! +//! \param ulBase is the base address of the SPI module +//! +//! This function disables the SPI channel for transmitting and receiving. +//! +//! \return None +//! +// +//***************************************************************************** +void +SPIDisable(unsigned long ulBase) +{ + // + // Reset Channel Enable Bit + // + HWREG(ulBase + MCSPI_O_CH0CTRL) &= ~MCSPI_CH0CTRL_EN; +} + + +//***************************************************************************** +// +//! Enables the SPI DMA operation for transmitting and/or receving. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulFlags selectes the DMA signal for transmit and/or receive. +//! +//! This function enables transmit and/or receive DMA request based on the +//! \e ulFlags parameter. +//! +//! The parameter \e ulFlags is the logical OR of one or more of +//! the following : +//! - \b SPI_RX_DMA +//! - \b SPI_TX_DMA +//! +//! \return None. +// +//***************************************************************************** +void +SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Enable DMA based on ulFlags + // + HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags; +} + +//***************************************************************************** +// +//! Disables the SPI DMA operation for transmitting and/or receving. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulFlags selectes the DMA signal for transmit and/or receive. +//! +//! This function disables transmit and/or receive DMA request based on the +//! \e ulFlags parameter. +//! +//! The parameter \e ulFlags is the logical OR of one or more of +//! the following : +//! - \b SPI_RX_DMA +//! - \b SPI_TX_DMA +//! +//! \return None. +// +//***************************************************************************** +void +SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Disable DMA based on ulFlags + // + HWREG(ulBase + MCSPI_O_CH0CONF) &= ~ulFlags; +} + +//***************************************************************************** +// +//! Performs a software reset of the specified SPI module +//! +//! \param ulBase is the base address of the SPI module +//! +//! This function performs a software reset of the specified SPI module +//! +//! \return None. +// +//***************************************************************************** +void +SPIReset(unsigned long ulBase) +{ + + // + // Assert soft reset (auto clear) + // + HWREG(ulBase + MCSPI_O_SYSCONFIG) |= MCSPI_SYSCONFIG_SOFTRESET; + + // + // wait until reset is done + // + while(!(HWREG(ulBase + MCSPI_O_SYSSTATUS)& MCSPI_SYSSTATUS_RESETDONE)) + { + } +} + +//***************************************************************************** +// +//! Sets the configuration of a SPI module +//! +//! \param ulBase is the base address of the SPI module +//! \param ulSPIClk is the rate of clock supplied to the SPI module. +//! \param ulBitRate is the desired bit rate.(master mode) +//! \param ulMode is the mode of operation. +//! \param ulSubMode is one of the valid sub-modes. +//! \param ulConfig is logical OR of configuration paramaters. +//! +//! This function configures SPI port for operation in specified sub-mode and +//! required bit rated as specified by \e ulMode and \e ulBitRate parameters +//! respectively. +//! +//! The SPI module can operate in either master or slave mode. The parameter +//! \e ulMode can be one of the following +//! -\b SPI_MODE_MASTER +//! -\b SPI_MODE_SLAVE +//! +//! The SPI module supports 4 sub modes based on SPI clock polarity and phase. +//! +//! 
+//! Polarity Phase  Sub-Mode
+//!   0       0        0
+//!   0       1        1
+//!   1       0        2
+//!   1       1        3
+//!
+//! +//! Required sub mode can be select by setting \e ulSubMode parameter to one +//! of the following +//! - \b SPI_SUB_MODE_0 +//! - \b SPI_SUB_MODE_1 +//! - \b SPI_SUB_MODE_2 +//! - \b SPI_SUB_MODE_3 +//! +//! The parameter \e ulConfig is logical OR of five values: the word length, +//! active level for chip select, software or hardware controled chip select, +//! 3 or 4 pin mode and turbo mode. +//! mode. +//! +//! SPI support 8, 16 and 32 bit word lengths defined by:- +//! - \b SPI_WL_8 +//! - \b SPI_WL_16 +//! - \b SPI_WL_32 +//! +//! Active state of Chip[ Selece can be defined by:- +//! - \b SPI_CS_ACTIVELOW +//! - \b SPI_CS_ACTIVEHIGH +//! +//! SPI chip select can be configured to be controlled either by hardware or +//! software:- +//! - \b SPI_SW_CS +//! - \b SPI_HW_CS +//! +//! The module can work in 3 or 4 pin mode defined by:- +//! - \b SPI_3PIN_MODE +//! - \b SPI_4PIN_MODE +//! +//! Turbo mode can be set on or turned off using:- +//! - \b SPI_TURBO_MODE_ON +//! - \b SPI_TURBO_MODE_OFF +//! +//! \return None. +// +//***************************************************************************** +void +SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, + unsigned long ulBitRate, unsigned long ulMode, + unsigned long ulSubMode, unsigned long ulConfig) +{ + + unsigned long ulRegData; + unsigned long ulDivider; + + // + // Read MODULCTRL register + // + ulRegData = HWREG(ulBase + MCSPI_O_MODULCTRL); + + // + // Set Master mode with h/w chip select + // + ulRegData &= ~(MCSPI_MODULCTRL_MS | + MCSPI_MODULCTRL_SINGLE); + + // + // Enable software control Chip Select, Init delay + // and 3-pin mode + // + ulRegData |= (((ulConfig >> 24) | ulMode) & 0xFF); + + // + // Write the configuration + // + HWREG(ulBase + MCSPI_O_MODULCTRL) = ulRegData; + + // + // Set IS, DPE0, DPE1 based on master or slave mode + // + if(ulMode == SPI_MODE_MASTER) + { + ulRegData = 0x1 << 16; + } + else + { + ulRegData = 0x6 << 16; + } + + // + // Mask the configurations and set clock divider granularity + // to 1 cycle + // + ulRegData = (ulRegData & ~(MCSPI_CH0CONF_WL_M | + MCSPI_CH0CONF_EPOL | + MCSPI_CH0CONF_POL | + MCSPI_CH0CONF_PHA | + MCSPI_CH0CONF_TURBO ) | + MCSPI_CH0CONF_CLKG); + + // + // Get the divider value + // + ulDivider = ((ulSPIClk/ulBitRate) - 1); + + // + // The least significant four bits of the divider is used fo configure + // CLKD in MCSPI_CHCONF next eight least significant bits are used to + // configure the EXTCLK in MCSPI_CHCTRL + // + ulRegData |= ((ulDivider & 0x0000000F) << 2); + HWREG(ulBase + MCSPI_O_CH0CTRL) = ((ulDivider & 0x00000FF0) << 4); + + // + // Set the protocol, CS polarity, word length + // and turbo mode + // + ulRegData = ((ulRegData | + ulSubMode) | (ulConfig & 0x0008FFFF)); + + // + // Write back the CONF register + // + HWREG(ulBase + MCSPI_O_CH0CONF) = ulRegData; + +} + +//***************************************************************************** +// +//! Receives a word from the specified port. +//! +//! \param ulBase is the base address of the SPI module. +//! \param pulData is pointer to receive data variable. +//! +//! This function gets a SPI word from the receive FIFO for the specified +//! port. +//! +//! \return Returns the number of elements read from the receive FIFO. +// +//***************************************************************************** +long +SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) +{ + unsigned long ulRegVal; + + // + // Read register status register + // + ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT); + + // + // Check is data is available + // + if(ulRegVal & MCSPI_CH0STAT_RXS) + { + *pulData = HWREG(ulBase + MCSPI_O_RX0); + return(1); + } + + return(0); +} + +//***************************************************************************** +// +//! Waits for the word to be received on the specified port. +//! +//! \param ulBase is the base address of the SPI module. +//! \param pulData is pointer to receive data variable. +//! +//! This function gets a SPI word from the receive FIFO for the specified +//! port. If there is no word available, this function waits until a +//! word is received before returning. +//! +//! \return Returns the word read from the specified port, cast as an +//! \e unsigned long. +// +//***************************************************************************** +void +SPIDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Wait for Rx data + // + while(!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS)) + { + } + + // + // Read the value + // + *pulData = HWREG(ulBase + MCSPI_O_RX0); +} + +//***************************************************************************** +// +//! Transmits a word on the specified port. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulData is data to be transmitted. +//! +//! This function transmits a SPI word on the transmit FIFO for the specified +//! port. +//! +//! \return Returns the number of elements written to the transmit FIFO. +//! +//***************************************************************************** +long +SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) +{ + unsigned long ulRegVal; + + // + // Read status register + // + ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT); + + // + // Write value into Tx register/FIFO + // if space is available + // + if(ulRegVal & MCSPI_CH0STAT_TXS) + { + HWREG(ulBase + MCSPI_O_TX0) = ulData; + return(1); + } + + return(0); +} + +//***************************************************************************** +// +//! Waits until the word is transmitted on the specified port. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulData is data to be transmitted. +//! +//! This function transmits a SPI word on the transmit FIFO for the specified +//! port. This function waits until the space is available on transmit FIFO +//! +//! \return None +//! +//***************************************************************************** +void +SPIDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Wait for space in FIFO + // + while(!(HWREG(ulBase + MCSPI_O_CH0STAT)&MCSPI_CH0STAT_TXS)) + { + } + + // + // Write the data + // + HWREG(ulBase + MCSPI_O_TX0) = ulData; +} + +//***************************************************************************** +// +//! Enables the transmit and/or receive FIFOs. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulFlags selects the FIFO(s) to be enabled +//! +//! This function enables the transmit and/or receive FIFOs as specified by +//! \e ulFlags. +//! The parameter \e ulFlags shoulde be logical OR of one or more of the +//! following: +//! - \b SPI_TX_FIFO +//! - \b SPI_RX_FIFO +//! +//! \return None. +// +//***************************************************************************** +void +SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Set FIFO enable bits. + // + HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags; +} + +//***************************************************************************** +// +//! Disables the transmit and/or receive FIFOs. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulFlags selects the FIFO(s) to be enabled +//! +//! This function disables transmit and/or receive FIFOs. as specified by +//! \e ulFlags. +//! The parameter \e ulFlags shoulde be logical OR of one or more of the +//! following: +//! - \b SPI_TX_FIFO +//! - \b SPI_RX_FIFO +//! +//! \return None. +// +//***************************************************************************** +void +SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Reset FIFO Enable bits. + // + HWREG(ulBase + MCSPI_O_CH0CONF) &= ~(ulFlags); +} + +//***************************************************************************** +// +//! Sets the FIFO level at which DMA requests or interrupts are generated. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulTxLevel is the Almost Empty Level for transmit FIFO. +//! \param ulRxLevel is the Almost Full Level for the receive FIFO. +//! +//! This function Sets the FIFO level at which DMA requests or interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel) +{ + unsigned long ulRegVal; + + // + // Read the current configuration + // + ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); + + // + // Mask and set new FIFO thresholds. + // + ulRegVal = ((ulRegVal & 0xFFFF0000) | (((ulRxLevel-1) << 8) | (ulTxLevel-1))); + + // + // Set the transmit and receive FIFO thresholds. + // + HWREG(ulBase + MCSPI_O_XFERLEVEL) = ulRegVal; + +} + +//***************************************************************************** +// +//! Gets the FIFO level at which DMA requests or interrupts are generated. +//! +//! \param ulBase is the base address of the SPI module +//! \param pulTxLevel is a pointer to storage for the transmit FIFO level +//! \param pulRxLevel is a pointer to storage for the receive FIFO level +//! +//! This function gets the FIFO level at which DMA requests or interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel) +{ + unsigned long ulRegVal; + + // + // Read the current configuration + // + ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); + + *pulTxLevel = (ulRegVal & 0xFF); + + *pulRxLevel = ((ulRegVal >> 8) & 0xFF); + +} + +//***************************************************************************** +// +//! Sets the word count. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulWordCount is number of SPI words to be transmitted. +//! +//! This function sets the word count, which is the number of SPI word to +//! be transferred on channel when using the FIFO buffer. +//! +//! \return None. +// +//***************************************************************************** +void +SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount) +{ + unsigned long ulRegVal; + + // + // Read the current configuration + // + ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); + + // + // Mask and set the word count + // + HWREG(ulBase + MCSPI_O_XFERLEVEL) = ((ulRegVal & 0x0000FFFF)| + (ulWordCount & 0xFFFF) << 16); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a SPI interrupt. +//! +//! \param ulBase is the base address of the SPI module +//! \param pfnHandler is a pointer to the function to be called when the +//! SPI interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! SPI interrupts must be enabled via SPIIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Determine the interrupt number based on the SPI module + // + ulInt = SPIIntNumberGet(ulBase); + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the SPI interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a SPI interrupt. +//! +//! \param ulBase is the base address of the SPI module +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a SPI interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Determine the interrupt number based on the SPI module + // + ulInt = SPIIntNumberGet(ulBase); + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables individual SPI interrupt sources. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated SPI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b SPI_INT_DMATX +//! - \b SPI_INT_DMARX +//! - \b SPI_INT_EOW +//! - \b SPI_INT_RX_OVRFLOW +//! - \b SPI_INT_RX_FULL +//! - \b SPI_INT_TX_UDRFLOW +//! - \b SPI_INT_TX_EMPTY +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + unsigned long ulDmaMsk; + + // + // Enable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMATX) + { + ulDmaMsk = SPIDmaMaskGet(ulBase); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; + } + + // + // Enable DMA Rx Interrupt + // + if(ulIntFlags & SPI_INT_DMARX) + { + ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; + } + + // + // Enable the specific Interrupts + // + HWREG(ulBase + MCSPI_O_IRQENABLE) |= (ulIntFlags & 0x0003000F); +} + + +//***************************************************************************** +// +//! Disables individual SPI interrupt sources. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated SPI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to SPIIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + unsigned long ulDmaMsk; + + // + // Disable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMATX) + { + ulDmaMsk = SPIDmaMaskGet(ulBase); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; + } + + // + // Disable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMARX) + { + ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; + } + + // + // Disable the specific Interrupts + // + HWREG(ulBase + MCSPI_O_IRQENABLE) &= ~(ulIntFlags & 0x0003000F); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the SPI module +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the specified SPI. +//! The status of interrupts that are allowed to reflect to the processor can +//! be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in SPIIntEnable(). +// +//***************************************************************************** +unsigned long +SPIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + unsigned long ulIntStat; + unsigned long ulIntFlag; + unsigned long ulDmaMsk; + + // + // Get SPI interrupt status + // + ulIntFlag = HWREG(ulBase + MCSPI_O_IRQSTATUS) & 0x0003000F; + + if(bMasked) + { + ulIntFlag &= HWREG(ulBase + MCSPI_O_IRQENABLE); + } + + // + // Get the interrupt bit + // + ulDmaMsk = SPIDmaMaskGet(ulBase); + + // + // Get the DMA interrupt status + // + if(bMasked) + { + ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED); + } + else + { + ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW); + } + + // + // Get SPI Tx DMA done status + // + if(ulIntStat & ulDmaMsk) + { + ulIntFlag |= SPI_INT_DMATX; + } + + // + // Get SPI Rx DMA done status + // + if(ulIntStat & (ulDmaMsk >> 1)) + { + ulIntFlag |= SPI_INT_DMARX; + } + + // + // Return status + // + return(ulIntFlag); +} + +//***************************************************************************** +// +//! Clears SPI interrupt sources. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SPI interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to SPIIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + unsigned long ulDmaMsk; + + // + // Disable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMATX) + { + ulDmaMsk = SPIDmaMaskGet(ulBase); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; + } + + // + // Disable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMARX) + { + ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; + } + + // + // Clear Interrupts + // + HWREG(ulBase + MCSPI_O_IRQSTATUS) = (ulIntFlags & 0x0003000F); +} + +//***************************************************************************** +// +//! Enables the chip select in software controlled mode +//! +//! \param ulBase is the base address of the SPI module. +//! +//! This function enables the Chip select in software controlled mode. The +//! active state of CS will depend on the configuration done via +//! \sa SPIConfigExpClkSet(). +//! +//! \return None. +// +//***************************************************************************** +void SPICSEnable(unsigned long ulBase) +{ + // + // Set Chip Select enable bit. + // + HWREG( ulBase+MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; +} + +//***************************************************************************** +// +//! Disables the chip select in software controlled mode +//! +//! \param ulBase is the base address of the SPI module. +//! +//! This function disables the Chip select in software controlled mode. The +//! active state of CS will depend on the configuration done via +//! sa SPIConfigSetExpClk(). +//! +//! \return None. +// +//***************************************************************************** +void SPICSDisable(unsigned long ulBase) +{ + // + // Reset Chip Select enable bit. + // + HWREG( ulBase+MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; +} + +//***************************************************************************** +// +//! Send/Receive data buffer over SPI channel +//! +//! \param ulBase is the base address of SPI module +//! \param ucDout is the pointer to Tx data buffer or 0. +//! \param ucDin is pointer to Rx data buffer or 0 +//! \param ulCount is the size of data in bytes. +//! \param ulFlags controlls chip select toggling. +//! +//! This function transfers \e ulCount bytes of data over SPI channel. Since +//! the API sends a SPI word at a time \e ulCount should be a multiple of +//! word length set using SPIConfigSetExpClk(). +//! +//! If the \e ucDout parameter is set to 0, the function will send 0xFF over +//! the SPI MOSI line. +//! +//! If the \e ucDin parameter is set to 0, the function will ignore data on SPI +//! MISO line. +//! +//! The parameter \e ulFlags is logical OR of one or more of the following +//! +//! - \b SPI_CS_ENABLE if CS needs to be enabled at start of transfer. +//! - \b SPI_CS_DISABLE if CS need to be disabled at the end of transfer. +//! +//! This function will not return until data has been transmitted +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +long SPITransfer(unsigned long ulBase, unsigned char *ucDout, + unsigned char *ucDin, unsigned long ulCount, + unsigned long ulFlags) +{ + unsigned long ulWordLength; + long lRet; + + // + // Get the word length + // + ulWordLength = (HWREG(ulBase + MCSPI_O_CH0CONF) & MCSPI_CH0CONF_WL_M); + + // + // Check for word length. + // + if( !((ulWordLength == SPI_WL_8) || (ulWordLength == SPI_WL_16) || + (ulWordLength == SPI_WL_32)) ) + { + return -1; + } + + if( ulWordLength == SPI_WL_8 ) + { + // + // Do byte transfer + // + lRet = SPITransfer8(ulBase,ucDout,ucDin,ulCount,ulFlags); + } + else if( ulWordLength == SPI_WL_16 ) + { + + // + // Do half-word transfer + // + lRet = SPITransfer16(ulBase,(unsigned short *)ucDout, + (unsigned short *)ucDin,ulCount,ulFlags); + } + else + { + // + // Do word transfer + // + lRet = SPITransfer32(ulBase,(unsigned long *)ucDout, + (unsigned long *)ucDin,ulCount,ulFlags); + } + + // + // return + // + return lRet; + +} +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/spi.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/spi.h new file mode 100644 index 000000000..da77b200d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/spi.h @@ -0,0 +1,168 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// spi.h +// +// Defines and Macros for the SPI. +// +//***************************************************************************** + +#ifndef __SPI_H__ +#define __SPI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// Values that can be passed to SPIConfigSetExpClk() as ulMode parameter +//***************************************************************************** +#define SPI_MODE_MASTER 0x00000000 +#define SPI_MODE_SLAVE 0x00000004 + +//***************************************************************************** +// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter +//***************************************************************************** +#define SPI_SUB_MODE_0 0x00000000 +#define SPI_SUB_MODE_1 0x00000001 +#define SPI_SUB_MODE_2 0x00000002 +#define SPI_SUB_MODE_3 0x00000003 + + +//***************************************************************************** +// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter +//***************************************************************************** +#define SPI_SW_CTRL_CS 0x01000000 +#define SPI_HW_CTRL_CS 0x00000000 +#define SPI_3PIN_MODE 0x02000000 +#define SPI_4PIN_MODE 0x00000000 +#define SPI_TURBO_ON 0x00080000 +#define SPI_TURBO_OFF 0x00000000 +#define SPI_CS_ACTIVEHIGH 0x00000000 +#define SPI_CS_ACTIVELOW 0x00000040 +#define SPI_WL_8 0x00000380 +#define SPI_WL_16 0x00000780 +#define SPI_WL_32 0x00000F80 + +//***************************************************************************** +// Values that can be passed to SPIFIFOEnable() and SPIFIFODisable() +//***************************************************************************** +#define SPI_TX_FIFO 0x08000000 +#define SPI_RX_FIFO 0x10000000 + +//***************************************************************************** +// Values that can be passed to SPIDMAEnable() and SPIDMADisable() +//***************************************************************************** +#define SPI_RX_DMA 0x00008000 +#define SPI_TX_DMA 0x00004000 + +//***************************************************************************** +// Values that can be passed to SPIIntEnable(), SPIIntDiasble(), +// SPIIntClear() or returned from SPIStatus() +//***************************************************************************** +#define SPI_INT_DMATX 0x20000000 +#define SPI_INT_DMARX 0x10000000 +#define SPI_INT_EOW 0x00020000 +#define SPI_INT_WKS 0x00010000 +#define SPI_INT_RX_OVRFLOW 0x00000008 +#define SPI_INT_RX_FULL 0x00000004 +#define SPI_INT_TX_UDRFLOW 0x00000002 +#define SPI_INT_TX_EMPTY 0x00000001 + +//***************************************************************************** +// Values that can be passed to SPITransfer() +//***************************************************************************** +#define SPI_CS_ENABLE 0x00000001 +#define SPI_CS_DISABLE 0x00000002 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void SPIEnable(unsigned long ulBase); +extern void SPIDisable(unsigned long ulBase); +extern void SPIReset(unsigned long ulBase); +extern void SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, + unsigned long ulBitRate, unsigned long ulMode, + unsigned long ulSubMode, unsigned long ulConfig); +extern long SPIDataGetNonBlocking(unsigned long ulBase, + unsigned long * pulData); +extern void SPIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SPIDataPutNonBlocking(unsigned long ulBase, + unsigned long ulData); +extern void SPIDataPut(unsigned long ulBase, unsigned long ulData); +extern void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags); +extern void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags); +extern void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel); +extern void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel); +extern void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount); +extern void SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void SPIIntUnregister(unsigned long ulBase); +extern void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags); +extern void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags); +extern void SPICSEnable(unsigned long ulBase); +extern void SPICSDisable(unsigned long ulBase); +extern long SPITransfer(unsigned long ulBase, unsigned char *ucDout, + unsigned char *ucDin, unsigned long ulSize, + unsigned long ulFlags); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SPI_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/systick.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/systick.c new file mode 100644 index 000000000..3bdd50e1c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/systick.c @@ -0,0 +1,280 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// systick.c +// +// Driver for the SysTick timer in NVIC. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "systick.h" + +//***************************************************************************** +// +//! Enables the SysTick counter. +//! +//! This function starts the SysTick counter. If an interrupt handler has been +//! registered, it is called when the SysTick counter rolls over. +//! +//! \note Calling this function causes the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to SysTickPeriodSet(). If +//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be +//! written to force the reload. Any write to this register clears the SysTick +//! counter to 0 and causes a reload with the supplied period on the next +//! clock. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickEnable(void) +{ + // + // Enable SysTick. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the SysTick counter. +//! +//! This function stops the SysTick counter. If an interrupt handler has been +//! registered, it is not called until SysTick is restarted. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickDisable(void) +{ + // + // Disable SysTick. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the SysTick interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! This function registers the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(FAULT_SYSTICK, pfnHandler); + + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the SysTick interrupt. +//! +//! This function unregisters the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntUnregister(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_SYSTICK); +} + +//***************************************************************************** +// +//! Enables the SysTick interrupt. +//! +//! This function enables the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler is not required to clear the SysTick +//! interrupt source because it is cleared automatically by the NVIC when the +//! interrupt handler is called. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntEnable(void) +{ + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! Disables the SysTick interrupt. +//! +//! This function disables the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntDisable(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} + +//***************************************************************************** +// +//! Sets the period of the SysTick counter. +//! +//! \param ulPeriod is the number of clock ticks in each period of the SysTick +//! counter and must be between 1 and 16,777,216, inclusive. +//! +//! This function sets the rate at which the SysTick counter wraps, which +//! equates to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload +//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and causes a reload with the \e ulPeriod supplied here on +//! the next clock after SysTick is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickPeriodSet(unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); + + // + // Set the period of the SysTick counter. + // + HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; +} + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps, which +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +unsigned long +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(HWREG(NVIC_ST_RELOAD) + 1); +} + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter, which is +//! a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +unsigned long +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(HWREG(NVIC_ST_CURRENT)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/systick.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/systick.h new file mode 100644 index 000000000..21f1ced37 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/systick.h @@ -0,0 +1,83 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// systick.h +// +// Prototypes for the SysTick driver. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/timer.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/timer.h new file mode 100644 index 000000000..61c59d6e4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/timer.h @@ -0,0 +1,215 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// timer.h +// +// Prototypes for the timer module +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** + +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count + // timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count + // timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers + +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** + +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + + +//***************************************************************************** +// +// Values that can be passed to TimerSynchronize as the ulTimers parameter. +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B + +//***************************************************************************** +// +// Values that can be passed to TimerDMAEventSet() or returned from +// TimerDMAEventGet(). +// +//***************************************************************************** +#define TIMER_DMA_MODEMATCH_B 0x00000800 +#define TIMER_DMA_CAPEVENT_B 0x00000400 +#define TIMER_DMA_CAPMATCH_B 0x00000200 +#define TIMER_DMA_TIMEOUT_B 0x00000100 +#define TIMER_DMA_MODEMATCH_A 0x00000010 +#define TIMER_DMA_CAPEVENT_A 0x00000004 +#define TIMER_DMA_CAPMATCH_A 0x00000002 +#define TIMER_DMA_TIMEOUT_A 0x00000001 + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); + +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerValueSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); + +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent); +extern unsigned long TimerDMAEventGet(unsigned long ulBase); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/uart.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/uart.h new file mode 100644 index 000000000..99de0b8b2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/uart.h @@ -0,0 +1,239 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// uart.h +// +// Defines and Macros for the UART. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_DMATX 0x20000 // DMA Tx Done interrupt Mask +#define UART_INT_DMARX 0x10000 // DMA Rx Done interrupt Mask +#define UART_INT_EOT 0x800 // End of transfer interrupt Mask +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask +#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask + + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter +// and returned by UARTConfigGetExpClk in the pulConfig parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ulParity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and +// returned by UARTFIFOLevelGet in the pulTxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and +// returned by UARTFIFOLevelGet in the pulRxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTModemControlSet()and UARTModemControlClear() +// or returned from UARTModemControlGet(). +// +//***************************************************************************** +#define UART_OUTPUT_RTS 0x00000800 + +//***************************************************************************** +// +// Values that can be returned from UARTModemStatusGet(). +// +//***************************************************************************** +#define UART_INPUT_CTS 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTFlowControl() or returned from +// UARTFlowControlGet(). +// +//***************************************************************************** +#define UART_FLOWCONTROL_TX 0x00008000 +#define UART_FLOWCONTROL_RX 0x00004000 +#define UART_FLOWCONTROL_NONE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +#define UART_TXINT_MODE_FIFO 0x00000000 +#define UART_TXINT_MODE_EOT 0x00000010 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel); +extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); +extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern void UARTFIFOEnable(unsigned long ulBase); +extern void UARTFIFODisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern tBoolean UARTBusy(unsigned long ulBase); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); +extern unsigned long UARTRxErrorGet(unsigned long ulBase); +extern void UARTRxErrorClear(unsigned long ulBase); +extern void UARTModemControlSet(unsigned long ulBase, + unsigned long ulControl); +extern void UARTModemControlClear(unsigned long ulBase, + unsigned long ulControl); +extern unsigned long UARTModemControlGet(unsigned long ulBase); +extern unsigned long UARTModemStatusGet(unsigned long ulBase); +extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTFlowControlGet(unsigned long ulBase); +extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTTxIntModeGet(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/udma.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/udma.c new file mode 100644 index 000000000..4c0b0af53 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/udma.c @@ -0,0 +1,1261 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// udma.c +// +// Driver for the micro-DMA controller. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uDMA_Micro_Direct_Memory_Access_api +//! @{ +// +//***************************************************************************** + + +#include "inc/hw_types.h" +#include "inc/hw_udma.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "debug.h" +#include "interrupt.h" +#include "udma.h" + + +//***************************************************************************** +// +//! Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAEnable(void) +{ + // + // Set the master enable bit in the config register. + // + HWREG(UDMA_BASE + UDMA_O_CFG) = UDMA_CFG_MASTEN; +} + +//***************************************************************************** +// +//! Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller cannot operate until re-enabled with uDMAEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +uDMADisable(void) +{ + // + // Clear the master enable bit in the config register. + // + HWREG(UDMA_BASE + UDMA_O_CFG) = 0; +} + +//***************************************************************************** +// +//! Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +unsigned long +uDMAErrorStatusGet(void) +{ + // + // Return the uDMA error status. + // + return(HWREG(UDMA_BASE + UDMA_O_ERRCLR)); +} + +//***************************************************************************** +// +//! Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. This function should +//! be called from within the uDMA error interrupt handler to clear the +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAErrorStatusClear(void) +{ + // + // Clear the uDMA error interrupt. + // + HWREG(UDMA_BASE + UDMA_O_ERRCLR) = 1; +} + +//***************************************************************************** +// +//! Enables a uDMA channel for operation. +//! +//! \param ulChannelNum is the channel number to enable. +//! +//! This function enables a specific uDMA channel for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel is automatically disabled by +//! the uDMA controller. Therefore, this function should be called prior to +//! starting up any new transfer. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelEnable(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the enable set register. + // + HWREG(UDMA_BASE + UDMA_O_ENASET) = 1 << (ulChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Disables a uDMA channel for operation. +//! +//! \param ulChannelNum is the channel number to disable. +//! +//! This function disables a specific uDMA channel. Once disabled, a channel +//! cannot respond to uDMA transfer requests until re-enabled via +//! uDMAChannelEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelDisable(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the enable clear register. + // + HWREG(UDMA_BASE + UDMA_O_ENACLR) = 1 << (ulChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Checks if a uDMA channel is enabled for operation. +//! +//! \param ulChannelNum is the channel number to check. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! function can be used to check the status of a transfer, as the channel is +//! automatically disabled at the end of a transfer. +//! +//! \return Returns \b true if the channel is enabled, \b false if disabled. +// +//***************************************************************************** +tBoolean +uDMAChannelIsEnabled(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // AND the specified channel bit with the enable register and return the + // result. + // + return((HWREG(UDMA_BASE + UDMA_O_ENASET) & + (1 << (ulChannelNum & 0x1f))) ? true : false); +} + +//***************************************************************************** +// +//! Sets the base address for the channel control table. +//! +//! \param pControlTable is a pointer to the 1024-byte-aligned base address +//! of the uDMA channel control table. +//! +//! This function configures the base address of the channel control table. +//! This table resides in system memory and holds control information for each +//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base +//! address must be configured before any of the channel functions can be used. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels and the transfer modes that are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAControlBaseSet(void *pControlTable) +{ + // + // Check the arguments. + // + ASSERT(((unsigned long)pControlTable & ~0x3FF) == + (unsigned long)pControlTable); + ASSERT((unsigned long)pControlTable >= 0x20000000); + + // + // Program the base address into the register. + // + HWREG(UDMA_BASE + UDMA_O_CTLBASE) = (unsigned long)pControlTable; +} + +//***************************************************************************** +// +//! Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +void * +uDMAControlBaseGet(void) +{ + // + // Read the current value of the control base register and return it to + // the caller. + // + return((void *)HWREG(UDMA_BASE + UDMA_O_CTLBASE)); +} + +//***************************************************************************** +// +//! Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +void * +uDMAControlAlternateBaseGet(void) +{ + // + // Read the current value of the control base register and return it to + // the caller. + // + return((void *)HWREG(UDMA_BASE + UDMA_O_ALTBASE)); +} + +//***************************************************************************** +// +//! Requests a uDMA channel to start a transfer. +//! +//! \param ulChannelNum is the channel number on which to request a uDMA +//! transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This function could be used for performing a memory-to-memory +//! transfer or if for some reason, a transfer needs to be initiated by software +//! instead of the peripheral associated with that channel. +//! +//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then +//! the completion is signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion is signaled on the +//! peripheral's interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelRequest(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the software uDMA request register. + // + HWREG(UDMA_BASE + UDMA_O_SWREQ) = 1 << (ulChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Enables attributes of a uDMA channel. +//! +//! \param ulChannelNum is the channel to configure. +//! \param ulAttr is a combination of attributes for the channel. +//! +//! This function is used to enable attributes of a uDMA channel. +//! +//! The \e ulAttr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Set the useburst bit for this channel if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) = 1 << ulChannelNum; + } + + // + // Set the alternate control select bit for this channel, + // if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_BASE + UDMA_O_ALTSET) = 1 << ulChannelNum; + } + + // + // Set the high priority bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_BASE + UDMA_O_PRIOSET) = 1 << ulChannelNum; + } + + // + // Set the request mask bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_BASE + UDMA_O_REQMASKSET) = 1 << ulChannelNum; + } +} + +//***************************************************************************** +// +//! Disables attributes of a uDMA channel. +//! +//! \param ulChannelNum is the channel to configure. +//! \param ulAttr is a combination of attributes for the channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! The \e ulAttr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Clear the useburst bit for this channel if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_BASE + UDMA_O_USEBURSTCLR) = 1 << ulChannelNum; + } + + // + // Clear the alternate control select bit for this channel, if set in + // ulConfig. + // + if(ulAttr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_BASE + UDMA_O_ALTCLR) = 1 << ulChannelNum; + } + + // + // Clear the high priority bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_BASE + UDMA_O_PRIOCLR) = 1 << ulChannelNum; + } + + // + // Clear the request mask bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_BASE + UDMA_O_REQMASKCLR) = 1 << ulChannelNum; + } +} + +//***************************************************************************** +// +//! Gets the enabled attributes of a uDMA channel. +//! +//! \param ulChannelNum is the channel to configure. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! \return Returns the logical OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +unsigned long +uDMAChannelAttributeGet(unsigned long ulChannelNum) +{ + unsigned long ulAttr = 0; + + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Check to see if useburst bit is set for this channel. + // + if(HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_USEBURST; + } + + // + // Check to see if the alternate control bit is set for this channel. + // + if(HWREG(UDMA_BASE + UDMA_O_ALTSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_ALTSELECT; + } + + // + // Check to see if the high priority bit is set for this channel. + // + if(HWREG(UDMA_BASE + UDMA_O_PRIOSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // + // Check to see if the request mask bit is set for this channel. + // + if(HWREG(UDMA_BASE + UDMA_O_REQMASKSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_REQMASK; + } + + // + // Return the configuration flags. + // + return(ulAttr); +} + +//***************************************************************************** +// +//! Sets the control parameters for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulControl is logical OR of several control values to set the control +//! parameters for the channel. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! parameters are typically not changed often. +//! +//! The \e ulChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. +//! +//! The \e ulControl parameter is the logical OR of five values: the data size, +//! the source address increment, the destination address increment, the +//! arbitration size, and the use burst flag. The choices available for each +//! of these values is described below. +//! +//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or +//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. +//! +//! Choose the source address increment from one of \b UDMA_SRC_INC_8, +//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or +//! to select non-incrementing. +//! +//! Choose the destination address increment from one of \b UDMA_DST_INC_8, +//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or +//! to select non-incrementing. +//! +//! The arbitration size determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size +//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, +//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 +//! items, in powers of 2. +//! +//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only +//! respond to burst requests at the tail end of a scatter-gather transfer. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelControlSet(unsigned long ulChannelStructIndex, + unsigned long ulControl) +{ + tDMAControlTable *pCtl; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pCtl = (tDMAControlTable *)HWREG(UDMA_BASE+UDMA_O_CTLBASE); + + // + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + // + pCtl[ulChannelStructIndex].ulControl = + ((pCtl[ulChannelStructIndex].ulControl & + ~(UDMA_CHCTL_DSTINC_M | + UDMA_CHCTL_DSTSIZE_M | + UDMA_CHCTL_SRCINC_M | + UDMA_CHCTL_SRCSIZE_M | + UDMA_CHCTL_ARBSIZE_M | + UDMA_CHCTL_NXTUSEBURST)) | + ulControl); +} + +//***************************************************************************** +// +//! Sets the transfer parameters for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulMode is the type of uDMA transfer. +//! \param pvSrcAddr is the source address for the transfer. +//! \param pvDstAddr is the destination address for the transfer. +//! \param ulTransferSize is the number of data items to transfer. +//! +//! This function is used to configure the parameters for a uDMA transfer. +//! These parameters are typically changed often. The function +//! uDMAChannelControlSet() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \e ulChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. +//! +//! The \e ulMode parameter should be one of the following values: +//! +//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. +//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once +//! started even if the request is removed. +//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the +//! primary and alternate control structures for the channel. This mode +//! allows use of ping-pong buffering for uDMA transfers. +//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather +//! transfer. +//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather +//! transfer. +//! +//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. For example, if the item size is set to 4-bytes, +//! these addresses must be 4-byte aligned. The compiler can take care of this +//! alignment if the pointers are pointing to storage of the appropriate +//! data type. +//! +//! The \e ulTransferSize parameter is the number of data items, not the number +//! of bytes. The value of this parameter should not exceed 1024. +//! +//! The two scatter-gather modes, memory and peripheral, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function looks for the \b UDMA_PRI_SELECT and +//! \b UDMA_ALT_SELECT flag along with the channel number and sets the +//! scatter-gather mode as appropriate for the primary or alternate control +//! structure. +//! +//! The channel must also be enabled using uDMAChannelEnable() after calling +//! this function. The transfer does not begin until the channel has been +//! configured and enabled. Note that the channel is automatically disabled +//! after the transfer is completed, meaning that uDMAChannelEnable() must be +//! called again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results are unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelTransferSet(unsigned long ulChannelStructIndex, + unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr, + unsigned long ulTransferSize) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + unsigned long ulInc; + unsigned long ulBufferBytes; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); + ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((unsigned long)pvSrcAddr >= 0x20000000); + ASSERT((unsigned long)pvDstAddr >= 0x20000000); + ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024)); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); + + // + // Get the current control word value and mask off the mode and size + // fields. + // + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); + + // + // Adjust the mode if the alt control structure is selected. + // + if(ulChannelStructIndex & UDMA_ALT_SELECT) + { + if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ulMode |= UDMA_MODE_ALT_SELECT; + } + } + + // + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + // + ulControl |= ulMode | ((ulTransferSize - 1) << 4); + + // + // Get the address increment value for the source, from the control word. + // + ulInc = (ulControl & UDMA_CHCTL_SRCINC_M); + + // + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + // + if(ulInc != UDMA_SRC_INC_NONE) + { + ulInc = ulInc >> 26; + ulBufferBytes = ulTransferSize << ulInc; + pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulBufferBytes - 1); + } + + // + // Load the source ending address into the control block. + // + pControlTable[ulChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // + // Get the address increment value for the destination, from the control + // word. + // + ulInc = ulControl & UDMA_CHCTL_DSTINC_M; + + // + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + // + if(ulInc != UDMA_DST_INC_NONE) + { + // + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer must point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + // + if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ulChannelStructIndex | + UDMA_ALT_SELECT].ulSpare; + } + // + // Not a scatter-gather transfer, calculate end pointer normally. + // + else + { + ulInc = ulInc >> 30; + ulBufferBytes = ulTransferSize << ulInc; + pvDstAddr = (void *)((unsigned long)pvDstAddr + ulBufferBytes - 1); + } + } + + // + // Load the destination ending address into the control block. + // + pControlTable[ulChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // + // Write the new control word value. + // + pControlTable[ulChannelStructIndex].ulControl = ulControl; +} + +//***************************************************************************** +// +//! Configures a uDMA channel for scatter-gather mode. +//! +//! \param ulChannelNum is the uDMA channel number. +//! \param ulTaskCount is the number of scatter-gather tasks to execute. +//! \param pvTaskList is a pointer to the beginning of the scatter-gather +//! task list. +//! \param ulIsPeriphSG is a flag to indicate it is a peripheral scatter-gather +//! transfer (else it is memory scatter-gather transfer) +//! +//! This function is used to configure a channel for scatter-gather mode. +//! The caller must have already set up a task list and must pass a pointer to +//! the start of the task list as the \e pvTaskList parameter. The +//! \e ulTaskCount parameter is the count of tasks in the task list, not the +//! size of the task list. The flag \e bIsPeriphSG should be used to indicate +//! if scatter-gather should be configured for peripheral or memory +//! operation. +//! +//! \sa uDMATaskStructEntry +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount, + void *pvTaskList, unsigned long ulIsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // + // Check the parameters + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ulTaskCount <= 1024); + ASSERT(ulTaskCount != 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); + + // + // Get a handy pointer to the task list + // + pTaskTable = (tDMAControlTable *)pvTaskList; + + // + // Compute the ending address for the source pointer. This address is the + // last element of the last task in the task table + // + pControlTable[ulChannelNum].pvSrcEndAddr = + &pTaskTable[ulTaskCount - 1].ulSpare; + + // + // Compute the ending address for the destination pointer. This address + // is the end of the alternate structure for this channel. + // + pControlTable[ulChannelNum].pvDstEndAddr = + &pControlTable[ulChannelNum | UDMA_ALT_SELECT].ulSpare; + + // + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + // + pControlTable[ulChannelNum].ulControl = + (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 | + UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 | + UDMA_CHCTL_ARBSIZE_4 | + (((ulTaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) | + (ulIsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG : + UDMA_CHCTL_XFERMODE_MEM_SG)); +} + +//***************************************************************************** +// +//! Gets the current transfer size for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items is returned. If the transfer is +//! complete, then 0 is returned. +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +unsigned long +uDMAChannelSizeGet(unsigned long ulChannelStructIndex) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); + + // + // Get the current control word value and mask off all but the size field + // and the mode field. + // + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); + + // + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer + // + if(ulControl == 0) + { + return(0); + } + + // + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + // + else + { + // + // Shift the size field and add one, then return to user. + // + return((ulControl >> 4) + 1); + } +} + +//***************************************************************************** +// +//! Gets the transfer mode for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the transfer mode for the uDMA channel and +//! to query the status of a transfer on a channel. When the transfer is +//! complete the mode is \b UDMA_MODE_STOP. +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which is one of the following values: \b UDMA_MODE_STOP, +//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. +// +//***************************************************************************** +unsigned long +uDMAChannelModeGet(unsigned long ulChannelStructIndex) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_O_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); + + // + // Get the current control word value and mask off all but the mode field. + // + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + UDMA_CHCTL_XFERMODE_M); + + // + // Check if scatter/gather mode, and if so, mask off the alt bit. + // + if(((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ulControl &= ~UDMA_MODE_ALT_SELECT; + } + + // + // Return the mode to the caller. + // + return(ulControl); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the uDMA controller. +//! +//! \param ulIntChannel identifies which uDMA interrupt is to be registered. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This function registers and enables the handler to be called when the uDMA +//! controller generates an interrupt. The \e ulIntChannel parameter should be +//! one of the following: +//! +//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts +//! from the uDMA software channel (UDMA_CHANNEL_SW) +//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error +//! interrupts +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note The interrupt handler for the uDMA is for transfer completion when +//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The +//! interrupts for each peripheral channel are handled through the individual +//! peripheral interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(pfnHandler); + ASSERT((ulIntChannel == UDMA_INT_SW) || (ulIntChannel == UDMA_INT_ERR)); + + // + // Register the interrupt handler. + // + IntRegister(ulIntChannel, pfnHandler); + + // + // Enable the memory management fault. + // + IntEnable(ulIntChannel); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the uDMA controller. +//! +//! \param ulIntChannel identifies which uDMA interrupt to unregister. +//! +//! This function disables and unregisters the handler to be called for the +//! specified uDMA interrupt. The \e ulIntChannel parameter should be one of +//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function +//! uDMAIntRegister(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntUnregister(unsigned long ulIntChannel) +{ + // + // Disable the interrupt. + // + IntDisable(ulIntChannel); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulIntChannel); +} + +//***************************************************************************** +// +//! Gets the uDMA controller channel interrupt status. +//! +//! This function is used to get the interrupt status of the uDMA controller. +//! The returned value is a 32-bit bit mask that indicates which channels are +//! requesting an interrupt. This function can be used from within an +//! interrupt handler to determine or confirm which uDMA channel has requested +//! an interrupt. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. +//! +//! \return Returns a 32-bit mask which indicates requesting uDMA channels. +//! There is a bit for each channel and a 1 indicates that the channel +//! is requesting an interrupt. Multiple bits can be set. +// +//***************************************************************************** +unsigned long +uDMAIntStatus(void) +{ + + + // + // Return the value of the uDMA interrupt status register + // + return(HWREG(UDMA_BASE + UDMA_O_CHIS)); +} + +//***************************************************************************** +// +//! Clears uDMA interrupt status. +//! +//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! This function clears bits in the uDMA interrupt status register according +//! to which bits are set in \e ulChanMask. There is one bit for each channel. +//! If a a bit is set in \e ulChanMask, then that corresponding channel's +//! interrupt status is cleared (if it was set). +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntClear(unsigned long ulChanMask) +{ + + // + // Clear the requested bits in the uDMA interrupt status register + // + HWREG(UDMA_BASE + UDMA_O_CHIS) = ulChanMask; +} + +//***************************************************************************** +// +//! Assigns a peripheral mapping for a uDMA channel. +//! +//! \param ulMapping is a macro specifying the peripheral assignment for +//! a channel. +//! +//! This function assigns a peripheral mapping to a uDMA channel. It is +//! used to select which peripheral is used for a uDMA channel. The parameter +//! \e ulMapping should be one of the macros named \b UDMA_CHn_tttt from the +//! header file \e udma.h. For example, to assign uDMA channel 8 to the +//! UARTA0 RX channel, the parameter should be the macro \b UDMA_CH8_UARTA0_RX. +//! +//! Please consult the data sheet for a table showing all the +//! possible peripheral assignments for the uDMA channels for a particular +//! device. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for +//! your part. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAssign(unsigned long ulMapping) +{ + unsigned long ulMapReg; + unsigned long ulMapShift; + unsigned long ulChannelNum; + + // + // Check the parameters + // + ASSERT((ulMapping & 0xffffff00) < 0x00050000); + + + // + // Extract the channel number and map encoding value from the parameter. + // + ulChannelNum = ulMapping & 0x1f; + ulMapping = ulMapping >> 16; + + // + // Find the uDMA channel mapping register and shift value to use for this + // channel + // + ulMapReg = UDMA_BASE + UDMA_O_CHMAP0 + ((ulChannelNum / 8) * 4); + ulMapShift = (ulChannelNum % 8) * 4; + + // + // Set the channel map encoding for this channel + // + HWREG(ulMapReg) = (HWREG(ulMapReg) & ~(0xf << ulMapShift)) | + ulMapping << ulMapShift; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/udma.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/udma.h new file mode 100644 index 000000000..d1e4d27ee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/udma.h @@ -0,0 +1,668 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// udma.h +// +// Prototypes and macros for the uDMA controller. +// +//***************************************************************************** + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup uDMA_Micro_Direct_Memory_Access_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// A structure that defines an entry in the channel control table. These +// fields are used by the uDMA controller and normally it is not necessary for +// software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + // + // The ending source address of the data transfer. + // + volatile void *pvSrcEndAddr; + + // + // The ending destination address of the data transfer. + // + volatile void *pvDstEndAddr; + + // + // The channel control mode. + // + volatile unsigned long ulControl; + + // + // An unused location. + // + volatile unsigned long ulSpare; +} +tDMAControlTable; + +//***************************************************************************** +// +//! A helper macro for building scatter-gather task table entries. +//! +//! \param ulTransferCount is the count of items to transfer for this task. +//! \param ulItemSize is the bit size of the items to transfer for this task. +//! \param ulSrcIncrement is the bit size increment for source data. +//! \param pvSrcAddr is the starting address of the data to transfer. +//! \param ulDstIncrement is the bit size increment for destination data. +//! \param pvDstAddr is the starting address of the destination data. +//! \param ulArbSize is the arbitration size to use for the transfer task. +//! \param ulMode is the transfer mode for this task. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! The \e ulTransferCount parameter is the number of items that will be +//! transferred by this task. It must be in the range 1-1024. +//! +//! The \e ulItemSize parameter is the bit size of the transfer data. It must +//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. +//! +//! The \e ulSrcIncrement parameter is the increment size for the source data. +//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, +//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. +//! +//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source +//! data. +//! +//! The \e ulDstIncrement parameter is the increment size for the destination +//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, +//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. +//! +//! The \e pvDstAddr parameter is a void pointer to the beginning of the +//! location where the data will be transferred. +//! +//! The \e ulArbSize parameter is the arbitration size for the transfer, and +//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on +//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in +//! powers of 2, from 1 to 1024. +//! +//! The \e ulMode parameter is the mode to use for this transfer task. It +//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note +//! that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of tDMAControlTable type, like this: +//! +//! \verbatim +//! tDMAControlTable MyTaskList[] = +//! { +//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, +//! UDMA_SRC_INC_8, MySourceBuf, +//! UDMA_DST_INC_8, MyDestBuf, +//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), +//! uDMATaskStructEntry(Task2Count, ... ), +//! } +//! \endverbatim +//! +//! \return Nothing; this is not a function. +// +//***************************************************************************** +#define uDMATaskStructEntry(ulTransferCount, \ + ulItemSize, \ + ulSrcIncrement, \ + pvSrcAddr, \ + ulDstIncrement, \ + pvDstAddr, \ + ulArbSize, \ + ulMode) \ + { \ + (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ + ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \ + ((ulSrcIncrement) >> 26)) - 1]))), \ + (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \ + ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \ + ((ulDstIncrement) >> 30)) - 1]))), \ + (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \ + (((ulTransferCount) - 1) << 4) | \ + ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ + (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \ + } + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAModeSet() and returned +// uDMAModeGet(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ + 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER \ + 0x00000006 +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 + +//***************************************************************************** +// +// uDMA interrupt sources, to be passed to uDMAIntRegister() and +// uDMAIntUnregister(). +// +//***************************************************************************** +#define UDMA_INT_SW INT_UDMA +#define UDMA_INT_ERR INT_UDMAERR + +//***************************************************************************** + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xc0000000 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_NEXT_USEBURST 0x00000008 + +//***************************************************************************** +// +// Values that can be passed to uDMAChannelAssign() to select peripheral +// mapping for each channel. The channels named RESERVED may be assigned +// to a peripheral in future parts. +// +//***************************************************************************** +// +// Channel 0 +// +#define UDMA_CH0_TIMERA0_A 0x00000000 +#define UDMA_CH0_SHAMD5_CIN 0x00010000 +#define UDMA_CH0_SW 0x00030000 + +// +// Channel 1 +// +#define UDMA_CH1_TIMERA0_B 0x00000001 +#define UDMA_CH1_SHAMD5_DIN 0x00010001 +#define UDMA_CH1_SW 0x00030001 + +// +// Channel 2 +// +#define UDMA_CH2_TIMERA1_A 0x00000002 +#define UDMA_CH2_SHAMD5_COUT 0x00010002 +#define UDMA_CH2_SW 0x00030002 + +// +// Channel 3 +// +#define UDMA_CH3_TIMERA1_B 0x00000003 +#define UDMA_CH3_DES_CIN 0x00010003 +#define UDMA_CH3_SW 0x00030003 + +// +// Channel 4 +// +#define UDMA_CH4_TIMERA2_A 0x00000004 +#define UDMA_CH4_DES_DIN 0x00010004 +#define UDMA_CH4_I2S_RX 0x00020004 +#define UDMA_CH4_SW 0x00030004 + +// +// Channel 5 +// +#define UDMA_CH5_TIMERA2_B 0x00000005 +#define UDMA_CH5_DES_DOUT 0x00010005 +#define UDMA_CH5_I2S_TX 0x00020005 +#define UDMA_CH5_SW 0x00030005 + +// +// Channel 6 +// +#define UDMA_CH6_TIMERA3_A 0x00000006 +#define UDMA_CH6_GSPI_RX 0x00010006 +#define UDMA_CH6_GPIOA2 0x00020006 +#define UDMA_CH6_SW 0x00030006 + +// +// Channel 7 +// +#define UDMA_CH7_TIMERA3_B 0x00000007 +#define UDMA_CH7_GSPI_TX 0x00010007 +#define UDMA_CH7_GPIOA3 0x00020007 +#define UDMA_CH7_SW 0x00030007 + + +// +// Channel 8 +// +#define UDMA_CH8_UARTA0_RX 0x00000008 +#define UDMA_CH8_TIMERA0_A 0x00010008 +#define UDMA_CH8_TIMERA2_A 0x00020008 +#define UDMA_CH8_SW 0x00030008 + + +// +// Channel 9 +// +#define UDMA_CH9_UARTA0_TX 0x00000009 +#define UDMA_CH9_TIMERA0_B 0x00010009 +#define UDMA_CH9_TIMERA2_B 0x00020009 +#define UDMA_CH9_SW 0x00030009 + + +// +// Channel 10 +// +#define UDMA_CH10_UARTA1_RX 0x0000000A +#define UDMA_CH10_TIMERA1_A 0x0001000A +#define UDMA_CH10_TIMERA3_A 0x0002000A +#define UDMA_CH10_SW 0x0003000A + +// +// Channel 11 +// +#define UDMA_CH11_UARTA1_TX 0x0000000B +#define UDMA_CH11_TIMERA1_B 0x0001000B +#define UDMA_CH11_TIMERA3_B 0x0002000B +#define UDMA_CH11_SW 0x0003000B + + +// +// Channel 12 +// +#define UDMA_CH12_LSPI_RX 0x0000000C +#define UDMA_CH12_SW 0x0003000C + + +// +// Channel 13 +// +#define UDMA_CH13_LSPI_TX 0x0000000D +#define UDMA_CH13_SW 0x0003000D + + +// +// Channel 14 +// +#define UDMA_CH14_ADC_CH0 0x0000000E +#define UDMA_CH14_SDHOST_RX 0x0002000E +#define UDMA_CH14_SW 0x0003000E + + +// +// Channel 15 +// +#define UDMA_CH15_ADC_CH1 0x0000000F +#define UDMA_CH15_SDHOST_TX 0x0002000F +#define UDMA_CH15_SW 0x0003000F + + +// +// Channel 16 +// +#define UDMA_CH16_ADC_CH2 0x00000010 +#define UDMA_CH16_TIMERA2_A 0x00010010 +#define UDMA_CH16_SW 0x00030010 + + +// +// Channel 17 +// +#define UDMA_CH17_ADC_CH3 0x00000011 +#define UDMA_CH17_TIMERA2_B 0x00010011 +#define UDMA_CH17_SW 0x00030011 + +// +// Channel 18 +// +#define UDMA_CH18_GPIOA0 0x00000012 +#define UDMA_CH18_AES_CIN 0x00010012 +#define UDMA_CH18_I2S_RX 0x00020012 +#define UDMA_CH18_SW 0x00030012 + + +// +// Channel 19 +// +#define UDMA_CH19_GPOIA1 0x00000013 +#define UDMA_CH19_AES_COUT 0x00010013 +#define UDMA_CH19_I2S_TX 0x00020013 +#define UDMA_CH19_SW 0x00030013 + + +// +// Channel 20 +// +#define UDMA_CH20_GPIOA2 0x00000014 +#define UDMA_CH20_AES_DIN 0x00010014 +#define UDMA_CH20_SW 0x00030014 + + +// +// Channel 21 +// +#define UDMA_CH21_GPIOA3 0x00000015 +#define UDMA_CH21_AES_DOUT 0x00010015 +#define UDMA_CH21_SW 0x00030015 + + +// +// Channel 22 +// +#define UDMA_CH22_CAMERA 0x00000016 +#define UDMA_CH22_GPIOA4 0x00010016 +#define UDMA_CH22_SW 0x00030016 + + +// +// Channel 23 +// +#define UDMA_CH23_SDHOST_RX 0x00000017 +#define UDMA_CH23_TIMERA3_A 0x00010017 +#define UDMA_CH23_TIMERA2_A 0x00020017 +#define UDMA_CH23_SW 0x00030017 + + +// +// Channel 24 +// +#define UDMA_CH24_SDHOST_TX 0x00000018 +#define UDMA_CH24_TIMERA3_B 0x00010018 +#define UDMA_CH24_TIMERA2_B 0x00020018 +#define UDMA_CH24_SW 0x00030018 + + +// +// Channel 25 +// +#define UDMA_CH25_SSPI_RX 0x00000019 +#define UDMA_CH25_I2CA0_RX 0x00010019 +#define UDMA_CH25_SW 0x00030019 + + +// +// Channel 26 +// +#define UDMA_CH26_SSPI_TX 0x0000001A +#define UDMA_CH26_I2CA0_TX 0x0001001A +#define UDMA_CH26_SW 0x0003001A + + +// +// Channel 27 +// +#define UDMA_CH27_GPIOA0 0x0001001B +#define UDMA_CH27_SW 0x0003001B + + +// +// Channel 28 +// +#define UDMA_CH28_GPIOA1 0x0001001C +#define UDMA_CH28_SW 0x0003001C + + +// +// Channel 29 +// +#define UDMA_CH29_GPIOA4 0x0000001D +#define UDMA_CH29_SW 0x0003001D + + +// +// Channel 30 +// +#define UDMA_CH30_GSPI_RX 0x0000001E +#define UDMA_CH30_SDHOST_RX 0x0001001E +#define UDMA_CH30_I2CA0_RX 0x0002001E +#define UDMA_CH30_SW 0x0003001E + + +// +// Channel 31 +// +#define UDMA_CH31_GSPI_TX 0x0000001F +#define UDMA_CH31_SDHOST_TX 0x0001001F +#define UDMA_CH31_I2CA0_RX 0x0002001F +#define UDMA_CH31_SW 0x0003001F + +//***************************************************************************** +// +// The following are defines for the Micro Direct Memory Access (uDMA) offsets. +// +//***************************************************************************** +#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void uDMAEnable(void); +extern void uDMADisable(void); +extern unsigned long uDMAErrorStatusGet(void); +extern void uDMAErrorStatusClear(void); +extern void uDMAChannelEnable(unsigned long ulChannelNum); +extern void uDMAChannelDisable(unsigned long ulChannelNum); +extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum); +extern void uDMAControlBaseSet(void *pControlTable); +extern void *uDMAControlBaseGet(void); +extern void *uDMAControlAlternateBaseGet(void); +extern void uDMAChannelRequest(unsigned long ulChannelNum); +extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum, + unsigned long ulAttr); +extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum, + unsigned long ulAttr); +extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum); +extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex, + unsigned long ulControl); +extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex, + unsigned long ulMode, void *pvSrcAddr, + void *pvDstAddr, + unsigned long ulTransferSize); +extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum, + unsigned ulTaskCount, void *pvTaskList, + unsigned long ulIsPeriphSG); +extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex); +extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex); +extern void uDMAIntRegister(unsigned long ulIntChannel, + void (*pfnHandler)(void)); +extern void uDMAIntUnregister(unsigned long ulIntChannel); +extern unsigned long uDMAIntStatus(void); +extern void uDMAIntClear(unsigned long ulChanMask); +extern void uDMAChannelAssign(unsigned long ulMapping); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UDMA_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/utils.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/utils.c new file mode 100644 index 000000000..918a29cca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/utils.c @@ -0,0 +1,109 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// utils.c +// +// Utility APIs +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup Utils_api +//! @{ +// +//***************************************************************************** +#include "utils.h" + + +//***************************************************************************** +// +//! Provides a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! This function provides a means of generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! The loop takes 3 cycles/loop. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) || defined(DOXYGEN) +void +UtilsDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne.n UtilsDelay\n"); +} +#endif + +#if defined(gcc) +void __attribute__((naked)) +UtilsDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne UtilsDelay\n" + " bx lr"); +} +#endif + +// +// For CCS implement this function in pure assembly. This prevents the TI +// compiler from doing funny things with the optimizer. +// +#if defined(ccs) + __asm(" .sect \".text:UtilsDelay\"\n" + " .clink\n" + " .thumbfunc UtilsDelay\n" + " .thumb\n" + " .global UtilsDelay\n" + "UtilsDelay:\n" + " subs r0, #1\n" + " bne.n UtilsDelay\n" + " bx lr\n"); +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/utils.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/utils.h new file mode 100644 index 000000000..bbbdac9f2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/utils.h @@ -0,0 +1,76 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// utils.h +// +// Prototypes and macros for utility APIs +// +//***************************************************************************** + +#ifndef __UTILS_H__ +#define __UTILS_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UtilsDelay(unsigned long ulCount); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif //__UTILS_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/version.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/version.h new file mode 100644 index 000000000..d74114f2c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/version.h @@ -0,0 +1,77 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// version.h +// +// Contains Driverlib version details +// +//***************************************************************************** + +#ifndef __DRIVERLIB_VERSION_H__ +#define __DRIVERLIB_VERSION_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#define DRIVERLIB_MAJOR_VERSION_NUM 1 +#define DRIVERLIB_MINOR_VERSION_NUM 50 +#define DRIVERLIB_PATCH_VERSION_NUM 3_1 +#define DRIVERLIB_BUILD_VERSION_NUM 00 +#define DRIVERLIB_RELEASE_DAY 30 +#define DRIVERLIB_RELEASE_MONTH 3 +#define DRIVERLIB_RELEASE_YEAR 2016 + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_VERSION_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/wdt.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/wdt.h new file mode 100644 index 000000000..573cddb52 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/driverlib/wdt.h @@ -0,0 +1,87 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// wdt.h - Prototypes for the Watchdog Timer API +// +// + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallEnable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/asmdefs.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/asmdefs.h new file mode 100644 index 000000000..262a0a3b4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/asmdefs.h @@ -0,0 +1,231 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +// asmdefs.h - Macros to allow assembly code be portable among toolchains. +// +//***************************************************************************** + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for code_red. +// +//***************************************************************************** +#ifdef codered + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // codered + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef ewarm + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler nmenonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // ewarm + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(gcc) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // gcc + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#ifdef rvmdk + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler nmenonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // rvmdk + +//***************************************************************************** +// +// The defines required for Sourcery G++. +// +//***************************************************************************** +#if defined(sourcerygxx) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // sourcerygxx + +#endif // __ASMDEF_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_adc.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_adc.h new file mode 100644 index 000000000..f75d1ddb0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_adc.h @@ -0,0 +1,890 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets. +// +//***************************************************************************** +#define ADC_O_ADC_CTRL 0x00000000 // ADC control register. +#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting +#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting +#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting +#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting +#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting +#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting +#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting +#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting +#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable + // register +#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable + // register +#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable + // register +#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable + // register +#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable + // register +#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable + // register +#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable + // register +#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable + // register +#define ADC_O_adc_ch0_irq_status \ + 0x00000044 // Channel 0 interrupt status + // register + +#define ADC_O_adc_ch1_irq_status \ + 0x00000048 // Channel 1 interrupt status + // register + +#define ADC_O_adc_ch2_irq_status \ + 0x0000004C + +#define ADC_O_adc_ch3_irq_status \ + 0x00000050 // Channel 3 interrupt status + // register + +#define ADC_O_adc_ch4_irq_status \ + 0x00000054 // Channel 4 interrupt status + // register + +#define ADC_O_adc_ch5_irq_status \ + 0x00000058 + +#define ADC_O_adc_ch6_irq_status \ + 0x0000005C // Channel 6 interrupt status + // register + +#define ADC_O_adc_ch7_irq_status \ + 0x00000060 // Channel 7 interrupt status + // register + +#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register +#define ADC_O_adc_timer_configuration \ + 0x00000068 // ADC timer configuration register + +#define ADC_O_adc_timer_current_count \ + 0x00000070 // ADC timer current count register + +#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register +#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register +#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register +#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register +#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register +#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register +#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register +#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register +#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register +#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status + // register +#define ADC_O_adc_ch2_fifo_lvl 0x0000009C +#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status + // register +#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status + // register +#define ADC_O_adc_ch5_fifo_lvl 0x000000A8 +#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status + // register +#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status + // register + +#define ADC_O_ADC_CH_ENABLE 0x000000B8 + +//****************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ADC_CTRL register. +// +//****************************************************************************** +#define ADC_ADC_CTRL_adc_cap_scale \ + 0x00000020 // ADC CAP SCALE. + +#define ADC_ADC_CTRL_adc_buf_bypass \ + 0x00000010 // ADC ANA CIO buffer bypass. + // Signal is modelled in ANA TOP. + // When '1': ADC buffer is bypassed. + +#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1: + // ADC buffer is enabled. +#define ADC_ADC_CTRL_adc_core_en \ + 0x00000004 // ANA ADC core en. This signal act + // as glbal enable to ADC CIO. When + // 1: ADC core is enabled. + +#define ADC_ADC_CTRL_adc_soft_reset \ + 0x00000002 // ADC soft reset. When '1' : reset + // ADC internal logic. + +#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC + // module is enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_gain register. +// +//****************************************************************************** +#define ADC_adc_ch0_gain_adc_channel0_gain_M \ + 0x00000003 // gain setting for ADC channel 0. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch0_gain_adc_channel0_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_gain register. +// +//****************************************************************************** +#define ADC_adc_ch1_gain_adc_channel1_gain_M \ + 0x00000003 // gain setting for ADC channel 1. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch1_gain_adc_channel1_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_gain register. +// +//****************************************************************************** +#define ADC_adc_ch2_gain_adc_channel2_gain_M \ + 0x00000003 // gain setting for ADC channel 2. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch2_gain_adc_channel2_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_gain register. +// +//****************************************************************************** +#define ADC_adc_ch3_gain_adc_channel3_gain_M \ + 0x00000003 // gain setting for ADC channel 3. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch3_gain_adc_channel3_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_gain register. +// +//****************************************************************************** +#define ADC_adc_ch4_gain_adc_channel4_gain_M \ + 0x00000003 // gain setting for ADC channel 4 + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch4_gain_adc_channel4_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_gain register. +// +//****************************************************************************** +#define ADC_adc_ch5_gain_adc_channel5_gain_M \ + 0x00000003 // gain setting for ADC channel 5. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch5_gain_adc_channel5_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_gain register. +// +//****************************************************************************** +#define ADC_adc_ch6_gain_adc_channel6_gain_M \ + 0x00000003 // gain setting for ADC channel 6 + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch6_gain_adc_channel6_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_gain register. +// +//****************************************************************************** +#define ADC_adc_ch7_gain_adc_channel7_gain_M \ + 0x00000003 // gain setting for ADC channel 7. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch7_gain_adc_channel7_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_dma_mode_en register. +// +//****************************************************************************** +#define ADC_adc_dma_mode_en_DMA_MODEenable_M \ + 0x000000FF // this register enable DMA mode. + // when '1' respective ADC channel + // is enabled for DMA. When '0' only + // interrupt mode is enabled. Bit 0: + // channel 0 DMA mode enable. Bit 1: + // channel 1 DMA mode enable. Bit 2: + // channel 2 DMA mode enable. Bit 3: + // channel 3 DMA mode enable. bit 4: + // channel 4 DMA mode enable. bit 5: + // channel 5 DMA mode enable. bit 6: + // channel 6 DMA mode enable. bit 7: + // channel 7 DMA mode enable. + +#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_timer_configuration register. +// +//****************************************************************************** +#define ADC_adc_timer_configuration_timeren \ + 0x02000000 // when '1' timer is enabled. + +#define ADC_adc_timer_configuration_timerreset \ + 0x01000000 // when '1' reset timer. + +#define ADC_adc_timer_configuration_timercount_M \ + 0x00FFFFFF // Timer count configuration. 17 + // bit counter is supported. Other + // MSB's are redundent. + +#define ADC_adc_timer_configuration_timercount_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_timer_current_count register. +// +//****************************************************************************** +#define ADC_adc_timer_current_count_timercurrentcount_M \ + 0x0001FFFF // Timer count configuration + +#define ADC_adc_timer_current_count_timercurrentcount_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel0FIFODATA register. +// +//****************************************************************************** +#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel1FIFODATA register. +// +//****************************************************************************** +#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel2FIFODATA register. +// +//****************************************************************************** +#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel3FIFODATA register. +// +//****************************************************************************** +#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel4FIFODATA register. +// +//****************************************************************************** +#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel5FIFODATA register. +// +//****************************************************************************** +#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel6FIFODATA register. +// +//****************************************************************************** +#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel7FIFODATA register. +// +//****************************************************************************** +#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0 + + + +#endif // __HW_ADC_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_aes.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_aes.h new file mode 100644 index 000000000..44ef89554 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_aes.h @@ -0,0 +1,804 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_AES_H__ +#define __HW_AES_H__ + +//***************************************************************************** +// +// The following are defines for the AES_P register offsets. +// +//***************************************************************************** +#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third + // key +#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit + // key) / CBC-MAC third key (MSW) +#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC + // third key (LSW) +#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit + // key) / CBC-MAC third key +#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key / + // Hash Key input +#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit + // key) + CCM/CBC-MAC second key + // (MSW) / Hash Key input (MSW) +#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key + // (LSW) / Hash Key input (LSW) +#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key / + // Hash Key input +#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key) +#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key) +#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key) +#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key) +#define AES_O_KEY1_2 0x00000030 // Key +#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key) +#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key) +#define AES_O_KEY1_1 0x0000003C // Key +#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input + // (LSW) +#define AES_O_IV_IN_1 0x00000044 // Initialization vector input +#define AES_O_IV_IN_2 0x00000048 // Initialization vector input +#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input + // (MSW) +#define AES_O_CTRL 0x00000050 // register determines the mode of + // operation of the AES Engine +#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers + // (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. +#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers + // (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. +#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The + // authentication length register + // store the authentication data + // length in bytes for combined + // modes only (GCM or CCM) Supported + // AAD-lengths for CCM are from 0 to + // (2^16 - 2^8) bytes. For GCM any + // value up to (2^32 - 1) bytes can + // be used. Once processing with + // this context is started@@ this + // length decrements to zero. A + // write to this register triggers + // the engine to start using this + // context for GCM and CCM. For XTS + // this register is optionally used + // to load ‘j’. Loading of ‘j’ is + // only required if ‘j’ != 0. ‘j’ is + // a 28-bit value and must be + // written to bits [31-4] of this + // register. ‘j’ represents the + // sequential number of the 128-bit + // block inside the data unit. For + // the first block in a unit@@ this + // value is zero. It is not required + // to provide a ‘j’ for each new + // data block within a unit. Note + // that it is possible to start with + // a ‘j’ unequal to zero; refer to + // Table 4 for more details. For a + // Host read operation@@ these + // registers return all-zeroes. +#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write + // plaintext/ciphertext (MSW) +#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write + // plaintext/ciphertext +#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write + // plaintext/ciphertext +#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write + // plaintext/ciphertext (LSW) +#define AES_O_TAG_OUT_0 0x00000070 +#define AES_O_TAG_OUT_1 0x00000074 +#define AES_O_TAG_OUT_2 0x00000078 +#define AES_O_TAG_OUT_3 0x0000007C +#define AES_O_REVISION 0x00000080 // Register AES_REVISION +#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This + // register configures the DMA + // signals and controls the IDLE and + // reset logic +#define AES_O_SYSSTATUS 0x00000088 +#define AES_O_IRQSTATUS 0x0000008C // This register indicates the + // interrupt status. If one of the + // interrupt bits is set the + // interrupt output will be asserted +#define AES_O_IRQENABLE 0x00000090 // This register contains an enable + // bit for each unique interrupt + // generated by the module. It + // matches the layout of + // AES_IRQSTATUS register. An + // interrupt is enabled when the bit + // in this register is set to ‘1’. + // An interrupt that is enabled is + // propagated to the SINTREQUEST_x + // output. All interrupts need to be + // enabled explicitly by writing + // this register. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_6 register. +// +//****************************************************************************** +#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_6_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_7 register. +// +//****************************************************************************** +#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_7_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_4 register. +// +//****************************************************************************** +#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_4_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_5 register. +// +//****************************************************************************** +#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_5_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_2 register. +// +//****************************************************************************** +#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_3 register. +// +//****************************************************************************** +#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_3_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_0 register. +// +//****************************************************************************** +#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_1 register. +// +//****************************************************************************** +#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_6 register. +// +//****************************************************************************** +#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_6_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_7 register. +// +//****************************************************************************** +#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_7_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_4 register. +// +//****************************************************************************** +#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_4_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_5 register. +// +//****************************************************************************** +#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_5_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_2 register. +// +//****************************************************************************** +#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_3 register. +// +//****************************************************************************** +#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_3_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_0 register. +// +//****************************************************************************** +#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_1 register. +// +//****************************************************************************** +#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_0 register. +// +//****************************************************************************** +#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_0_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_1 register. +// +//****************************************************************************** +#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_2 register. +// +//****************************************************************************** +#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_3 register. +// +//****************************************************************************** +#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_CTRL register. +// +//****************************************************************************** +#define AES_CTRL_CONTEXT_READY \ + 0x80000000 // If ‘1’@@ this read-only status + // bit indicates that the context + // data registers can be overwritten + // and the host is permitted to + // write the next context. + +#define AES_CTRL_SVCTXTRDY \ + 0x40000000 // If ‘1’@@ this read-only status + // bit indicates that an AES + // authentication TAG and/or IV + // block(s) is/are available for the + // host to retrieve. This bit is + // only asserted if the + // ‘save_context’ bit is set to ‘1’. + // The bit is mutual exclusive with + // the ‘context_ready’ bit. + +#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate + // that an authentication TAG or + // result IV needs to be stored as a + // result context. If this bit is + // set@@ context output DMA and/or + // interrupt will be asserted if the + // operation is finished and related + // signals are enabled. +#define AES_CTRL_CCM_M 0x01C00000 // Defines “Mâ€? that indicated the + // length of the authentication + // field for CCM operations; the + // authentication field length + // equals two times (the value of + // CCM-M plus one). Note that the + // AES Engine always returns a + // 128-bit authentication field@@ of + // which the M least significant + // bytes are valid. All values are + // supported. +#define AES_CTRL_CCM_S 22 +#define AES_CTRL_CCM_L_M 0x00380000 // Defines “Lâ€? that indicated the + // width of the length field for CCM + // operations; the length field in + // bytes equals the value of CMM-L + // plus one. Supported values for L + // are (programmed value): 2 (1)@@ 4 + // (3) and 8 (7). +#define AES_CTRL_CCM_L_S 19 +#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a + // combined mode@@ using AES for + // both authentication and + // encryption. No additional mode + // selection is required. 0 Other + // mode selected 1 ccm mode selected +#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is + // a combined mode@@ using the + // Galois field multiplier GF(2^128) + // for authentication and AES-CTR + // mode for encryption@@ the bits + // specify the GCM mode. 0x0 No + // operation 0x1 GHASH with H loaded + // and Y0-encrypted forced to zero + // 0x2 GHASH with H loaded and + // Y0-encrypted calculated + // internally 0x3 Autonomous GHASH + // (both H and Y0-encrypted + // calculated internally) +#define AES_CTRL_GCM_S 16 +#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the + // Direction bit must be set to ‘1’ + // for this mode. 0 Other mode + // selected 1 cbcmac mode selected +#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the + // AES key size must be set to + // 128-bit for this mode. 0 Other + // mode selected 1 f9 selected +#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the + // AES key size must be set to + // 128-bit for this mode. 0 Other + // mode selected 1 f8 selected +#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected; + // the bits specify the XTS mode.01 + // = Previous/intermediate tweak + // value and ‘j’ loaded (value is + // loaded via IV@@ j is loaded via + // the AAD length register) 0x0 No + // operation 0x1 + // Previous/intermediate tweak value + // and ‘j’ loaded (value is loaded + // via IV@@ j is loaded via the AAD + // length register) 0x2 Key2@@ i and + // j loaded (i is loaded via IV@@ j + // is loaded via the AAD length + // register) 0x3 Key2 and i loaded@@ + // j=0 (i is loaded via IV) +#define AES_CTRL_XTS_S 11 +#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback + // mode (CFB128) is selected. 0 + // other mode selected 1 cfb + // selected +#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM) + // is selected@@ this is a counter + // mode with a 16-bit wide counter. + // 0 Other mode selected. 1 ICM mode + // selected +#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for + // AES-CTR mode 0x0 Counter is 32 + // bits 0x1 Counter is 64 bits 0x2 + // Counter is 128 bits 0x3 Counter + // is 192 bits +#define AES_CTRL_CTR_WIDTH_S 7 +#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for + // GCM and CCM@@ when + // encryption/decryption is + // required. 0 Other mode selected 1 + // Counter mode +#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc + // mode +#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is + // 128 bits. 0x2 Key is 192 bits 0x3 + // Key is 256 +#define AES_CTRL_KEY_SIZE_S 3 +#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt + // operation is performed. If set to + // ‘0’ a decrypt operation is + // performed. Read 0 decryption is + // selected Read 1 Encryption is + // selected +#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status + // bit indicates that the 16-byte + // input buffer is empty@@ and the + // host is permitted to write the + // next block of data. +#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status + // bit indicates that an AES output + // block is available for the host + // to retrieve. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_C_LENGTH_0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_C_LENGTH_1 register. +// +//****************************************************************************** +#define AES_C_LENGTH_1_LENGTH_M \ + 0x1FFFFFFF // Data length (MSW) length + // registers (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. + +#define AES_C_LENGTH_1_LENGTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_AUTH_LENGTH register. +// +//****************************************************************************** +#define AES_AUTH_LENGTH_AUTH_M \ + 0xFFFFFFFF // data + +#define AES_AUTH_LENGTH_AUTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_0 register. +// +//****************************************************************************** +#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_0_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_1 register. +// +//****************************************************************************** +#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_2 register. +// +//****************************************************************************** +#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_3 register. +// +//****************************************************************************** +#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register. +// +//****************************************************************************** +#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_0_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register. +// +//****************************************************************************** +#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_1_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register. +// +//****************************************************************************** +#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_2_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register. +// +//****************************************************************************** +#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW) +#define AES_TAG_OUT_3_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_REVISION register. +// +//****************************************************************************** +#define AES_REVISION_SCHEME_M 0xC0000000 +#define AES_REVISION_SCHEME_S 30 +#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define AES_REVISION_FUNC_S 16 +#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by + // IP design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define AES_REVISION_R_RTL_S 11 +#define AES_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X)@@ maintained + // by IP specification owner. X + // changes ONLY when: (1) There is a + // major feature addition. An + // example would be adding Master + // Mode to Utopia Level2. The Func + // field (or Class/Type in old PID + // format) will remain the same. X + // does NOT change due to: (1) Bug + // fixes (2) Change in feature + // parameters. + +#define AES_REVISION_X_MAJOR_S 8 +#define AES_REVISION_CUSTOM_M 0x000000C0 +#define AES_REVISION_CUSTOM_S 6 +#define AES_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y)@@ maintained + // by IP specification owner. Y + // changes ONLY when: (1) Features + // are scaled (up or down). + // Flexibility exists in that this + // feature scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R@@ S@@ X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless@@ the spec tracks + // the IP bugs. An RTL release (say + // for silicon PG1.1) that occurs + // due to bug fix should document + // the corresponding spec number + // (X.Y.S) in its release notes. + +#define AES_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSCONFIG register. +// +//****************************************************************************** +#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \ + 0x00000200 // If set to '1' the two context + // out requests + // (dma_req_context_out_en@@ Bit [8] + // above@@ and context_out interrupt + // enable@@ Bit [3] of AES_IRQENABLE + // register) are mapped on the + // corresponding data output request + // bit. In this case@@ the original + // ‘context out’ bit values are + // ignored. + +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ + 0x00000100 // If set to ‘1’@@ the DMA context + // output request is enabled (for + // context data out@@ e.g. TAG for + // authentication modes). 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // If set to ‘1’@@ the DMA context + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // If set to ‘1’@@ the DMA output + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // If set to ‘1’@@ the DMA input + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSSTATUS register. +// +//****************************************************************************** +#define AES_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQSTATUS register. +// +//****************************************************************************** +#define AES_IRQSTATUS_CONTEXT_OUT \ + 0x00000008 // This bit indicates + // authentication tag (and IV) + // interrupt(s) is/are active and + // triggers the interrupt output. + +#define AES_IRQSTATUS_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define AES_IRQSTATUS_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQENABLE register. +// +//****************************************************************************** +#define AES_IRQENABLE_CONTEXT_OUT \ + 0x00000008 // This bit indicates + // authentication tag (and IV) + // interrupt(s) is/are active and + // triggers the interrupt output. + +#define AES_IRQENABLE_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define AES_IRQENABLE_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + + + + +#endif // __HW_AES_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_apps_config.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_apps_config.h new file mode 100644 index 000000000..db2d0eeee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_apps_config.h @@ -0,0 +1,749 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __HW_APPS_CONFIG_H__ +#define __HW_APPS_CONFIG_H__ + +//***************************************************************************** +// +// The following are defines for the APPS_CONFIG register offsets. +// +//***************************************************************************** +#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \ + 0x00000000 // Patch trap address Register + // array + +#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \ + 0x00000078 + +#define APPS_CONFIG_O_FAULT_STATUS_REG \ + 0x0000007C + +#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \ + 0x00000080 + +#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \ + 0x00000084 + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK \ + 0x0000008C + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \ + 0x00000090 + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \ + 0x00000094 + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \ + 0x00000098 + +#define APPS_CONFIG_O_DMA_DONE_INT_ACK \ + 0x0000009C + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \ + 0x000000A0 + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \ + 0x000000A4 + +#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \ + 0x000000A8 + +#define APPS_CONFIG_O_RESERVD_REG_0 \ + 0x000000AC + +#define APPS_CONFIG_O_GPT_TRIG_SEL \ + 0x000000B0 + +#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \ + 0x000000B4 + +#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \ + 0x000000B8 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \ + 0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus + // fault is generated for the + // address + // PATCH_TRAP_ADDR_REG[n][31:0] from + // Idcode bus. The exception routine + // should take care to jump to the + // location where the patch + // correspond to this address is + // kept. + +#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_PATCH_TRAP_EN_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \ + 0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus + // fault is generated for the + // address PATCH_TRAP_ADD[n][31:0] + // from Idcode bus. The exception + // routine should take care to jump + // to the location where the patch + // correspond to this address is + // kept. + +#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_FAULT_STATUS_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \ + 0x0000003E // This field shows because of + // which patch trap address the + // bus_fault is generated. If the + // PATCH_ERR bit is set, then it + // means the bus fault is generated + // because of + // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX] + +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1 +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \ + 0x00000001 // This bit is set when there is a + // bus fault because of patched + // address access to the Apps boot + // rom. Write 0 to clear this + // register. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \ + 0x00000001 // This bit is set when there is a + // an error in memss write access. + // And the address causing this + // error is captured in + // MEMSS_ERR_ADDR_REG. To capture + // the next error address one have + // to clear this bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \ + 0x0000F000 // 1= disable corresponding + // interrupt;0 = interrupt enabled + // bit 14: ADC channel 7 interrupt + // enable/disable bit 13: ADC + // channel 5 interrupt + // enable/disable bit 12: ADC + // channel 3 interrupt + // enable/disable bit 11: ADC + // channel 1 interrupt + // enable/disable + +#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \ + 0x00000800 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \ + 0x00000400 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \ + 0x00000200 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \ + 0x00000100 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \ + 0x00000080 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \ + 0x00000040 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \ + 0x00000020 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \ + 0x00000010 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \ + 0x00000008 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \ + 0x00000004 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \ + 0x00000002 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \ + 0x00000001 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \ + 0x0000F000 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect bit 14: ADC channel 7 DMA + // Done IRQ bit 13: ADC channel 5 + // DMA Done IRQ bit 12: ADC channel + // 3 DMA Done IRQ bit 11: ADC + // channel 1 DMA Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \ + 0x00000800 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \ + 0x00000400 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \ + 0x00000200 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \ + 0x00000100 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000080 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000040 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000020 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000010 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000008 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000004 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \ + 0x00000002 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \ + 0x00000001 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \ + 0x0000F000 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect bit 14: ADC channel 7 DMA + // Done IRQ mask bit 13: ADC channel + // 5 DMA Done IRQ mask bit 12: ADC + // channel 3 DMA Done IRQ mask bit + // 11: ADC channel 1 DMA Done IRQ + // mask + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000800 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000400 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \ + 0x00000200 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \ + 0x00000100 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000080 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000040 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000020 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000010 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000008 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000004 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000002 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000001 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 or 0 to clear all + // DMA_DONE interrupt; + +#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_ACK register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \ + 0x0000F000 // write 1 to clear corresponding + // interrupt; 0 = no effect; bit 14: + // ADC channel 7 DMA Done IRQ bit + // 13: ADC channel 5 DMA Done IRQ + // bit 12: ADC channel 3 DMA Done + // IRQ bit 11: ADC channel 1 DMA + // Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12 +#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \ + 0x00000800 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \ + 0x00000400 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \ + 0x00000200 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \ + 0x00000100 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \ + 0x00000080 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \ + 0x00000040 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \ + 0x00000020 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \ + 0x00000010 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \ + 0x00000008 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \ + 0x00000004 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \ + 0x00000002 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \ + 0x00000001 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \ + 0x0000F000 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask bit 14: ADC + // channel 7 DMA Done IRQ bit 13: + // ADC channel 5 DMA Done IRQ bit + // 12: ADC channel 3 DMA Done IRQ + // bit 11: ADC channel 1 DMA Done + // IRQ + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12 +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000800 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000400 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \ + 0x00000200 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \ + 0x00000100 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000080 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000040 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000020 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000010 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000008 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000004 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000002 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000001 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \ + 0x0000F000 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive bit 14: ADC channel 7 + // DMA Done IRQ bit 13: ADC channel + // 5 DMA Done IRQ bit 12: ADC + // channel 3 DMA Done IRQ bit 11: + // ADC channel 1 DMA Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12 +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \ + 0x00000800 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \ + 0x00000400 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \ + 0x00000200 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \ + 0x00000100 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000080 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000040 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000020 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000010 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000008 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000004 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \ + 0x00000002 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \ + 0x00000001 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \ + 0x00000001 // Write 1 to clear the LSB of + // FAULT_STATUS_REG + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_RESERVD_REG_0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_GPT_TRIG_SEL register. +// +//****************************************************************************** +#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \ + 0x000000FF // This bit is implemented for GPT + // trigger mode select. GPT IP + // support 2 modes: RTC mode and + // external trigger. When this bit + // is set to logic '1': enable + // external trigger mode for APPS + // GPT CP0 and CP1 pin. bit 0: when + // set '1' enable external GPT + // trigger 0 on GPIO0 CP0 pin else + // RTC mode is selected. bit 1: when + // set '1' enable external GPT + // trigger 1 on GPIO0 CP1 pin else + // RTC mode is selected. bit 2: when + // set '1' enable external GPT + // trigger 2 on GPIO1 CP0 pin else + // RTC mode is selected. bit 3: when + // set '1' enable external GPT + // trigger 3 on GPIO1 CP1 pin else + // RTC mode is selected. bit 4: when + // set '1' enable external GPT + // trigger 4 on GPIO2 CP0 pin else + // RTC mode is selected. bit 5: when + // set '1' enable external GPT + // trigger 5 on GPIO2 CP1 pin else + // RTC mode is selected. bit 6: when + // set '1' enable external GPT + // trigger 6 on GPIO3 CP0 pin else + // RTC mode is selected. bit 7: when + // set '1' enable external GPT + // trigger 7 on GPIO3 CP1 pin else + // RTC mode is selected. + +#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \ + 0x00000007 // Capture data from d2d_spare pads + +#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \ + 0x00000007 // Send data to d2d_spare pads - + // eventually this will get + // registered in top die + +#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0 + + + +#endif // __HW_APPS_CONFIG_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_apps_rcm.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_apps_rcm.h new file mode 100644 index 000000000..8645df085 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_apps_rcm.h @@ -0,0 +1,1508 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_APPS_RCM_H__ +#define __HW_APPS_RCM_H__ + +//***************************************************************************** +// +// The following are defines for the APPS_RCM register offsets. +// +//***************************************************************************** +#define APPS_RCM_O_CAMERA_CLK_GEN \ + 0x00000000 + +#define APPS_RCM_O_CAMERA_CLK_GATING \ + 0x00000004 + +#define APPS_RCM_O_CAMERA_SOFT_RESET \ + 0x00000008 + +#define APPS_RCM_O_MCASP_CLK_GATING \ + 0x00000014 + +#define APPS_RCM_O_MCASP_SOFT_RESET \ + 0x00000018 + +#define APPS_RCM_O_MMCHS_CLK_GEN \ + 0x00000020 + +#define APPS_RCM_O_MMCHS_CLK_GATING \ + 0x00000024 + +#define APPS_RCM_O_MMCHS_SOFT_RESET \ + 0x00000028 + +#define APPS_RCM_O_MCSPI_A1_CLK_GEN \ + 0x0000002C + +#define APPS_RCM_O_MCSPI_A1_CLK_GATING \ + 0x00000030 + +#define APPS_RCM_O_MCSPI_A1_SOFT_RESET \ + 0x00000034 + +#define APPS_RCM_O_MCSPI_A2_CLK_GEN \ + 0x00000038 + +#define APPS_RCM_O_MCSPI_A2_CLK_GATING \ + 0x00000040 + +#define APPS_RCM_O_MCSPI_A2_SOFT_RESET \ + 0x00000044 + +#define APPS_RCM_O_UDMA_A_CLK_GATING \ + 0x00000048 + +#define APPS_RCM_O_UDMA_A_SOFT_RESET \ + 0x0000004C + +#define APPS_RCM_O_GPIO_A_CLK_GATING \ + 0x00000050 + +#define APPS_RCM_O_GPIO_A_SOFT_RESET \ + 0x00000054 + +#define APPS_RCM_O_GPIO_B_CLK_GATING \ + 0x00000058 + +#define APPS_RCM_O_GPIO_B_SOFT_RESET \ + 0x0000005C + +#define APPS_RCM_O_GPIO_C_CLK_GATING \ + 0x00000060 + +#define APPS_RCM_O_GPIO_C_SOFT_RESET \ + 0x00000064 + +#define APPS_RCM_O_GPIO_D_CLK_GATING \ + 0x00000068 + +#define APPS_RCM_O_GPIO_D_SOFT_RESET \ + 0x0000006C + +#define APPS_RCM_O_GPIO_E_CLK_GATING \ + 0x00000070 + +#define APPS_RCM_O_GPIO_E_SOFT_RESET \ + 0x00000074 + +#define APPS_RCM_O_WDOG_A_CLK_GATING \ + 0x00000078 + +#define APPS_RCM_O_WDOG_A_SOFT_RESET \ + 0x0000007C + +#define APPS_RCM_O_UART_A0_CLK_GATING \ + 0x00000080 + +#define APPS_RCM_O_UART_A0_SOFT_RESET \ + 0x00000084 + +#define APPS_RCM_O_UART_A1_CLK_GATING \ + 0x00000088 + +#define APPS_RCM_O_UART_A1_SOFT_RESET \ + 0x0000008C + +#define APPS_RCM_O_GPT_A0_CLK_GATING \ + 0x00000090 + +#define APPS_RCM_O_GPT_A0_SOFT_RESET \ + 0x00000094 + +#define APPS_RCM_O_GPT_A1_CLK_GATING \ + 0x00000098 + +#define APPS_RCM_O_GPT_A1_SOFT_RESET \ + 0x0000009C + +#define APPS_RCM_O_GPT_A2_CLK_GATING \ + 0x000000A0 + +#define APPS_RCM_O_GPT_A2_SOFT_RESET \ + 0x000000A4 + +#define APPS_RCM_O_GPT_A3_CLK_GATING \ + 0x000000A8 + +#define APPS_RCM_O_GPT_A3_SOFT_RESET \ + 0x000000AC + +#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \ + 0x000000B0 + +#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \ + 0x000000B4 + +#define APPS_RCM_O_CRYPTO_CLK_GATING \ + 0x000000B8 + +#define APPS_RCM_O_CRYPTO_SOFT_RESET \ + 0x000000BC + +#define APPS_RCM_O_MCSPI_S0_CLK_GATING \ + 0x000000C8 + +#define APPS_RCM_O_MCSPI_S0_SOFT_RESET \ + 0x000000CC + +#define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \ + 0x000000D0 + +#define APPS_RCM_O_I2C_CLK_GATING \ + 0x000000D8 + +#define APPS_RCM_O_I2C_SOFT_RESET \ + 0x000000DC + +#define APPS_RCM_O_APPS_LPDS_REQ \ + 0x000000E4 + +#define APPS_RCM_O_APPS_TURBO_REQ \ + 0x000000EC + +#define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \ + 0x00000108 + +#define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \ + 0x0000010C + +#define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \ + 0x00000110 + +#define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \ + 0x00000114 + +#define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \ + 0x00000118 + +#define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \ + 0x00000120 + +#define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \ + 0x00000124 + + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of Camera func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_CAMERA_CLK_GEN_NU1_M \ + 0x000000F8 + +#define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3 +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of Camera func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable camera clk during + // deep-sleep mode + +#define APPS_RCM_CAMERA_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable camera clk during + // sleep mode ; 0- Disable camera + // clk during sleep mode + +#define APPS_RCM_CAMERA_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable camera clk during run + // mode ; 0- Disable camera clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \ + 0x00000002 // 1 - Camera clocks/resets are + // enabled ; 0 - Camera + // clocks/resets are disabled + +#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for Camera-core + // ; 0 - De-assert reset for + // Camera-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCASP_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCASP clk during + // deep-sleep mode + +#define APPS_RCM_MCASP_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCASP_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCASP clk during sleep + // mode ; 0- Disable MCASP clk + // during sleep mode + +#define APPS_RCM_MCASP_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCASP_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCASP clk during run + // mode ; 0- Disable MCASP clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \ + 0x00000002 // 1 - MCASP Clocks/resets are + // enabled ; 0 - MCASP Clocks/resets + // are disabled + +#define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for MCASP-core + // ; 0 - De-assert reset for + // MCASP-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MMCHS func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_MMCHS_CLK_GEN_NU1_M \ + 0x000000F8 + +#define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3 +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MMCHS func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MMCHS clk during + // deep-sleep mode + +#define APPS_RCM_MMCHS_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MMCHS clk during sleep + // mode ; 0- Disable MMCHS clk + // during sleep mode + +#define APPS_RCM_MMCHS_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MMCHS clk during run + // mode ; 0- Disable MMCHS clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \ + 0x00000002 // 1 - MMCHS Clocks/resets are + // enabled ; 0 - MMCHS Clocks/resets + // are disabled + +#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for MMCHS-core + // ; 0 - De-assert reset for + // MMCHS-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud clk + // for MCSPI_A1 ; 1 - PLL divclk is + // used as baud clk for MCSPI_A1. + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11 +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A1 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3 +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A1 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCSPI_A1 clk during + // deep-sleep mode + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCSPI_A1 clk during + // sleep mode ; 0- Disable MCSPI_A1 + // clk during sleep mode + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCSPI_A1 clk during + // run mode ; 0- Disable MCSPI_A1 + // clk during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are + // enabled ; 0 - MCSPI_A1 + // Clocks/Resets are disabled + +#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for + // MCSPI_A1-core ; 0 - De-assert + // reset for MCSPI_A1-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud-clk + // for MCSPI_A2 ; 1 - PLL divclk is + // used as baud-clk for MCSPI_A2 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11 +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A2 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3 +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A2 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCSPI_A2 clk during + // deep-sleep mode + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCSPI_A2 clk during + // sleep mode ; 0- Disable MCSPI_A2 + // clk during sleep mode + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCSPI_A2 clk during + // run mode ; 0- Disable MCSPI_A2 + // clk during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are + // enabled ; 0 - MCSPI_A2 + // Clocks/Resets are disabled + +#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for + // MCSPI_A2-core ; 0 - De-assert + // reset for MCSPI_A2-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UDMA_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UDMA_A clk during + // deep-sleep mode 0 - Disable + // UDMA_A clk during deep-sleep mode + // ; + +#define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UDMA_A clk during + // sleep mode 0 - Disable UDMA_A clk + // during sleep mode ; + +#define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UDMA_A clk during run + // mode 0 - Disable UDMA_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UDMA_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \ + 0x00000002 // 1 - UDMA_A Clocks/Resets are + // enabled ; 0 - UDMA_A + // Clocks/Resets are disabled + +#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for DMA_A ; 0 - + // De-assert reset for DMA_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_A clk during + // deep-sleep mode 0 - Disable + // GPIO_A clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_A clk during + // sleep mode 0 - Disable GPIO_A clk + // during sleep mode ; + +#define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_A clk during run + // mode 0 - Disable GPIO_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_A Clocks/Resets are + // enabled ; 0 - GPIO_A + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_A ; 0 + // - De-assert reset for GPIO_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_B_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_B clk during + // deep-sleep mode 0 - Disable + // GPIO_B clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_B clk during + // sleep mode 0 - Disable GPIO_B clk + // during sleep mode ; + +#define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_B clk during run + // mode 0 - Disable GPIO_B clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_B_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_B Clocks/Resets are + // enabled ; 0 - GPIO_B + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_B ; 0 + // - De-assert reset for GPIO_B + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_C_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_C clk during + // deep-sleep mode 0 - Disable + // GPIO_C clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_C clk during + // sleep mode 0 - Disable GPIO_C clk + // during sleep mode ; + +#define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_C clk during run + // mode 0 - Disable GPIO_C clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_C_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_C Clocks/Resets are + // enabled ; 0 - GPIO_C + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_C ; 0 + // - De-assert reset for GPIO_C + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_D_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_D clk during + // deep-sleep mode 0 - Disable + // GPIO_D clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_D clk during + // sleep mode 0 - Disable GPIO_D clk + // during sleep mode ; + +#define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_D clk during run + // mode 0 - Disable GPIO_D clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_D_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_D Clocks/Resets are + // enabled ; 0 - GPIO_D + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_D ; 0 + // - De-assert reset for GPIO_D + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_E_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_E clk during + // deep-sleep mode 0 - Disable + // GPIO_E clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_E clk during + // sleep mode 0 - Disable GPIO_E clk + // during sleep mode ; + +#define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_E clk during run + // mode 0 - Disable GPIO_E clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_E_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_E Clocks/Resets are + // enabled ; 0 - GPIO_E + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_E ; 0 + // - De-assert reset for GPIO_E + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_WDOG_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \ + 0x03000000 // "00" - Sysclk ; "01" - REF_CLK + // (38.4 MHz) ; "10/11" - Slow_clk + +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable WDOG_A clk during + // deep-sleep mode 0 - Disable + // WDOG_A clk during deep-sleep mode + // ; + +#define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable WDOG_A clk during + // sleep mode 0 - Disable WDOG_A clk + // during sleep mode ; + +#define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable WDOG_A clk during run + // mode 0 - Disable WDOG_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_WDOG_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \ + 0x00000002 // 1 - WDOG_A Clocks/Resets are + // enabled ; 0 - WDOG_A + // Clocks/Resets are disabled + +#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for WDOG_A ; 0 + // - De-assert reset for WDOG_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UART_A0 clk during + // deep-sleep mode 0 - Disable + // UART_A0 clk during deep-sleep + // mode ; + +#define APPS_RCM_UART_A0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9 +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UART_A0 clk during + // sleep mode 0 - Disable UART_A0 + // clk during sleep mode ; + +#define APPS_RCM_UART_A0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1 +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UART_A0 clk during + // run mode 0 - Disable UART_A0 clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \ + 0x00000002 // 1 - UART_A0 Clocks/Resets are + // enabled ; 0 - UART_A0 + // Clocks/Resets are disabled + +#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for UART_A0 ; 0 + // - De-assert reset for UART_A0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UART_A1 clk during + // deep-sleep mode 0 - Disable + // UART_A1 clk during deep-sleep + // mode ; + +#define APPS_RCM_UART_A1_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9 +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UART_A1 clk during + // sleep mode 0 - Disable UART_A1 + // clk during sleep mode ; + +#define APPS_RCM_UART_A1_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1 +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UART_A1 clk during + // run mode 0 - Disable UART_A1 clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \ + 0x00000002 // 1 - UART_A1 Clocks/Resets are + // enabled ; 0 - UART_A1 + // Clocks/Resets are disabled + +#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // UART_A1 ; 0 - De-assert the soft + // reset for UART_A1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A0 clock + // during deep-sleep ; 0 - Disable + // the GPT_A0 clock during + // deep-sleep + +#define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A0 clock + // during sleep ; 0 - Disable the + // GPT_A0 clock during sleep + +#define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A0 clock + // during run ; 0 - Disable the + // GPT_A0 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A0 clocks/resets are + // enabled ; 0 - GPT_A0 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A0 ; 0 - De-assert the soft + // reset for GPT_A0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A1 clock + // during deep-sleep ; 0 - Disable + // the GPT_A1 clock during + // deep-sleep + +#define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A1 clock + // during sleep ; 0 - Disable the + // GPT_A1 clock during sleep + +#define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A1 clock + // during run ; 0 - Disable the + // GPT_A1 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A1 clocks/resets are + // enabled ; 0 - GPT_A1 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A1 ; 0 - De-assert the soft + // reset for GPT_A1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A2_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A2 clock + // during deep-sleep ; 0 - Disable + // the GPT_A2 clock during + // deep-sleep + +#define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A2 clock + // during sleep ; 0 - Disable the + // GPT_A2 clock during sleep + +#define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A2 clock + // during run ; 0 - Disable the + // GPT_A2 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A2_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A2 clocks/resets are + // enabled ; 0 - GPT_A2 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A2 ; 0 - De-assert the soft + // reset for GPT_A2 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A3_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A3 clock + // during deep-sleep ; 0 - Disable + // the GPT_A3 clock during + // deep-sleep + +#define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A3 clock + // during sleep ; 0 - Disable the + // GPT_A3 clock during sleep + +#define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A3 clock + // during run ; 0 - Disable the + // GPT_A3 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A3_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A3 Clocks/resets are + // enabled ; 0 - GPT_A3 + // Clocks/resets are disabled + +#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A3 ; 0 - De-assert the soft + // reset for GPT_A3 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \ + 0x03FF0000 + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16 +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \ + 0x0000FFFF + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \ + 0x00010000 // 1 - Assert the reset for MCASP + // Frac-clk div; 0 - Donot assert + // the reset for MCASP frac clk-div + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \ + 0x000003FF + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CRYPTO_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable the Crypto clock + // during deep-sleep + +#define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9 +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the Crypto clock + // during sleep ; 0 - Disable the + // Crypto clock during sleep + +#define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1 +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the Crypto clock + // during run ; 0 - Disable the + // Crypto clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CRYPTO_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \ + 0x00000002 // 1 - Crypto clocks/resets are + // enabled ; 0 - Crypto + // clocks/resets are disabled + +#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // Crypto ; 0 - De-assert the soft + // reset for Crypto + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable the MCSPI_S0 clock + // during deep-sleep + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9 +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the MCSPI_S0 clock + // during sleep ; 0 - Disable the + // MCSPI_S0 clock during sleep + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1 +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the MCSPI_S0 clock + // during run ; 0 - Disable the + // MCSPI_S0 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are + // enabled ; 0 - MCSPI_S0 + // Clocks/resets are disabled + +#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // MCSPI_S0 ; 0 - De-assert the soft + // reset for MCSPI_S0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud-clk + // for MCSPI_S0 ; 1 - PLL divclk is + // used as buad-clk for MCSPI_S0 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_S0 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_S0 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_I2C_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the I2C Clock during + // deep-sleep 0 - Disable the I2C + // clock during deep-sleep + +#define APPS_RCM_I2C_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_I2C_CLK_GATING_NU1_S 9 +#define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the I2C clock during + // sleep ; 0 - Disable the I2C clock + // during sleep + +#define APPS_RCM_I2C_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_I2C_CLK_GATING_NU2_S 1 +#define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the I2C clock during + // run ; 0 - Disable the I2C clock + // during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_I2C_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \ + 0x00000002 // 1 - I2C Clocks/Resets are + // enabled ; 0 - I2C clocks/resets + // are disabled + +#define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // Shared-I2C ; 0 - De-assert the + // soft reset for Shared-I2C + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_LPDS_REQ register. +// +//****************************************************************************** +#define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \ + 0x00000001 // 1 - Request for LPDS + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_TURBO_REQ register. +// +//****************************************************************************** +#define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \ + 0x00000001 // 1 - Request for TURBO + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \ + 0x00000002 // 1 - Enable the NWP to wake APPS + // from deep-sleep ; 0 - Disable NWP + // to wake APPS from deep-sleep + +#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \ + 0x00000001 // 1 - Enable deep-sleep wake timer + // in APPS RCM for deep-sleep; 0 - + // Disable deep-sleep wake timer in + // APPS RCM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \ + 0xFFFF0000 // Configuration (in slow_clks) + // which says when to request for + // OPP during deep-sleep exit + +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16 +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \ + 0x0000FFFF // Configuration (in slow_clks) + // which says when to request for + // WAKE during deep-sleep exit + +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register. +// +//****************************************************************************** +#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \ + 0x00000002 // 1- Enable the sleep wakeup due + // to NWP request. 0- Disable the + // sleep wakeup due to NWP request + +#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \ + 0x00000001 // 1- Enable the sleep wakeup due + // to sleep-timer; 0-Disable the + // sleep wakeup due to sleep-timer + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \ + 0xFFFFFFFF // Configuration (number of + // sysclks-80MHz) for the Sleep + // wakeup timer + +#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register. +// +//****************************************************************************** +#define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \ + 0x00000001 // When 1 => APPS generated a wake + // request to NWP (When NWP is in + // any of its low-power modes : + // SLP/DSLP/LPDS) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register. +// +//****************************************************************************** +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \ + 0x00000008 // 1 - Indicates that deep-sleep + // timer expiry had caused the + // wakeup from deep-sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \ + 0x00000004 // 1 - Indicates that sleep timer + // expiry had caused the wakeup from + // sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \ + 0x00000002 // 1 - Indicates that NWP had + // caused the wakeup from deep-sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \ + 0x00000001 // 1 - Indicates that NWP had + // caused the wakeup from Sleep + + + + +#endif // __HW_APPS_RCM_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_camera.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_camera.h new file mode 100644 index 000000000..7b60e8ffa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_camera.h @@ -0,0 +1,521 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_CAMERA_H__ +#define __HW_CAMERA_H__ + +//***************************************************************************** +// +// The following are defines for the CAMERA register offsets. +// +//***************************************************************************** +#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP + // revision code ( Parallel Mode) +#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the + // various parameters of the OCP + // interface (CCP and Parallel Mode) +#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status + // information about the module + // excluding the interrupt status + // information (CCP and Parallel + // Mode) +#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups + // all the status of the module + // internal events that can generate + // an interrupt (CCP & Parallel + // Mode) +#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register + // allows to enable/disable the + // module internal sources of + // interrupt on an event-by-event + // basis (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the + // various parameters of the Camera + // Core block (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA + // interface of the Camera Core + // block (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value + // of the clock divisor used to + // generate the external clock + // (Parallel Mode) +#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to + // the FIFO and read from the FIFO + // (CCP & Parallel Mode) +#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status + // of some important variables of + // the camera core module (CCP & + // Parallel Mode) +#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values + // of the generic parameters of the + // module + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_REVISION register. +// +//****************************************************************************** +#define CAMERA_CC_REVISION_REV_M \ + 0x000000FF // IP revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 + +#define CAMERA_CC_REVISION_REV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_SYSCONFIG register. +// +//****************************************************************************** +#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \ + 0x00000018 // Slave interface power management + // req/ack control """00"" + // Force-idle. An idle request is + // acknoledged unconditionally" + // """01"" No-idle. An idle request + // is never acknowledged" """10"" + // reserved (Smart-idle not + // implemented)" + +#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3 +#define CAMERA_CC_SYSCONFIG_SOFT_RESET \ + 0x00000002 // Software reset. Set this bit to + // 1 to trigger a module reset. The + // bit is automatically reset by the + // hardware. During reset it always + // returns 0. 0 Normal mode 1 The + // module is reset + +#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \ + 0x00000001 // Internal OCP clock gating + // strategy 0 OCP clock is + // free-running 1 Automatic OCP + // clock gating strategy is applied + // based on the OCP interface + // activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_SYSSTATUS register. +// +//****************************************************************************** +#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \ + 0x00000001 // Internal Reset Monitoring 0 + // Internal module reset is on-going + // 1 Reset completed + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_IRQSTATUS register. +// +//****************************************************************************** +#define CAMERA_CC_IRQSTATUS_FS_IRQ \ + 0x00080000 // Frame Start has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_LE_IRQ \ + 0x00040000 // Line End has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_LS_IRQ \ + 0x00020000 // Line Start has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FE_IRQ \ + 0x00010000 // Frame End has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \ + 0x00000800 // FSP code error 0 Event false "1 + // Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \ + 0x00000400 // Frame Height Error 0 Event false + // "1 Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \ + 0x00000200 // False Synchronization Code 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \ + 0x00000100 // Shifted Synchronization Code 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \ + 0x00000010 // FIFO is not empty 0 Event false + // "1 Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \ + 0x00000008 // FIFO is full 0 Event false "1 + // Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \ + 0x00000004 // FIFO threshold has been reached + // 0 Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \ + 0x00000002 // FIFO overflow has occurred 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \ + 0x00000001 // FIFO underflow has occurred 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_IRQENABLE register. +// +//****************************************************************************** +#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \ + 0x00080000 // Frame Start Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \ + 0x00040000 // Line End Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \ + 0x00020000 // Line Start Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \ + 0x00010000 // Frame End Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \ + 0x00000800 // FSP code Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \ + 0x00000400 // Frame Height Error Interrupt + // Enable 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \ + 0x00000200 // False Synchronization Code + // Interrupt Enable 0 Event is + // masked 1 Event generates an + // interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \ + 0x00000100 // False Synchronization Code + // Interrupt Enable 0 Event is + // masked 1 Event generates an + // interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \ + 0x00000010 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \ + 0x00000008 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \ + 0x00000004 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \ + 0x00000002 // FIFO Overflow Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \ + 0x00000001 // FIFO Underflow Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +//****************************************************************************** +// +// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \ + 0x00080000 // Synchronize all camera sensor + // inputs This must be set during + // the configuration phase before + // CC_EN set to '1'. This can be + // used in very high frequency to + // avoid dependancy to the IO + // timings. 0 No synchro (most of + // applications) 1 Synchro enabled + // (should never be required) + +#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite + // states machines of the camera + // core module - by writing a 1 to + // this bit. must be applied when + // CC_EN = 0 Reads returns 0 +#define CAMERA_CC_CTRL_CC_FRAME_TRIG \ + 0x00020000 // Set the modality in which CC_EN + // works when a disabling of the + // sensor camera core is wanted "If + // CC_FRAME_TRIG = 1 by writing + // ""0"" to CC_EN" the module is + // disabled at the end of the frame + // "If CC_FRAME_TRIG = 0 by writing + // ""0"" to CC_EN" the module is + // disabled immediately + +#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of + // the camera core module "By + // writing ""1"" to this field the + // module is enabled." "By writing + // ""0"" to this field the module is + // disabled at" the end of the frame + // if CC_FRAM_TRIG =1 and is + // disabled immediately if + // CC_FRAM_TRIG = 0 +#define CAMERA_CC_CTRL_NOBT_SYNCHRO \ + 0x00002000 // Enables to start at the + // beginning of the frame or not in + // NoBT 0 Acquisition starts when + // Vertical synchro is high 1 + // Acquisition starts when Vertical + // synchro goes from low to high + // (beginning of the frame) - + // Recommended. + +#define CAMERA_CC_CTRL_BT_CORRECT \ + 0x00001000 // Enables the correction within + // the sync codes in BT mode 0 + // correction is not enabled 1 + // correction is enabled + +#define CAMERA_CC_CTRL_PAR_ORDERCAM \ + 0x00000800 // Enables swap between image-data + // in parallel mode 0 swap is not + // enabled 1 swap is enabled + +#define CAMERA_CC_CTRL_PAR_CLK_POL \ + 0x00000400 // Inverts the clock coming from + // the sensor in parallel mode 0 + // clock not inverted - data sampled + // on rising edge 1 clock inverted - + // data sampled on falling edge + +#define CAMERA_CC_CTRL_NOBT_HS_POL \ + 0x00000200 // Sets the polarity of the + // synchronization signals in NOBT + // parallel mode 0 CAM_P_HS is + // active high 1 CAM_P_HS is active + // low + +#define CAMERA_CC_CTRL_NOBT_VS_POL \ + 0x00000100 // Sets the polarity of the + // synchronization signals in NOBT + // parallel mode 0 CAM_P_VS is + // active high 1 CAM_P_VS is active + // low + +#define CAMERA_CC_CTRL_PAR_MODE_M \ + 0x0000000E // Sets the Protocol Mode of the + // Camera Core module in parallel + // mode (when CCP_MODE = 0) """000"" + // Parallel NOBT 8-bit" """001"" + // Parallel NOBT 10-bit" """010"" + // Parallel NOBT 12-bit" """011"" + // reserved" """100"" Parallet BT + // 8-bit" """101"" Parallel BT + // 10-bit" """110"" reserved" + // """111"" FIFO test mode. Refer to + // Table 12 - FIFO Write and Read + // access" + +#define CAMERA_CC_CTRL_PAR_MODE_S 1 +#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode + // 0 CCP mode disabled 1 CCP mode + // enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_CTRL_DMA register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_DMA_DMA_EN \ + 0x00000100 // Sets the number of dma request + // lines 0 DMA interface disabled + // The DMA request line stays + // inactive 1 DMA interface enabled + // The DMA request line is + // operational + +#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \ + 0x0000007F // Sets the threshold of the FIFO + // the assertion of the dmarequest + // line takes place when the + // threshold is reached. + // """0000000"" threshold set to 1" + // """0000001"" threshold set to 2" + // … """1111111"" threshold set to + // 128" + +#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_CTRL_XCLK register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \ + 0x0000001F // Sets the clock divisor value for + // CAM_XCLK generation. based on + // CAM_MCK (value of CAM_MCLK is + // 96MHz) """00000"" CAM_XCLK Stable + // Low Level" Divider not enabled + // """00001"" CAM_XCLK Stable High + // Level" Divider not enabled from 2 + // to 30 CAM_XCLK = CAM_MCLK / + // XCLK_DIV """11111"" Bypass - + // CAM_XCLK = CAM_MCLK" + +#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_FIFO_DATA register. +// +//****************************************************************************** +#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \ + 0xFFFFFFFF // Writes the 32-bit word into the + // FIFO Reads the 32-bit word from + // the FIFO + +#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the CAMERA_O_CC_TEST register. +// +//****************************************************************************** +#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \ + 0xFF000000 // FIFO READ Pointer This field + // shows the value of the FIFO read + // pointer Expected value ranges + // from 0 to 127 + +#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24 +#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \ + 0x00FF0000 // FIFO WRITE pointer This field + // shows the value of the FIFO write + // pointer Expected value ranges + // from 0 to 127 + +#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16 +#define CAMERA_CC_TEST_FIFO_LEVEL_M \ + 0x0000FF00 // FIFO level (how many 32-bit + // words the FIFO contains) This + // field shows the value of the FIFO + // level and can assume values from + // 0 to 128 + +#define CAMERA_CC_TEST_FIFO_LEVEL_S 8 +#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \ + 0x000000FF // FIFO level peak This field shows + // the max value of the FIFO level + // and can assume values from 0 to + // 128 + +#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_GEN_PAR register. +// +//****************************************************************************** +#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \ + 0x00000007 // Camera Core FIFO DEPTH generic + // parameter + +#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0 + + + +#endif // __HW_CAMERA_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_common_reg.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_common_reg.h new file mode 100644 index 000000000..e07c61e1d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_common_reg.h @@ -0,0 +1,1119 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_COMMON_REG_H__ +#define __HW_COMMON_REG_H__ + +//***************************************************************************** +// +// The following are defines for the COMMON_REG register offsets. +// +//***************************************************************************** +#define COMMON_REG_O_I2C_Properties_Register \ + 0x00000000 + +#define COMMON_REG_O_SPI_Properties_Register \ + 0x00000004 + +#define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \ + 0x0000000C + +#define COMMON_REG_O_APPS_sh_resource_Interrupt_status \ + 0x00000010 + +#define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \ + 0x00000014 + +#define COMMON_REG_O_NWP_sh_resource_Interrupt_status \ + 0x00000018 + +#define COMMON_REG_O_Flash_ctrl_reg \ + 0x0000001C + +#define COMMON_REG_O_Bus_matrix_M0_segment_access_config \ + 0x00000024 + +#define COMMON_REG_O_Bus_matrix_M1_segment_access_config \ + 0x00000028 + +#define COMMON_REG_O_Bus_matrix_M2_segment_access_config \ + 0x0000002C + +#define COMMON_REG_O_Bus_matrix_M3_segment_access_config \ + 0x00000030 + +#define COMMON_REG_O_Bus_matrix_M4_segment_access_config \ + 0x00000034 + +#define COMMON_REG_O_Bus_matrix_M5_segment_access_config \ + 0x00000038 + +#define COMMON_REG_O_GPIO_properties_register \ + 0x0000003C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE1 \ + 0x00000040 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE2 \ + 0x00000044 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE3 \ + 0x00000048 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE4 \ + 0x0000004C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE5 \ + 0x00000050 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE6 \ + 0x00000054 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE7 \ + 0x00000058 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE8 \ + 0x0000005C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE9 \ + 0x00000060 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE10 \ + 0x00000064 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE11 \ + 0x00000068 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE12 \ + 0x0000006C + +#define COMMON_REG_O_APPS_SEMAPPHORE_PEND \ + 0x00000070 + +#define COMMON_REG_O_NW_SEMAPPHORE_PEND \ + 0x00000074 + +#define COMMON_REG_O_SEMAPHORE_STATUS \ + 0x00000078 + +#define COMMON_REG_O_IDMEM_TIM_Update \ + 0x0000007C + +#define COMMON_REG_O_FPGA_ROM_WR_EN \ + 0x00000080 + +#define COMMON_REG_O_NW_INT_MASK \ + 0x00000084 + +#define COMMON_REG_O_NW_INT_MASK_SET \ + 0x00000088 + +#define COMMON_REG_O_NW_INT_MASK_CLR \ + 0x0000008C + +#define COMMON_REG_O_NW_INT_STS_CLR \ + 0x00000090 + +#define COMMON_REG_O_NW_INT_ACK 0x00000094 +#define COMMON_REG_O_NW_INT_TRIG \ + 0x00000098 + +#define COMMON_REG_O_NW_INT_STS_MASKED \ + 0x0000009C + +#define COMMON_REG_O_NW_INT_STS_RAW \ + 0x000000A0 + +#define COMMON_REG_O_APPS_INT_MASK \ + 0x000000A4 + +#define COMMON_REG_O_APPS_INT_MASK_SET \ + 0x000000A8 + +#define COMMON_REG_O_APPS_INT_MASK_CLR \ + 0x000000AC + +#define COMMON_REG_O_APPS_INT_STS_CLR \ + 0x000000B0 + +#define COMMON_REG_O_APPS_INT_ACK \ + 0x000000B4 + +#define COMMON_REG_O_APPS_INT_TRIG \ + 0x000000B8 + +#define COMMON_REG_O_APPS_INT_STS_MASKED \ + 0x000000BC + +#define COMMON_REG_O_APPS_INT_STS_RAW \ + 0x000000C0 + +#define COMMON_REG_O_IDMEM_TIM_Updated \ + 0x000000C4 + +#define COMMON_REG_O_APPS_GPIO_TRIG_EN \ + 0x000000C8 + +#define COMMON_REG_O_EMU_DEBUG_REG \ + 0x000000CC + +#define COMMON_REG_O_SEMAPHORE_STATUS2 \ + 0x000000D0 + +#define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \ + 0x000000D4 + +#define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \ + 0x000000D8 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_I2C_Properties_Register register. +// +//****************************************************************************** +#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SPI_Properties_Register register. +// +//****************************************************************************** +#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_sh_resource_Interrupt_enable register. +// +//****************************************************************************** +#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \ + 0x0000000F // Interrupt enable APPS bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_sh_resource_Interrupt_status register. +// +//****************************************************************************** +#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \ + 0x0000000F // Interrupt enable APPS bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NWP_sh_resource_Interrupt_enable register. +// +//****************************************************************************** +#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \ + 0x0000000F // Interrupt enable NWP bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NWP_sh_resource_Interrupt_status register. +// +//****************************************************************************** +#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \ + 0x0000000F // Interrupt enable NWP bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Flash_ctrl_reg register. +// +//****************************************************************************** +#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M0_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \ + 0x0003FFFF // Master 0 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M1_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \ + 0x0003FFFF // Master 1 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M2_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \ + 0x0003FFFF // Master 2 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M3_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \ + 0x0003FFFF // Master 3 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M4_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \ + 0x0003FFFF // Master 4 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M5_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \ + 0x0003FFFF // Master 5 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_GPIO_properties_register register. +// +//****************************************************************************** +#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \ + 0x000003FF // Shared GPIO configuration + // register. Bit [1:0] to configure + // GPIO0 Bit [3:2] to configure + // GPIO1 Bit [5:4] to configure + // GPIO2 Bit [7:6] to configure + // GPIO3 Bit [9:8] to configure + // GPIO4 each GPIO can be + // individully selected. When “00â€? + // GPIO is free resource. When “01â€? + // GPIO is APPS resource. When “10â€? + // GPIO is NWP resource. Writing 11 + // doesnt have any affect, i.e. If + // one write only relevant gpio + // semaphore and other bits are 1s, + // it'll not disturb the other + // semaphore bits. For example : Say + // If NW wants to take control of + // gpio-1, one should write + // 10'b11_1111_1011 and if one wants + // to release it write + // 10'b11_1111_0011. + +#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE1 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE2 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE3 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE4 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE5 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE6 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE7 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE8 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE9 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE10 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE11 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE12 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \ + 0xFFFFFFFF // APPS NW semaphore register - not + // reflected in status. + +#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_SEMAPPHORE_PEND register. +// +//****************************************************************************** +#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \ + 0xFFFFFFFF // APPS SEMAPOHORE STATUS + +#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_SEMAPPHORE_PEND register. +// +//****************************************************************************** +#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \ + 0xFFFFFFFF // NW SEMAPHORE STATUS + +#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_STATUS register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \ + 0xFFFFFFFF // SEMAPHORE STATUS 9:8 :semaphore + // status of flash_control 7:6 + // :semaphore status of + // gpio_properties 5:4 + // :semaphore status of + // spi_propertie 1:0 :semaphore + // status of i2c_propertie + +#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_IDMEM_TIM_Update register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_FPGA_ROM_WR_EN register. +// +//****************************************************************************** +#define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \ + 0x00000001 // when '1' enables Write into + // IDMEM CORE ROM, APPS ROM, NWP ROM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \ + 0xFFFFFFFF // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK_SET register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \ + 0xFFFFFFFF // write 1 to set corresponding bit + // in NW_INT_MASK;0 = no effect + +#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK_CLR register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // bit in NW_INT_MASK;0 = no effect + +#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_CLR register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt; 0 = no effect; + // interrupt is not lost if coincide + // with write operation + +#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_ACK register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt;0 = no effect + +#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_TRIG register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \ + 0xFFFFFFFF // Writing a 1 to a bit in this + // register causes the the Host CPU + // if enabled (not masked). This + // register is self-clearing. + // Writing 0 has no effect + +#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_MASKED register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by NW_INT mask + +#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_RAW register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \ + 0xFFFFFFFF // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK_SET register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \ + 0xFFFFFFFF // write 1 to set corresponding bit + // in APPS_INT_MASK;0 = no effect + +#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK_CLR register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // bit in APPS_INT_MASK;0 = no + // effect + +#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_CLR register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt; 0 = no effect; + // interrupt is not lost if coincide + // with write operation + +#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_ACK register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt;0 = no effect + +#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_TRIG register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \ + 0xFFFFFFFF // Writing a 1 to a bit in this + // register causes the the Host CPU + // if enabled (not masked). This + // register is self-clearing. + // Writing 0 has no effect + +#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_MASKED register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by APPS_INT mask + +#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_RAW register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_IDMEM_TIM_Updated register. +// +//****************************************************************************** +#define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \ + 0x00000001 // toggle in this signal + // indicatesIDMEM_TIM_UPDATE + // register mentioned above is + // updated. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_GPIO_TRIG_EN register. +// +//****************************************************************************** +#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \ + 0x0000001F // APPS GPIO Trigger EN control. + // Bit 0: when '1' enable GPIO 0 + // trigger. This bit enables trigger + // for all GPIO 0 pins (GPIO 0 to + // GPIO7). Bit 1: when '1' enable + // GPIO 1 trigger. This bit enables + // trigger for all GPIO 1 pins ( + // GPIO8 to GPIO15). Bit 2: when '1' + // enable GPIO 2 trigger. This bit + // enables trigger for all GPIO 2 + // pins (GPIO16 to GPIO23). Bit 3: + // when '1' enable GPIO 3 trigger. + // This bit enables trigger for all + // GPIO 3 pins (GPIO24 to GPIO31). + // Bit 4: when '1' enable GPIO 4 + // trigger. This bit enables trigger + // for all GPIO 4 pins.(GPIO32 to + // GPIO39) + +#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_EMU_DEBUG_REG register. +// +//****************************************************************************** +#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \ + 0xFFFFFFFF // 0 th bit used for stalling APPS + // DMA and 1st bit is used for + // stalling NWP DMA for debug + // purpose. Other bits are unused. + +#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_STATUS2 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \ + 0x00FFFFFF // SEMAPHORE STATUS 23:22 + // :semaphore status of + // apps_nw_semaphore11 21:20 + // :semaphore status of + // apps_nw_semaphore11 19:18 + // :semaphore status of + // apps_nw_semaphore10 17:16 + // :semaphore status of + // apps_nw_semaphore9 15:14 + // :semaphore status of + // apps_nw_semaphore8 13:12 + // :semaphore status of + // apps_nw_semaphore7 11:10 + // :semaphore status of + // apps_nw_semaphore6 9:8 :semaphore + // status of apps_nw_semaphore5 7:6 + // :semaphore status of + // apps_nw_semaphore4 5:4 :semaphore + // status of apps_nw_semaphore3 3:2 + // :semaphore status of + // apps_nw_semaphore2 1:0 :semaphore + // status of apps_nw_semaphore1 + +#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \ + 0x0003FFFF // 1:0 : prvious owner of + // i2c_properties_reg[1:0] 3:2 : + // prvious owner of + // spi_properties_reg[1:0] 5:4 : + // prvious owner of + // gpio_properties_reg[1:0] 9:8 : + // prvious owner of + // gpio_properties_reg[3:2] 11:10 : + // prvious owner of + // gpio_properties_reg[5:4] 13:12 : + // prvious owner of + // gpio_properties_reg[7:6] 15:14 : + // prvious owner of + // gpio_properties_reg[9:8] 17:16 : + // prvious owner of + // flash_control_reg[1:0] + +#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \ + 0x00FFFFFF // 1:0 : previous owner of + // apps_nw_semaphore1_reg[1:0] 3:2 : + // previous owner of + // apps_nw_semaphore2_reg[1:0] 5:4 : + // previous owner of + // apps_nw_semaphore3_reg[1:0] 7:6 : + // previous owner of + // apps_nw_semaphore4_reg[1:0] 9:8 : + // previous owner of + // apps_nw_semaphore5_reg[1:0] 11:10 + // : previous owner of + // apps_nw_semaphore6_reg[1:0] 13:12 + // : previous owner of + // apps_nw_semaphore7_reg[1:0] 15:14 + // : previous owner of + // apps_nw_semaphore8_reg[1:0] 17:16 + // : previous owner of + // apps_nw_semaphore9_reg[1:0] 19:18 + // : previous owner of + // apps_nw_semaphore10_reg[1:0] + // 21:20 : previous owner of + // apps_nw_semaphore11_reg[1:0] + // 23:22 : previous owner of + // apps_nw_semaphore12_reg[1:0] + +#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0 + + + +#endif // __HW_COMMON_REG_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_des.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_des.h new file mode 100644 index 000000000..124f17e40 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_des.h @@ -0,0 +1,341 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_DES_H__ +#define __HW_DES_H__ + +//***************************************************************************** +// +// The following are defines for the DES_P register offsets. +// +//***************************************************************************** +#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key +#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key +#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key +#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key +#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit + // key/192-bit key +#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit + // key/192-bit key +#define DES_O_IV_L 0x00000018 // Initialization vector LSW +#define DES_O_IV_H 0x0000001C // Initialization vector MSW +#define DES_O_CTRL 0x00000020 +#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data + // length in bytes for all modes. + // Once processing is started with + // this context this length + // decrements to zero. Data lengths + // up to (2^32 – 1) bytes are + // allowed. A write to this register + // triggers the engine to start + // using this context. For a Host + // read operation these registers + // return all-zeroes. +#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write + // encrypted/decrypted data. +#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write + // encrypted/decrypted data. +#define DES_O_REVISION 0x00000030 +#define DES_O_SYSCONFIG 0x00000034 +#define DES_O_SYSSTATUS 0x00000038 +#define DES_O_IRQSTATUS 0x0000003C // This register indicates the + // interrupt status. If one of the + // interrupt bits is set the + // interrupt output will be asserted +#define DES_O_IRQENABLE 0x00000040 // This register contains an enable + // bit for each unique interrupt + // generated by the module. It + // matches the layout of + // DES_IRQSTATUS register. An + // interrupt is enabled when the bit + // in this register is set to 1 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_L register. +// +//****************************************************************************** +#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3 +#define DES_KEY3_L_KEY3_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_H register. +// +//****************************************************************************** +#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3 +#define DES_KEY3_H_KEY3_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_L register. +// +//****************************************************************************** +#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2 +#define DES_KEY2_L_KEY2_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_H register. +// +//****************************************************************************** +#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2 +#define DES_KEY2_H_KEY2_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_L register. +// +//****************************************************************************** +#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1 +#define DES_KEY1_L_KEY1_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_H register. +// +//****************************************************************************** +#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1 +#define DES_KEY1_H_KEY1_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_L register. +// +//****************************************************************************** +#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC + // CFB modes +#define DES_IV_L_IV_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_H register. +// +//****************************************************************************** +#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC + // CFB modes +#define DES_IV_H_IV_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_CTRL register. +// +//****************************************************************************** +#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit + // indicates that the context data + // registers can be overwritten and + // the host is permitted to write + // the next context. +#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0 + // ecb mode 0x1 cbc mode 0x2 cfb + // mode 0x3 reserved +#define DES_CTRL_MODE_S 4 +#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES + // encryption/decryption. 0 des mode + // 1 tdes mode +#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0 + // decryption is selected 1 + // Encryption is selected +#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to + // encrypt/decrypt data +#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data + // decrypted/encrypted ready +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_LENGTH register. +// +//****************************************************************************** +#define DES_LENGTH_LENGTH_M 0xFFFFFFFF +#define DES_LENGTH_LENGTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_L register. +// +//****************************************************************************** +#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption +#define DES_DATA_L_DATA_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_H register. +// +//****************************************************************************** +#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption +#define DES_DATA_H_DATA_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_REVISION register. +// +//****************************************************************************** +#define DES_REVISION_SCHEME_M 0xC0000000 +#define DES_REVISION_SCHEME_S 30 +#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define DES_REVISION_FUNC_S 16 +#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define DES_REVISION_R_RTL_S 11 +#define DES_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. + +#define DES_REVISION_X_MAJOR_S 8 +#define DES_REVISION_CUSTOM_M 0x000000C0 +#define DES_REVISION_CUSTOM_S 6 +#define DES_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. + +#define DES_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSCONFIG register. +// +//****************************************************************************** +#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // If set to ‘1’ the DMA context + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // If set to ‘1’ the DMA output + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // If set to ‘1’ the DMA input + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSSTATUS register. +// +//****************************************************************************** +#define DES_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQSTATUS register. +// +//****************************************************************************** +#define DES_IRQSTATUS_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define DES_IRQSTATUS_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQENABLE register. +// +//****************************************************************************** +#define DES_IRQENABLE_M_DATA_OUT \ + 0x00000004 // If this bit is set to ‘1’ the + // secure data output interrupt is + // enabled. + +#define DES_IRQENABLE_M_DATA_IN \ + 0x00000002 // If this bit is set to ‘1’ the + // secure data input interrupt is + // enabled. + +#define DES_IRQENABLE_M_CONTEX_IN \ + 0x00000001 // If this bit is set to ‘1’ the + // secure context interrupt is + // enabled. + + + + +#endif // __HW_DES_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_dthe.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_dthe.h new file mode 100644 index 000000000..b871c6d24 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_dthe.h @@ -0,0 +1,394 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** + +#ifndef __HW_DTHE_H__ +#define __HW_DTHE_H__ + +//***************************************************************************** +// +// The following are defines for the DTHE register offsets. +// +//***************************************************************************** +#define DTHE_O_SHA_IM 0x00000810 +#define DTHE_O_SHA_RIS 0x00000814 +#define DTHE_O_SHA_MIS 0x00000818 +#define DTHE_O_SHA_IC 0x0000081C +#define DTHE_O_AES_IM 0x00000820 +#define DTHE_O_AES_RIS 0x00000824 +#define DTHE_O_AES_MIS 0x00000828 +#define DTHE_O_AES_IC 0x0000082C +#define DTHE_O_DES_IM 0x00000830 +#define DTHE_O_DES_RIS 0x00000834 +#define DTHE_O_DES_MIS 0x00000838 +#define DTHE_O_DES_IC 0x0000083C +#define DTHE_O_EIP_CGCFG 0x00000A00 +#define DTHE_O_EIP_CGREQ 0x00000A04 +#define DTHE_O_CRC_CTRL 0x00000C00 +#define DTHE_O_CRC_SEED 0x00000C10 +#define DTHE_O_CRC_DIN 0x00000C14 +#define DTHE_O_CRC_RSLT_PP 0x00000C18 +#define DTHE_O_RAND_KEY0 0x00000F00 +#define DTHE_O_RAND_KEY1 0x00000F04 +#define DTHE_O_RAND_KEY2 0x00000F08 +#define DTHE_O_RAND_KEY3 0x00000F0C + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IMST register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is + // raised when DMA complets the + // output context movement from + // internal register +#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IRIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done +#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IMIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done +#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_ICIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement doneâ€? + // flag +#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output doneâ€? flag +#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input doneâ€? flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IMST register. +// +//****************************************************************************** +#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is + // raised when DMA finishes writing + // last word of the process result +#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is + // raised when DMA complets the + // output context movement from + // internal register +#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IRIS register. +// +//****************************************************************************** +#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done +#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IMIS register. +// +//****************************************************************************** +#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done +#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_ICIS register. +// +//****************************************************************************** +#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement + // doneâ€? flag +#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement doneâ€? + // flag +#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output doneâ€? flag +#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input doneâ€? flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IMST register. +// +//****************************************************************************** +#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is + // raised when DMA finishes writing + // last word of the process result +#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IRIS register. +// +//****************************************************************************** +#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IMIS register. +// +//****************************************************************************** +#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_ICIS register. +// +//****************************************************************************** +#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement + // doneâ€? flag +#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement doneâ€? + // flag +#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input doneâ€? flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_EIP_CGCFG register. +// +//****************************************************************************** +#define DTHE_EIP_CGCFG_EIP29_CFG \ + 0x00000010 // Clock gating protocol setting + // for EIP29T. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP75_CFG \ + 0x00000008 // Clock gating protocol setting + // for EIP75T. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP16_CFG \ + 0x00000004 // Clock gating protocol setting + // for DES. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP36_CFG \ + 0x00000002 // Clock gating protocol setting + // for AES. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP57_CFG \ + 0x00000001 // Clock gating protocol setting + // for SHAMD5. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_EIP_CGREQ register. +// +//****************************************************************************** +#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5â€? write “1â€? to lower + // bits [4:0] will set the bit. + // Write “0â€? will be ignored When + // “0x2â€? write “1â€? to lower bit + // [4:0] will clear the bit. Write + // “0â€? will be ignored for other key + // value, regular read write + // operation +#define DTHE_EIP_CGREQ_Key_S 28 +#define DTHE_EIP_CGREQ_EIP29_REQ \ + 0x00000010 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP75_REQ \ + 0x00000008 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP16_REQ \ + 0x00000004 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP36_REQ \ + 0x00000002 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP57_REQ \ + 0x00000001 // 0 – request clock gating 1 – + // request to un-gate the clock. + +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register. +// +//****************************************************************************** +#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED + // register context as starting + // value 10 – all “zeroâ€? 11 – all + // “oneâ€? This is self clearing. With + // first write to data register this + // value clears to zero and remain + // zero for rest of the operation + // unless written again +#define DTHE_CRC_CTRL_INIT_S 13 +#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8 + // bit +#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result + // before storing to CRC_RSLT_PP0 +#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result + // byte before storing to + // CRC_RSLT_PP0. applicable for all + // bytes in word +#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For + // all bytes in word +#define DTHE_CRC_CTRL_ENDIAN_M \ + 0x00000030 // Endian control [0] – swap byte + // in half-word [1] – swap half word + +#define DTHE_CRC_CTRL_ENDIAN_S 4 +#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 – + // polynomial 0x8005 0001 – + // polynomial 0x1021 0010 – + // polynomial 0x4C11DB7 0011 – + // polynomial 0x1EDC6F41 1000 – TCP + // checksum TYPE in DTHE_S_CRC_CTRL + // & DTHE_S_CRC_CTRL should be + // exclusive +#define DTHE_CRC_CTRL_TYPE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_SEED register. +// +//****************************************************************************** +#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and + // checksum operation. Please see + // CTRL register for more detail. + // This resister also holds the + // latest result of CRC or checksum + // operation +#define DTHE_CRC_SEED_SEED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_DIN register. +// +//****************************************************************************** +#define DTHE_CRC_DIN_DATA_IN_M \ + 0xFFFFFFFF // Input data for CRC or checksum + // operation + +#define DTHE_CRC_DIN_DATA_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_CRC_RSLT_PP register. +// +//****************************************************************************** +#define DTHE_CRC_RSLT_PP_RSLT_PP_M \ + 0xFFFFFFFF // Input data for CRC or checksum + // operation + +#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY0 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [31:0] +#define DTHE_RAND_KEY0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY1 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [63:32] +#define DTHE_RAND_KEY1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY2 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [95:34] +#define DTHE_RAND_KEY2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY3 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [127:96] +#define DTHE_RAND_KEY3_KEY_S 0 + + + +#endif // __HW_DTHE_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_flash_ctrl.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_flash_ctrl.h new file mode 100644 index 000000000..0e0e10b88 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_flash_ctrl.h @@ -0,0 +1,1864 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_FLASH_CTRL_H__ +#define __HW_FLASH_CTRL_H__ + +//***************************************************************************** +// +// The following are defines for the FLASH_CTRL register offsets. +// +//***************************************************************************** +#define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA) + // offset 0x000 During a write + // operation this register contains + // a 4-byte-aligned address and + // specifies where the data is + // written. During erase operations + // this register contains a 1 + // KB-aligned CPU byte address and + // specifies which block is erased. + // Note that the alignment + // requirements must be met by + // software or the results of the + // operation are unpredictable. +#define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset + // 0x004 This register contains the + // data to be written during the + // programming cycle or read during + // the read cycle. Note that the + // contents of this register are + // undefined for a read access of an + // execute-only block. This register + // is not used during erase cycles. +#define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC) + // offset 0x008 When this register + // is written the Flash memory + // controller initiates the + // appropriate access cycle for the + // location specified by the Flash + // Memory Address (FMA) register . + // If the access is a write access + // the data contained in the Flash + // Memory Data (FMD) register is + // written to the specified address. + // This register must be the final + // register written and initiates + // the memory operation. The four + // control bits in the lower byte of + // this register are used to + // initiate memory operations. +#define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt + // Status (FCRIS) offset 0x00C This + // register indicates that the Flash + // memory controller has an + // interrupt condition. An interrupt + // is sent to the interrupt + // controller only if the + // corresponding FCIM register bit + // is set. +#define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask + // (FCIM) offset 0x010 This register + // controls whether the Flash memory + // controller generates interrupts + // to the controller. +#define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked + // Interrupt Status and Clear + // (FCMISC) offset 0x014 This + // register provides two functions. + // First it reports the cause of an + // interrupt by indicating which + // interrupt source or sources are + // signalling the interrupt. Second + // it serves as the method to clear + // the interrupt reporting. +#define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2) + // offset 0x020 When this register + // is written the Flash memory + // controller initiates the + // appropriate access cycle for the + // location specified by the Flash + // Memory Address (FMA) register . + // If the access is a write access + // the data contained in the Flash + // Write Buffer (FWB) registers is + // written. This register must be + // the final register written as it + // initiates the memory operation. +#define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid + // (FWBVAL) offset 0x030 This + // register provides a bitwise + // status of which FWBn registers + // have been written by the + // processor since the last write of + // the Flash memory write buffer. + // The entries with a 1 are written + // on the next write of the Flash + // memory write buffer. This + // register is cleared after the + // write operation by hardware. A + // protection violation on the write + // operation also clears this + // status. Software can program the + // same 32 words to various Flash + // memory locations by setting the + // FWB[n] bits after they are + // cleared by the write operation. + // The next write operation then + // uses the same data as the + // previous one. In addition if a + // FWBn register change should not + // be written to Flash memory + // software can clear the + // corresponding FWB[n] bit to + // preserve the existing data when + // the next write operation occurs. +#define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0 + // This register indicates the size + // of the on-chip Flash memory. + // Important: This register should + // be used to determine the size of + // the Flash memory that is + // implemented on this + // microcontroller. However to + // support legacy software the DC0 + // register is available. A read of + // the DC0 register correctly + // identifies legacy memory sizes. + // Software must use the FSIZE + // register for memory sizes that + // are not listed in the DC0 + // register description. +#define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4 + // This register indicates the size + // of the on-chip SRAM. Important: + // This register should be used to + // determine the size of the SRAM + // that is implemented on this + // microcontroller. However to + // support legacy software the DC0 + // register is available. A read of + // the DC0 register correctly + // identifies legacy memory sizes. + // Software must use the SSIZE + // register for memory sizes that + // are not listed in the DC0 + // register description. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMA register. +// +//****************************************************************************** +#define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF // Address Offset Address offset in + // Flash memory where operation is + // performed except for nonvolatile + // registers +#define FLASH_CTRL_FMA_OFFSET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMD register. +// +//****************************************************************************** +#define FLASH_CTRL_FMD_DATA_M 0xFFFFFFFF // Data Value Data value for write + // operation. +#define FLASH_CTRL_FMD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMC register. +// +//****************************************************************************** +#define FLASH_CTRL_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This + // field contains a write key which + // is used to minimize the incidence + // of accidental Flash memory + // writes. The value 0xA442 must be + // written into this field for a + // Flash memory write to occur. + // Writes to the FMC register + // without this WRKEY value are + // ignored. A read of this field + // returns the value 0. +#define FLASH_CTRL_FMC_WRKEY_S 16 +#define FLASH_CTRL_FMC_COMT 0x00000008 // Commit Register Value This bit + // is used to commit writes to + // Flash-memory-resident registers + // and to monitor the progress of + // that process. Value Description 1 + // Set this bit to commit (write) + // the register value to a + // Flash-memory-resident register. + // When read a 1 indicates that the + // previous commit access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous commit access is + // complete. +#define FLASH_CTRL_FMC_MERASE1 0x00000004 // Mass Erase Flash Memory This bit + // is used to mass erase the Flash + // main memory and to monitor the + // progress of that process. Value + // Description 1 Set this bit to + // erase the Flash main memory. When + // read a 1 indicates that the + // previous mass erase access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous mass erase access is + // complete. +#define FLASH_CTRL_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory + // This bit is used to erase a page + // of Flash memory and to monitor + // the progress of that process. + // Value Description 1 Set this bit + // to erase the Flash memory page + // specified by the contents of the + // FMA register. When read a 1 + // indicates that the previous page + // erase access is not complete. 0 A + // write of 0 has no effect on the + // state of this bit. When read a 0 + // indicates that the previous page + // erase access is complete. +#define FLASH_CTRL_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + // This bit is used to write a word + // into Flash memory and to monitor + // the progress of that process. + // Value Description 1 Set this bit + // to write the data stored in the + // FMD register into the Flash + // memory location specified by the + // contents of the FMA register. + // When read a 1 indicates that the + // write update access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous write update access is + // complete. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FCRIS register. +// +//****************************************************************************** +#define FLASH_CTRL_FCRIS_PROGRIS \ + 0x00002000 // Program Verify Error Raw + // Interrupt Status Value + // Description 1 An interrupt is + // pending because the verify of a + // PROGRAM operation failed. 0 An + // interrupt has not occurred. This + // bit is cleared by writing a 1 to + // the PROGMISC bit in the FCMISC + // register. + +#define FLASH_CTRL_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because the + // verify of an ERASE operation + // failed. 0 An interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the ERMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_INVDRIS \ + 0x00000400 // Invalid Data Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because a + // bit that was previously + // programmed as a 0 is now being + // requested to be programmed as a + // 1. 0 An interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the INVMISC bit in + // the FCMISC register. + +#define FLASH_CTRL_FCRIS_VOLTRIS \ + 0x00000200 // Pump Voltage Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because the + // regulated voltage of the pump + // went out of spec during the Flash + // operation and the operation was + // terminated. 0 An interrupt has + // not occurred. This bit is cleared + // by writing a 1 to the VOLTMISC + // bit in the FCMISC register. + +#define FLASH_CTRL_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status This + // bit provides status EEPROM + // operation. Value Description 1 An + // EEPROM interrupt has occurred. 0 + // An EEPROM interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the EMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status + // This bit provides status on + // programming cycles which are + // write or erase actions generated + // through the FMC or FMC2 register + // bits (see page 537 and page 549). + // Value Description 1 The + // programming or erase cycle has + // completed. 0 The programming or + // erase cycle has not completed. + // This status is sent to the + // interrupt controller when the + // PMASK bit in the FCIM register is + // set. This bit is cleared by + // writing a 1 to the PMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + // Value Description 1 A program or + // erase action was attempted on a + // block of Flash memory that + // contradicts the protection policy + // for that block as set in the + // FMPPEn registers. 0 No access has + // tried to improperly program or + // erase the Flash memory. This + // status is sent to the interrupt + // controller when the AMASK bit in + // the FCIM register is set. This + // bit is cleared by writing a 1 to + // the AMISC bit in the FCMISC + // register. +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register. +// +//****************************************************************************** +#define FLASH_CTRL_FCIM_ILLMASK 0x00004000 // Illegal Address Interrupt Mask + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the ILLARIS bit + // is set. 0 The ILLARIS interrupt + // is suppressed and not sent to the + // interrupt controller. +#define FLASH_CTRL_FCIM_PROGMASK \ + 0x00002000 // PROGVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the PROGRIS bit is set. 0 + // The PROGRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_PREMASK 0x00001000 // PREVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the PRERIS bit is set. 0 The + // PRERIS interrupt is suppressed + // and not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ERRIS bit is set. 0 The + // ERRIS interrupt is suppressed and + // not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_INVDMASK \ + 0x00000400 // Invalid Data Interrupt Mask + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the INVDRIS bit + // is set. 0 The INVDRIS interrupt + // is suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_VOLTMASK \ + 0x00000200 // VOLT Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the VOLTRIS bit is set. 0 + // The VOLTRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_LOCKMASK \ + 0x00000100 // LOCK Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the LOCKRIS bit is set. 0 + // The LOCKRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ERIS bit is set. 0 The + // ERIS interrupt is suppressed and + // not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_PMASK 0x00000002 // Programming Interrupt Mask This + // bit controls the reporting of the + // programming raw interrupt status + // to the interrupt controller. + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the PRIS bit is + // set. 0 The PRIS interrupt is + // suppressed and not sent to the + // interrupt controller. +#define FLASH_CTRL_FCIM_AMASK 0x00000001 // Access Interrupt Mask This bit + // controls the reporting of the + // access raw interrupt status to + // the interrupt controller. Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ARIS bit is set. 0 The + // ARIS interrupt is suppressed and + // not sent to the interrupt + // controller. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FCMISC register. +// +//****************************************************************************** +#define FLASH_CTRL_FCMISC_ILLMISC \ + 0x00004000 // Illegal Address Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled. Writing a + // 1 to this bit clears ILLAMISC and + // also the ILLARIS bit in the FCRIS + // register (see page 540). 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_PROGMISC \ + 0x00002000 // PROGVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // PROGMISC and also the PROGRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_PREMISC \ + 0x00001000 // PREVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // PREMISC and also the PRERIS bit + // in the FCRIS register . 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_ERMISC \ + 0x00000800 // ERVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // ERMISC and also the ERRIS bit in + // the FCRIS register 0 When read a + // 0 indicates that an interrupt has + // not occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_INVDMISC \ + 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled. Writing a + // 1 to this bit clears INVDMISC and + // also the INVDRIS bit in the FCRIS + // register (see page 540). 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_VOLTMISC \ + 0x00000200 // VOLT Masked Interrupt Status and + // Clear Value Description 1 When + // read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // VOLTMISC and also the VOLTRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_LOCKMISC \ + 0x00000100 // LOCK Masked Interrupt Status and + // Clear Value Description 1 When + // read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // LOCKMISC and also the LOCKRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // EMISC and also the ERIS bit in + // the FCRIS register 0 When read a + // 0 indicates that an interrupt has + // not occurred. A write of 0 has no + // effect on the state of this bit. +#define FLASH_CTRL_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled because a + // programming cycle completed. + // Writing a 1 to this bit clears + // PMISC and also the PRIS bit in + // the FCRIS register 0 When read a + // 0 indicates that a programming + // cycle complete interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. +#define FLASH_CTRL_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled + // because a program or erase action + // was attempted on a block of Flash + // memory that contradicts the + // protection policy for that block + // as set in the FMPPEn registers. + // Writing a 1 to this bit clears + // AMISC and also the ARIS bit in + // the FCRIS register 0 When read a + // 0 indicates that no improper + // accesses have occurred. A write + // of 0 has no effect on the state + // of this bit. +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register. +// +//****************************************************************************** +#define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This + // field contains a write key which + // is used to minimize the incidence + // of accidental Flash memory + // writes. The value 0xA442 must be + // written into this field for a + // write to occur. Writes to the + // FMC2 register without this WRKEY + // value are ignored. A read of this + // field returns the value 0. +#define FLASH_CTRL_FMC2_WRKEY_S 16 +#define FLASH_CTRL_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write This + // bit is used to start a buffered + // write to Flash memory. Value + // Description 1 Set this bit to + // write the data stored in the FWBn + // registers to the location + // specified by the contents of the + // FMA register. When read a 1 + // indicates that the previous + // buffered Flash memory write + // access is not complete. 0 A write + // of 0 has no effect on the state + // of this bit. When read a 0 + // indicates that the previous + // buffered Flash memory write + // access is complete. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWBVAL register. +// +//****************************************************************************** +#define FLASH_CTRL_FWBVAL_FWBN_M \ + 0xFFFFFFFF // Flash Memory Write Buffer Value + // Description 1 The corresponding + // FWBn register has been updated + // since the last buffer write + // operation and is ready to be + // written to Flash memory. 0 The + // corresponding FWBn register has + // no new data to be written. Bit 0 + // corresponds to FWB0 offset 0x100 + // and bit 31 corresponds to FWB31 + // offset 0x13C. + +#define FLASH_CTRL_FWBVAL_FWBN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB1_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB2_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB3_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB4_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB4_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB5_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB5_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB6_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB6_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB7_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB7_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB8_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB8_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB9_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB9_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB10 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB10_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB11 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB11_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB12 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB12_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB13 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB13_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB14 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB14_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB15 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB15_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB16 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB16_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB17 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB17_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB18 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB18_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB19 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB19_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB20 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB20_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB21 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB21_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB22 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB22_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB23 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB23_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB24 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB24_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB25 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB25_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB26 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB26_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB27 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB27_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB28 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB28_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB29 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB29_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB30 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB30_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB31 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB31_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB32 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB32_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FSIZE register. +// +//****************************************************************************** +#define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF // Flash Size Indicates the size of + // the on-chip Flash memory. Value + // Description 0x0003 8 KB of Flash + // 0x0007 16 KB of Flash 0x000F 32 + // KB of Flash 0x001F 64 KB of Flash + // 0x002F 96 KB of Flash 0x003F 128 + // KB of Flash 0x005F 192 KB of + // Flash 0x007F 256 KB of Flash +#define FLASH_CTRL_FSIZE_SIZE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_SSIZE register. +// +//****************************************************************************** +#define FLASH_CTRL_SSIZE_SRAM_SIZE_M \ + 0x0000FFFF // SRAM Size Indicates the size of + // the on-chip SRAM. Value + // Description 0x0007 2 KB of SRAM + // 0x000F 4 KB of SRAM 0x0017 6 KB + // of SRAM 0x001F 8 KB of SRAM + // 0x002F 12 KB of SRAM 0x003F 16 KB + // of SRAM 0x004F 20 KB of SRAM + // 0x005F 24 KB of SRAM 0x007F 32 KB + // of SRAM + +#define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0 +#define FLASH_CTRL_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_CTRL_FMC2_WRKEY 0xA4420000 // FLASH write key +#define FLASH_CTRL_O_FWBN FLASH_CTRL_O_FWB1 +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read + // Enable 0 +#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read + // Enable 1 +#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read + // Enable 2 +#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read + // Enable 3 +#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read + // Enable 4 +#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read + // Enable 5 +#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read + // Enable 6 +#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read + // Enable 7 +#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read + // Enable 8 +#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read + // Enable 9 +#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read + // Enable 10 +#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read + // Enable 11 +#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read + // Enable 12 +#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read + // Enable 13 +#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read + // Enable 14 +#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read + // Enable 15 + +#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program + // Enable 0 +#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program + // Enable 1 +#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program + // Enable 2 +#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program + // Enable 3 +#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program + // Enable 4 +#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program + // Enable 5 +#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program + // Enable 6 +#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program + // Enable 7 +#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program + // Enable 8 +#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program + // Enable 9 +#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program + // Enable 10 +#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program + // Enable 11 +#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program + // Enable 12 +#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program + // Enable 13 +#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program + // Enable 14 +#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program + // Enable 15 + +#define FLASH_USECRL 0x400FE140 // USec Reload +#define FLASH_CTRL_ERASE_SIZE 0x00000400 + + +#endif // __HW_FLASH_CTRL_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_gpio.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_gpio.h new file mode 100644 index 000000000..bd4200be1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_gpio.h @@ -0,0 +1,1351 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO register offsets. +// +//***************************************************************************** +#define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000 + // 7000 0x4002 4000 GPIO Data + // (GPIODATA)@@ offset 0x000 The + // GPIODATA register is the data + // register. In software control + // mode@@ values written in the + // GPIODATA register are transferred + // onto the GPIO port pins if the + // respective pins have been + // configured as outputs through the + // GPIO Direction (GPIODIR) register + // (see page 653). In order to write + // to GPIODATA@@ the corresponding + // bits in the mask@@ resulting from + // the address bus bits [9:2]@@ must + // be set. Otherwise@@ the bit + // values remain unchanged by the + // write. Similarly@@ the values + // read from this register are + // determined for each bit by the + // mask bit derived from the address + // used to access the data + // register@@ bits [9:2]. Bits that + // are set in the address mask cause + // the corresponding bits in + // GPIODATA to be read@@ and bits + // that are clear in the address + // mask cause the corresponding bits + // in GPIODATA to be read as 0@@ + // regardless of their value. A read + // from GPIODATA returns the last + // bit value written if the + // respective pins are configured as + // outputs@@ or it returns the value + // on the corresponding input pin + // when these are configured as + // inputs. All bits are cleared by a + // reset. +#define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000 + // 7400 0x4002 4400 GPIO Direction + // (GPIODIR)@@ offset 0x400 The + // GPIODIR register is the data + // direction register. Setting a bit + // in the GPIODIR register + // configures the corresponding pin + // to be an output@@ while clearing + // a bit configures the + // corresponding pin to be an input. + // All bits are cleared by a reset@@ + // meaning all GPIO pins are inputs + // by default. +#define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000 + // 7404 0x4002 4404 GPIO Interrupt + // Sense (GPIOIS)@@ offset 0x404 The + // GPIOIS register is the interrupt + // sense register. Setting a bit in + // the GPIOIS register configures + // the corresponding pin to detect + // levels@@ while clearing a bit + // configures the corresponding pin + // to detect edges. All bits are + // cleared by a reset. +#define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000 + // 7408 0x4002 4408 GPIO Interrupt + // Both Edges (GPIOIBE)@@ offset + // 0x408 The GPIOIBE register allows + // both edges to cause interrupts. + // When the corresponding bit in the + // GPIO Interrupt Sense (GPIOIS) + // register is set to detect edges@@ + // setting a bit in the GPIOIBE + // register configures the + // corresponding pin to detect both + // rising and falling edges@@ + // regardless of the corresponding + // bit in the GPIO Interrupt Event + // (GPIOIEV) register . Clearing a + // bit configures the pin to be + // controlled by the GPIOIEV + // register. All bits are cleared by + // a reset. +#define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000 + // 740C 0x4002 440C GPIO Interrupt + // Event (GPIOIEV)@@ offset 0x40C + // The GPIOIEV register is the + // interrupt event register. Setting + // a bit in the GPIOIEV register + // configures the corresponding pin + // to detect rising edges or high + // levels@@ depending on the + // corresponding bit value in the + // GPIO Interrupt Sense (GPIOIS) + // register . Clearing a bit + // configures the pin to detect + // falling edges or low levels@@ + // depending on the corresponding + // bit value in the GPIOIS register. + // All bits are cleared by a reset. +#define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000 + // 7410 0x4002 4410 GPIO Interrupt + // Mask (GPIOIM)@@ offset 0x410 The + // GPIOIM register is the interrupt + // mask register. Setting a bit in + // the GPIOIM register allows + // interrupts that are generated by + // the corresponding pin to be sent + // to the interrupt controller on + // the combined interrupt signal. + // Clearing a bit prevents an + // interrupt on the corresponding + // pin from being sent to the + // interrupt controller. All bits + // are cleared by a reset. +#define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000 + // 7414 0x4002 4414 GPIO Raw + // Interrupt Status (GPIORIS)@@ + // offset 0x414 The GPIORIS register + // is the raw interrupt status + // register. A bit in this register + // is set when an interrupt + // condition occurs on the + // corresponding GPIO pin. If the + // corresponding bit in the GPIO + // Interrupt Mask (GPIOIM) register + // is set@@ the interrupt is sent to + // the interrupt controller. Bits + // read as zero indicate that + // corresponding input pins have not + // initiated an interrupt. A bit in + // this register can be cleared by + // writing a 1 to the corresponding + // bit in the GPIO Interrupt Clear + // (GPIOICR) register. +#define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000 + // 7418 0x4002 4418 GPIO Masked + // Interrupt Status (GPIOMIS)@@ + // offset 0x418 The GPIOMIS register + // is the masked interrupt status + // register. If a bit is set in this + // register@@ the corresponding + // interrupt has triggered an + // interrupt to the interrupt + // controller. If a bit is clear@@ + // either no interrupt has been + // generated@@ or the interrupt is + // masked. If no port pin@@ other + // than the one that is being used + // as an ADC trigger@@ is being used + // to generate interrupts@@ the + // appropriate Interrupt Set Enable + // (ENn) register can disable the + // interrupts for the port@@ and the + // ADC interrupt can be used to read + // back the converted data. + // Otherwise@@ the port interrupt + // handler must ignore and clear + // interrupts on the port pin and + // wait for the ADC interrupt@@ or + // the ADC interrupt must be + // disabled in the EN0 register and + // the port interrupt handler must + // poll the ADC registers until the + // conversion is completed. If no + // port pin@@ other than the one + // that is being used as an ADC + // trigger@@ is being used to + // generate interrupts@@ the + // appropriate Interrupt Set Enable + // (ENn) register can disable the + // interrupts for the port@@ and the + // ADC interrupt can be used to read + // back the converted data. + // Otherwise@@ the port interrupt + // handler must ignore and clear + // interrupts on the port pin and + // wait for the ADC interrupt@@ or + // the ADC interrupt must be + // disabled in the EN0 register and + // the port interrupt handler must + // poll the ADC registers until the + // conversion is completed. Note + // that if the Port B GPIOADCCTL + // register is cleared@@ PB4 can + // still be used as an external + // trigger for the ADC. This is a + // legacy mode which allows code + // written for previous Stellaris + // devices to operate on this + // microcontroller. GPIOMIS is the + // state of the interrupt after + // masking. +#define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000 + // 741C 0x4002 441C GPIO Interrupt + // Clear (GPIOICR)@@ offset 0x41C + // The GPIOICR register is the + // interrupt clear register. Writing + // a 1 to a bit in this register + // clears the corresponding + // interrupt bit in the GPIORIS and + // GPIOMIS registers. Writing a 0 + // has no effect. +#define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000 + // 7420 0x4002 4420 GPIO Alternate + // Function Select (GPIOAFSEL)@@ + // offset 0x420 The GPIOAFSEL + // register is the mode control + // select register. If a bit is + // clear@@ the pin is used as a GPIO + // and is controlled by the GPIO + // registers. Setting a bit in this + // register configures the + // corresponding GPIO line to be + // controlled by an associated + // peripheral. Several possible + // peripheral functions are + // multiplexed on each GPIO. The + // GPIO Port Control (GPIOPCTL) + // register is used to select one of + // the possible functions. +#define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000 + // 7500 0x4002 4500 GPIO 2-mA Drive + // Select (GPIODR2R)@@ offset 0x500 + // The GPIODR2R register is the 2-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV2 bit for a GPIO + // signal@@ the corresponding DRV4 + // bit in the GPIODR4R register and + // DRV8 bit in the GPIODR8R register + // are automatically cleared by + // hardware. By default@@ all GPIO + // pins have 2-mA drive. +#define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000 + // 7504 0x4002 4504 GPIO 4-mA Drive + // Select (GPIODR4R)@@ offset 0x504 + // The GPIODR4R register is the 4-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV4 bit for a GPIO + // signal@@ the corresponding DRV2 + // bit in the GPIODR2R register and + // DRV8 bit in the GPIODR8R register + // are automatically cleared by + // hardware. +#define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000 + // 7508 0x4002 4508 GPIO 8-mA Drive + // Select (GPIODR8R)@@ offset 0x508 + // The GPIODR8R register is the 8-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV8 bit for a GPIO + // signal@@ the corresponding DRV2 + // bit in the GPIODR2R register and + // DRV4 bit in the GPIODR4R register + // are automatically cleared by + // hardware. The 8-mA setting is + // also used for high-current + // operation. Note: There is no + // configuration difference between + // 8-mA and high-current operation. + // The additional current capacity + // results from a shift in the + // VOH/VOL levels. +#define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000 + // 750C 0x4002 450C GPIO Open Drain + // Select (GPIOODR)@@ offset 0x50C + // The GPIOODR register is the open + // drain control register. Setting a + // bit in this register enables the + // open-drain configuration of the + // corresponding GPIO pad. When + // open-drain mode is enabled@@ the + // corresponding bit should also be + // set in the GPIO Digital Input + // Enable (GPIODEN) register . + // Corresponding bits in the drive + // strength and slew rate control + // registers (GPIODR2R@@ GPIODR4R@@ + // GPIODR8R@@ and GPIOSLR) can be + // set to achieve the desired rise + // and fall times. The GPIO acts as + // an open-drain input if the + // corresponding bit in the GPIODIR + // register is cleared. If open + // drain is selected while the GPIO + // is configured as an input@@ the + // GPIO will remain an input and the + // open-drain selection has no + // effect until the GPIO is changed + // to an output. When using the I2C + // module@@ in addition to + // configuring the pin to open + // drain@@ the GPIO Alternate + // Function Select (GPIOAFSEL) + // register bits for the I2C clock + // and data pins should be set +#define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000 + // 7510 0x4002 4510 GPIO Pull-Up + // Select (GPIOPUR)@@ offset 0x510 + // The GPIOPUR register is the + // pull-up control register. When a + // bit is set@@ a weak pull-up + // resistor on the corresponding + // GPIO signal is enabled. Setting a + // bit in GPIOPUR automatically + // clears the corresponding bit in + // the GPIO Pull-Down Select + // (GPIOPDR) register . Write access + // to this register is protected + // with the GPIOCR register. Bits in + // GPIOCR that are cleared prevent + // writes to the equivalent bit in + // this register. +#define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000 + // 7514 0x4002 4514 GPIO Pull-Down + // Select (GPIOPDR)@@ offset 0x514 + // The GPIOPDR register is the + // pull-down control register. When + // a bit is set@@ a weak pull-down + // resistor on the corresponding + // GPIO signal is enabled. Setting a + // bit in GPIOPDR automatically + // clears the corresponding bit in + // the GPIO Pull-Up Select (GPIOPUR) + // register +#define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000 + // 7518 0x4002 4518 The GPIOSLR + // register is the slew rate control + // register. Slew rate control is + // only available when using the + // 8-mA drive strength option via + // the GPIO 8-mA Drive Select + // (GPIODR8R) register +#define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000 + // 751C 0x4002 451C GPIO Digital + // Enable (GPIODEN)@@ offset 0x51C + // Note: Pins configured as digital + // inputs are Schmitt-triggered. The + // GPIODEN register is the digital + // enable register. By default@@ all + // GPIO signals except those listed + // below are configured out of reset + // to be undriven (tristate). Their + // digital function is disabled; + // they do not drive a logic value + // on the pin and they do not allow + // the pin voltage into the GPIO + // receiver. To use the pin as a + // digital input or output (either + // GPIO or alternate function)@@ the + // corresponding GPIODEN bit must be + // set. +#define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000 + // 7520 0x4002 4520 GPIO Lock + // (GPIOLOCK)@@ offset 0x520 The + // GPIOLOCK register enables write + // access to the GPIOCR register . + // Writing 0x4C4F.434B to the + // GPIOLOCK register unlocks the + // GPIOCR register. Writing any + // other value to the GPIOLOCK + // register re-enables the locked + // state. Reading the GPIOLOCK + // register returns the lock status + // rather than the 32-bit value that + // was previously written. + // Therefore@@ when write accesses + // are disabled@@ or locked@@ + // reading the GPIOLOCK register + // returns 0x0000.0001. When write + // accesses are enabled@@ or + // unlocked@@ reading the GPIOLOCK + // register returns 0x0000.0000. +#define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000 + // 7524 0x4002 4524 GPIO Commit + // (GPIOCR)@@ offset 0x524 The + // GPIOCR register is the commit + // register. The value of the GPIOCR + // register determines which bits of + // the GPIOAFSEL@@ GPIOPUR@@ + // GPIOPDR@@ and GPIODEN registers + // are committed when a write to + // these registers is performed. If + // a bit in the GPIOCR register is + // cleared@@ the data being written + // to the corresponding bit in the + // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ + // or GPIODEN registers cannot be + // committed and retains its + // previous value. If a bit in the + // GPIOCR register is set@@ the data + // being written to the + // corresponding bit of the + // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ + // or GPIODEN registers is committed + // to the register and reflects the + // new value. The contents of the + // GPIOCR register can only be + // modified if the status in the + // GPIOLOCK register is unlocked. + // Writes to the GPIOCR register are + // ignored if the status in the + // GPIOLOCK register is locked. +#define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000 + // 7528 0x4002 4528 The GPIOAMSEL + // register controls isolation + // circuits to the analog side of a + // unified I/O pad. Because the + // GPIOs may be driven by a 5-V + // source and affect analog + // operation@@ analog circuitry + // requires isolation from the pins + // when they are not used in their + // analog function. Each bit of this + // register controls the isolation + // circuitry for the corresponding + // GPIO signal. +#define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) 0x4000 552C + // 0x4000 652C 0x4000 752C 0x4002 + // 452C GPIO Port Control + // (GPIOPCTL)@@ offset 0x52C The + // GPIOPCTL register is used in + // conjunction with the GPIOAFSEL + // register and selects the specific + // peripheral signal for each GPIO + // pin when using the alternate + // function mode. Most bits in the + // GPIOAFSEL register are cleared on + // reset@@ therefore most GPIO pins + // are configured as GPIOs by + // default. When a bit is set in the + // GPIOAFSEL register@@ the + // corresponding GPIO signal is + // controlled by an associated + // peripheral. The GPIOPCTL register + // selects one out of a set of + // peripheral functions for each + // GPIO@@ providing additional + // flexibility in signal definition. +#define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in + // cc3xx. ADC trigger via GPIO is + // not supported. 0x4000 5530 0x4000 + // 6530 0x4000 7530 0x4002 4530 GPIO + // ADC Control (GPIOADCCTL)@@ offset + // 0x530 This register is used to + // configure a GPIO pin as a source + // for the ADC trigger. Note that if + // the Port B GPIOADCCTL register is + // cleared@@ PB4 can still be used + // as an external trigger for the + // ADC. This is a legacy mode which + // allows code written for previous + // Stellaris devices to operate on + // this microcontroller. +#define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000 + // 7534 0x4002 4534 GPIO DMA Control + // (GPIODMACTL)@@ offset 0x534 This + // register is used to configure a + // GPIO pin as a source for the ?DMA + // trigger. +#define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000 + // 7538 0x4002 4538 GPIO Select + // Interrupt (GPIOSI)@@ offset 0x538 + // This register is used to enable + // individual interrupts for each + // pin. Note: This register is only + // available on Port P and Port Q. +#define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000 + // 7FD0 0x4002 4FD0 GPIO Peripheral + // Identification 4 + // (GPIOPeriphID4)@@ offset 0xFD0 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000 + // 7FD4 0x4002 4FD4 GPIO Peripheral + // Identification 5 + // (GPIOPeriphID5)@@ offset 0xFD4 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000 + // 7FD8 0x4002 4FD8 GPIO Peripheral + // Identification 6 + // (GPIOPeriphID6)@@ offset 0xFD8 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000 + // 7FDC 0x4002 4FDC GPIO Peripheral + // Identification 7 + // (GPIOPeriphID7)@@ offset 0xFDC + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000 + // 7FE0 0x4002 4FE0 GPIO Peripheral + // Identification 0 + // (GPIOPeriphID0)@@ offset 0xFE0 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000 + // 7FE4 0x4002 4FE4 GPIO Peripheral + // Identification 1 + // (GPIOPeriphID1)@@ offset 0xFE4 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000 + // 7FE8 0x4002 4FE8 GPIO Peripheral + // Identification 2 + // (GPIOPeriphID2)@@ offset 0xFE8 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000 + // 7FEC 0x4002 4FEC GPIO Peripheral + // Identification 3 + // (GPIOPeriphID3)@@ offset 0xFEC + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000 + // 7FF0 0x4002 4FF0 GPIO PrimeCell + // Identification 0 (GPIOPCellID0)@@ + // offset 0xFF0 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000 + // 7FF4 0x4002 4FF4 GPIO PrimeCell + // Identification 1 (GPIOPCellID1)@@ + // offset 0xFF4 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000 + // 7FF8 0x4002 4FF8 GPIO PrimeCell + // Identification 2 (GPIOPCellID2)@@ + // offset 0xFF8 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000 + // 7FFC 0x4002 4FFC GPIO PrimeCell + // Identification 3 (GPIOPCellID3)@@ + // offset 0xFFC The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system.0xb1 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register. +// +//****************************************************************************** +#define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is + // virtually mapped to 256 locations + // in the address space. To + // facilitate the reading and + // writing of data to these + // registers by independent + // drivers@@ the data read from and + // written to the registers are + // masked by the eight address lines + // [9:2]. Reads from this register + // return its current state. Writes + // to this register only affect bits + // that are not masked by ADDR[9:2] + // and are configured as outputs. +#define GPIO_GPIO_DATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register. +// +//****************************************************************************** +#define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value + // Description 0 Corresponding pin + // is an input. 1 Corresponding pins + // is an output. +#define GPIO_GPIO_DIR_DIR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IS register. +// +//****************************************************************************** +#define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value + // Description 0 The edge on the + // corresponding pin is detected + // (edge-sensitive). 1 The level on + // the corresponding pin is detected + // (level-sensitive). +#define GPIO_GPIO_IS_IS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register. +// +//****************************************************************************** +#define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value + // Description 0 Interrupt + // generation is controlled by the + // GPIO Interrupt Event (GPIOIEV) + // register. 1 Both edges on the + // corresponding pin trigger an + // interrupt. +#define GPIO_GPIO_IBE_IBE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register. +// +//****************************************************************************** +#define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value + // Description 1 A falling edge or a + // Low level on the corresponding + // pin triggers an interrupt. 0 A + // rising edge or a High level on + // the corresponding pin triggers an + // interrupt. +#define GPIO_GPIO_IEV_IEV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IM register. +// +//****************************************************************************** +#define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value + // Description 0 The interrupt from + // the corresponding pin is masked. + // 1 The interrupt from the + // corresponding pin is sent to the + // interrupt controller. +#define GPIO_GPIO_IM_IME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register. +// +//****************************************************************************** +#define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value + // Description 1 An interrupt + // condition has occurred on the + // corresponding pin. 0 interrupt + // condition has not occurred on the + // corresponding pin. A bit is + // cleared by writing a 1 to the + // corresponding bit in the GPIOICR + // register. +#define GPIO_GPIO_RIS_RIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register. +// +//****************************************************************************** +#define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status + // Value Description 1 An interrupt + // condition on the corresponding + // pin has triggered an interrupt to + // the interrupt controller. 0 An + // interrupt condition on the + // corresponding pin is masked or + // has not occurred. A bit is + // cleared by writing a 1 to the + // corresponding bit in the GPIOICR + // register. +#define GPIO_GPIO_MIS_MIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register. +// +//****************************************************************************** +#define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value + // Description 1 The corresponding + // interrupt is cleared. 0 The + // corresponding interrupt is + // unaffected. +#define GPIO_GPIO_ICR_IC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 2-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 2-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR4R + // or GPIODR8R register. 0 Setting a + // bit in either the GPIODR4 + // register or the GPIODR8 register + // clears the corresponding 2-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR2R_DRV2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 4-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 4-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR2R + // or GPIODR8R register. 0 Setting a + // bit in either the GPIODR2 + // register or the GPIODR8 register + // clears the corresponding 4-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR4R_DRV4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 8-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 8-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR2R + // or GPIODR4R register. 0 Setting a + // bit in either the GPIODR2 + // register or the GPIODR4 register + // clears the corresponding 8-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR8R_DRV8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register. +// +//****************************************************************************** +#define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // Open Drain Enable Value + // Description 1 The corresponding + // pin is configured as open drain. + // 0 The corresponding pin is not + // configured as open drain. +#define GPIO_GPIO_ODR_ODE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register. +// +//****************************************************************************** +#define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Pad Weak + // Pull-Up Enable Value Description + // 1 The corresponding pin has a + // weak pull-up resistor. 0 The + // corresponding pin is not + // affected. Setting a bit in the + // GPIOPDR register clears the + // corresponding bit in the GPIOPUR + // register. The change is effective + // on the second clock cycle after + // the write if accessing GPIO via + // the APB memory aperture. If using + // AHB access@@ the change is + // effective on the next clock + // cycle. +#define GPIO_GPIO_PUR_PUE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register. +// +//****************************************************************************** +#define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Pad Weak + // Pull-Down Enable Value + // Description 1 The corresponding + // pin has a weak pull-down + // resistor. 0 The corresponding pin + // is not affected. Setting a bit in + // the GPIOPUR register clears the + // corresponding bit in the GPIOPDR + // register. The change is effective + // on the second clock cycle after + // the write if accessing GPIO via + // the APB memory aperture. If using + // AHB access@@ the change is + // effective on the next clock + // cycle. +#define GPIO_GPIO_PDR_PDE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register. +// +//****************************************************************************** +#define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Slew Rate + // Limit Enable (8-mA drive only) + // Value Description 1 Slew rate + // control is enabled for the + // corresponding pin. 0 Slew rate + // control is disabled for the + // corresponding pin. +#define GPIO_GPIO_SLR_SRL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register. +// +//****************************************************************************** +#define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Digital Enable + // Value Description 0 The digital + // functions for the corresponding + // pin are disabled. 1 The digital + // functions for the corresponding + // pin are enabled. +#define GPIO_GPIO_DEN_DEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register. +// +//****************************************************************************** +#define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in + // cc3xx. GPIO Lock A write of the + // value 0x4C4F.434B unlocks the + // GPIO Commit (GPIOCR) register for + // write access.A write of any other + // value or a write to the GPIOCR + // register reapplies the lock@@ + // preventing any register updates. + // A read of this register returns + // the following values: Value + // Description 0x1 The GPIOCR + // register is locked and may not be + // modified. 0x0 The GPIOCR register + // is unlocked and may be modified. +#define GPIO_GPIO_LOCK_LOCK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_CR register. +// +//****************************************************************************** +#define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) GPIO Commit + // Value Description The + // corresponding GPIOAFSEL@@ + // GPIOPUR@@ GPIOPDR@@ or GPIODEN + // bits can be written. 1 The + // corresponding GPIOAFSEL@@ + // GPIOPUR@@ GPIOPDR@@ or GPIODEN + // bits cannot be written. 0 Note: + // The default register type for the + // GPIOCR register is RO for all + // GPIO pins with the exception of + // the NMI pin and the four JTAG/SWD + // pins (PD7@@ PF0@@ and PC[3:0]). + // These six pins are the only GPIOs + // that are protected by the GPIOCR + // register. Because of this@@ the + // register type for GPIO Port D7@@ + // GPIO Port F0@@ and GPIO Port + // C[3:0] is R/W. The default reset + // value for the GPIOCR register is + // 0x0000.00FF for all GPIO pins@@ + // with the exception of the NMI pin + // and the four JTAG/SWD pins (PD7@@ + // PF0@@ and PC[3:0]). To ensure + // that the JTAG port is not + // accidentally programmed as GPIO + // pins@@ the PC[3:0] pins default + // to non-committable. Similarly@@ + // to ensure that the NMI pin is not + // accidentally programmed as a GPIO + // pin@@ the PD7 and PF0 pins + // default to non-committable. + // Because of this@@ the default + // reset value of GPIOCR for GPIO + // Port C is 0x0000.00F0@@ for GPIO + // Port D is 0x0000.007F@@ and for + // GPIO Port F is 0x0000.00FE. +#define GPIO_GPIO_CR_CR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register. +// +//****************************************************************************** +#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \ + 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) GPIO Analog + // Mode Select Value Description 1 + // The analog function of the pin is + // enabled@@ the isolation is + // disabled@@ and the pin is capable + // of analog functions. 0 The analog + // function of the pin is disabled@@ + // the isolation is enabled@@ and + // the pin is capable of digital + // functions as specified by the + // other GPIO configuration + // registers. Note: This register + // and bits are only valid for GPIO + // signals that share analog + // function through a unified I/O + // pad. The reset state of this + // register is 0 for all signals. + +#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register. +// +//****************************************************************************** +#define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 7 This field controls the + // configuration for GPIO pin 7. +#define GPIO_GPIO_PCTL_PMC7_S 28 +#define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 6 This field controls the + // configuration for GPIO pin 6. +#define GPIO_GPIO_PCTL_PMC6_S 24 +#define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 5 This field controls the + // configuration for GPIO pin 5. +#define GPIO_GPIO_PCTL_PMC5_S 20 +#define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 4 This field controls the + // configuration for GPIO pin 4. +#define GPIO_GPIO_PCTL_PMC4_S 16 +#define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 43 This field controls + // the configuration for GPIO pin 3. +#define GPIO_GPIO_PCTL_PMC3_S 12 +#define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 1 This field controls the + // configuration for GPIO pin 1. +#define GPIO_GPIO_PCTL_PMC1_S 8 +#define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 2 This field controls the + // configuration for GPIO pin 2. +#define GPIO_GPIO_PCTL_PMC2_S 4 +#define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 0 This field controls the + // configuration for GPIO pin 0. +#define GPIO_GPIO_PCTL_PMC0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_ADCCTL register. +// +//****************************************************************************** +#define GPIO_GPIO_ADCCTL_ADCEN_M \ + 0x000000FF // This register is not used in + // cc3xx. ADC trigger via GPIO is + // not supported. ADC Trigger Enable + // Value Description 1 The + // corresponding pin is used to + // trigger the ADC. 0 The + // corresponding pin is not used to + // trigger the ADC. + +#define GPIO_GPIO_ADCCTL_ADCEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_DMACTL register. +// +//****************************************************************************** +#define GPIO_GPIO_DMACTL_DMAEN_M \ + 0x000000FF // This register is not used in the + // cc3xx. Alternate register to + // support this feature is coded in + // the APPS_NWP_CMN space. refer + // register as offset 0x400F70D8 + // ?DMA Trigger Enable Value + // Description 1 The corresponding + // pin is used to trigger the ?DMA. + // 0 The corresponding pin is not + // used to trigger the ?DMA. + +#define GPIO_GPIO_DMACTL_DMAEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_SI register. +// +//****************************************************************************** +#define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value + // Description 1 Each pin has its + // own interrupt vector. 0 All port + // pin interrupts are OR'ed together + // to produce a summary interrupt. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID4 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID4_PID4_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [7:0] + +#define GPIO_GPIO_PERIPHID4_PID4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID5 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID5_PID5_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [15:8] + +#define GPIO_GPIO_PERIPHID5_PID5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID6 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID6_PID6_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [23:16] + +#define GPIO_GPIO_PERIPHID6_PID6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID7 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID7_PID7_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [31:24] + +#define GPIO_GPIO_PERIPHID7_PID7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID0 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID0_PID0_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [7:0] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID0_PID0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID1 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID1_PID1_M \ + 0x000000FF // GPIO Peripheral ID Register + // [15:8] Can be used by software to + // identify the presence of this + // peripheral. + +#define GPIO_GPIO_PERIPHID1_PID1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID2 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID2_PID2_M \ + 0x000000FF // This register is not used in + // CC3XX.v GPIO Peripheral ID + // Register [23:16] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID2_PID2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID3 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID3_PID3_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [31:24] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID3_PID3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID0 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID0_CID0_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [7:0] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID0_CID0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID1 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID1_CID1_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [15:8] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID1_CID1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID2 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID2_CID2_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [23:16] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID2_CID2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID3 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID3_CID3_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [31:24] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID3_CID3_S 0 + + + +#endif // __HW_GPIO_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_gprcm.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_gprcm.h new file mode 100644 index 000000000..a1b454062 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_gprcm.h @@ -0,0 +1,3324 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_GPRCM_H__ +#define __HW_GPRCM_H__ + +//***************************************************************************** +// +// The following are defines for the GPRCM register offsets. +// +//***************************************************************************** +#define GPRCM_O_APPS_SOFT_RESET 0x00000000 +#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \ + 0x00000004 + +#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \ + 0x00000008 + +#define GPRCM_O_APPS_RESET_CAUSE \ + 0x0000000C + +#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \ + 0x00000010 + +#define GPRCM_O_APPS_SRAM_DSLP_CFG \ + 0x00000018 + +#define GPRCM_O_APPS_SRAM_LPDS_CFG \ + 0x0000001C + +#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \ + 0x00000020 + +#define GPRCM_O_TOP_DIE_ENABLE 0x00000100 +#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \ + 0x00000104 + +#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \ + 0x00000108 + +#define GPRCM_O_ADC_CLK_CONFIG 0x0000010C +#define GPRCM_O_APPS_GPIO_WAKE_CONF \ + 0x00000110 + +#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \ + 0x00000114 + +#define GPRCM_O_MEM_HCLK_DIV_CFG \ + 0x00000118 + +#define GPRCM_O_MEM_SYSCLK_DIV_CFG \ + 0x0000011C + +#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \ + 0x00000120 + +#define GPRCM_O_NWP_SOFT_RESET 0x00000400 +#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \ + 0x00000404 + +#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \ + 0x00000408 + +#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C +#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \ + 0x00000410 + +#define GPRCM_O_NWP_SRAM_DSLP_CFG \ + 0x00000418 + +#define GPRCM_O_NWP_SRAM_LPDS_CFG \ + 0x0000041C + +#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \ + 0x00000420 + +#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \ + 0x00000424 + +#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \ + 0x00000428 + +#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \ + 0x0000042C + +#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \ + 0x00000430 + +#define GPRCM_O_NWP_GPIO_WAKE_CONF \ + 0x00000434 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \ + 0x00000438 + +#define GPRCM_O_GPRCM_DIEID_READ_REG5 \ + 0x00000448 + +#define GPRCM_O_GPRCM_DIEID_READ_REG6 \ + 0x0000044C + +#define GPRCM_O_REF_FSM_CFG0 0x00000800 +#define GPRCM_O_REF_FSM_CFG1 0x00000804 +#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \ + 0x00000808 + +#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \ + 0x0000080C + +#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \ + 0x00000810 + +#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \ + 0x00000814 + +#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \ + 0x00000818 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \ + 0x0000081C + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \ + 0x00000820 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \ + 0x00000824 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \ + 0x00000828 + +#define GPRCM_O_SPARE_RW0 0x0000082C +#define GPRCM_O_SPARE_RW1 0x00000830 +#define GPRCM_O_APLLMCS_MCU_OVERRIDES \ + 0x00000834 + +#define GPRCM_O_SYSCLK_SWITCH_STATUS \ + 0x00000838 + +#define GPRCM_O_REF_LDO_CONTROLS \ + 0x0000083C + +#define GPRCM_O_REF_RTRIM_CONTROL \ + 0x00000840 + +#define GPRCM_O_REF_SLICER_CONTROLS0 \ + 0x00000844 + +#define GPRCM_O_REF_SLICER_CONTROLS1 \ + 0x00000848 + +#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \ + 0x0000084C + +#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \ + 0x00000850 + +#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \ + 0x00000854 + +#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \ + 0x00000858 + +#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \ + 0x0000085C + +#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \ + 0x00000860 + +#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \ + 0x00000864 + +#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868 +#define GPRCM_O_MEMSS_PWR_PS 0x0000086C +#define GPRCM_O_REF_FSM_DEBUG 0x00000870 +#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \ + 0x00000874 + +#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \ + 0x00000878 + +#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \ + 0x0000087C + +#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \ + 0x00000880 + +#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \ + 0x00000884 + +#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \ + 0x00000888 + +#define GPRCM_O_MEM_REF_FSM_CFG2 \ + 0x0000088C + +#define GPRCM_O_TESTCTRL_POWER_CTRL \ + 0x00000C10 + +#define GPRCM_O_SSDIO_POWER_CTRL \ + 0x00000C14 + +#define GPRCM_O_MCSPI_N1_POWER_CTRL \ + 0x00000C18 + +#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C +#define GPRCM_O_WL_SDIO_POWER_CTRL \ + 0x00000C20 + +#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \ + 0x00000C24 + +#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \ + 0x00000C28 + +#define GPRCM_O_APPS_SECURE_INIT_DONE \ + 0x00000C30 + +#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \ + 0x00000C34 + +#define GPRCM_O_EN_APPS_REBOOT 0x00000C38 +#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \ + 0x00000C3C + +#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \ + 0x00000C40 + +#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \ + 0x00000C44 + +#define GPRCM_O_NWP_PWR_STATE 0x00000C48 +#define GPRCM_O_APPS_PWR_STATE 0x00000C4C +#define GPRCM_O_MCU_PWR_STATE 0x00000C50 +#define GPRCM_O_WTOP_PM_PS 0x00000C54 +#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \ + 0x00000C58 + +#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \ + 0x00000C5C + +#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \ + 0x00000C60 + +#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \ + 0x00000C64 + +#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \ + 0x00000C68 + +#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \ + 0x00000C6C + +#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \ + 0x00000C70 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \ + 0x00000C78 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \ + 0x00000C7C + +#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \ + 0x00000C80 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \ + 0x00000C84 + +#define GPRCM_O_WTOP_MEM_RET_CFG \ + 0x00000C88 + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \ + 0x00000C8C + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \ + 0x00000C90 + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \ + 0x00000C94 + +#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \ + 0x00000C98 + +#define GPRCM_O_DCDC_CLK_GEN_CONFIG \ + 0x00000C9C + +#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \ + 0x00000CA0 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \ + 0x00000CA4 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \ + 0x00000CA8 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \ + 0x00000CAC + +#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \ + 0x00000CB0 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \ + 0x00000CB4 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \ + 0x00000CB8 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \ + 0x00000CBC + +#define GPRCM_O_GPRCM_DIEID_READ_REG0 \ + 0x00000CC0 + +#define GPRCM_O_GPRCM_DIEID_READ_REG1 \ + 0x00000CC4 + +#define GPRCM_O_GPRCM_DIEID_READ_REG2 \ + 0x00000CC8 + +#define GPRCM_O_GPRCM_DIEID_READ_REG3 \ + 0x00000CCC + +#define GPRCM_O_GPRCM_DIEID_READ_REG4 \ + 0x00000CD0 + +#define GPRCM_O_APPS_SS_OVERRIDES \ + 0x00000CD4 + +#define GPRCM_O_NWP_SS_OVERRIDES \ + 0x00000CD8 + +#define GPRCM_O_SHARED_SS_OVERRIDES \ + 0x00000CDC + +#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \ + 0x00000CE0 + +#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \ + 0x00000CE4 + +#define GPRCM_O_MCU_PSCON_OVERRIDES \ + 0x00000CE8 + +#define GPRCM_O_WTOP_PSCON_OVERRIDES \ + 0x00000CEC + +#define GPRCM_O_WELP_PSCON_OVERRIDES \ + 0x00000CF0 + +#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \ + 0x00000CF4 + +#define GPRCM_O_MCSPI_PSCON_OVERRIDES \ + 0x00000CF8 + +#define GPRCM_O_SSDIO_PSCON_OVERRIDES \ + 0x00000CFC + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \ + 0x00000002 // Soft-reset1 for APPS : Cortex + // sysrstn is asserted and in + // addition to that the associated + // APPS Peripherals are also reset. + // This is an auto-clear bit. + +#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \ + 0x00000001 // Soft-reset0 for APPS : Only + // sys-resetn for Cortex will be + // asserted. This is an auto-clear + // bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKEUP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \ + 0x000000FF // Mask for LPDS Wakeup interrupt : + // [7] - Host IRQ from NWP [6] - + // NWP_LPDS_Wake_irq (TRUE_LPDS) [5] + // - NWP Wake-request to APPS [4] - + // GPIO [3:1] - Reserved [0] - LPDS + // Wakeup-timer + +#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKEUP_SRC register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \ + 0x000000FF // Indicates the cause for wakeup + // from LPDS : [7] - Host IRQ from + // NWP [6] - NWP_LPDS_Wake_irq + // (TRUE_LPDS) [5] - NWP + // Wake-request to APPS [4] - GPIO + // [3:1] - Reserved [0] - LPDS + // Wakeup-timer + +#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_RESET_CAUSE register. +// +//****************************************************************************** +#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \ + 0x000000FF // Indicates the reset cause for + // APPS : "0000" - Wake from HIB/OFF + // mode; "0001" - Wake from LPDS ; + // "0010" - Reserved ; "0011" - + // Soft-reset0 (Only APPS + // Cortex-sysrstn is asserted); + // "0100" - Soft-reset1 (APPS + // Cortex-sysrstn and APPS + // peripherals are reset); "0101" - + // WDOG0 (APPS Cortex-sysrstn and + // APPS peripherals are reset); + // "0110" - MCU Soft-reset (APPS + + // NWP Cortex-sysrstn + Peripherals + // are reset); "0111" - Secure Init + // done (Indication that reset has + // happened after DevInit); "1000" - + // Dev Mode Patch Init done (During + // development mode, patch + // downloading and Cortex + // re-vectoring is completed) + +#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \ + 0xFFFFFFFF // OPP Request Configuration + // (Number of slow-clk cycles) for + // LPDS Wake-timer : This + // configuration implies the RTC + // time-stamp, which must be few + // slow-clks prior to + // APPS_LPDS_WAKETIME_WAKE_CFG, such + // that by the time actual wakeup is + // given, OPP is already switched to + // ACTIVE (RUN). + +#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SRAM_DSLP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \ + 0x000FFFFF // Configuration of APPS Memories + // during Deep-sleep : 0 - SRAMs are + // OFF ; 1 - SRAMs are Retained. + // APPS SRAM Cluster information : + // [0] - 1st column in MEMSS + // (Applicable only when owned by + // APPS); [1] - 2nd column in MEMSS + // (Applicable only when owned by + // APPS); [2] - 3rd column in MEMSS + // (Applicable only when owned by + // APPS) ; [3] - 4th column in MEMSS + // (Applicable only when owned by + // APPS) ; [16] - MCU-PD - Apps + // cluster 0 (TBD); [19:18] - + // Reserved. + +#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SRAM_LPDS_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \ + 0x000FFFFF // Configuration of APPS Memories + // during LPDS : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. APPS SRAM + // Cluster information : [0] - 1st + // column in MEMSS (Applicable only + // when owned by APPS); [1] - 2nd + // column in MEMSS (Applicable only + // when owned by APPS); [2] - 3rd + // column in MEMSS (Applicable only + // when owned by APPS) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by APPS) ; [16] - + // MCU-PD - Apps cluster 0 (TBD); + // [19:18] - Reserved. + +#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \ + 0xFFFFFFFF // Configuration (in no of + // slow_clks) which says when the + // actual wakeup request for + // removing the PD-reset be given. + +#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_ENABLE register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \ + 0x00001000 + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \ + 0x00000F00 + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8 +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \ + 0x00000002 // 1 - Top-die is enabled ; + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \ + 0x00000001 // 1 - Enable the top-die ; 0 - + // Disable the top-die + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \ + 0xF0000000 // Configuration (in slow_clks) for + // number of clks between + // Flash-3p3-rstn to D2D POR Resetn. + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28 +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \ + 0x00FF0000 // Configuration (in slow_clks) for + // number of clks between Top-die + // Switch-Enable and Top-die Flash + // 3p3 Reset removal + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16 +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \ + 0x000000FF // Configuration (in slow_clks) for + // number of clks between D2D POR + // Reset removal and bottom die FMC + // reset removal + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_GLOBAL_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \ + 0x00000001 // 1 - Assert the global reset for + // MCU (APPS + NWP) ; Asserts both + // Cortex sysrstn and its + // peripherals 0 - Deassert the + // global reset for MCU (APPS + NWP) + // ; Asserts both Cortex sysrstn and + // its peripherals Note : Reset for + // shared peripherals is not + // affected here. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_ADC_CLK_CONFIG register. +// +//****************************************************************************** +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \ + 0x000007C0 // Configuration (in number of 38.4 + // MHz clks) for the OFF-Time in + // generation of ADC_CLK + +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6 +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \ + 0x0000003E // Configuration (in number of 38.4 + // MHz clks) for the ON-Time in + // generation of ADC_CLK + +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1 +#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \ + 0x00000001 // 1 - Enable the ADC_CLK ; 0 - + // Disable the ADC_CLK + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \ + 0x00000003 // "00" - Wake on Level0 on + // selected GPIO pin (GPIO is + // selected inside the HIB3p3 + // module); "01" - Wakeup on + // fall-edge of GPIO pin. + +#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register. +// +//****************************************************************************** +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \ + 0xFFFFFFFE + +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1 +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \ + 0x00000001 // 1 - Override the secure-mode + // done for booting up NWP (Wakeup + // NWP on its event independent of + // CM4 state) ; 0 - Donot override + // the secure-mode done for NWP boot + // (NWP must be enabled by CM4 only) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_HCLK_DIV_CFG register. +// +//****************************************************************************** +#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \ + 0x00000007 // Division configuration for + // HCLKDIVOUT : "000" - Divide by 1 + // ; "001" - Divide by 2 ; "010" - + // Divide by 3 ; "011" - Divide by 4 + // ; "100" - Divide by 5 ; "101" - + // Divide by 6 ; "110" - Divide by 7 + // ; "111" - Divide by 8 + +#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SYSCLK_DIV_CFG register. +// +//****************************************************************************** +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \ + 0x00000038 + +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3 +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \ + 0x00000007 + +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_LOCK_TIME_CONF register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \ + 0x0000FF00 + +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8 +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \ + 0x000000FF + +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \ + 0x00000002 // Soft-reset1 for NWP - Cortex + // sysrstn and NWP associated + // peripherals are - This is an + // auto-clr bit. + +#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \ + 0x00000001 // Soft-reset0 for NWP - Only + // Cortex-sysrstn is asserted - This + // is an auto-clear bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKEUP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \ + 0x000000FF // Mask for LPDS Wakeup interrupt : + // 7 - WLAN Host Interrupt ; 6 - + // WLAN to NWP Wake request ; 5 - + // APPS to NWP Wake request; 4 - + // GPIO Wakeup ; 3 - Autonomous UART + // Wakeup ; 2 - SSDIO Wakeup ; 1 - + // Autonomous SPI Wakeup ; 0 - LPDS + // Wakeup-timer + +#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKEUP_SRC register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \ + 0x000000FF // Indicates the cause for NWP + // LPDS-Wakeup : 7 - WLAN Host + // Interrupt ; 6 - WLAN to NWP Wake + // request ; 5 - APPS to NWP Wake + // request; 4 - GPIO Wakeup ; 3 - + // Autonomous UART Wakeup ; 2 - + // SSDIO Wakeup ; 1 - Autonomous SPI + // Wakeup ; 0 - LPDS Wakeup-timer + +#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_RESET_CAUSE register. +// +//****************************************************************************** +#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \ + 0x000000FF // Indicates the reset cause for + // NWP : "0000" - Wake from HIB/OFF + // mode; "0001" - Wake from LPDS ; + // "0010" - Reserved ; "0011" - + // Soft-reset0 (Only NWP + // Cortex-sysrstn is asserted); + // "0100" - Soft-reset1 (NWP + // Cortex-sysrstn and NWP + // peripherals are reset); "0101" - + // WDOG0 (NWP Cortex-sysrstn and NWP + // peripherals are reset); "0110" - + // MCU Soft-reset (APPS + NWP + // Cortex-sysrstn + Peripherals are + // reset); "0111" - SSDIO Function2 + // reset (Only Cortex-sysrstn is + // asserted) ; "1000" - Reset due to + // WDOG of APPS (NWP Cortex-sysrstn + // and NWP peripherals are reset); + +#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \ + 0xFFFFFFFF // OPP Request Configuration + // (Number of slow-clk cycles) for + // LPDS Wake-timer + +#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SRAM_DSLP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \ + 0x000FFFFF // Configuration of NWP Memories + // during DSLP : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. NWP SRAM + // Cluster information : [2] - 3rd + // column in MEMSS (Applicable only + // when owned by NWP) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by NWP) ; [4] - 5th + // column in MEMSS (Applicable only + // when owned by NWP) ; [5] - 6th + // column in MEMSS (Applicable only + // when owned by NWP) ; [6] - 7th + // column in MEMSS (Applicable only + // when owned by NWP) ; [7] - 8th + // column in MEMSS (Applicable only + // when owned by NWP) ; [8] - 9th + // column in MEMSS (Applicable only + // when owned by NWP) ; [9] - 10th + // column in MEMSS (Applicable only + // when owned by NWP) ; [10] - 11th + // column in MEMSS (Applicable only + // when owned by NWP) ; [11] - 12th + // column in MEMSS (Applicable only + // when owned by NWP) ; [12] - 13th + // column in MEMSS (Applicable only + // when owned by NWP) ; [13] - 14th + // column in MEMSS (Applicable only + // when owned by NWP) ; [14] - 15th + // column in MEMSS (Applicable only + // when owned by NWP) ; [19:18] - + // Reserved. + +#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SRAM_LPDS_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \ + 0x000FFFFF // Configuration of NWP Memories + // during LPDS : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. NWP SRAM + // Cluster information : [2] - 3rd + // column in MEMSS (Applicable only + // when owned by NWP) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by NWP) ; [4] - 5th + // column in MEMSS (Applicable only + // when owned by NWP) ; [5] - 6th + // column in MEMSS (Applicable only + // when owned by NWP) ; [6] - 7th + // column in MEMSS (Applicable only + // when owned by NWP) ; [7] - 8th + // column in MEMSS (Applicable only + // when owned by NWP) ; [8] - 9th + // column in MEMSS (Applicable only + // when owned by NWP) ; [9] - 10th + // column in MEMSS (Applicable only + // when owned by NWP) ; [10] - 11th + // column in MEMSS (Applicable only + // when owned by NWP) ; [11] - 12th + // column in MEMSS (Applicable only + // when owned by NWP) ; [12] - 13th + // column in MEMSS (Applicable only + // when owned by NWP) ; [13] - 14th + // column in MEMSS (Applicable only + // when owned by NWP) ; [14] - 15th + // column in MEMSS (Applicable only + // when owned by NWP) ; [19:18] - + // Reserved. + +#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \ + 0xFFFFFFFF // Wake time configuration (no of + // slow clks) for NWP wake from + // LPDS. + +#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register. +// +//****************************************************************************** +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \ + 0xFFFE0000 + +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17 +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \ + 0x00010000 // 0 - APPS is selected as host for + // Autonms SPI ; 1 - External host + // is selected as host for Autonms + // SPI + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register. +// +//****************************************************************************** +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \ + 0x00010000 + +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \ + 0x00000002 // When 1 => IDLE-mode is + // acknowledged by the SPI-IP. (This + // is for MCSPI_N1) + +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \ + 0x00000001 // When 1 => Request for IDLE-mode + // for autonomous SPI. (This is for + // MCSPI_N1) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register. +// +//****************************************************************************** +#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \ + 0x00000001 // 1 - Request for waking up NWP + // from any of its low-power modes + // (SLP/DSLP/LPDS) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register. +// +//****************************************************************************** +#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \ + 0x00000001 // 1 - Request for wakinp up WLAN + // from its ELP Mode (This gets + // triggered to ELP-logic of WLAN) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \ + 0x00000003 // "00" - Wakeup on level0 of the + // selected GPIO (GPIO gets selected + // inside HIB3P3-module); "01" - + // Wakeup on fall-edge of selected + // GPIO. + +#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG12 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \ + 0x0000FFFF // This corrsponds to ROW_32 + // [31:16] of the FUSEFARM. SPARE + +#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG5 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \ + 0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM + // : [5:0] - ADC OFFSET ; [13:6] - + // TEMP_SENSE ; [14:14] - DFT_GSG ; + // [15:15] - FMC_DISABLE ; [31:16] - + // WLAN_MAC ID + +#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG6 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \ + 0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM + // : [31:0] : WLAN MAC ID + +#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_CFG0 register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \ + 0x00FF0000 // ANA-BGAP Settling time (In + // number of slow_clks) + +#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16 +#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \ + 0x0000FF00 // Slicer LDO settling time (In + // number of slow clks) + +#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8 +#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \ + 0x000000FF // Dig-buffer settling time (In + // number of slow clks) + +#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_CFG1 register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \ + 0xFF000000 // XTAL settling time (In number of + // slow clks) + +#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24 +#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \ + 0x00FF0000 // LV Slicer settling time + +#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16 +#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \ + 0x0000FF00 // HV Slicer Pull-down settling + // time + +#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8 +#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \ + 0x000000FF // HV Slicer settling time + +#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \ + 0x00007F00 // Configuration for WLAN APLLMCS - + // N[6:0], if the XTAL frequency is + // 40 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8 +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \ + 0x000000FF // Configuration for WLAN APLLMCS - + // M[7:0], if the XTAL frequency is + // 40 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \ + 0x00000010 // Configuration for WLAN APLLMCS - + // if the XTAL frequency if 40 MHz + // (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \ + 0x00000008 // Configuration for WLAN APLLMCS - + // Sel96, if the XTAL frequency is + // 40 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \ + 0x00000007 // Configuration for WLAN APLLMCS - + // Selinpfreq, if the XTAL frequency + // is 40 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \ + 0x00007F00 // Configuration for WLAN APLLMCS - + // N[6:0], if the XTAL frequency is + // 26 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8 +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \ + 0x000000FF // Configuration for WLAN APLLMCS - + // M[7:0], if the XTAL frequency is + // 26 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \ + 0x00000010 // Configuration for WLAN APLLMCS - + // if the XTAL frequency if 26 MHz + // (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \ + 0x00000008 // Configuration for WLAN APLLMCS - + // Sel96, if the XTAL frequency is + // 26 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \ + 0x00000007 // Configuration for WLAN APLLMCS - + // Selinpfreq, if the XTAL frequency + // is 26 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \ + 0x00080000 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \ + 0x00070000 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16 +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \ + 0x00000700 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8 +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \ + 0x00000020 // Override control for + // WLAN_APLLMCS_M[8]. When set to1, + // M[8] will be selected by bit [3]. + // (Else controlled from WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \ + 0x00000010 // Override for WLAN_APLLMCS_M[8]. + // Applicable only when bit [4] is + // set to 1. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \ + 0x00000004 // Override control for + // WLAN_APLLMCS_N[8:7]. When set + // to1, N[8:7] will be selected by + // bits [2:1]. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \ + 0x00000003 // Override value for + // WLAN_APLLMCS_N[8:7] bits. + // Applicable only when bit [1] is + // set to 1. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \ + 0x38000000 + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \ + 0x07000000 + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \ + 0x007F0000 // Configuration for MCU-APLLMCS : + // N during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \ + 0x0000FF00 // Configuration for MCU-APLLMCS : + // M during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // M[8] during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \ + 0x00000003 // Configuration for MCU-APLLMCS : + // N[8:7] during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // HISPEED during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \ + 0x00000008 // Configuration for MCU-APLLMCS : + // SEL96 during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \ + 0x00000007 // Configuration for MCU-APLLMCS : + // SELINPFREQ during RUN mode. + // Selected if the XTAL frequency is + // 38.4 MHz (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \ + 0x007F0000 // Configuration for MCU-APLLMCS : + // N during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \ + 0x0000FF00 // Configuration for MCU-APLLMCS : + // M during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // M[8] during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \ + 0x00000003 // Configuration for MCU-APLLMCS : + // N[8:7] during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // HISPEED during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \ + 0x00000008 // Configuration for MCU-APLLMCS : + // SEL96 during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \ + 0x00000007 // Configuration for MCU-APLLMCS : + // SELINPFREQ during RUN mode. + // Selected if the XTAL frequency is + // 26 MHz (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \ + 0x00000400 // 1 - APLLMCS_MCU is locked ; 0 - + // APLLMCS_MCU is not locked + +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \ + 0x00000200 // Override for APLLMCS_MCU Enable. + // Applicable if bit [8] is set + +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \ + 0x00000100 // 1 - Enable for APLLMCS_MCU comes + // from bit [9]. 0 - Enable for + // APLLMCS_MCU comes from FSM. + +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \ + 0x00000006 // Override for sysclk src + // (applicable only if bit [0] is + // set to 1. "00"- SLOW_CLK "01"- + // XTAL_CLK "10"- PLL_CLK + +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1 +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \ + 0x00000001 // 1 - Sysclk src is selected from + // bits [2:1] of this register. 0 - + // Sysclk src is selected from FSM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SYSCLK_SWITCH_STATUS register. +// +//****************************************************************************** +#define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \ + 0x00000001 // 1 - Sysclk switching is + // complete. 0 - Sysclk switching is + // in progress. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_LDO_CONTROLS register. +// +//****************************************************************************** +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \ + 0x00010000 // 1 - Enable for REF_LDO comes + // from bit [0] of this register ; 0 + // - Enable for REF_LDO comes from + // the FSM. Note : Final REF_LDO_EN + // reaches on the port + // TOP_PM_REG2[0] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \ + 0x0000C000 // Spare bits for REF_CTRL_FSM. + // Reaches directly on port + // TOP_PM_REG2[15:14] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14 +#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \ + 0x00003800 // REF TLOAD Enable. Reaches + // directly on port + // TOP_PM_REG2[13:11] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11 +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \ + 0x00000700 // REF_LDO Test-mux control. + // Reaches directly on port + // TOP_PM_REG2[10:8] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8 +#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \ + 0x000000C0 // REF BW Control. Reaches directly + // on port TOP_PM_REG2[7:6] of + // gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6 +#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \ + 0x0000003C // REF VTRIM Control. Reaches + // directly on port TOP_PM_REG2[5:2] + // of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2 +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \ + 0x00000002 // REF LDO Bypass Enable. Reaches + // directly on port TOP_PM_REG2[1] + // of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \ + 0x00000001 // Override for REF_LDO Enable. + // Applicable only if bit [16] of + // this register is set. Note : + // Final REF_LDO_EN reaches on the + // port TOP_PM_REG2[0] of gprcm. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_RTRIM_CONTROL register. +// +//****************************************************************************** +#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \ + 0x18000000 // This is [5:4] bits of + // TOP_PM_REG0 + +#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27 +#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \ + 0x07FF0000 // This is [15:5] bits of + // TOP_CLKM_REG0 + +#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16 +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \ + 0x00000100 // 1 - CLKM_RTRIM comes for + // bits[4:0] of this register. 0 - + // CLKM_RTRIM comes from Efuse + // (after efuse_done = 1). + +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \ + 0x0000001F // CLKM_TRIM Override. Applicable + // when efuse_done = 0 or bit[8] is + // set to 1. + +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_SLICER_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \ + 0x00200000 // 1 - EN_DIG_BUF_TOP comes from + // bit [14] of this register. 0 - + // EN_DIG_BUF_TOP comes from the + // FSM. Note : Final EN_DIG_BUF_WLAN + // reaches on TOP_CLKM_REG1_IN[14] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \ + 0x00100000 // 1 - EN_DIG_BUF_TOP comes from + // bit [15] of this register. 0 - + // EN_DIG_BUF_TOP comes from the + // FSM. Note : Final EN_DIG_BUF_TOP + // reaches on TOP_CLKM_REG1_IN[15] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \ + 0x00080000 // 1 - EN_XTAL comes from bit [3] + // of this register. 0 - EN_XTAL + // comes from FSM. Note : Final + // XTAL_EN reaches on + // TOP_CLKM_REG1_IN[3] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \ + 0x00040000 // 1 - Enable HV Slicer comes from + // bit [2] of this register. 0 - + // Enable HV Slicer comes from FSM. + // Note : Final HV_SLICER_EN reaches + // on port TOP_CLKM_REG1_IN[1] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \ + 0x00020000 // 1 - Enable LV Slicer comes from + // bit[1] of this register. 0 - + // Enable LV Slicer comes from FSM. + // Note : final LV_SLICER_EN reaches + // on port TOP_CLKM_REG1_IN[2] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \ + 0x00010000 // 1 - Enable HV Pull-down comes + // from bit[0] of this register. 0 - + // Enable HV Pull-down comes from + // FSM. Note : Final HV_PULL_DOWN + // reaches on port + // TOP_CLKM_REG1_IN[0] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \ + 0x00008000 // Override for EN_DIG_BUF_TOP. + // Applicable if bit[20] is set to + // 1. Note : Final EN_DIG_BUF_TOP + // reaches on TOP_CLKM_REG1_IN[15] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \ + 0x00004000 // Override for EN_DIG_BUF_WLAN. + // Applicable if bit[19] is set to + // 1. Note : Final EN_DIG_BUF_WLAN + // reaches on TOP_CLKM_REG1_IN[14] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \ + 0x00002000 // CLKOUT Flip Enable. Reaches on + // bit[13] of TOP_CLKM_REG1_IN[13] + // port of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \ + 0x00001000 // Enable divide2 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[12] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \ + 0x00000800 // Enable divide3 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[11] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \ + 0x00000400 // Enable divide4 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[10] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \ + 0x000003C0 // CM Test-mux select. Reaches on + // TOP_CLMM_REG1_IN[9:6] port of + // gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6 +#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \ + 0x00000030 // Slicer spare0 control. Reaches + // on TOP_CLKM_REG1_IN[5:4] port of + // gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4 +#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \ + 0x00000008 // Enable XTAL override. Reaches on + // TOP_CLKM_REG1_IN[3] port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \ + 0x00000004 // Enable HV Slicer override. + // Reaches on TOP_CLKM_REG1_IN[1] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \ + 0x00000002 // Enable LV Slicer override. + // Reaches on TOP_CLKM_REG1_IN[2] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \ + 0x00000001 // Enable HV Pull-down override. + // Reaches on TOP_CLKM_REG1_IN[0] + // port of gprcm + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_SLICER_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \ + 0x0000FC00 // Slicer spare1. Reaches on port + // TOP_CLKM_REG2_IN[15:10] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10 +#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \ + 0x000003F0 // XOSC Trim. Reaches on port + // TOP_CLKM_REG2_IN[9:4] of gprcm + +#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4 +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \ + 0x00000008 // Slicer ITRIM Toggle. Reaches on + // port TOP_CLKM_REG2_IN[3] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \ + 0x00000007 // LV Slicer trim. Reaches on port + // TOP_CLKM_REG2_IN[2:0] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_BGAP_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \ + 0xFF800000 + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \ + 0x00400000 // 1 - REF_MAG_TRIM comes from + // bit[4:0] of register + // REF_ANA_BGAP_CONTROLS1 [Addr : + // 0x0850]; 0 - REF_MAG_TRIM comes + // from efuse (After efc_done = 1). + // Note : Final REF_MAG_TRIM reaches + // on port TOP_PM_REG1[4:0] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \ + 0x00200000 // 1 - REF_V2I_TRIM comes from + // bit[9:6] of this register ; 0 - + // REF_V2I_TRIM comes from efuse + // (After efc_done = 1). Note : + // Final REF_V2I_TRIM reaches on + // port TOP_PM_REG0[9:6] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \ + 0x00100000 // 1 - REF_TEMP_TRIM comes from + // bit[15:10] of this register ; 0 - + // REF_TEMP_TRIM comes from efuse + // (After efc_done = 1). Note : + // Final REF_TEMP_TRIM reaches on + // port TOP_PM_REG0[15:10] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \ + 0x00080000 // 1 - REF_STARTUP_EN comes from + // bit [3] of this register ; 0 - + // REF_STARTUP_EN comes from FSM. + // Note : Final REF_STARTUP_EN + // reaches on port TOP_PM_REG0[3] of + // gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \ + 0x00040000 // 1 - REF_V2I_EN comes from bit + // [2] of this register ; 0 - + // REF_V2I_EN comes from FSM. Note : + // Final REF_V2I_EN reaches on port + // TOP_PM_REG0[2] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \ + 0x00020000 // 1 - REF_FC_EN comes from bit [1] + // of this register ; 0 - REF_FC_EN + // comes from FSM. Note : Final + // REF_FC_EN reaches on port + // TOP_PM_REG0[1] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \ + 0x00010000 // 1 - REF_BGAP_EN comes from bit + // [0] of this register ; 0 - + // REF_BGAP_EN comes from FSM. Note + // : Final REF_BGAP_EN reaches on + // port TOP_PM_REG0[0] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \ + 0x0000FC00 // REF_TEMP_TRIM override. + // Applicable when bit [20] of this + // register set to 1. (or efc_done = + // 0) Note : Final REF_TEMP_TRIM + // reaches on port + // TOP_PM_REG0[15:10] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \ + 0x000003C0 // REF_V2I_TRIM Override. + // Applicable when bit [21] of this + // register set to 1 . (of efc_done + // = 0) Note : Final REF_V2I_TRIM + // reaches on port TOP_PM_REG0[9:6] + // of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \ + 0x00000030 + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \ + 0x00000008 // REF_STARTUP_EN override. + // Applicable when bit [19] of this + // register is set to 1. Note : + // Final REF_STARTUP_EN reaches on + // port TOP_PM_REG0[3] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \ + 0x00000004 // REF_V2I_EN override. Applicable + // when bit [21] of this register is + // set to 1. Note : Final REF_V2I_EN + // reaches on port TOP_PM_REG0[2] of + // gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \ + 0x00000002 // REF_FC_EN override. Applicable + // when bit [17] of this register is + // set to 1. Note : Final REF_FC_EN + // reaches on port TOP_PM_REG0[1] of + // gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \ + 0x00000001 // REF_BGAP_EN override. Applicable + // when bit [16] of this register + // set to 1. Note : Final + // REF_BGAP_EN reaches on port + // TOP_PM_REG0[0] of gprcm. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_BGAP_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \ + 0xFFFF0000 + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \ + 0x0000C000 // REF_BGAP_SPARE. Reaches on port + // TOP_PM_REG1[15:14] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \ + 0x00003E00 // REF_BGAP_TMUX_CTRL. Reaches on + // port TOP_PM_REG1[13:9] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \ + 0x000001E0 // REF_FILT_TRIM. Reaches on port + // TOP_PM_REG1[8:5] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \ + 0x0000001F // REF_MAG_TRIM Override. + // Applicable when bit[22] of + // REF_ANA_BGAP_CONTROLS0 [0x084C] + // set to 1 (of efc_done = 0). Note + // : Final REF_MAG_TRIM reaches on + // port TOP_PM_REG1[4:0] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_SPARE_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \ + 0xFFFF0000 + +#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16 +#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \ + 0x0000FFFF // Spare control. Reaches on + // TOP_PM_REG3 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_SPARE_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \ + 0xFFFF0000 // Spare control. Reaches on + // TOP_CLKM_REG3 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16 +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \ + 0x0000FFFF // Spare control. Reaches on + // TOP_CLKM_REG4 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PSCON_OVERRIDES0 register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \ + 0xFFFF0000 + +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16 +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \ + 0x0000FFFF + +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PSCON_OVERRIDES1 register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6 +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \ + 0x00000020 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \ + 0x00000010 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \ + 0x00000008 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \ + 0x00000004 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \ + 0x00000002 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_PLL_REF_LOCK_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3 +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \ + 0x00000004 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \ + 0x00000002 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PSCON_DEBUG register. +// +//****************************************************************************** +#define GPRCM_MCU_PSCON_DEBUG_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_MCU_PSCON_DEBUG_reserved_S 6 +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \ + 0x00000038 // MCU_PSCON_RTC_ON = "0000"; + // MCU_PSCON_RTC_OFF = "0001"; + // MCU_PSCON_RTC_RET = "0010"; + // MCU_PSCON_RTC_OFF_TO_ON = "0011"; + // MCU_PSCON_RTC_RET_TO_ON = "0100"; + // MCU_PSCON_RTC_ON_TO_RET = "0101"; + // MCU_PSCON_RTC_ON_TO_OFF = "0110"; + // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP + // = "0111"; + // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP + // = "1000"; + +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3 +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \ + 0x00000007 + +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PWR_PS register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PWR_PS_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_MEMSS_PWR_PS_reserved_S 3 +#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \ + 0x00000007 // MEMSS_PM_SLEEP = "000"; + // MEMSS_PM_WAIT_OPP = "010"; + // MEMSS_PM_ACTIVE = "011"; + // MEMSS_PM_SLEEP_TO_ACTIVE = "100"; + // MEMSS_PM_ACTIVE_TO_SLEEP = "101"; + +#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_DEBUG register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_DEBUG_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_REF_FSM_DEBUG_reserved_S 6 +#define GPRCM_REF_FSM_DEBUG_fref_mode_M \ + 0x00000030 // 01 - HV Mode ; 10 - LV Mode ; 11 + // - XTAL Mode + +#define GPRCM_REF_FSM_DEBUG_fref_mode_S 4 +#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \ + 0x0000000F // constant FREF_CLK_OFF = "00000"; + // constant FREF_EN_BGAP = "00001"; + // constant FREF_EN_LDO = "00010"; + // constant FREF_EN_SLI_HV = + // "00011"; constant + // FREF_EN_SLI_HV_PD = "00100"; + // constant FREF_EN_DIG_BUF = + // "00101"; constant FREF_EN_OSC = + // "00110"; constant FREF_EN_SLI_LV + // = "00111"; constant + // FREF_EN_CLK_REQ = "01000"; + // constant FREF_CLK_VALID = + // "01001"; constant FREF_MODE_DET0 + // = "01010"; constant + // FREF_MODE_DET1 = "01011"; + // constant FREF_MODE_DET2 = + // "10010"; constant FREF_MODE_DET3 + // = "10011"; constant FREF_VALID = + // "01100"; constant FREF_VALID0 = + // "01101"; constant FREF_VALID1 = + // "01110"; constant FREF_VALID2 = + // "01111"; constant + // FREF_WAIT_EXT_TCXO0 = "10000"; + // constant FREF_WAIT_EXT_TCXO1 = + // "10001"; + +#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register. +// +//****************************************************************************** +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \ + 0xFFFFFFE0 + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5 +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \ + 0x00000010 // 1 - Override the sytem-opp + // request to ANATOP using bit0 of + // this register + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \ + 0x0000000F // "0001" - RUN ; "0010" - DSLP ; + // "0100" - LPDS ; Others - NA + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register. +// +//****************************************************************************** +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \ + 0xFFFFFFFE + +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1 +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \ + 0x00000001 // 1 - Enable sleep-opp (DSLP/LPDS) + // entry even if Test-Pd is kept ON + // ; 0 - Donot enable sleep-opp + // (DSLP/LPDS) entry with Test-Pd + // ON. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3 +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \ + 0x00000004 // NA + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \ + 0x00000002 // NA + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \ + 0x00000001 // NA + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \ + 0x00000004 // 1 - Override the MCU-PD power + // modes using bits [1] & [0] ; + +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \ + 0x00000002 // 1 - Request for power-down of + // MCU-PD ; + +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \ + 0x00000001 // 1 - Request for retention mode + // of MCU-PD. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \ + 0x00000002 // 1- Override the MCSPI + // (Autonomous SPI) memory state + // using bit [0] + +#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \ + 0x00000001 // 1 - Request for power-down of + // Autonomous SPI 8k memory ; 0 - + // Donot request power-down of + // Autonomous SPI 8k Memory + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \ + 0x00000100 + +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \ + 0x00000002 + +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_REF_FSM_CFG2 register. +// +//****************************************************************************** +#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \ + 0x00380000 // Number of RTC clocks for keeping + // the FC_EN asserted high + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19 +#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \ + 0x00070000 // Number of RTC clocks for keeping + // the STARTUP_EN asserted high + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16 +#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \ + 0x0000FFFF // Number of RTC clocks for waiting + // for clock to settle. + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TESTCTRL_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1 +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \ + 0x00000001 // 0 - Disable the TestCtrl-pd ; 1 + // - Enable the TestCtrl-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \ + 0x00000006 // 1 - SSDIO-PD is ON ; 0 - + // SSDIO-PD is OFF + +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1 +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \ + 0x00000001 // 0 - Disable the SSDIO-pd ; 1 - + // Enable the SSDIO-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_N1_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \ + 0x00000006 // 1 - MCSPI_N1-PD is ON ; 0 - + // MCSPI_N1-PD if OFF + +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1 +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \ + 0x00000001 // 0 - Disable the MCSPI_N1-pd ; 1 + // - Enable the MCSPI_N1-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \ + 0x00001C00 + +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10 +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \ + 0x00000200 + +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \ + 0x00000100 + +#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1 +#define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \ + 0x00000001 // 0 - Disable the WELP-pd ; 1 - + // Enable the WELP-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1 +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \ + 0x00000001 // 0 - Disable the WL_SDIO-pd ; 1 - + // Enable the WL_SDIO-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register. +// +//****************************************************************************** +#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \ + 0x00FFFFFF // SRAM (WTOP+DRP) state during + // Active-mode : 1 - SRAMs are ON ; + // 0 - SRAMs are OFF. Cluster + // information : [0] - 1st column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) [1] - 2nd column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [2] - 3rd column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [3] - 4th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [4] - + // 5th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [5] - 6th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [6] - 7th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [7] - 8th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [8] - 9th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [9] - + // 10th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [10] - 11th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [11] - 12th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [12] - 13th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [13] - 14th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [14] - + // 15th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [15] - 16th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [23:16] - Internal to + // WTOP Cluster + +#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register. +// +//****************************************************************************** +#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \ + 0x00FFFFFF // SRAM (WTOP+DRP) state during + // Sleep-mode : 1 - SRAMs are RET ; + // 0 - SRAMs are OFF. Cluster + // information : [0] - 1st column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) [1] - 2nd column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [2] - 3rd column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [3] - 4th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [4] - + // 5th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [5] - 6th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [6] - 7th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [7] - 8th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [8] - 9th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [9] - + // 10th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [10] - 11th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [11] - 12th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [12] - 13th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [13] - 14th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [14] - + // 15th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [15] - 16th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [23:16] - Internal to + // WTOP Cluster + +#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SECURE_INIT_DONE register. +// +//****************************************************************************** +#define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \ + 0x00000002 // 1-Secure mode init is done ; + // 0-Secure mode init is not done + +#define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \ + 0x00000001 // Must be programmed 1 in order to + // say that secure-mode device init + // is done + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_DEV_MODE_INIT_DONE register. +// +//****************************************************************************** +#define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \ + 0x00000001 // 1 - Patch download and other + // initializations are done (before + // removing APPS resetn) for + // development mode (#3) . 0 - + // Development mode (#3) init is not + // done yet + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_EN_APPS_REBOOT register. +// +//****************************************************************************** +#define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \ + 0x00000001 // 1 - When 1, disable the reboot + // of APPS after DevInit is + // completed. In this case, APPS + // will permanantly help in reset. 0 + // - When 0, enable the reboot of + // APPS after DevInit is completed. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_APPS_PERIPH_PRESENT register. +// +//****************************************************************************** +#define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \ + 0x00010000 // 1 - Enable ; 0 - Disable + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \ + 0x00008000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \ + 0x00004000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \ + 0x00002000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \ + 0x00001000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \ + 0x00000800 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \ + 0x00000400 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \ + 0x00000200 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \ + 0x00000100 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \ + 0x00000080 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \ + 0x00000040 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \ + 0x00000020 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \ + 0x00000010 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \ + 0x00000008 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \ + 0x00000004 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \ + 0x00000002 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_NWP_PERIPH_PRESENT register. +// +//****************************************************************************** +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \ + 0x00000200 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \ + 0x00000100 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \ + 0x00000080 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \ + 0x00000040 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \ + 0x00000020 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \ + 0x00000010 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \ + 0x00000008 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \ + 0x00000004 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \ + 0x00000002 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SHARED_PERIPH_PRESENT register. +// +//****************************************************************************** + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \ + 0x00000040 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \ + 0x00000020 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \ + 0x00000010 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \ + 0x00000008 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \ + 0x00000004 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \ + 0x00000002 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \ + 0x00000F00 // "0000"- PORZ :- NWP is yet to be + // enabled by APPS during powerup + // (from HIB/OFF) ; "0011"- ACTIVE + // :- NWP is enabled, clocks and + // resets to NWP-SubSystem are + // enabled ; "0010"- LPDS :- NWP is + // in LPDS-mode ; Clocks and reset + // to NWP-SubSystem are gated ; + // "0101"- WAIT_FOR_OPP :- NWP is in + // transition from LPDS to ACTIVE, + // where it is waiting for OPP to be + // stable ; "1000"- + // WAKE_TIMER_OPP_REQ :- NWP is in + // transition from LPDS, where the + // wakeup cause is LPDS_Wake timer + // OTHERS : NA + +#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8 +#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \ + 0x00000007 // "000" - NWP_RUN : NWP is in RUN + // state (default) - Applicable only + // when NWP_PWR_STATE_PS = ACTIVE ; + // "001" - NWP_SLP : NWP is in SLEEP + // state (default) - Applicable only + // when NWP_PWR_STATE_PS = ACTIVE ; + // "010" - NWP_DSLP : NWP is in + // Deep-Sleep state (default) - + // Applicable only when + // NWP_PWR_STATE_PS = ACTIVE ; "011" + // - WAIT_FOR_ACTIVE : NWP is in + // transition from Deep-sleep to + // Run, where it is waiting for OPP + // to be stable ; "100" - + // WAIT_FOR_DSLP_TIMER_WAKE_REQ : + // NWP is in transition from + // Deep-sleep to Run, where the + // wakeup cause is deep-sleep + // wake-timer + +#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \ + 0x00000F00 // "0000"- PORZ :- APPS is waiting + // for PLL_clock during powerup + // (from HIB/OFF) ; "0011"- ACTIVE + // :- APPS is enabled, clocks and + // resets to APPS-SubSystem are + // enabled ; APPS might be either in + // Secure or Un-secure mode during + // this state. "1001" - + // SECURE_MODE_LPDS :- While in + // ACTIVE (Secure-mode), APPS had to + // program the DevInit_done bit at + // the end, after which it enters + // into this state, where the reset + // to APPS will be asserted. From + // this state APPS might either + // re-boot itself or enter into LPDS + // depending upon whether the device + // is 3200 or 3100. "0010"- LPDS :- + // APPS is in LPDS-mode ; Clocks and + // reset to APPS-SubSystem are gated + // ; "0101"- WAIT_FOR_OPP :- APPS is + // in transition from LPDS to + // ACTIVE, where it is waiting for + // OPP to be stable ; "1000" - + // WAKE_TIMER_OPP_REQ : APPS is in + // transition from LPDS, where the + // wakeup cause is LPDS_Wake timer ; + // "1010" - WAIT_FOR_PATCH_INIT : + // APPS enters into this state + // during development-mode #3 (SOP = + // 3), where it is waiting for patch + // download to complete and 0x4 hack + // is programmed. OTHERS : NA + +#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8 +#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \ + 0x00000007 // "000" - APPS_RUN : APPS is in + // RUN state (default) - Applicable + // only when APPS_PWR_STATE_PS = + // ACTIVE ; "001" - APPS_SLP : APPS + // is in SLEEP state (default) - + // Applicable only when + // APPS_PWR_STATE_PS = ACTIVE ; + // "010" - APPS_DSLP : APPS is in + // Deep-Sleep state (default) - + // Applicable only when + // APPS_PWR_STATE_PS = ACTIVE ; + // "011" - WAIT_FOR_ACTIVE : APPS is + // in transition from Deep-sleep to + // Run, where it is waiting for OPP + // to be stable ; "100" - + // WAIT_FOR_DSLP_TIMER_WAKE_REQ : + // APPS is in transition from + // Deep-sleep to Run, where the + // wakeup cause is deep-sleep + // wake-timer + +#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \ + 0x0000001F // TBD + +#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PM_PS register. +// +//****************************************************************************** +#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \ + 0x00000007 // "011" - WTOP_PM_ACTIVE (Default) + // :- WTOP_Pd is in ACTIVE mode; + // "100" - WTOP_PM_ACTIVE_TO_SLEEP + // :- WTOP_Pd is in transition from + // ACTIVE to SLEEP ; "000" - + // WTOP_PM_SLEEP : WTOP-Pd is in + // Sleep-state ; "100" - + // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd + // is in transition from SLEEP to + // ACTIVE ; "000" - + // WTOP_PM_WAIT_FOR_OPP : Wait for + // OPP to be stable ; + +#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WTOP PD + // Resetz. When set to 1, + // WTOP_Resetz will be controlled by + // bit [0] + +#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WTOP PD Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WELP PD + // Resetz. When set to 1, + // WELP_Resetz will be controlled by + // bit [0] + +#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WELP PD Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WL_SDIO + // Resetz. When set to 1, + // WL_SDIO_Resetz will be controlled + // by bit [0] + +#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WL_SDIO Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for SSDIO + // Resetz. When set to 1, + // SSDIO_Resetz will be controlled + // by bit [0] + +#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for SSDIO Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for MCSPI_N1 + // Resetz. When set to 1, + // MCSPI_N1_Resetz will be + // controlled by bit [0] + +#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for MCSPI_N1 Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for TESTCTRL-PD + // Resetz. When set to 1, + // TESTCTRL_Resetz will be + // controlled by bit [0] + +#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for TESTCTRL Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for MCU-PD + // Resetz. When set to 1, MCU_Resetz + // will be controlled by bit [0] + +#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for MCU Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG0 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \ + 0xFFFFFFFF // This is ROW_14 [31:0] of + // FUSEFARM. [0:0] : XTAL_IS_26MHZ + // [5:1] : TOP_CLKM_RTRIM[4:0] + // [10:6] : ANA_BGAP_MAG_TRIM[4:0] + // [16:11] : ANA_BGAP_TEMP_TRIM[5:0] + // [20:17] : ANA_BGAP_V2I_TRIM[3:0] + // [25:22] : PROCESS INDICATOR + // [26:26] : Reserved [31:27] : + // FUSEROM Version + +#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG1 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \ + 0x0000FFFF // This is ROW_15[15:0] of FUSEFARM + // 1. NWP Peripheral Present bits + // [15:8] NWP_GPT_N0_PP [15:15] + // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP + // [13:13] NWP_UDMA_PP [12:12] + // NWP_UART_N0_PP [11:11] + // NWP_UART_N1_PP [10:10] + // NWP_SSDIO_PP [9:9] + // NWP_MCSPI_N1_PP [8:8] 2. Shared + // Peripheral Present bits [7:0] + // SHARED SPI PP [6:6] + // SHARED I2C PP [5:5] SHARED + // GPIO-A PP [4:4] SHARED GPIO-B PP + // [3:3] SHARED GPIO-C PP [2:2] + // SHARED GPIO-D PP [1:1] SHARED + // GPIO-E PP [0:0] + +#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG2 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \ + 0xFFFFFFFF // This is ROW_16[15:0] & + // ROW_15[31:16] of FUSEFARM. + // [31:21] - Reserved [20:16] - + // CHIP_ID [15:15] - SSBD SOP + // Control [14:14] - SSBD TAP + // Control [13:2] - APPS Peripheral + // Present bits : APPS_CAMERA_PP + // [13:13] APPS_MMCHS_PP [12:12] + // APPS_MCASP_PP [11:11] + // APPS_MCSPI_A1_PP [10:10] + // APPS_MCSPI_A2_PP [9:9] + // APPS_UDMA_PP [8:8] APPS_WDOG_PP + // [7:7] APPS_UART_A0_PP [6:6] + // APPS_UART_A1_PP [5:5] + // APPS_GPT_A0_PP [4:4] + // APPS_GPT_A1_PP [3:3] + // APPS_GPT_A2_PP [2:2] + // APPS_GPT_A3_PP [1:1] [0:0] - NWP + // Peripheral present bits + // NWP_ACSPI_PP [0:0] + +#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG3 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \ + 0xFFFFFFFF // This is ROW_17[15:0] & + // ROW_16[31:16] of FUSEFARM : + // [31:16] - TEST_TAP_KEY(15:0) + // [15:0] - Reserved + +#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_MEM_RET_CFG register. +// +//****************************************************************************** +#define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \ + 0x00000001 // 1 - Soft-compile memories in + // WTOP can be turned-off during + // WTOP-sleep mode ; 0 - + // Soft-compile memories in WTOP + // must be kept on during WTOP-sleep + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG0 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \ + 0x007FFFFF // TBD + +#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG1 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \ + 0x000FFFFF // TBD + +#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG2 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \ + 0x00000018 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3 +#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \ + 0x00000004 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \ + 0x00000002 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \ + 0x00000001 // TBD + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_ENABLE register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \ + 0x00000001 // 1 - Enable switching of sysclk + // to Coex-clk path ; 0 - Disable + // switching of sysclk to Coex-clk + // path. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_DCDC_CLK_GEN_CONFIG register. +// +//****************************************************************************** +#define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \ + 0x00000001 // 1 - Enable the clock for DCDC + // (PWM-mode) ; 0 - Disable the + // clock for DCDC (PWM-mode) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG4 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \ + 0x0000FFFF // This corresponds to + // ROW_17[31:16] of the FUSEFARM : + // [15:0] : TEST_TAP_KEY(31:16) + +#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG5 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \ + 0xFFFFFFFF // Corresponds to ROW_18 of + // FUSEFARM. [29:0] - + // MEMSS_COLUMN_SEL_LSW ; [30:30] - + // WLAN GEM DISABLE ; [31:31] - + // SERIAL WIRE JTAG SELECT + +#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG6 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \ + 0x0000FFFF // Corresponds to ROW_19[15:0] of + // FUSEFARM. [15:0] : + // MEMSS_COLUMN_SEL_MSW + +#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG7 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_20[15:0] & + // ROW_19[31:16] of FUSEFARM. + // FLASH_REGION0 + +#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG8 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_21[15:0] & + // ROW_20[31:16] of FUSEFARM. + // FLASH_REGION1 + +#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG9 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_22[15:0] & + // ROW_21[31:16] of FUSEFARM. + // FLASH_REGION2 + +#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG10 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_23[15:0] & + // ROW_22[31:16] of FUSEFARM. + // FLASH_REGION3 + +#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG11 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_24[15:0] & + // ROW_23[31:16] of FUSEFARM. + // FLASH_DESCRIPTOR + +#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG0 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \ + 0xFFFFFFFF // Corresponds to bits [191:160] of + // the FUSEFARM. This is ROW_5 of + // FUSEFARM [191:160] : [31:0] : + // DIE_ID0 [31:0] : DEVX [11:0] DEVY + // [23:12] DEVWAF [29:24] DEV_SPARE + // [31:30] + +#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG1 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \ + 0xFFFFFFFF // Corresponds to bits [223:192] of + // the FUSEFARM. This is ROW_6 of + // FUSEFARM :- DEVLOT [23:0] DEVFAB + // [28:24] DEVFABBE [31:29] + +#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG2 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \ + 0xFFFFFFFF // Corresponds to bits [255:224] of + // the FUSEFARM. This is ROW_7 of + // FUSEFARM:- DEVDESREV[4:0] + // Memrepair[5:5] MakeDefined[16:6] + // CHECKSUM[30:17] Reserved : + // [31:31] + +#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG3 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \ + 0xFFFFFFFF // Corresponds to bits [287:256] of + // the FUSEFARM. This is ROW_8 of + // FUSEFARM :- DIEID0 - DEVREG + // [31:0] + +#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG4 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \ + 0xFFFFFFFF // Corresponds to bits [319:288] of + // the FUSEFARM. This is ROW_9 of + // FUSEFARM :- [7:0] - VBATMON ; + // [13:8] - BUFF_OFFSET ; [15:15] - + // DFT_GXG ; [14:14] - DFT_GLX ; + // [19:16] - PHY ROM Version ; + // [23:20] - MAC ROM Version ; + // [27:24] - NWP ROM Version ; + // [31:28] - APPS ROM Version + +#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APPS_SS_OVERRIDES_reserved_M \ + 0xFFFFFC00 + +#define GPRCM_APPS_SS_OVERRIDES_reserved_S 10 +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \ + 0x00000200 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \ + 0x00000100 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \ + 0x00000080 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \ + 0x00000040 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \ + 0x00000020 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \ + 0x00000010 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \ + 0x00000008 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \ + 0x00000002 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_NWP_SS_OVERRIDES_reserved_M \ + 0xFFFFFC00 + +#define GPRCM_NWP_SS_OVERRIDES_reserved_S 10 +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \ + 0x00000200 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \ + 0x00000100 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \ + 0x00000080 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \ + 0x00000040 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \ + 0x00000020 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \ + 0x00000010 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \ + 0x00000008 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \ + 0x00000002 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SHARED_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_SHARED_SS_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8 +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \ + 0x00000080 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \ + 0x00000040 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \ + 0x00000020 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \ + 0x00000010 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \ + 0x00000008 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \ + 0x00000004 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \ + 0x00000002 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_IDMEM_CORE_RST_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8 +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \ + 0x00000080 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \ + 0x00000040 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \ + 0x00000020 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \ + 0x00000010 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \ + 0x00000008 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \ + 0x00000002 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_FSM_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \ + 0xFFFFF000 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12 +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \ + 0x00000800 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \ + 0x00000400 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \ + 0x00000200 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \ + 0x00000100 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \ + 0x00000080 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \ + 0x00000040 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \ + 0x00000020 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \ + 0x00000010 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \ + 0x00000008 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \ + 0x00000002 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \ + 0xFFF00000 + +#define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \ + 0x00080000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \ + 0x00040000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \ + 0x00020000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \ + 0x00010000 + +#define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \ + 0x0000FC00 + +#define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \ + 0x00000200 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \ + 0x00000100 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \ + 0x000000F0 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \ + 0x0000000F + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \ + 0xFFC00000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22 +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \ + 0x00200000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \ + 0x00100000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \ + 0x00080000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \ + 0x00040000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \ + 0x00020000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \ + 0x00010000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \ + 0x0000FF00 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8 +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \ + 0x000000FF + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8 +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \ + 0x00000080 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \ + 0x00000040 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \ + 0x00000020 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \ + 0x00000010 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \ + 0x00000008 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \ + 0x00000004 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \ + 0x00000001 + + + + +#endif // __HW_GPRCM_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_hib1p2.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_hib1p2.h new file mode 100644 index 000000000..205f26c90 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_hib1p2.h @@ -0,0 +1,1752 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_HIB1P2_H__ +#define __HW_HIB1P2_H__ + +//***************************************************************************** +// +// The following are defines for the HIB1P2 register offsets. +// +//***************************************************************************** +#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \ + 0x00000000 + +#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \ + 0x00000004 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS0 \ + 0x00000008 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS1 \ + 0x0000000C + +#define HIB1P2_O_DIG_DCDC_PARAMETERS2 \ + 0x00000010 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS3 \ + 0x00000014 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS4 \ + 0x00000018 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS5 \ + 0x0000001C + +#define HIB1P2_O_DIG_DCDC_PARAMETERS6 \ + 0x00000020 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS0 \ + 0x00000024 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS1 \ + 0x00000028 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS16 \ + 0x00000064 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS17 \ + 0x00000068 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS18 \ + 0x0000006C + +#define HIB1P2_O_ANA_DCDC_PARAMETERS19 \ + 0x00000070 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \ + 0x00000074 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \ + 0x00000078 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \ + 0x0000007C + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \ + 0x00000080 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \ + 0x00000084 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \ + 0x00000088 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \ + 0x0000008C + +#define HIB1P2_O_PMBIST_PARAMETERS0 \ + 0x00000094 + +#define HIB1P2_O_PMBIST_PARAMETERS1 \ + 0x00000098 + +#define HIB1P2_O_PMBIST_PARAMETERS2 \ + 0x0000009C + +#define HIB1P2_O_PMBIST_PARAMETERS3 \ + 0x000000A0 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \ + 0x000000A4 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \ + 0x000000A8 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \ + 0x000000AC + +#define HIB1P2_O_DIG_DCDC_VTRIM_CFG \ + 0x000000B0 + +#define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \ + 0x000000B4 + +#define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \ + 0x000000B8 + +#define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \ + 0x000000BC + +#define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \ + 0x000000C0 + +#define HIB1P2_O_CM_OSC_16M_CONFIG \ + 0x000000C4 + +#define HIB1P2_O_SOP_SENSE_VALUE \ + 0x000000C8 + +#define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \ + 0x000000CC + +#define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \ + 0x000000D0 + +#define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \ + 0x000000D4 + +#define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \ + 0x000000D8 + +#define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \ + 0x000000DC + +#define HIB1P2_O_HIB1P2_POR_TEST_CTRL \ + 0x000000E0 + +#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \ + 0x000000E4 + +#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \ + 0x000000E8 + +#define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \ + 0x000000EC + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \ + 0x000000F0 + +#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \ + 0x000000F4 + +#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \ + 0x000000F8 + +#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \ + 0x000000FC + +#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \ + 0x00000100 + +#define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \ + 0x00000104 + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \ + 0x00000108 + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \ + 0x0000010C + +#define HIB1P2_O_CM_SPARE 0x00000110 +#define HIB1P2_O_PORPOL_SPARE 0x00000114 +#define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \ + 0x00000118 + +#define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \ + 0x0000011C + +#define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \ + 0x00000120 + +#define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \ + 0x00000124 + +#define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \ + 0x00000128 + +#define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \ + 0x0000012C + +#define HIB1P2_O_MEM_HIB_FSM_DEBUG \ + 0x00000130 + +#define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \ + 0x00000134 + +#define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \ + 0x00000138 + +#define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \ + 0x0000013C + +#define HIB1P2_O_MEM_CM_TEST_MODE \ + 0x00000140 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \ + 0xC0000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \ + 0x30000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \ + 0x08000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \ + 0x04000000 // FSM Override value for SLDO_EN : + // Applicable only when bit [4] of + // this register is set to 1. + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \ + 0x02000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \ + 0x01000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \ + 0x00FC0000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \ + 0x0003FF00 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \ + 0x00000080 // FSM Override value for + // SKA_LDO_EN : Applicable only when + // bit [3] of this register is set + // to 1. + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \ + 0x00000040 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \ + 0x00000020 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \ + 0x00000010 // When 1, bit[26] of this register + // will be used as SLDO_EN + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \ + 0x00000008 // When 1, bit[26] of this register + // will be used as SKA_LDO_EN + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \ + 0x00000007 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \ + 0xFFC00000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \ + 0x003F0000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \ + 0x00008000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \ + 0x00004000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \ + 0x00002000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \ + 0x00001000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \ + 0x00000800 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \ + 0x000007FF + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \ + 0x80000000 // Override value for DCDC_DIG_EN : + // Applicable only when bit [31] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \ + 0x20000000 // Override value for + // DCDC_DIG_EN_SUBREG_1P8V : + // Applicable only when bit [30] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \ + 0x10000000 // Override value for + // DCDC_DIG_EN_SUBREG_1P2V : + // Applicable only when bit [29] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \ + 0x08000000 // Override value for + // DCDC_DIG_SLP_EN : Applicable only + // when bit [28] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \ + 0x04000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \ + 0x02000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \ + 0x01000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \ + 0x00800000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \ + 0x00400000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \ + 0x003F0000 // Override value for + // DCDC_DIG_VTRIM : Applicable only + // when bit [27] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \ + 0x0000C000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \ + 0x00003000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \ + 0x00000800 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \ + 0x00000780 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \ + 0x00000078 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3 +#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \ + 0x00000007 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \ + 0x20000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \ + 0x10000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \ + 0x08000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \ + 0x04000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \ + 0x02000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \ + 0x01FFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \ + 0x0F000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \ + 0x00C00000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \ + 0x00300000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16 +#define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \ + 0x00008000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \ + 0x00007800 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \ + 0x00000400 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \ + 0x000003FC + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \ + 0x00000002 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \ + 0x00000001 // Override value for + // DCDC_DIG_COT_EN : Applicable only + // when bit[26] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \ + 0x7F800000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \ + 0x00400000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \ + 0x00200000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \ + 0x001FE000 // Override value for + // DCDC_DIG_ILIM_TRIM : Applicable + // only when bit [25] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \ + 0x00001800 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \ + 0x00000400 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \ + 0x00000200 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \ + 0x000001F0 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \ + 0x0000000C + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \ + 0x00000002 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS4 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \ + 0x20000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \ + 0x1FFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS5 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS6 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \ + 0x80000000 // Override for ANA DCDC EN + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \ + 0x20000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \ + 0x10000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \ + 0x08000000 // Override for ANA DCDC PWM + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \ + 0x04000000 // Override for ANA DCDC SLP + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \ + 0x02000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \ + 0x01000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \ + 0x00800000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \ + 0x00400000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \ + 0x00200000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \ + 0x001E0000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \ + 0x00018000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \ + 0x00006000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \ + 0x00001000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \ + 0x00000F00 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \ + 0x000000F0 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \ + 0x0000000F + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \ + 0x0C000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \ + 0x03000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \ + 0x00F00000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \ + 0x00008000 // (Earlier SHOOTTHRU CTRL) + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \ + 0x00004000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \ + 0x00003E00 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \ + 0x00000100 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \ + 0x00000080 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \ + 0x00000060 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \ + 0x00000010 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \ + 0x0000000C + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2 +#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \ + 0x00000003 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS16 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \ + 0x00200000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \ + 0x00100000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \ + 0x000FF000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \ + 0x00000C00 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \ + 0x00000200 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \ + 0x00000100 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \ + 0x000000F8 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \ + 0x00000006 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS17 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \ + 0x40000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \ + 0x3FFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS18 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS19 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \ + 0x20000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \ + 0x18000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \ + 0x04000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \ + 0x02000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \ + 0x01000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \ + 0x00800000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \ + 0x00400000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \ + 0x003C0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \ + 0x00020000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \ + 0x00010000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \ + 0x00008000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \ + 0x00004000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \ + 0x00002000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \ + 0x00001000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \ + 0x00000800 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \ + 0x00000400 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \ + 0x00000200 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \ + 0x000001E0 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \ + 0x0000001E + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \ + 0x0F000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \ + 0x00F00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \ + 0x0000F000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \ + 0x00000F00 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \ + 0x000000C0 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \ + 0x00000030 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \ + 0x0000000C + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \ + 0x00000003 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \ + 0xC0000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \ + 0x30000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \ + 0x0C000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \ + 0x03000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \ + 0x00800000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \ + 0x00400000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \ + 0x00200000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \ + 0x001F0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \ + 0x0000F000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \ + 0x00000800 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \ + 0x00000400 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \ + 0x000003FC + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \ + 0x00000003 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \ + 0x20000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \ + 0x1F000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \ + 0x00E00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \ + 0x001C0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \ + 0x0003C000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \ + 0x00003C00 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \ + 0x00000300 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \ + 0x00000080 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \ + 0x00000040 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \ + 0x00000020 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \ + 0x0000001F + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS4 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS5 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS6 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \ + 0x3FFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \ + 0x80000000 + +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \ + 0x7FFFF800 + +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11 +#define HIB1P2_PMBIST_PARAMETERS0_NA21_M \ + 0x000007FF + +#define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \ + 0xFFFF0000 + +#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16 +#define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \ + 0x00008000 + +#define HIB1P2_PMBIST_PARAMETERS1_NA22_M \ + 0x00007FFF + +#define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \ + 0xFFFF0000 + +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16 +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \ + 0x0000E000 + +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13 +#define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \ + 0x00001000 + +#define HIB1P2_PMBIST_PARAMETERS3_NA23_M \ + 0x00000FFF + +#define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS8 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \ + 0x7C000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26 +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \ + 0x03E00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21 +#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \ + 0x001FFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \ + 0xFFFFFFC0 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6 +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \ + 0x00000020 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \ + 0x00000010 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \ + 0x00000008 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \ + 0x00000004 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \ + 0x00000002 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \ + 0xFFFFFFFC + +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \ + 0x00000002 + +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_VTRIM_CFG register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \ + 0xFF000000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \ + 0x00FC0000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \ + 0x0003F000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \ + 0x00000FC0 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \ + 0x0000003F + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \ + 0xFFFF8000 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \ + 0x00007000 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \ + 0x00000E00 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \ + 0x000001C0 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \ + 0x00000038 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \ + 0x00000007 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \ + 0xFFFFFFF8 + +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3 +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \ + 0x00000007 + +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \ + 0xFFFFFFC0 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6 +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \ + 0x00000038 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3 +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \ + 0x00000007 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register. +// +//****************************************************************************** +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \ + 0xFFFFFFF8 + +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3 +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \ + 0x00000007 + +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_CM_OSC_16M_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \ + 0xFFFC0000 + +#define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18 +#define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \ + 0x00020000 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \ + 0x00010000 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \ + 0x0000FC00 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10 +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \ + 0x000003F0 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4 +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \ + 0x00000008 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \ + 0x00000007 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SOP_SENSE_VALUE register. +// +//****************************************************************************** +#define HIB1P2_SOP_SENSE_VALUE_reserved_M \ + 0xFFFFFF00 + +#define HIB1P2_SOP_SENSE_VALUE_reserved_S 8 +#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \ + 0x000000FF + +#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \ + 0xFF800000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \ + 0x00400000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \ + 0x003FC000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \ + 0x00002000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \ + 0x00001FC0 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \ + 0x00000020 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \ + 0x0000001F + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \ + 0xFFFFFFFF // Corresponds to ROW_12 of + // FUSEFARM. [7:0] : + // DCDC_DIG_ILIM_TRIM_LOWV(7:0) + // [15:8] : + // DCDC_ANA_ILIM_TRIM_LOWV(7:0) + // [23:16] : + // DCDC_FLASH_ILIM_TRIM_LOWV(7:0) + // [24:24] : DTHE SHA DISABLE + // [25:25] : DTHE DES DISABLE + // [26:26] : DTHE AES DISABLE + // [31:27] : HD_BG_RTRIM (4:0) + +#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \ + 0xFFFFFFFF // Corresponds to ROW_13 of the + // FUSEFARM. [7:0] : HD_BG_MAG_TRIM + // (7:0) [14:8] : HD_BG_TEMP_TRIM + // (6:0) [15:15] : GREYOUT ENABLE + // DUTY CYCLING [31:16] : + // Reserved/Checksum + +#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_POR_TEST_CTRL register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \ + 0xFFFFFF00 + +#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8 +#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \ + 0x000000FF + +#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \ + 0x0000FF00 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \ + 0x000000FE + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \ + 0xFFF00000 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \ + 0x000FFFFF + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CFG2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \ + 0xFFFFFE00 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9 +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \ + 0x00000100 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \ + 0x000000FC + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2 +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \ + 0x00000002 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16 +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16 +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \ + 0xFFFFF000 + +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12 +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \ + 0x00000FFF + +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register. +// +//****************************************************************************** +#define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \ + 0xFF000000 + +#define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24 +#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \ + 0x00FF0000 + +#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16 +#define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \ + 0x0000FFFF + +#define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PORPOL_SPARE register. +// +//****************************************************************************** +#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \ + 0xFFFFFFFF + +#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \ + 0x00000002 + +#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \ + 0x00000002 + +#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_HIB_FSM_DEBUG register. +// +//****************************************************************************** +#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \ + 0x00000700 + +#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8 +#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \ + 0x000000F0 + +#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4 +#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \ + 0x0000000F + +#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \ + 0x000FFFFF + +#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_WEAK_PROCESS register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register. +// +//****************************************************************************** +#define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \ + 0x00000002 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_CM_TEST_MODE register. +// +//****************************************************************************** +#define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \ + 0x00000001 + + + + +#endif // __HW_HIB1P2_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_hib3p3.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_hib3p3.h new file mode 100644 index 000000000..8d5a40aa1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_hib3p3.h @@ -0,0 +1,1140 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_HIB3P3_H__ +#define __HW_HIB3P3_H__ + +//***************************************************************************** +// +// The following are defines for the HIB3P3 register offsets. +// +//***************************************************************************** +#define HIB3P3_O_MEM_HIB_REQ 0x00000000 +#define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \ + 0x00000004 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \ + 0x00000008 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \ + 0x0000000C + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \ + 0x00000010 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \ + 0x00000014 + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \ + 0x00000018 + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \ + 0x0000001C + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \ + 0x00000020 + +#define HIB3P3_O_MEM_INT_OSC_CONF \ + 0x0000002C + +#define HIB3P3_O_MEM_XTAL_OSC_CONF \ + 0x00000034 + +#define HIB3P3_O_MEM_BGAP_PARAMETERS0 \ + 0x00000038 + +#define HIB3P3_O_MEM_BGAP_PARAMETERS1 \ + 0x0000003C + +#define HIB3P3_O_MEM_HIB_DETECTION_STATUS \ + 0x00000040 + +#define HIB3P3_O_MEM_HIB_MISC_CONTROLS \ + 0x00000044 + +#define HIB3P3_O_MEM_HIB_CONFIG 0x00000050 +#define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \ + 0x00000054 + +#define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \ + 0x00000058 + +#define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \ + 0x0000005C + +#define HIB3P3_O_MEM_HIB_UART_CONF \ + 0x00000400 + +#define HIB3P3_O_MEM_GPIO_WAKE_EN \ + 0x00000404 + +#define HIB3P3_O_MEM_GPIO_WAKE_CONF \ + 0x00000408 + +#define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \ + 0x0000040C + +#define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \ + 0x00000410 + +#define HIB3P3_O_MEM_JTAG_CONF 0x00000414 +#define HIB3P3_O_MEM_HIB_REG0 0x00000418 +#define HIB3P3_O_MEM_HIB_REG1 0x0000041C +#define HIB3P3_O_MEM_HIB_REG2 0x00000420 +#define HIB3P3_O_MEM_HIB_REG3 0x00000424 +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \ + 0x0000045C + +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \ + 0x00000460 + +#define HIB3P3_O_MEM_HIB_MISC_CONFIG \ + 0x00000464 + +#define HIB3P3_O_MEM_HIB_WAKE_STATUS \ + 0x00000468 + +#define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \ + 0x0000046C + +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \ + 0x00000470 + +#define HIB3P3_O_HIBANA_SPARE_LOWV \ + 0x00000474 + +#define HIB3P3_O_HIB_TMUX_CTRL 0x00000478 +#define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \ + 0x0000047C + +#define HIB3P3_O_HIB_COMP_TRIM 0x00000480 +#define HIB3P3_O_HIB_EN_TS 0x00000484 +#define HIB3P3_O_HIB_1P8V_DET_EN \ + 0x00000488 + +#define HIB3P3_O_HIB_VBAT_MON_EN \ + 0x0000048C + +#define HIB3P3_O_HIB_NHIB_ENABLE \ + 0x00000490 + +#define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \ + 0x00000494 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REQ register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REQ_reserved_M \ + 0xFFFFFE00 + +#define HIB3P3_MEM_HIB_REQ_reserved_S 9 +#define HIB3P3_MEM_HIB_REQ_NU1_M \ + 0x000001FC + +#define HIB3P3_MEM_HIB_REQ_NU1_S 2 +#define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \ + 0x00000002 // 1 - Specifies that the Hiberante + // mode is without clocks ; 0 - + // Specified that the Hibernate mode + // is with clocks This register will + // be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +#define HIB3P3_MEM_HIB_REQ_mem_hib_req \ + 0x00000001 // 1 - Request for hibernate mode + // (This is an auto-clear bit) ; 0 - + // Donot request for hibernate mode + // This register will be reset + // during Hibernate -WO-Clks mode + // (but not during Hibernate-W-Clks + // mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \ + 0x00000001 // 1 - Enable the RTC timer to + // start running ; 0 - Keep the RTC + // timer disabled This register will + // be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \ + 0x00000001 // 1 - Reset the RTC timer ; 0 - + // Donot reset the RTC timer. This + // is an auto-clear bit. This + // register will be reset during + // Hibernate -WO-Clks mode (but not + // during Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_READ register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \ + 0x00000001 // 1 - Latch the running RTC timer + // into local registers. After + // programming this bit to 1, the + // F/w can read the latched RTC + // timer values from + // MEM_HIB_RTC_TIMER_LSW and + // MEM_HIB_RTC_TIMER_MSW. Before the + // F/w (APPS or NWP) wants to read + // the RTC-Timer, it has to program + // this bit to 1, then only read the + // MSW and LSW values. This is an + // auto-clear bit. This register + // will be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \ + 0xFFFFFFFF // Lower 32b value of the latched + // RTC-Timer. + +#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16 +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \ + 0x0000FFFF // Upper 32b value of the latched + // RTC-Timer. + +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_EN register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \ + 0x00000001 // 1 - Enable the RTC timer based + // wakeup during Hibernate mode ; 0 + // - Disable the RTC timer based + // wakeup during Hibernate mode This + // register will be reset during + // Hibernate-WO-Clks mode (but not + // during Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \ + 0xFFFFFFFF // Configuration for RTC-Timer + // Wakeup (Lower 32b word) + +#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16 +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \ + 0x0000FFFF // Configuration for RTC-Timer + // Wakeup (Upper 16b word) + +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_INT_OSC_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_INT_OSC_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16 +#define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \ + 0x00008000 // 1 - Internal 32kHz Oscillator is + // valid ; 0 - Internal 32k + // oscillator clk is not valid + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \ + 0x00007E00 + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9 +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \ + 0x00000100 // When 1, the INT_32K_OSC_EN comes + // from bit [0] of this register, + // else comes from the FSM. This + // register will be reset during + // Hibernate-WO-Clks mode (but not + // during Hibernate-W-Clks mode) + +#define HIB3P3_MEM_INT_OSC_CONF_NU1 \ + 0x00000080 + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \ + 0x0000007E + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1 +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \ + 0x00000001 // Override value for INT_OSC_EN. + // Applicable only when bit [3] of + // this register is set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_XTAL_OSC_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \ + 0xFFF00000 + +#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \ + 0x00080000 // When 1, the SLICER_EN comes from + // bit [10] of this register, else + // comes from the FSM. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \ + 0x00040000 // When 1, the XTAL_EN comes from + // bit [0] of this register, else + // comes from the FSM. + +#define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \ + 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL + // Clk is yet to be valid. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \ + 0x0001F800 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \ + 0x00000400 // SLICER_EN Override value : + // Applicable only when bit [19] of + // this register is set to 1. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \ + 0x00000380 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \ + 0x00000070 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \ + 0x00000008 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \ + 0x00000006 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \ + 0x00000001 // XTAL_EN Override value : + // Applicable only when bit [18] of + // this register is set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_BGAP_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \ + 0xFFF80000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19 +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \ + 0x00040000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \ + 0x0001C000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14 +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \ + 0x00001000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \ + 0x00000800 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \ + 0x00000400 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \ + 0x000003FF + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_BGAP_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \ + 0xE0000000 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29 +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \ + 0x1F000000 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24 +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \ + 0x00000008 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \ + 0x00000004 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \ + 0x00000002 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_DETECTION_STATUS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \ + 0xFFFFFF80 + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7 +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \ + 0x00000040 // 1 - 1.8 V supply forced mode. + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \ + 0x00000004 // 1 - 3.3 V supply forced mode for + // Flash supply + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \ + 0x00000002 // 1 - Forced clock mode + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \ + 0x00000001 // 1 - XTAL clock mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_MISC_CONTROLS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \ + 0xFFFFF800 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11 +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \ + 0x00000400 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \ + 0x00000200 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \ + 0x000001C0 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6 +#define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \ + 0x00000020 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \ + 0x00000010 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_CONFIG register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \ + 0xFF000000 + +#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24 +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \ + 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD + // for digital path (SHARED4) ; 0 - + // Disable VDD_FLASH_INDP_PAD for + // digital path (SHARED4) ; Before + // programming this bit to 1, ensure + // that the device is in FORCED 3.3 + // supply Mode, which can be + // inferred from the register : + // MEM_HIB_DETECTION_STATUS : 0x0040 + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \ + 0x00040000 // 1 - Enable the + // VDD_FB_GPIO_MUX_PAD for digital + // path (SHARED3) ; 0 - Disable the + // VDD_FB_GPIO_MUX_PAD for digital + // path (SHARED3) ; This pin can be + // used only in modes other than + // SOP("111") + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \ + 0x00020000 // 1 - Enable the PM_TEST_PAD for + // digital GPIO path (SHARED2) ; 0 - + // Disable the PM_TEST_PAD for + // digital GPIO path (SHARED2) This + // pin can be used for digital only + // in modes other then SOP-111 + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \ + 0x00010000 // 1 - Enable the XTAL_N pin + // digital GPIO path (SHARED1); 0 - + // Disable the XTAL_N pin digital + // GPIO path (SHARED1). Before + // programming this bit to 1, ensure + // that the device is in FORCED CLK + // Mode, which can inferred from the + // register : + // MEM_HIB_DETECTION_STATUS : + // 0x0040. + +#define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \ + 0x00000100 // 1 - Enable the XTAL Clock ; 0 - + // Donot enable the XTAL Clock. This + // bit has to be programmed to 1 (by + // APPS Devinit F/w), during exit + // from OFF or Hib_wo_clks modes, + // after checking if the slow_clk + // mode is XTAL_CLK mode. Once + // enabled the XTAL will be disabled + // only after entering HIB_WO_CLKS + // mode. This register will be reset + // during Hibernate -WO-Clks mode + // (but not during Hibernate-W-Clks + // mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \ + 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0 + // - Disable the HIB RTC - IRQ + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \ + 0xFFFFFFFF // Configuration for LSW of the + // RTC-Timestamp at which interrupt + // need to be generated + +#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \ + 0x0000FFFF // Configuration for MSW of thr + // RTC-Timestamp at which the + // interrupt need to be generated + +#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_UART_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_UART_CONF_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1 +#define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \ + 0x00000001 // 1 - Enable the UART-Autonomous + // mode wakeup during Hibernate mode + // ; This is an auto-clear bit, once + // programmed to 1, it will latched + // into an internal register which + // remain asserted until the + // Hib-wakeup is initiated. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_GPIO_WAKE_EN register. +// +//****************************************************************************** +#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \ + 0xFFFFFF00 + +#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8 +#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \ + 0x000000FF // 1 - Enable the GPIO-Autonomous + // mode wakeup during Hibernate mode + // ; This is an auto-clear bit, once + // programmed to 1, it will latched + // into an internal register which + // remain asserted until the + // Hib-wakeup is initiated. + +#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16 +#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \ + 0x0000FFFF // Configuration to say whether the + // GPIO wakeup has to happen on + // Level0 or falling-edge for the + // given group. “00â€? – Level0 “01â€? – + // Level1 “10â€?- Fall-edge “11â€?- + // Rise-edge [1:0] – Conf for GPIO0 + // [3:2] – Conf for GPIO1 [5:4] – + // Conf for GPIO2 [7:6] – Conf for + // GPIO3 [9:8] – Conf for GPIO4 + // [11:10] – Conf for GPIO5 [13:12] + // – Conf for GPIO6 + +#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_PAD_OEN_RET33_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \ + 0x00000004 // 1 - Override the OEN33 and RET33 + // controls of GPIOs during + // SOP-Bootdebug mode ; 0 - Donot + // override the OEN33 and RET33 + // controls of GPIOs during + // SOP-Bootdebug mode + +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \ + 0x00000004 // 1 - Override the OEN33 and RET33 + // controls of UART NRTS GPIO during + // SOP-Bootdebug mode ; 0 - Donot + // override the OEN33 and RET33 + // controls of UART NRTS GPIO during + // SOP-Bootdebug mode + +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_JTAG_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \ + 0x00000200 + +#define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \ + 0x00000100 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \ + 0x00000008 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \ + 0x00000004 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG2 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG3 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \ + 0xFFFF0000 // Configuration for the number of + // slow-clks between de-assertion of + // EN_BG_3P3V to assertion of + // EN_BG_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \ + 0x00008000 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \ + 0x00006000 // Configuration for the number of + // slow-clks between assertion of + // EN_COMP_3P3V and assertion of + // EN_COMP_LATCH_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \ + 0x00001800 // Configuration for the number of + // slow-clks between assertion of + // (EN_CAP_SW_3P3V,EN_COMP_REF) and + // assertion of (EN_COMP_3P3V) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \ + 0x00000600 // Configuration for the number of + // slow-clks between assertion of + // (EN_BG_3P3V) and assertion of + // (EN_CAP_SW_3P3V, + // EN_COMP_REF_3P3V) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \ + 0x00000100 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \ + 0x00000080 // 1 - EN_VBOK4BG_REF comes from + // bit[10] of the register + // MEM_BGAP_PARAMETERS0 [0x0038]. 0 + // - EN_VBOK4BG_REF comes directly + // from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \ + 0x00000040 // 1 - EN_VBOK4BG comes from + // bit[11] of the register + // MEM_BGAP_PARAMETERS0 [0x0038]. 0 + // - EN_VBOK4BG comes directly from + // the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \ + 0x00000020 // 1 - EN_V2I comes from bit[2] of + // the register MEM_BGAP_PARAMETERS1 + // [0x003C]. 0 - EN_V2I comes + // directly from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \ + 0x00000010 // 1 - EN_POR_COMP_REF comes from + // bit[9] of the register + // MEM_HIB_MISC_CONTROLS [0x0044]. 0 + // - EN_POR_COMP_REF comes directly + // from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \ + 0x00000008 // 1 - EN_POR_COMP comes from + // bit[10] of the register + // MEM_HIB_MISC_CONTROLS [0x044]. 0 + // - EN_POR_COMP comes directly from + // the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \ + 0x00000004 // 1 - EN_CAP_SW comes from bit[1] + // of the register + // MEM_BGAP_PARAMETERS1 [0x003C]. 0 + // - EN_CAP_SW comes directly from + // Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \ + 0x00000002 // 1 - EN_BGAP comes from bit[0] of + // the register MEM_BGAP_PARAMETERS1 + // [0x003C]. 0 - EN_BGAP comes + // directly from Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \ + 0x0000C000 // Configuration for number of + // slow-clks between de-assertion of + // EN_COMP_LATCH and assertion of + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \ + 0x00003000 // Configuration for number of + // slow-clks between assertion of + // EN_COMP_REF to assertion of + // EN_COMP during HIB-Exit + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \ + 0x00000C00 // TBD + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \ + 0x00000300 // Configuration in number of + // slow-clks between assertion of + // (EN_BGAP_3P3V, EN_CAP_SW_3P3V, + // EN_ACT_IREF_3P3V, EN_COMP_REF) to + // assertion of EN_COMP_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \ + 0x000000C0 // Configuration in number of + // slow-clks between de-assertion of + // (EN_COMP_3P3V, EN_COMP_REF_3P3V, + // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V) + // to deassertion of EN_BGAP_3P3V. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \ + 0x0000003F + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_MISC_CONFIG register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_WAKE_STATUS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \ + 0x0000001E // "0100" - GPIO ; "0010" - RTC ; + // "0001" - UART Others - Reserved + +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1 +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \ + 0x00000001 // 1 - Wake from Hibernate ; 0 - + // Wake from OFF + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \ + 0x00000007 + +#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \ + 0xFFFFF800 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \ + 0x00000600 // Deassertion of EN_COMP_LATCH_3P3 + // to deassertion of (EN_COMP_3P3, + // EN_COMP_REF_3P3, EN_ACT_IREF_3P3, + // EN_CAP_SW_3P3) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \ + 0x000001C0 // Assertion of EN_COMP_LATCH_3P3 + // to deassertion of + // EN_COMP_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \ + 0x00000030 // Deassertion of (EN_CAP_SW_3P3, + // EN_COMP_REF_3P3, EN_COMP_3P3, + // EN_COMP_OUT_LATCH_3P3) to + // deassertion of EN_BGAP_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \ + 0x0000000C // Assertion of EN_COMP_3P3 to + // assertion of EN_COMPOUT_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \ + 0x00000003 // Assertion of EN_COMP_3P3 to + // assertion of EN_COMPOUT_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIBANA_SPARE_LOWV register. +// +//****************************************************************************** +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \ + 0xFFC00000 + +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22 +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \ + 0x0001FFFF + +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_TMUX_CTRL register. +// +//****************************************************************************** +#define HIB3P3_HIB_TMUX_CTRL_reserved_M \ + 0xFFFFFC00 + +#define HIB3P3_HIB_TMUX_CTRL_reserved_S 10 +#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \ + 0x000003FF + +#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register. +// +//****************************************************************************** +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \ + 0xFFFFF000 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12 +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \ + 0x00000800 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \ + 0x00000400 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \ + 0x00000200 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \ + 0x00000100 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \ + 0x000000F0 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4 +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \ + 0x0000000F + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_COMP_TRIM register. +// +//****************************************************************************** +#define HIB3P3_HIB_COMP_TRIM_reserved_M \ + 0xFFFFFFF8 + +#define HIB3P3_HIB_COMP_TRIM_reserved_S 3 +#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \ + 0x00000007 + +#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_EN_TS register. +// +//****************************************************************************** +#define HIB3P3_HIB_EN_TS_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_HIB_EN_TS_reserved_S 1 +#define HIB3P3_HIB_EN_TS_mem_hd_en_ts \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_1P8V_DET_EN register. +// +//****************************************************************************** +#define HIB3P3_HIB_1P8V_DET_EN_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1 +#define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_VBAT_MON_EN register. +// +//****************************************************************************** +#define HIB3P3_HIB_VBAT_MON_EN_reserved_M \ + 0xFFFFFFFC + +#define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2 +#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \ + 0x00000002 + +#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_NHIB_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_UART_RTS_SW_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \ + 0x00000001 + + + + +#endif // __HW_HIB3P3_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_i2c.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_i2c.h new file mode 100644 index 000000000..2a92d6e02 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_i2c.h @@ -0,0 +1,505 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the I2C register offsets. +// +//***************************************************************************** +#define I2C_O_MSA 0x00000000 +#define I2C_O_MCS 0x00000004 +#define I2C_O_MDR 0x00000008 +#define I2C_O_MTPR 0x0000000C +#define I2C_O_MIMR 0x00000010 +#define I2C_O_MRIS 0x00000014 +#define I2C_O_MMIS 0x00000018 +#define I2C_O_MICR 0x0000001C +#define I2C_O_MCR 0x00000020 +#define I2C_O_MCLKOCNT 0x00000024 +#define I2C_O_MBMON 0x0000002C +#define I2C_O_MBLEN 0x00000030 +#define I2C_O_MBCNT 0x00000034 +#define I2C_O_SOAR 0x00000800 +#define I2C_O_SCSR 0x00000804 +#define I2C_O_SDR 0x00000808 +#define I2C_O_SIMR 0x0000080C +#define I2C_O_SRIS 0x00000810 +#define I2C_O_SMIS 0x00000814 +#define I2C_O_SICR 0x00000818 +#define I2C_O_SOAR2 0x0000081C +#define I2C_O_SACKCTL 0x00000820 +#define I2C_O_FIFODATA 0x00000F00 +#define I2C_O_FIFOCTL 0x00000F04 +#define I2C_O_FIFOSTATUS 0x00000F08 +#define I2C_O_OBSMUXSEL0 0x00000F80 +#define I2C_O_OBSMUXSEL1 0x00000F84 +#define I2C_O_MUXROUTE 0x00000F88 +#define I2C_O_PV 0x00000FB0 +#define I2C_O_PP 0x00000FC0 +#define I2C_O_PC 0x00000FC4 +#define I2C_O_CC 0x00000FC8 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//****************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_SA_S 1 +#define I2C_MSA_RS 0x00000001 // Receive not send +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//****************************************************************************** +#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_BUSY 0x00000001 // I2C Busy +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//****************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // Data Transferred +#define I2C_MDR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//****************************************************************************** +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period +#define I2C_MTPR_TPR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//****************************************************************************** +#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt + // Mask +#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask +#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask +#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//****************************************************************************** +#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt + // Status +#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt + // Status +#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt + // Status +#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt + // Status +#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt + // Status +#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt + // Status +#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt + // Status +#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//****************************************************************************** +#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask +#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask +#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status +#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//****************************************************************************** +#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt + // Clear +#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt + // Clear +#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt + // Clear +#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt + // Clear +#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear +#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear +#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear +#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt + // Clear +#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear +#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//****************************************************************************** +#define I2C_MCR_MMD 0x00000040 // Multi-master Disable +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//****************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//****************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBLEN register. +// +//****************************************************************************** +#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length +#define I2C_MBLEN_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBCNT register. +// +//****************************************************************************** +#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count +#define I2C_MBCNT_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//****************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//****************************************************************************** +#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write +#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//****************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//****************************************************************************** +#define I2C_SIMR_IM 0x00000100 // Interrupt Mask +#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask +#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//****************************************************************************** +#define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status +#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt + // Status +#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt + // Status +#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//****************************************************************************** +#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt + // Status +#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt + // Status +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//****************************************************************************** +#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask +#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask +#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear +#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//****************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//****************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFODATA register. +// +//****************************************************************************** +#define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte +#define I2C_FIFODATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOCTL register. +// +//****************************************************************************** +#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment +#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush +#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable +#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger +#define I2C_FIFOCTL_RXTRIG_S 16 +#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment +#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush +#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable +#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger +#define I2C_FIFOCTL_TXTRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register. +// +//****************************************************************************** +#define I2C_FIFOSTATUS_RXABVTRIG \ + 0x00040000 // RX FIFO Above Trigger Level + +#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full +#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty +#define I2C_FIFOSTATUS_TXBLWTRIG \ + 0x00000004 // TX FIFO Below Trigger Level + +#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full +#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register. +// +//****************************************************************************** +#define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3 +#define I2C_OBSMUXSEL0_LN3_S 24 +#define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2 +#define I2C_OBSMUXSEL0_LN2_S 16 +#define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1 +#define I2C_OBSMUXSEL0_LN1_S 8 +#define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0 +#define I2C_OBSMUXSEL0_LN0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register. +// +//****************************************************************************** +#define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7 +#define I2C_OBSMUXSEL1_LN7_S 24 +#define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6 +#define I2C_OBSMUXSEL1_LN6_S 16 +#define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5 +#define I2C_OBSMUXSEL1_LN5_S 8 +#define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4 +#define I2C_OBSMUXSEL1_LN4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MUXROUTE register. +// +//****************************************************************************** +#define I2C_MUXROUTE_LN7ROUTE_M \ + 0x70000000 // Lane 7 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN7ROUTE_S 28 +#define I2C_MUXROUTE_LN6ROUTE_M \ + 0x07000000 // Lane 6 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN6ROUTE_S 24 +#define I2C_MUXROUTE_LN5ROUTE_M \ + 0x00700000 // Lane 5 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN5ROUTE_S 20 +#define I2C_MUXROUTE_LN4ROUTE_M \ + 0x00070000 // Lane 4 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN4ROUTE_S 16 +#define I2C_MUXROUTE_LN3ROUTE_M \ + 0x00007000 // Lane 3 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN3ROUTE_S 12 +#define I2C_MUXROUTE_LN2ROUTE_M \ + 0x00000700 // Lane 2 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN2ROUTE_S 8 +#define I2C_MUXROUTE_LN1ROUTE_M \ + 0x00000070 // Lane 1 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN1ROUTE_S 4 +#define I2C_MUXROUTE_LN0ROUTE_M \ + 0x00000007 // Lane 0 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN0ROUTE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PV register. +// +//****************************************************************************** +#define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision +#define I2C_PV_MAJOR_S 8 +#define I2C_PV_MINOR_M 0x000000FF // Minor Revision +#define I2C_PV_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//****************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//****************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_CC register. +// +//****************************************************************************** + + + +#endif // __HW_I2C_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_ints.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_ints.h new file mode 100644 index 000000000..62dd537a2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_ints.h @@ -0,0 +1,119 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on CC3200. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA0 16 // GPIO Port S0 +#define INT_GPIOA1 17 // GPIO Port S1 +#define INT_GPIOA2 18 // GPIO Port S2 +#define INT_GPIOA3 19 // GPIO Port S3 +#define INT_UARTA0 21 // UART0 Rx and Tx +#define INT_UARTA1 22 // UART1 Rx and Tx +#define INT_I2CA0 24 // I2C controller +#define INT_ADCCH0 30 // ADC Sequence 0 +#define INT_ADCCH1 31 // ADC Sequence 1 +#define INT_ADCCH2 32 // ADC Sequence 2 +#define INT_ADCCH3 33 // ADC Sequence 3 +#define INT_WDT 34 // Watchdog Timer0 +#define INT_TIMERA0A 35 // Timer 0 subtimer A +#define INT_TIMERA0B 36 // Timer 0 subtimer B +#define INT_TIMERA1A 37 // Timer 1 subtimer A +#define INT_TIMERA1B 38 // Timer 1 subtimer B +#define INT_TIMERA2A 39 // Timer 2 subtimer A +#define INT_TIMERA2B 40 // Timer 2 subtimer B +#define INT_FLASH 45 // FLASH Control +#define INT_TIMERA3A 51 // Timer 3 subtimer A +#define INT_TIMERA3B 52 // Timer 3 subtimer B +#define INT_UDMA 62 // uDMA controller +#define INT_UDMAERR 63 // uDMA Error +#define INT_SHA 164 // SHA +#define INT_AES 167 // AES +#define INT_DES 169 // DES +#define INT_MMCHS 175 // SDIO +#define INT_I2S 177 // McAPS +#define INT_CAMERA 179 // Camera +#define INT_NWPIC 187 // Interprocessor communication +#define INT_PRCM 188 // Power, Reset and Clock Module +#define INT_SSPI 191 // Shared SPI +#define INT_GSPI 192 // Generic SPI +#define INT_LSPI 193 // Link SPI + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 195 //The above number plus 2? + + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + + +#endif // __HW_INTS_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mcasp.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mcasp.h new file mode 100644 index 000000000..4e338534d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mcasp.h @@ -0,0 +1,1708 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_MCASP_H__ +#define __HW_MCASP_H__ + +//***************************************************************************** +// +// The following are defines for the MCASP register offsets. +// +//***************************************************************************** +#define MCASP_O_PID 0x00000000 +#define MCASP_O_ESYSCONFIG 0x00000004 // Power Idle SYSCONFIG register. +#define MCASP_O_PFUNC 0x00000010 +#define MCASP_O_PDIR 0x00000014 +#define MCASP_O_PDOUT 0x00000018 +#define MCASP_O_PDSET 0x0000001C // The pin data set register + // (PDSET) is an alias of the pin + // data output register (PDOUT) for + // writes only. Writing a 1 to the + // PDSET bit sets the corresponding + // bit in PDOUT and if PFUNC = 1 + // (GPIO function) and PDIR = 1 + // (output) drives a logic high on + // the pin. +#define MCASP_O_PDIN 0x0000001C // The pin data input register + // (PDIN) holds the I/O pin state of + // each of the McASP pins. PDIN + // allows the actual value of the + // pin to be read regardless of the + // state of PFUNC and PDIR. +#define MCASP_O_PDCLR 0x00000020 // The pin data clear register + // (PDCLR) is an alias of the pin + // data output register (PDOUT) for + // writes only. Writing a 1 to the + // PDCLR bit clears the + // corresponding bit in PDOUT and if + // PFUNC = 1 (GPIO function) and + // PDIR = 1 (output) drives a logic + // low on the pin. +#define MCASP_O_TLGC 0x00000030 // for IODFT +#define MCASP_O_TLMR 0x00000034 // for IODFT +#define MCASP_O_TLEC 0x00000038 // for IODFT +#define MCASP_O_GBLCTL 0x00000044 +#define MCASP_O_AMUTE 0x00000048 +#define MCASP_O_LBCTL 0x0000004C +#define MCASP_O_TXDITCTL 0x00000050 +#define MCASP_O_GBLCTLR 0x00000060 +#define MCASP_O_RXMASK 0x00000064 +#define MCASP_O_RXFMT 0x00000068 +#define MCASP_O_RXFMCTL 0x0000006C +#define MCASP_O_ACLKRCTL 0x00000070 +#define MCASP_O_AHCLKRCTL 0x00000074 +#define MCASP_O_RXTDM 0x00000078 +#define MCASP_O_EVTCTLR 0x0000007C +#define MCASP_O_RXSTAT 0x00000080 +#define MCASP_O_RXTDMSLOT 0x00000084 +#define MCASP_O_RXCLKCHK 0x00000088 +#define MCASP_O_REVTCTL 0x0000008C +#define MCASP_O_GBLCTLX 0x000000A0 +#define MCASP_O_TXMASK 0x000000A4 +#define MCASP_O_TXFMT 0x000000A8 +#define MCASP_O_TXFMCTL 0x000000AC +#define MCASP_O_ACLKXCTL 0x000000B0 +#define MCASP_O_AHCLKXCTL 0x000000B4 +#define MCASP_O_TXTDM 0x000000B8 +#define MCASP_O_EVTCTLX 0x000000BC +#define MCASP_O_TXSTAT 0x000000C0 +#define MCASP_O_TXTDMSLOT 0x000000C4 +#define MCASP_O_TXCLKCHK 0x000000C8 +#define MCASP_O_XEVTCTL 0x000000CC +#define MCASP_O_CLKADJEN 0x000000D0 +#define MCASP_O_DITCSRA0 0x00000100 +#define MCASP_O_DITCSRA1 0x00000104 +#define MCASP_O_DITCSRA2 0x00000108 +#define MCASP_O_DITCSRA3 0x0000010C +#define MCASP_O_DITCSRA4 0x00000110 +#define MCASP_O_DITCSRA5 0x00000114 +#define MCASP_O_DITCSRB0 0x00000118 +#define MCASP_O_DITCSRB1 0x0000011C +#define MCASP_O_DITCSRB2 0x00000120 +#define MCASP_O_DITCSRB3 0x00000124 +#define MCASP_O_DITCSRB4 0x00000128 +#define MCASP_O_DITCSRB5 0x0000012C +#define MCASP_O_DITUDRA0 0x00000130 +#define MCASP_O_DITUDRA1 0x00000134 +#define MCASP_O_DITUDRA2 0x00000138 +#define MCASP_O_DITUDRA3 0x0000013C +#define MCASP_O_DITUDRA4 0x00000140 +#define MCASP_O_DITUDRA5 0x00000144 +#define MCASP_O_DITUDRB0 0x00000148 +#define MCASP_O_DITUDRB1 0x0000014C +#define MCASP_O_DITUDRB2 0x00000150 +#define MCASP_O_DITUDRB3 0x00000154 +#define MCASP_O_DITUDRB4 0x00000158 +#define MCASP_O_DITUDRB5 0x0000015C +#define MCASP_O_XRSRCTL0 0x00000180 +#define MCASP_O_XRSRCTL1 0x00000184 +#define MCASP_O_XRSRCTL2 0x00000188 +#define MCASP_O_XRSRCTL3 0x0000018C +#define MCASP_O_XRSRCTL4 0x00000190 +#define MCASP_O_XRSRCTL5 0x00000194 +#define MCASP_O_XRSRCTL6 0x00000198 +#define MCASP_O_XRSRCTL7 0x0000019C +#define MCASP_O_XRSRCTL8 0x000001A0 +#define MCASP_O_XRSRCTL9 0x000001A4 +#define MCASP_O_XRSRCTL10 0x000001A8 +#define MCASP_O_XRSRCTL11 0x000001AC +#define MCASP_O_XRSRCTL12 0x000001B0 +#define MCASP_O_XRSRCTL13 0x000001B4 +#define MCASP_O_XRSRCTL14 0x000001B8 +#define MCASP_O_XRSRCTL15 0x000001BC +#define MCASP_O_TXBUF0 0x00000200 +#define MCASP_O_TXBUF1 0x00000204 +#define MCASP_O_TXBUF2 0x00000208 +#define MCASP_O_TXBUF3 0x0000020C +#define MCASP_O_TXBUF4 0x00000210 +#define MCASP_O_TXBUF5 0x00000214 +#define MCASP_O_TXBUF6 0x00000218 +#define MCASP_O_TXBUF7 0x0000021C +#define MCASP_O_TXBUF8 0x00000220 +#define MCASP_O_TXBUF9 0x00000224 +#define MCASP_O_TXBUF10 0x00000228 +#define MCASP_O_TXBUF11 0x0000022C +#define MCASP_O_TXBUF12 0x00000230 +#define MCASP_O_TXBUF13 0x00000234 +#define MCASP_O_TXBUF14 0x00000238 +#define MCASP_O_TXBUF15 0x0000023C +#define MCASP_O_RXBUF0 0x00000280 +#define MCASP_O_RXBUF1 0x00000284 +#define MCASP_O_RXBUF2 0x00000288 +#define MCASP_O_RXBUF3 0x0000028C +#define MCASP_O_RXBUF4 0x00000290 +#define MCASP_O_RXBUF5 0x00000294 +#define MCASP_O_RXBUF6 0x00000298 +#define MCASP_O_RXBUF7 0x0000029C +#define MCASP_O_RXBUF8 0x000002A0 +#define MCASP_O_RXBUF9 0x000002A4 +#define MCASP_O_RXBUF10 0x000002A8 +#define MCASP_O_RXBUF11 0x000002AC +#define MCASP_O_RXBUF12 0x000002B0 +#define MCASP_O_RXBUF13 0x000002B4 +#define MCASP_O_RXBUF14 0x000002B8 +#define MCASP_O_RXBUF15 0x000002BC +#define MCASP_0_WFIFOCTL 0x00001000 +#define MCASP_0_WFIFOSTS 0x00001004 +#define MCASP_0_RFIFOCTL 0x00001008 +#define MCASP_0_RFIFOSTS 0x0000100C + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PID register. +// +//****************************************************************************** +#define MCASP_PID_SCHEME_M 0xC0000000 +#define MCASP_PID_SCHEME_S 30 +#define MCASP_PID_RESV_M 0x30000000 +#define MCASP_PID_RESV_S 28 +#define MCASP_PID_FUNCTION_M 0x0FFF0000 // McASP +#define MCASP_PID_FUNCTION_S 16 +#define MCASP_PID_RTL_M 0x0000F800 +#define MCASP_PID_RTL_S 11 +#define MCASP_PID_REVMAJOR_M 0x00000700 +#define MCASP_PID_REVMAJOR_S 8 +#define MCASP_PID_CUSTOM_M 0x000000C0 // non-custom +#define MCASP_PID_CUSTOM_S 6 +#define MCASP_PID_REVMINOR_M 0x0000003F +#define MCASP_PID_REVMINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCASP_O_ESYSCONFIG register. +// +//****************************************************************************** +#define MCASP_ESYSCONFIG_RSV_M 0xFFFFFFC0 // Reserved as per PDR 3.5 +#define MCASP_ESYSCONFIG_RSV_S 6 +#define MCASP_ESYSCONFIG_OTHER_M \ + 0x0000003C // Reserved for future expansion + +#define MCASP_ESYSCONFIG_OTHER_S 2 +#define MCASP_ESYSCONFIG_IDLE_MODE_M \ + 0x00000003 // Idle Mode + +#define MCASP_ESYSCONFIG_IDLE_MODE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PFUNC register. +// +//****************************************************************************** +#define MCASP_PFUNC_AFSR 0x80000000 // AFSR PFUNC 31 0 1 +#define MCASP_PFUNC_AHCLKR 0x40000000 // AHCLKR PFUNC 30 0 1 +#define MCASP_PFUNC_ACLKR 0x20000000 // ACLKR PFUNC 29 0 1 +#define MCASP_PFUNC_AFSX 0x10000000 // AFSX PFUNC 28 0 1 +#define MCASP_PFUNC_AHCLKX 0x08000000 // AHCLKX PFUNC 27 0 1 +#define MCASP_PFUNC_ACLKX 0x04000000 // ACLKX PFUNC 26 0 1 +#define MCASP_PFUNC_AMUTE 0x02000000 // AMUTE PFUNC 25 0 1 +#define MCASP_PFUNC_RESV1_M 0x01FF0000 // Reserved +#define MCASP_PFUNC_RESV1_S 16 +#define MCASP_PFUNC_AXR15 0x00008000 // AXR PFUNC BIT 15 0 1 +#define MCASP_PFUNC_AXR14 0x00004000 // AXR PFUNC BIT 14 0 1 +#define MCASP_PFUNC_AXR13 0x00002000 // AXR PFUNC BIT 13 0 1 +#define MCASP_PFUNC_AXR12 0x00001000 // AXR PFUNC BIT 12 0 1 +#define MCASP_PFUNC_AXR11 0x00000800 // AXR PFUNC BIT 11 0 1 +#define MCASP_PFUNC_AXR10 0x00000400 // AXR PFUNC BIT 10 0 1 +#define MCASP_PFUNC_AXR9 0x00000200 // AXR PFUNC BIT 9 0 1 +#define MCASP_PFUNC_AXR8 0x00000100 // AXR PFUNC BIT 8 0 1 +#define MCASP_PFUNC_AXR7 0x00000080 // AXR PFUNC BIT 7 0 1 +#define MCASP_PFUNC_AXR6 0x00000040 // AXR PFUNC BIT 6 0 1 +#define MCASP_PFUNC_AXR5 0x00000020 // AXR PFUNC BIT 5 0 1 +#define MCASP_PFUNC_AXR4 0x00000010 // AXR PFUNC BIT 4 0 1 +#define MCASP_PFUNC_AXR3 0x00000008 // AXR PFUNC BIT 3 0 1 +#define MCASP_PFUNC_AXR2 0x00000004 // AXR PFUNC BIT 2 0 1 +#define MCASP_PFUNC_AXR1 0x00000002 // AXR PFUNC BIT 1 0 1 +#define MCASP_PFUNC_AXR0 0x00000001 // AXR PFUNC BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDIR register. +// +//****************************************************************************** +#define MCASP_PDIR_AFSR 0x80000000 // AFSR PDIR 31 0 1 +#define MCASP_PDIR_AHCLKR 0x40000000 // AHCLKR PDIR 30 0 1 +#define MCASP_PDIR_ACLKR 0x20000000 // ACLKR PDIR 29 0 1 +#define MCASP_PDIR_AFSX 0x10000000 // AFSX PDIR 28 0 1 +#define MCASP_PDIR_AHCLKX 0x08000000 // AHCLKX PDIR 27 0 1 +#define MCASP_PDIR_ACLKX 0x04000000 // ACLKX PDIR 26 0 1 +#define MCASP_PDIR_AMUTE 0x02000000 // AMUTE PDIR 25 0 1 +#define MCASP_PDIR_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDIR_RESV_S 16 +#define MCASP_PDIR_AXR15 0x00008000 // AXR PDIR BIT 15 0 1 +#define MCASP_PDIR_AXR14 0x00004000 // AXR PDIR BIT 14 0 1 +#define MCASP_PDIR_AXR13 0x00002000 // AXR PDIR BIT 13 0 1 +#define MCASP_PDIR_AXR12 0x00001000 // AXR PDIR BIT 12 0 1 +#define MCASP_PDIR_AXR11 0x00000800 // AXR PDIR BIT 11 0 1 +#define MCASP_PDIR_AXR10 0x00000400 // AXR PDIR BIT 10 0 1 +#define MCASP_PDIR_AXR9 0x00000200 // AXR PDIR BIT 9 0 1 +#define MCASP_PDIR_AXR8 0x00000100 // AXR PDIR BIT 8 0 1 +#define MCASP_PDIR_AXR7 0x00000080 // AXR PDIR BIT 7 0 1 +#define MCASP_PDIR_AXR6 0x00000040 // AXR PDIR BIT 6 0 1 +#define MCASP_PDIR_AXR5 0x00000020 // AXR PDIR BIT 5 0 1 +#define MCASP_PDIR_AXR4 0x00000010 // AXR PDIR BIT 4 0 1 +#define MCASP_PDIR_AXR3 0x00000008 // AXR PDIR BIT 3 0 1 +#define MCASP_PDIR_AXR2 0x00000004 // AXR PDIR BIT 2 0 1 +#define MCASP_PDIR_AXR1 0x00000002 // AXR PDIR BIT 1 0 1 +#define MCASP_PDIR_AXR0 0x00000001 // AXR PDIR BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDOUT register. +// +//****************************************************************************** +#define MCASP_PDOUT_AFSR 0x80000000 // AFSR PDOUT 31 0 1 +#define MCASP_PDOUT_AHCLKR 0x40000000 // AHCLKR PDOUT 30 0 1 +#define MCASP_PDOUT_ACLKR 0x20000000 // ACLKR PDOUT 29 0 1 +#define MCASP_PDOUT_AFSX 0x10000000 // AFSX PDOUT 28 0 1 +#define MCASP_PDOUT_AHCLKX 0x08000000 // AHCLKX PDOUT 27 0 1 +#define MCASP_PDOUT_ACLKX 0x04000000 // ACLKX PDOUT 26 0 1 +#define MCASP_PDOUT_AMUTE 0x02000000 // AMUTE PDOUT 25 0 1 +#define MCASP_PDOUT_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDOUT_RESV_S 16 +#define MCASP_PDOUT_AXR15 0x00008000 // AXR PDOUT BIT 15 0 1 +#define MCASP_PDOUT_AXR14 0x00004000 // AXR PDOUT BIT 14 0 1 +#define MCASP_PDOUT_AXR13 0x00002000 // AXR PDOUT BIT 13 0 1 +#define MCASP_PDOUT_AXR12 0x00001000 // AXR PDOUT BIT 12 0 1 +#define MCASP_PDOUT_AXR11 0x00000800 // AXR PDOUT BIT 11 0 1 +#define MCASP_PDOUT_AXR10 0x00000400 // AXR PDOUT BIT 10 0 1 +#define MCASP_PDOUT_AXR9 0x00000200 // AXR PDOUT BIT 9 0 1 +#define MCASP_PDOUT_AXR8 0x00000100 // AXR PDOUT BIT 8 0 1 +#define MCASP_PDOUT_AXR7 0x00000080 // AXR PDOUT BIT 7 0 1 +#define MCASP_PDOUT_AXR6 0x00000040 // AXR PDOUT BIT 6 0 1 +#define MCASP_PDOUT_AXR5 0x00000020 // AXR PDOUT BIT 5 0 1 +#define MCASP_PDOUT_AXR4 0x00000010 // AXR PDOUT BIT 4 0 1 +#define MCASP_PDOUT_AXR3 0x00000008 // AXR PDOUT BIT 3 0 1 +#define MCASP_PDOUT_AXR2 0x00000004 // AXR PDOUT BIT 2 0 1 +#define MCASP_PDOUT_AXR1 0x00000002 // AXR PDOUT BIT 1 0 1 +#define MCASP_PDOUT_AXR0 0x00000001 // AXR PDOUT BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDSET register. +// +//****************************************************************************** +#define MCASP_PDSET_AFSR 0x80000000 +#define MCASP_PDSET_AHCLKR 0x40000000 +#define MCASP_PDSET_ACLKR 0x20000000 +#define MCASP_PDSET_AFSX 0x10000000 +#define MCASP_PDSET_AHCLKX 0x08000000 +#define MCASP_PDSET_ACLKX 0x04000000 +#define MCASP_PDSET_AMUTE 0x02000000 +#define MCASP_PDSET_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDSET_RESV_S 16 +#define MCASP_PDSET_AXR15 0x00008000 +#define MCASP_PDSET_AXR14 0x00004000 +#define MCASP_PDSET_AXR13 0x00002000 +#define MCASP_PDSET_AXR12 0x00001000 +#define MCASP_PDSET_AXR11 0x00000800 +#define MCASP_PDSET_AXR10 0x00000400 +#define MCASP_PDSET_AXR9 0x00000200 +#define MCASP_PDSET_AXR8 0x00000100 +#define MCASP_PDSET_AXR7 0x00000080 +#define MCASP_PDSET_AXR6 0x00000040 +#define MCASP_PDSET_AXR5 0x00000020 +#define MCASP_PDSET_AXR4 0x00000010 +#define MCASP_PDSET_AXR3 0x00000008 +#define MCASP_PDSET_AXR2 0x00000004 +#define MCASP_PDSET_AXR1 0x00000002 +#define MCASP_PDSET_AXR0 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDIN register. +// +//****************************************************************************** +#define MCASP_PDIN_AFSR 0x80000000 +#define MCASP_PDIN_AHCLKR 0x40000000 +#define MCASP_PDIN_ACLKR 0x20000000 +#define MCASP_PDIN_AFSX 0x10000000 +#define MCASP_PDIN_AHCLKX 0x08000000 +#define MCASP_PDIN_ACLKX 0x04000000 +#define MCASP_PDIN_AMUTE 0x02000000 +#define MCASP_PDIN_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDIN_RESV_S 16 +#define MCASP_PDIN_AXR15 0x00008000 +#define MCASP_PDIN_AXR14 0x00004000 +#define MCASP_PDIN_AXR13 0x00002000 +#define MCASP_PDIN_AXR12 0x00001000 +#define MCASP_PDIN_AXR11 0x00000800 +#define MCASP_PDIN_AXR10 0x00000400 +#define MCASP_PDIN_AXR9 0x00000200 +#define MCASP_PDIN_AXR8 0x00000100 +#define MCASP_PDIN_AXR7 0x00000080 +#define MCASP_PDIN_AXR6 0x00000040 +#define MCASP_PDIN_AXR5 0x00000020 +#define MCASP_PDIN_AXR4 0x00000010 +#define MCASP_PDIN_AXR3 0x00000008 +#define MCASP_PDIN_AXR2 0x00000004 +#define MCASP_PDIN_AXR1 0x00000002 +#define MCASP_PDIN_AXR0 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDCLR register. +// +//****************************************************************************** +#define MCASP_PDCLR_AFSR 0x80000000 // AFSR PDCLR 31 0 1 +#define MCASP_PDCLR_AHCLKR 0x40000000 // AHCLKR PDCLR 30 0 1 +#define MCASP_PDCLR_ACLKR 0x20000000 // ACLKR PDCLR 29 0 1 +#define MCASP_PDCLR_AFSX 0x10000000 // AFSX PDCLR 28 0 1 +#define MCASP_PDCLR_AHCLKX 0x08000000 // AHCLKX PDCLR 27 0 1 +#define MCASP_PDCLR_ACLKX 0x04000000 // ACLKX PDCLR 26 0 1 +#define MCASP_PDCLR_AMUTE 0x02000000 // AMUTE PDCLR 25 0 1 +#define MCASP_PDCLR_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDCLR_RESV_S 16 +#define MCASP_PDCLR_AXR15 0x00008000 // AXR PDCLR BIT 15 0 1 +#define MCASP_PDCLR_AXR14 0x00004000 // AXR PDCLR BIT 14 0 1 +#define MCASP_PDCLR_AXR13 0x00002000 // AXR PDCLR BIT 13 0 1 +#define MCASP_PDCLR_AXR12 0x00001000 // AXR PDCLR BIT 12 0 1 +#define MCASP_PDCLR_AXR11 0x00000800 // AXR PDCLR BIT 11 0 1 +#define MCASP_PDCLR_AXR10 0x00000400 // AXR PDCLR BIT 10 0 1 +#define MCASP_PDCLR_AXR9 0x00000200 // AXR PDCLR BIT 9 0 1 +#define MCASP_PDCLR_AXR8 0x00000100 // AXR PDCLR BIT 8 0 1 +#define MCASP_PDCLR_AXR7 0x00000080 // AXR PDCLR BIT 7 0 1 +#define MCASP_PDCLR_AXR6 0x00000040 // AXR PDCLR BIT 6 0 1 +#define MCASP_PDCLR_AXR5 0x00000020 // AXR PDCLR BIT 5 0 1 +#define MCASP_PDCLR_AXR4 0x00000010 // AXR PDCLR BIT 4 0 1 +#define MCASP_PDCLR_AXR3 0x00000008 // AXR PDCLR BIT 3 0 1 +#define MCASP_PDCLR_AXR2 0x00000004 // AXR PDCLR BIT 2 0 1 +#define MCASP_PDCLR_AXR1 0x00000002 // AXR PDCLR BIT 1 0 1 +#define MCASP_PDCLR_AXR0 0x00000001 // AXR PDCLR BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLGC register. +// +//****************************************************************************** +#define MCASP_TLGC_RESV_M 0xFFFF0000 // Reserved +#define MCASP_TLGC_RESV_S 16 +#define MCASP_TLGC_MT_M 0x0000C000 // MISR on/off trigger command 0x0 + // 0x1 0x2 0x3 +#define MCASP_TLGC_MT_S 14 +#define MCASP_TLGC_RESV1_M 0x00003E00 // Reserved +#define MCASP_TLGC_RESV1_S 9 +#define MCASP_TLGC_MMS 0x00000100 // Source of MISR input 0 1 +#define MCASP_TLGC_ESEL 0x00000080 // Output enable select 0 1 +#define MCASP_TLGC_TOEN 0x00000040 // Test output enable control. 0 1 +#define MCASP_TLGC_MC_M 0x00000030 // States of MISR 0x0 0x1 0x2 0x3 +#define MCASP_TLGC_MC_S 4 +#define MCASP_TLGC_PC_M 0x0000000E // Pattern code 0x0 0x1 0x2 0x3 0x4 + // 0x5 0x6 0x7 +#define MCASP_TLGC_PC_S 1 +#define MCASP_TLGC_TM 0x00000001 // Tie high; do not write to this + // bit 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLMR register. +// +//****************************************************************************** +#define MCASP_TLMR_TLMR_M 0xFFFFFFFF // Contains test result signature. +#define MCASP_TLMR_TLMR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLEC register. +// +//****************************************************************************** +#define MCASP_TLEC_TLEC_M 0xFFFFFFFF // Contains number of cycles during + // which MISR sig will be + // accumulated. +#define MCASP_TLEC_TLEC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTL register. +// +//****************************************************************************** +#define MCASP_GBLCTL_XFRST 0x00001000 // Frame sync generator reset 0 1 +#define MCASP_GBLCTL_XSMRST 0x00000800 // XMT state machine reset 0 1 +#define MCASP_GBLCTL_XSRCLR 0x00000400 // XMT serializer clear 0 1 +#define MCASP_GBLCTL_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 +#define MCASP_GBLCTL_XCLKRST 0x00000100 // XMT clock divder reset 0 1 +#define MCASP_GBLCTL_RFRST 0x00000010 // Frame sync generator reset 0 1 +#define MCASP_GBLCTL_RSMRST 0x00000008 // RCV state machine reset 0 1 +#define MCASP_GBLCTL_RSRCLR 0x00000004 // RCV serializer clear 0 1 +#define MCASP_GBLCTL_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 +#define MCASP_GBLCTL_RCLKRST 0x00000001 // RCV clock divder reset 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AMUTE register. +// +//****************************************************************************** +#define MCASP_AMUTE_XDMAERR 0x00001000 // MUTETXDMAERR occur 0 1 +#define MCASP_AMUTE_RDMAERR 0x00000800 // MUTERXDMAERR occur 0 1 +#define MCASP_AMUTE_XCKFAIL 0x00000400 // XMT bad clock 0 1 +#define MCASP_AMUTE_RCKFAIL 0x00000200 // RCV bad clock 0 1 +#define MCASP_AMUTE_XSYNCERR 0x00000100 // XMT unexpected FS 0 1 +#define MCASP_AMUTE_RSYNCERR 0x00000080 // RCV unexpected FS 0 1 +#define MCASP_AMUTE_XUNDRN 0x00000040 // XMT underrun occurs 0 1 +#define MCASP_AMUTE_ROVRN 0x00000020 // RCV overun occurs 0 1 +#define MCASP_AMUTE_INSTAT 0x00000010 +#define MCASP_AMUTE_INEN 0x00000008 // drive AMUTE active on mute in + // active 0 1 +#define MCASP_AMUTE_INPOL 0x00000004 // Mute input polarity 0 1 +#define MCASP_AMUTE_MUTEN_M 0x00000003 // AMUTE pin enable 0x0 0x1 0x2 +#define MCASP_AMUTE_MUTEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_LBCTL register. +// +//****************************************************************************** +#define MCASP_LBCTL_IOLBEN 0x00000010 // IO loopback enable 0 1 +#define MCASP_LBCTL_MODE_M 0x0000000C // Loop back clock source generator + // 0x0 0x1 0x2 0x3 +#define MCASP_LBCTL_MODE_S 2 +#define MCASP_LBCTL_ORD 0x00000002 // Loopback order 0 1 +#define MCASP_LBCTL_DLBEN 0x00000001 // Loop back mode 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXDITCTL register. +// +//****************************************************************************** +#define MCASP_TXDITCTL_VB 0x00000008 // Valib bit for odd TDM 0 1 +#define MCASP_TXDITCTL_VA 0x00000004 // Valib bit for even TDM 0 1 +#define MCASP_TXDITCTL_DITEN 0x00000001 // XMT DIT Mode Enable 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTLR register. +// +//****************************************************************************** +#define MCASP_GBLCTLR_XFRST 0x00001000 +#define MCASP_GBLCTLR_XSMRST 0x00000800 +#define MCASP_GBLCTLR_XSRCLR 0x00000400 +#define MCASP_GBLCTLR_XHCLKRST 0x00000200 +#define MCASP_GBLCTLR_XCLKRST 0x00000100 +#define MCASP_GBLCTLR_RFRST 0x00000010 // Frame sync generator reset 0 1 +#define MCASP_GBLCTLR_RSMRST 0x00000008 // RCV state machine reset 0 1 +#define MCASP_GBLCTLR_RSRCLR 0x00000004 // RCV serializer clear 0 1 +#define MCASP_GBLCTLR_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 +#define MCASP_GBLCTLR_RCLKRST 0x00000001 // RCV clock divder reset 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXMASK register. +// +//****************************************************************************** +#define MCASP_RXMASK_RMASK31 0x80000000 // RMASK BIT 31 0 1 +#define MCASP_RXMASK_RMASK30 0x40000000 // RMASK BIT 30 0 1 +#define MCASP_RXMASK_RMASK29 0x20000000 // RMASK BIT 29 0 1 +#define MCASP_RXMASK_RMASK28 0x10000000 // RMASK BIT 28 0 1 +#define MCASP_RXMASK_RMASK27 0x08000000 // RMASK BIT 27 0 1 +#define MCASP_RXMASK_RMASK26 0x04000000 // RMASK BIT 26 0 1 +#define MCASP_RXMASK_RMASK25 0x02000000 // RMASK BIT 25 0 1 +#define MCASP_RXMASK_RMASK24 0x01000000 // RMASK BIT 24 0 1 +#define MCASP_RXMASK_RMASK23 0x00800000 // RMASK BIT 23 0 1 +#define MCASP_RXMASK_RMASK22 0x00400000 // RMASK BIT 22 0 1 +#define MCASP_RXMASK_RMASK21 0x00200000 // RMASK BIT 21 0 1 +#define MCASP_RXMASK_RMASK20 0x00100000 // RMASK BIT 20 0 1 +#define MCASP_RXMASK_RMASK19 0x00080000 // RMASK BIT 19 0 1 +#define MCASP_RXMASK_RMASK18 0x00040000 // RMASK BIT 18 0 1 +#define MCASP_RXMASK_RMASK17 0x00020000 // RMASK BIT 17 0 1 +#define MCASP_RXMASK_RMASK16 0x00010000 // RMASK BIT 16 0 1 +#define MCASP_RXMASK_RMASK15 0x00008000 // RMASK BIT 15 0 1 +#define MCASP_RXMASK_RMASK14 0x00004000 // RMASK BIT 14 0 1 +#define MCASP_RXMASK_RMASK13 0x00002000 // RMASK BIT 13 0 1 +#define MCASP_RXMASK_RMASK12 0x00001000 // RMASK BIT 12 0 1 +#define MCASP_RXMASK_RMASK11 0x00000800 // RMASK BIT 11 0 1 +#define MCASP_RXMASK_RMASK10 0x00000400 // RMASK BIT 10 0 1 +#define MCASP_RXMASK_RMASK9 0x00000200 // RMASK BIT 9 0 1 +#define MCASP_RXMASK_RMASK8 0x00000100 // RMASK BIT 8 0 1 +#define MCASP_RXMASK_RMASK7 0x00000080 // RMASK BIT 7 0 1 +#define MCASP_RXMASK_RMASK6 0x00000040 // RMASK BIT 6 0 1 +#define MCASP_RXMASK_RMASK5 0x00000020 // RMASK BIT 5 0 1 +#define MCASP_RXMASK_RMASK4 0x00000010 // RMASK BIT 4 0 1 +#define MCASP_RXMASK_RMASK3 0x00000008 // RMASK BIT 3 0 1 +#define MCASP_RXMASK_RMASK2 0x00000004 // RMASK BIT 2 0 1 +#define MCASP_RXMASK_RMASK1 0x00000002 // RMASK BIT 1 0 1 +#define MCASP_RXMASK_RMASK0 0x00000001 // RMASK BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXFMT register. +// +//****************************************************************************** +#define MCASP_RXFMT_RDATDLY_M 0x00030000 // RCV Frame sync delay 0x0 0 Bit + // delay 0x1 1 Bit delay 0x2 2 Bit + // delay +#define MCASP_RXFMT_RDATDLY_S 16 +#define MCASP_RXFMT_RRVRS 0x00008000 // RCV serial stream bit order 0 1 +#define MCASP_RXFMT_RPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 +#define MCASP_RXFMT_RPAD_S 13 +#define MCASP_RXFMT_RPBIT_M 0x00001F00 // Pad bit position +#define MCASP_RXFMT_RPBIT_S 8 +#define MCASP_RXFMT_RSSZ_M 0x000000F0 // RCV slot Size 0x0 0x1 0x2 0x3 + // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB + // 0xC 0xD 0xE 0xF +#define MCASP_RXFMT_RSSZ_S 4 +#define MCASP_RXFMT_RBUSEL 0x00000008 // Write to RBUF using CPU/DMA 0 + // DMA port access 1 CPU port Access +#define MCASP_RXFMT_RROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 + // 0x3 0x4 0x5 0x6 0x7 +#define MCASP_RXFMT_RROT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXFMCTL register. +// +//****************************************************************************** +#define MCASP_RXFMCTL_RMOD_M 0x0000FF80 // RCV Frame sync mode +#define MCASP_RXFMCTL_RMOD_S 7 +#define MCASP_RXFMCTL_FRWID 0x00000010 // RCV Frame sync Duration 0 1 +#define MCASP_RXFMCTL_FSRM 0x00000002 // RCV frame sync External 0 1 +#define MCASP_RXFMCTL_FSRP 0x00000001 // RCV Frame sync Polarity 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_ACLKRCTL register. +// +//****************************************************************************** +#define MCASP_ACLKRCTL_BUSY 0x00100000 +#define MCASP_ACLKRCTL_DIVBUSY 0x00080000 +#define MCASP_ACLKRCTL_ADJBUSY 0x00040000 +#define MCASP_ACLKRCTL_CLKRADJ_M \ + 0x00030000 + +#define MCASP_ACLKRCTL_CLKRADJ_S 16 +#define MCASP_ACLKRCTL_CLKRP 0x00000080 // RCV Clock Polarity 0 1 +#define MCASP_ACLKRCTL_CLKRM 0x00000020 // RCV clock source 0 1 +#define MCASP_ACLKRCTL_CLKRDIV_M \ + 0x0000001F // RCV clock devide ratio + +#define MCASP_ACLKRCTL_CLKRDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AHCLKRCTL register. +// +//****************************************************************************** +#define MCASP_AHCLKRCTL_BUSY 0x00100000 +#define MCASP_AHCLKRCTL_DIVBUSY 0x00080000 +#define MCASP_AHCLKRCTL_ADJBUSY 0x00040000 +#define MCASP_AHCLKRCTL_HCLKRADJ_M \ + 0x00030000 + +#define MCASP_AHCLKRCTL_HCLKRADJ_S 16 +#define MCASP_AHCLKRCTL_HCLKRM 0x00008000 // High Freq. RCV clock Source 0 1 +#define MCASP_AHCLKRCTL_HCLKRP 0x00004000 // High Freq. clock Polarity Before + // diviser 0 1 +#define MCASP_AHCLKRCTL_HCLKRDIV_M \ + 0x00000FFF // RCV clock Divide Ratio + +#define MCASP_AHCLKRCTL_HCLKRDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXTDM register. +// +//****************************************************************************** +#define MCASP_RXTDM_RTDMS31 0x80000000 // RCV mode during TDM time slot 31 + // 0 1 +#define MCASP_RXTDM_RTDMS30 0x40000000 // RCV mode during TDM time slot 30 + // 0 1 +#define MCASP_RXTDM_RTDMS29 0x20000000 // RCV mode during TDM time slot 29 + // 0 1 +#define MCASP_RXTDM_RTDMS28 0x10000000 // RCV mode during TDM time slot 28 + // 0 1 +#define MCASP_RXTDM_RTDMS27 0x08000000 // RCV mode during TDM time slot 27 + // 0 1 +#define MCASP_RXTDM_RTDMS26 0x04000000 // RCV mode during TDM time slot 26 + // 0 1 +#define MCASP_RXTDM_RTDMS25 0x02000000 // RCV mode during TDM time slot 25 + // 0 1 +#define MCASP_RXTDM_RTDMS24 0x01000000 // RCV mode during TDM time slot 24 + // 0 1 +#define MCASP_RXTDM_RTDMS23 0x00800000 // RCV mode during TDM time slot 23 + // 0 1 +#define MCASP_RXTDM_RTDMS22 0x00400000 // RCV mode during TDM time slot 22 + // 0 1 +#define MCASP_RXTDM_RTDMS21 0x00200000 // RCV mode during TDM time slot 21 + // 0 1 +#define MCASP_RXTDM_RTDMS20 0x00100000 // RCV mode during TDM time slot 20 + // 0 1 +#define MCASP_RXTDM_RTDMS19 0x00080000 // RCV mode during TDM time slot 19 + // 0 1 +#define MCASP_RXTDM_RTDMS18 0x00040000 // RCV mode during TDM time slot 18 + // 0 1 +#define MCASP_RXTDM_RTDMS17 0x00020000 // RCV mode during TDM time slot 17 + // 0 1 +#define MCASP_RXTDM_RTDMS16 0x00010000 // RCV mode during TDM time slot 16 + // 0 1 +#define MCASP_RXTDM_RTDMS15 0x00008000 // RCV mode during TDM time slot 15 + // 0 1 +#define MCASP_RXTDM_RTDMS14 0x00004000 // RCV mode during TDM time slot 14 + // 0 1 +#define MCASP_RXTDM_RTDMS13 0x00002000 // RCV mode during TDM time slot 13 + // 0 1 +#define MCASP_RXTDM_RTDMS12 0x00001000 // RCV mode during TDM time slot 12 + // 0 1 +#define MCASP_RXTDM_RTDMS11 0x00000800 // RCV mode during TDM time slot 11 + // 0 1 +#define MCASP_RXTDM_RTDMS10 0x00000400 // RCV mode during TDM time slot 10 + // 0 1 +#define MCASP_RXTDM_RTDMS9 0x00000200 // RCV mode during TDM time slot 9 + // 0 1 +#define MCASP_RXTDM_RTDMS8 0x00000100 // RCV mode during TDM time slot 8 + // 0 1 +#define MCASP_RXTDM_RTDMS7 0x00000080 // RCV mode during TDM time slot 7 + // 0 1 +#define MCASP_RXTDM_RTDMS6 0x00000040 // RCV mode during TDM time slot 6 + // 0 1 +#define MCASP_RXTDM_RTDMS5 0x00000020 // RCV mode during TDM time slot 5 + // 0 1 +#define MCASP_RXTDM_RTDMS4 0x00000010 // RCV mode during TDM time slot 4 + // 0 1 +#define MCASP_RXTDM_RTDMS3 0x00000008 // RCV mode during TDM time slot 3 + // 0 1 +#define MCASP_RXTDM_RTDMS2 0x00000004 // RCV mode during TDM time slot 2 + // 0 1 +#define MCASP_RXTDM_RTDMS1 0x00000002 // RCV mode during TDM time slot 1 + // 0 1 +#define MCASP_RXTDM_RTDMS0 0x00000001 // RCV mode during TDM time slot 0 + // 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_EVTCTLR register. +// +//****************************************************************************** +#define MCASP_EVTCTLR_RSTAFRM 0x00000080 // RCV Start of Frame Interrupt 0 1 +#define MCASP_EVTCTLR_RDATA 0x00000020 // RCV Data Interrupt 0 1 +#define MCASP_EVTCTLR_RLAST 0x00000010 // RCV Last Slot Interrupt 0 1 +#define MCASP_EVTCTLR_RDMAERR 0x00000008 // RCV DMA Bus Error 0 1 +#define MCASP_EVTCTLR_RCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 +#define MCASP_EVTCTLR_RSYNCERR 0x00000002 // RCV Unexpected FSR Interrupt 0 1 +#define MCASP_EVTCTLR_ROVRN 0x00000001 // RCV Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXSTAT register. +// +//****************************************************************************** +#define MCASP_RXSTAT_RERR 0x00000100 // RCV Error 0 1 +#define MCASP_RXSTAT_RDMAERR 0x00000080 // RCV DMA bus error 0 1 +#define MCASP_RXSTAT_RSTAFRM 0x00000040 // Start of Frame-RCV 0 1 +#define MCASP_RXSTAT_RDATA 0x00000020 // Data Ready Flag 0 1 +#define MCASP_RXSTAT_RLAST 0x00000010 // Last Slot Interrupt Flag 0 1 +#define MCASP_RXSTAT_RTDMSLOT 0x00000008 // EvenOdd Slot 0 1 +#define MCASP_RXSTAT_RCKFAIL 0x00000004 // Bad Transmit Flag 0 1 +#define MCASP_RXSTAT_RSYNCERR 0x00000002 // Unexpected RCV Frame sync flag 0 + // 1 +#define MCASP_RXSTAT_ROVRN 0x00000001 // RCV Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXTDMSLOT register. +// +//****************************************************************************** +#define MCASP_RXTDMSLOT_RSLOTCNT_M \ + 0x000003FF // Current RCV time slot count + +#define MCASP_RXTDMSLOT_RSLOTCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXCLKCHK register. +// +//****************************************************************************** +#define MCASP_RXCLKCHK_RCNT_M 0xFF000000 // RCV clock count value +#define MCASP_RXCLKCHK_RCNT_S 24 +#define MCASP_RXCLKCHK_RMAX_M 0x00FF0000 // RCV clock maximum boundary +#define MCASP_RXCLKCHK_RMAX_S 16 +#define MCASP_RXCLKCHK_RMIN_M 0x0000FF00 // RCV clock minimum boundary +#define MCASP_RXCLKCHK_RMIN_S 8 +#define MCASP_RXCLKCHK_RPS_M 0x0000000F // RCV clock check prescaler 0x0 + // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 +#define MCASP_RXCLKCHK_RPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_REVTCTL register. +// +//****************************************************************************** +#define MCASP_REVTCTL_RDATDMA 0x00000001 // RCV data DMA request 0 Enable + // DMA Transfer 1 Disable DMA + // Transfer +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTLX register. +// +//****************************************************************************** +#define MCASP_GBLCTLX_XFRST 0x00001000 // Frame sync generator reset 0 1 +#define MCASP_GBLCTLX_XSMRST 0x00000800 // XMT state machine reset 0 1 +#define MCASP_GBLCTLX_XSRCLR 0x00000400 // XMT serializer clear 0 1 +#define MCASP_GBLCTLX_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 +#define MCASP_GBLCTLX_XCLKRST 0x00000100 // XMT clock divder reset 0 1 +#define MCASP_GBLCTLX_RFRST 0x00000010 +#define MCASP_GBLCTLX_RSMRST 0x00000008 +#define MCASP_GBLCTLX_RSRCLKR 0x00000004 +#define MCASP_GBLCTLX_RHCLKRST 0x00000002 +#define MCASP_GBLCTLX_RCLKRST 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXMASK register. +// +//****************************************************************************** +#define MCASP_TXMASK_XMASK31 0x80000000 // XMASK BIT 31 0 1 +#define MCASP_TXMASK_XMASK30 0x40000000 // XMASK BIT 30 0 1 +#define MCASP_TXMASK_XMASK29 0x20000000 // XMASK BIT 29 0 1 +#define MCASP_TXMASK_XMASK28 0x10000000 // XMASK BIT 28 0 1 +#define MCASP_TXMASK_XMASK27 0x08000000 // XMASK BIT 27 0 1 +#define MCASP_TXMASK_XMASK26 0x04000000 // XMASK BIT 26 0 1 +#define MCASP_TXMASK_XMASK25 0x02000000 // XMASK BIT 25 0 1 +#define MCASP_TXMASK_XMASK24 0x01000000 // XMASK BIT 24 0 1 +#define MCASP_TXMASK_XMASK23 0x00800000 // XMASK BIT 23 0 1 +#define MCASP_TXMASK_XMASK22 0x00400000 // XMASK BIT 22 0 1 +#define MCASP_TXMASK_XMASK21 0x00200000 // XMASK BIT 21 0 1 +#define MCASP_TXMASK_XMASK20 0x00100000 // XMASK BIT 20 0 1 +#define MCASP_TXMASK_XMASK19 0x00080000 // XMASK BIT 19 0 1 +#define MCASP_TXMASK_XMASK18 0x00040000 // XMASK BIT 18 0 1 +#define MCASP_TXMASK_XMASK17 0x00020000 // XMASK BIT 17 0 1 +#define MCASP_TXMASK_XMASK16 0x00010000 // XMASK BIT 16 0 1 +#define MCASP_TXMASK_XMASK15 0x00008000 // XMASK BIT 15 0 1 +#define MCASP_TXMASK_XMASK14 0x00004000 // XMASK BIT 14 0 1 +#define MCASP_TXMASK_XMASK13 0x00002000 // XMASK BIT 13 0 1 +#define MCASP_TXMASK_XMASK12 0x00001000 // XMASK BIT 12 0 1 +#define MCASP_TXMASK_XMASK11 0x00000800 // XMASK BIT 11 0 1 +#define MCASP_TXMASK_XMASK10 0x00000400 // XMASK BIT 10 0 1 +#define MCASP_TXMASK_XMASK9 0x00000200 // XMASK BIT 9 0 1 +#define MCASP_TXMASK_XMASK8 0x00000100 // XMASK BIT 8 0 1 +#define MCASP_TXMASK_XMASK7 0x00000080 // XMASK BIT 7 0 1 +#define MCASP_TXMASK_XMASK6 0x00000040 // XMASK BIT 6 0 1 +#define MCASP_TXMASK_XMASK5 0x00000020 // XMASK BIT 5 0 1 +#define MCASP_TXMASK_XMASK4 0x00000010 // XMASK BIT 4 0 1 +#define MCASP_TXMASK_XMASK3 0x00000008 // XMASK BIT 3 0 1 +#define MCASP_TXMASK_XMASK2 0x00000004 // XMASK BIT 2 0 1 +#define MCASP_TXMASK_XMASK1 0x00000002 // XMASK BIT 1 0 1 +#define MCASP_TXMASK_XMASK0 0x00000001 // XMASK BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXFMT register. +// +//****************************************************************************** +#define MCASP_TXFMT_XDATDLY_M 0x00030000 // XMT Frame sync delay 0x0 0 Bit + // delay 0x1 1 Bit delay 0x2 2 Bit + // delay +#define MCASP_TXFMT_XDATDLY_S 16 +#define MCASP_TXFMT_XRVRS 0x00008000 // XMT serial stream bit order 0 1 +#define MCASP_TXFMT_XPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 +#define MCASP_TXFMT_XPAD_S 13 +#define MCASP_TXFMT_XPBIT_M 0x00001F00 // Pad bit position +#define MCASP_TXFMT_XPBIT_S 8 +#define MCASP_TXFMT_XSSZ_M 0x000000F0 // XMT slot Size 0x0 0x1 0x2 0x3 + // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB + // 0xC 0xD 0xE 0xF +#define MCASP_TXFMT_XSSZ_S 4 +#define MCASP_TXFMT_XBUSEL 0x00000008 // Write to XBUF using CPU/DMA 0 + // DMA port access 1 CPU port Access +#define MCASP_TXFMT_XROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 + // 0x3 0x4 0x5 0x6 0x7 +#define MCASP_TXFMT_XROT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXFMCTL register. +// +//****************************************************************************** +#define MCASP_TXFMCTL_XMOD_M 0x0000FF80 // XMT Frame sync mode +#define MCASP_TXFMCTL_XMOD_S 7 +#define MCASP_TXFMCTL_FXWID 0x00000010 // XMT Frame sync Duration 0 1 +#define MCASP_TXFMCTL_FSXM 0x00000002 // XMT frame sync External 0 1 +#define MCASP_TXFMCTL_FSXP 0x00000001 // XMT Frame sync Polarity 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_ACLKXCTL register. +// +//****************************************************************************** +#define MCASP_ACLKXCTL_BUSY 0x00100000 +#define MCASP_ACLKXCTL_DIVBUSY 0x00080000 +#define MCASP_ACLKXCTL_ADJBUSY 0x00040000 +#define MCASP_ACLKXCTL_CLKXADJ_M \ + 0x00030000 + +#define MCASP_ACLKXCTL_CLKXADJ_S 16 +#define MCASP_ACLKXCTL_CLKXP 0x00000080 // XMT Clock Polarity 0 1 +#define MCASP_ACLKXCTL_ASYNC 0x00000040 // XMT/RCV operation sync /Async 0 + // 1 +#define MCASP_ACLKXCTL_CLKXM 0x00000020 // XMT clock source 0 1 +#define MCASP_ACLKXCTL_CLKXDIV_M \ + 0x0000001F // XMT clock devide ratio + +#define MCASP_ACLKXCTL_CLKXDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AHCLKXCTL register. +// +//****************************************************************************** +#define MCASP_AHCLKXCTL_BUSY 0x00100000 +#define MCASP_AHCLKXCTL_DIVBUSY 0x00080000 +#define MCASP_AHCLKXCTL_ADJBUSY 0x00040000 +#define MCASP_AHCLKXCTL_HCLKXADJ_M \ + 0x00030000 + +#define MCASP_AHCLKXCTL_HCLKXADJ_S 16 +#define MCASP_AHCLKXCTL_HCLKXM 0x00008000 // High Freq. XMT clock Source 0 1 +#define MCASP_AHCLKXCTL_HCLKXP 0x00004000 // High Freq. clock Polarity Before + // diviser 0 1 +#define MCASP_AHCLKXCTL_HCLKXDIV_M \ + 0x00000FFF // XMT clock Divide Ratio + +#define MCASP_AHCLKXCTL_HCLKXDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXTDM register. +// +//****************************************************************************** +#define MCASP_TXTDM_XTDMS31 0x80000000 // XMT mode during TDM time slot 31 + // 0 1 +#define MCASP_TXTDM_XTDMS30 0x40000000 // XMT mode during TDM time slot 30 + // 0 1 +#define MCASP_TXTDM_XTDMS29 0x20000000 // XMT mode during TDM time slot 29 + // 0 1 +#define MCASP_TXTDM_XTDMS28 0x10000000 // XMT mode during TDM time slot 28 + // 0 1 +#define MCASP_TXTDM_XTDMS27 0x08000000 // XMT mode during TDM time slot 27 + // 0 1 +#define MCASP_TXTDM_XTDMS26 0x04000000 // XMT mode during TDM time slot 26 + // 0 1 +#define MCASP_TXTDM_XTDMS25 0x02000000 // XMT mode during TDM time slot 25 + // 0 1 +#define MCASP_TXTDM_XTDMS24 0x01000000 // XMT mode during TDM time slot 24 + // 0 1 +#define MCASP_TXTDM_XTDMS23 0x00800000 // XMT mode during TDM time slot 23 + // 0 1 +#define MCASP_TXTDM_XTDMS22 0x00400000 // XMT mode during TDM time slot 22 + // 0 1 +#define MCASP_TXTDM_XTDMS21 0x00200000 // XMT mode during TDM time slot 21 + // 0 1 +#define MCASP_TXTDM_XTDMS20 0x00100000 // XMT mode during TDM time slot 20 + // 0 1 +#define MCASP_TXTDM_XTDMS19 0x00080000 // XMT mode during TDM time slot 19 + // 0 1 +#define MCASP_TXTDM_XTDMS18 0x00040000 // XMT mode during TDM time slot 18 + // 0 1 +#define MCASP_TXTDM_XTDMS17 0x00020000 // XMT mode during TDM time slot 17 + // 0 1 +#define MCASP_TXTDM_XTDMS16 0x00010000 // XMT mode during TDM time slot 16 + // 0 1 +#define MCASP_TXTDM_XTDMS15 0x00008000 // XMT mode during TDM time slot 15 + // 0 1 +#define MCASP_TXTDM_XTDMS14 0x00004000 // XMT mode during TDM time slot 14 + // 0 1 +#define MCASP_TXTDM_XTDMS13 0x00002000 // XMT mode during TDM time slot 13 + // 0 1 +#define MCASP_TXTDM_XTDMS12 0x00001000 // XMT mode during TDM time slot 12 + // 0 1 +#define MCASP_TXTDM_XTDMS11 0x00000800 // XMT mode during TDM time slot 11 + // 0 1 +#define MCASP_TXTDM_XTDMS10 0x00000400 // XMT mode during TDM time slot 10 + // 0 1 +#define MCASP_TXTDM_XTDMS9 0x00000200 // XMT mode during TDM time slot 9 + // 0 1 +#define MCASP_TXTDM_XTDMS8 0x00000100 // XMT mode during TDM time slot 8 + // 0 1 +#define MCASP_TXTDM_XTDMS7 0x00000080 // XMT mode during TDM time slot 7 + // 0 1 +#define MCASP_TXTDM_XTDMS6 0x00000040 // XMT mode during TDM time slot 6 + // 0 1 +#define MCASP_TXTDM_XTDMS5 0x00000020 // XMT mode during TDM time slot 5 + // 0 1 +#define MCASP_TXTDM_XTDMS4 0x00000010 // XMT mode during TDM time slot 4 + // 0 1 +#define MCASP_TXTDM_XTDMS3 0x00000008 // XMT mode during TDM time slot 3 + // 0 1 +#define MCASP_TXTDM_XTDMS2 0x00000004 // XMT mode during TDM time slot 2 + // 0 1 +#define MCASP_TXTDM_XTDMS1 0x00000002 // XMT mode during TDM time slot 1 + // 0 1 +#define MCASP_TXTDM_XTDMS0 0x00000001 // XMT mode during TDM time slot 0 + // 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_EVTCTLX register. +// +//****************************************************************************** +#define MCASP_EVTCTLX_XSTAFRM 0x00000080 // XMT Start of Frame Interrupt 0 1 +#define MCASP_EVTCTLX_XDATA 0x00000020 // XMT Data Interrupt 0 1 +#define MCASP_EVTCTLX_XLAST 0x00000010 // XMT Last Slot Interrupt 0 1 +#define MCASP_EVTCTLX_XDMAERR 0x00000008 // XMT DMA Bus Error 0 1 +#define MCASP_EVTCTLX_XCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 +#define MCASP_EVTCTLX_XSYNCERR 0x00000002 // XMT Unexpected FSR Interrupt 0 1 +#define MCASP_EVTCTLX_XUNDRN 0x00000001 // XMT Underrun Interrupt 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXSTAT register. +// +//****************************************************************************** +#define MCASP_TXSTAT_XERR 0x00000100 // XMT Error 0 1 +#define MCASP_TXSTAT_XDMAERR 0x00000080 // XMT DMA bus error 0 1 +#define MCASP_TXSTAT_XSTAFRM 0x00000040 // Start of Frame-XMT 0 1 +#define MCASP_TXSTAT_XDATA 0x00000020 // Data Ready Flag 0 1 +#define MCASP_TXSTAT_XLAST 0x00000010 // Last Slot Interrupt Flag 0 1 +#define MCASP_TXSTAT_XTDMSLOT 0x00000008 // EvenOdd Slot 0 1 +#define MCASP_TXSTAT_XCKFAIL 0x00000004 // Bad Transmit Flag 0 1 +#define MCASP_TXSTAT_XSYNCERR 0x00000002 // Unexpected XMT Frame sync flag 0 + // 1 +#define MCASP_TXSTAT_XUNDRN 0x00000001 // XMT Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXTDMSLOT register. +// +//****************************************************************************** +#define MCASP_TXTDMSLOT_XSLOTCNT_M \ + 0x000003FF // Current XMT time slot count + // during reset the value of this + // register is 0b0101111111 (0x17f) + // and after reset 0 + +#define MCASP_TXTDMSLOT_XSLOTCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXCLKCHK register. +// +//****************************************************************************** +#define MCASP_TXCLKCHK_XCNT_M 0xFF000000 // XMT clock count value +#define MCASP_TXCLKCHK_XCNT_S 24 +#define MCASP_TXCLKCHK_XMAX_M 0x00FF0000 // XMT clock maximum boundary +#define MCASP_TXCLKCHK_XMAX_S 16 +#define MCASP_TXCLKCHK_XMIN_M 0x0000FF00 // XMT clock minimum boundary +#define MCASP_TXCLKCHK_XMIN_S 8 +#define MCASP_TXCLKCHK_RESV 0x00000080 // Reserved +#define MCASP_TXCLKCHK_XPS_M 0x0000000F // XMT clock check prescaler 0x0 + // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 +#define MCASP_TXCLKCHK_XPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XEVTCTL register. +// +//****************************************************************************** +#define MCASP_XEVTCTL_XDATDMA 0x00000001 // XMT data DMA request 0 Enable + // DMA Transfer 1 Disable DMA + // Transfer +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_CLKADJEN register. +// +//****************************************************************************** +#define MCASP_CLKADJEN_ENABLE 0x00000001 // One-shot clock adjust enable 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA0 register. +// +//****************************************************************************** +#define MCASP_DITCSRA0_DITCSRA0_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA0_DITCSRA0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA1 register. +// +//****************************************************************************** +#define MCASP_DITCSRA1_DITCSRA1_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA1_DITCSRA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA2 register. +// +//****************************************************************************** +#define MCASP_DITCSRA2_DITCSRA2_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status Register + +#define MCASP_DITCSRA2_DITCSRA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA3 register. +// +//****************************************************************************** +#define MCASP_DITCSRA3_DITCSRA3_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status Register + +#define MCASP_DITCSRA3_DITCSRA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA4 register. +// +//****************************************************************************** +#define MCASP_DITCSRA4_DITCSRA4_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA4_DITCSRA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA5 register. +// +//****************************************************************************** +#define MCASP_DITCSRA5_DITCSRA5_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA5_DITCSRA5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB0 register. +// +//****************************************************************************** +#define MCASP_DITCSRB0_DITCSRB0_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB0_DITCSRB0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB1 register. +// +//****************************************************************************** +#define MCASP_DITCSRB1_DITCSRB1_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB1_DITCSRB1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB2 register. +// +//****************************************************************************** +#define MCASP_DITCSRB2_DITCSRB2_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB2_DITCSRB2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB3 register. +// +//****************************************************************************** +#define MCASP_DITCSRB3_DITCSRB3_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB3_DITCSRB3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB4 register. +// +//****************************************************************************** +#define MCASP_DITCSRB4_DITCSRB4_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB4_DITCSRB4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB5 register. +// +//****************************************************************************** +#define MCASP_DITCSRB5_DITCSRB5_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB5_DITCSRB5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA0 register. +// +//****************************************************************************** +#define MCASP_DITUDRA0_DITUDRA0_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA0_DITUDRA0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA1 register. +// +//****************************************************************************** +#define MCASP_DITUDRA1_DITUDRA1_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA1_DITUDRA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA2 register. +// +//****************************************************************************** +#define MCASP_DITUDRA2_DITUDRA2_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA2_DITUDRA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA3 register. +// +//****************************************************************************** +#define MCASP_DITUDRA3_DITUDRA3_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA3_DITUDRA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA4 register. +// +//****************************************************************************** +#define MCASP_DITUDRA4_DITUDRA4_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA4_DITUDRA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA5 register. +// +//****************************************************************************** +#define MCASP_DITUDRA5_DITUDRA5_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA5_DITUDRA5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB0 register. +// +//****************************************************************************** +#define MCASP_DITUDRB0_DITUDRB0_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB0_DITUDRB0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB1 register. +// +//****************************************************************************** +#define MCASP_DITUDRB1_DITUDRB1_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB1_DITUDRB1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB2 register. +// +//****************************************************************************** +#define MCASP_DITUDRB2_DITUDRB2_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB2_DITUDRB2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB3 register. +// +//****************************************************************************** +#define MCASP_DITUDRB3_DITUDRB3_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB3_DITUDRB3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB4 register. +// +//****************************************************************************** +#define MCASP_DITUDRB4_DITUDRB4_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB4_DITUDRB4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB5 register. +// +//****************************************************************************** +#define MCASP_DITUDRB5_DITUDRB5_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB5_DITUDRB5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL0 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL0_RRDY 0x00000020 +#define MCASP_XRSRCTL0_XRDY 0x00000010 +#define MCASP_XRSRCTL0_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL0_DISMOD_S 2 +#define MCASP_XRSRCTL0_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL0_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL1 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL1_RRDY 0x00000020 +#define MCASP_XRSRCTL1_XRDY 0x00000010 +#define MCASP_XRSRCTL1_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL1_DISMOD_S 2 +#define MCASP_XRSRCTL1_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL1_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL2 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL2_RRDY 0x00000020 +#define MCASP_XRSRCTL2_XRDY 0x00000010 +#define MCASP_XRSRCTL2_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL2_DISMOD_S 2 +#define MCASP_XRSRCTL2_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL2_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL3 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL3_RRDY 0x00000020 +#define MCASP_XRSRCTL3_XRDY 0x00000010 +#define MCASP_XRSRCTL3_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL3_DISMOD_S 2 +#define MCASP_XRSRCTL3_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL3_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL4 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL4_RRDY 0x00000020 +#define MCASP_XRSRCTL4_XRDY 0x00000010 +#define MCASP_XRSRCTL4_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL4_DISMOD_S 2 +#define MCASP_XRSRCTL4_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL4_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL5 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL5_RRDY 0x00000020 +#define MCASP_XRSRCTL5_XRDY 0x00000010 +#define MCASP_XRSRCTL5_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL5_DISMOD_S 2 +#define MCASP_XRSRCTL5_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL5_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL6 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL6_RRDY 0x00000020 +#define MCASP_XRSRCTL6_XRDY 0x00000010 +#define MCASP_XRSRCTL6_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL6_DISMOD_S 2 +#define MCASP_XRSRCTL6_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL6_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL7 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL7_RRDY 0x00000020 +#define MCASP_XRSRCTL7_XRDY 0x00000010 +#define MCASP_XRSRCTL7_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL7_DISMOD_S 2 +#define MCASP_XRSRCTL7_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL7_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL8 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL8_RRDY 0x00000020 +#define MCASP_XRSRCTL8_XRDY 0x00000010 +#define MCASP_XRSRCTL8_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL8_DISMOD_S 2 +#define MCASP_XRSRCTL8_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL8_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL9 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL9_RRDY 0x00000020 +#define MCASP_XRSRCTL9_XRDY 0x00000010 +#define MCASP_XRSRCTL9_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL9_DISMOD_S 2 +#define MCASP_XRSRCTL9_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL9_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL10 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL10_RRDY 0x00000020 +#define MCASP_XRSRCTL10_XRDY 0x00000010 +#define MCASP_XRSRCTL10_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL10_DISMOD_S 2 +#define MCASP_XRSRCTL10_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL10_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL11 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL11_RRDY 0x00000020 +#define MCASP_XRSRCTL11_XRDY 0x00000010 +#define MCASP_XRSRCTL11_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL11_DISMOD_S 2 +#define MCASP_XRSRCTL11_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL11_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL12 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL12_RRDY 0x00000020 +#define MCASP_XRSRCTL12_XRDY 0x00000010 +#define MCASP_XRSRCTL12_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL12_DISMOD_S 2 +#define MCASP_XRSRCTL12_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL12_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL13 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL13_RRDY 0x00000020 +#define MCASP_XRSRCTL13_XRDY 0x00000010 +#define MCASP_XRSRCTL13_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL13_DISMOD_S 2 +#define MCASP_XRSRCTL13_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL13_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL14 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL14_RRDY 0x00000020 +#define MCASP_XRSRCTL14_XRDY 0x00000010 +#define MCASP_XRSRCTL14_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL14_DISMOD_S 2 +#define MCASP_XRSRCTL14_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL14_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL15 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL15_RRDY 0x00000020 +#define MCASP_XRSRCTL15_XRDY 0x00000010 +#define MCASP_XRSRCTL15_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL15_DISMOD_S 2 +#define MCASP_XRSRCTL15_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL15_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF0 register. +// +//****************************************************************************** +#define MCASP_TXBUF0_XBUF0_M 0xFFFFFFFF // Transmit Buffer 0 +#define MCASP_TXBUF0_XBUF0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF1 register. +// +//****************************************************************************** +#define MCASP_TXBUF1_XBUF1_M 0xFFFFFFFF // Transmit Buffer 1 +#define MCASP_TXBUF1_XBUF1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF2 register. +// +//****************************************************************************** +#define MCASP_TXBUF2_XBUF2_M 0xFFFFFFFF // Transmit Buffer 2 +#define MCASP_TXBUF2_XBUF2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF3 register. +// +//****************************************************************************** +#define MCASP_TXBUF3_XBUF3_M 0xFFFFFFFF // Transmit Buffer 3 +#define MCASP_TXBUF3_XBUF3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF4 register. +// +//****************************************************************************** +#define MCASP_TXBUF4_XBUF4_M 0xFFFFFFFF // Transmit Buffer 4 +#define MCASP_TXBUF4_XBUF4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF5 register. +// +//****************************************************************************** +#define MCASP_TXBUF5_XBUF5_M 0xFFFFFFFF // Transmit Buffer 5 +#define MCASP_TXBUF5_XBUF5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF6 register. +// +//****************************************************************************** +#define MCASP_TXBUF6_XBUF6_M 0xFFFFFFFF // Transmit Buffer 6 +#define MCASP_TXBUF6_XBUF6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF7 register. +// +//****************************************************************************** +#define MCASP_TXBUF7_XBUF7_M 0xFFFFFFFF // Transmit Buffer 7 +#define MCASP_TXBUF7_XBUF7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF8 register. +// +//****************************************************************************** +#define MCASP_TXBUF8_XBUF8_M 0xFFFFFFFF // Transmit Buffer 8 +#define MCASP_TXBUF8_XBUF8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF9 register. +// +//****************************************************************************** +#define MCASP_TXBUF9_XBUF9_M 0xFFFFFFFF // Transmit Buffer 9 +#define MCASP_TXBUF9_XBUF9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF10 register. +// +//****************************************************************************** +#define MCASP_TXBUF10_XBUF10_M 0xFFFFFFFF // Transmit Buffer 10 +#define MCASP_TXBUF10_XBUF10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF11 register. +// +//****************************************************************************** +#define MCASP_TXBUF11_XBUF11_M 0xFFFFFFFF // Transmit Buffer 11 +#define MCASP_TXBUF11_XBUF11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF12 register. +// +//****************************************************************************** +#define MCASP_TXBUF12_XBUF12_M 0xFFFFFFFF // Transmit Buffer 12 +#define MCASP_TXBUF12_XBUF12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF13 register. +// +//****************************************************************************** +#define MCASP_TXBUF13_XBUF13_M 0xFFFFFFFF // Transmit Buffer 13 +#define MCASP_TXBUF13_XBUF13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF14 register. +// +//****************************************************************************** +#define MCASP_TXBUF14_XBUF14_M 0xFFFFFFFF // Transmit Buffer 14 +#define MCASP_TXBUF14_XBUF14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF15 register. +// +//****************************************************************************** +#define MCASP_TXBUF15_XBUF15_M 0xFFFFFFFF // Transmit Buffer 15 +#define MCASP_TXBUF15_XBUF15_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF0 register. +// +//****************************************************************************** +#define MCASP_RXBUF0_RBUF0_M 0xFFFFFFFF // Receive Buffer 0 +#define MCASP_RXBUF0_RBUF0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF1 register. +// +//****************************************************************************** +#define MCASP_RXBUF1_RBUF1_M 0xFFFFFFFF // Receive Buffer 1 +#define MCASP_RXBUF1_RBUF1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF2 register. +// +//****************************************************************************** +#define MCASP_RXBUF2_RBUF2_M 0xFFFFFFFF // Receive Buffer 2 +#define MCASP_RXBUF2_RBUF2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF3 register. +// +//****************************************************************************** +#define MCASP_RXBUF3_RBUF3_M 0xFFFFFFFF // Receive Buffer 3 +#define MCASP_RXBUF3_RBUF3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF4 register. +// +//****************************************************************************** +#define MCASP_RXBUF4_RBUF4_M 0xFFFFFFFF // Receive Buffer 4 +#define MCASP_RXBUF4_RBUF4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF5 register. +// +//****************************************************************************** +#define MCASP_RXBUF5_RBUF5_M 0xFFFFFFFF // Receive Buffer 5 +#define MCASP_RXBUF5_RBUF5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF6 register. +// +//****************************************************************************** +#define MCASP_RXBUF6_RBUF6_M 0xFFFFFFFF // Receive Buffer 6 +#define MCASP_RXBUF6_RBUF6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF7 register. +// +//****************************************************************************** +#define MCASP_RXBUF7_RBUF7_M 0xFFFFFFFF // Receive Buffer 7 +#define MCASP_RXBUF7_RBUF7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF8 register. +// +//****************************************************************************** +#define MCASP_RXBUF8_RBUF8_M 0xFFFFFFFF // Receive Buffer 8 +#define MCASP_RXBUF8_RBUF8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF9 register. +// +//****************************************************************************** +#define MCASP_RXBUF9_RBUF9_M 0xFFFFFFFF // Receive Buffer 9 +#define MCASP_RXBUF9_RBUF9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF10 register. +// +//****************************************************************************** +#define MCASP_RXBUF10_RBUF10_M 0xFFFFFFFF // Receive Buffer 10 +#define MCASP_RXBUF10_RBUF10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF11 register. +// +//****************************************************************************** +#define MCASP_RXBUF11_RBUF11_M 0xFFFFFFFF // Receive Buffer 11 +#define MCASP_RXBUF11_RBUF11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF12 register. +// +//****************************************************************************** +#define MCASP_RXBUF12_RBUF12_M 0xFFFFFFFF // Receive Buffer 12 +#define MCASP_RXBUF12_RBUF12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF13 register. +// +//****************************************************************************** +#define MCASP_RXBUF13_RBUF13_M 0xFFFFFFFF // Receive Buffer 13 +#define MCASP_RXBUF13_RBUF13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF14 register. +// +//****************************************************************************** +#define MCASP_RXBUF14_RBUF14_M 0xFFFFFFFF // Receive Buffer 14 +#define MCASP_RXBUF14_RBUF14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF15 register. +// +//****************************************************************************** +#define MCASP_RXBUF15_RBUF15_M 0xFFFFFFFF // Receive Buffer 15 +#define MCASP_RXBUF15_RBUF15_S 0 + + + +#endif // __HW_MCASP_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mcspi.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mcspi.h new file mode 100644 index 000000000..90bd2b203 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mcspi.h @@ -0,0 +1,1747 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_MCSPI_H__ +#define __HW_MCSPI_H__ + +//***************************************************************************** +// +// The following are defines for the MCSPI register offsets. +// +//***************************************************************************** +#define MCSPI_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) + // Used by software to track + // features bugs and compatibility +#define MCSPI_O_HL_HWINFO 0x00000004 // Information about the IP + // module's hardware configuration + // i.e. typically the module's HDL + // generics (if any). Actual field + // format and encoding is up to the + // module's designer to decide. +#define MCSPI_O_HL_SYSCONFIG 0x00000010 // 0x4402 1010 0x4402 2010 Clock + // management configuration +#define MCSPI_O_REVISION 0x00000100 // 0x4402 1100 0x4402 2100 This + // register contains the hard coded + // RTL revision number. +#define MCSPI_O_SYSCONFIG 0x00000110 // 0x4402 1110 0x4402 2110 This + // register allows controlling + // various parameters of the OCP + // interface. +#define MCSPI_O_SYSSTATUS 0x00000114 // 0x4402 1114 0x4402 2114 This + // register provides status + // information about the module + // excluding the interrupt status + // information +#define MCSPI_O_IRQSTATUS 0x00000118 // 0x4402 1118 0x4402 2118 The + // interrupt status regroups all the + // status of the module internal + // events that can generate an + // interrupt +#define MCSPI_O_IRQENABLE 0x0000011C // 0x4402 111C 0x4402 211C This + // register allows to enable/disable + // the module internal sources of + // interrupt on an event-by-event + // basis. +#define MCSPI_O_WAKEUPENABLE 0x00000120 // 0x4402 1120 0x4402 2120 The + // wakeup enable register allows to + // enable/disable the module + // internal sources of wakeup on + // event-by-event basis. +#define MCSPI_O_SYST 0x00000124 // 0x4402 1124 0x4402 2124 This + // register is used to check the + // correctness of the system + // interconnect either internally to + // peripheral bus or externally to + // device IO pads when the module is + // configured in system test + // (SYSTEST) mode. +#define MCSPI_O_MODULCTRL 0x00000128 // 0x4402 1128 0x4402 2128 This + // register is dedicated to the + // configuration of the serial port + // interface. +#define MCSPI_O_CH0CONF 0x0000012C // 0x4402 112C 0x4402 212C This + // register is dedicated to the + // configuration of the channel 0 +#define MCSPI_O_CH0STAT 0x00000130 // 0x4402 1130 0x4402 2130 This + // register provides status + // information about transmitter and + // receiver registers of channel 0 +#define MCSPI_O_CH0CTRL 0x00000134 // 0x4402 1134 0x4402 2134 This + // register is dedicated to enable + // the channel 0 +#define MCSPI_O_TX0 0x00000138 // 0x4402 1138 0x4402 2138 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX0 0x0000013C // 0x4402 113C 0x4402 213C This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH1CONF 0x00000140 // 0x4402 1140 0x4402 2140 This + // register is dedicated to the + // configuration of the channel. +#define MCSPI_O_CH1STAT 0x00000144 // 0x4402 1144 0x4402 2144 This + // register provides status + // information about transmitter and + // receiver registers of channel 1 +#define MCSPI_O_CH1CTRL 0x00000148 // 0x4402 1148 0x4402 2148 This + // register is dedicated to enable + // the channel 1 +#define MCSPI_O_TX1 0x0000014C // 0x4402 114C 0x4402 214C This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX1 0x00000150 // 0x4402 1150 0x4402 2150 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH2CONF 0x00000154 // 0x4402 1154 0x4402 2154 This + // register is dedicated to the + // configuration of the channel 2 +#define MCSPI_O_CH2STAT 0x00000158 // 0x4402 1158 0x4402 2158 This + // register provides status + // information about transmitter and + // receiver registers of channel 2 +#define MCSPI_O_CH2CTRL 0x0000015C // 0x4402 115C 0x4402 215C This + // register is dedicated to enable + // the channel 2 +#define MCSPI_O_TX2 0x00000160 // 0x4402 1160 0x4402 2160 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX2 0x00000164 // 0x4402 1164 0x4402 2164 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH3CONF 0x00000168 // 0x4402 1168 0x4402 2168 This + // register is dedicated to the + // configuration of the channel 3 +#define MCSPI_O_CH3STAT 0x0000016C // 0x4402 116C 0x4402 216C This + // register provides status + // information about transmitter and + // receiver registers of channel 3 +#define MCSPI_O_CH3CTRL 0x00000170 // 0x4402 1170 0x4402 2170 This + // register is dedicated to enable + // the channel 3 +#define MCSPI_O_TX3 0x00000174 // 0x4402 1174 0x4402 2174 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX3 0x00000178 // 0x4402 1178 0x4402 2178 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_XFERLEVEL 0x0000017C // 0x4402 117C 0x4402 217C This + // register provides transfer levels + // needed while using FIFO buffer + // during transfer. +#define MCSPI_O_DAFTX 0x00000180 // 0x4402 1180 0x4402 2180 This + // register contains the SPI words + // to transmit on the serial link + // when FIFO used and DMA address is + // aligned on 256 bit.This register + // is an image of one of MCSPI_TX(i) + // register corresponding to the + // channel which have its FIFO + // enabled. +#define MCSPI_O_DAFRX 0x000001A0 // 0x4402 11A0 0x4402 21A0 This + // register contains the SPI words + // to received on the serial link + // when FIFO used and DMA address is + // aligned on 256 bit.This register + // is an image of one of MCSPI_RX(i) + // register corresponding to the + // channel which have its FIFO + // enabled. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_HL_REV register. +// +//****************************************************************************** +#define MCSPI_HL_REV_SCHEME_M 0xC0000000 +#define MCSPI_HL_REV_SCHEME_S 30 +#define MCSPI_HL_REV_RSVD_M 0x30000000 // Reserved These bits are + // initialized to zero and writes to + // them are ignored. +#define MCSPI_HL_REV_RSVD_S 28 +#define MCSPI_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define MCSPI_HL_REV_FUNC_S 16 +#define MCSPI_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define MCSPI_HL_REV_R_RTL_S 11 +#define MCSPI_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. +#define MCSPI_HL_REV_X_MAJOR_S 8 +#define MCSPI_HL_REV_CUSTOM_M 0x000000C0 +#define MCSPI_HL_REV_CUSTOM_S 6 +#define MCSPI_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. +#define MCSPI_HL_REV_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_HL_HWINFO register. +// +//****************************************************************************** +#define MCSPI_HL_HWINFO_RETMODE 0x00000040 +#define MCSPI_HL_HWINFO_FFNBYTE_M \ + 0x0000003E + +#define MCSPI_HL_HWINFO_FFNBYTE_S 1 +#define MCSPI_HL_HWINFO_USEFIFO 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCSPI_O_HL_SYSCONFIG register. +// +//****************************************************************************** +#define MCSPI_HL_SYSCONFIG_IDLEMODE_M \ + 0x0000000C // Configuration of the local + // target state management mode. By + // definition target can handle + // read/write transaction as long as + // it is out of IDLE state. 0x0 + // Force-idle mode: local target's + // idle state follows (acknowledges) + // the system's idle requests + // unconditionally i.e. regardless + // of the IP module's internal + // requirements.Backup mode for + // debug only. 0x1 No-idle mode: + // local target never enters idle + // state.Backup mode for debug only. + // 0x2 Smart-idle mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module shall not + // generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 "Smart-idle + // wakeup-capable mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MCSPI_HL_SYSCONFIG_IDLEMODE_S 2 +#define MCSPI_HL_SYSCONFIG_FREEEMU \ + 0x00000002 // Sensitivity to emulation (debug) + // suspend input signal. 0 IP module + // is sensitive to emulation suspend + // 1 IP module is not sensitive to + // emulation suspend + +#define MCSPI_HL_SYSCONFIG_SOFTRESET \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_REVISION register. +// +//****************************************************************************** +#define MCSPI_REVISION_REV_M 0x000000FF // IP revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 +#define MCSPI_REVISION_REV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYSCONFIG register. +// +//****************************************************************************** +#define MCSPI_SYSCONFIG_CLOCKACTIVITY_M \ + 0x00000300 // Clocks activity during wake up + // mode period 0x0 OCP and + // Functional clocks may be switched + // off. 0x1 OCP clock is maintained. + // Functional clock may be + // switched-off. 0x2 Functional + // clock is maintained. OCP clock + // may be switched-off. 0x3 OCP and + // Functional clocks are maintained. + +#define MCSPI_SYSCONFIG_CLOCKACTIVITY_S 8 +#define MCSPI_SYSCONFIG_SIDLEMODE_M \ + 0x00000018 // Power management 0x0 If an idle + // request is detected the McSPI + // acknowledges it unconditionally + // and goes in Inactive mode. + // Interrupt DMA requests and wake + // up lines are unconditionally + // de-asserted and the module wakeup + // capability is deactivated even if + // the bit + // MCSPI_SYSCONFIG[EnaWakeUp] is + // set. 0x1 If an idle request is + // detected the request is ignored + // and the module does not switch to + // wake up mode and keeps on + // behaving normally. 0x2 If an idle + // request is detected the module + // will switch to idle mode based on + // its internal activity. The wake + // up capability cannot be used. 0x3 + // If an idle request is detected + // the module will switch to idle + // mode based on its internal + // activity and the wake up + // capability can be used if the bit + // MCSPI_SYSCONFIG[EnaWakeUp] is + // set. + +#define MCSPI_SYSCONFIG_SIDLEMODE_S 3 +#define MCSPI_SYSCONFIG_ENAWAKEUP \ + 0x00000004 // WakeUp feature control 0 WakeUp + // capability is disabled 1 WakeUp + // capability is enabled + +#define MCSPI_SYSCONFIG_SOFTRESET \ + 0x00000002 // Software reset. During reads it + // always returns 0. 0 (write) + // Normal mode 1 (write) Set this + // bit to 1 to trigger a module + // reset.The bit is automatically + // reset by the hardware. + +#define MCSPI_SYSCONFIG_AUTOIDLE \ + 0x00000001 // Internal OCP Clock gating + // strategy 0 OCP clock is + // free-running 1 Automatic OCP + // clock gating strategy is applied + // based on the OCP interface + // activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYSSTATUS register. +// +//****************************************************************************** +#define MCSPI_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_IRQSTATUS register. +// +//****************************************************************************** +#define MCSPI_IRQSTATUS_EOW 0x00020000 +#define MCSPI_IRQSTATUS_WKS 0x00010000 +#define MCSPI_IRQSTATUS_RX3_FULL \ + 0x00004000 + +#define MCSPI_IRQSTATUS_TX3_UNDERFLOW \ + 0x00002000 + +#define MCSPI_IRQSTATUS_TX3_EMPTY \ + 0x00001000 + +#define MCSPI_IRQSTATUS_RX2_FULL \ + 0x00000400 + +#define MCSPI_IRQSTATUS_TX2_UNDERFLOW \ + 0x00000200 + +#define MCSPI_IRQSTATUS_TX2_EMPTY \ + 0x00000100 + +#define MCSPI_IRQSTATUS_RX1_FULL \ + 0x00000040 + +#define MCSPI_IRQSTATUS_TX1_UNDERFLOW \ + 0x00000020 + +#define MCSPI_IRQSTATUS_TX1_EMPTY \ + 0x00000010 + +#define MCSPI_IRQSTATUS_RX0_OVERFLOW \ + 0x00000008 + +#define MCSPI_IRQSTATUS_RX0_FULL \ + 0x00000004 + +#define MCSPI_IRQSTATUS_TX0_UNDERFLOW \ + 0x00000002 + +#define MCSPI_IRQSTATUS_TX0_EMPTY \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_IRQENABLE register. +// +//****************************************************************************** +#define MCSPI_IRQENABLE_EOW_ENABLE \ + 0x00020000 // End of Word count Interrupt + // Enable. 0 Interrupt disabled 1 + // Interrupt enabled + +#define MCSPI_IRQENABLE_WKE 0x00010000 // Wake Up event interrupt Enable + // in slave mode when an active + // control signal is detected on the + // SPIEN line programmed in the + // field MCSPI_CH0CONF[SPIENSLV] 0 + // Interrupt disabled 1 Interrupt + // enabled +#define MCSPI_IRQENABLE_RX3_FULL_ENABLE \ + 0x00004000 // Receiver register Full Interrupt + // Enable. Ch 3 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX3_UNDERFLOW_ENABLE \ + 0x00002000 // Transmitter register Underflow + // Interrupt Enable. Ch 3 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX3_EMPTY_ENABLE \ + 0x00001000 // Transmitter register Empty + // Interrupt Enable. Ch3 0 Interrupt + // disabled 1 Interrupt enabled + +#define MCSPI_IRQENABLE_RX2_FULL_ENABLE \ + 0x00000400 // Receiver register Full Interrupt + // Enable. Ch 2 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX2_UNDERFLOW_ENABLE \ + 0x00000200 // Transmitter register Underflow + // Interrupt Enable. Ch 2 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX2_EMPTY_ENABLE \ + 0x00000100 // Transmitter register Empty + // Interrupt Enable. Ch 2 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX1_FULL_ENABLE \ + 0x00000040 // Receiver register Full Interrupt + // Enable. Ch 1 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX1_UNDERFLOW_ENABLE \ + 0x00000020 // Transmitter register Underflow + // Interrupt Enable. Ch 1 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX1_EMPTY_ENABLE \ + 0x00000010 // Transmitter register Empty + // Interrupt Enable. Ch 1 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX0_OVERFLOW_ENABLE \ + 0x00000008 // Receiver register Overflow + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX0_FULL_ENABLE \ + 0x00000004 // Receiver register Full Interrupt + // Enable. Ch 0 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE \ + 0x00000002 // Transmitter register Underflow + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX0_EMPTY_ENABLE \ + 0x00000001 // Transmitter register Empty + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCSPI_O_WAKEUPENABLE register. +// +//****************************************************************************** +#define MCSPI_WAKEUPENABLE_WKEN 0x00000001 // WakeUp functionality in slave + // mode when an active control + // signal is detected on the SPIEN + // line programmed in the field + // MCSPI_CH0CONF[SPIENSLV] 0 The + // event is not allowed to wakeup + // the system even if the global + // control bit + // MCSPI_SYSCONF[EnaWakeUp] is set. + // 1 The event is allowed to wakeup + // the system if the global control + // bit MCSPI_SYSCONF[EnaWakeUp] is + // set. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYST register. +// +//****************************************************************************** +#define MCSPI_SYST_SSB 0x00000800 // Set status bit 0 No action. + // Writing 0 does not clear already + // set status bits; This bit must be + // cleared prior attempting to clear + // a status bit of the + // register. 1 + // Force to 1 all status bits of + // MCSPI_IRQSTATUS register. Writing + // 1 into this bit sets to 1 all + // status bits contained in the + // register. +#define MCSPI_SYST_SPIENDIR 0x00000400 // Set the direction of the + // SPIEN[3:0] lines and SPICLK line + // 0 output (as in master mode) 1 + // input (as in slave mode) +#define MCSPI_SYST_SPIDATDIR1 0x00000200 // Set the direction of the + // SPIDAT[1] 0 output 1 input +#define MCSPI_SYST_SPIDATDIR0 0x00000100 // Set the direction of the + // SPIDAT[0] 0 output 1 input +#define MCSPI_SYST_WAKD 0x00000080 // SWAKEUP output (signal data + // value of internal signal to + // system). The signal is driven + // high or low according to the + // value written into this register + // bit. 0 The pin is driven low. 1 + // The pin is driven high. +#define MCSPI_SYST_SPICLK 0x00000040 // SPICLK line (signal data value) + // If MCSPI_SYST[SPIENDIR] = 1 + // (input mode direction) this bit + // returns the value on the CLKSPI + // line (high or low) and a write + // into this bit has no effect. If + // MCSPI_SYST[SPIENDIR] = 0 (output + // mode direction) the CLKSPI line + // is driven high or low according + // to the value written into this + // register. +#define MCSPI_SYST_SPIDAT_1 0x00000020 // SPIDAT[1] line (signal data + // value) If MCSPI_SYST[SPIDATDIR1] + // = 0 (output mode direction) the + // SPIDAT[1] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIDATDIR1] = 1 (input + // mode direction) this bit returns + // the value on the SPIDAT[1] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIDAT_0 0x00000010 // SPIDAT[0] line (signal data + // value) If MCSPI_SYST[SPIDATDIR0] + // = 0 (output mode direction) the + // SPIDAT[0] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIDATDIR0] = 1 (input + // mode direction) this bit returns + // the value on the SPIDAT[0] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_3 0x00000008 // SPIEN[3] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[3] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[3] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_2 0x00000004 // SPIEN[2] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[2] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[2] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_1 0x00000002 // SPIEN[1] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[1] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[1] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_0 0x00000001 // SPIEN[0] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[0] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[0] line + // (high or low) and a write into + // this bit has no effect. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_MODULCTRL register. +// +//****************************************************************************** +#define MCSPI_MODULCTRL_FDAA 0x00000100 // FIFO DMA Address 256-bit aligned + // This register is used when a FIFO + // is managed by the module and DMA + // connected to the controller + // provides only 256 bit aligned + // address. If this bit is set the + // enabled channel which uses the + // FIFO has its datas managed + // through MCSPI_DAFTX and + // MCSPI_DAFRX registers instead of + // MCSPI_TX(i) and MCSPI_RX(i) + // registers. 0 FIFO data managed by + // MCSPI_TX(i) and MCSPI_RX(i) + // registers. 1 FIFO data managed by + // MCSPI_DAFTX and MCSPI_DAFRX + // registers. +#define MCSPI_MODULCTRL_MOA 0x00000080 // Multiple word ocp access: This + // register can only be used when a + // channel is enabled using a FIFO. + // It allows the system to perform + // multiple SPI word access for a + // single 32-bit OCP word access. + // This is possible for WL < 16. 0 + // Multiple word access disabled 1 + // Multiple word access enabled with + // FIFO +#define MCSPI_MODULCTRL_INITDLY_M \ + 0x00000070 // Initial spi delay for first + // transfer: This register is an + // option only available in SINGLE + // master mode The controller waits + // for a delay to transmit the first + // spi word after channel enabled + // and corresponding TX register + // filled. This Delay is based on + // SPI output frequency clock No + // clock output provided to the + // boundary and chip select is not + // active in 4 pin mode within this + // period. 0x0 No delay for first + // spi transfer. 0x1 The controller + // wait 4 spi bus clock 0x2 The + // controller wait 8 spi bus clock + // 0x3 The controller wait 16 spi + // bus clock 0x4 The controller wait + // 32 spi bus clock + +#define MCSPI_MODULCTRL_INITDLY_S 4 +#define MCSPI_MODULCTRL_SYSTEM_TEST \ + 0x00000008 // Enables the system test mode 0 + // Functional mode 1 System test + // mode (SYSTEST) + +#define MCSPI_MODULCTRL_MS 0x00000004 // Master/ Slave 0 Master - The + // module generates the SPICLK and + // SPIEN[3:0] 1 Slave - The module + // receives the SPICLK and + // SPIEN[3:0] +#define MCSPI_MODULCTRL_PIN34 0x00000002 // Pin mode selection: This + // register is used to configure the + // SPI pin mode in master or slave + // mode. If asserted the controller + // only use SIMOSOMI and SPICLK + // clock pin for spi transfers. 0 + // SPIEN is used as a chip select. 1 + // SPIEN is not used.In this mode + // all related option to chip select + // have no meaning. +#define MCSPI_MODULCTRL_SINGLE 0x00000001 // Single channel / Multi Channel + // (master mode only) 0 More than + // one channel will be used in + // master mode. 1 Only one channel + // will be used in master mode. This + // bit must be set in Force SPIEN + // mode. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0CONF register. +// +//****************************************************************************** +#define MCSPI_CH0CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH0CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH0CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH0CONF_TCS0_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH0CONF_TCS0_S 25 +#define MCSPI_CH0CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH0CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH0CONF[SBPOL] +#define MCSPI_CH0CONF_SPIENSLV_M \ + 0x00600000 // Channel 0 only and slave mode + // only: SPI slave select signal + // detection. Reserved bits for + // other cases. 0x0 Detection + // enabled only on SPIEN[0] 0x1 + // Detection enabled only on + // SPIEN[1] 0x2 Detection enabled + // only on SPIEN[2] 0x3 Detection + // enabled only on SPIEN[3] + +#define MCSPI_CH0CONF_SPIENSLV_S 21 +#define MCSPI_CH0CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH0CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH0CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH0CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH0CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH0CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH0CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH0CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH0CONF_TRM_S 12 +#define MCSPI_CH0CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH0CONF_WL_S 7 +#define MCSPI_CH0CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH0CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH0CONF_CLKD_S 2 +#define MCSPI_CH0CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH0CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0STAT register. +// +//****************************************************************************** +#define MCSPI_CH0STAT_RXFFF 0x00000040 +#define MCSPI_CH0STAT_RXFFE 0x00000020 +#define MCSPI_CH0STAT_TXFFF 0x00000010 +#define MCSPI_CH0STAT_TXFFE 0x00000008 +#define MCSPI_CH0STAT_EOT 0x00000004 +#define MCSPI_CH0STAT_TXS 0x00000002 +#define MCSPI_CH0STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0CTRL register. +// +//****************************************************************************** +#define MCSPI_CH0CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH0CTRL_EXTCLK_S 8 +#define MCSPI_CH0CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX0 register. +// +//****************************************************************************** +#define MCSPI_TX0_TDATA_M 0xFFFFFFFF // Channel 0 Data to transmit +#define MCSPI_TX0_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX0 register. +// +//****************************************************************************** +#define MCSPI_RX0_RDATA_M 0xFFFFFFFF // Channel 0 Received Data +#define MCSPI_RX0_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1CONF register. +// +//****************************************************************************** +#define MCSPI_CH1CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH1CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH1CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH1CONF_TCS1_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH1CONF_TCS1_S 25 +#define MCSPI_CH1CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH1CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH1CONF[SBPOL] +#define MCSPI_CH1CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH1CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH1CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH1CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH1CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH1CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH1CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH1CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH1CONF_TRM_S 12 +#define MCSPI_CH1CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH1CONF_WL_S 7 +#define MCSPI_CH1CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH1CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH1CONF_CLKD_S 2 +#define MCSPI_CH1CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH1CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1STAT register. +// +//****************************************************************************** +#define MCSPI_CH1STAT_RXFFF 0x00000040 +#define MCSPI_CH1STAT_RXFFE 0x00000020 +#define MCSPI_CH1STAT_TXFFF 0x00000010 +#define MCSPI_CH1STAT_TXFFE 0x00000008 +#define MCSPI_CH1STAT_EOT 0x00000004 +#define MCSPI_CH1STAT_TXS 0x00000002 +#define MCSPI_CH1STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1CTRL register. +// +//****************************************************************************** +#define MCSPI_CH1CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH1CTRL_EXTCLK_S 8 +#define MCSPI_CH1CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX1 register. +// +//****************************************************************************** +#define MCSPI_TX1_TDATA_M 0xFFFFFFFF // Channel 1 Data to transmit +#define MCSPI_TX1_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX1 register. +// +//****************************************************************************** +#define MCSPI_RX1_RDATA_M 0xFFFFFFFF // Channel 1 Received Data +#define MCSPI_RX1_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2CONF register. +// +//****************************************************************************** +#define MCSPI_CH2CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH2CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH2CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH2CONF_TCS2_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH2CONF_TCS2_S 25 +#define MCSPI_CH2CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH2CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH2CONF[SBPOL] +#define MCSPI_CH2CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH2CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH2CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH2CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH2CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH2CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH2CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH2CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH2CONF_TRM_S 12 +#define MCSPI_CH2CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH2CONF_WL_S 7 +#define MCSPI_CH2CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH2CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH2CONF_CLKD_S 2 +#define MCSPI_CH2CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH2CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2STAT register. +// +//****************************************************************************** +#define MCSPI_CH2STAT_RXFFF 0x00000040 +#define MCSPI_CH2STAT_RXFFE 0x00000020 +#define MCSPI_CH2STAT_TXFFF 0x00000010 +#define MCSPI_CH2STAT_TXFFE 0x00000008 +#define MCSPI_CH2STAT_EOT 0x00000004 +#define MCSPI_CH2STAT_TXS 0x00000002 +#define MCSPI_CH2STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2CTRL register. +// +//****************************************************************************** +#define MCSPI_CH2CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH2CTRL_EXTCLK_S 8 +#define MCSPI_CH2CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX2 register. +// +//****************************************************************************** +#define MCSPI_TX2_TDATA_M 0xFFFFFFFF // Channel 2 Data to transmit +#define MCSPI_TX2_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX2 register. +// +//****************************************************************************** +#define MCSPI_RX2_RDATA_M 0xFFFFFFFF // Channel 2 Received Data +#define MCSPI_RX2_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3CONF register. +// +//****************************************************************************** +#define MCSPI_CH3CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH3CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH3CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH3CONF_TCS3_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH3CONF_TCS3_S 25 +#define MCSPI_CH3CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH3CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH3CONF[SBPOL] +#define MCSPI_CH3CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH3CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH3CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH3CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH3CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH3CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH3CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH3CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH3CONF_TRM_S 12 +#define MCSPI_CH3CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH3CONF_WL_S 7 +#define MCSPI_CH3CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH3CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH3CONF_CLKD_S 2 +#define MCSPI_CH3CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH3CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3STAT register. +// +//****************************************************************************** +#define MCSPI_CH3STAT_RXFFF 0x00000040 +#define MCSPI_CH3STAT_RXFFE 0x00000020 +#define MCSPI_CH3STAT_TXFFF 0x00000010 +#define MCSPI_CH3STAT_TXFFE 0x00000008 +#define MCSPI_CH3STAT_EOT 0x00000004 +#define MCSPI_CH3STAT_TXS 0x00000002 +#define MCSPI_CH3STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3CTRL register. +// +//****************************************************************************** +#define MCSPI_CH3CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH3CTRL_EXTCLK_S 8 +#define MCSPI_CH3CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX3 register. +// +//****************************************************************************** +#define MCSPI_TX3_TDATA_M 0xFFFFFFFF // Channel 3 Data to transmit +#define MCSPI_TX3_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX3 register. +// +//****************************************************************************** +#define MCSPI_RX3_RDATA_M 0xFFFFFFFF // Channel 3 Received Data +#define MCSPI_RX3_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_XFERLEVEL register. +// +//****************************************************************************** +#define MCSPI_XFERLEVEL_WCNT_M 0xFFFF0000 // Spi word counterThis register + // holds the programmable value of + // number of SPI word to be + // transferred on channel which is + // using the FIFO buffer.When + // transfer had started a read back + // in this register returns the + // current SPI word transfer index. + // 0x0000 Counter not used 0x0001 + // one word 0xFFFE 65534 spi word + // 0xFFFF 65535 spi word +#define MCSPI_XFERLEVEL_WCNT_S 16 +#define MCSPI_XFERLEVEL_AFL_M 0x0000FF00 // Buffer Almost Full This register + // holds the programmable almost + // full level value used to + // determine almost full buffer + // condition. If the user wants an + // interrupt or a DMA read request + // to be issued during a receive + // operation when the data buffer + // holds at least n bytes then the + // buffer MCSPI_MODULCTRL[AFL] must + // be set with n-1.The size of this + // register is defined by the + // generic parameter FFNBYTE. 0x00 + // one byte 0x01 2 bytes 0xFE + // 255bytes 0xFF 256bytes +#define MCSPI_XFERLEVEL_AFL_S 8 +#define MCSPI_XFERLEVEL_AEL_M 0x000000FF // Buffer Almost EmptyThis register + // holds the programmable almost + // empty level value used to + // determine almost empty buffer + // condition. If the user wants an + // interrupt or a DMA write request + // to be issued during a transmit + // operation when the data buffer is + // able to receive n bytes then the + // buffer MCSPI_MODULCTRL[AEL] must + // be set with n-1. 0x00 one byte + // 0x01 2 bytes 0xFE 255 bytes 0xFF + // 256bytes +#define MCSPI_XFERLEVEL_AEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_DAFTX register. +// +//****************************************************************************** +#define MCSPI_DAFTX_DAFTDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA + // 256 bit aligned address. "This + // Register is only is used when + // MCSPI_MODULCTRL[FDAA] is set to + // ""1"" and only one of the + // MCSPI_CH(i)CONF[FFEW] of enabled + // channels is set. If these + // conditions are not respected any + // access to this register return a + // null value." +#define MCSPI_DAFTX_DAFTDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_DAFRX register. +// +//****************************************************************************** +#define MCSPI_DAFRX_DAFRDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA + // 256 bit aligned address. "This + // Register is only is used when + // MCSPI_MODULCTRL[FDAA] is set to + // ""1"" and only one of the + // MCSPI_CH(i)CONF[FFEW] of enabled + // channels is set. If these + // conditions are not respected any + // access to this register return a + // null value." +#define MCSPI_DAFRX_DAFRDATA_S 0 + + + +#endif // __HW_MCSPI_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_memmap.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_memmap.h new file mode 100644 index 000000000..dcf5806b6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_memmap.h @@ -0,0 +1,86 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the slave_1 interface. +// +//***************************************************************************** +#define FLASH_BASE 0x01000000 +#define SRAM_BASE 0x20000000 +#define WDT_BASE 0x40000000 +#define GPIOA0_BASE 0x40004000 +#define GPIOA1_BASE 0x40005000 +#define GPIOA2_BASE 0x40006000 +#define GPIOA3_BASE 0x40007000 +#define GPIOA4_BASE 0x40024000 +#define UARTA0_BASE 0x4000C000 +#define UARTA1_BASE 0x4000D000 +#define I2CA0_BASE 0x40020000 +#define TIMERA0_BASE 0x40030000 +#define TIMERA1_BASE 0x40031000 +#define TIMERA2_BASE 0x40032000 +#define TIMERA3_BASE 0x40033000 +#define STACKDIE_CTRL_BASE 0x400F5000 +#define COMMON_REG_BASE 0x400F7000 +#define FLASH_CONTROL_BASE 0x400FD000 +#define SYSTEM_CONTROL_BASE 0x400FE000 +#define UDMA_BASE 0x400FF000 +#define SDHOST_BASE 0x44010000 +#define CAMERA_BASE 0x44018000 +#define I2S_BASE 0x4401C000 +#define SSPI_BASE 0x44020000 +#define GSPI_BASE 0x44021000 +#define LSPI_BASE 0x44022000 +#define ARCM_BASE 0x44025000 +#define APPS_CONFIG_BASE 0x44026000 +#define GPRCM_BASE 0x4402D000 +#define OCP_SHARED_BASE 0x4402E000 +#define ADC_BASE 0x4402E800 +#define HIB1P2_BASE 0x4402F000 +#define HIB3P3_BASE 0x4402F800 +#define DTHE_BASE 0x44030000 +#define SHAMD5_BASE 0x44035000 +#define AES_BASE 0x44037000 +#define DES_BASE 0x44039000 + + +#endif // __HW_MEMMAP_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mmchs.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mmchs.h new file mode 100644 index 000000000..b7885e730 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_mmchs.h @@ -0,0 +1,1921 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_MMCHS_H__ +#define __HW_MMCHS_H__ + +//***************************************************************************** +// +// The following are defines for the MMCHS register offsets. +// +//***************************************************************************** +#define MMCHS_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) + // Used by software to track + // features bugs and compatibility +#define MMCHS_O_HL_HWINFO 0x00000004 // Information about the IP + // module's hardware configuration + // i.e. typically the module's HDL + // generics (if any). Actual field + // format and encoding is up to the + // module's designer to decide. +#define MMCHS_O_HL_SYSCONFIG 0x00000010 // Clock management configuration +#define MMCHS_O_SYSCONFIG 0x00000110 // System Configuration Register + // This register allows controlling + // various parameters of the OCP + // interface. +#define MMCHS_O_SYSSTATUS 0x00000114 // System Status Register This + // register provides status + // information about the module + // excluding the interrupt status + // information +#define MMCHS_O_CSRE 0x00000124 // Card status response error This + // register enables the host + // controller to detect card status + // errors of response type R1 R1b + // for all cards and of R5 R5b and + // R6 response for cards types SD or + // SDIO. When a bit MMCHS_CSRE[i] is + // set to 1 if the corresponding bit + // at the same position in the + // response MMCHS_RSP0[i] is set to + // 1 the host controller indicates a + // card error (MMCHS_STAT[CERR]) + // interrupt status to avoid the + // host driver reading the response + // register (MMCHS_RSP0). Note: No + // automatic card error detection + // for autoCMD12 is implemented; the + // host system has to check + // autoCMD12 response register + // (MMCHS_RESP76) for possible card + // errors. +#define MMCHS_O_SYSTEST 0x00000128 // System Test register This + // register is used to control the + // signals that connect to I/O pins + // when the module is configured in + // system test (SYSTEST) mode for + // boundary connectivity + // verification. Note: In SYSTEST + // mode a write into MMCHS_CMD + // register will not start a + // transfer. The buffer behaves as a + // stack accessible only by the + // local host (push and pop + // operations). In this mode the + // Transfer Block Size + // (MMCHS_BLK[BLEN]) and the Blocks + // count for current transfer + // (MMCHS_BLK[NBLK]) are needed to + // generate a Buffer write ready + // interrupt (MMCHS_STAT[BWR]) or a + // Buffer read ready interrupt + // (MMCHS_STAT[BRR]) and DMA + // requests if enabled. +#define MMCHS_O_CON 0x0000012C // Configuration register This + // register is used: - to select the + // functional mode or the SYSTEST + // mode for any card. - to send an + // initialization sequence to any + // card. - to enable the detection + // on DAT[1] of a card interrupt for + // SDIO cards only. and also to + // configure : - specific data and + // command transfers for MMC cards + // only. - the parameters related to + // the card detect and write protect + // input signals. +#define MMCHS_O_PWCNT 0x00000130 // Power counter register This + // register is used to program a mmc + // counter to delay command + // transfers after activating the + // PAD power this value depends on + // PAD characteristics and voltage. +#define MMCHS_O_BLK 0x00000204 // Transfer Length Configuration + // register MMCHS_BLK[BLEN] is the + // block size register. + // MMCHS_BLK[NBLK] is the block + // count register. This register + // shall be used for any card. +#define MMCHS_O_ARG 0x00000208 // Command argument Register This + // register contains command + // argument specified as bit 39-8 of + // Command-Format These registers + // must be initialized prior to + // sending the command itself to the + // card (write action into the + // register MMCHS_CMD register). + // Only exception is for a command + // index specifying stuff bits in + // arguments making a write + // unnecessary. +#define MMCHS_O_CMD 0x0000020C // Command and transfer mode + // register MMCHS_CMD[31:16] = the + // command register MMCHS_CMD[15:0] + // = the transfer mode. This + // register configures the data and + // command transfers. A write into + // the most significant byte send + // the command. A write into + // MMCHS_CMD[15:0] registers during + // data transfer has no effect. This + // register shall be used for any + // card. Note: In SYSTEST mode a + // write into MMCHS_CMD register + // will not start a transfer. +#define MMCHS_O_RSP10 0x00000210 // Command response[31:0] Register + // This 32-bit register holds bits + // positions [31:0] of command + // response type + // R1/R1b/R2/R3/R4/R5/R5b/R6 +#define MMCHS_O_RSP32 0x00000214 // Command response[63:32] Register + // This 32-bit register holds bits + // positions [63:32] of command + // response type R2 +#define MMCHS_O_RSP54 0x00000218 // Command response[95:64] Register + // This 32-bit register holds bits + // positions [95:64] of command + // response type R2 +#define MMCHS_O_RSP76 0x0000021C // Command response[127:96] + // Register This 32-bit register + // holds bits positions [127:96] of + // command response type R2 +#define MMCHS_O_DATA 0x00000220 // Data Register This register is + // the 32-bit entry point of the + // buffer for read or write data + // transfers. The buffer size is + // 32bits x256(1024 bytes). Bytes + // within a word are stored and read + // in little endian format. This + // buffer can be used as two 512 + // byte buffers to transfer data + // efficiently without reducing the + // throughput. Sequential and + // contiguous access is necessary to + // increment the pointer correctly. + // Random or skipped access is not + // allowed. In little endian if the + // local host accesses this register + // byte-wise or 16bit-wise the least + // significant byte (bits [7:0]) + // must always be written/read + // first. The update of the buffer + // address is done on the most + // significant byte write for full + // 32-bit DATA register or on the + // most significant byte of the last + // word of block transfer. Example + // 1: Byte or 16-bit access + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=1100 (2-bytes) OK + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=0100 (1-byte) OK + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=1000 (1-byte) Bad +#define MMCHS_O_PSTATE 0x00000224 // Present state register The Host + // can get status of the Host + // Controller from this 32-bit read + // only register. +#define MMCHS_O_HCTL 0x00000228 // Control register This register + // defines the host controls to set + // power wakeup and transfer + // parameters. MMCHS_HCTL[31:24] = + // Wakeup control MMCHS_HCTL[23:16] + // = Block gap control + // MMCHS_HCTL[15:8] = Power control + // MMCHS_HCTL[7:0] = Host control +#define MMCHS_O_SYSCTL 0x0000022C // SD system control register This + // register defines the system + // controls to set software resets + // clock frequency management and + // data timeout. MMCHS_SYSCTL[31:24] + // = Software resets + // MMCHS_SYSCTL[23:16] = Timeout + // control MMCHS_SYSCTL[15:0] = + // Clock control +#define MMCHS_O_STAT 0x00000230 // Interrupt status register The + // interrupt status regroups all the + // status of the module internal + // events that can generate an + // interrupt. MMCHS_STAT[31:16] = + // Error Interrupt Status + // MMCHS_STAT[15:0] = Normal + // Interrupt Status +#define MMCHS_O_IE 0x00000234 // Interrupt SD enable register + // This register allows to + // enable/disable the module to set + // status bits on an event-by-event + // basis. MMCHS_IE[31:16] = Error + // Interrupt Status Enable + // MMCHS_IE[15:0] = Normal Interrupt + // Status Enable +#define MMCHS_O_ISE 0x00000238 // Interrupt signal enable register + // This register allows to + // enable/disable the module + // internal sources of status on an + // event-by-event basis. + // MMCHS_ISE[31:16] = Error + // Interrupt Signal Enable + // MMCHS_ISE[15:0] = Normal + // Interrupt Signal Enable +#define MMCHS_O_AC12 0x0000023C // Auto CMD12 Error Status Register + // The host driver may determine + // which of the errors cases related + // to Auto CMD12 has occurred by + // checking this MMCHS_AC12 register + // when an Auto CMD12 Error + // interrupt occurs. This register + // is valid only when Auto CMD12 is + // enabled (MMCHS_CMD[ACEN]) and + // Auto CMD12Error (MMCHS_STAT[ACE]) + // is set to 1. Note: These bits are + // automatically reset when starting + // a new adtc command with data. +#define MMCHS_O_CAPA 0x00000240 // Capabilities register This + // register lists the capabilities + // of the MMC/SD/SDIO host + // controller. +#define MMCHS_O_CUR_CAPA 0x00000248 // Maximum current capabilities + // Register This register indicates + // the maximum current capability + // for each voltage. The value is + // meaningful if the voltage support + // is set in the capabilities + // register (MMCHS_CAPA). + // Initialization of this register + // (via a write access to this + // register) depends on the system + // capabilities. The host driver + // shall not modify this register + // after the initilaization. This + // register is only reinitialized by + // a hard reset (via RESETN signal) +#define MMCHS_O_FE 0x00000250 // Force Event Register for Error + // Interrupt status The force Event + // Register is not a physically + // implemented register. Rather it + // is an address at which the Error + // Interrupt Status register can be + // written. The effect of a write to + // this address will be reflected in + // the Error Interrupt Status + // Register if corresponding bit of + // the Error Interrupt Status Enable + // Register is set. +#define MMCHS_O_ADMAES 0x00000254 // ADMA Error Status Register When + // ADMA Error Interrupt is occurred + // the ADMA Error States field in + // this register holds the ADMA + // state and the ADMA System Address + // Register holds the address around + // the error descriptor. For + // recovering the error the Host + // Driver requires the ADMA state to + // identify the error descriptor + // address as follows: ST_STOP: + // Previous location set in the ADMA + // System Address register is the + // error descriptor address ST_FDS: + // Current location set in the ADMA + // System Address register is the + // error descriptor address ST_CADR: + // This sate is never set because do + // not generate ADMA error in this + // state. ST_TFR: Previous location + // set in the ADMA System Address + // register is the error descriptor + // address In case of write + // operation the Host Driver should + // use ACMD22 to get the number of + // written block rather than using + // this information since unwritten + // data may exist in the Host + // Controller. The Host Controller + // generates the ADMA Error + // Interrupt when it detects invalid + // descriptor data (Valid=0) at the + // ST_FDS state. In this case ADMA + // Error State indicates that an + // error occurs at ST_FDS state. The + // Host Driver may find that the + // Valid bit is not set in the error + // descriptor. +#define MMCHS_O_ADMASAL 0x00000258 // ADMA System address Low bits +#define MMCHS_O_REV 0x000002FC // Versions Register This register + // contains the hard coded RTL + // vendor revision number the + // version number of SD + // specification compliancy and a + // slot status bit. MMCHS_REV[31:16] + // = Host controller version + // MMCHS_REV[15:0] = Slot Interrupt + // Status + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HL_REV register. +// +//****************************************************************************** +#define MMCHS_HL_REV_SCHEME_M 0xC0000000 +#define MMCHS_HL_REV_SCHEME_S 30 +#define MMCHS_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define MMCHS_HL_REV_FUNC_S 16 +#define MMCHS_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define MMCHS_HL_REV_R_RTL_S 11 +#define MMCHS_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. +#define MMCHS_HL_REV_X_MAJOR_S 8 +#define MMCHS_HL_REV_CUSTOM_M 0x000000C0 +#define MMCHS_HL_REV_CUSTOM_S 6 +#define MMCHS_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. +#define MMCHS_HL_REV_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register. +// +//****************************************************************************** +#define MMCHS_HL_HWINFO_RETMODE 0x00000040 +#define MMCHS_HL_HWINFO_MEM_SIZE_M \ + 0x0000003C + +#define MMCHS_HL_HWINFO_MEM_SIZE_S 2 +#define MMCHS_HL_HWINFO_MERGE_MEM \ + 0x00000002 + +#define MMCHS_HL_HWINFO_MADMA_EN \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MMCHS_O_HL_SYSCONFIG register. +// +//****************************************************************************** +#define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \ + 0x00000030 // Configuration of the local + // initiator state management mode. + // By definition initiator may + // generate read/write transaction + // as long as it is out of STANDBY + // state. 0x0 Force-standby mode: + // local initiator is + // unconditionally placed in standby + // state.Backup mode for debug only. + // 0x1 No-standby mode: local + // initiator is unconditionally + // placed out of standby + // state.Backup mode for debug only. + // 0x2 Smart-standby mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator.IP module + // shall not generate + // (initiator-related) wakeup + // events. 0x3 "Smart-Standby + // wakeup-capable mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator. IP module may + // generate (master-related) wakeup + // events when in standby state.Mode + // is only relevant if the + // appropriate IP module ""mwakeup"" + // output is implemented." + +#define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4 +#define MMCHS_HL_SYSCONFIG_IDLEMODE_M \ + 0x0000000C // Configuration of the local + // target state management mode. By + // definition target can handle + // read/write transaction as long as + // it is out of IDLE state. 0x0 + // Force-idle mode: local target's + // idle state follows (acknowledges) + // the system's idle requests + // unconditionally i.e. regardless + // of the IP module's internal + // requirements.Backup mode for + // debug only. 0x1 No-idle mode: + // local target never enters idle + // state.Backup mode for debug only. + // 0x2 Smart-idle mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module shall not + // generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 "Smart-idle + // wakeup-capable mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2 +#define MMCHS_HL_SYSCONFIG_FREEEMU \ + 0x00000002 // Sensitivity to emulation (debug) + // suspend input signal. + // Functionality NOT implemented in + // MMCHS. 0 IP module is sensitive + // to emulation suspend 1 IP module + // is not sensitive to emulation + // suspend + +#define MMCHS_HL_SYSCONFIG_SOFTRESET \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register. +// +//****************************************************************************** +#define MMCHS_SYSCONFIG_STANDBYMODE_M \ + 0x00003000 // Master interface power + // Management standby/wait control. + // The bit field is only useful when + // generic parameter MADMA_EN + // (Master ADMA enable) is set as + // active otherwise it is a read + // only register read a '0'. 0x0 + // Force-standby. Mstandby is forced + // unconditionnaly. 0x1 No-standby. + // Mstandby is never asserted. 0x2 + // Smart-standby mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator.IP module + // shall not generate + // (initiator-related) wakeup + // events. 0x3 Smart-Standby + // wakeup-capable mode: "local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator. IP module may + // generate (master-related) wakeup + // events when in standby state.Mode + // is only relevant if the + // appropriate IP module ""mwakeup"" + // output is implemented." + +#define MMCHS_SYSCONFIG_STANDBYMODE_S 12 +#define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \ + 0x00000300 // Clocks activity during wake up + // mode period. Bit8: OCP interface + // clock Bit9: Functional clock 0x0 + // OCP and Functional clock may be + // switched off. 0x1 OCP clock is + // maintained. Functional clock may + // be switched-off. 0x2 Functional + // clock is maintained. OCP clock + // may be switched-off. 0x3 OCP and + // Functional clocks are maintained. + +#define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8 +#define MMCHS_SYSCONFIG_SIDLEMODE_M \ + 0x00000018 // Power management 0x0 If an idle + // request is detected the MMCHS + // acknowledges it unconditionally + // and goes in Inactive mode. + // Interrupt and DMA requests are + // unconditionally de-asserted. 0x1 + // If an idle request is detected + // the request is ignored and the + // module keeps on behaving + // normally. 0x2 Smart-idle mode: + // local target's idle state + // eventually follows (acknowledges) + // the system's idle requests + // depending on the IP module's + // internal requirements.IP module + // shall not generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 Smart-idle + // wakeup-capable mode: "local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MMCHS_SYSCONFIG_SIDLEMODE_S 3 +#define MMCHS_SYSCONFIG_ENAWAKEUP \ + 0x00000004 // Wakeup feature control 0 Wakeup + // capability is disabled 1 Wakeup + // capability is enabled + +#define MMCHS_SYSCONFIG_SOFTRESET \ + 0x00000002 + +#define MMCHS_SYSCONFIG_AUTOIDLE \ + 0x00000001 // Internal Clock gating strategy 0 + // Clocks are free-running 1 + // Automatic clock gating strategy + // is applied based on the OCP and + // MMC interface activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register. +// +//****************************************************************************** +#define MMCHS_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CSRE register. +// +//****************************************************************************** +#define MMCHS_CSRE_CSRE_M 0xFFFFFFFF // Card status response error +#define MMCHS_CSRE_CSRE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSTEST register. +// +//****************************************************************************** +#define MMCHS_SYSTEST_OBI 0x00010000 +#define MMCHS_SYSTEST_SDCD 0x00008000 +#define MMCHS_SYSTEST_SDWP 0x00004000 +#define MMCHS_SYSTEST_WAKD 0x00002000 +#define MMCHS_SYSTEST_SSB 0x00001000 +#define MMCHS_SYSTEST_D7D 0x00000800 +#define MMCHS_SYSTEST_D6D 0x00000400 +#define MMCHS_SYSTEST_D5D 0x00000200 +#define MMCHS_SYSTEST_D4D 0x00000100 +#define MMCHS_SYSTEST_D3D 0x00000080 +#define MMCHS_SYSTEST_D2D 0x00000040 +#define MMCHS_SYSTEST_D1D 0x00000020 +#define MMCHS_SYSTEST_D0D 0x00000010 +#define MMCHS_SYSTEST_DDIR 0x00000008 +#define MMCHS_SYSTEST_CDAT 0x00000004 +#define MMCHS_SYSTEST_CDIR 0x00000002 +#define MMCHS_SYSTEST_MCKD 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CON register. +// +//****************************************************************************** +#define MMCHS_CON_SDMA_LNE 0x00200000 // Slave DMA Level/Edge Request: + // The waveform of the DMA request + // can be configured either edge + // sensitive with early de-assertion + // on first access to MMCHS_DATA + // register or late de-assertion + // request remains active until last + // allowed data written into + // MMCHS_DATA. 0 Slave DMA edge + // sensitive Early DMA de-assertion + // 1 Slave DMA level sensitive Late + // DMA de-assertion +#define MMCHS_CON_DMA_MNS 0x00100000 // DMA Master or Slave selection: + // When this bit is set and the + // controller is configured to use + // the DMA Ocp master interface is + // used to get datas from system + // using ADMA2 procedure (direct + // access to the memory).This option + // is only available if generic + // parameter MADMA_EN is asserted to + // '1'. 0 The controller is slave on + // data transfers with system. 1 The + // controller is master on data + // exchange with system controller + // must be configured as using DMA. +#define MMCHS_CON_DDR 0x00080000 // Dual Data Rate mode: When this + // register is set the controller + // uses both clock edge to emit or + // receive data. Odd bytes are + // transmitted on falling edges and + // even bytes are transmitted on + // rise edges. It only applies on + // Data bytes and CRC Start end bits + // and CRC status are kept full + // cycle. This bit field is only + // meaningful and active for even + // clock divider ratio of + // MMCHS_SYSCTL[CLKD] it is + // insensitive to MMCHS_HCTL[HSPE] + // setting. 0 Standard mode : data + // are transmitted on a single edge + // depending on MMCHS_HCTRL[HSPE]. 1 + // Data Bytes and CRC are + // transmitted on both edge. +#define MMCHS_CON_BOOT_CF0 0x00040000 +#define MMCHS_CON_BOOT_ACK 0x00020000 // Book acknowledge received: When + // this bit is set the controller + // should receive a boot status on + // DAT0 line after next command + // issued. If no status is received + // a data timeout will be generated. + // 0 No acknowledge to be received 1 + // A boot status will be received on + // DAT0 line after issuing a + // command. +#define MMCHS_CON_CLKEXTFREE 0x00010000 // External clock free running: + // This register is used to maintain + // card clock out of transfer + // transaction to enable slave + // module for example to generate a + // synchronous interrupt on DAT[1]. + // The Clock will be maintain only + // if MMCHS_SYSCTL[CEN] is set. 0 + // External card clock is cut off + // outside active transaction + // period. 1 External card clock is + // maintain even out of active + // transaction period only if + // MMCHS_SYSCTL[CEN] is set. +#define MMCHS_CON_PADEN 0x00008000 // Control Power for MMC Lines: + // This register is only useful when + // MMC PADs contain power saving + // mechanism to minimize its leakage + // power. It works as a GPIO that + // directly control the ACTIVE pin + // of PADs. Excepted for DAT[1] the + // signal is also combine outside + // the module with the dedicated + // power control MMCHS_CON[CTPL] + // bit. 0 ADPIDLE module pin is not + // forced it is automatically + // generated by the MMC fsms. 1 + // ADPIDLE module pin is forced to + // active state. +#define MMCHS_CON_OBIE 0x00004000 // Out-of-Band Interrupt Enable MMC + // cards only: This bit enables the + // detection of Out-of-Band + // Interrupt on MMCOBI input pin. + // The usage of the Out-of-Band + // signal (OBI) is optional and + // depends on the system + // integration. 0 Out-of-Band + // interrupt detection disabled 1 + // Out-of-Band interrupt detection + // enabled +#define MMCHS_CON_OBIP 0x00002000 // Out-of-Band Interrupt Polarity + // MMC cards only: This bit selects + // the active level of the + // out-of-band interrupt coming from + // MMC cards. The usage of the + // Out-of-Band signal (OBI) is + // optional and depends on the + // system integration. 0 active high + // level 1 active low level +#define MMCHS_CON_CEATA 0x00001000 // CE-ATA control mode MMC cards + // compliant with CE-ATA:By default + // this bit is set to 0. It is use + // to indicate that next commands + // are considered as specific CE-ATA + // commands that potentially use + // 'command completion' features. 0 + // Standard MMC/SD/SDIO mode. 1 + // CE-ATA mode next commands are + // considered as CE-ATA commands. +#define MMCHS_CON_CTPL 0x00000800 // Control Power for DAT[1] line + // MMC and SD cards: By default this + // bit is set to 0 and the host + // controller automatically disables + // all the input buffers outside of + // a transaction to minimize the + // leakage current. SDIO cards: When + // this bit is set to 1 the host + // controller automatically disables + // all the input buffers except the + // buffer of DAT[1] outside of a + // transaction in order to detect + // asynchronous card interrupt on + // DAT[1] line and minimize the + // leakage current of the buffers. 0 + // Disable all the input buffers + // outside of a transaction. 1 + // Disable all the input buffers + // except the buffer of DAT[1] + // outside of a transaction. +#define MMCHS_CON_DVAL_M 0x00000600 // Debounce filter value All cards + // This register is used to define a + // debounce period to filter the + // card detect input signal (SDCD). + // The usage of the card detect + // input signal (SDCD) is optional + // and depends on the system + // integration and the type of the + // connector housing that + // accommodates the card. 0x0 33 us + // debounce period 0x1 231 us + // debounce period 0x2 1 ms debounce + // period 0x3 84 ms debounce period +#define MMCHS_CON_DVAL_S 9 +#define MMCHS_CON_WPP 0x00000100 // Write protect polarity For SD + // and SDIO cards only This bit + // selects the active level of the + // write protect input signal + // (SDWP). The usage of the write + // protect input signal (SDWP) is + // optional and depends on the + // system integration and the type + // of the connector housing that + // accommodates the card. 0 active + // high level 1 active low level +#define MMCHS_CON_CDP 0x00000080 // Card detect polarity All cards + // This bit selects the active level + // of the card detect input signal + // (SDCD). The usage of the card + // detect input signal (SDCD) is + // optional and depends on the + // system integration and the type + // of the connector housing that + // accommodates the card. 0 active + // high level 1 active low level +#define MMCHS_CON_MIT 0x00000040 // MMC interrupt command Only for + // MMC cards. This bit must be set + // to 1 when the next write access + // to the command register + // (MMCHS_CMD) is for writing a MMC + // interrupt command (CMD40) + // requiring the command timeout + // detection to be disabled for the + // command response. 0 Command + // timeout enabled 1 Command timeout + // disabled +#define MMCHS_CON_DW8 0x00000020 // 8-bit mode MMC select For + // SD/SDIO cards this bit must be + // set to 0. For MMC card this bit + // must be set following a valid + // SWITCH command (CMD6) with the + // correct value and extend CSD + // index written in the argument. + // Prior to this command the MMC + // card configuration register (CSD + // and EXT_CSD) must be verified for + // compliancy with MMC standard + // specification 4.x (see section + // 3.6). 0 1-bit or 4-bit Data width + // (DAT[0] used MMC SD cards) 1 + // 8-bit Data width (DAT[7:0] used + // MMC cards) +#define MMCHS_CON_MODE 0x00000010 // Mode select All cards These bits + // select between Functional mode + // and SYSTEST mode. 0 Functional + // mode. Transfers to the + // MMC/SD/SDIO cards follow the card + // protocol. MMC clock is enabled. + // MMC/SD transfers are operated + // under the control of the CMD + // register. 1 SYSTEST mode The + // signal pins are configured as + // general-purpose input/output and + // the 1024-byte buffer is + // configured as a stack memory + // accessible only by the local host + // or system DMA. The pins retain + // their default type (input output + // or in-out). SYSTEST mode is + // operated under the control of the + // SYSTEST register. +#define MMCHS_CON_STR 0x00000008 // Stream command Only for MMC + // cards. This bit must be set to 1 + // only for the stream data + // transfers (read or write) of the + // adtc commands. Stream read is a + // class 1 command (CMD11: + // READ_DAT_UNTIL_STOP). Stream + // write is a class 3 command + // (CMD20: WRITE_DAT_UNTIL_STOP). 0 + // Block oriented data transfer 1 + // Stream oriented data transfer +#define MMCHS_CON_HR 0x00000004 // Broadcast host response Only for + // MMC cards. This register is used + // to force the host to generate a + // 48-bit response for bc command + // type. "It can be used to + // terminate the interrupt mode by + // generating a CMD40 response by + // the core (see section 4.3 + // ""Interrupt Mode"" in the MMC [1] + // specification). In order to have + // the host response to be generated + // in open drain mode the register + // MMCHS_CON[OD] must be set to 1." + // When MMCHS_CON[CEATA] is set to 1 + // and MMCHS_ARG set to 0x00000000 + // when writing 0x00000000 into + // MMCHS_CMD register the host + // controller performs a 'command + // completion signal disable' token + // i.e. CMD line held to '0' during + // 47 cycles followed by a 1. 0 The + // host does not generate a 48-bit + // response instead of a command. 1 + // The host generates a 48-bit + // response instead of a command or + // a command completion signal + // disable token. +#define MMCHS_CON_INIT 0x00000002 // Send initialization stream All + // cards. When this bit is set to 1 + // and the card is idle an + // initialization sequence is sent + // to the card. "An initialization + // sequence consists of setting the + // CMD line to 1 during 80 clock + // cycles. The initialisation + // sequence is mandatory - but it is + // not required to do it through + // this bit - this bit makes it + // easier. Clock divider + // (MMCHS_SYSCTL[CLKD]) should be + // set to ensure that 80 clock + // periods are greater than 1ms. + // (see section 9.3 ""Power-Up"" in + // the MMC card specification [1] or + // section 6.4 in the SD card + // specification [2])." Note: in + // this mode there is no command + // sent to the card and no response + // is expected 0 The host does not + // send an initialization sequence. + // 1 The host sends an + // initialization sequence. +#define MMCHS_CON_OD 0x00000001 // Card open drain mode. Only for + // MMC cards. This bit must be set + // to 1 for MMC card commands 1 2 3 + // and 40 and if the MMC card bus is + // operating in open-drain mode + // during the response phase to the + // command sent. Typically during + // card identification mode when the + // card is either in idle ready or + // ident state. It is also necessary + // to set this bit to 1 for a + // broadcast host response (see + // Broadcast host response register + // MMCHS_CON[HR]) 0 No Open Drain 1 + // Open Drain or Broadcast host + // response +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_PWCNT register. +// +//****************************************************************************** +#define MMCHS_PWCNT_PWRCNT_M 0x0000FFFF // Power counter register. This + // register is used to introduce a + // delay between the PAD ACTIVE pin + // assertion and the command issued. + // 0x0000 No additional delay added + // 0x0001 TCF delay (card clock + // period) 0x0002 TCF x 2 delay + // (card clock period) 0xFFFE TCF x + // 65534 delay (card clock period) + // 0xFFFF TCF x 65535 delay (card + // clock period) +#define MMCHS_PWCNT_PWRCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_BLK register. +// +//****************************************************************************** +#define MMCHS_BLK_NBLK_M 0xFFFF0000 // Blocks count for current + // transfer This register is enabled + // when Block count Enable + // (MMCHS_CMD[BCE]) is set to 1 and + // is valid only for multiple block + // transfers. Setting the block + // count to 0 results no data blocks + // being transferred. Note: The host + // controller decrements the block + // count after each block transfer + // and stops when the count reaches + // zero. This register can be + // accessed only if no transaction + // is executing (i.e after a + // transaction has stopped). Read + // operations during transfers may + // return an invalid value and write + // operation will be ignored. In + // suspend context the number of + // blocks yet to be transferred can + // be determined by reading this + // register. When restoring transfer + // context prior to issuing a Resume + // command The local host shall + // restore the previously saved + // block count. 0x0000 Stop count + // 0x0001 1 block 0x0002 2 blocks + // 0xFFFF 65535 blocks +#define MMCHS_BLK_NBLK_S 16 +#define MMCHS_BLK_BLEN_M 0x00000FFF // Transfer Block Size. This + // register specifies the block size + // for block data transfers. Read + // operations during transfers may + // return an invalid value and write + // operations are ignored. When a + // CMD12 command is issued to stop + // the transfer a read of the BLEN + // field after transfer completion + // (MMCHS_STAT[TC] set to 1) will + // not return the true byte number + // of data length while the stop + // occurs but the value written in + // this register before transfer is + // launched. 0x000 No data transfer + // 0x001 1 byte block length 0x002 2 + // bytes block length 0x003 3 bytes + // block length 0x1FF 511 bytes + // block length 0x200 512 bytes + // block length 0x7FF 2047 bytes + // block length 0x800 2048 bytes + // block length +#define MMCHS_BLK_BLEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ARG register. +// +//****************************************************************************** +#define MMCHS_ARG_ARG_M 0xFFFFFFFF // Command argument bits [31:0] +#define MMCHS_ARG_ARG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CMD register. +// +//****************************************************************************** +#define MMCHS_CMD_INDX_M 0x3F000000 // Command index Binary encoded + // value from 0 to 63 specifying the + // command number send to card 0x00 + // CMD0 or ACMD0 0x01 CMD1 or ACMD1 + // 0x02 CMD2 or ACMD2 0x03 CMD3 or + // ACMD3 0x04 CMD4 or ACMD4 0x05 + // CMD5 or ACMD5 0x06 CMD6 or ACMD6 + // 0x07 CMD7 or ACMD7 0x08 CMD8 or + // ACMD8 0x09 CMD9 or ACMD9 0x0A + // CMD10 or ACMD10 0x0B CMD11 or + // ACMD11 0x0C CMD12 or ACMD12 0x0D + // CMD13 or ACMD13 0x0E CMD14 or + // ACMD14 0x0F CMD15 or ACMD15 0x10 + // CMD16 or ACMD16 0x11 CMD17 or + // ACMD17 0x12 CMD18 or ACMD18 0x13 + // CMD19 or ACMD19 0x14 CMD20 or + // ACMD20 0x15 CMD21 or ACMD21 0x16 + // CMD22 or ACMD22 0x17 CMD23 or + // ACMD23 0x18 CMD24 or ACMD24 0x19 + // CMD25 or ACMD25 0x1A CMD26 or + // ACMD26 0x1B CMD27 or ACMD27 0x1C + // CMD28 or ACMD28 0x1D CMD29 or + // ACMD29 0x1E CMD30 or ACMD30 0x1F + // CMD31 or ACMD31 0x20 CMD32 or + // ACMD32 0x21 CMD33 or ACMD33 0x22 + // CMD34 or ACMD34 0x23 CMD35 or + // ACMD35 0x24 CMD36 or ACMD36 0x25 + // CMD37 or ACMD37 0x26 CMD38 or + // ACMD38 0x27 CMD39 or ACMD39 0x28 + // CMD40 or ACMD40 0x29 CMD41 or + // ACMD41 0x2A CMD42 or ACMD42 0x2B + // CMD43 or ACMD43 0x2C CMD44 or + // ACMD44 0x2D CMD45 or ACMD45 0x2E + // CMD46 or ACMD46 0x2F CMD47 or + // ACMD47 0x30 CMD48 or ACMD48 0x31 + // CMD49 or ACMD49 0x32 CMD50 or + // ACMD50 0x33 CMD51 or ACMD51 0x34 + // CMD52 or ACMD52 0x35 CMD53 or + // ACMD53 0x36 CMD54 or ACMD54 0x37 + // CMD55 or ACMD55 0x38 CMD56 or + // ACMD56 0x39 CMD57 or ACMD57 0x3A + // CMD58 or ACMD58 0x3B CMD59 or + // ACMD59 0x3C CMD60 or ACMD60 0x3D + // CMD61 or ACMD61 0x3E CMD62 or + // ACMD62 0x3F CMD63 or ACMD63 +#define MMCHS_CMD_INDX_S 24 +#define MMCHS_CMD_CMD_TYPE_M 0x00C00000 // Command type This register + // specifies three types of special + // command: Suspend Resume and + // Abort. These bits shall be set to + // 00b for all other commands. 0x0 + // Others Commands 0x1 "CMD52 for + // writing ""Bus Suspend"" in CCCR" + // 0x2 "CMD52 for writing ""Function + // Select"" in CCCR" 0x3 "Abort + // command CMD12 CMD52 for writing + // "" I/O Abort"" in CCCR" +#define MMCHS_CMD_CMD_TYPE_S 22 +#define MMCHS_CMD_DP 0x00200000 // Data present select This + // register indicates that data is + // present and DAT line shall be + // used. It must be set to 0 in the + // following conditions: - command + // using only CMD line - command + // with no data transfer but using + // busy signal on DAT[0] - Resume + // command 0 Command with no data + // transfer 1 Command with data + // transfer +#define MMCHS_CMD_CICE 0x00100000 // Command Index check enable This + // bit must be set to 1 to enable + // index check on command response + // to compare the index field in the + // response against the index of the + // command. If the index is not the + // same in the response as in the + // command it is reported as a + // command index error + // (MMCHS_STAT[CIE] set to1) Note: + // The register CICE cannot be + // configured for an Auto CMD12 then + // index check is automatically + // checked when this command is + // issued. 0 Index check disable 1 + // Index check enable +#define MMCHS_CMD_CCCE 0x00080000 // Command CRC check enable This + // bit must be set to 1 to enable + // CRC7 check on command response to + // protect the response against + // transmission errors on the bus. + // If an error is detected it is + // reported as a command CRC error + // (MMCHS_STAT[CCRC] set to 1). + // Note: The register CCCE cannot be + // configured for an Auto CMD12 and + // then CRC check is automatically + // checked when this command is + // issued. 0 CRC7 check disable 1 + // CRC7 check enable +#define MMCHS_CMD_RSP_TYPE_M 0x00030000 // Response type This bits defines + // the response type of the command + // 0x0 No response 0x1 Response + // Length 136 bits 0x2 Response + // Length 48 bits 0x3 Response + // Length 48 bits with busy after + // response +#define MMCHS_CMD_RSP_TYPE_S 16 +#define MMCHS_CMD_MSBS 0x00000020 // Multi/Single block select This + // bit must be set to 1 for data + // transfer in case of multi block + // command. For any others command + // this bit shall be set to 0. 0 + // Single block. If this bit is 0 it + // is not necessary to set the + // register MMCHS_BLK[NBLK]. 1 Multi + // block. When Block Count is + // disabled (MMCHS_CMD[BCE] is set + // to 0) in Multiple block transfers + // (MMCHS_CMD[MSBS] is set to 1) the + // module can perform infinite + // transfer. +#define MMCHS_CMD_DDIR 0x00000010 // Data transfer Direction Select + // This bit defines either data + // transfer will be a read or a + // write. 0 Data Write (host to + // card) 1 Data Read (card to host) +#define MMCHS_CMD_ACEN 0x00000004 // Auto CMD12 Enable SD card only. + // When this bit is set to 1 the + // host controller issues a CMD12 + // automatically after the transfer + // completion of the last block. The + // Host Driver shall not set this + // bit to issue commands that do not + // require CMD12 to stop data + // transfer. In particular secure + // commands do not require CMD12. 0 + // Auto CMD12 disable 1 Auto CMD12 + // enable or CCS detection enabled. +#define MMCHS_CMD_BCE 0x00000002 // Block Count Enable Multiple + // block transfers only. This bit is + // used to enable the block count + // register (MMCHS_BLK[NBLK]). When + // Block Count is disabled + // (MMCHS_CMD[BCE] is set to 0) in + // Multiple block transfers + // (MMCHS_CMD[MSBS] is set to 1) the + // module can perform infinite + // transfer. 0 Block count disabled + // for infinite transfer. 1 Block + // count enabled for multiple block + // transfer with known number of + // blocks +#define MMCHS_CMD_DE 0x00000001 // DMA Enable This bit is used to + // enable DMA mode for host data + // access. 0 DMA mode disable 1 DMA + // mode enable +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP10 register. +// +//****************************************************************************** +#define MMCHS_RSP10_RSP1_M 0xFFFF0000 // Command Response [31:16] +#define MMCHS_RSP10_RSP1_S 16 +#define MMCHS_RSP10_RSP0_M 0x0000FFFF // Command Response [15:0] +#define MMCHS_RSP10_RSP0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP32 register. +// +//****************************************************************************** +#define MMCHS_RSP32_RSP3_M 0xFFFF0000 // Command Response [63:48] +#define MMCHS_RSP32_RSP3_S 16 +#define MMCHS_RSP32_RSP2_M 0x0000FFFF // Command Response [47:32] +#define MMCHS_RSP32_RSP2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP54 register. +// +//****************************************************************************** +#define MMCHS_RSP54_RSP5_M 0xFFFF0000 // Command Response [95:80] +#define MMCHS_RSP54_RSP5_S 16 +#define MMCHS_RSP54_RSP4_M 0x0000FFFF // Command Response [79:64] +#define MMCHS_RSP54_RSP4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP76 register. +// +//****************************************************************************** +#define MMCHS_RSP76_RSP7_M 0xFFFF0000 // Command Response [127:112] +#define MMCHS_RSP76_RSP7_S 16 +#define MMCHS_RSP76_RSP6_M 0x0000FFFF // Command Response [111:96] +#define MMCHS_RSP76_RSP6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_DATA register. +// +//****************************************************************************** +#define MMCHS_DATA_DATA_M 0xFFFFFFFF // Data Register [31:0] In + // functional mode (MMCHS_CON[MODE] + // set to the default value 0) A + // read access to this register is + // allowed only when the buffer read + // enable status is set to 1 + // (MMCHS_PSTATE[BRE]) otherwise a + // bad access (MMCHS_STAT[BADA]) is + // signaled. A write access to this + // register is allowed only when the + // buffer write enable status is set + // to 1(MMCHS_STATE[BWE]) otherwise + // a bad access (MMCHS_STAT[BADA]) + // is signaled and the data is not + // written. +#define MMCHS_DATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_PSTATE register. +// +//****************************************************************************** +#define MMCHS_PSTATE_CLEV 0x01000000 +#define MMCHS_PSTATE_DLEV_M 0x00F00000 // DAT[3:0] line signal level + // DAT[3] => bit 23 DAT[2] => bit 22 + // DAT[1] => bit 21 DAT[0] => bit 20 + // This status is used to check DAT + // line level to recover from errors + // and for debugging. This is + // especially useful in detecting + // the busy signal level from + // DAT[0]. The value of these + // registers after reset depends on + // the DAT lines level at that time. +#define MMCHS_PSTATE_DLEV_S 20 +#define MMCHS_PSTATE_WP 0x00080000 +#define MMCHS_PSTATE_CDPL 0x00040000 +#define MMCHS_PSTATE_CSS 0x00020000 +#define MMCHS_PSTATE_CINS 0x00010000 +#define MMCHS_PSTATE_BRE 0x00000800 +#define MMCHS_PSTATE_BWE 0x00000400 +#define MMCHS_PSTATE_RTA 0x00000200 +#define MMCHS_PSTATE_WTA 0x00000100 +#define MMCHS_PSTATE_DLA 0x00000004 +#define MMCHS_PSTATE_DATI 0x00000002 +#define MMCHS_PSTATE_CMDI 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HCTL register. +// +//****************************************************************************** +#define MMCHS_HCTL_OBWE 0x08000000 // Wakeup event enable for + // 'Out-of-Band' Interrupt. This bit + // enables wakeup events for + // 'Out-of-Band' assertion. Wakeup + // is generated if the wakeup + // feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). The + // write to this register is ignored + // when MMCHS_CON[OBIE] is not set. + // 0 Disable wakeup on 'Out-of-Band' + // Interrupt 1 Enable wakeup on + // 'Out-of-Band' Interrupt +#define MMCHS_HCTL_REM 0x04000000 // Wakeup event enable on SD card + // removal This bit enables wakeup + // events for card removal + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card removal 1 + // Enable wakeup on card removal +#define MMCHS_HCTL_INS 0x02000000 // Wakeup event enable on SD card + // insertion This bit enables wakeup + // events for card insertion + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card insertion + // 1 Enable wakeup on card insertion +#define MMCHS_HCTL_IWE 0x01000000 // Wakeup event enable on SD card + // interrupt This bit enables wakeup + // events for card interrupt + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card interrupt + // 1 Enable wakeup on card interrupt +#define MMCHS_HCTL_IBG 0x00080000 // Interrupt block at gap This bit + // is valid only in 4-bit mode of + // SDIO card to enable interrupt + // detection in the interrupt cycle + // at block gap for a multiple block + // transfer. For MMC cards and for + // SD card this bit should be set to + // 0. 0 Disable interrupt detection + // at the block gap in 4-bit mode 1 + // Enable interrupt detection at the + // block gap in 4-bit mode +#define MMCHS_HCTL_RWC 0x00040000 // Read wait control The read wait + // function is optional only for + // SDIO cards. If the card supports + // read wait this bit must be + // enabled then requesting a stop at + // block gap (MMCHS_HCTL[SBGR]) + // generates a read wait period + // after the current end of block. + // Be careful if read wait is not + // supported it may cause a conflict + // on DAT line. 0 Disable Read Wait + // Control. Suspend/Resume cannot be + // supported. 1 Enable Read Wait + // Control +#define MMCHS_HCTL_CR 0x00020000 // Continue request This bit is + // used to restart a transaction + // that was stopped by requesting a + // stop at block gap + // (MMCHS_HCTL[SBGR]). Set this bit + // to 1 restarts the transfer. The + // bit is automatically set to 0 by + // the host controller when transfer + // has restarted i.e DAT line is + // active (MMCHS_PSTATE[DLA]) or + // transferring data + // (MMCHS_PSTATE[WTA]). The Stop at + // block gap request must be + // disabled (MMCHS_HCTL[SBGR]=0) + // before setting this bit. 0 No + // affect 1 transfer restart +#define MMCHS_HCTL_SBGR 0x00010000 // Stop at block gap request This + // bit is used to stop executing a + // transaction at the next block + // gap. The transfer can restart + // with a continue request + // (MMHS_HCTL[CR]) or during a + // suspend/resume sequence. In case + // of read transfer the card must + // support read wait control. In + // case of write transfer the host + // driver shall set this bit after + // all block data written. Until the + // transfer completion + // (MMCHS_STAT[TC] set to 1) the + // host driver shall leave this bit + // set to 1. If this bit is set the + // local host shall not write to the + // data register (MMCHS_DATA). 0 + // Transfer mode 1 Stop at block gap +#define MMCHS_HCTL_SDVS_M 0x00000E00 // SD bus voltage select All cards. + // The host driver should set to + // these bits to select the voltage + // level for the card according to + // the voltage supported by the + // system (MMCHS_CAPA[VS18VS30VS33]) + // before starting a transfer. 0x5 + // 1.8V (Typical) 0x6 3.0V (Typical) + // 0x7 3.3V (Typical) +#define MMCHS_HCTL_SDVS_S 9 +#define MMCHS_HCTL_SDBP 0x00000100 // SD bus power Before setting this + // bit the host driver shall select + // the SD bus voltage + // (MMCHS_HCTL[SDVS]). If the host + // controller detects the No card + // state this bit is automatically + // set to 0. If the module is power + // off a write in the command + // register (MMCHS_CMD) will not + // start the transfer. A write to + // this bit has no effect if the + // selected SD bus voltage + // MMCHS_HCTL[SDVS] is not supported + // according to capability register + // (MMCHS_CAPA[VS*]). 0 Power off 1 + // Power on +#define MMCHS_HCTL_CDSS 0x00000080 // Card Detect Signal Selection + // This bit selects source for the + // card detection.When the source + // for the card detection is + // switched the interrupt should be + // disabled during the switching + // period by clearing the Interrupt + // Status/Signal Enable register in + // order to mask unexpected + // interrupt being caused by the + // glitch. The Interrupt + // Status/Signal Enable should be + // disabled during over the period + // of debouncing. 0 SDCD# is + // selected (for normal use) 1 The + // Card Detect Test Level is + // selected (for test purpose) +#define MMCHS_HCTL_CDTL 0x00000040 // Card Detect Test Level: This bit + // is enabled while the Card Detect + // Signal Selection is set to 1 and + // it indicates card inserted or + // not. 0 No Card 1 Card Inserted +#define MMCHS_HCTL_DMAS_M 0x00000018 // DMA Select Mode: One of + // supported DMA modes can be + // selected. The host driver shall + // check support of DMA modes by + // referring the Capabilities + // register. Use of selected DMA is + // determined by DMA Enable of the + // Transfer Mode register. This + // register is only meaningful when + // MADMA_EN is set to 1. When + // MADMA_EN is set to 0 the bit + // field is read only and returned + // value is 0. 0x0 Reserved 0x1 + // Reserved 0x2 32-bit Address ADMA2 + // is selected 0x3 Reserved +#define MMCHS_HCTL_DMAS_S 3 +#define MMCHS_HCTL_HSPE 0x00000004 // High Speed Enable: Before + // setting this bit the Host Driver + // shall check the High Speed + // Support in the Capabilities + // register. If this bit is set to 0 + // (default) the Host Controller + // outputs CMD line and DAT lines at + // the falling edge of the SD Clock. + // If this bit is set to 1 the Host + // Controller outputs CMD line and + // DAT lines at the rising edge of + // the SD Clock.This bit shall not + // be set when dual data rate mode + // is activated in MMCHS_CON[DDR]. 0 + // Normal speed mode 1 High speed + // mode +#define MMCHS_HCTL_DTW 0x00000002 // Data transfer width For MMC card + // this bit must be set following a + // valid SWITCH command (CMD6) with + // the correct value and extend CSD + // index written in the argument. + // Prior to this command the MMC + // card configuration register (CSD + // and EXT_CSD) must be verified for + // compliance with MMC standard + // specification 4.x (see section + // 3.6). This register has no effect + // when the MMC 8-bit mode is + // selected (register MMCHS_CON[DW8] + // set to1 ) For SD/SDIO cards this + // bit must be set following a valid + // SET_BUS_WIDTH command (ACMD6) + // with the value written in bit 1 + // of the argument. Prior to this + // command the SD card configuration + // register (SCR) must be verified + // for the supported bus width by + // the SD card. 0 1-bit Data width + // (DAT[0] used) 1 4-bit Data width + // (DAT[3:0] used) +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSCTL register. +// +//****************************************************************************** +#define MMCHS_SYSCTL_SRD 0x04000000 // Software reset for DAT line This + // bit is set to 1 for reset and + // released to 0 when completed. DAT + // finite state machine in both + // clock domain are also reset. Here + // below are the registers cleared + // by MMCHS_SYSCTL[SRD]: #VALUE! - + // MMCHS_PSTATE: BRE BWE RTA WTA DLA + // and DATI - MMCHS_HCTL: SBGR and + // CR - MMCHS_STAT: BRR BWR BGE and + // TC OCP and MMC buffer data + // management is reinitialized. 0 + // Reset completed 1 Software reset + // for DAT line +#define MMCHS_SYSCTL_SRC 0x02000000 // Software reset for CMD line This + // bit is set to 1 for reset and + // released to 0 when completed. CMD + // finite state machine in both + // clock domain are also reset. Here + // below the registers cleared by + // MMCHS_SYSCTL[SRC]: - + // MMCHS_PSTATE: CMDI - MMCHS_STAT: + // CC OCP and MMC command status + // management is reinitialized. 0 + // Reset completed 1 Software reset + // for CMD line +#define MMCHS_SYSCTL_SRA 0x01000000 // Software reset for all This bit + // is set to 1 for reset and + // released to 0 when completed. + // This reset affects the entire + // host controller except for the + // card detection circuit and + // capabilities registers. 0 Reset + // completed 1 Software reset for + // all the design +#define MMCHS_SYSCTL_DTO_M 0x000F0000 // Data timeout counter value and + // busy timeout. This value + // determines the interval by which + // DAT lines timeouts are detected. + // The host driver needs to set this + // bitfield based on - the maximum + // read access time (NAC) (Refer to + // the SD Specification Part1 + // Physical Layer) - the data read + // access time values (TAAC and + // NSAC) in the card specific data + // register (CSD) of the card - the + // timeout clock base frequency + // (MMCHS_CAPA[TCF]). If the card + // does not respond within the + // specified number of cycles a data + // timeout error occurs + // (MMCHS_STA[DTO]). The + // MMCHS_SYSCTL[DTO] register is + // also used to check busy duration + // to generate busy timeout for + // commands with busy response or + // for busy programming during a + // write command. Timeout on CRC + // status is generated if no CRC + // token is present after a block + // write. 0x0 TCF x 2^13 0x1 TCF x + // 2^14 0xE TCF x 2^27 0xF Reserved +#define MMCHS_SYSCTL_DTO_S 16 +#define MMCHS_SYSCTL_CLKD_M 0x0000FFC0 // Clock frequency select These + // bits define the ratio between a + // reference clock frequency (system + // dependant) and the output clock + // frequency on the CLK pin of + // either the memory card (MMC SD or + // SDIO). 0x000 Clock Ref bypass + // 0x001 Clock Ref bypass 0x002 + // Clock Ref / 2 0x003 Clock Ref / 3 + // 0x3FF Clock Ref / 1023 +#define MMCHS_SYSCTL_CLKD_S 6 +#define MMCHS_SYSCTL_CEN 0x00000004 // Clock enable This bit controls + // if the clock is provided to the + // card or not. 0 The clock is not + // provided to the card . Clock + // frequency can be changed . 1 The + // clock is provided to the card and + // can be automatically gated when + // MMCHS_SYSCONFIG[AUTOIDLE] is set + // to 1 (default value) . The host + // driver shall wait to set this bit + // to 1 until the Internal clock is + // stable (MMCHS_SYSCTL[ICS]). +#define MMCHS_SYSCTL_ICS 0x00000002 +#define MMCHS_SYSCTL_ICE 0x00000001 // Internal clock enable This + // register controls the internal + // clock activity. In very low power + // state the internal clock is + // stopped. Note: The activity of + // the debounce clock (used for + // wakeup events) and the OCP clock + // (used for reads and writes to the + // module register map) are not + // affected by this register. 0 The + // internal clock is stopped (very + // low power state). 1 The internal + // clock oscillates and can be + // automatically gated when + // MMCHS_SYSCONFIG[AUTOIDLE] is set + // to 1 (default value) . +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_STAT register. +// +//****************************************************************************** +#define MMCHS_STAT_BADA 0x20000000 +#define MMCHS_STAT_CERR 0x10000000 +#define MMCHS_STAT_ADMAE 0x02000000 +#define MMCHS_STAT_ACE 0x01000000 +#define MMCHS_STAT_DEB 0x00400000 +#define MMCHS_STAT_DCRC 0x00200000 +#define MMCHS_STAT_DTO 0x00100000 +#define MMCHS_STAT_CIE 0x00080000 +#define MMCHS_STAT_CEB 0x00040000 +#define MMCHS_STAT_CCRC 0x00020000 +#define MMCHS_STAT_CTO 0x00010000 +#define MMCHS_STAT_ERRI 0x00008000 +#define MMCHS_STAT_BSR 0x00000400 +#define MMCHS_STAT_OBI 0x00000200 +#define MMCHS_STAT_CIRQ 0x00000100 +#define MMCHS_STAT_CREM 0x00000080 +#define MMCHS_STAT_CINS 0x00000040 +#define MMCHS_STAT_BRR 0x00000020 +#define MMCHS_STAT_BWR 0x00000010 +#define MMCHS_STAT_DMA 0x00000008 +#define MMCHS_STAT_BGE 0x00000004 +#define MMCHS_STAT_TC 0x00000002 +#define MMCHS_STAT_CC 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_IE register. +// +//****************************************************************************** +#define MMCHS_IE_BADA_ENABLE 0x20000000 // Bad access to data space + // Interrupt Enable 0 Masked 1 + // Enabled +#define MMCHS_IE_CERR_ENABLE 0x10000000 // Card error interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_ADMAE_ENABLE 0x02000000 // ADMA error Interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_ACE_ENABLE 0x01000000 // Auto CMD12 error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DEB_ENABLE 0x00400000 // Data end bit error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DCRC_ENABLE 0x00200000 // Data CRC error Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_DTO_ENABLE 0x00100000 // Data timeout error Interrupt + // Enable 0 The data timeout + // detection is deactivated. The + // host controller provides the + // clock to the card until the card + // sends the data or the transfer is + // aborted. 1 The data timeout + // detection is enabled. +#define MMCHS_IE_CIE_ENABLE 0x00080000 // Command index error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CEB_ENABLE 0x00040000 // Command end bit error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CCRC_ENABLE 0x00020000 // Command CRC error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CTO_ENABLE 0x00010000 // Command timeout error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_NULL 0x00008000 // Fixed to 0 The host driver shall + // control error interrupts using + // the Error Interrupt Signal Enable + // register. Writes to this bit are + // ignored +#define MMCHS_IE_BSR_ENABLE 0x00000400 // Boot status interrupt Enable A + // write to this register when + // MMCHS_CON[BOOT_ACK] is set to 0x0 + // is ignored. 0 Masked 1 Enabled +#define MMCHS_IE_OBI_ENABLE 0x00000200 // Out-of-Band interrupt Enable A + // write to this register when + // MMCHS_CON[OBIE] is set to '0' is + // ignored. 0 Masked 1 Enabled +#define MMCHS_IE_CIRQ_ENABLE 0x00000100 // Card interrupt Enable A clear of + // this bit also clears the + // corresponding status bit. During + // 1-bit mode if the interrupt + // routine doesn't remove the source + // of a card interrupt in the SDIO + // card the status bit is reasserted + // when this bit is set to 1. 0 + // Masked 1 Enabled +#define MMCHS_IE_CREM_ENABLE 0x00000080 // Card removal Interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_CINS_ENABLE 0x00000040 // Card insertion Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_BRR_ENABLE 0x00000020 // Buffer Read Ready Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_BWR_ENABLE 0x00000010 // Buffer Write Ready Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DMA_ENABLE 0x00000008 // DMA interrupt Enable 0 Masked 1 + // Enabled +#define MMCHS_IE_BGE_ENABLE 0x00000004 // Block Gap Event Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_TC_ENABLE 0x00000002 // Transfer completed Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CC_ENABLE 0x00000001 // Command completed Interrupt + // Enable 0 Masked 1 Enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ISE register. +// +//****************************************************************************** +#define MMCHS_ISE_BADA_SIGEN 0x20000000 // Bad access to data space signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CERR_SIGEN 0x10000000 // Card error interrupt signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_ADMAE_SIGEN 0x02000000 // ADMA error signal status Enable + // 0 Masked 1 Enabled +#define MMCHS_ISE_ACE_SIGEN 0x01000000 // Auto CMD12 error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DEB_SIGEN 0x00400000 // Data end bit error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DCRC_SIGEN 0x00200000 // Data CRC error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DTO_SIGEN 0x00100000 // Data timeout error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CIE_SIGEN 0x00080000 // Command index error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CEB_SIGEN 0x00040000 // Command end bit error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CCRC_SIGEN 0x00020000 // Command CRC error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CTO_SIGEN 0x00010000 // Command timeout error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_NULL 0x00008000 // Fixed to 0 The host driver shall + // control error interrupts using + // the Error Interrupt Signal Enable + // register. Writes to this bit are + // ignored +#define MMCHS_ISE_BSR_SIGEN 0x00000400 // Boot status signal status + // EnableA write to this register + // when MMCHS_CON[BOOT_ACK] is set + // to 0x0 is ignored. 0 Masked 1 + // Enabled +#define MMCHS_ISE_OBI_SIGEN 0x00000200 // Out-Of-Band Interrupt signal + // status Enable A write to this + // register when MMCHS_CON[OBIE] is + // set to '0' is ignored. 0 Masked 1 + // Enabled +#define MMCHS_ISE_CIRQ_SIGEN 0x00000100 // Card interrupt signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CREM_SIGEN 0x00000080 // Card removal signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CINS_SIGEN 0x00000040 // Card insertion signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_BRR_SIGEN 0x00000020 // Buffer Read Ready signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_BWR_SIGEN 0x00000010 // Buffer Write Ready signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DMA_SIGEN 0x00000008 // DMA interrupt Signal status + // enable 0 Masked 1 Enabled +#define MMCHS_ISE_BGE_SIGEN 0x00000004 // Black Gap Event signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_TC_SIGEN 0x00000002 // Transfer completed signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CC_SIGEN 0x00000001 // Command completed signal status + // Enable 0 Masked 1 Enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_AC12 register. +// +//****************************************************************************** +#define MMCHS_AC12_CNI 0x00000080 +#define MMCHS_AC12_ACIE 0x00000010 +#define MMCHS_AC12_ACEB 0x00000008 +#define MMCHS_AC12_ACCE 0x00000004 +#define MMCHS_AC12_ACTO 0x00000002 +#define MMCHS_AC12_ACNE 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CAPA register. +// +//****************************************************************************** +#define MMCHS_CAPA_BIT64 0x10000000 +#define MMCHS_CAPA_VS18 0x04000000 +#define MMCHS_CAPA_VS30 0x02000000 +#define MMCHS_CAPA_VS33 0x01000000 +#define MMCHS_CAPA_SRS 0x00800000 +#define MMCHS_CAPA_DS 0x00400000 +#define MMCHS_CAPA_HSS 0x00200000 +#define MMCHS_CAPA_AD2S 0x00080000 +#define MMCHS_CAPA_MBL_M 0x00030000 +#define MMCHS_CAPA_MBL_S 16 +#define MMCHS_CAPA_BCF_M 0x00003F00 +#define MMCHS_CAPA_BCF_S 8 +#define MMCHS_CAPA_TCU 0x00000080 +#define MMCHS_CAPA_TCF_M 0x0000003F +#define MMCHS_CAPA_TCF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register. +// +//****************************************************************************** +#define MMCHS_CUR_CAPA_CUR_1V8_M \ + 0x00FF0000 + +#define MMCHS_CUR_CAPA_CUR_1V8_S 16 +#define MMCHS_CUR_CAPA_CUR_3V0_M \ + 0x0000FF00 + +#define MMCHS_CUR_CAPA_CUR_3V0_S 8 +#define MMCHS_CUR_CAPA_CUR_3V3_M \ + 0x000000FF + +#define MMCHS_CUR_CAPA_CUR_3V3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_FE register. +// +//****************************************************************************** +#define MMCHS_FE_FE_BADA 0x20000000 +#define MMCHS_FE_FE_CERR 0x10000000 +#define MMCHS_FE_FE_ADMAE 0x02000000 +#define MMCHS_FE_FE_ACE 0x01000000 +#define MMCHS_FE_FE_DEB 0x00400000 +#define MMCHS_FE_FE_DCRC 0x00200000 +#define MMCHS_FE_FE_DTO 0x00100000 +#define MMCHS_FE_FE_CIE 0x00080000 +#define MMCHS_FE_FE_CEB 0x00040000 +#define MMCHS_FE_FE_CCRC 0x00020000 +#define MMCHS_FE_FE_CTO 0x00010000 +#define MMCHS_FE_FE_CNI 0x00000080 +#define MMCHS_FE_FE_ACIE 0x00000010 +#define MMCHS_FE_FE_ACEB 0x00000008 +#define MMCHS_FE_FE_ACCE 0x00000004 +#define MMCHS_FE_FE_ACTO 0x00000002 +#define MMCHS_FE_FE_ACNE 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ADMAES register. +// +//****************************************************************************** +#define MMCHS_ADMAES_LME 0x00000004 // ADMA Length Mismatch Error: (1) + // While Block Count Enable being + // set the total data length + // specified by the Descriptor table + // is different from that specified + // by the Block Count and Block + // Length. (2) Total data length can + // not be divided by the block + // length. 0 No Error 1 Error +#define MMCHS_ADMAES_AES_M 0x00000003 // ADMA Error State his field + // indicates the state of ADMA when + // error is occurred during ADMA + // data transfer. "This field never + // indicates ""10"" because ADMA + // never stops in this state." 0x0 + // ST_STOP (Stop DMA)Contents of + // SYS_SDR register 0x1 ST_STOP + // (Stop DMA)Points the error + // descriptor 0x2 Never set this + // state(Not used) 0x3 ST_TFR + // (Transfer Data)Points the next of + // the error descriptor +#define MMCHS_ADMAES_AES_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ADMASAL register. +// +//****************************************************************************** +#define MMCHS_ADMASAL_ADMA_A32B_M \ + 0xFFFFFFFF // ADMA System address 32 bits.This + // register holds byte address of + // executing command of the + // Descriptor table. 32-bit Address + // Descriptor uses lower 32-bit of + // this register. At the start of + // ADMA the Host Driver shall set + // start address of the Descriptor + // table. The ADMA increments this + // register address which points to + // next line when every fetching a + // Descriptor line. When the ADMA + // Error Interrupt is generated this + // register shall hold valid + // Descriptor address depending on + // the ADMA state. The Host Driver + // shall program Descriptor Table on + // 32-bit boundary and set 32-bit + // boundary address to this + // register. ADMA2 ignores lower + // 2-bit of this register and + // assumes it to be 00b. + +#define MMCHS_ADMASAL_ADMA_A32B_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_REV register. +// +//****************************************************************************** +#define MMCHS_REV_VREV_M 0xFF000000 // Vendor Version Number: IP + // revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 +#define MMCHS_REV_VREV_S 24 +#define MMCHS_REV_SREV_M 0x00FF0000 +#define MMCHS_REV_SREV_S 16 +#define MMCHS_REV_SIS 0x00000001 // Slot Interrupt Status This + // status bit indicates the inverted + // state of interrupt signal for the + // module. By a power on reset or by + // setting a software reset for all + // (MMCHS_HCTL[SRA]) the interrupt + // signal shall be de-asserted and + // this status shall read 0. + + + +#endif // __HW_MMCHS_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_nvic.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_nvic.h new file mode 100644 index 000000000..968fc36fc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_nvic.h @@ -0,0 +1,1712 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg + +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable +#define NVIC_EN5 0xE000E114 // Interrupt 160-191 Set Enable + +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable + +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable +#define NVIC_DIS5 0xE000E194 // Interrupt 160-191 Clear Enable + +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending + +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending +#define NVIC_PEND5 0xE000E214 // Interrupt 160-191 Set Pending + +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending + +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending +#define NVIC_UNPEND5 0xE000E294 // Interrupt 160-191 Clear Pending + +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit + +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit +#define NVIC_ACTIVE5 0xE000E314 // Interrupt 160-191 Active Bit + +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority + +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority +#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority +#define NVIC_PRI35 0xE000E48C // Interrupt 140-143 Priority +#define NVIC_PRI36 0xE000E490 // Interrupt 144-147 Priority +#define NVIC_PRI37 0xE000E494 // Interrupt 148-151 Priority +#define NVIC_PRI38 0xE000E498 // Interrupt 152-155 Priority +#define NVIC_PRI39 0xE000E49C // Interrupt 156-159 Priority +#define NVIC_PRI40 0xE000E4A0 // Interrupt 160-163 Priority +#define NVIC_PRI41 0xE000E4A4 // Interrupt 164-167 Priority +#define NVIC_PRI42 0xE000E4A8 // Interrupt 168-171 Priority +#define NVIC_PRI43 0xE000E4AC // Interrupt 172-175 Priority +#define NVIC_PRI44 0xE000E4B0 // Interrupt 176-179 Priority +#define NVIC_PRI45 0xE000E4B4 // Interrupt 180-183 Priority +#define NVIC_PRI46 0xE000E4B8 // Interrupt 184-187 Priority +#define NVIC_PRI47 0xE000E4BC // Interrupt 188-191 Priority +#define NVIC_PRI48 0xE000E4C0 // Interrupt 192-195 Priority + + + +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable + +#undef NVIC_EN1_INT_M +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable + +#undef NVIC_DIS1_INT_M +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending + +#undef NVIC_PEND1_INT_M +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending + +#undef NVIC_UNPEND1_INT_M +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active + +#undef NVIC_ACTIVE1_INT_M +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor + +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor + +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number + +#undef NVIC_INT_CTRL_VEC_PEN_M +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number + +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number + +#undef NVIC_INT_CTRL_VEC_ACT_M +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number + +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset + +#undef NVIC_VTABLE_OFFSET_M +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset + +#define NVIC_VTABLE_OFFSET_S 9 + +#undef NVIC_VTABLE_OFFSET_S +#define NVIC_VTABLE_OFFSET_S 10 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid + +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation + +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid + +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation + +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID + +#undef NVIC_SW_TRIG_INTID_M +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID + +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_ocp_shared.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_ocp_shared.h new file mode 100644 index 000000000..d9c720003 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_ocp_shared.h @@ -0,0 +1,3447 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_OCP_SHARED_H__ +#define __HW_OCP_SHARED_H__ + +//***************************************************************************** +// +// The following are defines for the OCP_SHARED register offsets. +// +//***************************************************************************** +#define OCP_SHARED_O_SEMAPHORE1 0x00000000 +#define OCP_SHARED_O_SEMAPHORE2 0x00000004 +#define OCP_SHARED_O_SEMAPHORE3 0x00000008 +#define OCP_SHARED_O_SEMAPHORE4 0x0000000C +#define OCP_SHARED_O_SEMAPHORE5 0x00000010 +#define OCP_SHARED_O_SEMAPHORE6 0x00000014 +#define OCP_SHARED_O_SEMAPHORE7 0x00000018 +#define OCP_SHARED_O_SEMAPHORE8 0x0000001C +#define OCP_SHARED_O_SEMAPHORE9 0x00000020 +#define OCP_SHARED_O_SEMAPHORE10 \ + 0x00000024 + +#define OCP_SHARED_O_SEMAPHORE11 \ + 0x00000028 + +#define OCP_SHARED_O_SEMAPHORE12 \ + 0x0000002C + +#define OCP_SHARED_O_IC_LOCKER_ID \ + 0x00000030 + +#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \ + 0x00000034 + +#define OCP_SHARED_O_WL_SEMAPHORE_PEND \ + 0x00000038 + +#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \ + 0x0000003C + +#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \ + 0x00000040 + +#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \ + 0x00000044 + +#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \ + 0x00000048 + +#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \ + 0x0000004C + +#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \ + 0x00000050 + +#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \ + 0x00000054 + +#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \ + 0x00000058 + +#define OCP_SHARED_O_SSBD_SEED 0x0000005C +#define OCP_SHARED_O_SSBD_CHK 0x00000060 +#define OCP_SHARED_O_SSBD_POLY_SEL \ + 0x00000064 + +#define OCP_SHARED_O_SPARE_REG_0 \ + 0x00000068 + +#define OCP_SHARED_O_SPARE_REG_1 \ + 0x0000006C + +#define OCP_SHARED_O_SPARE_REG_2 \ + 0x00000070 + +#define OCP_SHARED_O_SPARE_REG_3 \ + 0x00000074 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \ + 0x000000A0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \ + 0x000000A4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \ + 0x000000A8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \ + 0x000000AC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \ + 0x000000B0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \ + 0x000000B4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \ + 0x000000B8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \ + 0x000000BC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \ + 0x000000C0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \ + 0x000000C4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \ + 0x000000C8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \ + 0x000000CC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \ + 0x000000D0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \ + 0x000000D4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \ + 0x000000D8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \ + 0x000000DC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \ + 0x000000E0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \ + 0x000000E4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \ + 0x000000E8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \ + 0x000000EC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \ + 0x000000F0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \ + 0x000000F4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \ + 0x000000F8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \ + 0x000000FC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \ + 0x00000100 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \ + 0x00000104 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \ + 0x00000108 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \ + 0x0000010C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \ + 0x00000110 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \ + 0x00000114 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \ + 0x00000118 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \ + 0x0000011C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \ + 0x00000120 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \ + 0x00000124 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \ + 0x00000128 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \ + 0x0000012C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \ + 0x00000130 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \ + 0x00000134 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \ + 0x00000138 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \ + 0x0000013C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \ + 0x00000140 + +#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \ + 0x00000144 // This register provide control to + // GPIO_CC3XXV1 IO PAD. Common + // control signals to all bottom Die + // IO's are controlled via this. + +#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \ + 0x00000148 + +#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \ + 0x0000014C + +#define OCP_SHARED_O_D2D_MISC_PAD_CONF \ + 0x00000150 + +#define OCP_SHARED_O_SOP_CONF_OVERRIDE \ + 0x00000154 + +#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \ + 0x00000158 + +#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \ + 0x0000015C + +#define OCP_SHARED_O_ALT_PC_VAL_NW \ + 0x00000160 + +#define OCP_SHARED_O_ALT_PC_VAL_APPS \ + 0x00000164 + +#define OCP_SHARED_O_SPARE_REG_4 \ + 0x00000168 + +#define OCP_SHARED_O_SPARE_REG_5 \ + 0x0000016C + +#define OCP_SHARED_O_SH_SPI_CS_MASK \ + 0x00000170 + +#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \ + 0x00000174 + +#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \ + 0x00000178 + +#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \ + 0x0000017C + +#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \ + 0x00000180 + +#define OCP_SHARED_O_CC3XX_DEV_PADCONF \ + 0x00000184 + +#define OCP_SHARED_O_SPARE_REG_8 \ + 0x00000188 + +#define OCP_SHARED_O_SPARE_REG_6 \ + 0x0000018C + +#define OCP_SHARED_O_SPARE_REG_7 \ + 0x00000190 + +#define OCP_SHARED_O_APPS_WLAN_ORBIT \ + 0x00000194 + +#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \ + 0x00000198 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE1 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE2 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE3 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE4 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE5 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE6 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE7 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE8 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE9 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE10 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE11 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE12 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_IC_LOCKER_ID register. +// +//****************************************************************************** +#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \ + 0x00000007 // This register is used for + // allowing only one master OCP to + // perform write transactions to the + // OCP slaves. Each bit represents + // an IP in the following format: { + // JTAG,WLAN, NWP mcu}. As any of + // the bits is set to one, the + // correlating IP is preventing the + // other IP's from performing write + // transactions to the slaves. As + // the Inter Connect is locked, the + // only the locking IP can write to + // the register and by that + // releasing the lock. 3'b000 => IC + // is not locked. 3'b001 => IC is + // locked by NWP mcu. 3'b010 => IC + // is locked by WLAN. 3'b100 => IC + // is locked by JTAG. + +#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_MCU_SEMAPHORE_PEND register. +// +//****************************************************************************** +#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \ + 0x0000FFFF // This register specifies the + // semaphore for which the NWP mcu + // is waiting to be released. It is + // set to the serial number of a + // given locked semaphore after it + // was read by the NWP mcu. Only + // [11:0] is used. + +#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_WL_SEMAPHORE_PEND register. +// +//****************************************************************************** +#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \ + 0x0000FFFF // This register specifies the + // semaphore for which the WLAN is + // waiting to be released. It is set + // to the serial number of a given + // locked semaphore after it was + // read by the WLAN. Only [11:0] is + // used. + +#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register. +// +//****************************************************************************** +#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \ + 0x0000FFFF // This information serves the IPs + // for knowing in which platform are + // they integrated at: 0 = CC31XX. + +#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \ + 0x00000FFF // Captured/released semaphores + // status for the 12 semaphores. + // Each bit of the 12 bits + // represents a semaphore. 0 => + // Semaphore Free. 1 => Semaphore + // Captured. + +#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_CONFIG_CTRL register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \ + 0x00000010 // This bit is used to enable + // timeout mechanism for top_ocp_ic + // (for debug puropse). When 1 value + // , in case any ocp slave doesn't + // give sresponse within 16 cylcles + // top_ic will give error response + // itself to avoid bus hange. + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \ + 0x00000008 // 1 bit should be accessible only + // in devinit. This will enable 0x4 + // hack for apps processor + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \ + 0x00000004 // 1 bit, should be accessible only + // in devinit. This will enable 0x4 + // hack for nw processor + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \ + 0x00000002 // When set NW can take over apps + // rom and flash via IDCODE bus. + // Apps will able to access this + // register only during devinit and + // reset value should be 0. + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \ + 0x00000001 // When this bit is set to 0 WPSI + // host interface wil be selected, + // when this bit is set to 1 , WLAN + // host async bridge will be + // selected. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \ + 0x3FFFFFFF // This register provides memss RAM + // column configuration for column 0 + // to 9. 3 bits are allocated per + // column. This register is required + // to be configured before starting + // RAM access. Changing register + // setting while code is running + // will result into unpredictable + // memory behaviour. Register is + // supported to configured ones + // after core is booted up. 3 bit + // encoding per column is as + // follows: when 000 : WLAN, 001: + // NWP, 010: APPS, 011: PHY, 100: + // OCLA column 0 select: bit [2:0] + // :when 000 -> WLAN,001 -> NWP,010 + // -> APPS, 011 -> PHY, 100 -> OCLA + // column 1 select: bit [5:3] + // :column 2 select: bit [8 : 6]: + // column 3 select : bit [11: 9] + // column 4 select : bit [14:12] + // column 5 select : bit [17:15] + // column 6 select : bit [20:18] + // column 7 select : bit [23:21] + // column 8 select : bit [26:24] + // column 9 select : bit [29:27] + // column 10 select + +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \ + 0x00000FFF // This register provides memss RAM + // column configuration for column + // 10 to 15. 3 bits are allocated + // per column. This register is + // required to be configured before + // starting RAM access. Changing + // register setting while code is + // running will result into + // unpredictable memory behaviour. + // Register is supported to + // configured ones after core is + // booted up. 3 bit encoding per + // column is as follows: when 000 : + // WLAN, 001: NWP, 010: APPS, 011: + // PHY, 100: OCLA column 11 select : + // bit [2:0] column 12 select : bit + // [5:3] column 13 select : bit [8 : + // 6] column 14 select : + +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_WLAN_ELP_WAKE_EN register. +// +//****************************************************************************** +#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \ + 0x00000001 // when '1' : signal will enabled + // ELP power doamin when '0': ELP is + // not powered up. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register. +// +//****************************************************************************** +#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. This register is not used + // , similar register availble in + // GPRCM space. + +#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register. +// +//****************************************************************************** +#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_SEED register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_CHK register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_POLY_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \ + 0x00000003 // 2 bit, Writable only during + // devinit, and whole 2 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_0 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \ + 0xFFFFFFFF // Devinit code should look for + // whether corresponding fuse is + // blown and if blown write to the + // 11th bit of this register to + // disable flshtst interface + +#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_1 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_2 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_3 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \ + 0xFFFFFFFF // APPS Software register + +#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." "For example in + // case of I2C Value gets latched at + // rising edge of RET33.""" """ 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_2 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_3 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_4 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_5 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_6 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_7 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_8 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_9 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_10 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_11 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_12 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_13 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_14 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_15 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_16 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_17 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_18 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_19 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_20 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_21 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_22 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_23 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_24 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_25 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_26 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_27 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_28 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_29 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_30 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_31 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_32 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_33 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_34 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_35 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_36 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_37 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_38 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_39 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_40 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \ + 0x0007FFFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." "For example in + // case of I2C Value gets latched at + // rising edge of RET33.""" """ 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \ + 0x00000080 // when '1' enable ISO A control to + // D2D Pads else ISO is disabled. + // For these PADS to be functional + // this signals should be set 0. + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \ + 0x00000040 // when '1' enable ISO Y control to + // D2D Pads else ISO is disabled. + // For these PADS to be functional + // this signals should be set 0. + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \ + 0x00000020 // If level ‘1’ enables the PAD to + // ODI path for JTAG PADS [PAD 23, + // 24, 28, 29]. Else ODI is pulled + // ‘Low’ regardless of PAD level." + // "Value gets latched at rising + // edge of RET33.""" """ + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \ + 0x00000018 // 00’: hysteriris = 10% of VDDS + // (difference between upper and + // lower threshold of the schmit + // trigger) ‘01’: hysteriris = 20% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger) ‘10’: hysteriris = 30% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger) ‘11’: hysteriris = 40% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger)" """ + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3 +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \ + 0x00000004 // If logic ‘0’ there is no + // hysteresis. Set to ‘1’ to enable + // hysteresis. Leave the choice to + // customers""" + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \ + 0x00000002 // Normal functional operation set + // this to logic ‘1’ to increase the + // speed of the o/p buffer at the + // cost of 0.2uA static current + // consumption per IO. During IDDQ + // test and during Hibernate this + // would be forced to logic ‘0’. + // Value is not latched at rising + // edge of RET33."" + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \ + 0x00000001 // If level ‘1’ enables the PAD to + // ODI path. Else ODI is pulled + // ‘Low’ regardless of PAD level." + // "Value gets latched at rising + // edge of RET33.""" """ + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \ + 0x0000003F // this register implements common + // IO control to all devement mode + // PADs; these PADs are DEV_PAD33 to + // DEV_PAD39. Bit [1:0] : Drive + // strength control. These 2 bits + // are connected to DEV PAD drive + // strength control. possible drive + // stregnths are 2MA, 4MA and 6 MA + // for the these IO's. bit 0: when + // set to logic value '1' enable 2MA + // drive strength for DEVPAD01 to 07 + // bit 1: when set to logic value + // '1' enable 4MA drive strength for + // DEVPAD01 to 07. bit[3:2] : WK + // PULL UP and PULL down control. + // These 2 bits provide IWKPUEN and + // IWKPDEN control for all DEV IO's. + // bit 2: when set to logic value + // '1' enable WKPU to DEVPAD01 to 07 + // bit 3: when set to logic value + // '1' enable WKPD to DEVPAD01 to + // 07. bit 4: WK PULL control for + // DEV_PKG_DETECT pin. when '1' + // pullup enabled else it is + // disable. bit 5: when set to logic + // value '1' enable 8MA drive + // strength for DEVPAD01 to 07. + +#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \ + 0x1FFFFFFF // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + // this register control OEN2X pin + // of D2D TOSTACK PAD: OEN1X and + // OEN2X decoding is as follows: + // "when ""00"" :" "when ""01"" : + // dirve strength is '1' and output + // buffer enabled." "when ""10"" : + // drive strength is 2 and output + // buffer is disabled." "when ""11"" + // : dirve strength is '3' and + // output buffer enabled." + +#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_MISC_PAD_CONF register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \ + 0x00000200 // This register provide OEN2X + // control to D2D PADS OEN/OEN2X + // control. When 0 : Act as input + // buffer else output buffer with + // drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \ + 0x00000100 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \ + 0x00000080 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \ + 0x00000040 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \ + 0x00000020 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \ + 0x00000010 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \ + 0x00000008 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \ + 0x00000007 // D2D SPARE PAD OEN/OEN2X control. + // When 0: Act as input buffer else + // output buffer with drive strength + // 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SOP_CONF_OVERRIDE register. +// +//****************************************************************************** +#define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \ + 0x00000001 // when '1' : signal will ovberride + // SoP setting of JTAG PADS. when + // '0': SoP setting will control + // JTAG PADs [ TDI, TDO, TMS, TCK] + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \ + 0x00000020 // This register contains debug + // subsystem status bits From APPS + // MCU status bit to indicates + // whether serial wire or 4 pins + // jtag select. + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \ + 0x00000010 // cjtag bypass bit select + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \ + 0x00000008 // serial wire interface bit select + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \ + 0x00000004 // apps tap enable status + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \ + 0x00000002 // tap enable status + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \ + 0x00000001 // ssbd unlock status + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \ + 0x0000FFFF // debug mux select register. Upper + // 8 bits are used for debug module + // selection. Lower 8 bit [7:0] used + // inside debug module for selecting + // module specific signals. + // Bits[15:8: when set x"00" : GPRCM + // debug bus. When "o1" : SDIO debug + // debug bus when x"02" : + // autonoumous SPI when x"03" : + // TOPIC when x"04": memss when + // x"25": mcu debug bus : APPS debug + // when x"45": mcu debug bus : NWP + // debug when x"65": mcu debug bus : + // AHB2VBUS debug when x"85": mcu + // debug bus : VBUS2HAB debug when + // x"95": mcu debug bus : RCM debug + // when x"A5": mcu debug bus : + // crypto debug when x"06": WLAN + // debug bus when x"07": debugss bus + // when x"08": ADC debug when x"09": + // SDIO PHY debug bus then "others" + // : no debug is selected + +#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_ALT_PC_VAL_NW register. +// +//****************************************************************************** +#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \ + 0xFFFFFFFF // 32 bit. Program counter value + // for 0x4 address when Alt_pc_en_nw + // is set. + +#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_ALT_PC_VAL_APPS register. +// +//****************************************************************************** +#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \ + 0xFFFFFFFF // 32 bit. Program counter value + // for 0x4 address when + // Alt_pc_en_apps is set + +#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_4 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \ + 0xFFFFFFFE // HW register + +#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1 +#define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \ + 0x00000001 // Data to the top die launched at + // negative edge instead of positive + // edge. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_5 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \ + 0xFFFFFFFF // HW register + +#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SH_SPI_CS_MASK register. +// +//****************************************************************************** +#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \ + 0x0000000F // ( chip select 0 is unmasked + // after reset. When ‘1’ : CS is + // unmasked or else masked. Valid + // configurations are 1000, 0100, + // 0010 or 0001. Any other setting + // can lead to unpredictable + // behavior. + +#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEVICE_TYPE register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \ + 0x00000060 // reserved bits tied off "00". + +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5 +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \ + 0x0000001F // CC3XX Device type information. + +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register. +// +//****************************************************************************** +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \ + 0x000000F0 // [4] 1: switch between + // WLAN_I2C_SCL and + // TOP_GPIO_PORT4_I2C closes 0: + // switch opens [5] 1: switch + // between WLAN_I2C_SCL and + // TOP_VSENSE_PORT closes 0: switch + // opens [6] 1: switch between + // WLAN_I2C_SCL and WLAN_ANA_TP4 + // closes 0: switch opens [7] + // Reserved + +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4 +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \ + 0x0000000F // [0] 1: switch between + // WLAN_I2C_SDA and + // TOP_GPIO_PORT3_I2C closes 0: + // switch opens [1] 1: switch + // between WLAN_I2C_SDA and + // TOP_IFORCE_PORT closes 0: switch + // opens [2] 1: switch between + // WLAN_I2C_SDA and WLAN_ANA_TP3 + // closes 0: switch opens [3] + // Reserved + +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \ + 0x00000001 // when '0' indicates package type + // is development. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_AUTONMS_SPICLK_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \ + 0x00000002 // This bit is used to bypass MCPSI + // autonomous mode .if this bit is 1 + // autonomous MCSPI logic will be + // bypassed and it will act as link + // SPI + +#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \ + 0x00000001 // This bit is used in SPI + // Autonomous mode to switch clock + // from system clock to SPI clk that + // is coming from PAD. When value 1 + // PAD SPI clk is used as system + // clock in LPDS mode by SPI as well + // as autonomous wrapper logic. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEV_PADCONF register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \ + 0x0000FFFF + +#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_IDMEM_TIM_UPDATE register. +// +//****************************************************************************** +#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \ + 0xFFFFFFFF + +#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_6 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_7 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_APPS_WLAN_ORBIT register. +// +//****************************************************************************** +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \ + 0xFFFFFC00 // Spare bit + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10 +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \ + 0x00000200 // A rising edge on this bit + // indicates that the test case + // passes. This bit would be brought + // out on the pin interface during + // ORBIT. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \ + 0x00000100 // This register bit is writable by + // the FW and when set to 1 it + // indicates the start of a test + // execution. A failing edge on this + // bit indicates that the test + // execution is complete. This bit + // would be brought out on the pin + // interface during ORBIT. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \ + 0x000000FC // Implies the test case ID that + // needs to run. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2 +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \ + 0x00000002 // This bit is used to trigger the + // execution of test cases within + // the (ROM based) IP. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \ + 0x00000001 // When this bit is 1 it implies + // ORBIT mode of operation and the + // (ROM based) IP start the + // execution from a test case + // perspective + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register. +// +//****************************************************************************** +#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \ + 0xFFFFFFFF // scratch pad register. + +#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0 + + + +#endif // __HW_OCP_SHARED_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_shamd5.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_shamd5.h new file mode 100644 index 000000000..cefe9fc59 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_shamd5.h @@ -0,0 +1,1244 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_SHAMD5_H__ +#define __HW_SHAMD5_H__ + +//***************************************************************************** +// +// The following are defines for the SHAMD5_P register offsets. +// +//***************************************************************************** +#define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for + // MD5 [159:128] for SHA-1 [255:224] + // for SHA-2 / HMAC Key [31:0] for + // HMAC key proc READ: Outer Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 +#define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for + // MD5 [127:96] for SHA-1 [223:192] + // for SHA-2 / HMAC Key [63:32] for + // HMAC key proc READ: Outer Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 +#define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for + // MD5 [95:64] for SHA-1 [191:160] + // for SHA-2 / HMAC Key [95:64] for + // HMAC key proc READ: Outer Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA-2 +#define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for + // MD5 [63:31] for SHA-1 [159:128] + // for SHA-2 / HMAC Key [127:96] for + // HMAC key proc READ: Outer Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 +#define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for + // SHA-1 [127:96] for SHA-2 / HMAC + // Key [159:128] for HMAC key proc + // READ: Outer Digest [31:0] for + // SHA-1 [127:96] for SHA-2 +#define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for + // SHA-2 / HMAC Key [191:160] for + // HMAC key proc READ: Outer Digest + // [95:64] for SHA-2 +#define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for + // SHA-2 / HMAC Key [223:192] for + // HMAC key proc READ: Outer Digest + // [63:32] for SHA-2 +#define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for + // SHA-2 / HMAC Key [255:224] for + // HMAC key proc READ: Outer Digest + // [31:0] for SHA-2 +#define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 / HMAC + // Key [287:256] for HMAC key proc + // READ: Intermediate / Inner Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 / + // Result Digest/MAC [127:96] for + // MD5 [159:128] for SHA-1 [223:192] + // for SHA-2 224 [255:224] for SHA-2 + // 256 +#define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 / HMAC + // Key [319:288] for HMAC key proc + // READ: Intermediate / Inner Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 / + // Result Digest/MAC [95:64] for MD5 + // [127:96] for SHA-1 [191:160] for + // SHA-2 224 [223:192] for SHA-2 256 +#define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA- 2 / HMAC Key + // [351:320] for HMAC key proc READ: + // Intermediate / Inner Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA-2 / Result + // Digest/MAC [63:32] for MD5 + // [95:64] for SHA-1 [159:128] for + // SHA-2 224 [191:160] for SHA-2 256 +#define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 / HMAC Key + // [383:352] for HMAC key proc READ: + // Intermediate / Inner Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 / Result + // Digest/MAC [31:0] for MD5 [63:32] + // for SHA-1 [127:96] for SHA-2 224 + // [159:128] for SHA-2 256 +#define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest + // [31:0] for SHA-1 [127:96] for + // SHA-2 / HMAC Key [415:384] for + // HMAC key proc READ: Intermediate + // / Inner Digest [31:0] for SHA-1 + // [127:96] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-1 + // [95:64] for SHA-2 224 [127:96] + // for SHA-2 256 +#define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest + // [95:64] for SHA-2 / HMAC Key + // [447:416] for HMAC key proc READ: + // Intermediate / Inner Digest + // [95:64] for SHA-2 / Result + // Digest/MAC [63:32] for SHA-2 224 + // [95:64] for SHA-2 256 +#define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest + // [63:32] for SHA-2 / HMAC Key + // [479:448] for HMAC key proc READ: + // Intermediate / Inner Digest + // [63:32] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-2 224 + // [63:32] for SHA-2 256 +#define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest + // [31:0] for SHA-2 / HMAC Key + // [511:480] for HMAC key proc READ: + // Intermediate / Inner Digest + // [31:0] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-2 256 +#define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count + // ([31:6] only [5:0] assumed 0) + // READ: Result / IntermediateDigest + // Count The initial digest byte + // count for hash/HMAC continue + // operations (HMAC Key Processing = + // 0 and Use Algorithm Constants = + // 0) on the Secure World must be + // written to this register prior to + // starting the operation by writing + // to S_HASH_MODE. When either HMAC + // Key Processing is 1 or Use + // Algorithm Constants is 1 this + // register does not need to be + // written it will be overwritten + // with 64 (1 hash block of key XOR + // ipad) or 0 respectively + // automatically. When starting a + // HMAC operation from pre-computes + // (HMAC Key Processing is 0) then + // the value 64 must be written here + // to compensate for the appended + // key XOR ipad block. Note that the + // value written should always be a + // 64 byte multiple the lower 6 bits + // written are ignored. The updated + // digest byte count (initial digest + // byte count + bytes processed) can + // be read from this register when + // the status register indicates + // that the operation is done or + // suspended due to a context switch + // request or when a Secure World + // context out DMA is requested. In + // Advanced DMA mode when not + // suspended with a partial result + // reading the SHAMD5_DIGEST_COUNT + // register triggers the Hash/HMAC + // Engine to start the next context + // input DMA. Therefore reading the + // SHAMD5_DIGEST_COUNT register + // should always be the last + // context-read action if not + // suspended with a partial result + // (i.e. PartHashReady interrupt not + // pending). +#define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE +#define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining + // Byte Count (bytes) READ: + // Remaining Byte Count. The value + // programmed MUST be a 64-byte + // multiple if Close Hash is set to + // 0. This register is also the + // trigger to start processing: once + // this register is written the core + // will commence requesting input + // data via DMA or IRQ (if + // programmed length > 0) and start + // processing. The remaining byte + // count for the active operation + // can be read from this register + // when the interrupt status + // register indicates that the + // operation is suspended due to a + // context switch request. +#define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0 +#define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1 +#define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2 +#define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3 +#define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4 +#define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5 +#define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6 +#define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7 +#define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8 +#define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9 +#define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10 +#define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11 +#define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12 +#define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13 +#define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14 +#define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15 +#define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV +#define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG +#define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS +#define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS +#define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The + // SHAMD5_IRQENABLE register contains + // an enable bit for each unique + // interrupt for the public side. An + // interrupt is enabled when both + // the global enable in + // SHAMD5_SYSCONFIG (PIT_en) and the + // bit in this register are both set + // to 1. An interrupt that is + // enabled is propagated to the + // SINTREQUEST_P output. Please note + // that the dedicated partial hash + // output (SINTREQUEST_PART_P) is + // not affected by this register it + // is only affected by the global + // enable SHAMD5_SYSCONFIG (PIT_en). +#define SHAMD5_O_HASH512_ODIGEST_A \ + 0x00000200 + +#define SHAMD5_O_HASH512_ODIGEST_B \ + 0x00000204 + +#define SHAMD5_O_HASH512_ODIGEST_C \ + 0x00000208 + +#define SHAMD5_O_HASH512_ODIGEST_D \ + 0x0000020C + +#define SHAMD5_O_HASH512_ODIGEST_E \ + 0x00000210 + +#define SHAMD5_O_HASH512_ODIGEST_F \ + 0x00000214 + +#define SHAMD5_O_HASH512_ODIGEST_G \ + 0x00000218 + +#define SHAMD5_O_HASH512_ODIGEST_H \ + 0x0000021C + +#define SHAMD5_O_HASH512_ODIGEST_I \ + 0x00000220 + +#define SHAMD5_O_HASH512_ODIGEST_J \ + 0x00000224 + +#define SHAMD5_O_HASH512_ODIGEST_K \ + 0x00000228 + +#define SHAMD5_O_HASH512_ODIGEST_L \ + 0x0000022C + +#define SHAMD5_O_HASH512_ODIGEST_M \ + 0x00000230 + +#define SHAMD5_O_HASH512_ODIGEST_N \ + 0x00000234 + +#define SHAMD5_O_HASH512_ODIGEST_O \ + 0x00000238 + +#define SHAMD5_O_HASH512_ODIGEST_P \ + 0x0000023C + +#define SHAMD5_O_HASH512_IDIGEST_A \ + 0x00000240 + +#define SHAMD5_O_HASH512_IDIGEST_B \ + 0x00000244 + +#define SHAMD5_O_HASH512_IDIGEST_C \ + 0x00000248 + +#define SHAMD5_O_HASH512_IDIGEST_D \ + 0x0000024C + +#define SHAMD5_O_HASH512_IDIGEST_E \ + 0x00000250 + +#define SHAMD5_O_HASH512_IDIGEST_F \ + 0x00000254 + +#define SHAMD5_O_HASH512_IDIGEST_G \ + 0x00000258 + +#define SHAMD5_O_HASH512_IDIGEST_H \ + 0x0000025C + +#define SHAMD5_O_HASH512_IDIGEST_I \ + 0x00000260 + +#define SHAMD5_O_HASH512_IDIGEST_J \ + 0x00000264 + +#define SHAMD5_O_HASH512_IDIGEST_K \ + 0x00000268 + +#define SHAMD5_O_HASH512_IDIGEST_L \ + 0x0000026C + +#define SHAMD5_O_HASH512_IDIGEST_M \ + 0x00000270 + +#define SHAMD5_O_HASH512_IDIGEST_N \ + 0x00000274 + +#define SHAMD5_O_HASH512_IDIGEST_O \ + 0x00000278 + +#define SHAMD5_O_HASH512_IDIGEST_P \ + 0x0000027C + +#define SHAMD5_O_HASH512_DIGEST_COUNT \ + 0x00000280 + +#define SHAMD5_O_HASH512_MODE 0x00000284 +#define SHAMD5_O_HASH512_LENGTH 0x00000288 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_DIGEST_COUNT register. +// +//****************************************************************************** +#define SHAMD5_DIGEST_COUNT_DATA_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DIGEST_COUNT_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_MODE register. +// +//****************************************************************************** +#define SHAMD5_MODE_HMAC_OUTER_HASH \ + 0x00000080 // The HMAC Outer Hash is performed + // on the hash digest when the inner + // hash hash finished (block length + // exhausted and final hash + // performed if close_hash is 1). + // This bit should normally be set + // together with close_hash to + // finish the inner hash first or + // Block Length should be zero (HMAC + // continue with the just outer hash + // to be done). Auto cleared + // internally when outer hash + // performed. 0 No operation 1 hmac + // processing + +#define SHAMD5_MODE_HMAC_KEY_PROC \ + 0x00000020 // Performs HMAC key processing on + // the 512 bit HMAC key loaded into + // the SHAMD5_IDIGEST_{A to H} and + // SHAMD5_ODIGEST_{A to H} register + // block. Once HMAC key processing + // is finished this bit is + // automatically cleared and the + // resulting Inner and Outer digest + // is available from + // SHAMD5_IDIGEST_{A to H} and + // SHAMD5_ODIGEST_{A to H} + // respectively after which regular + // hash processing (using + // SHAMD5_IDIGEST_{A to H} as initial + // digest) will commence until the + // Block Length is exhausted. 0 No + // operation. 1 Hmac processing. + +#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the + // hash/HMAC will be 'closed' at the + // end of the block as per + // MD5/SHA-1/SHA-2 specification + // (i.e. appropriate padding is + // added) or no padding is done + // allowing the hash to be continued + // later. However if the hash/HMAC + // is not closed then the Block + // Length MUST be a multiple of 64 + // bytes to ensure correct + // operation. Auto cleared + // internally when hash closed. 0 No + // padding hash computation can be + // contimued. 1 Last packet will be + // padded. +#define SHAMD5_MODE_ALGO_CONSTANT \ + 0x00000008 // The initial digest register will + // be overwritten with the algorithm + // constants for the selected + // algorithm when hashing and the + // initial digest count register + // will be reset to 0. This will + // start a normal hash operation. + // When continuing an existing hash + // or when performing an HMAC + // operation this register must be + // set to 0 and the + // intermediate/inner digest or HMAC + // key and digest count need to be + // written to the context input + // registers prior to writing + // SHAMD5_MODE. Auto cleared + // internally after first block + // processed. 0 Use pre-calculated + // digest (from an other operation) + // 1 Use constants of the selected + // algo. + +#define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash + // algorithm to be used for + // processing: 0x0 md5_128 algorithm + // 0x1 sha1_160 algorithm 0x2 + // sha2_224 algorithm 0x3 sha2_256 + // algorithm +#define SHAMD5_MODE_ALGO_S 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_LENGTH register. +// +//****************************************************************************** +#define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data +#define SHAMD5_LENGTH_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA0_IN_DATA0_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA0_IN_DATA0_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA1_IN_DATA1_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA1_IN_DATA1_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA2_IN_DATA2_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA2_IN_DATA2_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA3_IN_DATA3_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA3_IN_DATA3_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA4_IN_DATA4_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA4_IN_DATA4_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA5_IN_DATA5_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA5_IN_DATA5_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA6_IN_DATA6_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA6_IN_DATA6_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA7_IN_DATA7_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA7_IN_DATA7_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA8_IN_DATA8_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA8_IN_DATA8_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA9_IN_DATA9_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA9_IN_DATA9_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA10_IN_DATA10_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA10_IN_DATA10_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA11_IN_DATA11_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA11_IN_DATA11_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA12_IN_DATA12_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA12_IN_DATA12_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA13_IN_DATA13_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA13_IN_DATA13_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA14_IN_DATA14_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA14_IN_DATA14_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA15_IN_DATA15_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA15_IN_DATA15_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_REVISION register. +// +//****************************************************************************** +#define SHAMD5_REVISION_SCHEME_M 0xC0000000 +#define SHAMD5_REVISION_SCHEME_S 30 +#define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define SHAMD5_REVISION_FUNC_S 16 +#define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define SHAMD5_REVISION_R_RTL_S 11 +#define SHAMD5_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. + +#define SHAMD5_REVISION_X_MAJOR_S 8 +#define SHAMD5_REVISION_CUSTOM_M 0x000000C0 +#define SHAMD5_REVISION_CUSTOM_S 6 +#define SHAMD5_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. + +#define SHAMD5_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register. +// +//****************************************************************************** +#define SHAMD5_SYSCONFIG_PADVANCED \ + 0x00000080 // If set to 1 Advanced mode is + // enabled for the Secure World. If + // set to 0 Legacy mode is enabled + // for the Secure World. + +#define SHAMD5_SYSCONFIG_PCONT_SWT \ + 0x00000040 // Finish all pending data and + // context DMA input requests (but + // will not assert any new requests) + // finish processing all data in the + // module and provide a saved + // context (partial hash result + // updated digest count remaining + // length updated mode information + // where applicable) for the last + // operation that was interrupted so + // that it can be resumed later. + +#define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008 +#define SHAMD5_SYSCONFIG_PIT_EN 0x00000004 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register. +// +//****************************************************************************** +#define SHAMD5_SYSSTATUS_RESETDONE \ + 0x00000001 // data + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register. +// +//****************************************************************************** +#define SHAMD5_IRQSTATUS_CONTEXT_READY \ + 0x00000008 // indicates that the secure side + // context input registers are + // available for a new context for + // the next packet to be processed. + +#define SHAMD5_IRQSTATUS_PARTHASH_READY \ + 0x00000004 // After a secure side context + // switch request this bit will read + // as 1 indicating that the saved + // context is available from the + // secure side context output + // registers. Note that if the + // context switch request coincides + // with a final hash (when hashing) + // or an outer hash (when doing + // HMAC) that PartHashReady will not + // become active but a regular + // Output Ready will occur instead + // (indicating that the result is + // final and therefore no + // continuation is required). + +#define SHAMD5_IRQSTATUS_INPUT_READY \ + 0x00000002 // indicates that the secure side + // data FIFO is ready to receive the + // next 64 byte data block. + +#define SHAMD5_IRQSTATUS_OUTPUT_READY \ + 0x00000001 // Indicates that a (partial) + // result or saved context is + // available from the secure side + // context output registers. + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register. +// +//****************************************************************************** +#define SHAMD5_IRQENABLE_M_CONTEXT_READY \ + 0x00000008 // mask for context ready + +#define SHAMD5_IRQENABLE_M_PARTHASH_READY \ + 0x00000004 // mask for partial hash + +#define SHAMD5_IRQENABLE_M_INPUT_READY \ + 0x00000002 // mask for input_ready + +#define SHAMD5_IRQENABLE_M_OUTPUT_READY \ + 0x00000001 // mask for output_ready + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_A_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_B_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_C_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_D_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_E_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_F_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_G_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_H_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_I register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_I_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_I_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_J register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_J_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_J_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_K register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_K_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_K_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_L register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_L_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_L_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_M register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_M_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_M_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_N register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_N_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_N_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_O register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_O_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_O_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_P register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_A_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_B_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_C_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_D_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_E_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_F_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_G_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_H_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_I register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_I_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_I_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_J register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_J_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_J_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_K register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_K_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_K_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_L register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_L_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_L_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_M register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_M_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_M_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_N register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_N_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_N_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_O register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_O_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_O_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_P register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_DIGEST_COUNT register. +// +//****************************************************************************** +#define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_MODE register. +// +//****************************************************************************** +#define SHAMD5_HASH512_MODE_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_MODE_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_LENGTH register. +// +//****************************************************************************** +#define SHAMD5_HASH512_LENGTH_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_LENGTH_DATA_S 0 + + + +#endif // __HW_SHAMD5_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h new file mode 100644 index 000000000..479da15de --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h @@ -0,0 +1,766 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __HW_STACK_DIE_CTRL_H__ +#define __HW_STACK_DIE_CTRL_H__ + +//***************************************************************************** +// +// The following are defines for the STACK_DIE_CTRL register offsets. +// +//***************************************************************************** +#define STACK_DIE_CTRL_O_STK_UP_RESET \ + 0x00000000 // Can be written only by Base + // Processor. Writing to this + // register will reset the stack + // processor reset will be + // de-asserted upon clearing this + // register. + +#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \ + 0x00000004 // This register defines who among + // base processor and stack + // processor have highest priority + // for Sram Access. Can be written + // only by Base Processor. + +#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \ + 0x00000008 // In Spinlock mode this Register + // defines who among base processor + // and stack processor have access + // to Sram Bank2 right now. In + // Handshake mode this Register + // defines who among base processor + // and stack processor have access + // to Sram Bank2 and Bank3 right + // now. Its Clear only register and + // is set by hardware. Lower bit can + // be cleared only by Base Processor + // and Upper bit Cleared only by the + // Stack processor. + +#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \ + 0x0000000C // In Spinlock mode whenever Base + // processor wants the access to + // Sram Bank2 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by Stack + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \ + 0x00000010 // In Spinlock mode Whenever Stack + // processor wants the access to + // Sram Bank2 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by the Base + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \ + 0x00000014 // Register defines who among base + // processor and stack processor + // have access to Sram Bank3 right + // now. Its Clear only register and + // is set by hardware. Lower bit can + // be cleared only by Base Processor + // and Upper bit Cleared only by the + // Stack processor. + +#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \ + 0x00000018 // In Spinlock mode whenever Base + // processor wants the access to + // Sram Bank3 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by Stack + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \ + 0x0000001C // In Spinlock mode Whenever Stack + // processor wants the access to + // Sram Bank3 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by the Base + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \ + 0x00000020 // Read State Machine timing + // configuration register. Generally + // Bit 4 and 3 will be identical. + // For stacked die always 43 are 0 + // and 6:5 == 1 for 120Mhz. + +#define STACK_DIE_CTRL_O_RDSM_CFG_EE \ + 0x00000024 // Read State Machine timing + // configuration register. Generally + // Bit 4 and 3 will be identical. + // For stacked die always 43 are 0 + // and 6:5 == 1 for 120Mhz. + +#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \ + 0x00000028 // Reading this register Base + // procesor will able to know the + // reason for the interrupt. This is + // clear only register - set by HW + // upon an interrupt to Base + // processor and can be cleared only + // by BASE processor. + +#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \ + 0x0000002C // Reading this register Stack + // procesor will able to know the + // reason for the interrupt. This is + // clear only register - set by HW + // upon an interrupt to Stack + // processor and can be cleared only + // by Stack processor. + +#define STACK_DIE_CTRL_O_STK_CLK_EN \ + 0x00000030 // Can be written only by base + // processor. Controls the enable + // pin of the cgcs for the clocks + // going to CM3 dft ctrl block and + // Sram. + +#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \ + 0x00000034 // Can be written only by the base + // processor. Decides the ram + // sharing mode :: handshake or + // Spinlock mode. + +#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \ + 0x00000038 // Stores the last bus fault + // address. + +#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \ + 0x0000003C // write only registers on read + // returns 0.W Write 1 to clear the + // bust fault to store the new bus + // fault address + +#define STACK_DIE_CTRL_O_RESET_CAUSE \ + 0x00000040 // Reset cause value captured from + // the ICR_CLKRST block. + +#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \ + 0x00000044 // Watchdog timer event value + // captured from the ICR_CLKRST + // block + +#define STACK_DIE_CTRL_O_DMA_REQ \ + 0x00000048 // To send Dma Request to bottom + // die. + +#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \ + 0x0000004C // Address offset within SRAM to + // which CM3 should jump after + // reset. + +#define STACK_DIE_CTRL_O_SW_REG1 \ + 0x00000050 // These are sw registers for + // topdie processor and bottom die + // processor to communicate. Both + // can set and read these registers. + // In case of write clash bottom + // die's processor wins and top die + // processor access is ignored. + +#define STACK_DIE_CTRL_O_SW_REG2 \ + 0x00000054 // These are sw registers for + // topdie processor and bottom die + // processor to communicate. Both + // can set and read these registers. + // In case of write clash bottom + // die's processor wins and top die + // processor access is ignored. + +#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \ + 0x00000058 // By posting the request Flash can + // be put into low-power mode + // (Sleep) without powering down the + // Flash. Earlier (in Garnet) this + // was fully h/w controlled and the + // control for this was coming from + // SysCtl while entering into Cortex + // Deep-sleep mode. But for our + // device the D2D i/f doesnt support + // this. The Firmware has to program + // the register in the top-die for + // entering into this mode and wait + // for an interrupt. + +#define STACK_DIE_CTRL_O_MISC_CTL \ + 0x0000005C // Miscellanious control register. + +#define STACK_DIE_CTRL_O_SW_DFT_CTL \ + 0x000000FC // DFT control and status bits + +#define STACK_DIE_CTRL_O_PADN_CTL_0 \ + 0x00000100 // Mainly for For controlling the + // pads OEN pins. There are total 60 + // pads and hence 60 control registe + // i.e n value varies from 0 to 59. + // Here is the mapping for the + // pad_ctl register number and the + // functionality : 0 D2DPAD_DMAREQ1 + // 1 D2DPAD_DMAREQ0 2 + // D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 + // D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 + // D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 + // D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS + // 10 D2DPAD_JTAG_TDI 11-27 + // D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE + // -1:0] 28-56 D2DPAD_TOSTACK + // [D2D_TOSTACK_SIZE -1:0] 57-59 + // D2DPAD_SPARE [D2D_SPARE_PAD_SIZE + // -1:0] 0:00 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_RESET register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \ + 0x00000001 // 1 :Assert Reset 0 : Deassert the + // Reset + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \ + 0x00000003 // 00 : Equal Priority 01 : Stack + // Processor have priority 10 : Base + // Processor have priority 11 : + // Unused + +#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \ + 0x00000002 // Stack Processor should clear it + // when it is done with the sram + // bank usage. Set by HW It is set + // when Stack Processor is granted + // the access to this bank + +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \ + 0x00000001 // Base Processor should clear it + // when it is done wth the sram + // usage. Set by HW It is set when + // Base Processor is granted the + // access to this bank + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \ + 0x00000001 // Base Processor will set when + // Sram access is needed in Spin + // Lock mode. In Handshake mode + // Stack Processor will set to + // inform Base Processor that it is + // done with the processing of data + // in SRAM and is now ready to use + // by the base processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \ + 0x00000001 // Stack Processor will set when + // Sram access is needed in Spin + // Lock mode. In Handshake mode Base + // Processor will set to inform + // Stack Processor to start + // processing the data in the Ram. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \ + 0x00000002 // Stack Processor should clear it + // when it is done with the sram + // bank usage. Set by HW It is set + // when Stack Processor is granted + // the access to this bank. + +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \ + 0x00000001 // Base Processor should clear it + // when it is done wth the sram + // usage. Set by HW it is set when + // Base Processor is granted the + // access to this bank. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \ + 0x00000001 // Base Processor will set when + // Sram access is needed in Spin + // Lock mode. Not used in handshake + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \ + 0x00000001 // Stack Processor will set when + // Sram access is needed in Spin + // Lock mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RDSM_CFG_CPU register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \ + 0x000000C0 // Bank Clock Hi Time 00 : HCLK + // pulse 01 : 1 cycle of HCLK 10 : + // 1.5 cycles of HCLK 11 : 2 cycles + // of HCLK + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6 +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \ + 0x00000020 // FLCLK 0 : indicates flash clock + // rise aligns on HCLK rise 1 : + // indicates flash clock rise aligns + // on HCLK fall + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \ + 0x00000010 // 0 : Always register flash rdata + // before sending to CPU 1 : Drive + // Flash rdata directly out on MISS + // (Both ICODE / DCODE) + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \ + 0x0000000F // Number of wait states inserted + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RDSM_CFG_EE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \ + 0x000000C0 // Bank Clock Hi Time 00 : HCLK + // pulse 01 : 1 cycle of HCLK 10 : + // 1.5 cycles of HCLK 11 : 2 cycles + // of HCLK + +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6 +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \ + 0x00000020 // FLCLK 0 : indicates flash clock + // rise aligns on HCLK rise 1 : + // indicates flash clock rise aligns + // on HCLK fall + +#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \ + 0x00000010 // 0 : Always register flash rdata + // before sending to CPU 1 : Drive + // Flash rdata directly out on MISS + // (Both ICODE / DCODE) + +#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \ + 0x0000000F // Number of wait states inserted + +#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \ + 0x00000010 // Set when Relinquish Interrupt + // sent to Base processor for Bank3. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \ + 0x00000008 // Set when Relinquish Interrupt + // sent to Base processor for Bank2. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \ + 0x00000004 // Set when Bank3 is granted to + // Base processor. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \ + 0x00000002 // Set when Bank2 is granted to + // BAse processor. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \ + 0x00000001 // Set when there Base processor do + // an Invalid access to Sram. Ex : + // Accessing the bank which is not + // granted for BAse processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \ + 0x00000008 // Set when Relinquish Interrupt + // sent to Stack processor for + // Bank3. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \ + 0x00000004 // Set when Relinquish Interrupt + // sent to Stack processor for + // Bank2. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \ + 0x00000002 // Set when Bank3 is granted to + // Stack processor. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \ + 0x00000001 // Set when Bank2 is granted to + // Stack processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_CLK_EN register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \ + 0x00000004 // Enable the clock going to sram. + +#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \ + 0x00000002 // Enable the clock going to dft + // control block + +#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \ + 0x00000001 // Enable the clock going to Cm3 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \ + 0x00000001 // 0 : Handshake Mode 1 : Spinlock + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \ + 0xFFFFFFFF // Fault Address + +#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BUS_FAULT_CLR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \ + 0x00000001 // When set it'll clear the bust + // fault address register to store + // the new bus fault address + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RESET_CAUSE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_DMA_REQ register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \ + 0x00000002 // Generate DMAREQ1 on setting this + // bit. + +#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \ + 0x00000001 // Generate DMAREQ0 on setting this + // bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_REG1 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_REG2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \ + 0x00000002 // captures the status of of + // fmc_lpm_ack + +#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \ + 0x00000001 // When set assert + // iflpe2fmc_lpm_req to FMC. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_MISC_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \ + 0x00000080 // 1 : will reset the async wdog + // timer runing on piosc clock + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \ + 0x00000020 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \ + 0x00000010 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \ + 0x00000008 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \ + 0x00000004 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 3 goes to Bank3 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank2 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \ + 0x00000002 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 2 goes to Bank2 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank2 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \ + 0x00000001 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 1 goes to Bank1 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_DFT_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \ + 0x20000000 // when set to '1' all flash + // control signals switch over to + // CM3 control when '0' it is under + // the D2D interface control + +#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \ + 0x10000000 // 1 indicates in SWIF mode the + // control signals to flash are from + // FMC CPU read controls the clock + // and address. that is one can give + // address via FMC and read through + // IDMEM. + +#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \ + 0x00800000 // 'CPU Done' bit for PBIST. Write + // '1' to indicate test done. + +#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \ + 0x00400000 // 'CPU Fail' bit for PBIST. Write + // '1' to indicate test failed. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \ + 0x00001000 // when set to '1' flash bank 4 + // (EEPROM) is owned by the CM3for + // reads over DCODE bus. When '0' + // access control given to D2D + // interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \ + 0x00000800 // when set to '1' flash bank 3 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \ + 0x00000400 // when set to '1' flash bank 2 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \ + 0x00000200 // when set to '1' flash bank 1 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \ + 0x00000100 // when set to '1' flash bank 0 is + // owned by the CM3 for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_PADN_CTL_0 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \ + 0x00000008 // This bit is valid for only the + // spare pads ie for n=57 to 59. + // value to drive at the output of + // the pad + +#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \ + 0x00000004 // This bit is valid for only the + // spare pads ie for n=57 to 59. + // captures the 'Y' pin of the pad + // which is the data being driven + // into the die + +#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \ + 0x00000002 // OEN2X control when '1' enables + // the output with 1x. Total drive + // strength is decided bu oen1x + // setting + oen2x setting. + +#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \ + 0x00000001 // OEN1X control when '1' enables + // the output with 1x . Total drive + // strength is decided bu oen1x + // setting + oen2x setting. + + + + +#endif // __HW_STACK_DIE_CTRL_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_timer.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_timer.h new file mode 100644 index 000000000..0a95ea8de --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_timer.h @@ -0,0 +1,780 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +//***************************************************************************** + +//##### INTERNAL BEGIN ##### +// +// This is an auto-generated file. Do not edit by hand. +// Created by version 6779 of DriverLib. +// +//##### INTERNAL END ##### + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following are defines for the Timer register offsets. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // GPTM Configuration +#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode +#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode +#define TIMER_O_CTL 0x0000000C // GPTM Control +//##### GARNET BEGIN ##### +#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize +//##### GARNET END ##### +#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask +#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status +#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status +#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear +#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load +#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load +#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match +#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match +#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale +#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale +#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match +#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match +#define TIMER_O_TAR 0x00000048 // GPTM Timer A +#define TIMER_O_TBR 0x0000004C // GPTM Timer B +#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value +#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value +#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide +#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot +#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot +#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value +#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value +#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event +#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties + + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) + // counter configuration +#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The + // function is controlled by bits + // 1:0 of GPTMTAMR and GPTMTBMR + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +//##### GARNET END ##### +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +//##### GARNET END ##### +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable +//##### GARNET BEGIN ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNC11_M 0x00C00000 // Synchronize GPTM Timer 11 +#define TIMER_SYNC_SYNC11_TA 0x00400000 // A timeout event for Timer A of + // GPTM11 is triggered +#define TIMER_SYNC_SYNC11_TB 0x00800000 // A timeout event for Timer B of + // GPTM11 is triggered +#define TIMER_SYNC_SYNC11_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM11 is + // triggered +#define TIMER_SYNC_SYNC10_M 0x00300000 // Synchronize GPTM Timer 10 +#define TIMER_SYNC_SYNC10_TA 0x00100000 // A timeout event for Timer A of + // GPTM10 is triggered +#define TIMER_SYNC_SYNC10_TB 0x00200000 // A timeout event for Timer B of + // GPTM10 is triggered +#define TIMER_SYNC_SYNC10_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM10 is + // triggered +#define TIMER_SYNC_SYNC9_M 0x000C0000 // Synchronize GPTM Timer 9 +#define TIMER_SYNC_SYNC9_TA 0x00040000 // A timeout event for Timer A of + // GPTM9 is triggered +#define TIMER_SYNC_SYNC9_TB 0x00080000 // A timeout event for Timer B of + // GPTM9 is triggered +#define TIMER_SYNC_SYNC9_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM9 is + // triggered +#define TIMER_SYNC_SYNC8_M 0x00030000 // Synchronize GPTM Timer 8 +#define TIMER_SYNC_SYNC8_TA 0x00010000 // A timeout event for Timer A of + // GPTM8 is triggered +#define TIMER_SYNC_SYNC8_TB 0x00020000 // A timeout event for Timer B of + // GPTM8 is triggered +#define TIMER_SYNC_SYNC8_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM8 is + // triggered +#define TIMER_SYNC_SYNC7_M 0x0000C000 // Synchronize GPTM Timer 7 +#define TIMER_SYNC_SYNC7_TA 0x00004000 // A timeout event for Timer A of + // GPTM7 is triggered +#define TIMER_SYNC_SYNC7_TB 0x00008000 // A timeout event for Timer B of + // GPTM7 is triggered +#define TIMER_SYNC_SYNC7_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM7 is + // triggered +#define TIMER_SYNC_SYNC6_M 0x00003000 // Synchronize GPTM Timer 6 +#define TIMER_SYNC_SYNC6_TA 0x00001000 // A timeout event for Timer A of + // GPTM6 is triggered +#define TIMER_SYNC_SYNC6_TB 0x00002000 // A timeout event for Timer B of + // GPTM6 is triggered +#define TIMER_SYNC_SYNC6_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM6 is + // triggered +#define TIMER_SYNC_SYNC5_M 0x00000C00 // Synchronize GPTM Timer 5 +#define TIMER_SYNC_SYNC5_TA 0x00000400 // A timeout event for Timer A of + // GPTM5 is triggered +#define TIMER_SYNC_SYNC5_TB 0x00000800 // A timeout event for Timer B of + // GPTM5 is triggered +#define TIMER_SYNC_SYNC5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +#define TIMER_SYNC_SYNC4_M 0x00000300 // Synchronize GPTM Timer 4 +#define TIMER_SYNC_SYNC4_TA 0x00000100 // A timeout event for Timer A of + // GPTM4 is triggered +#define TIMER_SYNC_SYNC4_TB 0x00000200 // A timeout event for Timer B of + // GPTM4 is triggered +#define TIMER_SYNC_SYNC4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +#define TIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM Timer 3 +#define TIMER_SYNC_SYNC3_TA 0x00000040 // A timeout event for Timer A of + // GPTM3 is triggered +#define TIMER_SYNC_SYNC3_TB 0x00000080 // A timeout event for Timer B of + // GPTM3 is triggered +#define TIMER_SYNC_SYNC3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +#define TIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM Timer 2 +#define TIMER_SYNC_SYNC2_TA 0x00000010 // A timeout event for Timer A of + // GPTM2 is triggered +#define TIMER_SYNC_SYNC2_TB 0x00000020 // A timeout event for Timer B of + // GPTM2 is triggered +#define TIMER_SYNC_SYNC2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +#define TIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM Timer 1 +#define TIMER_SYNC_SYNC1_TA 0x00000004 // A timeout event for Timer A of + // GPTM1 is triggered +#define TIMER_SYNC_SYNC1_TB 0x00000008 // A timeout event for Timer B of + // GPTM1 is triggered +#define TIMER_SYNC_SYNC1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +#define TIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM Timer 0 +#define TIMER_SYNC_SYNC0_TA 0x00000001 // A timeout event for Timer A of + // GPTM0 is triggered +#define TIMER_SYNC_SYNC0_TB 0x00000002 // A timeout event for Timer B of + // GPTM0 is triggered +#define TIMER_SYNC_SYNC0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Mask +//##### GARNET END ##### +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match + // Interrupt Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt + // Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt + // Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match + // Interrupt Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt + // Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt + // Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Raw Interrupt Status +//##### GARNET END ##### +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw + // Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw + // Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw + // Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw + // Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw + // Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw + // Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Masked Interrupt Status +//##### GARNET END ##### +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked + // Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked + // Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked + // Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked + // Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Clear +//##### GARNET END ##### +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match + // Interrupt Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt + // Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt + // Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match + // Interrupt Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt + // Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt + // Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +//##### GARNET END ##### +#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load + // Register High +#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load + // Register Low +#define TIMER_TAILR_TAILRH_S 16 +#define TIMER_TAILR_TAILRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAILR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +//##### GARNET END ##### +#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_TBILRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBILR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +//##### GARNET END ##### +#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High +#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low +#define TIMER_TAMATCHR_TAMRH_S 16 +#define TIMER_TAMATCHR_TAMRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAMATCHR_TAMR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +//##### GARNET END ##### +#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low +//##### GARNET BEGIN ##### +#define TIMER_TBMATCHR_TBMR_S 0 +//##### GARNET END ##### +#define TIMER_TBMATCHR_TBMRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +//##### GARNET END ##### +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +//##### GARNET BEGIN ##### +#define TIMER_TAPR_TAPSRH_S 8 +//##### GARNET END ##### +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +//##### GARNET END ##### +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +//##### GARNET BEGIN ##### +#define TIMER_TBPR_TBPSRH_S 8 +//##### GARNET END ##### +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +//##### GARNET END ##### +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +//##### GARNET BEGIN ##### +#define TIMER_TAPMR_TAPSMRH_S 8 +//##### GARNET END ##### +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +//##### GARNET END ##### +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +//##### GARNET BEGIN ##### +#define TIMER_TBPMR_TBPSMRH_S 8 +//##### GARNET END ##### +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +//##### GARNET END ##### +#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High +#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAR_TARH_S 16 +#define TIMER_TAR_TARL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +//##### GARNET END ##### +#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B +#define TIMER_TBR_TBRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +//##### GARNET END ##### +#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High +#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAV_TAVH_S 16 +#define TIMER_TAV_TAVL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAV_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +//##### GARNET END ##### +#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register +#define TIMER_TBV_TBVL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start +#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE__0 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE__1 0x00000001 // Timer A and Timer B counters are + // 32 bits each with an 16-bit + // prescale counter +//##### GARNET END ##### + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CFG +// register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CTL +// register. +// +//***************************************************************************** +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_RIS +// register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAILR +// register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBILR +// register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAR +// register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBR +// register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the timer +// registers. +// +//***************************************************************************** +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnMR +// register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPR +// register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPMR +// register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +#endif + +#endif // __HW_TIMER_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_types.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_types.h new file mode 100644 index 000000000..0c4703d99 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_types.h @@ -0,0 +1,78 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif // __HW_TYPES_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_uart.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_uart.h new file mode 100644 index 000000000..f3b83aba8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_uart.h @@ -0,0 +1,419 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the UART register offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 +#define UART_O_RSR 0x00000004 +#define UART_O_ECR 0x00000004 +#define UART_O_FR 0x00000018 +#define UART_O_ILPR 0x00000020 +#define UART_O_IBRD 0x00000024 +#define UART_O_FBRD 0x00000028 +#define UART_O_LCRH 0x0000002C +#define UART_O_CTL 0x00000030 +#define UART_O_IFLS 0x00000034 +#define UART_O_IM 0x00000038 +#define UART_O_RIS 0x0000003C +#define UART_O_MIS 0x00000040 +#define UART_O_ICR 0x00000044 +#define UART_O_DMACTL 0x00000048 +#define UART_O_LCTL 0x00000090 +#define UART_O_LSS 0x00000094 +#define UART_O_LTIM 0x00000098 +#define UART_O_9BITADDR 0x000000A4 +#define UART_O_9BITAMASK 0x000000A8 +#define UART_O_PP 0x00000FC0 +#define UART_O_CC 0x00000FC8 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//****************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//****************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//****************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//****************************************************************************** +#define UART_FR_RI 0x00000100 // Ring Indicator +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_DCD 0x00000004 // Data Carrier Detect +#define UART_FR_DSR 0x00000002 // Data Set Ready +#define UART_FR_CTS 0x00000001 // Clear To Send +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//****************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//****************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//****************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//****************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 : + // UART_LCRH_WLEN_5 : 5 bits + // (default) 0x00000020 : + // UART_LCRH_WLEN_6 : 6 bits + // 0x00000040 : UART_LCRH_WLEN_7 : 7 + // bits 0x00000060 : + // UART_LCRH_WLEN_8 : 8 bits +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//****************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RI 0x00002000 // Ring Indicator +#define UART_CTL_DCD 0x00001000 // Data Carrier Detect +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_DTR 0x00000400 // Data Terminal Ready +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_LIN 0x00000040 // LIN Mode Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//****************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX_S 3 +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//****************************************************************************** +#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask +#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask +#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask +#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask +#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt + // Mask +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt + // Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem + // Interrupt Mask +#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask +#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem + // Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//****************************************************************************** +#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt + // Status +#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status +#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt + // Status +#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt + // Status +#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw + // Interrupt Status +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw + // Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw + // Interrupt Status +#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem + // Raw Interrupt Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status +#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw + // Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//****************************************************************************** +#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt + // Status +#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt + // Status +#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt + // Status +#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt + // Status +#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked + // Interrupt Status +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked + // Interrupt Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked + // Interrupt Status +#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem + // Masked Interrupt Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status +#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked + // Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//****************************************************************************** +#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear +#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear +#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear +#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear +#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt + // Clear +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt + // Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem + // Interrupt Clear +#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear +#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem + // Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//****************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCTL register. +// +//****************************************************************************** +#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 : + // UART_LCTL_BLEN_13T : Sync break + // length is 13T bits (default) + // 0x00000010 : UART_LCTL_BLEN_14T : + // Sync break length is 14T bits + // 0x00000020 : UART_LCTL_BLEN_15T : + // Sync break length is 15T bits + // 0x00000030 : UART_LCTL_BLEN_16T : + // Sync break length is 16T bits +#define UART_LCTL_BLEN_S 4 +#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LSS register. +// +//****************************************************************************** +#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot +#define UART_LSS_TSS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LTIM register. +// +//****************************************************************************** +#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value +#define UART_LTIM_TIMER_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UART_O_9BITADDR register. +// +//****************************************************************************** +#define UART_9BITADDR_9BITEN \ + 0x00008000 // Enable 9-Bit Mode + +#define UART_9BITADDR_ADDR_M \ + 0x000000FF // Self Address for 9-Bit Mode + +#define UART_9BITADDR_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UART_O_9BITAMASK register. +// +//****************************************************************************** +#define UART_9BITAMASK_RANGE_M \ + 0x0000FF00 // Self Address Range for 9-Bit + // Mode + +#define UART_9BITAMASK_RANGE_S 8 +#define UART_9BITAMASK_MASK_M \ + 0x000000FF // Self Address Mask for 9-Bit Mode + +#define UART_9BITAMASK_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//****************************************************************************** +#define UART_PP_MSE 0x00000008 // Modem Support Extended +#define UART_PP_MS 0x00000004 // Modem Support +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//****************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source + // 0x00000005 : UART_CC_CS_PIOSC : + // PIOSC 0x00000000 : + // UART_CC_CS_SYSCLK : The system + // clock (default) +#define UART_CC_CS_S 0 + + + +#endif // __HW_UART_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_udma.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_udma.h new file mode 100644 index 000000000..bbad6b916 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_udma.h @@ -0,0 +1,338 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// The following are defines for the UDMA register offsets. +// +//***************************************************************************** +#define UDMA_O_STAT 0x00000000 +#define UDMA_O_CFG 0x00000004 +#define UDMA_O_CTLBASE 0x00000008 +#define UDMA_O_ALTBASE 0x0000000C +#define UDMA_O_WAITSTAT 0x00000010 +#define UDMA_O_SWREQ 0x00000014 +#define UDMA_O_USEBURSTSET 0x00000018 +#define UDMA_O_USEBURSTCLR 0x0000001C +#define UDMA_O_REQMASKSET 0x00000020 +#define UDMA_O_REQMASKCLR 0x00000024 +#define UDMA_O_ENASET 0x00000028 +#define UDMA_O_ENACLR 0x0000002C +#define UDMA_O_ALTSET 0x00000030 +#define UDMA_O_ALTCLR 0x00000034 +#define UDMA_O_PRIOSET 0x00000038 +#define UDMA_O_PRIOCLR 0x0000003C +#define UDMA_O_ERRCLR 0x0000004C +#define UDMA_O_CHASGN 0x00000500 +#define UDMA_O_CHIS 0x00000504 +#define UDMA_O_CHMAP0 0x00000510 +#define UDMA_O_CHMAP1 0x00000514 +#define UDMA_O_CHMAP2 0x00000518 +#define UDMA_O_CHMAP3 0x0000051C +#define UDMA_O_PV 0x00000FB0 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_STAT register. +// +//****************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_DMACHANS_S 16 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status + // 0x00000090 : UDMA_STAT_STATE_DONE + // : Done 0x00000000 : + // UDMA_STAT_STATE_IDLE : Idle + // 0x00000010 : + // UDMA_STAT_STATE_RD_CTRL : Reading + // channel controller data + // 0x00000030 : + // UDMA_STAT_STATE_RD_DSTENDP : + // Reading destination end pointer + // 0x00000040 : + // UDMA_STAT_STATE_RD_SRCDAT : + // Reading source data 0x00000020 : + // UDMA_STAT_STATE_RD_SRCENDP : + // Reading source end pointer + // 0x00000080 : + // UDMA_STAT_STATE_STALL : Stalled + // 0x000000A0 : + // UDMA_STAT_STATE_UNDEF : Undefined + // 0x00000060 : UDMA_STAT_STATE_WAIT + // : Waiting for uDMA request to + // clear 0x00000070 : + // UDMA_STAT_STATE_WR_CTRL : Writing + // channel controller data + // 0x00000050 : + // UDMA_STAT_STATE_WR_DSTDAT : + // Writing destination data +#define UDMA_STAT_STATE_S 4 +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CFG register. +// +//****************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CTLBASE register. +// +//****************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTBASE register. +// +//****************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_WAITSTAT register. +// +//****************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M \ + 0xFFFFFFFF // Channel [n] Wait Status + +#define UDMA_WAITSTAT_WAITREQ_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SWREQ register. +// +//****************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request +#define UDMA_SWREQ_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UDMA_O_USEBURSTSET register. +// +//****************************************************************************** +#define UDMA_USEBURSTSET_SET_M \ + 0xFFFFFFFF // Channel [n] Useburst Set + +#define UDMA_USEBURSTSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UDMA_O_USEBURSTCLR register. +// +//****************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M \ + 0xFFFFFFFF // Channel [n] Useburst Clear + +#define UDMA_USEBURSTCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_REQMASKSET register. +// +//****************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set +#define UDMA_REQMASKSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register. +// +//****************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear +#define UDMA_REQMASKCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ENASET register. +// +//****************************************************************************** +#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set +#define UDMA_ENASET_CHENSET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ENACLR register. +// +//****************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear +#define UDMA_ENACLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTSET register. +// +//****************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set +#define UDMA_ALTSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTCLR register. +// +//****************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear +#define UDMA_ALTCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PRIOSET register. +// +//****************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set +#define UDMA_PRIOSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PRIOCLR register. +// +//****************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear +#define UDMA_PRIOCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ERRCLR register. +// +//****************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHASGN register. +// +//****************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHIS register. +// +//****************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status +#define UDMA_CHIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP0 register. +// +//****************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH0SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP1 register. +// +//****************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH8SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP2 register. +// +//****************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH16SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP3 register. +// +//****************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH24SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PV register. +// +//****************************************************************************** +#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision +#define UDMA_PV_MAJOR_S 8 +#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision +#define UDMA_PV_MINOR_S 0 + + + +#endif // __HW_UDMA_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_wdt.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_wdt.h new file mode 100644 index 000000000..f80c0463c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_wdt.h @@ -0,0 +1,133 @@ +/* + * ------------------------------------------- + * CC3220 SDK - v0.10.00.00 + * ------------------------------------------- + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_WDT_H__ +#define __HW_WDT_H__ + +//***************************************************************************** +// +// The following are defines for the WDT register offsets. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 +#define WDT_O_VALUE 0x00000004 +#define WDT_O_CTL 0x00000008 +#define WDT_O_ICR 0x0000000C +#define WDT_O_RIS 0x00000010 +#define WDT_O_MIS 0x00000014 +#define WDT_O_TEST 0x00000418 +#define WDT_O_LOCK 0x00000C00 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//****************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//****************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//****************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit + // is not used in cc3xx, WDOG shall + // always generate RESET to system + // irrespective of this bit setting. +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//****************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//****************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//****************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//****************************************************************************** +#define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable +#define WDT_TEST_STALL_EN_S 10 +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//****************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_S 0 +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + + + + + +#endif // __HW_WDT_H__ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/ADC.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/ADC.h new file mode 100644 index 000000000..6bc09c77a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/ADC.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ADC.h + * + * @brief ADC driver interface + * + * The ADC header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * The ADC driver operates as a simplified ADC module with only single channel + * sampling support. It also operates on blocking only mode which means users + * have to wait the current sampling finished before starting another sampling. + * The sampling channel needs to be specified in the ADC_open() before calling + * ADC_convert(). + * + * The APIs in this driver serve as an interface to a typical TI-RTOS + * application. The specific peripheral implementations are responsible to + * create all the SYS/BIOS specific primitives to allow for thread-safe + * operation. + * User can use the ADC driver or the ADCBuf driver that has more features. + * But both ADC and ADCBuf cannot be used together in an application. + * + * ## Opening the driver # + * + * @code + * ADC_Handle adc; + * ADC_Params params; + * + * ADC_Params_init(¶ms); + * adc = ADC_open(Board_ADCCHANNEL_A0, ¶ms); + * if (adc != NULL) { + * ADC_close(adc); + * } + * @endcode + * + * ## Converting # + * An ADC conversion with a ADC peripheral is started by calling ADC_convert(). + * The result value is returned by ADC_convert() once the conversion is + * finished. + * + * @code + * int_fast16_t res; + * uint_fast16_t adcValue; + * + * res = ADC_convert(adc, &adcValue); + * if (res == ADC_STATUS_SUCCESS) { + * //use adcValue + * } + * @endcode + * + * # Implementation # + * + * This module serves as the main interface for TI-RTOS + * applications. Its purpose is to redirect the module's APIs to specific + * peripheral implementations which are specified using a pointer to a + * ADC_FxnTable. + * + * The ADC driver interface module is joined (at link time) to a + * NULL-terminated array of ADC_Config data structures named *ADC_config*. + * *ADC_config* is implemented in the application with each entry being an + * instance of a ADC peripheral. Each entry in *ADC_config* contains a: + * - (ADC_FxnTable *) to a set of functions that implement a ADC peripheral + * - (void *) data object that is associated with the ADC_FxnTable + * - (void *) hardware attributes that are associated to the ADC_FxnTable + * + * # Instrumentation # + * The ADC driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic operations performed | + * Diags_USER2 | detailed operations performed | + * + * ============================================================================ + */ + +#ifndef ti_drivers_ADC__include +#define ti_drivers_ADC__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @defgroup ADC_CONTROL ADC_control command and status codes + * These ADC macros are reservations for ADC.h + * @{ + */ + +/*! + * Common ADC_control command code reservation offset. + * ADC driver implementations should offset command codes with ADC_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define ADCXYZ_CMD_COMMAND0 ADC_CMD_RESERVED + 0 + * #define ADCXYZ_CMD_COMMAND1 ADC_CMD_RESERVED + 1 + * @endcode + */ +#define ADC_CMD_RESERVED (32) + +/*! + * Common ADC_control status code reservation offset. + * ADC driver implementations should offset status codes with + * ADC_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ADCXYZ_STATUS_ERROR0 ADC_STATUS_RESERVED - 0 + * #define ADCXYZ_STATUS_ERROR1 ADC_STATUS_RESERVED - 1 + * #define ADCXYZ_STATUS_ERROR2 ADC_STATUS_RESERVED - 2 + * @endcode + */ +#define ADC_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code returned by ADC_control(). + * + * ADC_control() returns ADC_STATUS_SUCCESS if the control code was executed + * successfully. + * @{ + * @ingroup ADC_CONTROL + */ +#define ADC_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by ADC_control(). + * + * ADC_control() returns ADC_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define ADC_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by ADC_control() for undefined + * command codes. + * + * ADC_control() returns ADC_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define ADC_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup ADC_CMD Command Codes + * ADC_CMD_* macros are general command codes for ADC_control(). Not all ADC + * driver implementations support these command codes. + * @{ + * @ingroup ADC_CONTROL + */ + +/* Add ADC_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief A handle that is returned from a ADC_open() call. + */ +typedef struct ADC_Config_ *ADC_Handle; + +/*! + * @brief ADC Parameters + * + * ADC parameters are used to with the ADC_open() call. Only custom argument + * is supported in the parameters. Default values for these parameters are + * set using ADC_Params_init(). + * + * @sa ADC_Params_init() + */ +typedef struct ADC_Params_ { + void *custom; /*!< Custom argument used by driver + implementation */ + bool isProtected; /*!< By default ADC uses a semaphore + to guarantee thread safety. Setting + this parameter to 'false' will eliminate + the usage of a semaphore for thread + safety. The user is then responsible + for ensuring that parallel invocations + of ADC_convert() are thread safe. */ +} ADC_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * ADC_close(). + */ +typedef void (*ADC_CloseFxn) (ADC_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADC_control(). + */ +typedef int_fast16_t (*ADC_ControlFxn) (ADC_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADC_ConvertFxn(). + */ +typedef int_fast16_t (*ADC_ConvertFxn) (ADC_Handle handle, uint16_t *value); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADC_convertRawToMicroVolts(). + */ +typedef uint32_t (*ADC_ConvertRawToMicroVolts) (ADC_Handle handle, + uint16_t rawAdcValue); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADC_init(). + */ +typedef void (*ADC_InitFxn) (ADC_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADC_open(). + */ +typedef ADC_Handle (*ADC_OpenFxn) (ADC_Handle handle, ADC_Params *params); + +/*! + * @brief The definition of a ADC function table that contains the + * required set of functions to control a specific ADC driver + * implementation. + */ +typedef struct ADC_FxnTable_ { + /*! Function to close the specified peripheral */ + ADC_CloseFxn closeFxn; + + /*! Function to perform implementation specific features */ + ADC_ControlFxn controlFxn; + + /*! Function to initiate a ADC single channel conversion */ + ADC_ConvertFxn convertFxn; + + /*! Function to convert raw ADC result to microvolts */ + ADC_ConvertRawToMicroVolts convertRawToMicroVolts; + + /*! Function to initialize the given data object */ + ADC_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + ADC_OpenFxn openFxn; +} ADC_FxnTable; + +/*! + * @brief ADC Global configuration + * + * The ADC_Config structure contains a set of pointers used to characterize + * the ADC driver implementation. + * + * This structure needs to be defined before calling ADC_init() and it must + * not be changed thereafter. + * + * @sa ADC_init() + */ +typedef struct ADC_Config_ { + /*! Pointer to a table of driver-specific implementations of ADC APIs */ + ADC_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ADC_Config; + +/*! + * @brief Function to close a ADC driver + * + * @pre ADC_open() has to be called first. + * + * @param handle An ADC handle returned from ADC_open() + * + * @sa ADC_open() + */ +extern void ADC_close(ADC_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * ADC_Handle. + * + * @pre ADC_open() has to be called first. + * + * @param handle A ADC handle returned from ADC_open() + * + * @param cmd A command value defined by the driver specific + * implementation + * + * @param arg An optional R/W (read/write) argument that is + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa ADC_open() + */ +extern int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief Function to perform ADC conversion + * + * Function to perform ADC single channel single sample conversion. + * + * @pre ADC_open() has been called + * + * @param handle An ADC_Handle + * @param value A pointer to the conversion result + * + * @return The return value indicates the conversion is succeeded or + * failed. The value could be ADC_STATUS_SUCCESS or + * ADC_STATUS_ERROR. + * + * @sa ADC_open() + * @sa ADC_close() + */ +extern int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value); + +/*! + * @brief Function performs conversion from raw ADC result to actual value in + * microvolts. + * + * @pre ADC_open() and ADC_convert() has to be called first. + * + * @param handle A ADC handle returned from ADC_open() + * + * @param rawAdcValue A sampling result return from ADC_convert() + * + * @return The actual sampling result in micro volts unit. + * + * @sa ADC_open() + */ +extern uint32_t ADC_convertRawToMicroVolts(ADC_Handle handle, + uint16_t rawAdcValue); + +/*! + * @brief Function to initializes the ADC driver + * + * @pre The ADC_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ADC driver APIs. + */ +extern void ADC_init(void); + +/*! + * @brief Function to initialize the ADC peripheral + * + * Function to initialize the ADC peripheral specified by the + * particular index value. + * + * @pre ADC_init() has been called + * + * @param index Logical peripheral number for the ADC indexed into + * the ADC_config table + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A ADC_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa ADC_init() + * @sa ADC_close() + */ +extern ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params); + +/*! + * @brief Function to initialize the ADC_Params struct to its defaults + * + * @param params An pointer to ADC_Params structure for + * initialization + * + * Defaults values are: + * custom = NULL + */ +extern void ADC_Params_init(ADC_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ADC__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/ADCBuf.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/ADCBuf.h new file mode 100644 index 000000000..e0d38b647 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/ADCBuf.h @@ -0,0 +1,602 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ADCBuf.h + * + * @brief ADCBuf driver interface + * + * The ADCBuf header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * The ADCBuf driver in TI-RTOS samples an analogue waveform at a specified + * frequency. The resulting samples are transferred to a buffer provided by + * the application. The driver can either take n samples once, or continuously + * sample by double-buffering and providing a callback to process each finished + * buffer. + * + * The APIs in this driver serve as an interface to a typical TI-RTOS + * application. The specific peripheral implementations are responsible to + * create all the SYS/BIOS specific primitives to allow for thread-safe + * operation. + + * User can use the ADC driver or the ADCBuf driver. But both ADC and ADCBuf + * cannot be used together in an application. + * + * ## Opening the driver # + * + * @code + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * + * ADCBuf_Params_init(&adcBufParams); + * adcBufHandle = ADCBuf_open(Board_ADCBuf0, &adcBufParams); + * @endcode + * + * ## Making a conversion # + * In this context, a conversion refers to taking multiple ADC samples and + * transferring them to an application-provided buffer. + * To start a conversion, the application must configure an ADCBuf_Conversion struct + * and call ADCBuf_convert(). In blocking mode, ADCBuf_convert() will return + * when the conversion is finished and the desired number of samples have been made. + * In callback mode, ADCBuf_convert() will return immediately and the application will + * get a callback when the conversion is done. + * + * @code + * ADCBuf_Conversion blockingConversion; + * + * blockingConversion.arg = NULL; + * blockingConversion.adcChannel = Board_ADCCHANNEL_A1; + * blockingConversion.sampleBuffer = sampleBufferOnePtr; + * blockingConversion.sampleBufferTwo = NULL; + * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (!ADCBuf_convert(adcBuf, &continuousConversion, 1)) { + * // handle error + * } + * @endcode + * + * ## Canceling a conversion # + * ADCBuf_convertCancel() is used to cancel an ADCBuf conversion when the driver is + * used in ::ADCBuf_RETURN_MODE_CALLBACK. + * + * Calling this API while no conversion is in progress has no effect. If a + * conversion is in progress, it is canceled and the provided callback function + * is called. + * + * In ::ADCBuf_RECURRENCE_MODE_CONTINUOUS, this function must be called to stop the + * conversion. The driver will continue providing callbacks with fresh samples + * until thie ADCBuf_convertCancel() function is called. The callback function is not + * called after ADCBuf_convertCancel() while in ::ADCBuf_RECURRENCE_MODE_CONTINUOUS. + * + * # Implementation # + * + * This module serves as the main interface for TI-RTOS applications. Its + * purpose is to redirect the module's APIs to specific peripheral + * implementations which are specified using a pointer to an ADCBuf_FxnTable. + * + * The ADCBuf driver interface module is joined (at link time) to a + * NULL-terminated array of ADCBuf_Config data structures named *ADCBuf_config*. + * *ADCBuf_config* is implemented in the application with each entry being an + * instance of an ADCBuf peripheral. Each entry in *ADCBuf_config* contains a: + * - (ADCBuf_FxnTable *) to a set of functions that implement an ADCBuf peripheral + * - (void *) data object that is associated with the ADCBuf_FxnTable + * - (void *) hardware attributes that are associated to the ADCBuf_FxnTable + * + * # Instrumentation # + * + * The ADCBuf driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ---------------------------------| + * Diags_USER1 | basic operations performed | + * Diags_USER2 | detailed operations performed | + * + * ============================================================================ + */ + +#ifndef ti_drivers_adcbuf__include +#define ti_drivers_adcbuf__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @defgroup ADCBUF_CONTROL ADCBuf_control command and status codes + * These ADCBuf macros are reservations for ADCBuf.h + * @{ + */ + +/*! + * Common ADCBuf_control command code reservation offset. + * ADC driver implementations should offset command codes with ADCBuf_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define ADCXYZ_COMMAND0 ADCBuf_CMD_RESERVED + 0 + * #define ADCXYZ_COMMAND1 ADCBuf_CMD_RESERVED + 1 + * @endcode + */ +#define ADCBuf_CMD_RESERVED (32) + +/*! + * Common ADCBuf_control status code reservation offset. + * ADC driver implementations should offset status codes with + * ADCBuf_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ADCXYZ_STATUS_ERROR0 ADCBuf_STATUS_RESERVED - 0 + * #define ADCXYZ_STATUS_ERROR1 ADCBuf_STATUS_RESERVED - 1 + * #define ADCXYZ_STATUS_ERROR2 ADCBuf_STATUS_RESERVED - 2 + * @endcode + */ +#define ADCBuf_STATUS_RESERVED (-32) + +/*! + * \brief Success status code returned by: + * ADCBuf_control() + * + * Functions return ADCBuf_STATUS_SUCCESS if the call was executed + * successfully. + * @{ + * @ingroup ADCBUF_CONTROL + */ +#define ADCBuf_STATUS_SUCCESS (0) + +/*! + * \brief Generic error status code returned by ADCBuf_control(). + * + * ADCBuf_control() returns ADCBuf_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define ADCBuf_STATUS_ERROR (-1) + +/*! + * \brief An error status code returned by ADCBuf_control() for undefined + * command codes. + * + * ADCBuf_control() returns ADCBuf_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define ADCBuf_STATUS_UNDEFINEDCMD (-2) + +/*! + * \brief An error status code returned by ADCBuf_adjustRawValues() if the + * function is not supported by a particular driver implementation. + * + * ADCBuf_adjustRawValues() returns ADCBuf_STATUS_UNSUPPORTED if the function is + * not supported by the driver implementation. + */ +#define ADCBuf_STATUS_UNSUPPORTED (-3) +/** @}*/ + +/** + * @defgroup ADCBUF_CMD Command Codes + * ADCBUF_CMD_* macros are general command codes for I2C_control(). Not all ADCBuf + * driver implementations support these command codes. + * @{ + * @ingroup ADCBUF_CONTROL + */ + +/* Add ADCBUF_CMD_ here */ + +/** @}*/ + +/** @}*/ + + +/*! + * @brief A handle that is returned from an ADCBuf_open() call. + */ +typedef struct ADCBuf_Config_ *ADCBuf_Handle; + +/*! + * @brief + * An ::ADCBuf_Conversion data structure is used with ADCBuf_convert(). It indicates + * which channel to perform the ADC conversion on, how many conversions to make, and where to put them. + * The arg variable is an user-definable argument which gets passed to the + * ::ADCBuf_Callback when the ADC driver is in ::ADCBuf_RETURN_MODE_CALLBACK. + */ +typedef struct ADCBuf_Conversion_ { + uint16_t samplesRequestedCount; /*!< Number of samples to convert and return */ + void *sampleBuffer; /*!< Buffer the results of the conversions are stored in */ + void *sampleBufferTwo; /*!< A second buffer that is filled in ::ADCBuf_RECURRENCE_MODE_CONTINUOUS mode while + the first buffer is processed by the application. The value is not used in + ::ADCBuf_RECURRENCE_MODE_ONE_SHOT mode. */ + void *arg; /*!< Argument to be passed to the callback function in ::ADCBuf_RETURN_MODE_CALLBACK */ + uint32_t adcChannel; /*!< Channel to perform the ADC conversion on. Mapping of channel to pin or internal signal is device specific. */ +} ADCBuf_Conversion; + +/*! + * @brief The definition of a callback function used by the ADC driver + * when used in ::ADCBuf_RETURN_MODE_CALLBACK. It is called in a HWI or SWI context depending on the device specific implementation. + */ +typedef void (*ADCBuf_Callback) (ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + void *completedADCBuffer, + uint32_t completedChannel); +/*! + * @brief ADC trigger mode settings + * + * This enum defines if the driver should make n conversions and return + * or run indefinitely and run a callback function every n conversions. + */ +typedef enum ADCBuf_Recurrence_Mode_ { + /*! + * The driver makes n measurements and returns or runs a callback function depending + * on the ::ADCBuf_Return_Mode setting. + */ + ADCBuf_RECURRENCE_MODE_ONE_SHOT, + /*! + * The driver makes n measurements and then runs a callback function. This process happens + * until the application calls ::ADCBuf_ConvertCancelFxn(). This setting can only be used in + * ::ADCBuf_RETURN_MODE_CALLBACK. + */ + ADCBuf_RECURRENCE_MODE_CONTINUOUS +} ADCBuf_Recurrence_Mode; + +/*! + * @brief ADC return mode settings + * + * This enum defines how the ADCBuf_convert() function returns. + * It either blocks or returns immediately and calls a callback function when the provided buffer has been filled. + */ +typedef enum ADCBuf_Return_Mode_ { + /*! + * Uses a semaphore to block while ADC conversions are performed. Context of the call + * must be a Task. + * + * @note Blocking return mode cannot be used in combination with ::ADCBuf_RECURRENCE_MODE_CONTINUOUS + */ + ADCBuf_RETURN_MODE_BLOCKING, + + /*! + * Non-blocking and will return immediately. When the conversion + * is finished the configured callback function is called. + */ + ADCBuf_RETURN_MODE_CALLBACK +} ADCBuf_Return_Mode; + + +/*! + * @brief ADC Parameters + * + * ADC Parameters are used to with the ADCBuf_open() call. Default values for + * these parameters are set using ADCBuf_Params_init(). + * + * @sa ADCBuf_Params_init() + */ +typedef struct ADCBuf_Params_ { + uint32_t blockingTimeout; /*!< Timeout for semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */ + uint32_t samplingFrequency; /*!< The frequency at which the ADC will produce a sample */ + ADCBuf_Return_Mode returnMode; /*!< Return mode for all conversions */ + ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */ + ADCBuf_Recurrence_Mode recurrenceMode; /*!< One-shot or continuous conversion */ + void *custom; /*!< Pointer to a device specific extension of the ADCBuf_Params */ +} ADCBuf_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * ADCBuf_close(). + */ +typedef void (*ADCBuf_CloseFxn) (ADCBuf_Handle handle); + + +/*! + * @brief A function pointer to a driver specific implementation of + * ADCBuf_open(). + */ +typedef ADCBuf_Handle (*ADCBuf_OpenFxn) (ADCBuf_Handle handle, + const ADCBuf_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADCBuf_control(). + */ +typedef int_fast16_t (*ADCBuf_ControlFxn) (ADCBuf_Handle handle, + uint_fast8_t cmd, + void *arg); +/* + * @brief A function pointer to a driver specific implementation of + * ADCBuf_init(). + */ +typedef void (*ADCBuf_InitFxn) (ADCBuf_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADCBuf_convert(). + */ +typedef int_fast16_t (*ADCBuf_ConvertFxn) (ADCBuf_Handle handle, + ADCBuf_Conversion conversions[], + uint_fast8_t channelCount); +/*! + * @brief A function pointer to a driver specific implementation of + * ADCBuf_convertCancel(). + */ +typedef int_fast16_t (*ADCBuf_ConvertCancelFxn)(ADCBuf_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADCBuf_GetResolution(); + */ +typedef uint_fast8_t (*ADCBuf_GetResolutionFxn) (ADCBuf_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADCBuf_adjustRawValues(); + */ +typedef int_fast16_t (*ADCBuf_adjustRawValuesFxn)(ADCBuf_Handle handle, + void *sampleBuffer, + uint_fast16_t sampleCount, + uint32_t adcChannel); + +/*! + * @brief A function pointer to a driver specific implementation of + * ADCBuf_convertAdjustedToMicroVolts(); + */ +typedef int_fast16_t (*ADCBuf_convertAdjustedToMicroVoltsFxn) (ADCBuf_Handle handle, + uint32_t adcChannel, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount); + +/*! + * @brief The definition of an ADCBuf function table that contains the + * required set of functions to control a specific ADC driver + * implementation. + */ +typedef struct ADCBuf_FxnTable_ { + /*! Function to close the specified peripheral */ + ADCBuf_CloseFxn closeFxn; + /*! Function to driver implementation specific control function */ + ADCBuf_ControlFxn controlFxn; + /*! Function to initialize the given data object */ + ADCBuf_InitFxn initFxn; + /*! Function to open the specified peripheral */ + ADCBuf_OpenFxn openFxn; + /*! Function to start an ADC conversion with the specified peripheral */ + ADCBuf_ConvertFxn convertFxn; + /*! Function to abort a conversion being carried out by the specified peripheral */ + ADCBuf_ConvertCancelFxn convertCancelFxn; + /*! Function to get the resolution in bits of the ADC */ + ADCBuf_GetResolutionFxn getResolutionFxn; + /*! Function to adjust raw ADC return bit values to values comparable between devices of the same type */ + ADCBuf_adjustRawValuesFxn adjustRawValuesFxn; + /*! Function to convert adjusted ADC values to microvolts */ + ADCBuf_convertAdjustedToMicroVoltsFxn convertAdjustedToMicroVoltsFxn; +} ADCBuf_FxnTable; + +/*! + * @brief ADCBuf Global configuration + * + * The ADCBuf_Config structure contains a set of pointers used to characterise + * the ADC driver implementation. + * + * This structure needs to be defined before calling ADCBuf_init() and it must + * not be changed thereafter. + * + * @sa ADCBuf_init() + */ +typedef struct ADCBuf_Config_ { + /*! Pointer to a table of driver-specific implementations of ADC APIs */ + const ADCBuf_FxnTable *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ADCBuf_Config; + +/*! + * @brief Function to close an ADC peripheral specified by the ADC handle + * + * @pre ADCBuf_open() has to be called first. + * + * @pre In ADCBuf_RECURRENCE_MODE_CONTINUOUS, the application must call ADCBuf_convertCancel() first. + * + * @param handle An ADCBuf handle returned from ADCBuf_open() + * + * @sa ADCBuf_open() + */ +extern void ADCBuf_close(ADCBuf_Handle handle); + + +/*! + * @brief Function performs implementation specific features on a given + * ADCBuf_Handle. + * + * @pre ADCBuf_open() has to be called first. + * + * @param handle An ADCBuf handle returned from ADCBuf_open() + * + * @param cmd A command value defined by the driver specific + * implementation + * + * @param cmdArg A pointer to an optional R/W (read/write) argument that + * is accompanied with cmd + * + * @return An ADCBuf_Status describing an error or success state. Negative values + * indicates an error. + * + * @sa ADCBuf_open() + */ +extern int_fast16_t ADCBuf_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *cmdArg); + +/*! + * @brief This function initializes the ADC module. This function must + * + * @pre The ADCBuf_Config structure must exist and be persistent before this + * function can be called. + * This function call does not modify any peripheral registers. + * Function should only be called once. + */ +extern void ADCBuf_init(void); + +/*! + * @brief This function sets all fields of a specified ADCBuf_Params structure to their + * default values. + * + * @param params A pointer to ADCBuf_Params structure for initialization + * + * Default values are: + * returnMode = ADCBuf_RETURN_MODE_BLOCKING, + * blockingTimeout = 25000, + * callbackFxn = NULL, + * recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT, + * samplingFrequency = 10000, + * custom = NULL + * + * ADCBuf_Params::blockingTimeout should be set large enough to allow for the desired number of samples to be + * collected with the specified frequency. + */ +extern void ADCBuf_Params_init(ADCBuf_Params *params); + +/*! + * @brief This function opens a given ADCBuf peripheral. + * + * @param index Logical peripheral number for the ADCBuf indexed into + * the ADCBuf_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An ADCBuf_Handle on success or a NULL on an error or if it has been + * opened already. If NULL is returned further ADC API calls will + * result in undefined behaviour. + * + * @sa ADCBuf_close() + */ +extern ADCBuf_Handle ADCBuf_open(uint_least8_t index, ADCBuf_Params *params); + +/*! + * @brief This function starts a set of conversions on one or more channels. + * + * @param handle An ADCBuf handle returned from ADCBuf_open() + * + * @param conversions A pointer to an array of ADCBuf_Conversion structs with the specific parameters + * for each channel. Only use one ADCBuf_Conversion struct per channel. + * + * @param channelCount The number of channels to convert on in this call. Should be the length of the conversions array. + * Depending on the device, multiple simultaneous conversions may not be supported. See device + * specific implementation. + * + * @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise. + * + * @pre ADCBuf_open() must have been called prior. + * + * @sa ADCBuf_convertCancel() + */ +extern int_fast16_t ADCBuf_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount); + +/*! + * @brief This function cancels an ADC conversion that is in progress. + * + * This function must be called before calling ADCBuf_close(). + * + * @param handle An ADCBuf handle returned from ADCBuf_open() + * + * @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise. + * + * @sa ADCBuf_convert() + */ +extern int_fast16_t ADCBuf_convertCancel(ADCBuf_Handle handle); + +/*! + * @brief This function returns the resolution in bits of the specified ADC. + * + * @param handle An ADCBuf handle returned from ADCBuf_open(). + * + * @return The resolution in bits of the specified ADC. + * + * @pre ADCBuf_open() must have been called prior. + */ +extern uint_fast8_t ADCBuf_getResolution(ADCBuf_Handle handle); + + /*! + * @brief This function adjusts a raw ADC output buffer such that the result is comparable between devices of the same make. + * The function does the adjustment in-place. + * + * @param handle An ADCBuf handle returned from ADCBuf_open(). + * + * @param sampleBuf A buffer full of raw sample values. + * + * @param sampleCount The number of samples to adjust. + * + * @param adcChan The channel the buffer was sampled on. + * + * @return A buffer full of adjusted samples contained in sampleBuffer. + * + * @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise. + * + * @pre ADCBuf_open() must have been called prior. + */ +extern int_fast16_t ADCBuf_adjustRawValues(ADCBuf_Handle handle, void *sampleBuf, uint_fast16_t sampleCount, uint32_t adcChan); + + /*! + * @brief This function converts a raw ADC output value to a value scaled in micro volts. + * + * @param handle An ADCBuf handle returned from ADCBuf_open() + * + * @param adcChan The ADC channel the samples stem from. This parameter is only necessary for certain devices. + * See device specific implementation for details. + * + * @param adjustedSampleBuffer A buffer full of adjusted samples. + * + * @param outputMicroVoltBuffer The output buffer. The conversion does not occur in place due to the differing data type sizes. + * + * @param sampleCount The number of samples to convert. + * + * @return A number of measurements scaled in micro volts inside outputMicroVoltBuffer. + * + * @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise. + * + * @pre ADCBuf_open() must have been called prior. + * + * @pre ADCBuf_adjustRawValues() must be called on adjustedSampleBuffer prior. + */ +extern int_fast16_t ADCBuf_convertAdjustedToMicroVolts(ADCBuf_Handle handle, uint32_t adcChan, void *adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount); + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_adcbuf__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Camera.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Camera.h new file mode 100644 index 000000000..1c6072e0e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Camera.h @@ -0,0 +1,651 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file Camera.h + * + * @brief Camera driver interface + * + * The Camera header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The Camera driver is used to retrieve the data being transferred by the + * Camera sensor. + * This driver provides an API for capturing the image from the Camera sensor. + * The camera sensor control and implementation are the responsibility of the + * application using the interface. + * + * The Camera driver has been designed to operate in an RTOS environment. It + * protects its transactions with OS primitives supplied by the underlying + * RTOS. + * + * # Usage # + * + * The Camera driver includes the following APIs: + * - Camera_init(): Initialize the Camera driver. + * - Camera_Params_init(): Initialize a #Camera_Params structure with default + * vaules. + * - Camera_open(): Open an instance of the Camera driver. + * - Camera_control(): Performs implemenation-specific features on a given + * Camera peripheral. + * - Camera_capture(): Capture a frame. + * - Camera_close(): De-initialize a given Camera instance. + * + * + * ### Camera Driver Configuration # + * + * In order to use the Camera APIs, the application is required + * to provide device-specific Camera configuration in the Board.c file. + * The Camera driver interface defines a configuration data structure: + * + * @code + * typedef struct Camera_Config_ { + * Camera_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } Camera_Config; + * @endcode + * + * The application must declare an array of Camera_Config elements, named + * Camera_config[]. Each element of Camera_config[] must be populated with + * pointers to a device specific Camera driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the Camera peripheral's base address. + * Each element in Camera_config[] corresponds to + * a Camera instance, and none of the elements should have NULL pointers. + * There is no correlation between the index and the + * peripheral designation (such as Camera0 or Camera1). For example, it + * is possible to use Camera_config[0] for Camera1. + * + * Because the Camera configuration is very device dependent, you will need to + * check the doxygen for the device specific Camera implementation. There you + * will find a description of the Camera hardware attributes. Please also + * refer to the Board.c file of any of your examples to see the Camera + * configuration. + * + * ### Initializing the Camear Driver # + * The application initializes the Camera driver by calling Camera_init(). + * This function must be called before any other Camera API. Camera_init() + * iterates through the elements of the Camera_config[] array, calling + * the element's device implementation Camera initialization function. + * ### Camera Parameters + * + * The #Camera_Params structure is passed to Camera_open(). If NULL + * is passed for the parameters, Camera_open() uses default parameters. + * A #Camera_Params structure is initialized with default values by passing + * it to Camera_Params_init(). + * Some of the Camera parameters are described below. To see brief descriptions + * of all the parameters, see #Camera_Params. + * + * #### Camera Modes + * The Camera driver operates in either blocking mode or callback mode: + * - #Camera_MODE_BLOCKING: The call to Camera_capture() blocks until the + * capture has completed. + * - #Camera_MODE_CALLBACK: The call to Camera_capture() returns immediately. + * When the capture completes, the Camera driver will call a user- + * specified callback function. + * + * The capture mode is determined by the #Camera_Params.captureMode parameter + * passed to Camera_open(). The Camera driver defaults to blocking mode, if the + * application does not set it. + * + * Once a Camera driver instance is opened, the only way + * to change the capture mode is to close and re-open the Camera + * instance with the new capture mode. + * + * ### Opening the driver # + * The following example opens a Camera driver instance in blocking mode: + * @code + * Camera_Handle handle; + * Camera_Params params; + * + * Camera_Params_init(¶ms); + * params.captureMode = Camera_MODE_BLOCKING; + * < Change any other params as required > + * + * handle = Camera_open(someCamera_configIndexValue, ¶ms); + * if (!handle) { + * // Error opening the Camera driver + * } + * @endcode + * + * ### Capturing an Image # + * + * The following code example captures a frame. + * + * @code + * unsigned char captureBuffer[1920]; + * + * ret = Camera_capture(handle, &captureBuffer, sizeof(captureBuffer)); + * @endcode + * + * # Implementation # + * + * This module serves as the main interface for RTOS + * applications. Its purpose is to redirect the module's APIs to specific + * peripheral implementations which are specified using a pointer to a + * #Camera_FxnTable. + * + * The Camera driver interface module is joined (at link time) to an + * array of #Camera_Config data structures named *Camera_config*. + * *Camera_config* is implemented in the application with each entry being an + * instance of a Camera peripheral. Each entry in *Camera_config* contains a: + * - (Camera_FxnTable *) to a set of functions that implement a Camera + * peripheral + * - (void *) data object that is associated with the Camera_FxnTable + * - (void *) hardware attributes that are associated to the Camera_FxnTable + * + ******************************************************************************* + */ + +#ifndef ti_drivers_Camera__include +#define ti_drivers_Camera__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @defgroup CAMERA_CONTROL Camera_control command and status codes + * These Camera macros are reservations for Camera.h + * @{ + */ + +/*! + * Common Camera_control command code reservation offset. + * Camera driver implementations should offset command codes with + * CAMERA_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define CAMERAXYZ_CMD_COMMAND0 CAMERA_CMD_RESERVED + 0 + * #define CAMERAXYZ_CMD_COMMAND1 CAMERA_CMD_RESERVED + 1 + * @endcode + */ +#define CAMERA_CMD_RESERVED (32) + +/*! + * Common Camera_control status code reservation offset. + * Camera driver implementations should offset status codes with + * CAMERA_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define CAMERAXYZ_STATUS_ERROR0 CAMERA_STATUS_RESERVED - 0 + * #define CAMERAXYZ_STATUS_ERROR1 CAMERA_STATUS_RESERVED - 1 + * #define CAMERAXYZ_STATUS_ERROR2 CAMERA_STATUS_RESERVED - 2 + * @endcode + */ +#define CAMERA_STATUS_RESERVED (-32) + +/** + * @defgroup Camera_STATUS Status Codes + * Camera_STATUS_* macros are general status codes returned by Camera_control() + * @{ + * @ingroup Camera_CONTROL + */ + +/*! + * @brief Successful status code returned by Camera_control(). + * + * Camera_control() returns CAMERA_STATUS_SUCCESS if the control code was + * executed successfully. + */ +#define CAMERA_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by Camera_control(). + * + * Camera_control() returns CAMERA_STATUS_ERROR if the control code was not + * executed successfully. + */ +#define CAMERA_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by Camera_control() for undefined + * command codes. + * + * Camera_control() returns CAMERA_STATUS_UNDEFINEDCMD if the control code is + * not recognized by the driver implementation. + */ +#define CAMERA_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup Camera_CMD Command Codes + * Camera_CMD_* macros are general command codes for Camera_control(). Not all + * Camera driver implementations support these command codes. + * @{ + * @ingroup Camera_CONTROL + */ + +/* Add Camera_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief Wait forever define + */ +#define Camera_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from a Camera_open() call. + */ +typedef struct Camera_Config_ *Camera_Handle; + +/*! + * @brief The definition of a callback function used by the Camera driver + * when used in ::Camera_MODE_CALLBACK + * + * @param Camera_Handle Camera_Handle + * + * @param buf Pointer to capture buffer + * + * @param frameLength length of frame + * + */ +typedef void (*Camera_Callback) (Camera_Handle handle, void *buf, + size_t frameLength); + +/*! + * @brief Camera capture mode settings + * + * This enum defines the capture mode for the + * configured Camera. + */ +typedef enum Camera_CaptureMode_ { + /*! + * Uses a semaphore to block while data is being sent. Context of + * the call must be a Task. + */ + Camera_MODE_BLOCKING, + + /*! + * Non-blocking and will return immediately. When the capture + * by the interrupt is finished the configured callback function + * is called. + */ + Camera_MODE_CALLBACK +} Camera_CaptureMode; + +/*! + * @brief Camera HSync polarity + * + * This enum defines the polarity of the HSync signal. + */ +typedef enum Camera_HSyncPolarity_ { + Camera_HSYNC_POLARITY_HIGH = 0, + Camera_HSYNC_POLARITY_LOW +} Camera_HSyncPolarity; + +/*! + * @brief Camera VSync polarity + * + * This enum defines the polarity of the VSync signal. + */ +typedef enum Camera_VSyncPolarity_ { + Camera_VSYNC_POLARITY_HIGH = 0, + Camera_VSYNC_POLARITY_LOW +} Camera_VSyncPolarity; + +/*! + * @brief Camera pixel clock configuration + * + * This enum defines the pixel clock configuration. + */ +typedef enum Camera_PixelClkConfig_ { + Camera_PCLK_CONFIG_RISING_EDGE = 0, + Camera_PCLK_CONFIG_FALLING_EDGE +} Camera_PixelClkConfig; + +/*! + * @brief Camera byte order + * + * This enum defines the byte order of camera capture. + * + * In normal mode, the byte order is: + * | byte3 | byte2 | byte1 | byte0 | + * + * In swap mode, the bytes are ordered as: + * | byte2 | byte3 | byte0 | byte1 | + */ +typedef enum Camera_ByteOrder_ { + Camera_BYTE_ORDER_NORMAL = 0, + Camera_BYTE_ORDER_SWAP +} Camera_ByteOrder; + +/*! + * @brief Camera interface synchronization + * + * This enum defines the sensor to camera interface synchronization + * configuration. + */ +typedef enum Camera_IfSynchoronisation_ { + Camera_INTERFACE_SYNC_OFF = 0, + Camera_INTERFACE_SYNC_ON +} Camera_IfSynchoronisation; + +/*! + * @brief Camera stop capture configuration + * + * This enum defines the stop capture configuration. + */ +typedef enum Camera_StopCaptureConfig_ { + Camera_STOP_CAPTURE_IMMEDIATE = 0, + Camera_STOP_CAPTURE_FRAME_END +} Camera_StopCaptureConfig; + +/*! + * @brief Camera start capture configuration + * + * This enum defines the start capture configuration. + */ +typedef enum Camera_StartCaptureConfig_ { + Camera_START_CAPTURE_IMMEDIATE = 0, + Camera_START_CAPTURE_FRAME_START +} Camera_StartCaptureConfig; + +/*! + * @brief Camera Parameters + * + * Camera parameters are used to with the Camera_open() call. + * Default values for these parameters are set using Camera_Params_init(). + * + * If Camera_CaptureMode is set to Camera_MODE_BLOCKING then Camera_capture + * function calls will block thread execution until the capture has completed. + * + * If Camera_CaptureMode is set to Camera_MODE_CALLBACK then Camera_capture + * will not block thread execution and it will call the function specified by + * captureCallbackFxn. + * + * @sa Camera_Params_init() + */ +typedef struct Camera_Params_ { + /*!< Mode for camera capture */ + Camera_CaptureMode captureMode; + + /*!< Output clock to set divider */ + uint32_t outputClock; + + /*!< Polarity of Hsync */ + Camera_HSyncPolarity hsyncPolarity; + + /*!< Polarity of VSync */ + Camera_VSyncPolarity vsyncPolarity; + + /*!< Pixel clock configuration */ + Camera_PixelClkConfig pixelClkConfig; + + /*!< camera capture byte order */ + Camera_ByteOrder byteOrder; + + /*!< Camera-Sensor synchronization */ + Camera_IfSynchoronisation interfaceSync; + + /*!< Camera stop configuration */ + Camera_StopCaptureConfig stopConfig; + + /*!< Camera start configuration */ + Camera_StartCaptureConfig startConfig; + + /*!< Timeout for capture semaphore */ + uint32_t captureTimeout; + + /*!< Pointer to capture callback */ + Camera_Callback captureCallback; + + /*!< Custom argument used by driver implementation */ + void *custom; +} Camera_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * Camera_close(). + */ +typedef void (*Camera_CloseFxn) (Camera_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Camera_control(). + */ +typedef int_fast16_t (*Camera_ControlFxn) (Camera_Handle handle, + uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * Camera_init(). + */ +typedef void (*Camera_InitFxn) (Camera_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Camera_open(). + */ +typedef Camera_Handle (*Camera_OpenFxn) (Camera_Handle handle, + Camera_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * Camera_capture(). + */ +typedef int_fast16_t (*Camera_CaptureFxn) (Camera_Handle handle, void *buffer, + size_t bufferlen, size_t *frameLen); + +/*! + * @brief The definition of a Camera function table that contains the + * required set of functions to control a specific Camera driver + * implementation. + */ +typedef struct Camera_FxnTable_ { + /*! Function to close the specified peripheral */ + Camera_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + Camera_ControlFxn controlFxn; + + /*! Function to initialize the given data object */ + Camera_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + Camera_OpenFxn openFxn; + + /*! Function to initiate a Camera capture */ + Camera_CaptureFxn captureFxn; +} Camera_FxnTable; + +/*! + * @brief Camera Global configuration + * + * The Camera_Config structure contains a set of pointers used to characterize + * the Camera driver implementation. + * + * This structure needs to be defined before calling Camera_init() and it must + * not be changed thereafter. + * +* @sa Camera_init() + */ +typedef struct Camera_Config_ { + /*! Pointer to a table of driver-specific implementations of Camera APIs */ + Camera_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} Camera_Config; + +/*! + * @brief Function to close a Camera peripheral specified by the Camera handle + * + * @pre Camera_open() had to be called first. + * + * @param handle A Camera_Handle returned from Camera_open + * + * @sa Camera_open() + */ +extern void Camera_close(Camera_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * Camera_Handle. + * + * Commands for Camera_control can originate from Camera.h or from + * implementation specific Camera*.h (_CameraCC32XX.h_, etc.. ) files. + * While commands from Camera.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific Camera*.h files add + * unique driver capabilities but are not API portable across all Camera driver + * implementations. + * + * Commands supported by Camera.h follow a Camera_CMD_\ naming + * convention.
+ * Commands supported by Camera*.h follow a Camera*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref Camera_CMD "Camera_control command codes" for command codes. + * + * See @ref Camera_STATUS "Camera_control return status codes" for status codes. + * + * @pre Camera_open() has to be called first. + * + * @param handle A Camera handle returned from Camera_open() + * + * @param cmd Camera.h or Camera*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa Camera_open() + */ +extern int_fast16_t Camera_control(Camera_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief Function to initializes the Camera module + * + * @pre The Camera_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other Camera driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void Camera_init(void); + +/*! + * @brief Function to initialize a given Camera peripheral specified by the + * particular index value. The parameter specifies which mode the + * Camera will operate. + * + * @pre Camera controller has been initialized + * + * @param index Logical peripheral number for the Camera indexed into + * the Camera_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A Camera_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa Camera_init() + * @sa Camera_close() + */ +extern Camera_Handle Camera_open(uint_least8_t index, Camera_Params *params); + +/*! + * @brief Function to initialize the Camera_Params structure to its defaults + * + * @param params An pointer to Camera_Params structure for + * initialization + * + * Defaults values are: + * captureMode = Camera_MODE_BLOCKING; + * outputClock = 24000000; + * hsyncPolarity = Camera_HSYNC_POLARITY_HIGH; + * vsyncPolarity = Camera_VSYNC_POLARITY_HIGH; + * pixelClkConfig = Camera_PCLK_CONFIG_RISING_EDGE; + * byteOrder = Camera_BYTE_ORDER_NORMAL; + * interfaceSync = Camera_INTERFACE_SYNC_ON; + * stopConfig = Camera_STOP_CAPTURE_FRAME_END; + * startConfig = Camera_START_CAPTURE_FRAME_START; + * captureTimeout = Camera_WAIT_FOREVER; + * captureCallback = NULL; + */ +extern void Camera_Params_init(Camera_Params *params); + +/*! + * @brief Function that handles the Camera capture of a frame. + * + * In Camera_MODE_BLOCKING, Camera_capture will block task execution until + * the capture is complete. + * + * In Camera_MODE_CALLBACK, Camera_capture does not block task execution + * and calls a callback function specified by captureCallbackFxn. + * The Camera buffer must stay persistent until the Camera_capture + * function has completed! + * + * @param handle A Camera_Handle + * + * @param buffer A pointer to a WO (write-only) buffer into which the + * captured frame is placed + * + * @param bufferlen Length (in bytes) of the capture buffer + * + * @param frameLen Pointer to return number of bytes captured. + * + * @return CAMERA_STATUS_SUCCESS on successful capture, CAMERA_STATUS_ERROR if + * if otherwise. + * + * @sa Camera_open + */ +extern int_fast16_t Camera_capture(Camera_Handle handle, void *buffer, + size_t bufferlen, size_t *frameLen); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Camera__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Capture.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Capture.h new file mode 100644 index 000000000..1176b5392 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Capture.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file Capture.h + * + * @brief Capture driver interface + * + * The Capture header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * The Capture driver facilitates the capture routines by using general purpose + * timers. Capture instances must be opened by calling Capture_open() while + * passing in a Capture index and parameters data structure. + * + * When a capture instance is opened, the capture triggering edge and callback + * function are configured. The capture is stopped after calling Capture_open() + * until Capture_start() is called. + * + * When Capture_open() is called, it tries to occupy the user-specified timer by + * calling Timer_open(). If that timer is already allocated for other modules, + * NULL is returned. Otherwise, the Capture_Handle is returned. + + * A capture is triggered based on the user-specified capture mode: + * - CAPTURE_MODE_RISING_RISING + * - CAPTURE_MODE_RISING_FALLING + * - CAPTURE_MODE_ANY_EDGE + * The user-specified callback function is called once the input signal matches + * the capture mode and the value passed into callback function is the interval + * between two triggering edge in the user-specified unit. + * + * ## opening the driver ## + * + * @code + * Capture_Handle handle; + * Capture_Params params; + * + * Capture_Params_init(¶ms); + * params.mode = CAPTURE_MODE_RISING_FALLING; + * params.callbackFxn = someCaptureCallbackFunction; + * params.periodUnit = CAPTURE_PERIOD_US; + * handle = Capture_open(someCapture_configIndexValue, ¶ms); + * if (!handle) + * { + * System_printf("Capture did not open"); + * } + * + * ## starting the driver ## + + * @code + * status = Capture_start(handle); + * if (status == Capture_STATUS_ERROR) + * { + * System_printf("Capture cannot start"); + * } + * @endcode + * + * ## stoping the driver ## + * + * @code + * Capture_stop(handle); + * @endcode + * + * ## closing the driver ## + * + * @code + * Capture_close(handle); + * @endcode + * + * # Implementation # + * + * This module serves as the main interface for TI-RTOS + * applications. Its purpose is to redirect the module's APIs to specific + * peripheral implementations which are specified using a pointer to a + * Capture_FxnTable. + * + * The Capture driver interface module is joined (at link time) to a + * NULL-terminated array of Capture_Config data structures named *Capture_Config*. + * *Capture_Config* is implemented in the application with each entry being an + * instance of a Capture module. Each entry in *Capture_Config* contains a: + * - (Capture_FxnTable *) to a set of functions that implement a Capture module + * - (void *) data object that is associated with the Capture_FxnTable + * - (void *) hardware attributes that are associated to the Capture_FxnTable + * + * # Instrumentation # + * The Capture driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic operations performed | + * Diags_USER2 | detailed operations performed | + * + * ============================================================================ + */ +#ifndef ti_drivers_Capture__include +#define ti_drivers_Capture__include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +/*! + * @brief A handle that is returned from a Capture_open() call. + */ +typedef struct Capture_Config_ *Capture_Handle; + +/*! + * Common Capture_control command code reservation offset. + * Capture driver implementations should offset command codes with CAPTURE_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define CAPTUREXYZ_CMD_COMMAND0 CAPTURE_CMD_RESERVED + 0 + * #define CAPTUREXYZ_CMD_COMMAND1 CAPTURE_CMD_RESERVED + 1 + * @endcode + */ +#define CAPTURE_CMD_RESERVED (32) + +/*! + * Common Capture_control status code reservation offset. + * Capture driver implementations should offset status codes with + * CAPTURE_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define CAPTUREXYZ_STATUS_ERROR0 CAPTURE_STATUS_RESERVED - 0 + * #define CAPTUREXYZ_STATUS_ERROR1 CAPTURE_STATUS_RESERVED - 1 + * #define CAPTUREXYZ_STATUS_ERROR2 CAPTURE_STATUS_RESERVED - 2 + * @endcode + */ +#define CAPTURE_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code returned by Capture_control(). + * + * Capture_control() returns TIMER_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define CAPTURE_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by Capture_control(). + * + * Capture_control() returns CAPTURE_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define CAPTURE_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by Capture_control() for undefined + * command codes. + * + * Capture_control() returns TIMER_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define CAPTURE_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief Capture period unit enum + * + * The Capture period unit needs to be passed in Capture_open() to + * specify the unit of two capture triggering interval. + * + */ +typedef enum Capture_Period_Unit_ { + CAPTURE_PERIOD_US, /* Period in microseconds */ + CAPTURE_PERIOD_HZ, /* Period in frequency */ + CAPTURE_PERIOD_COUNTS, /* Period in counts */ +} Capture_Period_Unit; + +/*! + * @brief Capture mode enum + * + * The Capture mode needs to be passed in Capture_open() to specify the capture + * triggering mode. + * + */ +typedef enum Capture_Mode_ { + CAPTURE_MODE_RISING_RISING, /*!< capture is triggered at the rising edge followed by the rising edge */ + CAPTURE_MODE_FALLING_FALLING, /*!< capture is triggered at the falling edge followed by the falling edge */ + CAPTURE_MODE_ANY_EDGE + /*!< capture is triggered at the falling edge followed by the rising edge */ +} Capture_Mode; + +/*! + * @brief Capture callback function + * + * User definable callback function prototype. The Capture driver will call the + * defined function and pass in the Capture driver's handle and the pointer to the + * user-specified the argument. + * + * @param handle Capture_Handle + * + * @param interval Interval of two triggering edge in Capture_Period_Unit + * + */ +typedef void (*Capture_CallBackFxn)(Capture_Handle handle, uint32_t interval); + +/*! + * @brief Capture Parameters + * + * Capture parameters are used to with the Capture_open() call. Default values for + * these parameters are set using Capture_Params_init(). + * + */ +typedef struct Capture_Params_ { + Capture_Mode mode; /*!< Capture triggering mode */ + Capture_CallBackFxn callbackFxn; /*!< Callback function pointer */ + Capture_Period_Unit periodUnit; /*!< Period unit */ +} Capture_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * Capture_close(). + */ +typedef void (*Capture_CloseFxn)(Capture_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Capture_control(). + */ +typedef int_fast16_t (*Capture_ControlFxn)(Capture_Handle handle, + uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * Capture_init(). + */ +typedef void (*Capture_InitFxn)(Capture_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Capture_open(). + */ +typedef Capture_Handle (*Capture_OpenFxn)(Capture_Handle handle, + Capture_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * Capture_start(). + */ +typedef void (*Capture_StartFxn)(Capture_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Capture_stop(). + */ +typedef void (*Capture_StopFxn)(Capture_Handle handle); + +/*! + * @brief The definition of a Capture function table that contains the + * required set of functions to control a specific Capture driver + * implementation. + */ +typedef struct Capture_FxnTable_ { + /*! Function to close the specified peripheral */ + Capture_CloseFxn closeFxn; + + /*! Function to send control commands to the specified peripheral */ + Capture_ControlFxn controlFxn; + + /*! Function to initialize the specified peripheral */ + Capture_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + Capture_OpenFxn openFxn; + + /*! Function to start the specified peripheral */ + Capture_StartFxn startFxn; + + /*! Function to stop the specified peripheral */ + Capture_StopFxn stopFxn; + +} Capture_FxnTable; + +typedef struct Capture_Config_ { + Capture_FxnTable const *fxnTablePtr; + void *object; + void const *hwAttrs; +} Capture_Config; + +/*! + * @brief Function to close a Capture module specified by the Capture handle + * + * The function takes care of timer resource allocation. The corresponding timer + * resource to the Capture_Handle is released to be an available timer resource. + * + * @pre Capture_open() had to be called first. + * + * @param handle A Capture_Handle returned from Capture_open + * + * @sa Capture_open() + */ +extern void Capture_close(Capture_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * Capture_Handle. + * + * @pre Capture_open() must have been called first. + * + * @param handle A Capture_Handle returned from Capture_open(). + * + * @param cmd A command value defined by the driver specific + * implementation. + * + * @param arg A pointer to an optional R/W (read/write) argument that + * is accompanied with cmd. + * + * @return A Capture_Status describing an error or success state. Negative values + * indicate an error occurred. + * + * @sa Capture_open() + */ +extern int_fast16_t Capture_control(Capture_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief Function to initialize Capture. + */ +extern void Capture_init(void); + +/*! + * @brief Function to initialize a given Capture module specified by the + * particular index value. The parameter specifies which mode the Capture + * will operate. + * + * The function takes care of timer resource allocation. If the particular timer + * passed by user has already been used by other modules, the return value is NULL. + * If the particular timer is available to use, Capture module owns it and returns + * a Capture_Handle. + * + * @param index Logical instance number for the Capture indexed into + * the Capture_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A Capture_Handle on success or a NULL on an error if it has been + * opened already or used by other modules. + * + * @sa Capture_init() + * @sa Capture_close() + */ +extern Capture_Handle Capture_open(uint_least8_t index, Capture_Params *params); + +/*! + * @brief Function to initialize the Capture_Params struct to its defaults + * + * @param params An pointer to Capture_Params structure for + * initialization + * + * Defaults values are: + * mode = CAPTURE_MODE_RISING_RISING + * callbackFxn = user_specified_callbackFxn + * periodUnit = Capture_PERIOD_COUNTS + */ +extern void Capture_Params_init(Capture_Params *params); + +/*! + * @brief Function to start capture. The Capture running mode + * and interval period unit are specfied in the Capture_Params when calling + * Capture_open(). + * + * @param handle Capture_Handle + * + * @return CAPTURE_STATUS_SUCCESS if Capture starts successfully. + * CAPTURE_STATUS_ERROR if Capture fails to start. + * + */ +extern void Capture_start(Capture_Handle handle); + +/*! + * @brief Function to stop Capture after Capture_start() is called with success. + * + * @param handle Capture_Handle + * + */ +extern void Capture_stop(Capture_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Capture__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/GPIO.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/GPIO.h new file mode 100644 index 000000000..111c1ddb1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/GPIO.h @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file GPIO.h + * + * @brief GPIO driver + * + * The GPIO header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The GPIO module allows you to manage General Purpose I/O pins via simple + * and portable APIs. GPIO pin behavior is usually configured statically, + * but can also be configured or reconfigured at runtime. + * + * Because of its simplicity, the GPIO driver does not follow the model of + * other TI-RTOS drivers in which a driver application interface has + * separate device-specific implementations. This difference is most + * apparent in the GPIOxxx_Config structure, which does not require you to + * specify a particular function table or object. + * + * # Usage # + * The following code example demonstrates how + * to configure a GPIO pin to generate an interrupt and how to toggle an + * an LED on and off within the registered interrupt callback function. + * + * @code + * #include + * #include + * + * // Driver Header file + * #include + * + * // Example/Board Header file + * #include "Board.h" + * + * main() + * { + * // Call GPIO driver init function + * GPIO_init(); + * + * // Turn on user LED + * GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + * + * // install Button callback + * GPIO_setCallback(Board_GPIO_BUTTON0, gpioButtonFxn0); + * + * // Enable interrupts + * GPIO_enableInt(Board_GPIO_BUTTON0); + * + * ... + * } + * + * // + * // ======== gpioButtonFxn0 ======== + * // Callback function for the GPIO interrupt on Board_GPIO_BUTTON0. + * // + * void gpioButtonFxn0(unsigned int index) + * { + * // Toggle the LED + * GPIO_toggle(Board_GPIO_LED0); + * } + * + * @endcode + * + * Details for the example code above are described in the following + * subsections. + * + * ### GPIO Driver Configuration # + * + * In order to use the GPIO APIs, the application is required + * to provide 3 structures in the Board.c file: + * 1. An array of @ref GPIO_PinConfig elements that defines the + * initial configuration of each pin used by the application. A + * pin is referenced in the application by its corresponding index in this + * array. The pin type (that is, INPUT/OUTPUT), its initial state (that is + * OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.), and + * device specific pin identification are configured in each element + * of this array (see @ref GPIO_PinConfigSettings). + * Below is an MSP432 device specific example of the GPIO_PinConfig array: + * @code + * // + * // Array of Pin configurations + * // NOTE: The order of the pin configurations must coincide with what was + * // defined in MSP_EXP432P401R.h + * // NOTE: Pins not used for interrupts should be placed at the end of the + * // array. Callback entries can be omitted from callbacks array to + * // reduce memory usage. + * // + * GPIO_PinConfig gpioPinConfigs[] = { + * // Input pins + * // MSP_EXP432P401R_GPIO_S1 + * GPIOMSP432_P1_1 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING, + * // MSP_EXP432P401R_GPIO_S2 + * GPIOMSP432_P1_4 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING, + * + * // Output pins + * // MSP_EXP432P401R_GPIO_LED1 + * GPIOMSP432_P1_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + * // MSP_EXP432P401R_GPIO_LED_RED + * GPIOMSP432_P2_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + * }; + * @endcode + * + * 2. An array of @ref GPIO_CallbackFxn elements that is used to store + * callback function pointers for GPIO pins configured with interrupts. + * The indexes for these array elements correspond to the pins defined + * in the GPIO_pinConfig array. These function pointers can be defined + * statically by referencing the callback function name in the array + * element, or dynamically, by setting the array element to NULL and using + * GPIO_setCallback() at runtime to plug the callback entry. + * Pins not used for interrupts can be omitted from the callback array to + * reduce memory usage (if they are placed at the end of GPIO_pinConfig + * array). The callback function syntax should match the following: + * @code + * void (*GPIO_CallbackFxn)(unsigned int index); + * @endcode + * The index parameter is the same index that was passed to + * GPIO_setCallback(). This allows the same callback function to be used + * for multiple GPIO interrupts, by using the index to identify the GPIO + * that caused the interrupt. + * Keep in mind that the callback functions will be called in the context of + * an interrupt service routine and should be designed accordingly. When an + * interrupt is triggered, the interrupt status of all (interrupt enabled) pins + * on a port will be read, cleared, and the respective callbacks will be + * executed. Callbacks will be called in order from least significant bit to + * most significant bit. + * Below is an MSP432 device specific example of the GPIO_CallbackFxn array: + * @code + * // + * // Array of callback function pointers + * // NOTE: The order of the pin configurations must coincide with what was + * // defined in MSP_EXP432P401R.h + * // NOTE: Pins not used for interrupts can be omitted from callbacks array + * // to reduce memory usage (if placed at end of gpioPinConfigs + * // array). + * // + * GPIO_CallbackFxn gpioCallbackFunctions[] = { + * // MSP_EXP432P401R_GPIO_S1 + * NULL, + * // MSP_EXP432P401R_GPIO_S2 + * NULL + * }; + * @endcode + * + * 3. A device specific GPIOxxx_Config structure that tells the GPIO + * driver where the two aforementioned arrays are and the number of elements + * in each. The interrupt priority of all pins configured to generate + * interrupts is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + * Below is an MSP432 device specific example of a GPIOxxx_Config + * structure: + * @code + * // + * // MSP432 specific GPIOxxx_Config structure + * // + * const GPIOMSP432_Config GPIOMSP432_config = { + * .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + * .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + * .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + * .intPriority = (~0) + * }; + * @endcode + * + * ### Initializing the GPIO Driver # + * + * GPIO_init() must be called before any other GPIO APIs. This function + * configures each GPIO pin in the user-provided @ref GPIO_PinConfig + * array according to the defined settings. The user can also reconfigure + * a pin dynamically after GPIO_init() is called by using the + * GPIO_setConfig(), and GPIO_setCallback() APIs. + * + * # Implementation # + * + * Unlike most other TI-RTOS drivers, the GPIO driver has no generic function + * table with pointers to device-specific API implementations. All the generic + * GPIO APIs are implemented by the device-specific GPIO driver module. + * Additionally, there is no notion of an instance 'handle' with the GPIO driver. + * GPIO pins are referenced by their numeric index in the GPIO_PinConfig array. + * This design approach was used to enhance runtime and memory efficiency. + * + * ============================================================================ + */ + +#ifndef ti_drivers_GPIO__include +#define ti_drivers_GPIO__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @name GPIO_STATUS_* macros are general status codes returned by GPIO driver APIs. + * @{ + */ + +/*! + * @brief Common GPIO status code reservation offset. + * + * GPIO driver implementations should offset status codes with + * GPIO_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define GPIOTXYZ_STATUS_ERROR1 GPIO_STATUS_RESERVED - 1 + * #define GPIOTXYZ_STATUS_ERROR0 GPIO_STATUS_RESERVED - 0 + * #define GPIOTXYZ_STATUS_ERROR2 GPIO_STATUS_RESERVED - 2 + * @endcode + */ +#define GPIO_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code returned by GPI_setConfig(). + * + * GPI_setConfig() returns GPIO_STATUS_SUCCESS if the API was executed + * successfully. + */ +#define GPIO_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by GPI_setConfig(). + * + * GPI_setConfig() returns GPIO_STATUS_ERROR if the API was not executed + * successfully. + */ +#define GPIO_STATUS_ERROR (-1) +/** @}*/ + +/*! + * @brief GPIO pin configuration settings + * + * The upper 16 bits of the 32 bit PinConfig is reserved + * for pin configuration settings. + * + * The lower 16 bits are reserved for device-specific + * port/pin identifications + */ +typedef uint32_t GPIO_PinConfig; + +/*! + * @cond NODOC + * Internally used configuration bit access macros. + */ +#define GPIO_CFG_IO_MASK 0x00ff0000 +#define GPIO_CFG_IO_LSB 16 +#define GPIO_CFG_OUT_TYPE_MASK 0x00060000 +#define GPIO_CFG_OUT_TYPE_LSB 17 +#define GPIO_CFG_IN_TYPE_MASK 0x00060000 +#define GPIO_CFG_IN_TYPE_LSB 17 +#define GPIO_CFG_OUT_STRENGTH_MASK 0x00f00000 +#define GPIO_CFG_OUT_STRENGTH_LSB 20 +#define GPIO_CFG_INT_MASK 0x07000000 +#define GPIO_CFG_INT_LSB 24 +#define GPIO_CFG_OUT_BIT 19 +/*! @endcond */ + +/*! + * \defgroup GPIO_PinConfigSettings Macros used to configure GPIO pins + * @{ + */ +/** @name GPIO_PinConfig output pin configuration macros + * @{ + */ +#define GPIO_CFG_OUTPUT (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an output. */ +#define GPIO_CFG_OUT_STD (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is actively driven high and low */ +#define GPIO_CFG_OUT_OD_NOPULL (((uint32_t) 2) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain */ +#define GPIO_CFG_OUT_OD_PU (((uint32_t) 4) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull up */ +#define GPIO_CFG_OUT_OD_PD (((uint32_t) 6) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull dn */ + +#define GPIO_CFG_OUT_STR_LOW (((uint32_t) 0) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strengh to low */ +#define GPIO_CFG_OUT_STR_MED (((uint32_t) 1) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strengh to medium */ +#define GPIO_CFG_OUT_STR_HIGH (((uint32_t) 2) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strengh to high */ + +#define GPIO_CFG_OUT_HIGH (((uint32_t) 1) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 1. */ +#define GPIO_CFG_OUT_LOW (((uint32_t) 0) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 0. */ +/** @} */ + +/** @name GPIO_PinConfig input pin configuration macros + * @{ + */ +#define GPIO_CFG_INPUT (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an input. */ +#define GPIO_CFG_IN_NOPULL (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with no internal PU/PD */ +#define GPIO_CFG_IN_PU (((uint32_t) 3) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PU */ +#define GPIO_CFG_IN_PD (((uint32_t) 5) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PD */ +/** @} */ + +/** @name GPIO_PinConfig interrupt configuration macros + * @{ + */ +#define GPIO_CFG_IN_INT_NONE (((uint32_t) 0) << GPIO_CFG_INT_LSB) /*!< @hideinitializer No Interrupt */ +#define GPIO_CFG_IN_INT_FALLING (((uint32_t) 1) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on falling edge */ +#define GPIO_CFG_IN_INT_RISING (((uint32_t) 2) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on rising edge */ +#define GPIO_CFG_IN_INT_BOTH_EDGES (((uint32_t) 3) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on both edges */ +#define GPIO_CFG_IN_INT_LOW (((uint32_t) 4) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on low level */ +#define GPIO_CFG_IN_INT_HIGH (((uint32_t) 5) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on high level */ +/** @} */ + +/** @name Special GPIO_PinConfig configuration macros + * @{ + */ + +/*! + * @brief 'Or' in this @ref GPIO_PinConfig definition to inform GPIO_setConfig() + * to only configure the interrupt attributes of a GPIO input pin. + */ +#define GPIO_CFG_IN_INT_ONLY (((uint32_t) 1) << 27) /*!< @hideinitializer configure interrupt only */ + +/*! + * @brief Use this @ref GPIO_PinConfig definition to inform GPIO_init() + * NOT to configure the corresponding pin + */ +#define GPIO_DO_NOT_CONFIG 0x40000000 /*!< @hideinitializer Do not configure this Pin */ + +/** @} */ +/** @} end of GPIO_PinConfigSettings group */ + +/*! + * @brief GPIO callback function type + * + * @param index GPIO index. This is the same index that + * was passed to GPIO_setCallback(). This allows + * you to use the same callback function for multiple + * GPIO interrupts, by using the index to identify + * the GPIO that caused the interrupt. + */ +typedef void (*GPIO_CallbackFxn)(uint_least8_t index); + +/*! + * @brief Clear a GPIO pin interrupt flag + * + * Clears the GPIO interrupt for the specified index. + * + * Note: It is not necessary to call this API within a + * callback assigned to a pin. + * + * @param index GPIO index + */ +extern void GPIO_clearInt(uint_least8_t index); + +/*! + * @brief Disable a GPIO pin interrupt + * + * Disables interrupts for the specified GPIO index. + * + * @param index GPIO index + */ +extern void GPIO_disableInt(uint_least8_t index); + +/*! + * @brief Enable a GPIO pin interrupt + * + * Enables GPIO interrupts for the selected index to occur. + * + * Note: Prior to enabling a GPIO pin interrupt, make sure + * that a corresponding callback function has been provided. + * Use the GPIO_setCallback() API for this purpose at runtime. + * Alternatively, the callback function can be statically + * configured in the GPIO_CallbackFxn array provided. + * + * @param index GPIO index + */ +extern void GPIO_enableInt(uint_least8_t index); + +/*! + * @brief Get the current configuration for a gpio pin + * + * The pin configuration is provided in the static GPIO_PinConfig array, + * but can be changed with GPIO_setConfig(). GPIO_getConfig() gets the + * current pin configuration. + * + * @param index GPIO index + * @param pinConfig Location to store device specific pin + * configuration settings + */ +extern void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig); + +/*! + * @brief Initializes the GPIO module + * + * The pins defined in the application-provided *GPIOXXX_config* structure + * are initialized accordingly. + * + * @pre The GPIO_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other GPIO driver APIs. + */ +extern void GPIO_init(); + +/*! + * @brief Reads the value of a GPIO pin + * + * The value returned will either be zero or one depending on the + * state of the pin. + * + * @param index GPIO index + * + * @return 0 or 1, depending on the state of the pin. + */ +extern uint_fast8_t GPIO_read(uint_least8_t index); + +/*! + * @brief Bind a callback function to a GPIO pin interrupt + * + * Associate a callback function with a particular GPIO pin interrupt. + * + * Callbacks can be changed at any time, making it easy to switch between + * efficient, state-specific interrupt handlers. + * + * Note: The callback function is called within the context of an interrupt + * handler. + * + * Note: This API does not enable the GPIO pin interrupt. + * Use GPIO_enableInt() and GPIO_disableInt() to enable + * and disable the pin interrupt as necessary. + * + * Note: it is not necessary to call GPIO_clearInt() within a callback. + * That operation is performed internally before the callback is invoked. + * + * @param index GPIO index + * @param callback address of the callback function + */ +extern void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback); + +/*! + * @brief Configure the gpio pin + * + * Dynamically configure a gpio pin to a device specific setting. + * For many applications, the pin configurations provided in the static + * GPIO_PinConfig array is sufficient. + * + * For input pins with interrupt configurations, a corresponding interrupt + * object will be created as needed. + * + * @param index GPIO index + * @param pinConfig device specific pin configuration settings + */ +extern int_fast16_t GPIO_setConfig(uint_least8_t index, + GPIO_PinConfig pinConfig); + +/*! + * @brief Toggles the current state of a GPIO + * + * @param index GPIO index + */ +extern void GPIO_toggle(uint_least8_t index); + +/*! + * @brief Writes the value to a GPIO pin + * + * @param index GPIO index + * @param value must be either 0 or 1 + */ +extern void GPIO_write(uint_least8_t index, unsigned int value); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_GPIO__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2C.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2C.h new file mode 100644 index 000000000..592f8086e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2C.h @@ -0,0 +1,812 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file I2C.h + * + * @brief I2C driver interface + * + * The I2C driver interface provides device independent APIs, data types, + * and macros. The I2C header file should be included in an application as + * follows: + * @code + * #include + * @endcode + * + * # Overview # + * This section assumes that you have background knowledge and understanding + * about how the I2C protocol operates. For the full I2C specifications and + * user manual (UM10204), see the NXP Semiconductors website. + * + * The I2C driver has been designed to operate as a single I2C master by + * performing I2C transactions between the target and I2C slave peripherals. + * The I2C driver does not support I2C slave mode. + * I2C is a communication protocol - the specifications define how data + * transactions are to occur via the I2C bus. The specifications do not + * define how data is to be formatted or handled, allowing for flexible + * implementations across different peripheral vendors. As a result, the + * I2C handles only the exchange of data (or transactions) between master + * and slaves. It is the left to the application to interpret and + * manipulate the contents of each specific I2C peripheral. + * + * The I2C driver has been designed to operate in an RTOS environment. It + * protects its transactions with OS primitives supplied by the underlying + * RTOS. + * + * # Usage # + * + * The I2C driver includes the following APIs: + * - I2C_init(): Initialize the I2C driver. + * - I2C_Params_init(): Initialize an #I2C_Params structure with default + * vaules. + * - I2C_open(): Open an instance of the I2C driver. + * - I2C_control(): Performs implemenation-specific features on a given + * I2C peripheral. + * - I2C_transfer(): Transfer the data. + * - I2C_close(): De-initialize the I2C instance. + * + * + * ### I2C Driver Configuration # + * + * In order to use the I2C APIs, the application is required + * to provide device-specific I2C configuration in the Board.c file. + * The I2C driver interface defines a configuration data structure: + * + * @code + * typedef struct I2C_Config_ { + * I2C_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } I2C_Config; + * @endcode + * + * The application must declare an array of I2C_Config elements, named + * I2C_config[]. Each element of I2C_config[] must be populated with + * pointers to a device specific I2C driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the I2C peripheral's base address and + * pins. Each element in I2C_config[] corresponds to + * an I2C instance, and none of the elements should have NULL pointers. + * There is no correlation between the index and the + * peripheral designation (such as I2C0 or I2C1). For example, it is + * possible to use I2C_config[0] for I2C1. + * + * Because the I2C configuration is very device dependent, you will need to + * check the doxygen for the device specific I2C implementation. There you + * will find a description of the I2C hardware attributes. Please also + * refer to the Board.c file of any of your examples to see the I2C + * configuration. + * + * ### Initializing the I2C Driver # + * + * I2C_init() must be called before any other I2C APIs. This function + * iterates through the elements of the I2C_config[] array, calling + * the element's device implementation I2C initialization function. + * + * ### I2C Parameters + * + * The #I2C_Params structure is passed to the I2C_open() call. If NULL + * is passed for the parameters, I2C_open() uses default parameters. + * An #I2C_Params structure is initialized with default values by passing + * it to I2C_Params_init(). + * Some of the I2C parameters are described below. To see brief descriptions + * of all the parameters, see #I2C_Params. + * + * #### I2C Transfer Mode + * The I2C driver supports two transfer modes of operation: blocking and + * callback: + * - #I2C_MODE_BLOCKING: The call to I2C_transfer() blocks until the + * transfer completes. + * - #I2C_MODE_CALLBACK: The call to I2C_transfer() returns immediately. + * When the transfer completes, the I2C driver will call a user- + * specified callback function. + * + * The transfer mode is determined by the #I2C_Params.transferMode parameter + * passed to I2C_open(). The I2C driver defaults to blocking mode, if the + * application does not set it. + * + * In blocking mode, a task calling I2C_transfer() is blocked until the + * transaction completes. Other tasks requesting I2C transactions while + * a transaction is currently taking place, are also placed into a + * blocked state. + * + * In callback mode, an I2C_transfer() functions asynchronously, which + * means that it does not block a calling task's execution. In this + * mode, the user must set #I2C_Params.transferCallbackFxn to a user- + * provided callback function. After an I2C transaction has completed, + * the I2C driver calls the user- provided callback function. + * If another I2C transaction is requested, the transaction is queued up. + * As each transfer completes, the I2C driver will call the user-specified + * callback function. The user callback will be called from either hardware + * or software interrupt context, depending upon the device implementation. + * + * Once an I2C driver instance is opened, the + * only way to change the transfer mode is to close and re-open the I2C + * instance with the new transfer mode. + * + * #### Specifying an I2C Bus Frequency + * The I2C controller's bus frequency is determined by #I2C_Params.bitRate + * passed to I2C_open(). The standard I2C bus frequencies are 100 kHz and + * 400 kHz, with 100 kHz being the default. + * + * ### Opening the I2C Driver # + * After initializing the I2C driver by calling I2C_init(), the application + * can open an I2C instance by calling I2C_open(). This function + * takes an index into the I2C_config[] array and an I2C parameters data + * structure. The I2C instance is specified by the index of the I2C in + * I2C_config[]. Only one I2C index can be used at a time; + * calling I2C_open() a second time with the same index previosly + * passed to I2C_open() will result in an error. You can, + * though, re-use the index if the instance is closed via I2C_close(). + * + * If no I2C_Params structure is passed to I2C_open(), default values are + * used. If the open call is successful, it returns a non-NULL value. + * + * Example opening an I2C driver instance in blocking mode: + * @code + * I2C_Handle i2c; + * + * // NULL params are used, so default to blocking mode, 100 KHz + * i2c = I2C_open(Board_I2C0, NULL); + * + * if (!i2c) { + * // Error opening the I2C + * } + * @endcode + * + * Example opening an I2C driver instance in callback mode and 400KHz bit rate: + * + * @code + * I2C_Handle i2c; + * I2C_Params params; + * + * I2C_Params_init(¶ms); + * params.transferMode = I2C_MODE_CALLBACK; + * params.transferCallbackFxn = myCallbackFunction; + * params.bitRate = I2C_400kHz; + * + * handle = I2C_open(Board_I2C0, ¶ms); + * if (!i2c) { + * // Error opening I2C + * } + * @endcode + * + * ### Transferring data # + * An I2C transaction with an I2C peripheral is started by calling + * I2C_transfer(). Three types of transactions are supported: Write, Read, + * or Write/Read. Each transfer is completed before another transfer is + * initiated. + * + * For Write/Read transactions, the specified data is first written to the + * peripheral, then a repeated start is sent by the driver, which initiates + * the read operation. This type of transfer is useful if an I2C peripheral + * has a pointer register that needs to be adjusted prior to reading from + * the referenced data register. + * + * The details of each transaction are specified with an #I2C_Transaction data + * structure. This structure defines the slave I2C address, pointers + * to write and read buffers, and their associated byte counts. If + * no data needs to be written or read, the corresponding byte counts should + * be set to zero. + * + * If an I2C transaction is requested while a transaction is currently + * taking place, the new transaction is placed onto a queue to be processed + * in the order in which it was received. + * + * The below example shows sending three bytes of data to a slave peripheral + * at address 0x50, in blocking mode: + * + * @code + * unsigned char writeBuffer[3]; + * I2C_Transaction i2cTransaction; + * + * i2cTransaction.slaveAddress = 0x50; + * i2cTransaction.writeBuf = writeBuffer; + * i2cTransaction.writeCount = 3; + * i2cTransaction.readBuf = NULL; + * i2cTransaction.readCount = 0; + * + * status = I2C_transfer(i2c, &i2cTransaction); + * if (!status) { + * // Unsuccessful I2C transfer + * } + * @endcode + * + * The next example shows reading of five bytes of data from the I2C + * peripheral, also in blocking mode: + * + * @code + * unsigned char readBuffer[5]; + * I2C_Transaction i2cTransaction; + * + * i2cTransaction.slaveAddress = 0x50; + * i2cTransaction.writeBuf = NULL; + * i2cTransaction.writeCount = 0; + * i2cTransaction.readBuf = readBuffer; + * i2cTransaction.readCount = 5; + * + * status = I2C_transfer(i2c, &i2cTransaction); + * if (!status) { + * // Unsuccessful I2C transfer + * } + * @endcode + * + * This example shows writing of two bytes and reading of four bytes in a + * single transaction. + * + * @code + * unsigned char readBuffer[4]; + * unsigned char writeBuffer[2]; + * I2C_Transaction i2cTransaction; + * + * i2cTransaction.slaveAddress = 0x50; + * i2cTransaction.writeBuf = writeBuffer; + * i2cTransaction.writeCount = 2; + * i2cTransaction.readBuf = readBuffer; + * i2cTransaction.readCount = 4; + * + * status = I2C_transfer(i2c, &i2cTransaction); + * if (!status) { + * // Unsuccessful I2C transfer + * } + * @endcode + * + * This final example shows usage of asynchronous callback mode, with queuing + * of multiple transactions. Because multiple transactions are simultaneously + * queued, separate I2C_Transaction structures must be used. (This is a + * general rule, that I2C_Transaction structures cannot be reused until + * it is known that the previous transaction has completed.) + * + * First, for the callback function (that is specified in the I2C_open() call) + * the "arg" in the I2C_Transaction structure is a SemaphoreP_Handle; when + * this value is non-NULL, SemaphoreP_post() is called in the callback using + * the specified handle, to signal completion to the task that queued the + * transactions: + * + * @code + * Void callbackFxn(I2C_Handle handle, I2C_Transaction *msg, Bool transfer) { + * if (msg->arg != NULL) { + * SemaphoreP_post((SemaphoreP_Handle)(msg->arg)); + * } + * } + * @endcode + * + * Snippets of the task code that initiates the transactions are shown below. + * Note the use of multiple I2C_Transaction structures, and passing of the + * handle of the semaphore to be posted via i2cTransaction2.arg. + * I2C_transfer() is called three times to initiate each transaction. + * Since callback mode is used, these functions return immediately. After + * the transactions have been queued, other work can be done, and then + * eventually SemaphoreP_pend() is called to wait for the last I2C + * transaction to complete. Once the callback posts the semaphore, the task + * will be moved to the ready state, so the task can resume execution, after + * the SemaphoreP_pend() call. + * + * @code + * Void taskfxn(arg0, arg1) { + * + * I2C_Transaction i2cTransaction0; + * I2C_Transaction i2cTransaction1; + * I2C_Transaction i2cTransaction2; + * + * ... + * i2cTransaction0.arg = NULL; + * i2cTransaction1.arg = NULL; + * i2cTransaction2.arg = semaphoreHandle; + * + * ... + * I2C_transfer(i2c, &i2cTransaction0); + * I2C_transfer(i2c, &i2cTransaction1); + * I2C_transfer(i2c, &i2cTransaction2); + * + * ... + * + * SemaphoreP_pend(semaphoreHandle); + * + * ... + * } + * @endcode + * + * # Implementation # + * + * This top-level I2C module serves as the main interface for RTOS + * applications. Its purpose is to redirect the module's APIs to specific + * peripheral implementations which are specified using a pointer to an + * #I2C_FxnTable. + * + * The I2C driver interface module is joined (at link time) to an + * array of I2C_Config data structures named *I2C_config*. + * *I2C_config* is typically defined in the Board.c file used for the + * application. If there are multiple instances of I2C peripherals on the + * device, there will typically be multiple I2C_Config structures defined in + * the board file. Each entry in *I2C_config* contains a: + * - (I2C_FxnTable *) to a set of functions that implement a I2C peripheral + * - (void *) data object that is associated with the I2C_FxnTable + * - (void *) hardware attributes that are associated to the I2C_FxnTable + * + ******************************************************************************* + */ + +#ifndef ti_drivers_I2C__include +#define ti_drivers_I2C__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @defgroup I2C_CONTROL I2C_control command and status codes + * These I2C macros are reservations for I2C.h + * @{ + */ + +/*! + * Common I2C_control command code reservation offset. + * I2C driver implementations should offset command codes with I2C_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define I2CXYZ_CMD_COMMAND0 I2C_CMD_RESERVED + 0 + * #define I2CXYZ_CMD_COMMAND1 I2C_CMD_RESERVED + 1 + * @endcode + */ +#define I2C_CMD_RESERVED (32) + +/*! + * Common I2C_control status code reservation offset. + * I2C driver implementations should offset status codes with + * I2C_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define I2CXYZ_STATUS_ERROR0 I2C_STATUS_RESERVED - 0 + * #define I2CXYZ_STATUS_ERROR1 I2C_STATUS_RESERVED - 1 + * #define I2CXYZ_STATUS_ERROR2 I2C_STATUS_RESERVED - 2 + * @endcode + */ +#define I2C_STATUS_RESERVED (-32) + +/** + * @defgroup I2C_STATUS Status Codes + * I2C_STATUS_* macros are general status codes returned by I2C_control() + * @{ + * @ingroup I2C_CONTROL + */ + +/*! + * @brief Successful status code returned by I2C_control(). + * + * I2C_control() returns I2C_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define I2C_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by I2C_control(). + * + * I2C_control() returns I2C_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define I2C_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by I2C_control() for undefined + * command codes. + * + * I2C_control() returns I2C_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define I2C_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup I2C_CMD Command Codes + * I2C_CMD_* macros are general command codes for I2C_control(). Not all I2C + * driver implementations support these command codes. + * @{ + * @ingroup I2C_CONTROL + */ + +/* Add I2C_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief A handle that is returned from an I2C_open() call. + */ +typedef struct I2C_Config_ *I2C_Handle; + +/*! + * @brief I2C transaction + * + * This structure defines an I2C transaction. It specifies the buffer(s) and + * buffer size(s) to be written to and/or read from an I2C slave peripheral. + * arg is an optional user-supplied argument that will be passed + * to the user-supplied callback function when the I2C driver is in + * I2C_MODE_CALLBACK. + * nextPtr is a pointer used internally by the driver for queuing of multiple + * transactions; this value must never be modified by the user application. + */ +typedef struct I2C_Transaction_ { + void *writeBuf; /*!< Buffer containing data to be written */ + size_t writeCount; /*!< Number of bytes to be written to the slave */ + + void *readBuf; /*!< Buffer to which data is to be read into */ + size_t readCount; /*!< Number of bytes to be read from the slave */ + + uint_least8_t slaveAddress; /*!< Address of the I2C slave peripheral */ + + void *arg; /*!< Argument to be passed to the callback function */ + void *nextPtr; /*!< Used for queuing in I2C_MODE_CALLBACK mode */ +} I2C_Transaction; + +/*! + * @brief I2C transfer mode + * + * I2C_MODE_BLOCKING blocks task execution while an I2C transfer is in + * progress. + * I2C_MODE_CALLBACK does not block task execution, but calls a callback + * function when the I2C transfer has completed. + */ +typedef enum I2C_TransferMode_ { + I2C_MODE_BLOCKING, /*!< I2C_transfer() blocks execution */ + I2C_MODE_CALLBACK /*!< I2C_transfer() does not block */ +} I2C_TransferMode; + +/*! + * @brief I2C callback function + * + * User-definable callback function prototype. The I2C driver will call this + * callback upon transfer completion, specifying the I2C handle for the + * transfer (as returned from I2C_open()), the pointer to the I2C_Transaction + * that just completed, and the return value of I2C_transfer(). Note that + * this return value will be the same as if the transfer were performed in + * blocking mode. + * + * @param I2C_Handle I2C_Handle + + * @param I2C_Transaction* Address of the I2C_Transaction + + * @param bool Result of the I2C transfer + */ +typedef void (*I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction *transaction, + bool transferStatus); + +/*! + * @brief I2C bitRate + * + * Specifies one of the standard I2C bus bit rates for I2C communications. + * The default is I2C_100kHz. + */ +typedef enum I2C_BitRate_ { + I2C_100kHz = 0, + I2C_400kHz = 1 +} I2C_BitRate; + +/*! + * @brief I2C Parameters + * + * I2C parameters are used with the I2C_open() call. Default values for + * these parameters are set using I2C_Params_init(). + * + * If I2C_TransferMode is set to I2C_MODE_BLOCKING, I2C_transfer() function + * calls will block thread execution until the transaction has completed. In + * this case, the transferCallbackFxn parameter will be ignored. + * + * If I2C_TransferMode is set to I2C_MODE_CALLBACK, I2C_transfer() will not + * block thread execution, but it will call the function specified by + * transferCallbackFxn upon transfer completion. Sequential calls to + * I2C_transfer() in I2C_MODE_CALLBACK will put the I2C_Transaction structures + * onto an internal queue that automatically starts queued transactions after + * the previous transaction has completed. This queuing occurs regardless of + * any error state from previous transactions. + * + * I2C_BitRate specifies the I2C bus rate used for I2C communications. + * + * @sa I2C_Params_init() + */ +typedef struct I2C_Params_ { + I2C_TransferMode transferMode; /*!< Blocking or Callback mode */ + I2C_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */ + I2C_BitRate bitRate; /*!< I2C bus bit rate */ + void *custom; /*!< Custom argument used by driver + implementation */ +} I2C_Params; + +/*! + * @brief A function pointer to a driver-specific implementation of + * I2C_cancel(). + */ +typedef void (*I2C_CancelFxn) (I2C_Handle handle); + +/*! + * @brief A function pointer to a driver-specific implementation of + * I2C_close(). + */ +typedef void (*I2C_CloseFxn) (I2C_Handle handle); + +/*! + * @brief A function pointer to a driver-specific implementation of + * I2C_control(). + */ +typedef int_fast16_t (*I2C_ControlFxn) (I2C_Handle handle, uint_fast16_t cmd, + void *controlArg); + +/*! + * @brief A function pointer to a driver-specific implementation of + * I2C_init(). + */ +typedef void (*I2C_InitFxn) (I2C_Handle handle); + +/*! + * @brief A function pointer to a driver-specific implementation of + * I2C_open(). + */ +typedef I2C_Handle (*I2C_OpenFxn) (I2C_Handle handle, I2C_Params *params); + +/*! + * @brief A function pointer to a driver-specific implementation of + * I2C_transfer(). + */ +typedef bool (*I2C_TransferFxn) (I2C_Handle handle, + I2C_Transaction *transaction); + +/*! + * @brief The definition of an I2C function table that contains the + * required set of functions to control a specific I2C driver + * implementation. + */ +typedef struct I2C_FxnTable_ { + /*! Cancel all I2C data transfers */ + I2C_CancelFxn cancelFxn; + + /*! Close the specified peripheral */ + I2C_CloseFxn closeFxn; + + /*! Implementation-specific control function */ + I2C_ControlFxn controlFxn; + + /*! Initialize the given data object */ + I2C_InitFxn initFxn; + + /*! Open the specified peripheral */ + I2C_OpenFxn openFxn; + + /*! Initiate an I2C data transfer */ + I2C_TransferFxn transferFxn; +} I2C_FxnTable; + +/*! + * @brief I2C global configuration + * + * The I2C_Config structure contains a set of pointers used to characterize + * the I2C driver implementation. + * + * This structure needs to be defined before calling I2C_init() and it must + * not be changed thereafter. + * + * @sa I2C_init() + */ +typedef struct I2C_Config_ { + /*! Pointer to a table of driver-specific implementations of I2C APIs */ + I2C_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver-specific data object */ + void *object; + + /*! Pointer to a driver-specific hardware attributes structure */ + void const *hwAttrs; +} I2C_Config; + +/*! + * @brief Cancel all I2C transfers + * + * This function will cancel asynchronous I2C_transfer() operations, and is + * applicable only for I2C_MODE_CALLBACK. An in progress transfer, as well + * as any queued transfers will be canceled. The individual callback functions + * for each transfer will be called from the context that I2C_cancel() is + * called. + * + * @pre I2C_Transfer() has been called. + * + * @param handle An I2C_Handle returned from I2C_open() + * + * @note Different I2C slave devices will behave differently when an + * in-progress transfer fails and needs to be canceled. The slave + * may need to be reset, or there may be other slave-specific + * steps that can be used to successfully resume communication. + * + * @sa I2C_transfer() + */ +extern void I2C_cancel(I2C_Handle handle); + +/*! + * @brief Close an I2C peripheral specified by an I2C_Handle + * + * @pre I2C_open() has been called. + * + * @param handle An I2C_Handle returned from I2C_open() + * + * @sa I2C_open() + */ +extern void I2C_close(I2C_Handle handle); + +/*! + * @brief Perform implementation-specific features on a given + * I2C_Handle. + * + * Commands for I2C_control() can originate from I2C.h or from implementation + * specific I2C*.h (I2CCC26XX.h_, I2CMSP432.h_, etc.) files. + * While commands from I2C.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific I2C*.h files add + * unique driver capabilities but are not API portable across all I2C driver + * implementations. + * + * Commands supported by I2C.h follow a I2C_CMD_\ naming + * convention.
+ * Commands supported by I2C*.h follow a I2C*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref I2C_CMD "I2C_control command codes" for command codes. + * + * See @ref I2C_STATUS "I2C_control return status codes" for status codes. + * + * @pre I2C_open() has to be called first. + * + * @param handle An I2C_Handle returned from I2C_open() + * + * @param cmd I2C.h or I2C*.h command. + * + * @param controlArg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation-specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa I2C_open() + */ +extern int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd, + void *controlArg); + +/*! + * @brief Initializes the I2C module + * + * @pre The I2C_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other I2C driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void I2C_init(void); + +/*! + * @brief Initialize a given I2C peripheral as identified by an index value. + * The I2C_Params structure defines the operating mode, and any + * related settings. + * + * @pre The I2C controller has been initialized, via a previous call to + * I2C_init() + * + * @param index Logical peripheral number for the I2C indexed into + * the I2C_config table + * + * @param params Pointer to a parameter block. Default values will be + * used if NULL is specified for params. All the fields + * in this structure are are considered RO (read-only). + * + * @return An I2C_Handle on success, or NULL on an error, or if the peripheral + * is already opened. + * + * @sa I2C_init() + * @sa I2C_close() + */ +extern I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params); + +/*! + * @brief Initialize an I2C_Params struct to its defaults + * + * @param params A pointer to I2C_Params structure for + * initialization + * + * Defaults values are: + * transferMode = I2C_MODE_BLOCKING + * transferCallbackFxn = NULL + * bitRate = I2C_100kHz + */ +extern void I2C_Params_init(I2C_Params *params); + +/*! + * @brief Perform an I2C transaction with an I2C slave peripheral. + * + * This function will perform an I2C transfer, as specified by an + * I2C_Transaction structure. + * + * An I2C transaction may write data to a peripheral, or read data from a + * peripheral, or both write and read data, in a single transaction. If there + * is any data to be written, it will always be sent before any data is read + * from the peripheral. + * + * The data written to the peripheral is preceded with the peripheral's 7-bit + * I2C slave address (with the Write bit set). + * After all the data has been transmitted, the driver will evaluate if any + * data needs to be read from the device. + * If yes, another START bit is sent, along with the same 7-bit I2C slave + * address (with the Read bit). After the specified number of bytes have been + * read, the transfer is ended with a NACK and a STOP bit. Otherwise, if + * no data is to be read, the transfer is concluded with a STOP bit. + * + * In I2C_MODE_BLOCKING, I2C_transfer() will block thread execution until the + * transaction completes. Therefore, this function must only be called from an + * appropriate thread context (e.g., Task context for the TI-RTOS kernel). + * + * In I2C_MODE_CALLBACK, the I2C_transfer() call does not block thread + * execution. Instead, a callback function (specified during I2C_open(), via + * the transferCallbackFxn field in the I2C_Params structure) is called when + * the transfer completes. Success or failure of the transaction is reported + * via the callback function's bool argument. If a transfer is already in + * progress, the new transaction is put on an internal queue. The driver + * services the queue in a first come first served basis. + * + * @param handle An I2C_Handle + * + * @param transaction A pointer to an I2C_Transaction. All of the fields + * within the transaction structure should be considered + * write only, unless otherwise noted in the driver + * implementation. + * + * @note The I2C_Transaction structure must persist unmodified until the + * corresponding call to I2C_transfer() has completed. + * + * @return In I2C_MODE_BLOCKING: true for a successful transfer; false for an + * error (for example, an I2C bus fault (NACK)). + * + * In I2C_MODE_CALLBACK: always true. The transferCallbackFxn's bool + * argument will be true to indicate success, and false to indicate + * an error. + * + * @sa I2C_open + */ +extern bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_I2C__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2CSlave.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2CSlave.h new file mode 100644 index 000000000..0c567e7a0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2CSlave.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file I2CSlave.h + * + * @brief I2CSlave driver interface + * + * The I2CSlave header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * The I2CSlave driver operates as a slave on an I2C bus in either + * I2CSLAVE_MODE_BLOCKING or I2CSLAVE_MODE_CALLBACK. + * In blocking mode, the task's execution is blocked during the I2CSlave + * read/write transfer. When the transfer has completed, code execution will + * resume. In callback mode, the task's execution is not blocked, allowing + * for other transactions to be queued up or to process some other code. When + * the transfer has completed, the I2CSlave driver will call a user-specified + * callback function (from a HWI context). + * + * The APIs in this driver serve as an interface to a typical TI-RTOS + * application. The specific peripheral implementations are responsible to + * create all the SYS/BIOS specific primitives to allow for thread-safe + * operation. + * + * ## Opening the driver # + * + * @code + * I2CSlave_Handle handle; + * I2CSlave_Params params; + * + * I2CSlave_Params_init(¶ms); + * params.transferMode = I2CSLAVE_MODE_CALLBACK; + * params.transferCallbackFxn = someI2CSlaveCallbackFunction; + * handle = I2CSlave_open(someI2CSlave_configIndexValue, ¶ms); + * if (!handle) { + * System_printf("I2CSlave did not open"); + * } + * @endcode + * + * ## Transferring data # + * A I2CSlave transaction with a I2CSlave peripheral is started by calling + * I2CSlave_read() or I2CSlave_write(). + * Each transfer is performed atomically with the I2CSlave peripheral. + * + * @code + * ret = I2CSlave_read(i2cSlave, buffer, 5) + * if (!ret) { + * System_printf("Unsuccessful I2CSlave read"); + * } + * + * I2CSlave_write(i2cSlave, buffer, 3); + * if (!ret) { + * System_printf("Unsuccessful I2CSlave write"); + * } + + * @endcode + * + * # Implementation # + * + * This module serves as the main interface for TI-RTOS + * applications. Its purpose is to redirect the module's APIs to specific + * peripheral implementations which are specified using a pointer to a + * I2CSlave_FxnTable. + * + * The I2CSlave driver interface module is joined (at link time) to a + * NULL-terminated array of I2CSlave_Config data structures named + * *I2CSlave_config*. *I2CSlave_config* is implemented in the application + * with each entry being an instance of a I2CSlave peripheral. Each entry in + * *I2CSlave_config* contains a: + * - (I2CSlave_FxnTable *) to a set of functions that implement an I2CSlave + * - (void *) data object that is associated with the I2CSlave_FxnTable + * - (void *) hardware attributes that are associated to the I2CSlave_FxnTable + * + * # Instrumentation # + * The I2CSlave driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic operations performed | + * Diags_USER2 | detailed operations performed | + * + * ============================================================================ + */ + +#ifndef ti_drivers_I2CSLAVE__include +#define ti_drivers_I2CSLAVE__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @defgroup I2CSLAVE_CONTROL I2CSlave_control command and status codes + * These I2CSlave macros are reservations for I2CSlave.h + * @{ + */ +/*! + * Common I2CSlave_control command code reservation offset. + * I2CSlave driver implementations should offset command codes with + * I2CSLAVE_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define I2CSLAVEXYZ_COMMAND0 I2CSLAVE_CMD_RESERVED + 0 + * #define I2CSLAVEXYZ_COMMAND1 I2CSLAVE_CMD_RESERVED + 1 + * @endcode + */ +#define I2CSLAVE_CMD_RESERVED (32) + +/*! + * Common I2CSlave_control status code reservation offset. + * I2CSlave driver implementations should offset status codes with + * I2CSLAVE_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define I2CSLAVEXYZ_STATUS_ERROR0 I2CSLAVE_STATUS_RESERVED - 0 + * #define I2CSLAVEXYZ_STATUS_ERROR1 I2CSLAVE_STATUS_RESERVED - 1 + * #define I2CSLAVEXYZ_STATUS_ERROR2 I2CSLAVE_STATUS_RESERVED - 2 + * @endcode + */ +#define I2CSLAVE_STATUS_RESERVED (-32) + +/** + * @defgroup I2CSLAVE_STATUS Status Codes + * I2CSLAVE_STATUS_SUCCESS_* macros are general status codes returned by I2CSlave_control() + * @{ + * @ingroup I2CSLAVE_CONTROL + */ +/*! + * @brief Successful status code returned by I2CSlave_control(). + * + * I2CSlave_control() returns I2CSLAVE_STATUS_SUCCESS if the control code was + * executed successfully. + */ +#define I2CSLAVE_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by I2CSlave_control(). + * + * I2CSlave_control() returns I2CSLAVE_STATUS_ERROR if the control code was not + * executed successfully. + */ +#define I2CSLAVE_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by I2CSlave_control() for undefined + * command codes. + * + * I2CSlave_control() returns I2CSLAVE_STATUS_UNDEFINEDCMD if the control code + * is not recognized by the driver implementation. + */ +#define I2CSLAVE_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup I2CSLAVE_CMD Command Codes + * I2C_CMD_* macros are general command codes for I2CSlave_control(). Not all I2CSlave + * driver implementations support these command codes. + * @{ + * @ingroup I2CSLAVE_CONTROL + */ + +/* Add I2CSLAVE_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief A handle that is returned from a I2CSlave_open() call. + */ +typedef struct I2CSlave_Config_ *I2CSlave_Handle; + +/*! + * @brief I2CSlave mode + * + * This enum defines the state of the I2CSlave driver's state-machine. Do not + * modify. + */ +typedef enum I2CSlave_Mode_ { + I2CSLAVE_IDLE_MODE = 0, /*!< I2CSlave is not performing a transaction */ + I2CSLAVE_WRITE_MODE = 1, /*!< I2CSlave is currently performing write */ + I2CSLAVE_READ_MODE = 2, /*!< I2CSlave is currently performing read */ + I2CSLAVE_START_MODE = 3, /*!< I2CSlave received a START from a master */ + I2CSLAVE_ERROR = 0xFF /*!< I2CSlave error has occurred, exit gracefully */ +} I2CSlave_Mode; + +/*! + * @brief I2CSlave transfer mode + * + * I2CSLAVE_MODE_BLOCKING block task execution a I2CSlave transfer is in + * progress. I2CSLAVE_MODE_CALLBACK does not block task execution; but calls a + * callback function when the I2CSlave transfer has completed + */ +typedef enum I2CSlave_TransferMode_ { + I2CSLAVE_MODE_BLOCKING, /*!< I2CSlave read/write blocks execution*/ + I2CSLAVE_MODE_CALLBACK /*!< I2CSlave read/wrire queues transactions and + does not block */ +} I2CSlave_TransferMode; + +/*! + * @brief I2CSlave callback function + * + * User definable callback function prototype. The I2CSlave driver will call + * the defined function and pass in the I2CSlave driver's handle, and the + * return value of I2CSlave_read/I2CSlave_write. + * + * @param I2CSlave_Handle I2CSlave_Handle + + * @param bool Results of the I2CSlave transaction + */ +typedef void (*I2CSlave_CallbackFxn)(I2CSlave_Handle handle, bool status); + +/*! + * @brief I2CSlave Parameters + * + * I2CSlave parameters are used to with the I2CSlave_open() call. Default + * values for + * these parameters are set using I2CSlave_Params_init(). + * + * If I2CSlave_TransferMode is set to I2CSLAVE_MODE_BLOCKING then I2CSlave_read + * or I2CSlave_write function calls will block thread execution until the + * transaction has completed. + * + * If I2CSlave_TransferMode is set to I2CSLAVE_MODE_CALLBACK then + * I2CSlave read/write will not block thread execution and it will call the + * function specified by transferCallbackFxn. + * (regardless of error state). + * + * + * @sa I2CSlave_Params_init() + */ +typedef struct I2CSlave_Params_ { + /*!< Blocking or Callback mode */ + I2CSlave_TransferMode transferMode; + /*!< Callback function pointer */ + I2CSlave_CallbackFxn transferCallbackFxn; + /*!< Custom argument used by driver implementation */ + void *custom; +} I2CSlave_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * I2CSlave_close(). + */ +typedef void (*I2CSlave_CloseFxn) (I2CSlave_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * I2CSlave_control(). + */ +typedef int_fast16_t (*I2CSlave_ControlFxn) (I2CSlave_Handle handle, + uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * I2CSlave_init(). + */ +typedef void (*I2CSlave_InitFxn) (I2CSlave_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * I2CSlave_open(). + */ +typedef I2CSlave_Handle (*I2CSlave_OpenFxn) (I2CSlave_Handle handle, + I2CSlave_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * I2CSlave_WriteTransaction(). + */ +typedef bool (*I2CSlave_WriteFxn) (I2CSlave_Handle handle, + const void *buffer, size_t size); + + +/*! + * @brief A function pointer to a driver specific implementation of + * I2CSlave_ReadFxn(). + */ +typedef bool (*I2CSlave_ReadFxn) (I2CSlave_Handle handle, void *buffer, + size_t size); + + +/*! + * @brief The definition of a I2CSlave function table that contains the + * required set of functions to control a specific I2CSlave + * driver implementation. + */ +typedef struct I2CSlave_FxnTable_ { + /*! Function to close the specified peripheral */ + I2CSlave_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + I2CSlave_ControlFxn controlFxn; + + /*! Function to initialize the given data object */ + I2CSlave_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + I2CSlave_OpenFxn openFxn; + + /*! Function to initiate a I2CSlave data read */ + I2CSlave_ReadFxn readFxn; + + /*! Function to initiate a I2CSlave data write */ + I2CSlave_WriteFxn writeFxn; +} I2CSlave_FxnTable; + +/*! + * @brief I2CSlave Global configuration + * + * The I2CSlave_Config structure contains a set of pointers used to + * characterize the I2CSlave driver implementation. + * + * This structure needs to be defined before calling I2CSlave_init() and it + * must not be changed thereafter. + * + * @sa I2CSlave_init() + */ +typedef struct I2CSlave_Config_ { + /*! Pointer to a table of driver-specific implementations of I2CSlave APIs*/ + I2CSlave_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} I2CSlave_Config; + + +/*! + * @brief Function to close a I2CSlave peripheral specified by the I2CSlave + * handle + * @pre I2CSlave_open() had to be called first. + * + * @param handle A I2CSlave_Handle returned from I2CSlave_open + * + * @sa I2CSlave_open() + */ +extern void I2CSlave_close(I2CSlave_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * I2CSlave_Handle. + * + * Commands for I2CSlave_control can originate from I2CSlave.h or from implementation + * specific I2CSlave*.h (_I2CMSP432.h_, etc.. ) files. + * While commands from I2CSlave.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific I2CSlave*.h files add + * unique driver capabilities but are not API portable across all I2CSlave driver + * implementations. + * + * Commands supported by I2CSlave.h follow a I2CSLAVE_CMD_\ naming + * convention.
+ * Commands supported by I2CSlave*.h follow a I2CSLAVE*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref I2CSLAVE_CMD "I2CSlave_control command codes" for command codes. + * + * See @ref I2CSLAVE_STATUS "I2CSlave_control return status codes" for status codes. + * + * @pre I2CSlave_open() has to be called first. + * + * @param handle A I2CSlave handle returned from I2CSlave_open() + * + * @param cmd A command value defined by the driver specific + * implementation + * + * @param arg An optional R/W (read/write) argument that is + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa I2CSlave_open() + */ +extern int_fast16_t I2CSlave_control(I2CSlave_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief Function to initializes the I2CSlave module + * + * @pre The I2CSlave_config structure must exist and be persistent before + * this function can be called. This function must also be called + * before any other I2CSlave driver APIs. This function call does not + * modify any peripheral registers. + */ +extern void I2CSlave_init(void); + +/*! + * @brief Function to initialize a given I2CSlave peripheral specified by the + * particular index value. The parameter specifies which mode the + * I2CSlave will operate. + * + * @pre I2CSlave controller has been initialized + * + * @param index Logical peripheral number for the I2CSlave indexed + * into the I2CSlave_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A I2CSlave_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa I2CSlave_init() + * @sa I2CSlave_close() + */ +extern I2CSlave_Handle I2CSlave_open(uint_least8_t index, + I2CSlave_Params *params); + +/*! + * @brief Function to initialize the I2CSlave_Params struct to its defaults + * + * @param params An pointer to I2CSlave_Params structure for + * initialization + * + * Defaults values are: + * transferMode = I2CSLAVE_MODE_BLOCKING + * transferCallbackFxn = NULL + */ +extern void I2CSlave_Params_init(I2CSlave_Params *params); + +/*! + * @brief Function that handles the I2CSlave read for SYS/BIOS + * + * This function will start a I2CSlave read and can only be called from a + * Task context when in I2CSLAVE_MODE_BLOCKING. + * The I2CSlave read procedure starts with evaluating how many bytes are to be + * readby the I2CSlave peripheral. + * + * The data written by the I2CSlave is synchronized with the START and STOP + * from the master. + * + * In I2CSLAVE_MODE_BLOCKING, I2CSlave read/write will block task execution until + * the transaction has completed. + * + * In I2CSLAVE_MODE_CALLBACK, I2CSlave read/write does not block task execution + * and calls a callback function specified by transferCallbackFxn. If a + * transfer is already taking place, the transaction is put on an internal + * queue. The queue is serviced in a first come first served basis. + * + * @param handle A I2CSlave_Handle + * + * @param buffer A RO (read-only) pointer to an empty buffer in which + * received data should be written to. + * + * @param size The number of bytes to be written into buffer + * + * @return true on successful transfer + * false on an error + * + * @sa I2CSlave_open + */ + +extern bool I2CSlave_read(I2CSlave_Handle handle, void *buffer, + size_t size); +/*! + * @brief Function that handles the I2CSlave write for SYS/BIOS + * + * This function will start a I2CSlave write and can only be called from a + * Task context when in I2CSLAVE_MODE_BLOCKING. + * The I2CSlave transfer procedure starts with evaluating how many bytes are + * to be written. + * + * The data written by the I2CSlave is synchronized with the START and STOP + * from the master. If slave does not have as many bytes requested by master + * it writes 0xFF. I2CSlave keeps sending 0xFF till master sends a STOP. + * + * In I2CSLAVE_MODE_BLOCKING, I2CSlave read/write will block task execution + * until the transaction has completed. + * + * In I2CSLAVE_MODE_CALLBACK, I2CSlave read/write does not block task execution + * and calls a callback function specified by transferCallbackFxn. If a + * transfer is already taking place, the transaction is put on an internal + * queue. The queue is serviced in a first come first served basis. + * The I2CSlave_Transaction structure must stay persistent until the + * I2CSlave read/write function has completed! + * + * @param handle A I2CSlave_Handle + * + * @param buffer A WO (write-only) pointer to buffer containing data to + * be written to the master. + * + * @param size The number of bytes in buffer that should be written + * onto the master. + * + * @return true on successful write + * false on an error + * + * @sa I2CSlave_open + */ +extern bool I2CSlave_write(I2CSlave_Handle handle, const void *buffer, + size_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_I2CSLAVE__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2S.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2S.h new file mode 100644 index 000000000..ebb9727eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2S.h @@ -0,0 +1,764 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file I2S.h + * + * @brief I2S driver interface + * + * The I2S header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The I2S driver facilitates the use of Inter-IC Sound (I2S), which is + * used to connect digital audio devices so that audio signals can be + * communicated between devices. The I2S driver simplifies reading and + * writing to any of the Multichannel Audio Serial Port (McASP) peripherals + * on the board with Receive and Transmit support. These include blocking, + * non-blocking, read and write characters on the McASP peripheral. + * + * The APIs in this driver serve as an interface to a typical RTOS + * application. Its purpose is to redirect the I2S APIs to specific + * driver implementations which are specified using a pointer to an + * #I2S_FxnTable. + * The specific peripheral implementations are responsible + * for creating all the RTOS specific primitives to allow for thread-safe + * operation. + * + * # Usage # + * + * To use the I2S driver for reaading and writing data to the I2S peripheral, + * the application calls the following APIs: + * - I2S_init(): Initialize the I2S driver. + * - I2S_Params_init(): Initialize a #I2S_Params structure with default + * vaules. Then change the parameters from non-default values as + * needed. + * - I2S_open(): Open an instance of the I2S driver, passing the + * initialized parameters, or NULL, and an index (described later). + * - If using callback mode, I2S_read() and I2S_write(). + * - If using issue/reclaim mode, I2S_readIssue(), I2S_readReclaim(), + * I2S_writeIssue() and I2S_writeReclaim(). + * - I2S_close(): De-initialize the I2S instance. + * + * ### I2S Driver Configuration # + * + * In order to use the I2S APIs, the application is required + * to provide device-specific I2S configuration in the Board.c file. + * The I2S driver interface defines a configuration data structure: + * + * @code + * typedef struct I2S_Config_ { + * // Pointer to driver-specific implementation of I2S functions + * I2S_FxnTable const *fxnTablePtr; + * void *object; // Driver specific data object + * void const *hwAttrs; // Driver specific hardware attributes + * } I2S_Config; + * @endcode + * + * The application must declare an array of I2S_Config elements, named + * I2S_config[]. Each element of I2S_config[] must be populated with + * pointers to a device specific I2S driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the I2S peripheral's base address and pins. + * Each element in I2S_config[] corresponds to an I2S instance, and + * and none of the elements should have NULL pointers. + * There is no correlation between the index and the peripheral + * designation (such as I2S0 or I2S1). For example, it is possible + * to use I2S_config[0] for I2S1. + * + * Because I2S configuration is very device dependent, you will need to + * check the doxygen for the device specific I2S implementation. There you + * will find a description of the I2S hardware attributes. Please also + * refer to the board.c file of any of your examples to see the I2S + * configuration. + * + * ### Initializing the I2S Driver # + * + * I2S_init() must be called before any other I2S APIs. This function + * iterates through the elements of the I2S_config[] array, calling + * the element's device implementation I2S initialization function. + * + * ### I2S Parameters + * + * The #I2S_Params structure is passed to the I2S_open() call. If NULL + * is passed for the parameters, I2S_open() uses default parameters. + * An #I2S_Params structure is initialized with default values by passing + * it to I2S_Params_init(). + * Some of the I2S parameters are described below. To see brief descriptions + * of all the parameters, see #I2S_Params. + * + * #### I2S Operation Mode + * The I2S operation mode determines whether transmit and/or receive modes + * are enabled. The mode is specified with one of the following constants: + * - #I2S_OPMODE_TX_ONLY: Enable transmit only. + * - #I2S_OPMODE_RX_ONLY: Enable receive only. + * - #I2S_OPMODE_TX_RX_SYNC: Enable both receive and transmit. + * + * #### I2S Data Mode + * A separate data mode may be specified for read calls and write calls. + * The available modes are: + * - #I2S_MODE_CALLBACK: This mode is non-blocking. Calls to I2S_read() or + * I2S_write() return immediately. When the transfer is finished, the + * user configured callback function is called. + * - #I2S_MODE_ISSUERECLAIM: Call I2S_readIssue() and I2S_writeIssue() to + * queue buffers to the I2S. I2S_readReclaim() blocks until a buffer + * of data is available. I2S_writeReclaim() blocks until a buffer of + * data has been issued and the descriptor can be returned back to the + * caller. + * + * ### Opening the I2S Driver # + * After initializing the I2S driver by calling I2S_init(), the application + * can open an I2S instance by calling I2S_open(). This function + * takes an index into the I2S_config[] array, and an I2S parameters data + * structure. The I2S instance is specified by the index of the I2S in + * I2S_config[]. Only one I2S index can be used at a time; + * calling I2S_open() a second time with the same index previosly + * passed to I2S_open() will result in an error. You can, + * though, re-use the index if the instance is closed via I2S_close(). + * + * If NULL is passed for the I2S_Params structure to I2S_open(), default values + * are used. If the open call is successful, it returns a non-NULL value. + * + * Example opening an I2S driver instance: + * @code + * I2S_Handle handle; + * I2S_Params params; + * + * I2S_Params_init(¶ms); + * params.operationMode = I2S_MODE_TX_RX_SYNC; + * < Change other params as required > + * + * handle = I2S_open(Board_I2S0, ¶ms); + * if (!handle) { + * // Error opening I2S, handle accordingly + * } + * @endcode + * + * ### Writing Data # + * The following example calls I2S_writeIssue() to write to an I2S driver + * instance that has been opened. It first queues up two buffers of text. + * Within an infinite loop, it calls I2S_writeReclaim() to retrieve a + * buffer and then re-queues the buffer. + * + * @code + * const unsigned char hello[] = "Hello World\n"; + * const unsigned char hello1[] = "Hello World1\n"; + * I2S_BufDesc writeBuffer1; + * I2S_BufDesc writeBuffer2; + * I2S_BufDesc *pDesc = NULL; + * + * writeBuffer1.bufPtr = &hello; + * writeBuffer1.bufSize = sizeof(hello); + * writeBuffer2.bufPtr = &hello1; + * writeBuffer2.bufSize = sizeof(hello1); + * + * ret = I2S_writeIssue(handle, &writeBuffer1); + * ret = I2S_writeIssue(handle, &writeBuffer2); + * + * while(1) { + * ret = I2S_writeReclaim(handle, &pDesc); + * pDesc->bufPtr = &hello;; + * pDesc->bufSize = sizeof(hello); + * ret = I2S_writeIssue(handle, pDesc); + * } + * + * @endcode + * + * ### Reading Data # + * The following example calls I2S_readIssue() to queue a buffer for + * reading from an I2S driver instance. It first queues up two buffers of + * text. Within an infinite loop, it then calls I2S_readReclaim() to retrieve + * a full buffer of data. + * + * @code + * unsigned char rxBuffer[20]; + * unsigned char rxBuffer1[20]; + * I2S_BufDesc readBuffer1; + * I2S_BufDesc readBuffer2; + * I2S_BufDesc *pDesc = NULL; + * + * readBuffer1.bufPtr = &rxBuffer; + * readBuffer1.bufSize = 20; + * readBuffer2.bufPtr = &rxBuffer1; + * readBuffer2.bufSize = 20; + * + * ret = I2S_readIssue(handle, &readBuffer1); + * ret = I2S_readIssue(handle, &readBuffer2); + * + * while(1) + * { + * ret = I2S_readReclaim(handle, &pDesc); + * pDesc->bufPtr = &rxBuffer; + * pDesc->bufSize = 20; + * ret = I2S_readIssue(handle, pDesc); + * } + * @endcode + * + * # Implementation # + * + * The I2S driver interface module is joined (at link time) to an + * array of I2S_Config data structures named *I2S_config*. + * *I2S_config* is implemented in the application with each entry being an + * instance of a I2S peripheral. Each entry in *I2S_config* contains a: + * - (I2S_FxnTable *) to a set of functions that implement a I2S peripheral + * - (void *) data object that is associated with the I2S_FxnTable + * - (void *) hardware attributes that are associated to the I2S_FxnTable + * + ******************************************************************************* + */ + +#ifndef ti_drivers_I2S__include +#define ti_drivers_I2S__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +/** + * @defgroup I2S_CONTROL I2S_control command and status codes + * These I2S macros are reservations for I2S.h + * @{ + */ + +/*! + * Common I2S_control command code reservation offset. + * I2S driver implementations should offset command codes with I2S_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define I2SXYZ_CMD_COMMAND0 I2S_CMD_RESERVED + 0 + * #define I2SXYZ_CMD_COMMAND1 I2S_CMD_RESERVED + 1 + * @endcode + */ +#define I2S_CMD_RESERVED (32) + +/*! + * Common I2S_control status code reservation offset. + * I2S driver implementations should offset status codes with + * I2S_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define I2SXYZ_STATUS_ERROR0 I2S_STATUS_RESERVED - 0 + * #define I2SXYZ_STATUS_ERROR1 I2S_STATUS_RESERVED - 1 + * #define I2SXYZ_STATUS_ERROR2 I2S_STATUS_RESERVED - 2 + * @endcode + */ +#define I2S_STATUS_RESERVED (-32) + +/** + * @defgroup I2S_STATUS Status Codes + * I2S_STATUS_* macros are general status codes returned by I2S_control() + * @{ + * @ingroup I2S_CONTROL + */ + +/*! + * @brief Successful status code returned by I2S_control(). + * + * I2S_control() returns I2S_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define I2S_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by I2S_control(). + * + * I2S_control() returns I2S_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define I2S_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by I2S_control() for undefined + * command codes. + * + * I2S_control() returns I2S_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define I2S_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup I2S_CMD Command Codes + * I2S_CMD_* macros are general command codes for I2S_control(). Not all I2S + * driver implementations support these command codes. + * @{ + * @ingroup I2S_CONTROL + */ + +/* Add I2S_CMD_ here */ + +/** @}*/ + +/** @}*/ + +#define I2S_ERROR (I2S_STATUS_ERROR) + +/*! + * @brief Wait forever define + */ +#define I2S_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from a I2S_open() call. + */ +typedef struct I2S_Config_ *I2S_Handle; + +/*! + * @brief I2S buffer descriptor for issue/reclaim mode. + */ +typedef struct I2S_BufDesc_ { + + /*! Used internally to link descriptors together */ + List_Elem qElem; + + /*! Pointer to the buffer */ + void *bufPtr; + + /*! Size of the buffer (target MAUs). */ + size_t bufSize; + + /*! Optional argument associated with the descriptor. */ + uintptr_t descArg; +} I2S_BufDesc; + +/*! + * @brief The definition of a callback function used by the I2S driver + * when used in ::I2S_MODE_CALLBACK + * + * @param I2S_Handle I2S_Handle + * + * @param buf Pointer to read/write buffer + * + * @param count Number of elements read/written + */ +typedef void (*I2S_Callback)(I2S_Handle handle, I2S_BufDesc *desc); + +/*! + * @brief I2S mode settings + * + * This enum defines the read and write modes for the + * configured I2S. + */ +typedef enum I2S_DataMode_ { + /*! + * Non-blocking and will return immediately. When the transfer by the intr + * is finished the configured callback function is called. + */ + I2S_MODE_CALLBACK, + + /*! + * Use I2S_readIssue, I2S_writeIssue calls to queue buffers to the + * I2S. I2S_readReclaim() blocks until a buffer of data is available. + * I2S_writeReclaim() blocks until a buffer of data has been written + * and the descriptor can be returned back to the caller. + */ + I2S_MODE_ISSUERECLAIM +} I2S_DataMode; + +/*! + * @brief I2S mode settings + * + * This enumeration defines the mode for I2S operation. + */ +typedef enum I2S_OpMode_ { + I2S_OPMODE_TX_ONLY, /*!< Only Transmit enabled */ + I2S_OPMODE_RX_ONLY, /*!< Only Receive enabled */ + I2S_OPMODE_TX_RX_SYNC /*!< Receive and Transmit are enabled in Sync */ +} I2S_OpMode; + +/*! + * @brief I2S Serializer InActive state settings + * + * This enumeration defines the Serializer configuration + * in inactive state. + */ +typedef enum I2S_SerInActiveConfig_ { + I2S_SERCONFIG_INACT_TRI_STATE, /*!< Inactive state to tristate */ + I2S_SERCONFIG_INACT_LOW_LEVEL, /*!< Inactive state to low */ + I2S_SERCONFIG_INACT_HIGH_LEVEL /*!< Inactive state to high */ +} I2S_SerInActiveConfig; + +/*! + * @brief I2S serial pin mode + * + * This enumeration defines the Serial pin configuration + */ +typedef enum I2S_PinMode_ { + I2S_PINMODE_RX, /*!< Operate the pin in Rx mode */ + I2S_PINMODE_TX, /*!< Operate the pin in Tx mode */ + I2S_PINMODE_INACTIVE /*!< Pin in inactive mode */ +} I2S_PinMode; + +/*! + * @brief Basic I2S Parameters + * + * I2S parameters are used to with the I2S_open() call. Default values for + * these parameters are set using I2S_Params_init(). + * + * @sa I2S_Params_init() + */ +typedef struct I2S_Params_ { + /*!< I2S operational mode */ + I2S_OpMode operationMode; + + /*!< I2S sampling frequency configuration in samples/second */ + uint32_t samplingFrequency; + + /*!< Slot length */ + uint8_t slotLength; + + /*!< Bits per sample (Word length) */ + uint8_t bitsPerSample; + + /*!< Number of channels (slots per frame) */ + uint8_t numChannels; + + /*!< Mode for all read calls */ + I2S_DataMode readMode; + + /*!< Pointer to read callback */ + I2S_Callback readCallback; + + /*!< Timeout for read semaphore */ + uint32_t readTimeout; + + /*!< Mode for all write calls */ + I2S_DataMode writeMode; + + /*!< Pointer to write callback */ + I2S_Callback writeCallback; + + /*!< Timeout for write semaphore */ + uint32_t writeTimeout; + + /*!< Pointer to device specific custom params */ + void *customParams; +} I2S_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * I2S_CloseFxn(). + */ +typedef void (*I2S_CloseFxn) (I2S_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * I2S_control(). + */ +typedef int_fast16_t (*I2S_ControlFxn)(I2S_Handle handle, + uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * I2S_init(). + */ +typedef void (*I2S_InitFxn)(I2S_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * I2S_OpenFxn(). + */ +typedef I2S_Handle (*I2S_OpenFxn)(I2S_Handle handle, I2S_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * I2S_IssueFxn(). + */ +typedef int_fast16_t (*I2S_IssueFxn)(I2S_Handle handle, I2S_BufDesc *desc); + +/*! + * @brief A function pointer to a driver specific implementation of + * I2S_ReclaimFxn(). + */ +typedef size_t (*I2S_ReclaimFxn)(I2S_Handle handle, I2S_BufDesc **desc); + +/*! + * @brief The definition of a I2S function table that contains the + * required set of functions to control a specific I2S driver + * implementation. + */ +typedef struct I2S_FxnTable_ { + /*! Function to close the specified peripheral */ + I2S_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + I2S_ControlFxn controlFxn; + + /*! Function to initialize the given data object */ + I2S_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + I2S_OpenFxn openFxn; + + /*! Function to queue a buffer for reading from the specified peripheral */ + I2S_IssueFxn readIssueFxn; + + /*! Function to retrieve a received buffer of data from the specified peripheral */ + I2S_ReclaimFxn readReclaimFxn; + + /*! Function to queue a buffer for writing from the specified peripheral */ + I2S_IssueFxn writeIssueFxn; + + /*! Function to retrieve a sent buffer of data from the specified peripheral */ + I2S_ReclaimFxn writeReclaimFxn; + +} I2S_FxnTable; + +/*! @brief I2S Global configuration + * + * The I2S_Config structure contains a set of pointers used to characterize + * the I2S driver implementation. + * + * This structure needs to be defined before calling I2S_init() and it must + * not be changed thereafter. + * + * @sa I2S_init() + */ +typedef struct I2S_Config_ { + /*! Pointer to a table of a driver-specific implementation of I2S + functions */ + I2S_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} I2S_Config; + +/*! + * @brief Function to close a given I2S peripheral specified by the I2S + * handle. + * + * @pre I2S_open() had to be called first. + * + * @param handle A I2S_Handle returned from I2S_open + * + * @sa I2S_open() + */ +extern void I2S_close(I2S_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * I2S_Handle. + * + * Commands for I2S_control can originate from I2S.h or from + * implementation specific I2S*.h (_I2SCC32XX.h_, etc.. ) files. + * While commands from I2S.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific I2S*.h files add + * unique driver capabilities but are not API portable across all I2S driver + * implementations. + * + * Commands supported by I2S.h follow a I2S_CMD_\ naming + * convention.
+ * Commands supported by I2S*.h follow a I2S*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref I2S_CMD "I2S_control command codes" for command codes. + * + * See @ref I2S_STATUS "I2S_control return status codes" for status codes. + * + * @pre I2S_open() has to be called first. + * + * @param handle A I2S handle returned from I2S_open() + * + * @param cmd I2S.h or I2S*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa I2S_open() + */ +extern int_fast16_t I2S_control(I2S_Handle handle, + uint_fast16_t cmd, + void *arg); + +/*! + * @brief Function to initializes the I2S module + * + * @pre The I2S_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other I2S driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void I2S_init(void); + +/*! + * @brief Function to initialize a given I2S peripheral specified by the + * particular index value. The parameter specifies which mode the I2S + * will operate. + * + * @pre I2S controller has been initialized + * + * @param index Logical peripheral number for the I2S indexed into + * the I2S_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A I2S_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa I2S_init() + * @sa I2S_close() + */ +extern I2S_Handle I2S_open(uint_least8_t index, I2S_Params *params); + +/*! + * @brief Function to initialize the I2S_Params struct to its defaults + * + * @param params An pointer to I2S_Params structure for + * initialization + * + * Defaults values are: + * @code + * params.operationMode = #I2S_OPMODE_TX_RX_SYNC; + * params.samplingFrequency = 16000; + * params.slotLength = 16; + * params.bitsPerSample = 16; + * params.numChannels = 2; + * params.readMode = #I2S_MODE_ISSUERECLAIM; + * params.readCallback = NULL; + * params.readTimeout = #I2S_WAIT_FOREVER; + * params.writeMode = #I2S_MODE_ISSUERECLAIM; + * params.writeCallback = NULL; + * params.writeTimeout = #I2S_WAIT_FOREVER; + * params.customParams = NULL; + * @endcode + * + * @param params Parameter structure to initialize + */ +extern void I2S_Params_init(I2S_Params *params); + +/*! + * @brief Function to queue a buffer of data to the I2S in callback mode + * for reading. + * + * @param handle A I2S_Handle + * + * @param desc A pointer to a I2S_BufDesc object. The bufPtr + * and bufSize fields must be set to a buffer and the + * size of the buffer before passing to this function. + * @return Returns 0 if successful else would return + * I2S_STATUS_UNDEFINEDCMD on an error. + */ +extern int_fast16_t I2S_read(I2S_Handle handle, I2S_BufDesc *desc); + +/*! + + * @brief Function to queue a buffer of data to the I2S in Issue/Reclaim + * mode for reading. + * + * @param handle A I2S_Handle + * + * @param desc A pointer to a I2S_BufDesc object. The bufPtr + * and bufSize fields must be set to a buffer and the + * size of the buffer before passing to this function. + * @return Returns 0 if successful else would return + * I2S_STATUS_UNDEFINEDCMD on an error. + */ + +extern int_fast16_t I2S_readIssue(I2S_Handle handle, I2S_BufDesc *desc); + +/*! + * @brief Function to retrieve a full buffer of data read by the I2S. + * + * @param handle A I2S_Handle + * + * @param pDesc A pointer to a I2S_BufDesc pointer. + * + * @return Returns the number of bytes read from the I2S, or 0 on timeout. + */ +extern size_t I2S_readReclaim(I2S_Handle handle, I2S_BufDesc **pDesc); + +/*! + * @brief Function to queue a buffer of data to the I2S in + * callback mode for writing. + * + * @param handle A I2S_Handle + * + * @param desc A pointer to a I2S_BufDesc object. The bufPtr + * and bufSize fields must be set to a buffer and the + * size of the buffer before passing to this function. + * @return Returns 0 if successful else would return + * I2S_STATUS_UNDEFINEDCMD on an error. + */ +extern int_fast16_t I2S_write(I2S_Handle handle, I2S_BufDesc *desc); + +/*! + * @brief Function to queue a buffer of data to the I2S in + * Issue/Reclaim mode for writing. + * + * @param handle A I2S_Handle + * + * @param desc A pointer to a I2S_BufDesc object. The bufPtr + * and bufSize fields must be set to a buffer and the + * size of the buffer before passing to this function. + * @return Returns 0 if successful else would return + * I2S_STATUS_UNDEFINEDCMD on an error. + */ +extern int_fast16_t I2S_writeIssue(I2S_Handle handle, I2S_BufDesc *desc); + +/*! + * @brief Function to retrieve a buffer that the I2S has finished writing. + * + * @param handle A I2S_Handle + * + * @param pDesc A pointer to a I2S_BufDesc pointer. + * + * @return Returns the number of bytes that have been written to the I2S, + * 0 on timeout. + */ +extern size_t I2S_writeReclaim(I2S_Handle handle, I2S_BufDesc **pDesc); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_I2S__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/NVS.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/NVS.h new file mode 100644 index 000000000..03243128a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/NVS.h @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ========================================================================== + * @file NVS.h + * + * @brief PRELIMINARY Non-Volatile Storage Driver. + * + * WARNING These APIs are PRELIMINARY, and subject to + * change in the next few months. + * + * The NVS header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * + * The NVS module allows you to manage non-volatile memory. Using the + * NVS APIs, you can read and write data to persistant storage. Each NVS + * object manages a 'block' of non-volatile memory of a size specified in + * the NVS object's hardware attributes. A 'page' will refer to the + * smallest unit of non-volatile storage that can be erased at one time, + * and the page size is the size of this unit. This is hardware specific + * and may be meaningless for some persistant storage systems. However, + * in the case of flash memory, page size should be taken into account + * when deciding the block size for NVS to manage. For example on + * TM4C129x devices, a page size is 16KB. + * + * When page size is relevant (e.g. for flash memory), the size of an + * NVS block size must be less than or equal to the page size. The block + * size can be less than the page size, however, care must be taken not + * to use the area in the page outside of the block. When the block is + * erased, the entire page will be erased, clearing anything in the page + * that was written outside of the block. + * + * See the device specific NVS header file for configuration details. + * + * ========================================================================== + */ + +#ifndef ti_drivers_NVS__include +#define ti_drivers_NVS__include + +#include +#include +#include + +#if defined (__cplusplus) +extern "C" { +#endif + +/** + * @defgroup NVS_CONTROL NVS_control command and status codes + * These NVS macros are reservations for NVS.h + * @{ + */ + +/*! + * Common NVS_control command code reservation offset. + * NVS driver implementations should offset command codes with NVS_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define NVSXYZ_CMD_COMMAND0 NVS_CMD_RESERVED + 0 + * #define NVSXYZ_CMD_COMMAND1 NVS_CMD_RESERVED + 1 + * @endcode + */ +#define NVS_CMD_RESERVED 32 + +/*! + * Common NVS_control status code reservation offset. + * NVS driver implementations should offset status codes with + * NVS_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define NVSXYZ_STATUS_ERROR0 NVS_STATUS_RESERVED - 0 + * #define NVSXYZ_STATUS_ERROR1 NVS_STATUS_RESERVED - 1 + * #define NVSXYZ_STATUS_ERROR2 NVS_STATUS_RESERVED - 2 + * @endcode + */ +#define NVS_STATUS_RESERVED -32 + +/** + * @defgroup NVS_STATUS Status Codes + * NVS_STATUS_* macros are general status codes returned by NVS_control() + * @{ + * @ingroup NVS_CONTROL + */ + +/*! + * @brief Successful status code returned by NVS_control(). + * + * NVS_control() returns NVS_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define NVS_STATUS_SUCCESS 0 + +/*! + * @brief Generic error status code returned by NVS_control(). + * + * NVS_control() returns NVS_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define NVS_STATUS_ERROR -1 + +/*! + * @brief An error status code returned by NVS_control() for undefined + * command codes. + * + * NVS_control() returns NVS_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define NVS_STATUS_UNDEFINEDCMD -2 +/** @}*/ + +/** + * @defgroup NVS_CMD Command Codes + * NVS_CMD_* macros are general command codes for NVS_control(). Not all NVS + * driver implementations support these command codes. + * @{ + * @ingroup NVS_CONTROL + */ + +/* Add NVS_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief Success return code + */ +#define NVS_SOK (0) + +/*! + * @brief General failure return code + */ +#define NVS_EFAIL (-1) +#define NVS_EOFFSET (-3) +#define NVS_EALIGN (-4) +#define NVS_ENOTENOUGHBYTES (-5) +#define NVS_EALREADYWRITTEN (-6) +#define NVS_ECOPYBLOCK (-7) + +/*! + * @brief NVS write flags + * + * The following flags can be or'd together and passed as a bit mask + * to NVS_write. + */ + +/*! + * @brief Exclusive write flag + * + * Only write if the area has not already been written to since the last + * erase. In the case of flash memory on some devices, once data is written + * to a location, that location cannot be written to again without first + * erasing the entire flash page. If the NVS_WRITE_EXCLUSIVE flag is + * set in the flags passed to NVS_write(), the location where the data + * will be written to is first checked if it has been modified since the + * last time the NVS block was erarsed. If that is the case, NVS_write() + * will return an error. + */ +#define NVS_WRITE_EXCLUSIVE (0x1) + +/*! + * @brief Erase write flag. + * + * If NVS_WRITE_ERASE is set in the flags passed to NVS_write(), the entire + * NVS block will be erased before being written to. + */ +#define NVS_WRITE_ERASE (0x2) + +/*! + * @brief Validate write flag. + * + * If NVS_WRITE_VALIDATE is set in the flags passed to NVS_write(), the region + * in the NVS block that was written to will be validated (i.e., compared + * against the data buffer passed to NVS_write()). + */ +#define NVS_WRITE_VALIDATE (0x4) + +/*! + * @brief NVS Parameters + * + * NVS parameters are used with the NVS_open() call. Default values for + * these parameters are set using NVS_Params_init(). + * + * @sa NVS_Params_init() + */ +typedef struct NVS_Params { + bool eraseOnOpen; /*!< Erase block on open */ +} NVS_Params; + +/*! + * @brief NVS attributes + * + * The address of an NVS_Attrs structure can be passed to NVS_getAttrs() + * to fill in the fields. + * + * pageSize is the size of the smallest erase page. This is hardware + * specific. For example, all TM4C123x devices use 1KB pages, but + * TM4C129x devices use 16KB pages. Please consult the device datasheet + * to determine the pageSize to use. + * + * blockSize is the actual size of the NVS storage block that the + * application chooses to manage. + * If pageSize is greater than blockSize, care should be taken not to + * use the storage on the page that is outside of the block, since it + * may be erased when writing to the block. The block size must not be + * greater than the page size. + * + * @sa NVS_getAttrs() + */ +typedef struct NVS_Attrs { + size_t pageSize; /*! Hardware page size */ + size_t blockSize; /*! Size of the NVS block to manage */ +} NVS_Attrs; + +/*! + * @brief A handle that is returned from the NVS_open() call. + */ +typedef struct NVS_Config *NVS_Handle; + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_close(). + */ +typedef void (*NVS_CloseFxn) (NVS_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_control(). + */ +typedef int (*NVS_ControlFxn) (NVS_Handle handle, unsigned int cmd, + uintptr_t arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_exit(). + */ +typedef void (*NVS_ExitFxn) (NVS_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_getAttrs(). + */ +typedef int (*NVS_GetAttrsFxn) (NVS_Handle handle, NVS_Attrs *attrs); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_init(). + */ +typedef void (*NVS_InitFxn) (NVS_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_open(). + */ +typedef NVS_Handle (*NVS_OpenFxn) (NVS_Handle handle, NVS_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_read(). + */ +typedef int (*NVS_ReadFxn) (NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_write(). + */ +typedef int (*NVS_WriteFxn) (NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize, + unsigned int flags); + +/*! + * @brief The definition of an NVS function table that contains the + * required set of functions to control a specific NVS driver + * implementation. + */ +typedef struct NVS_FxnTable { + /*! Function to close the specified NVS block */ + NVS_CloseFxn closeFxn; + + /*! Function to apply control command to the specified NVS block */ + NVS_ControlFxn controlFxn; + + /*! Function to de-initialize the NVS module */ + NVS_ExitFxn exitFxn; + + /*! Function to get the NVS device-specific attributes */ + NVS_GetAttrsFxn getAttrsFxn; + + /*! Function to initialize the NVS module */ + NVS_InitFxn initFxn; + + /*! Function to open an NVS block */ + NVS_OpenFxn openFxn; + + /*! Function to read from the specified NVS block */ + NVS_ReadFxn readFxn; + + /*! Function to write to the specified NVS block */ + NVS_WriteFxn writeFxn; +} NVS_FxnTable; + +/*! + * @brief NVS Global configuration + * + * The NVS_Config structure contains a set of pointers used to characterize + * the NVS driver implementation. + * + * This structure needs to be defined before calling NVS_init() and it must + * not be changed thereafter. + * + * @sa NVS_init() + */ +typedef struct NVS_Config { + /*! Pointer to a table of driver-specific implementations of NVS APIs */ + NVS_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} NVS_Config; + +/*! + * @brief Function to close an NVS handle + * + * @param handle A handle returned from NVS_open() + * + * @sa NVS_open() + */ +extern void NVS_close(NVS_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * NVS_Handle. + * + * @pre NVS_open() must be called first. + * + * @param handle An NVS handle returned from NVS_open() + * + * @param cmd A command value defined by the driver specific + * implementation + * + * @param arg An optional R/W (read/write) argument that is + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa NVS_open() + */ +extern int NVS_control(NVS_Handle handle, unsigned int cmd, uintptr_t arg); + +/*! + * @brief Erase the block of storage reference by an NVS handle + * + * @param handle A handle returned from NVS_open() + * + * @return NVS_SOK Success. + * @return NVS_EFAIL An error occurred erasing the flash. + */ +extern int NVS_erase(NVS_Handle handle); + +/*! + * @brief Function to de-initialize the NVS module + * + * @pre NVS_init() was called. + */ +extern void NVS_exit(void); + +/*! + * @brief Function to get the NVS attributes + * + * @param handle A handle returned from NVS_open() + * + * @param attrs Location to store attributes. + */ +extern int NVS_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); + +/*! + * @brief Function to initialize the NVS module + * + * @pre The NVS_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other NVS APIs. + */ +extern void NVS_init(void); + +/*! + * @brief Get an NVS block for reading and writing. + * + * @pre NVS_init() was called. + * + * @param index Index in the NVS_config table of the block + * to manage. + * + * @param params Pointer to a parameter block. If NULL, default + * parameter values will be used. + */ +extern NVS_Handle NVS_open(int index, NVS_Params *params); + +/*! + * @brief Read data from an NVS block. + * + * @param handle A handle returned from NVS_open() + * + * @param offset The byte offset into the NVS block to start + * reading from. + * + * @param buffer A buffer to copy the data to. + * + * @param bufferSize The size of the buffer (number of bytes to read). + * + * @return NVS_SOK Success. + * @return NVS_EOFFSET The location and size to read from does not + * lie completely within the NVS block. + * + * @remark This call may block to ensure atomic access to the block. + */ +extern int NVS_read(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize); + +/*! + * @brief Write data to an NVS block. + * + * @param handle A handle returned from NVS_open() + * + * @param offset The byte offset into the NVS block to start + * writing. offset must be 4-byte aligned. + * + * @param buffer A buffer conntaining data to write to + * the NVS block. If buffer is NULL, the block + * will be erased. A non-NULL buffer must be + * aligned on a 4-byte boundary. + * + * @param bufferSize The size of the buffer (number of bytes to write). + * bufferSize must be a multiple of 4 bytes. + * + * @param flags Write flags (NVS_WRITE_EXCLUSIVE, NVS_WRITE_ERASE, + * NVS_WRITE_VALIDATE). + * + * @return NVS_SOK Success. + * @return NVS_EOFFSET The location and size to write to does not + * lie completely within the NVS block. + * @return NVS_EALIGN The offset or bufferSize is not 4-byte aligned. + * @return NVS_ALREADYWRITTEN + * The region to write to (the bufferSize region + * starting at offset into the block) has already + * been written to since the last erase, and + * NVS_WRITE_EXCLUSIVE is set in the flags parameter. + * + * @remark This call may block to ensure atomic access to the block. + */ +extern int NVS_write(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize, unsigned int flags); + +#if defined (__cplusplus) +} +#endif /* defined (__cplusplus) */ + +/*@}*/ +#endif /* ti_drivers_NVS__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/PIN.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/PIN.h new file mode 100644 index 000000000..5d8185c6c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/PIN.h @@ -0,0 +1,1058 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file PIN.h + * @brief Generic PIN & GPIO driver + * + * To use the PIN driver ensure that the correct TI-RTOS driver library for your + * device is linked in and include this header file: + * @code + * #include + * @endcode + * + * In order to use device-specific functionality or to use the size/speed- + * optimized versions of some of the PIN driver functions that circumvent error + * and resource checking, link in the correct TI-RTOS driver library for your + * device and include the device-specific PIN driver header file (which in turn + * includes PIN.h). As an example for the CC26xx family of devices: + * @code + * #include + * @endcode + * + * # Overview # + * The PIN driver allows clients (applications or other drivers) to allocate + * and control the I/O pins on the device. The pins can either be software- + * controlled general-purpose I/O (GPIO) or connected to hardware peripherals. + * Furthermore, the PIN driver allows clients to configure interrupt + * functionality on the pins to receive callbacks (and potentially wake up from + * the standby or idle power modes) on configurable signal edges. + * + * Most other drivers rely on functionality in the PIN driver. + * + * ## Structure ## + * In order to provide a generic driver interface, this file (PIN.h) only + * defines the API and some common data types and macros of the driver. A PIN + * client (application or driver) can in most cases only use the generic PIN + * API, however, for more advanced usage where device-specific pin + * configuration is used or device-specific PIN driver API extensions are + * used must use the device-specific PIN driver API. + * + * The device-independent API is implemented as function calls with pin + * access control based on the PIN client handle. For time-critical + * applications the device-specific API can be used directly, as these + * API functions are implemented as inlined functions without access control. + * + * ## Functionality ## + * The PIN module provides the following functionality: + * - Initialize I/O pins upon boot to a default configuration (possibly + * user-generated) + * - Provides atomic manipulation of I/O pin hardware registers to allow safe + * simultaneous use of I/O pin resources + * - I/O pin allocation + * - A set of pins can be allocated receiving a pin set handle. + * Typically each peripheral driver will allocate a set of pins and an + * application must allocate the pins it uses too + * - When a pin set is deallocated all the pins in it revert to the state + * they were initialized to at boot + * - General-purpose I/O (GPIO) services + * - Read input buffer value + * - Read and set output buffer value + * - Read and set output buffer enable + * - Access as single pin or port (muliple pins simultaneously) + * - Protect pin manipulation + * - Pins in an allocated set can only be manipulated using the corresponding + * handle. + * - No handle is needed to read input and output buffer values + * - I/O buffer/driver control + * - Input mode (detached, hysteresis, pull-up, pull-down) + * - Output mode (tristated, push-pull, open drain, open source) + * - Output driver strength control + * - Output driver slew rate control + * - I/O source/target selection (device-specific driver only) + * - Map pin to GPIO, peripheral or HW observation signal + * - Configuration of I/O interrupt and wakeup from standby + * - Interrupt configuration: signal edge to interrupt on, interrupt mask, + * callback function registration + * - Pins that have enabled interrupts will also wake up the device from low- + * power modes like standby and idle upon events + * - Provides data types and enums/defines for use in pin configurations + * definitions in board files, drivers and applications + * + * ## Pin Allocation ## + * The purpose of being able to allocate pins to a pin set is to: + * - Manage pin resources + * - Give exclusive, protected access to these pins + * - Establish a driver state in connection with these pins that allow + * functionality such as I/O interrupt callback and I/O port operations + * in a safe manner + * + * | API function | Description | + * |--------------------|------------------------------------------------------| + * | PIN_open() | Allocate pins to a set, returns handle | + * | PIN_add() | Add pin to pin set for open PIN handle | + * | PIN_remove() | Removes pin from pin set for open PIN handle | + * | PIN_close() | Deallocate pin set, revert to original GPIO state | + * + * ## GPIO ## + * Pins that are to be used as software-controlled general-purpose I/O (GPIO) + * need to be allocated in the same manner as for pins that will be mapped to + * hardware peripheral ports. A pin set requested with a PIN_open() call may + * contain a mix of pins to be used for GPIO and hardware-mapped pins. + * + * When a pin is deallocated using PIN_close() it reverts to the GPIO + * configuration it was given in the initial call to PIN_init(). + * + * | API function | Description | + * |----------------------|---------------------------------------------------| + * | PIN_init() | Initialize I/O pins to a safe GPIO state | + * | PIN_open() | Allocate pins to a set, returns handle | + * | PIN_close() | Deallocate pin set, revert to original GPIO state | + * | PIN_setConfig() | Sets parts of or complete pin configuration | + * | PIN_getConfig() | Returns pin configuration | + * | PIN_setOutputEnable()| Control output enable of GPIO pin | + * | PIN_getInputValue() | Read input value on pin | + * | PIN_setOutputValue() | Set output value of GPIO pin | + * | PIN_getOutputValue() | Get current output value of GPIO pin | + * + * ## GPIO Ports ## + * Sometimes it is necessary to be able to read from, write to or control + * multiple pins simultaneously (in time). The PIN driver allows a set of + * allocated pins, if they reside on the same GPIO port in the underlying + * hardware, to be manipulated simultaneously. + * + * | API function | Description | + * |--------------------------|---------------------------------------------------| + * | PIN_open() | Allocate pins to a set, returns handle | + * | PIN_close() | Deallocate pin set, revert to original GPIO state | + * | PIN_getPortMask() | Returns bitmask for allocated pins in GPIO port | + * | PIN_getPortInputValue() | Returns input value of whole GPIO port | + * | PIN_setPortOutputValue() | Sets output value of whole GPIO port (masked) | + * | PIN_getPortOutputValue() | Get current output value of whole GPIO port | + * | PIN_setPortOutputValue() | Sets output value of whole GPIO port (masked) | + * | PIN_setPortOutputEnable()| Sets output enable of whole GPIO port (masked) | + * + * ## I/O Pin Configuration ## + * Different devices provide different levels of configurability of I/O pins. + * The PIN driver provides a fairly extensive set of @ref PIN_GENERIC_FLAGS + * "generic IO configuration options" that are device-independent, all of which + * might not be supported by the underlying device-specific PIN driver and + * hardware. Likewise, the underlying device-specific PIN driver and hardware + * might support additional configuration options not covered by the generic + * options. + * + * To allow both independence from and flexibility to use features on the target + * device, the #PIN_Config entries used by the PIN driver allows use of either + * a set of @ref PIN_GENERIC_FLAGS "generic PIN configuration options" or a + * device-specific set of PIN configuration options defined in the underlying + * device-specific PIN driver (e.g. PINCC26XX.h) + * + * ### Mapping to GPIO or Peripheral ### + * Since the amount of flexibilty in which peripherals can be mapped to which + * pins and the manner in which this needs to be set up is highly + * device-specific, functions for configuring this is not part of the generic + * PIN driver API but is left to be implemented by device-specific PIN drivers. + * See the relevant device-specific PIN driver (e.g. PINCC26XX.h) for details. + * + * ### Input Mode ### + * The input mode of a pin controls: + * - Input buffer enable + * - Pull-ups or pull-downs + * - Hysteresis of input buffer + * - Inversion of logical input level + * - Potentially, device-specific options + * The input mode is set initially with PIN_init() or at a later stage with + * PIN_setConfig() and a bitmask with the relevant options + * + * | API function | Description | + * |------------------|-------------------------------------------------------| + * | PIN_init() | Initialize IOs to a safe GPIO state | + * | PIN_getConfig() | Returns pin configuration | + * | PIN_setConfig() | Sets parts of or complete pin configuration | + * + * ### Output Mode ### + * The output mode of a pin controls: + * - Output buffer enable + * - Output driver mode (push-pull, open-drain, open-source) + * - Output driver slew control + * - Output driver current (drive strength) + * - Inversion of logical output level + * - Potentially, device-specific options + * + * | API function | Description | + * |----------------------|---------------------------------------------------| + * | PIN_init() | Initialize IOs to a safe GPIO state | + * | PIN_setOutputEnable()| Control output enable of GPIO pins | + * | PIN_getConfig() | Returns pin configuration | + * | PIN_setConfig() | Sets parts of or complete pin configuration | + * + * ### Pin Interrupt and Pin Wakeup ### + * Pin interrupts are used to process asynchronous signal edge events on pins + * and potentially wake the device up from low power sleep modes. To use pin + * interrupts the relevant pins must be allocated and a interrupt callback + * registered by the client. The callback function will be called in a SWI + * context. + * + * | API function | Description | + * |---------------------|----------------------------------------------------| + * | PIN_init() | Initialize IOs to a safe GPIO state | + * | PIN_getConfig() | Returns pin configuration | + * | PIN_setConfig() | Sets parts of or complete pin configuration | + * | PIN_setInterrupt() | Control interrupt enable and edge for pin | + * | PIN_registerIntCb() | Register callback function for a set of pins | + * | PIN_setUserArg() | Sets a user argument associated with the handle | + * | PIN_getUserArg() | Gets a user argument associated with the handle | + * + * ## PIN Data Types ## + * The PIN driver defines the following data types: + * - #PIN_Id: identifies a pin in arguments or lists + * - #PIN_Config: provides I/O configuration options for a pin and also embeds + * a #PIN_Id identifier. See @ref PIN_GENERIC_FLAGS "available flags/fields" + * + * ## PIN Config Flags/Fields and Bitmasks ## + * The PIN driver uses the #PIN_Config data type many places and it merits some + * additional attention. A #PIN_Config value consists of a collection of flags + * and fields that define how an I/O pin and its attached GPIO interface should + * behave electrically and logically. In addition a #PIN_Config value also + * embeds a #PIN_Id pin ID, identifying which pin it refers to. + * + * A #PIN_Config value can use one of two mutually exclusive sets of flags and + * fields: @ref PIN_GENERIC_FLAGS "device-independent options" defined in + * PIN.h or device-dependent options defined in the device-specific + * implementation of the PIN driver interface. Any function that uses + * #PIN_Config will accept both option types, just not at the same time. + * PIN_getConfig() always returns device-independent options, an additional + * device-specific version (e.g. PINCC26XX_getConfig()) might return + * device-specific options. + * + * The bitmask argument for PIN_setConfig() decides which of the options the + * call should affect. All other options are kept at their current values in + * hardware. Thus PIN_setConfig(hPins, PIN_BM_PULLING, PIN_BM_PULLUP) will only + * change the pullup/pulldown configuration of the pin, leaving everything + * else, such as for instance output enable, input hysteresis or output value, + * untouched. For #PIN_Config lists (as supplied to PIN_init() for instance) + * there is no mask, so all options will affect the pin. + * + * Some of the options affect the pin regardless of whether it is mapped to + * a hardware peripheral or GPIO and some options only take effect when it is + * mapped to GPIO. These latter options have \_GPIO_ in their names. + * + * The default value for a flag/field is indicated with a star (*) in the + * description of the options and will be applied if any explicit value is + * not supplied for a flag/field that is masked. + * + * The available options can be grouped into categories as follows: + * + * ### Input Mode Options ### + * | Option | Option bitmask | HW/GPIO | Description | + * |--------------------|-----------------------|---------|--------------------------------| + * |#PIN_INPUT_EN (*) |#PIN_BM_INPUT_EN | Both | Enable pin input buffer | + * |#PIN_INPUT_DIS |#PIN_BM_INPUT_EN | Both | Disable pin input buffer | + * |#PIN_HYSTERESIS |#PIN_BM_HYSTERESIS | Both | Enable hysteresis on input | + * |#PIN_NOPULL (*) |#PIN_BM_PULLING | Both | No pullup/pulldown | + * |#PIN_PULLUP |#PIN_BM_PULLING | Both | Enable pullup | + * |#PIN_PULLDOWN |#PIN_BM_PULLING | Both | Enable pulldown | + * | |#PIN_BM_INPUT_MODE | | Mask for all input mode options| + * + * ### Output Mode Options ### + * | Option | Option bitmask | HW/GPIO | Description | + * |------------------------|------------------------|---------|----------------------------------| + * |#PIN_GPIO_OUTPUT_DIS (*)|#PIN_BM_GPIO_OUTPUT_EN | GPIO | Disable GPIO output buffer | + * |#PIN_GPIO_OUTPUT_EN |#PIN_BM_GPIO_OUTPUT_EN | GPIO | Enable GPIO output buffer | + * |#PIN_GPIO_LOW (*) |#PIN_BM_GPIO_OUTPUT_VAL | GPIO | Output 0 when GPIO | + * |#PIN_GPIO_HIGH |#PIN_BM_GPIO_OUTPUT_VAL | GPIO | Output 1 when GPIO | + * |#PIN_PUSHPULL (*) |#PIN_BM_OUTPUT_BUF | Both | Use push-pull output buffer | + * |#PIN_OPENDRAIN |#PIN_BM_OUTPUT_BUF | Both | Use open drain output buffer | + * |#PIN_OPENSOURCE |#PIN_BM_OUTPUT_BUF | Both | Use open source output buffer | + * |#PIN_SLEWCTRL |#PIN_BM_SLEWCTRL | Both | Enable output buffer slew control| + * |#PIN_DRVSTR_MIN (*) |#PIN_BM_DRVSTR | Both | Output buffer uses min drive | + * |#PIN_DRVSTR_MED |#PIN_BM_DRVSTR | Both | Output buffer uses medium drive | + * |#PIN_DRVSTR_MAX |#PIN_BM_DRVSTR | Both | Output buffer uses max drive | + * | |#PIN_BM_OUTPUT_MODE | | Mask for all output mode options | + * + * ### Misc Options ### + * | Option | Option bitmask | HW/GPIO | Description | + * |-------------------|------------------|---------|----------------------------------| + * |#PIN_INV_INOUT |#PIN_BM_INV_INOUT | Both | Invert input/output | + * |#PIN_IRQ_DIS (*) |#PIN_BM_IRQ | Both | Disable pin interrupts | + * |#PIN_IRQ_NEGEDGE |#PIN_BM_IRQ | Both | Pin interrupts on negative edges | + * |#PIN_IRQ_POSEDGE |#PIN_BM_IRQ | Both | Pin interrupts on negative edges | + * |#PIN_IRQ_BOTHEDGES |#PIN_BM_IRQ | Both | Pin interrupts on both edges | + * | |#PIN_BM_ALL | | Mask for *all* options | + * + * ## Initialization ## + * The PIN driver must be initialized before any other drivers are initialized. + * In order for IO pins to get a safe value as soon as possible PIN_init() + * should be called as early as possible in the boot sequence. Typically, + * PIN_init() is called at the start of main() before TI-RTOS is started with + * BIOS_start(). + * + * PIN_init() takes as an argument a #PIN_Config list containing default pin + * configurations. Typically the #PIN_Config list defined in the board files + * is used: + * @code + * PIN_init(BoardGpioInitTable); + * @endcode + * It is possible, however, to use another #PIN_Config list if desired. + * + * ## Power Management Interaction ## + * No specific interaction with power management module, as PIN is independent + * of power mode. + * + * ## Functionality Not Supported ## + * There is no known unsupported functionality. + * + * ## Instrumentation ## + * The pin driver does not use any of the instrumentation facilities. + * + * # Usage Examples # + * + * ## Initialization and Pin Allocation ## + * Example that illustrates when and how to call PIN_init(), PIN_open(), PIN_add(), PIN_close() + * @code + * // Default pin configuration. Typically resides in Board.c file. + * // IOs not mentioned here configured to default: input/output/pull disabled + * PIN_Config BoardGpioInitTable[] = { + * // DIO11: LED A (initially off) + * PIN_ID(11) | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * // DIO10: LED B (initially off) + * PIN_ID(10) | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * // DIO23: BUTTON A (ensure pull-up as button A is also used by other ICs) + * PIN_ID(23) | PIN_INPUT_EN | PIN_PULLUP | PIN_HYSTERESIS, + * // DIO3: LCD controller reset line (make sure LCD is in reset) + * PIN_ID(3) | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, + * // Terminate list + * PIN_TERMINATE + * }; + * + * Task_Struct taskStart; + * uint8_t taskStartStack[512]; + * + * // PIN_init() should be called as early as possible in boot + * void main() { + * // Default initialization of IO + * PIN_init(BoardGpioInitTable); + * + * // Configure startup task + * Task_Params taskParams; + * Task_Params_init(&taskParams); + * taskParams.stack = taskStartStack; + * taskParams.stackSize = sizeof(taskStartStack); + * Task_construct(&taskStart, taskStartFxn, &taskParams, NULL); + * + * // Start kernel (never returns) + * BIOS_start(); + * } + * + * // Human user interface PIN state/handle + * PIN_State hStateHui; + * #define HUI_LED_A PIN_ID(11) + * #define HUI_LED_B PIN_ID(10) + * #define HUI_LED_C PIN_ID(9) + * #define HUI_BUTTON_A PIN_ID(23) + * #define HUI_BUTTON_B PIN_ID(24) + * + * static void taskStartFxn(UArg a0, UArg a1) { + * // Define pins used by Human user interface and initial configuration + * const PIN_Config aPinListHui[] = { + * HUI_LED_A | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * HUI_LED_B | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * HUI_BUTTON_A | PIN_INPUT_EN | PIN_PULLUP | PIN_HYSTERESIS, + * HUI_BUTTON_B | PIN_INPUT_EN | PIN_PULLUP | PIN_HYSTERESIS, + * PIN_TERMINATE + * }; + * + * // Get handle to this collection of pins + * if (!PIN_open(&hStateHui, aPinListHui)) { + * // Handle allocation error + * } + * + * // ... + * + * // We can also add (and remove) pins to a set at run time + * PIN_Status status = PIN_add( + * &hStateHui, + * HUI_LED_C | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * ); + * if (status != PIN_SUCCESS) { + * // Handling allocation error is especially important with PIN_add() + * } + * + * // ... + * huiDoSomething(); + * + * // Before ending task, make sure to deallocate pins. They will return + * // to the default configurations provided in PIN_init() + * PIN_close(&hStateHui); + * } + * @endcode + * + * ## Application use of GPIO ## + * An example of using GPIO that builds on the previous example. Illustrates how + * to read input values, set output values and control output enable + * @code + * void huiDoSomething() { + * // Running lights on LEDs A-B-C (left to right). Button A causes left + * // movement, button B causes right movement, both simultaneously aborts + * // and disables LED output drivers + * + * // LED initial state (A off, B off, C on). Only our outputs are affected + * PIN_setPortOutputValue(&hStateHui, (1<0 right + * while (moveDir) { + * // Update LEDs + * if (moveDir<0) { + * // Left movement + * uint32_t t = PIN_getOutputValue(HUI_LED_A); + * PIN_setOutputValue(&hStateHui, HUI_LED_A, PIN_getOutputValue(HUI_LED_B)); + * PIN_setOutputValue(&hStateHui, HUI_LED_B, PIN_getOutputValue(HUI_LED_C)); + * PIN_setOutputValue(&hStateHui, HUI_LED_C, t); + * } else { + * // Right movement + * uint32_t t = PIN_getOutputValue(HUI_LED_C); + * PIN_setOutputValue(&hStateHui, HUI_LED_C, PIN_getOutputValue(HUI_LED_B)); + * PIN_setOutputValue(&hStateHui, HUI_LED_B, PIN_getOutputValue(HUI_LED_A)); + * PIN_setOutputValue(&hStateHui, HUI_LED_A, t); + * } + * + * // Sleep for 333 ms + * Task_sleep(333000/10); + * + * // Read input from both buttons simultaneously + * uint32_t buttons = PIN_getPortInputValue(&hStateHui); + * if (buttons&(1<0 right + * + * // Pin interrupt callback + * void huiPinIntCb(PIN_Handle handle, PIN_Id pinId) { + * // Ignore pinId and read input from both buttons simultaneously + * uint32_t buttons = PIN_getPortInputValue(&hStateHui); + * if (buttons&(1<0 right + * + * // Setup pin interrupts and register callback + * PIN_registerIntCb(&hStateHui, huiPinIntCb); + * PIN_setInterrupt(&hStateHui, HUI_BUTTON_A | PIN_IRQ_NEGEDGE); + * PIN_setInterrupt(&hStateHui, HUI_BUTTON_B | PIN_IRQ_NEGEDGE); + * + * while (moveDir) { + * // Update LEDs + * if (moveDir<0) { + * // Left movement + * uint32_t t = PIN_getOutputValue(HUI_LED_A); + * PIN_setOutputValue(&hStateHui, HUI_LED_A, PIN_getOutputValue(HUI_LED_B)); + * PIN_setOutputValue(&hStateHui, HUI_LED_B, PIN_getOutputValue(HUI_LED_C)); + * PIN_setOutputValue(&hStateHui, HUI_LED_C, t); + * } else { + * // Right movement + * uint32_t t = PIN_getOutputValue(HUI_LED_C); + * PIN_setOutputValue(&hStateHui, HUI_LED_C, PIN_getOutputValue(HUI_LED_B)); + * PIN_setOutputValue(&hStateHui, HUI_LED_B, PIN_getOutputValue(HUI_LED_A)); + * PIN_setOutputValue(&hStateHui, HUI_LED_A, t); + * } + * + * // Sleep for 333 ms (we will likely go into standby) + * Task_sleep(333000/10); + * } + * // Disable output enable for all pins (only our pins affected) + * PIN_setPortOutputEnable(&hStateHui, 0); + * // Disable pin interrupts + * PIN_setInterrupt(&hStateHui, HUI_BUTTON_A | PIN_IRQ_DIS); + * PIN_setInterrupt(&hStateHui, HUI_BUTTON_B | PIN_IRQ_DIS); + * } + * @endcode + * + ******************************************************************************* + */ + +#ifndef ti_drivers_PIN__include +#define ti_drivers_PIN__include +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +//#include + +typedef unsigned int uint_t; +typedef int int_t; + + +/** @brief Pin identifier data type + * + * Data type used to identify a pin through an index between 0 to 254. + * Typically the index does not refer to the physical device pin number but + * rather to the index of the subset of pins that are under software-control + * (e.g. index 3 refers to DIO3). + * This data type is used as arguments in API functions to identify which pin + * is affected or used in lists (terminated by #PIN_TERMINATE entry) identifying + * multiple pins + * @sa PIN_ID + */ +typedef uint8_t PIN_Id; + +/// Pin ID used to indicate no pin +#define PIN_UNASSIGNED 0xFF +/// Pin ID used to terminate a list of PIN_Id or PIN_Config entries +#define PIN_TERMINATE 0xFE + +/** @brief Pin configuration data type with embedded pin identifier + * + * A data type used to specify I/O-pin configuration options. The lower 8b + * contain an embedded pin ID (see #PIN_Id) and the top 24b contain + * flags/fields that affect I/O configuration. #PIN_Config entries can either + * use a @ref PIN_GENERIC_FLAGS "set of device-independent options" or + * device-specific options defined in PIN driver (e.g. PINCC26XX.h), but cannot + * mix the two. + * + * This data type is used as arguments or return values in API functions that + * manipulate pin configuration or used in lists (terminated by a + * #PIN_TERMINATE entry) for configuring multiple pins at a time. + */ +typedef uint32_t PIN_Config; + +/** @brief Macro for inserting or extracting a #PIN_Id in a #PIN_Config entry + * @par Usage + * @code + * PIN_Config pinCfg = PIN_ID(5) | PIN_GPIO_OUTPUT_EN | PIN_PUSHPULL | + * PIN_GPIO_HIGH | PIN_IRQ_POSEDGE; + * PIN_setConfig(hPins, PIN_BM_OUTPUT_MODE, pinCfg); + * // Trigger IRQ + * PIN_setOutputValue(hPins, PIN_ID(pinCfg), 1); + * @endcode + */ +#define PIN_ID(x) ((x)&0xFF) + + +/** @anchor PIN_GENERIC_FLAGS + * @name Generic PIN_Config flags/fields + * Generic (i.e. not device-specific) fields/flags for I/O configuration for + * use in #PIN_Config entries. All of these generic options may not be + * supported by the underlying device-specific PIN driver. A #PIN_Config + * entry may use either these generic fields/flags or device-specific ones + * defined in the device-specific PIN-driver, but may not mix the two. + * + * The entries starting with PIN_BM_ are bitmasks used to extract individual + * fields obtained from PIN_getConfig() or to pass as a parameter to + * PIN_setConfig()to define which options it should set. + * + * A star (*) in the descriptions below means the default if no option is + * supplied. + * \{ + */ +#define PIN_GEN (((uint32_t)1)<<31) ///< Flags that generic options are used + +#define PIN_INPUT_EN (PIN_GEN|(0<<29)) ///< (*) Enable input buffer +#define PIN_INPUT_DIS (PIN_GEN|(1<<29)) ///< Disable input buffer +#define PIN_HYSTERESIS (PIN_GEN|(1<<30)) ///< Enable input buffer hysteresis +#define PIN_NOPULL (PIN_GEN|(0<<13)) ///< (*) No pull-up or pull-down resistor +#define PIN_PULLUP (PIN_GEN|(1<<13)) ///< Pull-up resistor enabled +#define PIN_PULLDOWN (PIN_GEN|(2<<13)) ///< Pull-down resistor enabled +#define PIN_BM_INPUT_EN (1<<29) ///< Bitmask for input enable option +#define PIN_BM_HYSTERESIS (1<<30) ///< Bitmask input hysteresis option +#define PIN_BM_PULLING (0x3<<13) ///< Bitmask for pull-up/pull-down options + +/// Bitmask for all input mode options +#define PIN_BM_INPUT_MODE (PIN_BM_INPUT_EN|PIN_BM_HYSTERESIS|PIN_BM_PULLING) + +#define PIN_GPIO_OUTPUT_DIS (PIN_GEN|(0<<23)) ///< (*) Disable output buffer when GPIO +#define PIN_GPIO_OUTPUT_EN (PIN_GEN|(1<<23)) ///< Enable output buffer when GPIO +#define PIN_GPIO_LOW (PIN_GEN|(0<<22)) ///< Output buffer drives to VSS when GPIO +#define PIN_GPIO_HIGH (PIN_GEN|(1<<22)) ///< Output buffer drives to VDD when GPIO +#define PIN_PUSHPULL (PIN_GEN|(0<<25)) ///< (*) Output buffer mode: push/pull +#define PIN_OPENDRAIN (PIN_GEN|(2<<25)) ///< Output buffer mode: open drain +#define PIN_OPENSOURCE (PIN_GEN|(3<<25)) ///< Output buffer mode: open source +#define PIN_SLEWCTRL (PIN_GEN|(1<<12)) ///< Enable output buffer slew control +#define PIN_DRVSTR_MIN (PIN_GEN|(0x0<<8)) ///< (*) Lowest drive strength +#define PIN_DRVSTR_MED (PIN_GEN|(0x4<<8)) ///< Medium drive strength +#define PIN_DRVSTR_MAX (PIN_GEN|(0x8<<8)) ///< Highest drive strength +#define PIN_BM_GPIO_OUTPUT_EN (1<<23) ///< Bitmask for output enable option +#define PIN_BM_GPIO_OUTPUT_VAL (1<<22) ///< Bitmask for output value option +#define PIN_BM_OUTPUT_BUF (0x3<<25) ///< Bitmask for output buffer options +#define PIN_BM_SLEWCTRL (0x1<<12) ///< Bitmask for slew control options +#define PIN_BM_DRVSTR (0xF<<8) ///< Bitmask for drive strength options + +/// Bitmask for all output mode options +#define PIN_BM_OUTPUT_MODE (PIN_BM_GPIO_OUTPUT_VAL|PIN_BM_GPIO_OUTPUT_EN| \ + PIN_BM_OUTPUT_BUF|PIN_BM_SLEWCTRL|PIN_BM_DRVSTR) + +#define PIN_INV_INOUT (PIN_GEN|(1<<24)) ///< Logically invert input and output +#define PIN_BM_INV_INOUT (1<<24) ///< Bitmask for input/output inversion option + +#define PIN_IRQ_DIS (PIN_GEN|(0x0<<16)) ///< (*) Disable IRQ on pin +#define PIN_IRQ_NEGEDGE (PIN_GEN|(0x5<<16)) ///< Enable IRQ on negative edge +#define PIN_IRQ_POSEDGE (PIN_GEN|(0x6<<16)) ///< Enable IRQ on positive edge +#define PIN_IRQ_BOTHEDGES (PIN_GEN|(0x7<<16)) ///< Enable IRQ on both edges +#define PIN_BM_IRQ (0x7<<16) ///< Bitmask for pin interrupt option + +/// Bitmask for all options at once +#define PIN_BM_ALL (PIN_BM_INPUT_MODE|PIN_BM_OUTPUT_MODE|PIN_BM_INV_INOUT|PIN_BM_IRQ) +/** \} (PIN_GENERIC_FLAGS) + */ + + +/** @brief Struct used to store PIN client state + * Pointer to a PIN_State is used as handles (#PIN_Handle) in interactions with + * the I/O driver + * @note Must reside in persistent memory + * @note Fields must never be modified directly + */ +typedef struct PIN_State_s PIN_State; + + +/** @brief A handle that is returned from a PIN_open() call + * Used for further PIN client interaction with the PIN driver + */ +typedef PIN_State* PIN_Handle; + + +/** @brief I/O Interrupt callback function pointer type + * One PIN Interrupt callback can be registered by each PIN client and it + * will be called when one of the pins allocated by the client has an interrupt + * event. The callback is called from HWI context with handle and pin ID as + * arguments. + * @remark The callback must, as it runs in HWI context, execute and return + * quickly. Any lengthy operations should be performed in SWIs or tasks + * triggered by the callback + */ +typedef void (*PIN_IntCb)(PIN_Handle handle, PIN_Id pinId); + + +/** @brief underlying data structure for type #PIN_State + */ +struct PIN_State_s { + PIN_IntCb pCbFunc; ///< Pointer to interrupt callback function + uint_t bmPort; ///< Bitmask for pins allocated in port + UArg userArg; ///< User argument for whole handle + // TODO: add driver-specific field for extensions? +}; + +/// @brief Return value for many functions in the PIN driver interface +typedef enum { + PIN_SUCCESS = 0, ///< Operation succeeded + PIN_ALREADY_ALLOCATED = 1, ///< Operation failed, some pin already allocated + PIN_NO_ACCESS = 2, ///< Operation failed, client does not have access to pin + PIN_UNSUPPORTED = 3 ///< Operation not supported +} PIN_Status; + + +/** @brief PIN module initialization + * + * Must be called early in the boot sequence to ensure that I/O pins have safe + * configurations. This initialization sets up pins as GPIO as defined in an + * array (possibly user-generated) that typically resides in a board file. All + * pins not mentioned in aPinCfg[] are configured to be input/output/pull + * disabled. + * + * @note Function *cannot* be called more than once. + * + * @param aPinCfg[] Pointer to array of PIN_Config entries, one per pin + * that needs configuration. List terminates when a + * #PIN_TERMINATE entry is encountered. + * @return #PIN_SUCCESS if successful, else an error code. + */ +extern PIN_Status PIN_init(const PIN_Config aPinCfg[]); + + +/** @brief Allocate one or more pins for a driver or an application + * + * Allows a PIN client (driver or application) to allocate a set of pins, thus + * ensuring that they cannot be reconfigured/controlled by anyone else. The + * pins are identified by and reconfigured according to the #PIN_Config + * entries in aPinList. + * + * @param pState Pointer to a PIN_State object that will hold the state for + * this IO client. The object must be in persistent memory + * @param aPinList[] Pointer to array of #PIN_Config entries, one per pin to + * allocate. List terminates when #PIN_TERMINATE entry is + * encountered. + * @return A handle for further PIN driver calls or NULL if an error occurred + * (already allocated pin in aPinList or non-existent pin in aPinList) + */ +extern PIN_Handle PIN_open(PIN_State* pState, const PIN_Config aPinList[]); + + +/** @brief Add pin to pin set for open PIN handle + * + * If the requested pin is unallocated it will be added, else an error code + * will be returned. + * @param handle handle retrieved through an earlier call to PIN_open(). + * @param pinCfg Pin ID/configuration for pin to add. + * @return Error code if unsuccessful, else PIN_SUCCESS + */ +extern PIN_Status PIN_add(PIN_Handle handle, PIN_Config pinCfg); + + +/** @brief Removes pin from pin set foropen PIN handle + * + * If the requested pin is allocated to handle it will be removed from the pin + * set, else an error code will be returned. + * @param handle handle retrieved through an earlier call to PIN_open(). + * @param pinId Pin ID for pin to remove. + * @return Error code if unsuccessful, else PIN_SUCCESS + */ +extern PIN_Status PIN_remove(PIN_Handle handle, PIN_Id pinId); + + +/** @brief Deallocate all pins previously allocated with a call to PIN_open(). + * + * Deallocate pins allocated to handle and restore these pins to the + * pool of unallocated pins. Also restores the pin configuration to what it was + * set to when PIN_init() was called. + * @param handle handle retrieved through an earlier call to PIN_open(). + */ +extern void PIN_close(PIN_Handle handle); + + +/** @brief Sets a user argument associated with the handle + * + * Allows the application to store some data, for example a pointer to some + * data structure, with each PIN handle + * @param handle handle retrieved through an earlier call to PIN_open(). + * @param arg User argument + */ +static inline void PIN_setUserArg(PIN_Handle handle, UArg arg) { + if (handle) { + handle->userArg = arg; + } +} + + +/** @brief Gets a user argument associated with the handle + * + * Allows the application to store some data, for example a pointer to some + * data structure, with each PIN handle + * @param handle handle retrieved through an earlier call to PIN_open(). + * @return User argument. Has the value 0 if never initialized + */ +static inline UArg PIN_getUserArg(PIN_Handle handle) { + return handle->userArg; +} + + +/** @name Pin Manipulation/Configuration Functions + * Functions that are used to manipulate the configuration of I/O pins and to + * get input values and set output values. + * \{ + */ + +/** @brief Get pin input value (0/1) + * + * Input values of all pins are available to everyone so no handle required + * @param pinId ID of pin to get input value from + * @return Current input buffer value + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * myPin = PIN_getInputValue(PIN_ID(5)); + * @endcode + */ +extern uint_t PIN_getInputValue(PIN_Id pinId); + + +/** @brief Control output enable for GPIO pin + * + * @param handle Handle provided by previous call to PIN_open() + * @param pinId #PIN_Id entry identifying pin + * @param bOutEn Enable output buffer when true, else disable + * @return #PIN_SUCCESS if successful, else error code + * @remark This function is included for consistency with the corresponding + * port function and to provide a more efficient/directed approach. + * PIN_setConfig() can be used to achieve same result. + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * PIN_setOutputEnable(hPins, PIN_ID(11), 0); + * @endcode + */ +extern PIN_Status PIN_setOutputEnable(PIN_Handle handle, PIN_Id pinId, bool bOutEn); + + +/** @brief Control output value for GPIO pin + * + * @param handle Handle provided by previous call to PIN_open() + * @param pinId Pin ID + * @param val Output value (0/1) + * @return #PIN_SUCCESS if successful, else error code + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * PIN_setOutputValue(hPins, PIN_ID(4), 1); + * @endcode + */ +extern PIN_Status PIN_setOutputValue(PIN_Handle handle, PIN_Id pinId, uint_t val); + + +/** @brief Get value of GPIO pin output buffer + * + * Output values of all pins are available to everyone so no handle required + * @param pinId Pin ID + * @return Output value (0/1) + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * PIN_setOutputValue(hpins, PIN_ID(4), PIN_getOutputValue(PIN_ID(6))); + * @endcode + */ +extern uint_t PIN_getOutputValue(PIN_Id pinId); + + +/** @brief Control interrupt enable and edge for pin + * + * @param handle Handle provided by previous call to PIN_open() + * @param pinCfg #PIN_Config entry identifying pin ID and relevant pin + * configuration as combinations of: + * - #PIN_IRQ_DIS (default) + * - #PIN_IRQ_POSEDGE + * - #PIN_IRQ_NEGEDGE + * - #PIN_IRQ_BOTHEDGES + * @return #PIN_SUCCESS if successful, else error code + * @note Any pending interrupts on pins that have not had interrupt enabled + * will be cleared when enabling interrupts + * @par Usage + * @code + * PIN_setInterrupt(hPins, PIN_ID(8)|PIN_IRQ_POSEDGE); + * @endcode + */ +extern PIN_Status PIN_setInterrupt(PIN_Handle handle, PIN_Config pinCfg); + + +/** @brief Clear pending interrupt for pin, if any + * + * @param handle Handle provided by previous call to PIN_open() + * @param pinId #PIN_Id for pin to clear pending interrupt for + * @return #PIN_SUCCESS if successful, else error code + * @par Usage + * @code + * PIN_ClrPendInterrupt(hPins, PIN_ID(8)); + * @endcode + */ +extern PIN_Status PIN_clrPendInterrupt(PIN_Handle handle, PIN_Id pinId); + + +/** @brief Register callback function for a set of pins + * + * Registers a callback function (see #PIN_IntCb for details) for the client + * identified by handle that will be called from HWI context upon an interrupt + * event on one or more of the allocated pins that have interrupts enabled + * @param handle Handle provided by previous call to PIN_open() + * @param pCb Function pointer to a #PIN_IntCb function. + * @return #PIN_SUCCESS if successful, else error code + * @note Pin interrupts are serviced one at a time in pin order when + * simultaneous. Pin hardware interrupt flags are automatically cleared + * by PIN driver. + * @par Usage + * @code + * void pinIntHandler(PIN_Handle handle, PIN_Id pinId) { + * // Handle pin interrupt + * } + * ... + * PIN_registerIntCb(hPins, pinIntHandler); + * @endcode + */ +extern PIN_Status PIN_registerIntCb(PIN_Handle handle, PIN_IntCb pCb); + + + +/** @brief Returns pin configuration + * + * @param pinId Pin ID + * @return Current pin configuration as a device-independent #PIN_Config value + * @note The pin ID is embedded in return value. + * @note There is usually a device-specific version of this function that + * returns device-specific options + * @par Usage + * @code + * // Get config of pin 14 to be able to revert later + * myPinConfig = PIN_getConfig(PIN_ID(14)); + * // ... + * // Lots of pin reconfigurations + * // ... + * // Restore previous configuration + * PIN_setConfig(hPins, PIN_BM_ALL, myPinConfig); + * @endcode + */ +extern PIN_Config PIN_getConfig(PIN_Id pinId); + + +/** @brief Sets complete pin configuration + * + * @param handle Handle provided by previous call to PIN_open() + * @param bmMask Bitmask specifying which fields in cfg that should take + * effect, the rest keep their current value. + * @param pinCfg #PIN_Config entry with pin ID and pin configuration + * @return #PIN_SUCCESS if successful, else error code + * @par Usage + * @code + * // Set drive strength on pin 15 + * PIN_setConfig(hPins, PIN_BM_DRVSTR, PIN_ID(15)|PIN_DRVSTR_MAX); + * @endcode + */ +extern PIN_Status PIN_setConfig(PIN_Handle handle, PIN_Config bmMask, PIN_Config pinCfg); + + +/** \} (IO Manipulation/Configuration Functions) + */ + + +/** @name IO Port Functions + * Functions used to get input values for, set ouput values for and set output + * enables for multiple pins at a time. The size of so-called I/O ports that + * allows such multiple-pin operations are highly device dependent. In order to + * use the I/O port functions a set of pins that reside in the same I/O port + * must have been allocated previously with PIN_open(). + * \{ + */ + + +/** @brief Returns bitmask indicating pins allocated to client in GPIO port + * + * @param handle Handle provided by previous call to PIN_open() + * @return A bitmask indicating which bit positions in an I/O port the + * allocated I/O pins lie on, or zero if I/O port operations are not + * supported or the allocated pins span multiple I/O ports. The bitmask + * maps lowest pin index to the rightmost mask bit + */ +extern uint_t PIN_getPortMask(PIN_Handle handle); + + +/** @brief Read input value of whole GPIO port + * + * @param handle Handle provided by previous call to PIN_open() + * @return The simultaneous input value for the whole I/O port masked by the + * bit mask for the client's allocated pins + * @sa PIN_getPortMask() + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + */ +extern uint_t PIN_getPortInputValue(PIN_Handle handle); + + +/** @brief Returns value of whole GPIO port's output buffers + * + * The I/O port is identified by the pins allocated by client in a previous + * call to PIN_open() + * @param handle Handle provided by previous call to PIN_open() + * @return The current output value for whole I/O port + * @sa PIN_getPortMask() + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + */ +extern uint_t PIN_getPortOutputValue(PIN_Handle handle); + + +/** @brief Simultaneous write output buffer values of all allocated pins in GPIO port + * + * @param handle Handle provided by previous call to PIN_open() + * @param bmOutVal Bitmask indicating the desired output value for the whole + * port, only the pins allocated to the client will be + * affected + * @return #PIN_SUCCESS if successful, else error code + * @sa PIN_getPortMask() + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * // Invert all pins allocated to client + * PIN_setPortOutputVal(hPins, ~PIN_getPortOutputVals(hPins)); + * @endcode + */ +extern PIN_Status PIN_setPortOutputValue(PIN_Handle handle, uint_t bmOutVal); + + +/** @brief Set output enable for all pins allocated to client in GPIO port + * + * @param handle Handle provided by previous call to PIN_open() + * @param bmOutEn Bitmask indicating the desired output enable configuration + * for the whole port, only the pins allocated to the client + * will be affected + * @return #PIN_SUCCESS if successful, else error code + * @sa PIN_getPortMask() + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * // Set output to 0 on all allocated pins, then enable the output drivers + * pin_setPortOutputVal(hPins, 0); + * pin_setPortOutputEnable(hPins, PIN_getPortMask()); + * @endcode + */ +extern PIN_Status PIN_setPortOutputEnable(PIN_Handle handle, uint_t bmOutEn); + + +/** \} (IO Port Functions) + */ + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_PIN__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/PWM.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/PWM.h new file mode 100644 index 000000000..db372e3ea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/PWM.h @@ -0,0 +1,591 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PWM.h + * @brief PWM driver interface + * + * To use the PWM driver, ensure that the correct driver library for your + * device is linked in and include this header file as follows: + * @code + * #include + * @endcode + * + * This module serves as the main interface for applications. Its purpose + * is to redirect the PWM APIs to specific driver implementations + * which are specified using a pointer to a #PWM_FxnTable. + * + * # Overview # + * The PWM driver in TI-RTOS facilitates the generation of Pulse Width + * Modulated signals via simple and portable APIs. PWM instances must be + * opened by calling PWM_open() while passing in a PWM index and a parameters + * data structure. + * + * The driver APIs serve as an interface to a typical TI-RTOS application. + * The specific peripheral implementations are responsible for creating all OS + * specific primitives to allow for thread-safe operation. + * + * When a PWM instance is opened, the period, duty cycle and idle level are + * configured and the PWM is stopped (waveforms not generated until PWM_start() + * is called). The maximum period and duty supported is device dependent; + * refer to the implementation specific documentation for values. + * + * PWM outputs are active-high, meaning the duty will control the duration of + * high output on the pin (at 0% duty, the output is always low, at 100% duty, + * the output is always high). + * + * # Usage # + * + * @code + * PWM_Handle pwm; + * PWM_Params pwmParams; + * + * // Initialize the PWM driver. + * PWM_init(); + * + * // Initialize the PWM parameters + * PWM_Params_init(&pwmParams); + * pwmParams.idleLevel = PWM_IDLE_LOW; // Output low when PWM is not running + * pwmParams.period.unit = PWM_PERIOD_HZ; // Period is in Hz + * pwmParams.period.value = 1e6; // 1MHz + * pwmParams.duty.unit = PWM_DUTY_FRACTION; // Duty is in fractional percentage + * pwmParams.duty.value = 0; // 0% initial duty cycle + * + * // Open the PWM instance + * pwm = PWM_open(Board_PWM0, &pwmParams); + * + * if (pwm == NULL) { + * // PWM_open() failed + * while (1); + * } + * + * PWM_start(handle); // start PWM with 0% duty cycle + * + * PWM_setDuty(pwm, + * (PWM_DUTY_FRACTION_MAX / 2)); // set duty cycle to 50% + * @endcode + * + * Details for the example code above are described in the following + * subsections. + * + * ### PWM Driver Configuration # + * + * In order to use the PWM APIs, the application is required + * to provide device-specific PWM configuration in the Board.c file. + * The PWM driver interface defines a configuration data structure: + * + * @code + * typedef struct PWM_Config_ { + * PWM_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } PWM_Config; + * @endcode + * + * The application must declare an array of PWM_Config elements, named + * PWM_config[]. Each element of PWM_config[] is populated with + * pointers to a device specific PWM driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as which pin will be driven, and which timer peripheral + * will be used. Each element in PWM_config[] corresponds to + * a PWM instance, and none of the elements should have NULL pointers. + * + * Additionally, the PWM driver interface defines a global integer variable + * 'PWM_count' which is initialized to the number of PWM instances the + * application has defined in the PWM_Config array. + * + * You will need to check the device-specific PWM driver implementation's + * header file for example configuration. Please also refer to the + * Board.c file of any of your examples to see the PWM configuration. + * + * ### Initializing the PWM Driver # + * + * PWM_init() must be called before any other PWM APIs. This function + * calls the device implementation's PWM initialization function, for each + * element of PWM_config[]. + * + * ### Opening the PWM Driver # + * + * Opening a PWM requires four steps: + * 1. Create and initialize a PWM_Params structure. + * 2. Fill in the desired parameters. + * 3. Call PWM_open(), passing the index of the PWM in the PWM_config + * structure, and the address of the PWM_Params structure. The + * PWM instance is specified by the index in the PWM_config structure. + * 4. Check that the PWM handle returned by PWM_open() is non-NULL, + * and save it. The handle will be used to read and write to the + * PWM you just opened. + * + * Only one PWM index can be used at a time; calling PWM_open() a second + * time with the same index previously passed to PWM_open() will result in + * an error. You can, though, re-use the index if the instance is closed + * via PWM_close(). + * In the example code, Board_PWM0 is passed to PWM_open(). This macro + * is defined in the example's Board.h file. + * + * ### Modes of Operation # + * + * A PWM instance can be configured to interpret the period as one of three + * units: + * - #PWM_PERIOD_US: The period is in microseconds. + * - #PWM_PERIOD_HZ: The period is in (reciprocal) Hertz. + * - #PWM_PERIOD_COUNTS: The period is in timer counts. + * + * A PWM instance can be configured to interpret the duty as one of three + * units: + * - #PWM_DUTY_US: The duty is in microseconds. + * - #PWM_DUTY_FRACTION: The duty is in a fractional part of the period + * where 0 is 0% and #PWM_DUTY_FRACTION_MAX is 100%. + * - #PWM_DUTY_COUNTS: The period is in timer counts and must be less than + * the period. + * + * The idle level parameter is used to set the output to high/low when the + * PWM is not running (stopped or not started). The idle level can be + * set to: + * - #PWM_IDLE_LOW + * - #PWM_IDLE_HIGH + * + * The default PWM configuration is to set a duty of 0% with a 1MHz frequency. + * The default period units are in PWM_PERIOD_HZ and the default duty units + * are in PWM_DUTY_FRACTION. Finally, the default output idle level is + * PWM_IDLE_LOW. It is the application's responsibility to set the duty for + * each PWM output used. + * + * ### Controlling the PWM Duty Cycle # + * + * Once the PWM instance has been opened and started, the primary API used + * by the application will be #PWM_setDuty() to control the duty cycle of a + * PWM pin: + * + * @code + * PWM_setDuty(pwm, PWM_DUTY_FRACTION_MAX / 2); // Set 50% duty cycle + * @endcode + * + * # Implementation # + * + * The PWM driver interface module is joined (at link time) to an + * array of PWM_Config data structures named *PWM_config*. + * PWM_config is implemented in the application with each entry being a + * PWM instance. Each entry in *PWM_config* contains a: + * - (PWM_FxnTable *) to a set of functions that implement a PWM peripheral + * - (void *) data object that is associated with the PWM_FxnTable + * - (void *) hardware attributes that are associated with the PWM_FxnTable + * + * The PWM APIs are redirected to the device specific implementations + * using the PWM_FxnTable pointer of the PWM_config entry. + * In order to use device specific functions of the PWM driver directly, + * link in the correct driver library for your device and include the + * device specific PWM driver header file (which in turn includes PWM.h). + * For example, for the MSP432 family of devices, you would include the + * following header file: + * @code + * #include + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_PWM__include +#define ti_drivers_PWM__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*! + * @brief Maximum duty (100%) when configuring duty cycle as a fraction of + * period. + */ +#define PWM_DUTY_FRACTION_MAX ((uint32_t) ~0) + +/*! + * Common PWM_control command code reservation offset. + * PWM driver implementations should offset command codes with PWM_CMD_RESERVED + * growing positively. + * + * Example implementation specific command codes: + * @code + * #define PWMXYZ_COMMAND0 (PWM_CMD_RESERVED + 0) + * #define PWMXYZ_COMMAND1 (PWM_CMD_RESERVED + 1) + * @endcode + */ +#define PWM_CMD_RESERVED (32) + +/*! + * Common PWM_control status code reservation offset. + * PWM driver implementations should offset status codes with + * PWM_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define PWMXYZ_STATUS_ERROR0 (PWM_STATUS_RESERVED - 0) + * #define PWMXYZ_STATUS_ERROR1 (PWM_STATUS_RESERVED - 1) + * #define PWMXYZ_STATUS_ERROR2 (PWM_STATUS_RESERVED - 2) + * @endcode + */ +#define PWM_STATUS_RESERVED (-32) + +/*! + * @brief Success status code returned by: + * PWM_control(), PWM_setDuty(), PWM_setPeriod(). + * + * Functions return PWM_STATUS_SUCCESS if the call was executed + * successfully. + */ +#define PWM_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by PWM_control(). + * + * PWM_control() returns PWM_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define PWM_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by PWM_control() for undefined + * command codes. + * + * PWM_control() returns PWM_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define PWM_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned by PWM_setPeriod(). + * + * PWM_setPeriod() returns PWM_STATUS_INVALID_PERIOD if the period argument is + * invalid for the current configuration. + */ +#define PWM_STATUS_INVALID_PERIOD (-3) + +/*! + * @brief An error status code returned by PWM_setDuty(). + * + * PWM_setDuty() returns PWM_STATUS_INVALID_DUTY if the duty cycle argument is + * invalid for the current configuration. + */ +#define PWM_STATUS_INVALID_DUTY (-4) + +/*! + * @brief PWM period unit definitions. Refer to device specific + * implementation if using PWM_PERIOD_COUNTS (raw PWM/Timer counts). + */ +typedef enum PWM_Period_Units_ { + PWM_PERIOD_US, /* Period in microseconds */ + PWM_PERIOD_HZ, /* Period in (reciprocal) Hertz + (for example 2MHz = 0.5us period) */ + PWM_PERIOD_COUNTS /* Period in timer counts */ +} PWM_Period_Units; + +/*! + * @brief PWM duty cycle unit definitions. Refer to device specific + * implementation if using PWM_DUTY_COUNTS (raw PWM/Timer counts). + */ +typedef enum PWM_Duty_Units_ { + PWM_DUTY_US, /* Duty cycle in microseconds */ + PWM_DUTY_FRACTION, /* Duty as a fractional part of PWM_DUTY_FRACTION_MAX */ + PWM_DUTY_COUNTS /* Duty in timer counts */ +} PWM_Duty_Units; + +/*! + * @brief Idle output level when PWM is not running (stopped / not started). + */ +typedef enum PWM_IdleLevel_ { + PWM_IDLE_LOW = 0, + PWM_IDLE_HIGH = 1, +} PWM_IdleLevel; + +/*! + * @brief PWM Parameters + * + * PWM Parameters are used to with the PWM_open() call. Default values for + * these parameters are set using PWM_Params_init(). + * + * @sa PWM_Params_init() + */ +typedef struct PWM_Params_ { + PWM_Period_Units periodUnits; /*!< Units in which the period is specified */ + uint32_t periodValue; /*!< PWM initial period */ + PWM_Duty_Units dutyUnits; /*!< Units in which the duty is specified */ + uint32_t dutyValue; /*!< PWM initial duty */ + PWM_IdleLevel idleLevel; /*!< Pin output when PWM is stopped. */ + void *custom; /*!< Custom argument used by driver + implementation */ +} PWM_Params; + +/*! + * @brief A handle that is returned from a PWM_open() call. + */ +typedef struct PWM_Config_ *PWM_Handle; + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_close(). + */ +typedef void (*PWM_CloseFxn) (PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_control(). + */ +typedef int_fast16_t (*PWM_ControlFxn) (PWM_Handle handle, uint_fast16_t cmd, + void *arg); +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_init(). + */ +typedef void (*PWM_InitFxn) (PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_open(). + */ +typedef PWM_Handle (*PWM_OpenFxn) (PWM_Handle handle, PWM_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setDuty(). + */ +typedef int_fast16_t (*PWM_SetDutyFxn) (PWM_Handle handle, + uint32_t duty); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setPeriod(). + */ +typedef int_fast16_t (*PWM_SetPeriodFxn) (PWM_Handle handle, + uint32_t period); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_start(). + */ +typedef void (*PWM_StartFxn) (PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_stop(). + */ +typedef void (*PWM_StopFxn) (PWM_Handle handle); + +/*! + * @brief The definition of a PWM function table that contains the + * required set of functions to control a specific PWM driver + * implementation. + */ +typedef struct PWM_FxnTable_ { + /*! Function to close the specified instance */ + PWM_CloseFxn closeFxn; + /*! Function to driver implementation specific control function */ + PWM_ControlFxn controlFxn; + /*! Function to initialize the given data object */ + PWM_InitFxn initFxn; + /*! Function to open the specified instance */ + PWM_OpenFxn openFxn; + /*! Function to set the duty cycle for a specific instance */ + PWM_SetDutyFxn setDutyFxn; + /*! Function to set the period for a specific instance */ + PWM_SetPeriodFxn setPeriodFxn; + /*! Function to start the PWM output for a specific instance */ + PWM_StartFxn startFxn; + /*! Function to stop the PWM output for a specific instance */ + PWM_StopFxn stopFxn; +} PWM_FxnTable; + +/*! + * @brief PWM Global configuration. + * + * The PWM_Config structure contains a set of pointers used to characterize + * the PWM driver implementation. + * + */ +typedef struct PWM_Config_ { + /*! Pointer to a table of driver-specific implementations of PWM APIs */ + PWM_FxnTable const *fxnTablePtr; + /*! Pointer to a driver specific data object */ + void *object; + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} PWM_Config; + +/*! + * @brief Function to close a PWM instance specified by the PWM handle. + * + * @pre PWM_open() must have been called first. + * @pre PWM_stop() must have been called first if PWM was started. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_start() + * @sa PWM_stop() + */ +extern void PWM_close(PWM_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * PWM_Handle. + * + * @pre PWM_open() must have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @param cmd A command value defined by the driver specific + * implementation. + * + * @param arg A pointer to an optional R/W (read/write) argument that + * is accompanied with cmd. + * + * @return A PWM_Status describing an error or success state. Negative values + * indicate an error occurred. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief This function initializes the PWM module. + * + * @pre The PWM_config structure must exist and be persistent before this + * function can be called. This function must be called before any + * other PWM driver APIs. This function does not modify any peripheral + * registers & should only be called once. + */ +extern void PWM_init(void); + +/*! + * @brief This function opens a given PWM instance and sets the period, + * duty and idle level to those specified in the params argument. + * + * @param index Logical instance number for the PWM indexed into + * the PWM_config table. + * + * @param params Pointer to an parameter structure. If NULL default + * values are used. + * + * @return A PWM_Handle if successful or NULL on an error or if it has been + * opened already. If NULL is returned further PWM API calls will + * result in undefined behavior. + * + * @sa PWM_close() + */ +extern PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params); + +/*! + * @brief Function to initialize the PWM_Params structure to default values. + * + * @param params A pointer to PWM_Params structure for initialization. + * + * Defaults values are: + * Period units: PWM_PERIOD_HZ + * Period: 1e6 (1MHz) + * Duty cycle units: PWM_DUTY_FRACTION + * Duty cycle: 0% + * Idle level: PWM_IDLE_LOW + */ +extern void PWM_Params_init(PWM_Params *params); + +/*! + * @brief Function to set the duty cycle of the specified PWM handle. PWM + * instances run in active high output mode; 0% is always low output, + * 100% is always high output. This API can be called while the PWM + * is running & duty must always be lower than or equal to the period. + * If an error occurs while calling the function the PWM duty cycle + * will remain unchanged. + * + * @pre PWM_open() must have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @param duty Duty cycle in the units specified by the params used + * in PWM_open(). + * + * @return A PWM status describing an error or success. Negative values + * indicate an error. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty); + +/*! + * @brief Function to set the period of the specified PWM handle. This API + * can be called while the PWM is running & the period must always be + * larger than the duty cycle. + * If an error occurs while calling the function the PWM period + * will remain unchanged. + * + * @pre PWM_open() must have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @param period Period in the units specified by the params used + * in PWM_open(). + * + * @return A PWM status describing an error or success state. Negative values + * indicate an error. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period); + +/*! + * @brief Function to start the specified PWM handle with current settings. + * + * @pre PWM_open() has to have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_stop() + */ +extern void PWM_start(PWM_Handle handle); + +/*! + * @brief Function to stop the specified PWM handle. Output will set to the + * idle level specified by params in PWM_open(). + * + * @pre PWM_open() has to have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_start() + */ +extern void PWM_stop(PWM_Handle handle); + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_PWM__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Power.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Power.h new file mode 100644 index 000000000..7419300ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Power.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file Power.h + * + * @brief Power manager interface + * + * The Power header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * The Power manager facilitates the transition of the MCU from active state + * to one of the sleep states and vice versa. It provides drivers the + * ability to set and release dependencies on hardware resources and keeps + * a reference count on each resource to know when to enable or disable the + * peripheral clock to the resource. It provides drivers the ability to + * register a callback function upon a specific power event. In addition, + * drivers and apps can set or release constraints to prevent the MCU from + * transitioning into a particular sleep state. + * + * ============================================================================ + */ + +#ifndef ti_drivers_Power__include +#define ti_drivers_Power__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Power latency types */ +#define Power_TOTAL (1U) /*!< total latency */ +#define Power_RESUME (2U) /*!< resume latency */ + +/* Power notify responses */ +#define Power_NOTIFYDONE (0) /*!< OK, notify completed */ +#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */ + +/* Power status */ +#define Power_SOK (0) /*!< OK, operation succeeded */ +#define Power_EFAIL (-1) /*!< general failure */ +#define Power_EINVALIDINPUT (-2) /*!< invalid data value */ +#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */ +#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */ +#define Power_EBUSY (-5) /*!< busy with another transition */ + +/* Power transition states */ +#define Power_ACTIVE (1U) /*!< normal active state */ +#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */ +#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */ +#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */ +#define Power_CHANGING_PERF_LEVEL (5U) /*!< moving to new performance level */ + + +/*! + * @brief Power policy initialization function pointer + */ +typedef void (*Power_PolicyInitFxn)(void); + +/*! + * @brief Power policy function pointer + */ +typedef void (*Power_PolicyFxn)(void); + +/*! + * @brief Power notify function pointer + */ +typedef int_fast16_t (*Power_NotifyFxn)(uint_fast16_t eventType, + uintptr_t eventArg, uintptr_t clientArg); + +/*! + * @brief Power notify object structure. + * + * This struct specification is for internal use. Notification clients must + * pre-allocate a notify object when registering for a notification; + * Power_registerNotify() will take care initializing the internal elements + * appropriately. + */ +typedef struct Power_NotifyObj_ { + List_Elem link; /*!< for placing on the notify list */ + uint_fast16_t eventTypes; /*!< the event type */ + Power_NotifyFxn notifyFxn; /*!< notification function */ + uintptr_t clientArg; /*!< argument provided by client */ +} Power_NotifyObj; + +/*! + * @brief Disable the configured power policy from running when the CPU is + * idle + * + * Calling this function clears the flag that controls whether the configured + * power policy function is invoked on each pass through the Idle loop. + * This function call will override both a 'true' setting of the + * "enablePolicy" setting in the Power manager configuration object, as well + * as a previous runtime call to the Power_enablePolicy() function. + * + * @sa Power_enablePolicy + */ +void Power_disablePolicy(void); + +/*! + * @brief Enable the configured power policy to run when the CPU is idle + * + * Calling this function sets a flag that will cause the configured power + * policy function to be invoked on each pass through the Idle loop. This + * function call will override both a 'false' setting of the "enablePolicy" + * setting in the Power manager configuration object, as well as a previous + * runtime call to the Power_disablePolicy() function. + * + * For some processor families, automatic power transitions can make initial + * application development more difficult, as well as being at odds with + * basic debugger operation. This convenience function allows an application + * to be initially configured, built, and debugged, without automatic power + * transitions during idle time. When the application is found to be working, + * this function can be called (typically in main()) to enable the policy + * to run, without having to change the application configuration. + * + * @sa Power_disablePolicy + */ +void Power_enablePolicy(void); + +/*! + * @brief Get the constraints that have been declared with Power + * + * This function returns a bitmask indicating the constraints that are + * currently declared to the Power manager (via previous calls to + * Power_setConstraint()). For each constraint that is currently declared, + * the corresponding bit in the bitmask will be set. For example, if two + * clients have independently declared two different constraints, the returned + * bitmask will have two bits set. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * MSP432 are defined in PowerMSP432.h. The corresponding bit in the + * bitmask returned by this function can be derived by a left-shift using + * the constraint identifier. For example, for MSP432, for the corresponding + * bit for the PowerMSP432_DISALLOW_SLEEP constraint, the bit position is + * determined by the operation: (1 << PowerMSP432_DISALLOW_SLEEP) + * + * @return A bitmask of the currently declared constraints. + * + * @sa Power_setConstraint + */ +uint_fast32_t Power_getConstraintMask(void); + +/*! + * @brief Get the current dependency count for a resource + * + * This function returns the number of dependencies that are currently + * declared upon a resource. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param resourceId resource id + * + * @return The number of dependencies declared for the resource. + * Power_EINVALIDINPUT if the resourceId is invalid. + * + * @sa Power_setDependency + */ +int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId); + +/*! + * @brief Get the current performance level + * + * This function returns the current device performance level in effect. + * + * If performance scaling is not supported for the device, this function + * will always indicate a performance level of zero. + * + * @return The current performance level. + * + * @sa Power_setPerformanceLevel + */ +uint_fast16_t Power_getPerformanceLevel(void); + +/*! + * @brief Get the hardware transition latency for a sleep state + * + * This function reports the minimal hardware transition latency for a specific + * sleep state. The reported latency is that for a direct transition, and does + * not include any additional latency that might occur due to software-based + * notifications. + * + * Sleep states are device specific, and defined in the device-specific Power + * include file. For example, the sleep states for CC32XX are defined in + * PowerCC32XX.h. + * + * This function is typically called by the power policy function. The latency + * is reported in units of microseconds. + * + * @param sleepState the sleep state + * + * @param type the latency type (Power_TOTAL or Power_RESUME) + * + * @return The latency value, in units of microseconds. + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, + uint_fast16_t type); + +/*! + * @brief Get the current transition state of the Power manager + * + * This function returns the current transition state for the Power manager. + * For example, when no transitions are in progress, a status of Power_ACTIVE + * is returned. Power_ENTERING_SLEEP is returned during the transition to + * sleep, before sleep has occurred. Power_EXITING_SLEEP is returned + * after wakeup, as the device is being transitioned back to Power_ACTIVE. + * And Power_CHANGING_PERF_LEVEL is returned when a change is being made + * to the performance level. + * + * @return The current Power manager transition state. + */ +uint_fast16_t Power_getTransitionState(void); + +/*! + * @brief Power function to be added to the application idle loop + * + * This function should be added to the application idle loop. (The method to + * do this depends upon the operating system being used.) This function + * will invoke the configured power policy function when appropriate. The + * specific policy function to be invoked is configured as the 'policyFxn' + * in the application-defined Power configuration object. + * + */ +void Power_idleFunc(void); + +/*! + * @brief Power initialization function + * + * This function initializes Power manager internal state. It must be called + * prior to any other Power API. This function is normally called as part + * of TI-RTOS board initialization, for example, from within the + * \_initGeneral() function. + * + * @return Power_SOK + */ +int_fast16_t Power_init(void); + +/*! + * @brief Register a function to be called upon a specific power event + * + * This function registers a function to be called when a Power event occurs. + * Registrations and the corresponding notifications are processed in + * first-in-first-out (FIFO) order. The function registered must behave as + * described later, below. + * + * The pNotifyObj parameter is a pointer to a pre-allocated, opaque object + * that will be used by Power to support the notification. This object could + * be dynamically allocated, or declared as a global object. This function + * will properly initialized the object's fields as appropriate; the caller + * just needs to provide a pointer to this pre-existing object. + * + * The eventTypes parameter identifies the type of power event(s) for which + * the notify function being registered is to be called. (Event identifiers are + * device specific, and defined in the device-specific Power include file. + * For example, the events for MSP432 are defined in PowerMSP432.h.) The + * eventTypes parameter for this function call is treated as a bitmask, so + * multiple event types can be registered at once, using a common callback + * function. For example, to call the specified notifyFxn when both + * the entering deepsleep and awake from deepsleep events occur, eventTypes + * should be specified as: PowerMSP432_ENTERING_DEEPSLEEP | + * PowerMSP432_AWAKE_DEEPSLEEP + * + * The notifyFxn parameter specifies a callback function to be called when the + * specified Power event occurs. The notifyFxn must implement the following + * signature: + * status = notifyFxn(eventType, eventArg, clientArg); + * + * Where: eventType identifies the event being signalled, eventArg is an + * optional event-specific argument, and clientArg is an abitrary argument + * specified by the client at registration. Note that multipe types of events + * can be specified when registering the notification callback function, + * but when the callback function is actually called by Power, only a + * single eventType will be specified for the callback (i.e., the current + * event). The status returned by the client notification function must + * be one of the following constants: Power_NOTIFYDONE if the client processed + * the notification successfully, or Power_NOTIFYERROR if an error occurred + * during notification. + * + * The clientArg parameter is an arbitrary, client-defined argument to be + * passed back to the client upon notification. This argument may allow one + * notify function to be used by multiple instances of a driver (that is, the + * clientArg can be used to identify the instance of the driver that is being + * notified). + * + * @param pNotifyObj notification object (preallocated by caller) + * + * @param eventTypes event type or types + * + * @param notifyFxn client's callback function + * + * @param clientArg client-specified argument to pass with notification + * + * @return Power_SOK on success. + * Power_EINVALIDPOINTER if either pNotifyObj or notifyFxn are NULL. + * + * @sa Power_unregisterNotify + */ +int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj, + uint_fast16_t eventTypes, + Power_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Release a previously declared constraint + * + * This function releases a constraint that was previously declared with + * Power_setConstraint(). For example, if a device driver is starting an I/O + * transaction and wants to prohibit activation of a sleep state during the + * transaction, it uses Power_setConstraint() to declare the constraint, + * before starting the transaction. When the transaction completes, the + * driver calls this function to release the constraint, to allow the Power + * manager to once again allow transitions to sleep. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * MSP432 are defined in PowerMSP432.h. + * + * Only one constraint can be specified with each call to this function; to + * release multiple constraints this function must be called multiple times. + * + * It is critical that clients call Power_releaseConstraint() when operational + * constraints no longer exists. Otherwise, Power may be left unnecessarily + * restricted from activating power savings. + * + * @param constraintId constraint id + * + * @return Power_SOK on success. + * Power_EINVALIDINPUT if the constraintId is incorrect. + * Power_EFAIL if the constraint cannot be released. + * + * @sa Power_setConstraint + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId); + +/*! + * @brief Release a previously declared dependency + * + * This function releases a dependency that had been previously declared upon + * a resource (by a call to Power_setDependency()). + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param resourceId resource id + * + * @return Power_SOK on success. + * Power_EINVALIDINPUT if the resourceId is incorrect. + * Power_EFAIL if the resource dependency cannot be released. + * + * @sa Power_setDependency + */ +int_fast16_t Power_releaseDependency(uint_fast16_t resourceId); + +/*! + * @brief Declare an operational constraint + * + * Before taking certain actions, the Power manager checks to see if the + * requested action would conflict with a client-declared constraint. If the + * action does conflict, Power will not proceed with the request. This is the + * function that allows clients to declare their constraints with Power. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * MSP432 are defined in PowerMSP432.h. + * + * Only one constraint can be specified with each call to this function; to + * declare multiple constraints this function must be called multiple times. + * + * @param constraintId constraint id + * + * @return Power_SOK on success. + * Power_EINVALIDINPUT if the constraintId is incorrect. + * + * @sa Power_releaseConstraint + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId); + +/*! + * @brief Declare a dependency upon a resource + * + * This function declares a dependency upon a resource. For example, if a + * UART driver needs a specific UART peripheral, it uses this function to + * declare this to the Power manager. If the resource had been inactive, + * then Power will activate the peripheral during this function call. + * + * What is needed to make a peripheral resource 'active' will vary by device + * family. For some devices this may be a simple enable of a clock to the + * specified peripheral. For others it may also require a power on of a + * power domain. In either case, the Power manager will take care of these + * details, and will also implement reference counting for resources and their + * interdependencies. For example, if multiple UART peripherals reside in + * a shared serial power domain, the Power manager will power up the serial + * domain when it is first needed, and then automatically power the domain off + * later, when all related dependencies for the relevant peripherals are + * released. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param resourceId resource id + * + * @return Power_SOK on success. + * Power_EINVALIDINPUT if the resourceId is incorrect. + * + * @sa Power_releaseDependency + */ +int_fast16_t Power_setDependency(uint_fast16_t resourceId); + +/*! + * @brief Set the MCU performance level + * + * This function manages a transition to a new device performance level. + * Before the actual transition is initiated, notifications will be sent to + * any clients who've registered (with Power_registerNotify()) for a + * 'start change performance level' notification. The event name is device + * specific, and defined in the device-specific Power include file. For + * example, for MSP432, the event is "PowerMSP432_START_CHANGE_PERF_LEVEL", + * which is defined in PowerMSP432.h. Once notifications have been completed, + * the change to the performance level is initiated. After the level change + * is completed, there is a comparable event that can be used to signal a + * client that the change has completed. For example, on MSP432 the + * "PowerMSP432_DONE_CHANGE_PERF_LEVEL" event can be used to signal + * completion. + * + * This function will not return until the new performance level is in effect. + * If performance scaling is not supported for the device, or is prohibited + * by an active constraint, or if the specified level is invalid, then an + * error status will be returned. + * + * @param level the new performance level + * + * @return Power_SOK on success. + * Power_EINVALIDINPUT if the specified performance level is out of + * range of valid levels. + * Power_EBUSY if another transition is already in progress, or if + * a single constraint is set to prohibit any change to the + * performance level. + * Power_ECHANGE_NOT_ALLOWED if a level-specific constraint prohibits + * a change to the requested level. + * Power_EFAIL if performance scaling is not supported, if an + * error occurred during initialization, or if an error occurred + * during client notifications. + * + * @sa Power_getPerformanceLevel + */ +int_fast16_t Power_setPerformanceLevel(uint_fast16_t level); + +/*! + * @brief Set a new Power policy + * + * This function allows a new Power policy function to be selected at runtime. + * + * @param policy the new Power policy function + */ +void Power_setPolicy(Power_PolicyFxn policy); + +/*! + * @brief Put the device into a shutdown state + * + * This function will transition the device into a shutdown state. + * Before the actual transition is initiated, notifications will be sent to + * any clients who've registered (with Power_registerNotify()) for an + * 'entering shutdown' event. The event name is device specific, and defined + * in the device-specific Power include file. For example, for CC32XX, the + * event is "PowerCC32XX_ENTERING_SHUTDOWN", which is defined in + * PowerCC32XX.h. Once notifications have been completed, the device shutdown + * will commence. + * + * If the device is successfully transitioned to shutdown, this function + * call will never return. Upon wakeup, the device and application will + * be rebooted (through a device reset). If the transition is not + * successful, one of the error codes listed below will be returned. + * + * On some devices a timed wakeup from shutdown can be specified, using + * the shutdownTime parameter. This enables an autonomous application reboot + * at a future time. For example, an application can go to shutdown, and then + * automatically reboot at a future time to do some work. And once that work + * is done, the application can shutdown again, for another timed interval. + * The time interval is specified via the shutdownTime parameter. (On devices + * that do not support this feature, any value specified for shutdownTime will + * be ignored.) If the specified shutdownTime is less than the total + * shutdown latency for the device, then shutdownTime will be ignored. The + * shutdown latency for the device can be found in the device-specific Power + * include file. For example, for the CC32XX, this latency is defined in + * PowerCC32XX.h, as "PowerCC32XX_TOTALTIMESHUTDOWN".) + * + * @param shutdownState the device-specific shutdown state + * + * @param shutdownTime the amount of time (in milliseconds) to keep the + * the device in the shutdown state; this parameter + * is not supported on all device families + * + * @return Power_ECHANGE_NOT_ALLOWED if a constraint is prohibiting shutdown. + * Power_EFAIL if an error occurred during client notifications. + * Power_EINVALIDINPUT if the shutdownState is invalid. + * Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, + uint_fast32_t shutdownTime); + +/*! + * @brief Transition the device into a sleep state + * + * This function is called from the power policy when it has made a decision + * to put the device in a specific sleep state. This function returns to the + * caller (the policy function) once the device has awoken from sleep. + * + * This function must be called with interrupts disabled, and should not be + * called directly by the application, or by any drivers. + * This function does not check declared constraints; the policy function + * must check constraints before calling this function to initiate sleep. + * + * @param sleepState the sleep state + * + * @return Power_SOK on success, the device has slept and is awake again. + * Power_EFAIL if an error occurred during client notifications. + * Power_EINVALIDINPUT if the sleepState is invalid. + * Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState); + +/*! + * @brief Unregister previously registered notifications + * + * This function unregisters for event notifications that were previously + * registered with Power_registerNotify(). The caller must specify a pointer + * to the same notification object used during registration. + * + * @param pNotifyObj notify object + * + * @sa Power_registerNotify + */ +void Power_unregisterNotify(Power_NotifyObj *pNotifyObj); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Power__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SD.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SD.h new file mode 100644 index 000000000..5b5d14e40 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SD.h @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** ============================================================================ + * @file SD.h + * + * @brief SD driver interface + * + * The SD header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * + * The SD driver is designed to serve as an interface to perform basic + * transfers directly to the SD card. + * + * ## Opening the driver # + * + * @code + * SD_Handle handle; + * + * handle = SD_open(index, NULL); + * if (handle == NULL) { + * System_printf("Error opening SD driver\n"); + * } + * @endcode + * + * # Implementation # + * + * This module serves as the main interface for TI-RTOS applications. Its + * purpose is to redirect the module's APIs to specific peripheral + * implementations which are specified using a pointer to a + * SD_FxnTable. + * + * The SD driver interface module is joined (at link time) to a + * NULL-terminated array of SD_Config data structures named *SD_config*. + * *SD_config* is implemented in the application with each entry being an + * instance of a SD peripheral. Each entry in *SD_config* contains a: + * - (SD_FxnTable *) to a set of functions that implement a SD peripheral + * - (uintptr_t) data object that is associated with the SD_FxnTable + * - (uintptr_t) hardware attributes that are associated to the SD_FxnTable + * + * # Instrumentation # + * + * The SD driver interface produces log statements if + * instrumentation is enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic operations performed | + * Diags_USER2 | detailed operations performed | + * + * ============================================================================ + */ + +#ifndef ti_drivers_SD__include +#define ti_drivers_SD__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @defgroup SD_CONTROL SD_control command and status codes + * @{ + */ + +/*! + * Common SD_control command code reservation offset. + * SD driver implementations should offset command codes with + * SD_CMD_RESERVED growing positively. + * + * Example implementation specific command codes: + * @code + * #define SDXYZ_CMD_COMMAND0 (SD_CMD_RESERVED + 0) + * #define SDXYZ_CMD_COMMAND1 (SD_CMD_RESERVED + 1) + * @endcode + */ +#define SD_CMD_RESERVED (32) + +/*! + * Common SD_control status code reservation offset. + * SD driver implementations should offset status codes with + * SD_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SDXYZ_STATUS_ERROR0 (SD_STATUS_RESERVED - 0) + * #define SDXYZ_STATUS_ERROR1 (SD_STATUS_RESERVED - 1) + * #define SDXYZ_STATUS_ERROR2 (SD_STATUS_RESERVED - 2) + * @endcode + */ +#define SD_STATUS_RESERVED (-32) + +/** + * @defgroup SD_STATUS Status Codes + * SD_STATUS_* macros are general status codes returned by SD_control() + * @{ + * @ingroup SD_CONTROL + */ + +/*! + * @brief Successful status code returned by SD_control(). + * + * SD_control() returns SD_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define SD_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by SD_control(). + * + * SD_control() returns SD_STATUS_ERROR if the control code + * was not executed successfully. + */ +#define SD_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by SD_control() for + * undefined command codes. + * + * SD_control() returns SD_STATUS_UNDEFINEDCMD if the + * control code is not recognized by the driver implementation. + */ +#define SD_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup SD_CMD Command Codes + * SD_CMD_* macros are general command codes for SD_control(). Not all SD + * driver implementations support these command codes. + * @{ + * @ingroup SD_CONTROL + */ + +/* Add SD_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief SD Card type inserted + */ +typedef enum SD_CardType_ { + SD_NOCARD = 0, /*!< Unrecognized Card */ + SD_MMC = 1, /*!< Multi-media Memory Card (MMC) */ + SD_SDSC = 2, /*!< Standard SDCard (SDSC) */ + SD_SDHC = 3 /*!< High Capacity SDCard (SDHC) */ +} SD_CardType; + +/*! + * @brief A handle that is returned from a SD_open() call. + */ +typedef struct SD_Config_ *SD_Handle; + +/*! + * @brief SD Parameters + * + * SD Parameters are used to with the SD_open() call. + * Default values for these parameters are set using SD_Params_init(). + * + * @sa SD_Params_init() + */ + +/* SD Parameters */ +typedef struct SD_Params_ { + void *custom; /*!< Custom argument used by driver implementation */ +} SD_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_CloseFxn(). + */ +typedef void (*SD_CloseFxn) (SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_controlFxn(). + */ +typedef int_fast16_t (*SD_ControlFxn) (SD_Handle handle, + uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_getNumSectorsFxn(). + */ +typedef uint_fast32_t (*SD_getNumSectorsFxn) (SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_getSectorSizeFxn(). + */ +typedef uint_fast32_t (*SD_getSectorSizeFxn) (void); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_InitFxn(). + */ +typedef void (*SD_InitFxn) (SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_initializeFxn(). + */ +typedef int_fast16_t (*SD_InitializeFxn) (SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_OpenFxn(). + */ +typedef SD_Handle (*SD_OpenFxn) (SD_Handle handle, SD_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_readFxn(). + */ +typedef int_fast16_t (*SD_ReadFxn) (SD_Handle handle, void *buf, + int_fast32_t sector, uint_fast32_t secCount); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_writeFxn(). + */ +typedef int_fast16_t (*SD_WriteFxn) (SD_Handle handle, const void *buf, + int_fast32_t sector, uint_fast32_t secCount); + +/*! + * @brief The definition of a SD function table that contains the + * required set of functions to control a specific SD driver + * implementation. + */ +typedef struct SD_FxnTable_ { + /*! Function to close the specified peripheral */ + SD_CloseFxn closeFxn; + /*! Function to implementation specific control function */ + SD_ControlFxn controlFxn; + /*! Function to return the total number of sectors on the SD card */ + SD_getNumSectorsFxn getNumSectorsFxn; + /*! Function to return the sector size used to address the SD card */ + SD_getSectorSizeFxn getSectorSizeFxn; + /*! Function to initialize the given data object */ + SD_InitFxn initFxn; + /*! Function to initialize the SD card */ + SD_InitializeFxn initializeFxn; + /*! Function to open the specified peripheral */ + SD_OpenFxn openFxn; + /*! Function to read from the SD card */ + SD_ReadFxn readFxn; + /*! Function to write to the SD card */ + SD_WriteFxn writeFxn; +} SD_FxnTable; + +/*! + * @brief SD Global configuration + * + * The SD_Config structure contains a set of pointers used + * to characterize the SD driver implementation. + * + * This structure needs to be defined before calling SD_init() and it must + * not be changed thereafter. + * + * @sa SD_init() + */ +typedef struct SD_Config_ { + /*! Pointer to a table of driver-specific implementations of SD APIs */ + SD_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SD_Config; + +/*! + * @brief Function to close a SD peripheral specified by the SD handle. + * + * @pre SD_open() had to be called first. + * + * @param handle A SD handle returned from SD_open + * + * @sa SD_open() + */ +extern void SD_close(SD_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * SD_Handle. + * + * Commands for SD_control can originate from SD.h or from implementation + * specific SD*.h (SDHostCC32XX.h etc.. ) files. + * While commands from SD.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific SD*.h files add + * unique driver capabilities but are not API portable across all SD driver + * implementations. + * + * Commands supported by SD.h follow a SD*_CMD naming + * convention. + * + * Commands supported by SD*.h follow a SD*_CMD naming + * convention. + * Each control command defines arg differently. The types of arg are + * documented with each command. + * + * See @ref SD_CMD "SD_control command codes" for command codes. + * + * See @ref SD_STATUS "SD_control return status codes" for status codes. + * + * @pre SD_open() has to be called first. + * + * @param handle A SD handle returned from SD_open(). + * + * @param cmd SD.h or SD*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd. + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa SD_open() + */ +extern int_fast16_t SD_control(SD_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_getNumSectors(). + * Note: Total Card capacity is the (NumberOfSectors * SectorSize). + * + * @pre SD Card has been initialized using SD_initialize(). + * + * @param handle A SD handle returned from SD_open(). + * + * @return The total number of sectors on the SD card, + * or 0 if an error occurred. + * + * @sa SD_initialize() + */ +extern uint_fast32_t SD_getNumSectors(SD_Handle handle); + +/*! + * @brief Function to obtain the sector size used to access the SD card. + * + * @pre SD Card has been initialized using SD_initialize(). + * + * @param handle A SD handle returned from SD_open(). + * + * @return The sector size set for use during SD card read/write operations. + * + * @sa SD_initialize() + */ +extern uint_fast32_t SD_getSectorSize(SD_Handle handle); + +/*! + * @brief This function initializes the SD driver. + * + * @pre The SD_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other SD driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void SD_init(void); + +/*! + * @brief Function to initialize the SD_Params struct to its defaults. + * + * @param params A pointer to SD_Params structure for initialization. + */ +extern void SD_Params_init(SD_Params *params); + + /*! + * @brief A function pointer to a driver specific implementation of + * SD_initialize(). + * + * @pre SD controller has been opened by calling SD_open(). + * + * @param handle A SD handle returned from SD_open(). + * + * @return SD_STATUS_SUCCESS if no errors occurred during the initialization, + * SD_STATUS_ERROR otherwise. + */ +extern int_fast16_t SD_initialize(SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_open(). + * + * @pre SD controller has been initialized using SD_init(). + * + * @param index Logical peripheral number for the SD indexed into + * the SD_config table. + * + * @param params Pointer to a parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A SD_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa SD_init() + * @sa SD_close() + */ +extern SD_Handle SD_open(uint_least8_t index, SD_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_read(). + * + * @pre SD controller has been opened and initialized by calling SD_open() + * followed by SD_initialize(). + * + * @param handle A SD handle returned from SD_open(). + * + * @param buf Pointer to a buffer to read data into. + * + * @param sector Starting sector on the disk to read from. + * + * @param secCount Number of sectors to be read. + * + * @return SD_STATUS_SUCCESS if no errors occurred during the write, + * SD_STATUS_ERROR otherwise. + * + * @sa SD_initialize() + */ +extern int_fast16_t SD_read(SD_Handle handle, void *buf, + int_fast32_t sector, uint_fast32_t secCount); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_write(). + * + * @pre SD controller has been opened and initialized by calling SD_open() + * followed by SD_initialize(). + * + * @param handle A SD handle returned from SD_open(). + * + * @param buf Pointer to a buffer containing data to write to disk. + * + * @param sector Starting sector on the disk to write to. + * + * @param secCount Number of sectors to be written. + * + * @return SD_STATUS_SUCCESS if no errors occurred during the write, + * SD_STATUS_ERROR otherwise. + * + * @sa SD_initialize() + */ +extern int_fast16_t SD_write(SD_Handle handle, const void *buf, + int_fast32_t sector, uint_fast32_t secCount); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SD__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SDFatFS.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SDFatFS.h new file mode 100644 index 000000000..85ed53e50 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SDFatFS.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SDFatFS.h + * + * @brief FATFS driver interface + * + * The SDFatFS header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * # Operation # + * + * The SDFatFS driver is designed to hook into FatFs by implementing a + * set of functions that FatFs needs to call to perform basic block data + * transfers. This driver makes use of the SD driver for lower level disk IO + * operations. + * + * The only functions that should be called by the application are the + * standard driver framework functions (_open, _close, etc...). + * + * The application may use the FatFs APIs or the standard C + * runtime file I/O calls (fopen, fclose, etc...) given that SDFatFS_open has + * has been successfully called. After the SDFatFS_close API is called, + * ensure the application does NOT make any file I/O calls. + * + * ## Opening the driver # + * + * @code + * SDFatFS_Handle handle; + * + * handle = SDFatFS_open(index, driveNum, NULL); + * if (!handle) { + * System_printf("Error opening SDFatFS driver\n"); + * } + * @endcode + * + * # Implementation # + * + * The SDFatFS driver interface module is joined (at link time) to a NULL + * terminated array of SDFatFS_Config data structures named *SDFatFS_config*. + * *SDFatFS_config* is implemented in the application with each entry being an + * instance of the driver. Each entry in *SDFatFS_config* contains a: + * - (void *) data object that contains internal driver data structures + * + * # Instrumentation # + * + * The SDFatFS driver interface produces log statements if + * instrumentation is enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic operations performed | + * Diags_USER2 | detailed operations performed | + * ============================================================================ + */ + +#ifndef ti_drivers_SDFatFS__include +#define ti_drivers_SDFatFS__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include + +/*! + * @brief SDFatFS Object + * The application must not access any member variables of this structure! + */ +typedef struct SDFatFS_Object_ { + uint_fast32_t driveNum; + DSTATUS diskState; + FATFS filesystem; /* FATFS data object */ + SD_Handle sdHandle; +} SDFatFS_Object; + +/*! + * @brief A handle that is returned from a SDFatFS_open() call. + */ +typedef struct SDFatFS_Config_ *SDFatFS_Handle; + + +/*! + * @brief SDFatFS Global configuration + * + * The SDFatFS_Config structure contains a single pointer used to characterize + * the SDFatFS driver implementation. + * + * This structure needs to be defined before calling SDFatFS_init() and it must + * not be changed thereafter. + * + * @sa SDFatFS_init() + */ +typedef struct SDFatFS_Config_ { + /*! Pointer to a SDFatFS object */ + void *object; +} SDFatFS_Config; + +/*! + * @brief Function to open a SDFatFS instance on the specified drive. + * + * Function to mount the FatFs filesystem and register the SDFatFS disk + * I/O functions with the FatFS module. + * + * @param idx Logical peripheral number indexed into the HWAttrs + * table. + * @param drive Drive Number + */ +extern SDFatFS_Handle SDFatFS_open(uint_least8_t idx, uint_least8_t drive); + +/*! + * @brief Function to close a SDFatFS instance specified by the SDFatFS + * handle. + * + * This function unmounts the file system mounted by SDFatFS_open and + * unregisters the SDFatFS driver from the FatFs module. + * + * @pre SDFatFS_open() had to be called first. + * + * @param handle A SDFatFS handle returned from SDFatFS_open + * + * @sa SDFatFS_open() + */ +extern void SDFatFS_close(SDFatFS_Handle handle); + +/*! + * Function to initialize a SDFatFS instance + */ +extern void SDFatFS_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SDFatFS__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SDSPI.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SDSPI.h new file mode 100644 index 000000000..76ddf7c87 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SDSPI.h @@ -0,0 +1,455 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file SDSPI.h + * + * @brief SDSPI driver interface + * + * The SDSPI header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The SDSPI FatFs driver is used to communicate with SD (Secure Digital) + * cards via SPI (Serial Peripheral Interface). + * + * The SDSPI driver is a FatFs driver module for the FatFs middleware + * module. With the exception of the standard driver APIs - + * SDSPI_open(), SDSPI_close(), and SDSPI_init() - the SDSPI driver + * is exclusively used by FatFs module to handle the low-level hardware + * communications. + * + * The SDSPI driver only supports one SSI (SPI) peripheral at a given time. + * It does not utilize interrupts. + * + * The SDSPI driver is polling based for performance reasons and due to the + * relatively high SPI bus bit rate. This means it does not utilize the + * SPI's peripheral interrupts, and it consumes the entire CPU time when + * communicating with the SPI bus. Data transfers to or from the SD card + * are typically 512 bytes, which could take a significant amount of time + * to complete. During this time, only higher priority Tasks, Swis, and + * Hwis can preempt Tasks making calls that use the FatFs. + * + * # Usage # + * Before any FatFs or C I/O APIs can be used, the application needs to + * open the SDSPI driver. The SDSPI_open() function ensures that the SDSPI + * disk functions get registered with the FatFs module that subsequently + * mounts the FatFs volume to that particular drive. + * + * @code + * SDSPI_Handle sdspiHandle; + * SDSPI_Params sdspiParams; + * UInt peripheralNum = 0; + * UInt FatFsDriveNum = 0; + * + * SDSPI_Params_init(&sdspiParams); + * + * sdspiHandle = SDSPI_open(peripheralNum, FatFsDriveNum, &sdspiParams); + * if (sdspiHandle == NULL) { + * System_abort("Error opening SDSPI\n"); + * } + * @endcode + * + * Similarly, the SDSPI_close() function unmounts the FatFs volume and + * unregisters SDSPI disk functions. + * + * @code + * SDSPI_close(sdspiHandle); + * @endcode + * + * Note that it is up to the application to ensure the no FatFs or C I/O + * APIs are called before the SDSPI driver has been opened or after the + * SDSPI driver has been closed. + * + * ### SDSPI Driver Configuration # + * The SDSPI driver requires the application to initialize board-specific + * portions of the SDSPI and provide the SDSPI driver with the SDSPI_config + * structure. + * + * #### Board-Specific Configuration # + * + * The SDSPI_init() initializes the SDSPI driver snd any board-specific + * SDSPI peripheral settings. + * + * #### SDSPI_config Structure # + * + * The \<*board*\>.c file declares the SDSPI_config structure. This + * structure must be provided to the SDSPI driver. It must be initialized + * before the SDSPI_init() function is called and cannot be changed + * afterwards. + * + * The SDSPI driver interface defines a configuration data structure: + * + * @code + * typedef struct SDSPI_Config_ { + * SDSPI_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } SDSPI_Config; + * @endcode + * + * # Operation # + * + * The SDSPI driver is a driver designed to hook into FatFs. It implements a + * set of functions that FatFs needs to call to perform basic block data + * transfers. + * + * A SDSPI driver peripheral implementation doesn't require RTOS protection + * primitives due to the resource protection provided with FatFs. The only + * functions that can be called by the application are the standard driver + * framework functions (_open, _close, etc...). + * + * Once the driver has been opened, the application may used the FatFs APIs or + * the standard C runtime file I/O calls (fopen, fclose, etc...). Once the + * driver has been closed, ensure the application does NOT make any file I/O + * calls. + * + * ### Opening the SDSPI driver # + * + * @code + * SDSPI_Handle handle; + * SDSPI_Params params; + * + * SDSPI_Params_init(¶ms); + * params.bitRate = someNewBitRate; + * handle = SDSPI_open(someSDSPI_configIndexValue, ¶ms); + * if (!handle) { + * System_printf("SDSPI did not open"); + * } + * @endcode + * + * # Implementation # + * + * The SDSPI driver interface module is joined (at link time) to an + * array of SDSPI_Config data structures named *SDSPI_config*. + * SDSPI_config is implemented in the application with each entry being an + * instance of a SDSPI peripheral. Each entry in *SDSPI_config* contains a: + * - (SDSPI_FxnTable *) to a set of functions that implement a SDSPI peripheral + * - (void *) data object that is associated with the SDSPI_FxnTable + * - (void *) hardware attributes that are associated with the SDSPI_FxnTable + * + * The SDSPI APIs are redirected to the device specific implementations + * using the SDSPI_FxnTable pointer of the SDSPI_config entry. + * In order to use device specific functions of the SDSPI driver directly, + * link in the correct driver library for your device and include the + * device specific SDSPI driver header file (which in turn includes SDSPI.h). + * For example, for the MSP432 family of devices, you would include the + * following header file: + * @code + * #include + * @endcode + * + ******************************************************************************* + */ + +#ifndef ti_drivers_SDSPI__include +#define ti_drivers_SDSPI__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @defgroup SDSPI_CONTROL SDSPI_control command and status codes + * These SDSPI macros are reservations for SDSPI.h + * @{ + */ + +/*! + * Common SDSPI_control command code reservation offset. + * SDSPI driver implementations should offset command codes with + * SDSPI_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define SDSPIXYZ_CMD_COMMAND0 SDSPI_CMD_RESERVED + 0 + * #define SDSPIXYZ_CMD_COMMAND1 SDSPI_CMD_RESERVED + 1 + * @endcode + */ +#define SDSPI_CMD_RESERVED (32) + +/*! + * Common SDSPI_control status code reservation offset. + * SDSPI driver implementations should offset status codes with + * SDSPI_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SDSPIXYZ_STATUS_ERROR0 SDSPI_STATUS_RESERVED - 0 + * #define SDSPIXYZ_STATUS_ERROR1 SDSPI_STATUS_RESERVED - 1 + * #define SDSPIXYZ_STATUS_ERROR2 SDSPI_STATUS_RESERVED - 2 + * @endcode + */ +#define SDSPI_STATUS_RESERVED (-32) + +/** + * @defgroup SDSPI_STATUS Status Codes + * SDSPI_STATUS_* macros are general status codes returned by SDSPI_control() + * @{ + * @ingroup SDSPI_CONTROL + */ + +/*! + * @brief Successful status code returned by SDSPI_control(). + * + * SDSPI_control() returns SDSPI_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define SDSPI_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by SDSPI_control(). + * + * SDSPI_control() returns SDSPI_STATUS_ERROR if the control code was not + * executed successfully. + */ +#define SDSPI_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by SDSPI_control() for undefined + * command codes. + * + * SDSPI_control() returns SDSPI_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define SDSPI_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup SDSPI_CMD Command Codes + * SDSPI_CMD_* macros are general command codes for SDSPI_control(). Not all SDSPI + * driver implementations support these command codes. + * @{ + * @ingroup SDSPI_CONTROL + */ + +/* Add SDSPI_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief A handle that is returned from a SDSPI_open() call. + */ +typedef struct SDSPI_Config_ *SDSPI_Handle; + + +/*! + * @brief SDSPI Parameters + * + * SDSPI Parameters are used to with the SDSPI_open() call. Default values for + * these parameters are set using SDSPI_Params_init(). + * + * @sa SDSPI_Params_init() + */ +typedef struct SDSPI_Params_ { + uint32_t bitRate; /*!< SPI bit rate in Hz */ + void *custom; /*!< Custom argument used by driver implementation */ +} SDSPI_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * SDSPI_init(). + */ +typedef void (*SDSPI_InitFxn) (SDSPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SDSPI_open(). + */ +typedef SDSPI_Handle (*SDSPI_OpenFxn) (SDSPI_Handle handle, + uint_least8_t drv, + SDSPI_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SDSPI_close(). + */ +typedef void (*SDSPI_CloseFxn) (SDSPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SDSPI_control(). + */ +typedef int_fast16_t (*SDSPI_ControlFxn) (SDSPI_Handle handle, + uint_fast16_t cmd, + void *arg); + +/*! + * @brief The definition of a SDSPI function table that contains the + * required set of functions to control a specific SDSPI driver + * implementation. + */ +typedef struct SDSPI_FxnTable_ { + /*! Function to initialized the given data object */ + SDSPI_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + SDSPI_OpenFxn openFxn; + + /*! Function to close the specified peripheral */ + SDSPI_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + SDSPI_ControlFxn controlFxn; +} SDSPI_FxnTable; + +/*! + * @brief SDSPI Global configuration + * + * The SDSPI_Config structure contains a set of pointers used to characterize + * the SDSPI driver implementation. + * + * This structure needs to be defined before calling SDSPI_init() and it must + * not be changed thereafter. + * + * @sa SDSPI_init() + */ +typedef struct SDSPI_Config_ { + /*! Pointer to a table of driver-specific implementations of SDSPI APIs */ + SDSPI_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SDSPI_Config; + +/*! + * @brief Function to close a SDSPI peripheral specified by the SDSPI handle. + * This function unmounts the file system mounted by SDSPI_open and + * unregisters the SDSPI driver from BIOS' FatFs module. + * + * @pre SDSPI_open() had to be called first. + * + * @param handle A SDSPI handle returned from SDSPI_open + * + * @sa SDSPI_open() + */ +extern void SDSPI_close(SDSPI_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * SDSPI_Handle. + * + * Commands for SDSPI_control can originate from SDSPI.h or from implementation + * specific SDSPI*.h (_SDSPICC26XX.h_, _SDSPIMSP432.h_, etc.. ) files. + * While commands from SDSPI.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific SDSPI*.h files add + * unique driver capabilities but are not API portable across all SDSPI driver + * implementations. + * + * Commands supported by SDSPI.h follow a SDSPI_CMD_\ naming + * convention.
+ * Commands supported by SDSPI*.h follow a SDSPI*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref SDSPI_CMD "SDSPI_control command codes" for command codes. + * + * See @ref SDSPI_STATUS "SDSPI_control return status codes" for status codes. + * + * @pre SDSPI_open() has to be called first. + * + * @param handle A SDSPI handle returned from SDSPI_open() + * + * @param cmd SDSPI.h or SDSPI*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa SDSPI_open() + */ +extern int_fast16_t SDSPI_control(SDSPI_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief This function initializes the SDSPI driver module. + * + * @pre The SDSPI_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other SDSPI driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void SDSPI_init(void); + +/*! + * @brief This function registers the SDSPI driver with BIOS' FatFs module + * and mounts the FatFs file system. + * + * @pre SDSPI controller has been initialized using SDSPI_init() + * + * @param index Logical peripheral number for the SDSPI indexed into + * the SDSPI_config table + * + * @param drv Drive number to be associated with the SDSPI FatFs + * driver + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A SDSPI_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa SDSPI_init() + * @sa SDSPI_close() + */ +extern SDSPI_Handle SDSPI_open(uint_least8_t index, uint_least8_t drv, + SDSPI_Params *params); + +/*! + * @brief Function to initialize the SDSPI_Params struct to its defaults + * + * @param params An pointer to SDSPI_Params structure for + * initialization + * + * Defaults values are: + * bitRate = 12500000 (Hz) + */ +extern void SDSPI_Params_init(SDSPI_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SDSPI__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SPI.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SPI.h new file mode 100644 index 000000000..9a2bef4ff --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/SPI.h @@ -0,0 +1,846 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file SPI.h + * + * @brief SPI driver interface + * + * The SPI driver interface provides device independent APIs, data types, + * and macros. The SPI header file should be included in an application as + * follows: + * @code + * #include + * @endcode + * + * # Overview # + * The Serial Peripheral Interface (SPI) driver is a generic, full-duplex + * driver that transmits and receives data on a SPI bus. SPI is sometimes + * called SSI (Synchronous Serial Interface). + * The SPI protocol defines the format of a data transfer over the SPI bus, + * but it leaves flow control, data formatting, and handshaking mechanisms + * to higher-level software layers. + * + * The APIs in this driver serve as an interface to a typical RTOS + * application. Its purpose is to redirect the SPI APIs to specific + * driver implementations which are specified using a pointer to a + * #SPI_FxnTable. The specific SPI implementations are responsible for + * creating all the RTOS specific primitives to allow for thread-safe + * operation. + * + * The SPI driver operates on some key definitions and assumptions: + * - The driver operates transparently from the chip select. Some SPI + * controllers feature a hardware chip select to assert SPI slave + * peripherals. See the specific peripheral implementations on chip + * select requirements. + * + * - The SPI protocol does not account for a built-in handshaking mechanism + * and neither does this SPI driver. Therefore, when operating in + * ::SPI_SLAVE mode, the application must provide such a mechanism to + * ensure that the SPI slave is ready for the SPI master. The SPI slave + * must call SPI_transfer() *before* the SPI master starts transmitting. + * Some example application mechanisms could include: + * - Timed delays on the SPI master to guarantee the SPI slave is ready + * for a SPI transaction. + * - A form of GPIO flow control from the slave to the SPI master to notify + * the master when ready. + * + * # Usage # + * + * To use the SPI driver to send data over the SPI bus, the application + * calls the following APIs: + * - SPI_init(): Initialize the SPI driver. + * - SPI_Params_init(): Initialize a #SPI_Params structure with default + * vaules. Then change the parameters from non-default values as + * needed. + * - SPI_open(): Open an instance of the SPI driver, passing the + * initialized parameters, or NULL, and an index (described later). + * - SPI_transfer(): Transmit/receive data. This function takes a + * #SPI_Transaction argument that specifies buffers for data to be + * transmitted/received. + * - SPI_close(): De-initialize the SPI instance. + * + * The following code example opens a SPI instance as a master SPI, + * and issues a transaction. + * + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * SPI_Transaction spiTransaction; + * uint8_t transmitBuffer[MSGSIZE]; + * uint8_t receiveBuffer[MSGSIZE]; + * bool transferOK; + * + * SPI_init(); // Initialize the SPI driver + * + * SPI_Params_init(&spiParams); // Initialize SPI parameters + * spiParams.dataSize = 8; // 8-bit data size + * + * spi = SPI_open(Board_SPI0, &spiParams); + * if (spi == NULL) { + * while (1); // SPI_open() failed + * } + * + * // Fill in transmitBuffer + * + * spiTransaction.count = MSGSIZE; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * } + * @endcode + * + * More details on usage are provided in the following subsections. + * + * ### SPI Driver Configuration # + * + * In order to use the SPI APIs, the application is required + * to provide device-specific SPI configuration in the Board.c file. + * The SPI driver interface defines a configuration data structure: + * + * @code + * typedef struct SPI_Config_ { + * SPI_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } SPI_Config; + * @endcode + * + * The application must declare an array of SPI_Config elements, named + * SPI_config[]. Each element of SPI_config[] must be populated with + * pointers to a device specific SPI driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the SPI peripheral's base address, and + * the MOSI and MISO pins. Each element in SPI_config[] corresponds to + * a SPI instance, and none of the elements should have NULL pointers. + * There is no correlation between the index and the + * peripheral designation (such as SPI0 or SPI1). For example, it is + * possible to use SPI_config[0] for SPI1. + * + * Because the SPI configuration is very device dependent, you will need to + * check the doxygen for the device specific SPI implementation. There you + * will find a description of the SPI hardware attributes. Please also + * refer to the Board.c file of any of your examples to see the SPI + * configuration. + * + * ### Initializing the SPI Driver # + * + * SPI_init() must be called before any other SPI APIs. This function + * iterates through the elements of the SPI_config[] array, calling + * the element's device implementation SPI initialization function. + * + * ### SPI Parameters + * + * The #SPI_Params structure is passed to the SPI_open() call. If NULL + * is passed for the parameters, SPI_open() uses default parameters. + * A #SPI_Params structure is initialized with default values by passing + * it to SPI_Params_init(). + * Some of the SPI parameters are described below. To see brief descriptions + * of all the parameters, see #SPI_Params. + * + * #### SPI Mode + * The SPI driver operates in both SPI master and SPI slave modes. + * Logically, the implementation is identical, however the difference + * between these two modes is driven by hardware. The default mode is + * ::SPI_MASTER, but can be set to slave mode by setting ::SPI_Params.mode + * to ::SPI_SLAVE in the parameters passed to SPI_open(). See + * Master/Slave Modes for further + * details. + * + * #### SPI Transfer Mode + * The SPI driver supports two transfer modes of operation: blocking and + * callback. The transfer mode is determined by the transferMode parameter + * in the SPI_Params data structure. The SPI driver + * defaults to blocking mode, if the application does not set it. + * Once a SPI driver is opened, the only way to change the operation mode + * is to close and re-open the SPI instance with the new transfer mode. + * + * In blocking mode, a task's code execution is blocked until a SPI + * transaction has completed. This ensures that only one SPI transaction + * operates at a given time. Other tasks requesting SPI transactions while + * a transaction is currently taking place are also placed into a blocked + * state. SPI transactions are executed in the order in which they were + * received. In blocking mode, you cannot perform SPI transactions + * in the context of a software or hardware ISR. + * + * In callback mode, a SPI transaction functions asynchronously, which + * means that it does not block code execution. After a SPI transaction + * has been completed, the SPI driver calls a user-provided hook function. + * Callback mode is supported in the execution context of tasks and + * hardware interrupt routines. However, if a SPI transaction is + * requested while a transaction is taking place, SPI_transfer() returns + * FALSE. + * + * + * #### SPI Frame Formats and Data Size + * The SPI driver can configure the device's SPI peripheral with various + * SPI format options: SPI (with various polarity and phase settings), + * TI, and Micro-wire. The frame format is set with SPI_Params.frameFormat. + * The smallest single unit of data transmitted onto the SPI bus is called + * a SPI frame and is of size SPI_Params.dataSize. A series of SPI frames + * transmitted/received on a SPI bus is known as a SPI transaction. + * + * ### Opening the SPI Driver # + * After initializing the SPI driver by calling SPI_init(), the application + * can open a SPI instance by calling SPI_open(). This function + * takes an index into the SPI_config[] array, and a SPI parameters data + * structure. The SPI instance is specified by the index of the SPI in + * SPI_config[]. Only one SPI index can be used at a time; + * calling SPI_open() a second time with the same index previosly + * passed to SPI_open() will result in an error. You can, + * though, re-use the index if the instance is closed via SPI_close(). + * + * If no SPI_Params structure is passed to SPI_open(), default values are + * used. If the open call is successful, it returns a non-NULL value. + * + * Example opening a SPI driver instance in blocking mode: + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * + * SPI_Params_init(&spiParams); + * spiParams.transferMode = SPI_MODE_BLOCKING; + * spi = SPI_open(Board_SPI0, &spiParams); + * + * if (spi == NULL) { + * // Error opening SPI + * } + * @endcode + * + * Example opening a SPI driver instance in callback mode: + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * + * SPI_Params_init(&spiParams); + * spiParams.transferMode = SPI_MODE_CALLBACK; + * spiParams.transferCallbackFxn = UserCallbackFxn; + * + * spi = SPI_open(Board_SPI0, &spiParams); + * if (spi == NULL) { + * // Error opening SPI + * } + * @endcode + * + * + * ### SPI Transactions # + * + * A SPI transaction consists of a series of SPI frames + * transmitted/received on a SPI bus. A SPI transaction is performed + * using SPI_transfer(). SPI_transfer() accepts a pointer to a + * #SPI_Transaction structure that dictates the quantity of data to be + * sent and received. + * The SPI_Transaction.txBuf and SPI_Transaction.rxBuf are both pointers + * to data buffers. If txBuf is NULL, the driver sends SPI frames with all + * data bits set to 0. If rxBuf is NULL, the driver discards all SPI frames + * received. + * A SPI_transfer() of a SPI transaction is performed atomically. + * + * When the SPI is opened, the dataSize value determines the element types + * of txBuf and rxBuf. If the dataSize is from 4 to 8 bits, the driver + * assumes the data buffers are of type uint8_t (unsigned char). If the + * dataSize is larger than 8 bits, the driver assumes the data buffers are + * of type uint16_t (unsigned short). + * The optional SPI_Transaction.arg variable can only be used when the + * SPI driver has been opened in callback mode. This variable is used to + * pass a user-defined value into the user-defined callback function. + * + * SPI_transfer() always performs full-duplex SPI transactions. This means + * the SPI simultaneously receives data as it transmits data. The application + * is responsible for formatting the data to be transmitted as well as + * determining whether the data received is meaningful. + * Specifics about SPI frame formatting and data sizes are provided in + * device-specific data sheets and technical reference manuals. + * + * The following code snippets perform SPI transactions. + * + * Example transferring 6-bit SPI frames. The transmit and receive + * buffers are of type uint8_t. + * @code + * SPI_Transaction spiTransaction; + * uint8_t transmitBuffer[BUFSIZE]; + * uint8_t receiveBuffer[BUFSIZE]; + * bool transferOK; + * + * SPI_Params_init(&spiParams); + * spiParams.dataSize = 6; + * spi = SPI_open(Board_SPI0, &spiParams); + * ... + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * + * ret = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Unsuccessful SPI transfer + * } + * @endcode + * + * Example transferring 12-bit SPI frames. The transmit and receive + * buffers are of type uint16_t. + * @code + * SPI_Transaction spiTransaction; + * uint16_t transmitBuffer[BUFSIZE]; + * uint16_t receiveBuffer[BUFSIZE]; + * bool transferOK; + * + * SPI_Params_init(&spiParams); + * spiParams.dataSize = 12; + * spi = SPI_open(Board_SPI0, &spiParams); + * ... + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * + * ret = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Unsuccessful SPI transfer + * } + * @endcode + * + * ### Canceling a transaction # + * SPI_transferCancel() is used to cancel a SPI transaction when the driver is + * used in ::SPI_MODE_CALLBACK mode. + * + * Calling this API while no transfer is in progress has no effect. If a + * transfer is in progress, it is canceled and the callback functions is + * called. + * The ::SPI_Status status field in the ::SPI_Transaction structure + * can be examined within the callback to determine if the transaction + * succeeded. + * + * Example: + * @code + * SPI_transferCancel(spi); + * @endcode + * + * + *

Master/Slave Modes

+ * This SPI driver functions in both SPI master and SPI slave modes. + * Logically, the implementation is identical, however the difference between + * these two modes is driven by hardware. As a SPI master, the peripheral is + * in control of the clock signal and therefore will commence communications + * to the SPI slave immediately. As a SPI slave, the SPI driver prepares + * the peripheral to transmit and receive data in a way such that the + * peripheral is ready to transfer data when the SPI master initiates a + * transaction. + * + * ### Asserting on Chip Select + * The SPI protocol requires that the SPI master asserts a SPI slave's chip + * select pin prior to starting a SPI transaction. While this protocol is + * generally followed, various types of SPI peripherals have different + * timing requirements as to when and for how long the chip select pin must + * remain asserted for a SPI transaction. + * + * Commonly, the SPI master uses a hardware chip select to assert and + * de-assert the SPI slave for every data frame. In other cases, a SPI slave + * imposes the requirement of asserting the chip select over several SPI + * data frames. This is generally accomplished by using a regular, + * general-purpose output pin. Due to the complexity of such SPI peripheral + * implementations, this SPI driver has been designed to operate + * transparently to the SPI chip select. When the hardware chip + * select is used, the peripheral automatically selects/enables the + * peripheral. When using a software chip select, the application needs to + * handle the proper chip select and pin configuration. + * + * - _Hardware chip select_ No additional action by the application is + * required. + * - _Software chip select_ The application needs to handle the chip select + * assertion and de-assertion for the proper SPI peripheral. + * + * # Implementation # + * + * This module serves as the main interface for RTOS applications. Its + * purpose is to redirect the module's APIs to specific peripheral + * implementations which are specified using a pointer to a #SPI_FxnTable. + * + * The SPI driver interface module is joined (at link time) to an + * array of SPI_Config data structures named *SPI_config*. + * The SPI_config array is implemented in the application with each entry + * being an instance of a SPI peripheral. Each entry in *SPI_config* contains + * the following: + * - (SPI_FxnTable *) A pointer to a set of functions that implement a + * SPI peripheral. + * - (void *) A data object that is associated with the SPI_FxnTable. + * - (void *) The hardware attributes that are associated with the + * SPI_FxnTable. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_SPI__include +#define ti_drivers_SPI__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @defgroup SPI_CONTROL SPI_control command and status codes + * These SPI macros are reservations for SPI.h + * @{ + */ + +/*! + * Common SPI_control command code reservation offset. + * SPI driver implementations should offset command codes with SPI_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define SPIXYZ_CMD_COMMAND0 SPI_CMD_RESERVED + 0 + * #define SPIXYZ_CMD_COMMAND1 SPI_CMD_RESERVED + 1 + * @endcode + */ +#define SPI_CMD_RESERVED (32) + +/*! + * Common SPI_control status code reservation offset. + * SPI driver implementations should offset status codes with + * SPI_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SPIXYZ_STATUS_ERROR0 SPI_STATUS_RESERVED - 0 + * #define SPIXYZ_STATUS_ERROR1 SPI_STATUS_RESERVED - 1 + * #define SPIXYZ_STATUS_ERROR2 SPI_STATUS_RESERVED - 2 + * @endcode + */ +#define SPI_STATUS_RESERVED (-32) + +/** + * @defgroup SPI_STATUS Status Codes + * SPI_STATUS_* macros are general status codes returned by SPI_control() + * @{ + * @ingroup SPI_CONTROL + */ + +/*! + * @brief Successful status code returned by SPI_control(). + * + * SPI_control() returns SPI_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define SPI_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by SPI_control(). + * + * SPI_control() returns SPI_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define SPI_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by SPI_control() for undefined + * command codes. + * + * SPI_control() returns SPI_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define SPI_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup SPI_CMD Command Codes + * SPI_CMD_* macros are general command codes for SPI_control(). Not all SPI + * driver implementations support these command codes. + * @{ + * @ingroup SPI_CONTROL + */ + +/* Add SPI_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief Wait forever define + */ +#define SPI_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from a SPI_open() call. + */ +typedef struct SPI_Config_ *SPI_Handle; + +/*! + * @brief Status codes that are set by the SPI driver. + */ +typedef enum SPI_Status_ { + SPI_TRANSFER_COMPLETED = 0, + SPI_TRANSFER_STARTED, + SPI_TRANSFER_CANCELED, + SPI_TRANSFER_FAILED, + SPI_TRANSFER_CSN_DEASSERT +} SPI_Status; + +/*! + * @brief + * A ::SPI_Transaction data structure is used with SPI_transfer(). It indicates + * how many ::SPI_FrameFormat frames are sent and received from the buffers + * pointed to txBuf and rxBuf. + * The arg variable is an user-definable argument which gets passed to the + * ::SPI_CallbackFxn when the SPI driver is in ::SPI_MODE_CALLBACK. + */ +typedef struct SPI_Transaction_ { + /* User input (write-only) fields */ + size_t count; /*!< Number of frames for this transaction */ + void *txBuf; /*!< void * to a buffer with data to be transmitted */ + void *rxBuf; /*!< void * to a buffer to receive data */ + void *arg; /*!< Argument to be passed to the callback function */ + + /* User output (read-only) fields */ + SPI_Status status; /*!< Status code set by SPI_transfer */ +} SPI_Transaction; + +/*! + * @brief The definition of a callback function used by the SPI driver + * when used in ::SPI_MODE_CALLBACK + * + * @param SPI_Handle SPI_Handle + * @param SPI_Transaction* SPI_Transaction* + */ +typedef void (*SPI_CallbackFxn) (SPI_Handle handle, + SPI_Transaction *transaction); +/*! + * @brief + * Definitions for various SPI modes of operation. + */ +typedef enum SPI_Mode_ { + SPI_MASTER = 0, /*!< SPI in master mode */ + SPI_SLAVE = 1 /*!< SPI in slave mode */ +} SPI_Mode; + +/*! + * @brief + * Definitions for various SPI data frame formats. + */ +typedef enum SPI_FrameFormat_ { + SPI_POL0_PHA0 = 0, /*!< SPI mode Polarity 0 Phase 0 */ + SPI_POL0_PHA1 = 1, /*!< SPI mode Polarity 0 Phase 1 */ + SPI_POL1_PHA0 = 2, /*!< SPI mode Polarity 1 Phase 0 */ + SPI_POL1_PHA1 = 3, /*!< SPI mode Polarity 1 Phase 1 */ + SPI_TI = 4, /*!< TI mode */ + SPI_MW = 5 /*!< Micro-wire mode */ +} SPI_FrameFormat; + +/*! + * @brief + * + * SPI transfer mode determines the whether the SPI controller operates + * synchronously or asynchronously. In ::SPI_MODE_BLOCKING mode SPI_transfer() + * blocks code execution until the SPI transaction has completed. In + * ::SPI_MODE_CALLBACK SPI_transfer() does not block code execution and instead + * calls a ::SPI_CallbackFxn callback function when the transaction has + * completed. + */ +typedef enum SPI_TransferMode_ { + /*! + * SPI_transfer() blocks execution. This mode can only be used when called + * within a Task context + */ + SPI_MODE_BLOCKING, + /*! + * SPI_transfer() does not block code execution and will call a + * ::SPI_CallbackFxn. This mode can be used in a Task, Swi, or Hwi context. + */ + SPI_MODE_CALLBACK +} SPI_TransferMode; + +/*! + * @brief SPI Parameters + * + * SPI Parameters are used to with the SPI_open() call. Default values for + * these parameters are set using SPI_Params_init(). + * + * @sa SPI_Params_init() + */ +typedef struct SPI_Params_ { + SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ + uint32_t transferTimeout; /*!< Transfer timeout in system + ticks (Not supported with all + implementations */ + SPI_CallbackFxn transferCallbackFxn;/*!< Callback function pointer */ + SPI_Mode mode; /*!< Master or Slave mode */ + uint32_t bitRate; /*!< SPI bit rate in Hz */ + uint32_t dataSize; /*!< SPI data frame size in bits */ + SPI_FrameFormat frameFormat; /*!< SPI frame format */ + void *custom; /*!< Custom argument used by driver + implementation */ +} SPI_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_close(). + */ +typedef void (*SPI_CloseFxn) (SPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_control(). + */ +typedef int_fast16_t (*SPI_ControlFxn) (SPI_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_init(). + */ +typedef void (*SPI_InitFxn) (SPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_open(). + */ +typedef SPI_Handle (*SPI_OpenFxn) (SPI_Handle handle, SPI_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_transfer(). + */ +typedef bool (*SPI_TransferFxn) (SPI_Handle handle, + SPI_Transaction *transaction); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_transferCancel(). + */ +typedef void (*SPI_TransferCancelFxn) (SPI_Handle handle); + +/*! + * @brief The definition of a SPI function table that contains the + * required set of functions to control a specific SPI driver + * implementation. + */ +typedef struct SPI_FxnTable_ { + /*! Function to close the specified peripheral */ + SPI_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + SPI_ControlFxn controlFxn; + + /*! Function to initialize the given data object */ + SPI_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + SPI_OpenFxn openFxn; + + /*! Function to initiate a SPI data transfer */ + SPI_TransferFxn transferFxn; + + /*! Function to cancel SPI data transfer */ + SPI_TransferCancelFxn transferCancelFxn; +} SPI_FxnTable; + +/*! + * @brief SPI Global configuration + * + * The SPI_Config structure contains a set of pointers used to characterize + * the SPI driver implementation. + * + * This structure needs to be defined before calling SPI_init() and it must + * not be changed thereafter. + * + * @sa SPI_init() + */ +typedef struct SPI_Config_ { + /*! Pointer to a table of driver-specific implementations of SPI APIs */ + SPI_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SPI_Config; + +/*! + * @brief Function to close a SPI peripheral specified by the SPI handle + * + * @pre SPI_open() has to be called first. + * + * @param handle A SPI handle returned from SPI_open() + * + * @sa SPI_open() + */ +extern void SPI_close(SPI_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * SPI_Handle. + * + * Commands for SPI_control can originate from SPI.h or from implementation + * specific SPI*.h (_SPICC26XX.h_, _SPIMSP432.h_, etc.. ) files. + * While commands from SPI.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific SPI*.h files add + * unique driver capabilities but are not API portable across all SPI driver + * implementations. + * + * Commands supported by SPI.h follow a SPI_CMD_\ naming + * convention.
+ * Commands supported by SPI*.h follow a SPI*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref SPI_CMD "SPI_control command codes" for command codes. + * + * See @ref SPI_STATUS "SPI_control return status codes" for status codes. + * + * @pre SPI_open() has to be called first. + * + * @param handle A SPI handle returned from SPI_open() + * + * @param cmd SPI.h or SPI*.h commands. + * + * @param controlArg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa SPI_open() + */ +extern int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, + void *controlArg); + +/*! + * @brief This function initializes the SPI module. + * + * @pre The SPI_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other SPI driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void SPI_init(void); + +/*! + * @brief This function opens a given SPI peripheral. + * + * @pre SPI controller has been initialized using SPI_init() + * + * @param index Logical peripheral number for the SPI indexed into + * the SPI_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A SPI_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa SPI_init() + * @sa SPI_close() + */ +extern SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params); + +/*! + * @brief Function to initialize the SPI_Params struct to its defaults + * + * @param params An pointer to SPI_Params structure for + * initialization + * + * Defaults values are: + * transferMode = SPI_MODE_BLOCKING + * transferTimeout = SPI_WAIT_FOREVER + * transferCallbackFxn = NULL + * mode = SPI_MASTER + * bitRate = 1000000 (Hz) + * dataSize = 8 (bits) + * frameFormat = SPI_POL0_PHA0 + */ +extern void SPI_Params_init(SPI_Params *params); + +/*! + * @brief Function to perform SPI transactions + * + * If the SPI is in ::SPI_MASTER mode, it will immediately start the + * transaction. If the SPI is in ::SPI_SLAVE mode, it prepares itself for a + * transaction with a SPI master. + * + * In ::SPI_MODE_BLOCKING, SPI_transfer will block task execution until the + * transaction has completed. + * + * In ::SPI_MODE_CALLBACK, SPI_transfer() does not block task execution and + * calls a ::SPI_CallbackFxn. This makes the SPI_tranfer() safe to be used + * within a Task, Swi, or Hwi context. The ::SPI_Transaction structure must + * stay persistent until the SPI_transfer function has completed! + * + * @param handle A SPI_Handle + * + * @param transaction A pointer to a SPI_Transaction. All of the fields within + * transaction except SPI_Transaction.count and + * SPI_Transaction.status are WO (write-only) unless + * otherwise noted in the driver implementations. If a + * transaction timeout has occurred, SPI_Transaction.count + * will contain the number of frames that were transferred. + * + * @return true if started successfully; else false + * + * @sa SPI_open + * @sa SPI_transferCancel + */ +extern bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction); + +/*! + * @brief Function to cancel SPI transactions + * + * In ::SPI_MODE_BLOCKING, SPI_transferCancel has no effect. + * + * In ::SPI_MODE_CALLBACK, SPI_transferCancel() will stop an SPI transfer if + * if one is in progress. + * If a transaction was in progress, its callback function will be called + * in context from which this API is called from. The ::SPI_CallbackFxn + * function can determine if the transaction was successful or not by reading + * the ::SPI_Status status value in the ::SPI_Transaction structure. + * + * @param handle A SPI_Handle + * + * @sa SPI_open + * @sa SPI_transfer + */ +extern void SPI_transferCancel(SPI_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SPI__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Timer.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Timer.h new file mode 100644 index 000000000..55648435a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Timer.h @@ -0,0 +1,437 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file Timer.h + * + * @brief Timer driver interface + * + * The Timer header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * The Timer driver operates as a generic timer interface for timing interval + * handling. It can be configured to run in one-shot blocking mode, + * one-shot callback mode, continuous callback mode, or free-run mode. This + * driver does not have PWM or capture functionalities. These functionalities + * are addressed in both the Capture and PWM driver modules. + * + * The Timer driver also handles the general purpose timer resource allocation. + * For the driver that requires to use the general purpose timer, it calls + * Timer_open() to occupy the specified timer, and calls Timer_close() to release + * the occupied timer resource. + * + * ## Opening the Driver ## + * + * @code + * Timer_Handle handle; + * Timer_Params params; + * + * Timer_Params_init(¶ms); + * params.mode = TIMER_MODE_CONTINUOUS_CALLBACK; + * params.callbackFxn = someTimerCallbackFunction; + * params.periodUnit = TIMER_PERIOD_US; + * params.period = 5000000 + * handle = Timer_open(someTimer_configIndexValue, ¶ms); + * if (!handle) + * { + * System_printf("Timer did not open"); + * } + * + * ## Starting the Driver ## + + * @code + * status = Timer_start(handle); + * if (status == TIMER_STATUS_ERROR) + * { + * System_printf("Timer cannot start at specified period"); + * } + * @endcode + * + * ## Stopping the driver ## + * + * @code + * Timer_stop(handle); + * @endcode + * + * ## closing the driver ## + * + * @code + * Timer_close(handle); + * @endcode + * + * # Implementation # + * + * This module serves as the main interface for TI Drivers + * applications. Its purpose is to redirect the module's APIs to specific + * peripheral implementations which are specified using a pointer to a + * Timer_FxnTable. + * + * The Timer driver interface module is joined (at link time) to a + * NULL-terminated array of Timer_Config data structures named *Timer_config*. + * *Timer_config* is implemented in the application with each entry being an + * instance of a Timer peripheral. Each entry in *Timer_config* contains a: + * - (Timer_FxnTable *) to a set of functions that implement a Timer peripheral + * - (void *) data object that is associated with the Timer_FxnTable + * - (void *) hardware attributes that are associated to the Timer_FxnTable + * + * # Instrumentation # + * The Timer driver interface produces log statements if instrumentation is + * enabled. + * + * ============================================================================ + */ +#ifndef ti_drivers_Timer__include +#define ti_drivers_Timer__include + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * @brief A handle that is returned from a Timer_open() call. + */ +typedef struct Timer_Config_ *Timer_Handle; + +/*! + * Common Timer_control command code reservation offset. + * Timer driver implementations should offset command codes with TIMER_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define TIMERXYZ_CMD_COMMAND0 TIMER_CMD_RESERVED + 0 + * #define TIMERXYZ_CMD_COMMAND1 TIMER_CMD_RESERVED + 1 + * @endcode + */ +#define TIMER_CMD_RESERVED (32) + +/*! + * Common Timer_control status code reservation offset. + * Timer driver implementations should offset status codes with + * TIMER_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define TIMERXYZ_STATUS_ERROR0 TIMER_STATUS_RESERVED - 0 + * #define TIMERXYZ_STATUS_ERROR1 TIMER_STATUS_RESERVED - 1 + * #define TIMERXYZ_STATUS_ERROR2 TIMER_STATUS_RESERVED - 2 + * @endcode + */ +#define TIMER_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code returned by Timer_control(). + * + * Timer_control() returns TIMER_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define TIMER_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by Timer_control(). + * + * Timer_control() returns TIMER_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define TIMER_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by Timer_control() for undefined + * command codes. + * + * Timer_control() returns TIMER_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define TIMER_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief Timer mode enum + * + * The Timer mode needs to be passed in Timer_open() to specify the timer running + * mode which handles the interrupt differently. + * + */ +typedef enum Timer_Mode_ +{ + TIMER_ONESHOT_CB, /*!< User routine doesn't get blocked and user-specified + callback function is invoked once the timer interrupt happens for only one time */ + TIMER_ONESHOT_BLOCK, /*!< User routine gets blocked until timer interrupt + happens for only one time */ + TIMER_CONTINUOUS_CB, /*!< User routine doesn't get blocked and user-specified + callback function is invoked every time the timer interrupt happens */ + TIMER_MODE_FREE_RUNNING +} Timer_Mode; + +/*! + * @brief Timer period unit enum + * + * The Timer period unit needs to be passed in Timer_open() to + * specify the unit of timing interval. + * + */ +typedef enum Timer_Period_Units_ +{ + TIMER_PERIOD_US, /* Period in microseconds */ + TIMER_PERIOD_HZ, /* Period in frequency */ + TIMER_PERIOD_COUNTS /* Period in counts */ +} Timer_Period_Units; + +/*! + * @brief Timer callback function + * + * User definable callback function prototype. The Timer driver will call the + * defined function and pass in the Timer driver's handle and the pointer to the + * user-specified the argument. + * + * @param handle Timer_Handle + */ +typedef void (*Timer_CallBackFxn)(Timer_Handle handle); + +/*! + * @brief Timer Parameters + * + * Timer parameters are used to with the Timer_open() call. Default values for + * these parameters are set using Timer_Params_init(). + * + */ +typedef struct Timer_Params_ +{ + Timer_Mode timerMode; + Timer_Period_Units periodUnits; + Timer_CallBackFxn timerCallback; + uint32_t period; +} Timer_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_control(). + */ +typedef int_fast16_t (*Timer_ControlFxn)(Timer_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_close(). + */ +typedef void (*Timer_CloseFxn)(Timer_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_getCount(). + */ +typedef uint32_t (*Timer_GetCountFxn)(Timer_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_init(). + */ +typedef void (*Timer_InitFxn)(Timer_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_open(). + */ +typedef Timer_Handle (*Timer_OpenFxn)(Timer_Handle handle, + Timer_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_start(). + */ +typedef void (*Timer_StartFxn)(Timer_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_stop(). + */ +typedef void (*Timer_StopFxn)(Timer_Handle handle); + +/*! + * @brief The definition of a Timer function table that contains the + * required set of functions to control a specific Timer driver + * implementation. + */ +typedef struct Timer_FxnTable_ +{ + /*! Function to close the specified instance */ + Timer_CloseFxn closeFxn; + /*! Function to send contorl commands to the counter for a specific instance */ + Timer_ControlFxn controlFxn; + /*! Function to get the count of the timer for a specific instance */ + Timer_GetCountFxn getCountFxn; + /*! Function to open the specified instance */ + Timer_InitFxn initFxn; + /*! Function to open the specified instance */ + Timer_OpenFxn openFxn; + /*! Function to start the timer for a specific instance */ + Timer_StartFxn startFxn; + /*! Function to stop the timer for a specific instance */ + Timer_StopFxn stopFxn; +} Timer_FxnTable; + +typedef struct Timer_Config_ +{ + Timer_FxnTable const *fxnTablePtr; + void *object; + void const *hwAttrs; +} Timer_Config; + +/*! + * @brief Function performs implementation specific features on a given + * Timer_Handle. + * + * @pre Timer_open() must have been called first. + * + * @param handle A Timer_Handle returned from Timer_open(). + * + * @param cmd A command value defined by the driver specific + * implementation. + * + * @param arg A pointer to an optional R/W (read/write) argument that + * is accompanied with cmd. + * + * @return A Timer_Status describing an error or success state. Negative values + * indicate an error occurred. + * + * @sa Timer_open() + */ +extern int_fast16_t Timer_control(Timer_Handle handle, uint_fast16_t cmd, + void *arg); + + +/*! + * @brief Function to close a Timer peripheral specified by the Timer handle + * + * The function takes care of timer resource allocation. The corresponding timer + * resource to the Timer_Handle is released to be an available timer resource. + * + * @pre Timer_open() had to be called first. + * + * @param handle A Timer_Handle returned from Timer_open + * + * @sa Timer_open() + */ +extern void Timer_close(Timer_Handle handle); + +/*! + * @brief Function to get the current count of a started timer + * + * @pre Timer_open() had to be called first. + * + * @param handle A Timer_Handle returned from Timer_open + * + * @sa Timer_open() + * + * @return The current count of the specified Timer + * + */ +extern uint32_t Timer_getCount(Timer_Handle handle); + + +/*! + * @brief Function to initialize a timer module. This function will go through + * all available hardware resources and mark them as "available" + * + * @sa Timer_open() + */ +extern void Timer_init(void); + +/*! + * @brief Function to initialize a given Timer peripheral specified by the + * particular index value. The parameter specifies which mode the Timer + * will operate. + * + * The function takes care of timer resource allocation. If the particular timer + * passed by user has already been used by other modules, the return value is NULL. + * If the particular timer is available to use, Timer module owns it and returns + * a Timer_Handle. + * + * @param index Logical peripheral number for the Timer indexed into + * the Timer_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A Timer_Handle on success or a NULL on an error if it has been + * opened already or used by other modules. + * + * @sa Timer_init() + * @sa Timer_close() + */ +extern Timer_Handle Timer_open(uint_least8_t index, Timer_Params *params); + +/*! + * @brief Function to initialize the Timer_Params struct to its defaults + * + * @param params An pointer to Timer_Params structure for + * initialization + * + * Defaults values are: + * mode = TIMER_MODE_ONESHOT_BLOCKING + * callbackFxn = NULL + * periodUnit = TIMER_PERIOD_US + * period = 0xFFFF + */ +extern void Timer_Params_init(Timer_Params *params); + +/*! + * @brief Function to start Timer with the given period. The timer running mode + * and interval period unit are specified in the Timer_Params when calling + * Timer_open(). + * + * @param handle Timer_Handle + * + * @return TIMER_STATUS_SUCCESS if timer starts successfully. + * TIMER_STATUS_ERROR if timer fails to start. + * + */ +extern void Timer_start(Timer_Handle handle); + +/*! + * @brief Function to stop timer after Timer_start() is called with success. + * + * @param handle Timer_Handle + * + */ +extern void Timer_stop(Timer_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_driver_Timer__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/UART.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/UART.h new file mode 100644 index 000000000..0812ac786 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/UART.h @@ -0,0 +1,966 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file UART.h + * @brief UART driver interface + * + * To use the UART driver, ensure that the correct driver library for your + * device is linked in and include this header file as follows: + * @code + * #include + * @endcode + * + * This module serves as the main interface for applications. Its purpose + * is to redirect the UART APIs to specific driver implementations + * which are specified using a pointer to a #UART_FxnTable. + * + * # Overview # + * A UART is used to translate data between the chip and a serial port. + * The UART driver simplifies reading and writing to any of the UART + * peripherals on the board, with multiple modes of operation and performance. + * These include blocking, non-blocking, and polling, as well as text/binary + * mode, echo and return characters. + * + * The APIs in this driver serve as an interface to a typical RTOS + * application. The specific peripheral implementations are responsible for + * creating all the RTOS specific primitives to allow for thread-safe + * operation. + * + * # Usage # + * + * The UART driver interface provides device independent APIs, data types, + * and macros. The following code example opens a UART instance, reads + * a byte from the UART, and then writes the byte back to the UART. + * + * @code + * char input; + * UART_Handle uart; + * UART_Params uartParams; + * + * // Initialize the UART driver. + * UART_init(); + * + * // Create a UART with data processing off. + * UART_Params_init(&uartParams); + * uartParams.writeDataMode = UART_DATA_BINARY; + * uartParams.readDataMode = UART_DATA_BINARY; + * uartParams.readReturnMode = UART_RETURN_FULL; + * uartParams.readEcho = UART_ECHO_OFF; + * uartParams.baudRate = 9600; + * + * // Open an instance of the UART drivers + * uart = UART_open(Board_UART0, &uartParams); + * + * if (uart == NULL) { + * // UART_open() failed + * while (1); + * } + * + * // Loop forever echoing + * while (1) { + * UART_read(uart, &input, 1); + * UART_write(uart, &input, 1); + * } + * @endcode + * + * Details for the example code above are described in the following + * subsections. + * + * + * ### UART Driver Configuration # + * + * In order to use the UART APIs, the application is required + * to provide device-specific UART configuration in the Board.c file. + * The UART driver interface defines a configuration data structure: + * + * @code + * typedef struct UART_Config_ { + * UART_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } UART_Config; + * @endcode + * + * The application must declare an array of UART_Config elements, named + * UART_config[]. Each element of UART_config[] are populated with + * pointers to a device specific UART driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the UART peripheral's base address, and + * the pins for RX and TX. Each element in UART_config[] corresponds to + * a UART instance, and none of the elements should have NULL pointers. + * There is no correlation between the index and the peripheral designation + * (such as UART0 or UART1). For example, it is possible to use + * UART_config[0] for UART1. + * + * You will need to check the device-specific UART driver implementation's + * header file for example configuration. Please also refer to the + * Board.c file of any of your examples to see the UART configuration. + * + * ### Initializing the UART Driver # + * + * UART_init() must be called before any other UART APIs. This function + * calls the device implementation's UART initialization function, for each + * element of UART_config[]. + * + * ### Opening the UART Driver # + * + * Opening a UART requires four steps: + * 1. Create and initialize a UART_Params structure. + * 2. Fill in the desired parameters. + * 3. Call UART_open(), passing the index of the UART in the UART_config + * structure, and the address of the UART_Params structure. The + * UART instance is specified by the index in the UART_config structure. + * 4. Check that the UART handle returned by UART_open() is non-NULL, + * and save it. The handle will be used to read and write to the + * UART you just opened. + * + * Only one UART index can be used at a time; calling UART_open() a second + * time with the same index previosly passed to UART_open() will result in + * an error. You can, though, re-use the index if the instance is closed + * via UART_close(). + * In the example code, Board_UART0 is passed to UART_open(). This macro + * is defined in the example's Board.h file. + * + * + * ### Modes of Operation # + * + * The UART driver can operate in blocking mode or callback mode, by + * setting the writeMode and readMode parameters passed to UART_open(). + * If these parameters are not set, as in the example code, the UART + * driver defaults to blocking mode. Options for the writeMode and + * readMode parameters are #UART_MODE_BLOCKING and #UART_MODE_CALLBACK: + * + * - #UART_MODE_BLOCKING uses a semaphore to block while data is being sent. + * The context of calling UART_read() or UART_write() must be a Task when + * using #UART_MODE_BLOCKING. The UART_write() or UART_read() call + * will block until all data is sent or received, or the write timeout or + * read timeout expires, whichever happens first. + * + * - #UART_MODE_CALLBACK is non-blocking and UART_read() and UART_write() + * will return while data is being sent in the context of a hardware + * interrupt. When the read or write finishes, the UART driver will call + * the user's callback function. In some cases, the UART data transfer + * may have been canceled, or a newline may have been received, so the + * number of bytes sent/received are passed to the callback function. Your + * implementation of the callback function can use this imformation + * as needed. Since the user's callback may be called in the context of an + * ISR, the callback function must not make any RTOS blocking calls. + * + * The example sets the writeDataMode and readDataMode parameters to + * #UART_DATA_BINARY. Options for these parameters are #UART_DATA_BINARY + * and #UART_DATA_TEXT: + * + * - #UART_DATA_BINARY: The data is passed as is, without processing. + * + * - #UART_DATA_TEXT: Write actions add a carriage return before a + * newline character, and read actions replace a return with a newline. + * This effectively treats all device line endings as LF and all host + * PC line endings as CRLF. + * + * Other parameters set by the example are readReturnMode and readEcho. + * Options for the readReturnMode parameter are #UART_RETURN_FULL and + * #UART_RETURN_NEWLINE: + * + * - #UART_RETURN_FULL: The read action unblocks or returns when the buffer + * is full. + * - #UART_RETURN_NEWLINE: The read action unblocks or returns when a + * newline character if read, before the buffer is full. + * + * Options for the readEcho parameter are #UART_ECHO_OFF and #UART_ECHO_ON. + * This parameter determines whether the driver echoes data back to the + * UART. When echo is turned on, each character that is read by the target + * is written back, independent of any write operations. If data is + * received in the middle of a write and echo is turned on, the echoed + * characters will be mixed in with the write data. + * + * ### Reading and Writing data # + * + * The example code reads one byte frome the UART instance, and then writes + * one byte back to the same instance: + * + * @code + * UART_read(uart, &input, 1); + * UART_write(uart, &input, 1); + * @endcode + * + * The UART driver allows full duplex data transfers. Therefore, it is + * possible to call UART_read() and UART_write() at the same time (for + * either blocking or callback modes). It is not possible, however, + * to issue multiple concurrent operations in the same direction. + * For example, if one thread calls UART_read(uart0, buffer0...), + * any other thread attempting UART_read(uart0, buffer1...) will result in + * an error of UART_ERROR, until all the data from the first UART_read() + * has been transferred to buffer0. This applies to both blocking and + * and callback modes. So applications must either synchronize + * UART_read() (or UART_write()) calls that use the same UART handle, or + * check for the UART_ERROR return code indicating that a transfer is still + * ongoing. + * + * # Implementation # + * + * The UART driver interface module is joined (at link time) to an + * array of UART_Config data structures named *UART_config*. + * UART_config is implemented in the application with each entry being an + * instance of a UART peripheral. Each entry in *UART_config* contains a: + * - (UART_FxnTable *) to a set of functions that implement a UART peripheral + * - (void *) data object that is associated with the UART_FxnTable + * - (void *) hardware attributes that are associated with the UART_FxnTable + * + * The UART APIs are redirected to the device specific implementations + * using the UART_FxnTable pointer of the UART_config entry. + * In order to use device specific functions of the UART driver directly, + * link in the correct driver library for your device and include the + * device specific UART driver header file (which in turn includes UART.h). + * For example, for the MSP432 family of devices, you would include the + * following header file: + * @code + * #include + * @endcode + * + * ### Stack Requirements # + * It is STRONGLY discouraged to perform UART_read() or UART_write() + * calls within the driver's own callback function when in + * #UART_MODE_CALLBACK mode. Doing so will incur additional task or system + * stack size requirements. See the peripheral implementations' + * documentation for stack size estimations. It is expected that the + * user perform their own stack and usage analysis when choosing to + * nest these calls. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_UART__include +#define ti_drivers_UART__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @defgroup UART_CONTROL UART_control command and status codes + * These UART macros are reservations for UART.h + * @{ + */ + +/*! + * Common UART_control command code reservation offset. + * UART driver implementations should offset command codes with + * UART_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define UARTXYZ_CMD_COMMAND0 UART_CMD_RESERVED + 0 + * #define UARTXYZ_CMD_COMMAND1 UART_CMD_RESERVED + 1 + * @endcode + */ +#define UART_CMD_RESERVED (32) + +/*! + * Common UART_control status code reservation offset. + * UART driver implementations should offset status codes with + * UART_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define UARTXYZ_STATUS_ERROR0 UART_STATUS_RESERVED - 0 + * #define UARTXYZ_STATUS_ERROR1 UART_STATUS_RESERVED - 1 + * #define UARTXYZ_STATUS_ERROR2 UART_STATUS_RESERVED - 2 + * @endcode + */ +#define UART_STATUS_RESERVED (-32) + +/** + * @defgroup UART_STATUS Status Codes + * UART_STATUS_* macros are general status codes returned by UART_control() + * @{ + * @ingroup UART_CONTROL + */ + +/*! + * @brief Successful status code returned by UART_control(). + * + * UART_control() returns UART_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define UART_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by UART_control(). + * + * UART_control() returns UART_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define UART_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by UART_control() for undefined + * command codes. + * + * UART_control() returns UART_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define UART_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup UART_CMD Command Codes + * UART_CMD_* macros are general command codes for UART_control(). Not all UART + * driver implementations support these command codes. + * @{ + * @ingroup UART_CONTROL + */ + +/*! + * @brief Command code used by UART_control() to read the next unsigned char. + * + * This command is used to read the next unsigned char from the UART's circular + * buffer without removing it. With this command code, @b arg is a pointer to an + * integer. @b *arg contains the next @c unsigned @c char read if data is + * present, else @b *arg is set to #UART_ERROR. + */ +#define UART_CMD_PEEK (0) + +/*! + * @brief Command code used by UART_control() to determine if the read buffer + * is empty. + * + * This command is used to determine if there are any unsigned chars available + * to read from the UART's circular buffer using UART_read(). With this command + * code, @b arg is a pointer to a @c bool. @b *arg contains @c true if data is + * available, else @c false. + */ +#define UART_CMD_ISAVAILABLE (1) + +/*! + * @brief Command code used by UART_control() to determine how many unsigned + * chars are in the read buffer. + * + * This command is used to determine how many @c unsigned @c chars are available + * to read from the UART's circular buffer using UART_read(). With this command + * code, @b arg is a pointer to an @a integer. @b *arg contains the number of + * @c unsigned @c chars available to read. + */ +#define UART_CMD_GETRXCOUNT (2) + +/*! + * @brief Command code used by UART_control() to enable data receive by the + * UART. + * + * This command is used to enable the UART in such a way that it stores received + * unsigned chars into the circular buffer. For drivers that support power + * management, this typically means that the UART will set a power constraint + * while receive is enabled. UART_open() will always have this option + * enabled. With this command code, @b arg is @a don't @a care. + */ +#define UART_CMD_RXENABLE (3) + +/*! + * @brief Command code used by UART_control() to disable data received by the + * UART. + * + * This command is used to disable the UART in such a way that ignores the data + * it receives. For drivers that support power management, this typically means + * that the driver will release any power constraints, to permit the system to + * enter low power modes. With this command code, @b arg is @a don't @a care. + * + * @warning A call to UART_read() does @b NOT re-enable receive. + */ +#define UART_CMD_RXDISABLE (4) +/** @}*/ + +/** @}*/ + +#define UART_ERROR (UART_STATUS_ERROR) + +/*! + * @brief Wait forever define + */ +#define UART_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from a UART_open() call. + */ +typedef struct UART_Config_ *UART_Handle; + +/*! + * @brief The definition of a callback function used by the UART driver + * when used in #UART_MODE_CALLBACK + * The callback can occur in task or HWI context. + * + * @warning Making UART_read() or UART_write() calls within its own callback + * routines are STRONGLY discouraged as it will impact Task and + * System stack size requirements! See the documentation for the + * specific driver implementations for additional estimated stack + * requirements. + * + * @param UART_Handle UART_Handle + * + * @param buf Pointer to read/write buffer + * + * @param count Number of elements read/written + */ +typedef void (*UART_Callback) (UART_Handle handle, void *buf, size_t count); + +/*! + * @brief UART mode settings + * + * This enum defines the read and write modes for the configured UART. + */ +typedef enum UART_Mode_ { + /*! + * Uses a semaphore to block while data is being sent. Context of the call + * must be a Task. + */ + UART_MODE_BLOCKING, + + /*! + * Non-blocking and will return immediately. When UART_write() or + * UART_read() has finished, the callback function is called from either + * the caller's context or from an interrupt context. + */ + UART_MODE_CALLBACK +} UART_Mode; + +/*! + * @brief UART return mode settings + * + * This enumeration defines the return modes for UART_read() and + * UART_readPolling(). This mode only functions when in #UART_DATA_TEXT mode. + * + * #UART_RETURN_FULL unblocks or performs a callback when the read buffer has + * been filled. + * #UART_RETURN_NEWLINE unblocks or performs a callback whenever a newline + * character has been received. + * + * UART operation | UART_RETURN_FULL | UART_RETURN_NEWLINE | + * -------------- | ---------------- | ------------------- | + * UART_read() | Returns when buffer is full | Returns when buffer is full or newline was read | + * UART_write() | Sends data as is | Sends data with an additional newline at the end | + * + * @pre UART driver must be used in #UART_DATA_TEXT mode. + */ +typedef enum UART_ReturnMode_ { + /*! Unblock/callback when buffer is full. */ + UART_RETURN_FULL, + + /*! Unblock/callback when newline character is received. */ + UART_RETURN_NEWLINE +} UART_ReturnMode; + +/*! + * @brief UART data mode settings + * + * This enumeration defines the data mode for reads and writes. + * + * In #UART_DATA_BINARY, data is passed as is, with no processing. + * + * In #UART_DATA_TEXT mode, the driver will examine the #UART_ReturnMode + * value, to determine whether or not to unblock/callback when a newline + * is received. Read actions replace a carriage return with a newline, + * and write actions add a carriage return before a newline. This + * effectively treats all device line endings as LF, and all host PC line + * endings as CRLF. + */ +typedef enum UART_DataMode_ { + UART_DATA_BINARY = 0, /*!< Data is not processed */ + UART_DATA_TEXT = 1 /*!< Data is processed according to above */ +} UART_DataMode; + +/*! + * @brief UART echo settings + * + * This enumeration defines if the driver will echo data when uses in + * #UART_DATA_TEXT mode. This only applies to data received by the UART. + * + * #UART_ECHO_ON will echo back characters it received while in #UART_DATA_TEXT + * mode. + * #UART_ECHO_OFF will not echo back characters it received in #UART_DATA_TEXT + * mode. + * + * @pre UART driver must be used in #UART_DATA_TEXT mode. + */ +typedef enum UART_Echo_ { + UART_ECHO_OFF = 0, /*!< Data is not echoed */ + UART_ECHO_ON = 1 /*!< Data is echoed */ +} UART_Echo; + +/*! + * @brief UART data length settings + * + * This enumeration defines the UART data lengths. + */ +typedef enum UART_LEN_ { + UART_LEN_5 = 0, /*!< Data length is 5 bits */ + UART_LEN_6 = 1, /*!< Data length is 6 bits */ + UART_LEN_7 = 2, /*!< Data length is 7 bits */ + UART_LEN_8 = 3 /*!< Data length is 8 bits */ +} UART_LEN; + +/*! + * @brief UART stop bit settings + * + * This enumeration defines the UART stop bits. + */ +typedef enum UART_STOP_ { + UART_STOP_ONE = 0, /*!< One stop bit */ + UART_STOP_TWO = 1 /*!< Two stop bits */ +} UART_STOP; + +/*! + * @brief UART parity type settings + * + * This enumeration defines the UART parity types. + */ +typedef enum UART_PAR_ { + UART_PAR_NONE = 0, /*!< No parity */ + UART_PAR_EVEN = 1, /*!< Parity bit is even */ + UART_PAR_ODD = 2, /*!< Parity bit is odd */ + UART_PAR_ZERO = 3, /*!< Parity bit is always zero */ + UART_PAR_ONE = 4 /*!< Parity bit is always one */ +} UART_PAR; + +/*! + * @brief UART Parameters + * + * UART parameters are used with the UART_open() call. Default values for + * these parameters are set using UART_Params_init(). + * + * @sa UART_Params_init() + */ +typedef struct UART_Params_ { + UART_Mode readMode; /*!< Mode for all read calls */ + UART_Mode writeMode; /*!< Mode for all write calls */ + uint32_t readTimeout; /*!< Timeout for read calls in blocking mode. */ + uint32_t writeTimeout; /*!< Timeout for write calls in blocking mode. */ + UART_Callback readCallback; /*!< Pointer to read callback function for callback mode. */ + UART_Callback writeCallback; /*!< Pointer to write callback function for callback mode. */ + UART_ReturnMode readReturnMode; /*!< Receive return mode */ + UART_DataMode readDataMode; /*!< Type of data being read */ + UART_DataMode writeDataMode; /*!< Type of data being written */ + UART_Echo readEcho; /*!< Echo received data back */ + uint32_t baudRate; /*!< Baud rate for UART */ + UART_LEN dataLength; /*!< Data length for UART */ + UART_STOP stopBits; /*!< Stop bits for UART */ + UART_PAR parityType; /*!< Parity bit type for UART */ + void *custom; /*!< Custom argument used by driver implementation */ +} UART_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_CloseFxn(). + */ +typedef void (*UART_CloseFxn) (UART_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_ControlFxn(). + */ +typedef int_fast16_t (*UART_ControlFxn) (UART_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_InitFxn(). + */ +typedef void (*UART_InitFxn) (UART_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_OpenFxn(). + */ +typedef UART_Handle (*UART_OpenFxn) (UART_Handle handle, UART_Params *params); +/*! + * @brief A function pointer to a driver specific implementation of + * UART_ReadFxn(). + */ +typedef int_fast32_t (*UART_ReadFxn) (UART_Handle handle, void *buffer, + size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_ReadPollingFxn(). + */ +typedef int_fast32_t (*UART_ReadPollingFxn) (UART_Handle handle, void *buffer, + size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_ReadCancelFxn(). + */ +typedef void (*UART_ReadCancelFxn) (UART_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_WriteFxn(). + */ +typedef int_fast32_t (*UART_WriteFxn) (UART_Handle handle, const void *buffer, + size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_WritePollingFxn(). + */ +typedef int_fast32_t (*UART_WritePollingFxn) (UART_Handle handle, + const void *buffer, size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_WriteCancelFxn(). + */ +typedef void (*UART_WriteCancelFxn) (UART_Handle handle); + +/*! + * @brief The definition of a UART function table that contains the + * required set of functions to control a specific UART driver + * implementation. + */ +typedef struct UART_FxnTable_ { + /*! Function to close the specified peripheral */ + UART_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + UART_ControlFxn controlFxn; + + /*! Function to initialize the given data object */ + UART_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + UART_OpenFxn openFxn; + + /*! Function to read from the specified peripheral */ + UART_ReadFxn readFxn; + + /*! Function to read via polling from the specified peripheral */ + UART_ReadPollingFxn readPollingFxn; + + /*! Function to cancel a read from the specified peripheral */ + UART_ReadCancelFxn readCancelFxn; + + /*! Function to write from the specified peripheral */ + UART_WriteFxn writeFxn; + + /*! Function to write via polling from the specified peripheral */ + UART_WritePollingFxn writePollingFxn; + + /*! Function to cancel a write from the specified peripheral */ + UART_WriteCancelFxn writeCancelFxn; +} UART_FxnTable; + +/*! + * @brief UART Global configuration + * + * The UART_Config structure contains a set of pointers used to characterize + * the UART driver implementation. + * + * This structure needs to be defined before calling UART_init() and it must + * not be changed thereafter. + * + * @sa UART_init() + */ +typedef struct UART_Config_ { + /*! Pointer to a table of driver-specific implementations of UART APIs */ + UART_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} UART_Config; + +/*! + * @brief Function to close a UART peripheral specified by the UART handle + * + * @pre UART_open() has been called. + * @pre Ongoing asynchronous read or write have been canceled using + * UART_readCancel() or UART_writeCancel() respectively. + * + * @param handle A #UART_Handle returned from UART_open() + * + * @sa UART_open() + */ +extern void UART_close(UART_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #UART_Handle. + * + * Commands for %UART_control() can originate from UART.h or from implementation + * specific UART*.h (_UARTCC26XX.h_, _UARTMSP432.h_, etc.. ) files. + * While commands from UART.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific UART*.h files add + * unique driver capabilities but are not API portable across all UART driver + * implementations. + * + * Commands supported by UART.h follow a UART_CMD_\ naming + * convention.
+ * Commands supported by UART*.h follow a UART*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref UART_CMD "UART_control command codes" for command codes. + * + * See @ref UART_STATUS "UART_control return status codes" for status codes. + * + * @pre UART_open() has to be called. + * + * @param handle A UART handle returned from UART_open() + * + * @param cmd UART.h or UART*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa UART_open() + */ +extern int_fast16_t UART_control(UART_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief Function to initialize the UART module + * + * @pre The UART_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other UART driver APIs. + */ +extern void UART_init(void); + +/*! + * @brief Function to initialize a given UART peripheral + * + * Function to initialize a given UART peripheral specified by the + * particular index value. + * + * @pre UART_init() has been called + * + * @param index Logical peripheral number for the UART indexed into + * the UART_config table + * + * @param params Pointer to a parameter block. If NULL, default + * parameter values will be used. All the fields in + * this structure are RO (read-only). + * + * @return A #UART_Handle upon success. NULL if an error occurs, or if the + * indexed UART peripheral is already opened. + * + * @sa UART_init() + * @sa UART_close() + */ +extern UART_Handle UART_open(uint_least8_t index, UART_Params *params); + +/*! + * @brief Function to initialize the UART_Params struct to its defaults + * + * @param params An pointer to UART_Params structure for + * initialization + * + * Defaults values are: + * readMode = UART_MODE_BLOCKING; + * writeMode = UART_MODE_BLOCKING; + * readTimeout = UART_WAIT_FOREVER; + * writeTimeout = UART_WAIT_FOREVER; + * readCallback = NULL; + * writeCallback = NULL; + * readReturnMode = UART_RETURN_NEWLINE; + * readDataMode = UART_DATA_TEXT; + * writeDataMode = UART_DATA_TEXT; + * readEcho = UART_ECHO_ON; + * baudRate = 115200; + * dataLength = UART_LEN_8; + * stopBits = UART_STOP_ONE; + * parityType = UART_PAR_NONE; + */ +extern void UART_Params_init(UART_Params *params); + +/*! + * @brief Function that writes data to a UART with interrupts enabled. + * + * %UART_write() writes data from a memory buffer to the UART interface. + * The source is specified by \a buffer and the number of bytes to write + * is given by \a size. + * + * In #UART_MODE_BLOCKING, UART_write() blocks task execution until all + * the data in buffer has been written. + * + * In #UART_MODE_CALLBACK, %UART_write() does not block task execution. + * Instead, a callback function specified by UART_Params::writeCallback is + * called when the transfer is finished. + * The callback function can occur in the caller's task context or in a HWI or + * SWI context, depending on the device implementation. + * An unfinished asynchronous write operation must always be canceled using + * UART_writeCancel() before calling UART_close(). + * + * %UART_write() is mutually exclusive to UART_writePolling(). For an opened + * UART peripheral, either UART_write() or UART_writePolling() can be used, + * but not both. + * + * @warning Do not call %UART_write() from its own callback function when in + * #UART_MODE_CALLBACK. + * + * @sa UART_writePolling() + * + * @param handle A #UART_Handle returned by UART_open() + * + * @param buffer A read-only pointer to buffer containing data to + * be written to the UART + * + * @param size The number of bytes in the buffer that should be written + * to the UART + * + * @return Returns the number of bytes that have been written to the UART. + * If an error occurs, #UART_ERROR is returned. + * In #UART_MODE_CALLBACK mode, the return value is always 0. + */ +extern int_fast32_t UART_write(UART_Handle handle, const void *buffer, size_t size); + +/*! + * @brief Function that writes data to a UART, polling the peripheral to + * wait until new data can be written. Usage of this API is mutually + * exclusive with usage of UART_write(). + * + * This function initiates an operation to write data to a UART controller. + * + * UART_writePolling() will not return until all the data was written to the + * UART (or to its FIFO if applicable). + * + * @sa UART_write() + * + * @param handle A #UART_Handle returned by UART_open() + * + * @param buffer A read-only pointer to the buffer containing the data to + * be written to the UART + * + * @param size The number of bytes in the buffer that should be written + * to the UART + * + * @return Returns the number of bytes that have been written to the UART. + * If an error occurs, #UART_ERROR is returned. + */ +extern int_fast32_t UART_writePolling(UART_Handle handle, const void *buffer, size_t size); + +/*! + * @brief Function that cancels a UART_write() function call. + * + * This function cancels an asynchronous UART_write() operation and is only + * applicable in #UART_MODE_CALLBACK. + * UART_writeCancel() calls the registered TX callback function no matter how many bytes + * were sent. It is the application's responsibility to check the count argument in + * the callback function and handle cases where only a subset of the bytes were sent. + * + * @param handle A #UART_Handle returned by UART_open() + */ +extern void UART_writeCancel(UART_Handle handle); + +/*! + * @brief Function that reads data from a UART with interrupt enabled. + * + * %UART_read() reads data from a UART controller. The destination is specified + * by \a buffer and the number of bytes to read is given by \a size. + * + * In #UART_MODE_BLOCKING, %UART_read() blocks task execution until all + * the data in buffer has been read. + * + * In #UART_MODE_CALLBACK, %UART_read() does not block task execution. + * Instead, a callback function specified by UART_Params::readCallback + * is called when the transfer is finished. + * The callback function can occur in the caller's context or in HWI or SWI + * context, depending on the device-specific implementation. + * An unfinished asynchronous read operation must always be canceled using + * UART_readCancel() before calling UART_close(). + * + * %UART_read() is mutually exclusive to UART_readPolling(). For an opened + * UART peripheral, either %UART_read() or UART_readPolling() can be used, + * but not both. + * + * @warning Do not call %UART_read() from its own callback function when in + * #UART_MODE_CALLBACK. + * + * @sa UART_readPolling() + * + * @param handle A #UART_Handle returned by UART_open() + * + * @param buffer A pointer to an empty buffer to which + * received data should be written + * + * @param size The number of bytes to be written into buffer + * + * @return Returns the number of bytes that have been read from the UART, + * #UART_ERROR on an error. + */ +extern int_fast32_t UART_read(UART_Handle handle, void *buffer, size_t size); + +/*! + * @brief Function that reads data from a UART without interrupts. This API + * must be used mutually exclusive with UART_read(). + * + * This function initiates an operation to read data from a UART peripheral. + * + * %UART_readPolling() will not return until size data was read to the UART. + * + * @sa UART_read() + * + * @param handle A #UART_Handle returned by UART_open() + * + * @param buffer A pointer to an empty buffer in which + * received data should be written to + * + * @param size The number of bytes to be written into buffer + * + * @return Returns the number of bytes that have been read from the UART, + * #UART_ERROR on an error. + */ +extern int_fast32_t UART_readPolling(UART_Handle handle, void *buffer, size_t size); + +/*! + * @brief Function that cancels a UART_read() function call. + * + * This function cancels an asynchronous UART_read() operation and is only + * applicable in #UART_MODE_CALLBACK. + * UART_readCancel() calls the registered RX callback function no matter how many bytes + * were received. It is the application's responsibility to check the count argument in + * the callback function and handle cases where only a subset of the bytes were received. + * + * @param handle A #UART_Handle returned by UART_open() + */ +extern void UART_readCancel(UART_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_UART__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Watchdog.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Watchdog.h new file mode 100644 index 000000000..e09c8e109 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/Watchdog.h @@ -0,0 +1,538 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file Watchdog.h + * + * @brief Watchdog driver interface + * + * The Watchdog header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * + * A watchdog timer can be used to generate a reset signal if a system has + * become unresponsive. The Watchdog driver simplifies configuring and + * starting the watchdog peripherals. The watchdog peripheral can be + * configured with resets either on or off and a user-specified timeout + * period. + * + * When the watchdog peripheral is configured not to generate a reset, it + * can be used to cause a hardware interrupt at a programmable interval. + * The driver provides the ability to specify a user-provided callback + * function that is called when the watchdog causes an interrupt. + * + * # Operation # + * + * The Watchdog driver simplifies configuring and starting the Watchdog + * peripherals. The Watchdog can be set up to produce a reset signal after a + * timeout, or simply cause a hardware interrupt at a programmable interval. + * The driver provides the ability to specify a callback function that is + * called when the Watchdog causes an interrupt. + * + * When resets are turned on, it is the user application's responsibility to + * call Watchdog_clear() in order to clear the Watchdog and prevent a reset. + * Watchdog_clear() can be called at any time. + * + * # Usage # + * + * The Watchdog driver must be initialized by calling Watchdog_init(), + * before any other Watchdog APIs can be called. + * Once the watchdog is initialized, a Watchdog object can be created + * through the following steps: + * - Create and initialize the Watchdog_Params structure. + * - Assign desired values to parameters. + * - Call Watchdog_open(). + * - Save the Watchdog_Handle returned by Watchdog_open(). This will be + * used to interact with the Watchdog object just created. + * + * To have a user-defined function run at the hardware interrupt caused by + * a watchdog timer timeout, define a function of the following type: + * @code + * typedef void (*Watchdog_Callback)(uintptr_t); + * @endcode + * Then pass the function to Watchdog_open() through the Watchdog_Params + * structure. + * + * An example of the Watchdog creation process that uses a callback + * function: + * @code + * Watchdog_Params params; + * Watchdog_Handle watchdog; + * + * Watchdog_init(); + * + * Watchdog_Params_init(¶ms); + * params.resetMode = Watchdog_RESET_ON; + * params.callbackFxn = UserCallbackFxn; + * + * watchdog = Watchdog_open(Board_WATCHDOG, ¶ms); + * if (watchdog == NULL) { + * `Error opening watchdog` + * } + * @endcode + * + * If no Watchdog_Params structure is passed to Watchdog_open(), the + * default values are used. By default, the Watchdog driver has resets + * turned on, no callback function specified, and stalls the timer at + * breakpoints during debugging. + * + * Options for the resetMode parameter are Watchdog_RESET_ON and + * Watchdog_RESET_OFF. The latter allows the watchdog to be used like + * another timer interrupt. When resetMode is Watchdog_RESET_ON, it is up + * to the application to call Watchdog_clear() to clear the Watchdog + * interrupt flag to prevent a reset. Watchdog_clear() can be called at + * any time. + * + * # Implementation # + * + * This module serves as the main interface for TI-RTOS applications. Its + * purpose is to redirect the module's APIs to specific peripheral + * implementations which are specified using a pointer to a + * Watchdog_FxnTable. + * + * The Watchdog driver interface module is joined (at link time) + * to a NULL-terminated array of Watchdog_Config data structures named + * *Watchdog_config*. *Watchdog_config* is implemented in the application with + * each entry being an instance of a Watchdog peripheral. Each entry in + * *Watchdog_config* contains a: + * - (Watchdog_FxnTable *) to a set of functions that implement a Watchdog + * peripheral + * - (void *) data object that is associated with the Watchdog_FxnTable + * - (void *) hardware attributes that are associated to the Watchdog_FxnTable + * + ******************************************************************************* + */ + +#ifndef ti_drivers_Watchdog__include +#define ti_drivers_Watchdog__include + +#ifdef __cplusplus +extern "C" { +#endif + + +#include + +/** + * @defgroup Watchdog_CONTROL Watchdog_control command and status codes + * These Watchdog macros are reservations for Watchdog.h + * @{ + */ + +/*! + * Common Watchdog_control command code reservation offset. + * Watchdog driver implementations should offset command codes with + * Watchdog_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define WatchdogXYZ_CMD_COMMAND0 Watchdog_CMD_RESERVED + 0 + * #define WatchdogXYZ_CMD_COMMAND1 Watchdog_CMD_RESERVED + 1 + * @endcode + */ +#define Watchdog_CMD_RESERVED (32) + +/*! + * Common Watchdog_control status code reservation offset. + * Watchdog driver implementations should offset status codes with + * Watchdog_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define WatchdogXYZ_STATUS_ERROR0 Watchdog_STATUS_RESERVED - 0 + * #define WatchdogXYZ_STATUS_ERROR1 Watchdog_STATUS_RESERVED - 1 + * #define WatchdogXYZ_STATUS_ERROR2 Watchdog_STATUS_RESERVED - 2 + * @endcode + */ +#define Watchdog_STATUS_RESERVED (-32) + +/** + * @defgroup Watchdog_STATUS Status Codes + * Watchdog_STATUS_* macros are general status codes returned by Watchdog_control() + * @{ + * @ingroup Watchdog_CONTROL + */ + +/*! + * @brief Successful status code returned by Watchdog_control(). + * + * Watchdog_control() returns Watchdog_STATUS_SUCCESS if the control code was + * executed successfully. + */ +#define Watchdog_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by Watchdog_control(). + * + * Watchdog_control() returns Watchdog_STATUS_ERROR if the control code was not + * executed successfully. + */ +#define Watchdog_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by Watchdog_control() for undefined + * command codes. + * + * Watchdog_control() returns Watchdog_STATUS_UNDEFINEDCMD if the control code + * is not recognized by the driver implementation. + */ +#define Watchdog_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned by Watchdog_setReload() for drivers + * which do not support the aforementioned API. + * + * Watchdog_setReload() returns Watchdog_STATUS_UNSUPPORTED if the driver + * implementation does not support the aforementioned API. + */ +#define Watchdog_STATUS_UNSUPPORTED (-3) +/** @}*/ + +/** + * @defgroup Watchdog_CMD Command Codes + * Watchdog_CMD_* macros are general command codes for Watchdog_control(). Not all Watchdog + * driver implementations support these command codes. + * @{ + * @ingroup Watchdog_CONTROL + */ + +/* Add Watchdog_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! +* @brief Watchdog Handle +*/ +typedef struct Watchdog_Config_ *Watchdog_Handle; + +/*! + * @brief Watchdog debug stall settings + * + * This enumeration defines the debug stall modes for the Watchdog. On some + * targets, the Watchdog timer will continue to count down while a debugging + * session is halted. To avoid unwanted resets, the Watchdog can be set to + * stall while the processor is stopped by the debugger. + */ +typedef enum Watchdog_DebugMode_ { + Watchdog_DEBUG_STALL_ON, /*!< Watchdog will be stalled at breakpoints */ + Watchdog_DEBUG_STALL_OFF /*!< Watchdog will keep running at breakpoints */ +} Watchdog_DebugMode; + +/*! + * @brief Watchdog reset mode settings + * + * This enumeration defines the reset modes for the Watchdog. The Watchdog can + * be configured to either generate a reset upon timeout or simply produce a + * periodic interrupt. + */ +typedef enum Watchdog_ResetMode_ { + Watchdog_RESET_OFF, /*!< Timeouts generate interrupts only */ + Watchdog_RESET_ON /*!< Generates reset after timeout */ +} Watchdog_ResetMode; + +/*! + * @brief Watchdog callback pointer + * + * This is the typedef for the function pointer that will allow a callback + * function to be specified in the Watchdog_Params structure. The function + * will take a Watchdog_Handle of the Watchdog causing the interrupt (cast as + * a uintptr_t) as an argument. + */ +typedef void (*Watchdog_Callback)(uintptr_t handle); + +/*! + * @brief Watchdog Parameters + * + * Watchdog parameters are used to with the Watchdog_open() call. Default + * values for these parameters are set using Watchdog_Params_init(). + * + * @sa Watchdog_Params_init() + */ +typedef struct Watchdog_Params_ { + Watchdog_Callback callbackFxn; /*!< Pointer to callback. Not supported + on all targets. */ + Watchdog_ResetMode resetMode; /*!< Mode to enable resets. + Not supported on all targets. */ + Watchdog_DebugMode debugStallMode; /*!< Mode to stall WDT at breakpoints. + Not supported on all targets. */ + void *custom; /*!< Custom argument used by driver + implementation */ +} Watchdog_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_clear(). + */ +typedef void (*Watchdog_ClearFxn) (Watchdog_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_close(). + */ +typedef void (*Watchdog_CloseFxn) (Watchdog_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_control(). + */ +typedef int_fast16_t (*Watchdog_ControlFxn) (Watchdog_Handle handle, + uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_init(). + */ +typedef void (*Watchdog_InitFxn) (Watchdog_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_open(). + */ +typedef Watchdog_Handle (*Watchdog_OpenFxn) (Watchdog_Handle handle, + Watchdog_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_setReload(). + */ +typedef int_fast16_t (*Watchdog_SetReloadFxn)(Watchdog_Handle handle, + uint32_t ticks); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_ConvertMsToTicksFxn(). + */ +typedef uint32_t (*Watchdog_ConvertMsToTicksFxn) (uint32_t milliseconds); + +/*! + * @brief The definition of a Watchdog function table that contains the + * required set of functions to control a specific Watchdog driver + * implementation. + */ +typedef struct Watchdog_FxnTable_ { + Watchdog_ClearFxn watchdogClear; + Watchdog_CloseFxn watchdogClose; + Watchdog_ControlFxn watchdogControl; + Watchdog_InitFxn watchdogInit; + Watchdog_OpenFxn watchdogOpen; + Watchdog_SetReloadFxn watchdogSetReload; + Watchdog_ConvertMsToTicksFxn watchdogConvertMsToTicks; +} Watchdog_FxnTable; + +/*! + * @brief Watchdog Global configuration + * + * The Watchdog_Config structure contains a set of pointers used to + * characterize the Watchdog driver implementation. + * + * This structure needs to be defined before calling Watchdog_init() and + * it must not be changed thereafter. + * + * @sa Watchdog_init() + */ +typedef struct Watchdog_Config_ { + /*! + * Pointer to a table of driver-specific implementations of Watchdog APIs + */ + Watchdog_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} Watchdog_Config; + +/*! + * @brief Clears the Watchdog + * + * Clears the Watchdog to to prevent a reset signal from being generated if the + * module is in Watchdog_RESET_ON reset mode. + * + * @param handle Watchdog Handle + */ +extern void Watchdog_clear(Watchdog_Handle handle); + +/*! + * @brief Function to close a Watchdog peripheral specified by the Watchdog + * handle.It stops (holds) the Watchdog counting on applicable + * platforms. + * + * @pre Watchdog_open() has to be called first. + * + * @param handle A Watchdog_Handle returned from Watchdog_open + * + * @sa Watchdog_open() + */ +extern void Watchdog_close(Watchdog_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * Watchdog_Handle. + * + * Commands for Watchdog_control can originate from Watchdog.h or from implementation + * specific Watchdog*.h (_WatchdogCC26XX.h_, _WatchdogMSP432.h_, etc.. ) files. + * While commands from Watchdog.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific Watchdog*.h files add + * unique driver capabilities but are not API portable across all Watchdog driver + * implementations. + * + * Commands supported by Watchdog.h follow a Watchdog_CMD_\ naming + * convention.
+ * Commands supported by Watchdog*.h follow a Watchdog*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref Watchdog_CMD "Watchdog_control command codes" for command codes. + * + * See @ref Watchdog_STATUS "Watchdog_control return status codes" for status codes. + * + * @pre Watchdog_open() has to be called first. + * + * @param handle A Watchdog handle returned from Watchdog_open() + * + * @param cmd Watchdog.h or Watchdog*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa Watchdog_open() + */ +extern int_fast16_t Watchdog_control(Watchdog_Handle handle, + uint_fast16_t cmd, + void *arg); + +/*! + * @brief Initializes the Watchdog module + * + * The application-provided Watchdog_config must be present before the + * Watchdog_init function is called. The Watchdog_config must be persistent + * and not changed after Watchdog_init is called. This function must be called + * before any of the other Watchdog driver APIs. + */ +extern void Watchdog_init(void); + +/*! + * @brief Opens a Watchdog + * + * Opens a Watchdog object with the index and parameters specified, and + * returns a Watchdog_Handle. + * + * @param index Logical peripheral number for the Watchdog indexed + * into the Watchdog_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A Watchdog_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa Watchdog_init() + * @sa Watchdog_close() + */ +extern Watchdog_Handle Watchdog_open(uint_least8_t index, Watchdog_Params *params); + +/*! + * @brief Function to initialize the Watchdog_Params structure to its defaults + * + * @param params An pointer to Watchdog_Params structure for + * initialization + * + * Default parameters: + * callbackFxn = NULL + * resetMode = Watchdog_RESET_ON + * debugStallMode = Watchdog_DEBUG_STALL_ON + */ +extern void Watchdog_Params_init(Watchdog_Params *params); + +/*! + * @brief Sets the Watchdog reload value + * + * Sets the value from which the Watchdog will countdown after it reaches + * zero. This is how the reload value can be changed after the Watchdog has + * already been opened. The new reload value will be loaded into the Watchdog + * timer when this function is called. Watchdog_setReload is not reentrant. + * For CC13XX/CC26XX, if the parameter 'ticks' is set to zero (0), a Watchdog + * interrupt is immediately generated. + * + * This API is not applicable for all platforms. See the page for your + * specific driver implementation for details. + * + * @param handle Watchdog Handle + * + * @param ticks Value to be loaded into Watchdog timer + * Unit is in Watchdog clock ticks + * + * @return Watchdog_STATUS_SUCCESS if successful, Watchdog_STATUS_UNSUPPORTED + * if driver does not support this API. + */ +extern int_fast16_t Watchdog_setReload(Watchdog_Handle handle, uint32_t ticks); + +/*! + * @brief Converts milliseconds to Watchdog clock ticks + * + * Converts the input value into number of Watchdog clock ticks as close as + * possible. If the converted value exceeds 32 bits, a zero (0) will be + * returned to indicate overflow. The converted value can be used as the + * function parameter 'ticks' in Watchdog_setReload(). + * + * This API is not applicable for all platforms. See the page for your + * specific driver implementation for details. + * + * @param handle Watchdog Handle + * + * @param milliseconds Value to be converted + * + * @return Converted value in number of Watchdog clock ticks + * A value of zero (0) means the converted value exceeds 32 bits + * or that the operation is not supported for the specific device. + * + * @sa Watchdog_setReload() + */ +extern uint32_t Watchdog_convertMsToTicks(Watchdog_Handle handle, uint32_t milliseconds); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Watchdog__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/adc/ADCCC32XX.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/adc/ADCCC32XX.h new file mode 100644 index 000000000..c305ecb0b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/adc/ADCCC32XX.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ADCCC32XX.h + * + * @brief ADC driver implementation for the ADC peripheral on CC32XX + * + * This ADC driver implementation is designed to operate on a CC32XX ADC + * peripheral. The ADCCC32XX header file should be included in an application + * as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref ADC.h for a complete description of APIs & example of use. + * + * ============================================================================ + */ +#ifndef ti_drivers_adc_ADCMSP432__include +#define ti_drivers_adc_ADCMSP432__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include + + +#define ADCCC32XX_PIN_57_CH_0 (ADC_CH_0 << 8) | 0x38 +#define ADCCC32XX_PIN_58_CH_1 (ADC_CH_1 << 8) | 0x39 +#define ADCCC32XX_PIN_59_CH_2 (ADC_CH_2 << 8) | 0x3a +#define ADCCC32XX_PIN_60_CH_3 (ADC_CH_3 << 8) | 0x3b + +/* ADC function table pointer */ +extern const ADC_FxnTable ADCCC32XX_fxnTable; + +/*! + * @brief ADCCC32XX Hardware attributes + * + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC32XXWare these definitions are found in: + * - ti/devices/cc32xx/driverlib/adc.h + * + * A sample structure is shown below: + * @code + * const ADCCC32XX_HWAttrsV1 adcMSP432HWAttrs[Board_ADCCHANNELCOUNT] = { + * { + * .adcPin = ADCCC32XX_PIN_57 + * } + * }; + * @endcode + */ +typedef struct ADCCC32XX_HWAttrsV1 { + uint_fast16_t adcPin; +} ADCCC32XX_HWAttrsV1; + +/*! + * @brief ADCCC32XX_Status + * + * The application must not access any member variables of this structure! + */ +typedef struct ADCCC32XX_Status { + uint_fast32_t baseAddr; + SemaphoreP_Handle adcSemaphore; + uint_least8_t numOpenChannels; +} ADCCC32XX_Status; + +/*! + * @brief ADCCC32XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct ADCCC32XX_Object { + bool isOpen; + bool isProtected; /* Flag to indicate if thread safety is ensured by the driver */ +} ADCCC32XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_adc_ADCMSP432__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/crypto/CryptoCC32XX.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/crypto/CryptoCC32XX.h new file mode 100644 index 000000000..1f35010d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/crypto/CryptoCC32XX.h @@ -0,0 +1,512 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoCC32XX.h + * + * @brief Crypto driver implementation for a CC32XX Crypto controller. + * + * The Crypto header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * + * The CryptoCC32XX driver is used several security methods (AES, DES and HMAC Hash functions). + * This driver provides API for encrypt/decrypt (AES and DES) + * and sign/verify (HMAC hash) + * + * The application initializes the CryptoCC32XX driver by calling CryptoCC32XX_init() + * and is then ready to open a Crypto by calling CryptoCC32XX_open(). + * + * The APIs in this driver serve as an interface to a typical TI-RTOS + * application. The specific peripheral implementations are responsible to + * create all the OSAL specific primitives to allow for thread-safe + * operation. + * + * ## Opening the driver # + * + * @code + * CryptoCC32XX_Handle handle; + * + * handle = CryptoCC32XX_open(CryptoCC32XX_configIndexValue, CryptoCC32XX_AES | + CryptoCC32XX_DES | + CryptoCC32XX_HMAC); + * if (!handle) { + * System_printf("CryptoCC32XX did not open"); + * } + * @endcode + * + * + * ## AES data encryption # + * + * @code + * CryptoCC32XX_EncryptMethod method = desiredMethod; + * CryptoCC32XX_Params params; + * unsigned char plainData[16] = "whatsoever123456"; + * unsigned int plainDataLen = sizeof(plainData); + * unsigned char cipherData[16]; + * unsigned int cipherDataLen; + * + * params.aes.keySize = desiredKeySize; + * params.aes.pKey = (CryptoCC32XX_KeyPtr)desiredKey; // desiredKey length should be as the desiredKeySize + * params.aes.pIV = (void *)pointerToInitVector; + * ret = CryptoCC32XX_encrypt(handle, method , plainData, plainDataLen, cipherData , &cipherDataLen , ¶ms); + * + * @endcode + * + * ## Generate HMAC Hash signature # + * + * @code + * CryptoCC32XX_HmacMethod hmacMethod = desiredHmacMethod; + * CryptoCC32XX_Params params; + * unsigned char dataBuff[] = "whatsoever"; + * unsigned int dataLength = sizeof(dataBuff); + * unsigned char signatureBuff[32]; + * + * params.pKey = pointerToHMACkey; + * params.moreData = 0; + * ret = CryptoCC32XX_sign(handle, hmacMethod , &dataBuff, dataLength, &signatureBuff, ¶ms); + * + * @endcode + * + * # Implementation # + * + * The CryptoCC32XX driver interface module is joined (at link time) to a + * NULL-terminated array of CryptoCC32XX_Config data structures named *CryptoCC32XX_config*. + * *CryptoCC32XX_config* is implemented in the application with each entry being an + * instance of a CryptoCC32XX peripheral. Each entry in *CryptoCC32XX_config* contains a: + * - (void *) data object that is pointed to CryptoCC32XX_Object + * + * + * ============================================================================ + */ + +#ifndef ti_drivers_crypto_CryptoCC32XX__include +#define ti_drivers_crypto_CryptoCC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + + +#include +#include +#include +#include +#include + + +#define CryptoCC32XX_CMD_RESERVED 32 + +#define CryptoCC32XX_STATUS_RESERVED -32 + +/*! + * @brief Successful status code returned by Crypto Common functions. + * + */ +#define CryptoCC32XX_STATUS_SUCCESS 0 + +/*! + * @brief Generic error status code returned by Crypto Common functions. + * + */ +#define CryptoCC32XX_STATUS_ERROR -1 + +/*! + * @brief An error status code returned by Crypto Common functions for undefined + * command codes. + * + */ +#define CryptoCC32XX_STATUS_UNDEFINEDCMD -2 + +/*! + * @brief An error status code returned by CryptoCC32XX_verify for define error in + * verifying a given Hash value. + * + */ +#define CryptoCC32XX_STATUS_ERROR_VERIFY -3 + +/*! + * @brief An error status code returned by Crypto Common functions for define + * cryptographic type not supported. + * + */ +#define CryptoCC32XX_STATUS_ERROR_NOT_SUPPORTED -4 + + +#define CryptoCC32XX_MAX_TYPES 3 + + +/*! + * @brief Cryptography types configuration + * + * This enum defines bitwise Cryptography types. + */ +typedef enum +{ + CryptoCC32XX_AES = 0x01, /*!< Advanced Encryption Standard */ + CryptoCC32XX_DES = 0x02, /*!< Data Encryption Standard */ + CryptoCC32XX_HMAC = 0x04, /*!< Cryptographic hash function */ +}CryptoCC32XX_Type; + +/*! + * @brief AES and DES Cryptography methods configuration + * Keep the Crypto method in the lower 8 bit and + * Crypto type in the upper 8 bits + * + * This enum defines the AES and DES Cryptography modes. + */ +typedef enum +{ + CryptoCC32XX_AES_ECB = (CryptoCC32XX_AES << 8) | 1, /*!< AES Electronic CodeBook */ + CryptoCC32XX_AES_CBC, /*!< AES Cipher Block Chaining */ + CryptoCC32XX_AES_CTR, /*!< AES Counter */ + CryptoCC32XX_AES_ICM, /*!< AES Integer Counter Mode */ + CryptoCC32XX_AES_CFB, /*!< AES Cipher FeedBack */ + CryptoCC32XX_AES_GCM, /*!< AES Galois/Counter Mode */ + CryptoCC32XX_AES_CCM, /*!< AES Counter with CBC-MAC Mode */ + + CryptoCC32XX_DES_ECB = (CryptoCC32XX_DES << 8) | 1, /*!< DES Electronic CodeBook */ + CryptoCC32XX_DES_CBC, /*!< DES Cipher Block Chaining */ + CryptoCC32XX_DES_CFB, /*!< DES Cipher FeedBack */ + +}CryptoCC32XX_EncryptMethod; + +/*! + * @brief HMAC Cryptography methods configuration + * Keep the Crypto method in the lower 8 bit and + * Crypto type in the upper 8 bits + * + * This enum defines the HMAC HASH algorithms modes. + */ +typedef enum +{ + CryptoCC32XX_HMAC_MD5 = (CryptoCC32XX_HMAC << 8) | 1, /*!< MD5 used keyed-hash message authentication code */ + CryptoCC32XX_HMAC_SHA1, /*!< SHA1 used keyed-hash message authentication code */ + CryptoCC32XX_HMAC_SHA224, /*!< SHA224 used keyed-hash message authentication code */ + CryptoCC32XX_HMAC_SHA256 /*!< SHA256 used keyed-hash message authentication code */ + +}CryptoCC32XX_HmacMethod; + +/*! + * @brief AES Cryptography key size type configuration + * + * This enum defines the AES key size types + */ +typedef enum +{ + CryptoCC32XX_AES_KEY_SIZE_128BIT, + CryptoCC32XX_AES_KEY_SIZE_192BIT, + CryptoCC32XX_AES_KEY_SIZE_256BIT + +}CryptoCC32XX_AesKeySize; + +/*! + * @brief DES Cryptography key size type configuration + * + * This enum defines the DES key size types + */ +typedef enum +{ + CryptoCC32XX_DES_KEY_SIZE_SINGLE, + CryptoCC32XX_DES_KEY_SIZE_TRIPLE + +}CryptoCC32XX_DesKeySize; + + +/*! + * @brief AES Additional Authentication Data input parameters + * + * This structure defines the AES Additional Authentication Data input parameters used for + * CryptoCC32XX_AES_GCM and CryptoCC32XX_AES_CCM + */ +typedef struct +{ + uint8_t *pKey2; /*!< pointer to AES second key (CryptoCC32XX_AES_CCM) */ + CryptoCC32XX_AesKeySize key2Size; /*!< AES second Key size type (CryptoCC32XX_AES_CCM) */ + size_t len; /*!< length of the additional authentication data in bytes */ +}CryptoCC32XX_AesAadInputParams; + +/*! + * @brief AES Additional Authentication Data Parameters + * + * This union defines the AES additional authentication parameters used for + * CryptoCC32XX_AES_GCM and CryptoCC32XX_AES_CCM + */ +typedef union +{ + CryptoCC32XX_AesAadInputParams input; /*! + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_dma_UDMACC32XX__include +#define ti_drivers_dma_UDMACC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief UDMA error function pointer + */ +typedef void (*UDMACC32XX_ErrorFxn)(uintptr_t arg); + +/*! + * @brief UDMACC32XX Hardware attributes + * + * This structure contains the base address of the uDMA control + * table, and uDMA error interrupt attributes. + * + * The control table is used by the uDMA controller to store channel + * control structures. The control table can be located anywhere in + * system memory, but must be contiguous and aligned on a 1024-byte boundary. + * + * dmaErrorFxn is the uDMA peripheral's error interrupt handler. + * + * intPriority is priority of the uDMA peripheral's error interrupt, as + * defined by the underlying OS. It is passed unmodified to the + * underlying OS's interrupt handler creation code, so you need to + * refer to the OS documentation for usage. For example, for + * SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi + * documentation for SYS/BIOS usage of interrupt priorities. If the + * driver uses the ti.dpl interface instead of making OS + * calls directly, then the HwiP port handles the interrupt priority + * in an OS specific way. In the case of the SYS/BIOS port, + * intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * + * #include + * + * #if defined(__TI_COMPILER_VERSION__) + * #pragma DATA_ALIGN(dmaControlTable, 1024) + * #elif defined(__IAR_SYSTEMS_ICC__) + * #pragma data_alignment=1024 + * #elif defined(__GNUC__) + * __attribute__ ((aligned (1024))) + * #endif + * + * static tDMAControlTable dmaControlTable[64]; + * + * #include + * + * UDMACC32XX_Object udmaCC32XXObject; + * + * const UDMACC32XX_HWAttrs udmaCC32XXHWAttrs = { + * .controlBaseAddr = (void *)dmaControlTable, + * .dmaErrorFxn = UDMACC32XX_errorFxn, + * .intNum = INT_UDMAERR, + * .intPriority = (~0) + * }; + * @endcode + * + */ +typedef struct UDMACC32XX_HWAttrs { + void *controlBaseAddr; /*!< uDMA control registers base address */ + UDMACC32XX_ErrorFxn dmaErrorFxn; /*!< uDMA error interrupt handler */ + uint8_t intNum; /*!< uDMA error interrupt number */ + uint8_t intPriority; /*!< uDMA error interrupt priority. */ +} UDMACC32XX_HWAttrs; + +/*! + * @brief UDMACC32XX Global configuration + * + * The UDMACC32XX_Config structure contains pointers used by the UDMACC32XX + * driver. + * + * This structure needs to be defined before calling UDMACC32XX_init() and + * it must not be changed thereafter. + */ +typedef struct UDMACC32XX_Config { + void *object; /*!< Pointer to UDMACC32XX object */ + void const *hwAttrs; /*!< Pointer to hardware attributes */ +} UDMACC32XX_Config; + +/*! + * @brief A handle that is returned from a UDMACC32XX_open() call. + */ +typedef struct UDMACC32XX_Config *UDMACC32XX_Handle; + +/*! + * @brief UDMACC32XX object + * + * The application must not access any member variables of this structure! + */ +typedef struct UDMACC32XX_Object { + bool isOpen; /* Flag for open/close status */ + HwiP_Handle hwiHandle; /* DMA error Hwi */ +} UDMACC32XX_Object; + +/*! + * @brief Function to close the DMA driver. + * + * This function releases Power dependency on UDMA that was previously + * set with a call to UDMACC32XX_open(). If there is only one outstanding + * UDMACC32XX_open() call (i.e. all but one UDMACC32XX_open() calls have + * been matched by a corresponding call to UDMACC32XX_close()), this + * function will disable the UDMA. + * + * @pre UDMACC32XX_open() has to be called first. + * Calling context: Task + * + * @param handle A UDMACC32XX_Handle returned from UDMACC32XX_open() + * + * @return none + * + * @sa UDMACC32XX_open + */ +extern void UDMACC32XX_close(UDMACC32XX_Handle handle); + +/*! + * @brief Function to initialize the CC32XX DMA driver + * + * The function will set the isOpen flag to false, and should be called prior + * to opening the DMA driver. + * + * @return none + * + * @sa UDMACC32XX_open() + */ +extern void UDMACC32XX_init(); + +/*! + * @brief Function to initialize the CC32XX DMA peripheral + * + * UDMACC32XX_open() can be called multiple times. Each time the + * function is called, it will set a dependency on the peripheral and + * enable the clock. The Power dependency count on the UDMA will be + * equal to the number of outstanding calls to UDMACC32XX_open(). + * Calling UDMACC32XX_close() will decrement the Power dependency count, + * and the last call to UDMACC32XX_close() will disable the UDMA. + * + * @pre UDMACC32XX_init() has to be called first. + * Calling context: Task + * + * @return UDMACC32XX_Handle on success or NULL if an error has occurred. + * + * @sa UDMACC32XX_close() + */ +extern UDMACC32XX_Handle UDMACC32XX_open(); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_dma_UDMACC32XX__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/ClockP.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/ClockP.h new file mode 100644 index 000000000..e05d0cf87 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/ClockP.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ClockP.h + * + * @brief Clock interface for the RTOS Porting Interface + * + * The ClockP module can be used to schedule functions that run at intervals + * specified in the underlying kernel's system ticks. ClockP instances are + * one-shot. The one-shot function will be run once + * after the specified period has elapsed since calling ClockP_start(). + * + * The ClockP module can also be used to obtain the period of the kernel's + * system tick in microseconds. This is useful for determining the number of + * ticks needed for setting a Clock object's period. + * + * When using the TI-RTOS kernel, ClockP functions are run at software + * interrupt level. With FreeRTOS, the ClockP functions are run by a timer + * service task with priority configured by the application. + * + * A common use case is to post a semaphore in the clock function. There is a + * specific API for this: Semaphore_postFromClock(). This must be used in a + * clock function (instead of Semaphore_post). + * + * ============================================================================ + */ + +#ifndef ti_dpl_ClockP__include +#define ti_dpl_ClockP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Frequency-in-hertz struct + */ +typedef struct ClockP_FreqHz { + uint32_t hi; /*! most significant 32-bits of frequency */ + uint32_t lo; /*! least significant 32-bits of frequency */ +} ClockP_FreqHz; + +/*! + * @brief Status codes for ClockP APIs + */ +typedef enum ClockP_Status { + ClockP_OK = 0, + ClockP_FAILURE = -1 +} ClockP_Status; + +/*! + * @brief Opaque client reference to an instance of a ClockP + * + * A ClockP_Handle returned from the ::ClockP_create represents that instance. + * and then is used in the other instance based functions (e.g. ::ClockP_start, + * ::ClockP_stop, etc.). + */ +typedef void *ClockP_Handle; + +/*! + * @brief Prototype for a ClockP function. + */ +typedef void (*ClockP_Fxn)(uintptr_t arg); + +/*! + * @brief Basic ClockP Parameters + * + * Structure that contains the parameters passed into ::ClockP_create + * when creating a ClockP instance. The ::ClockP_Params_init function should + * be used to initialize the fields to default values before the application sets + * the fields manually. The ClockP default parameters are noted in + * ClockP_Params_init. + */ +typedef struct ClockP_Params { + char *name; /*!< Name of the clock instance. Memory must + persist for the life of the clock instance. + This can be used for debugging purposes, or + set to NULL if not needed. */ + uintptr_t arg; /*!< Argument passed into the clock function. */ +} ClockP_Params; + +/*! + * @brief Function to create a clock object. + * + * @param clockFxn Function called when timeout or period expires. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The ClockP default + * parameters are noted in ::ClockP_Params_init. + * + * @return A ClockP_Handle on success or a NULL on an error. This handle can + * be passed to ClockP_start() + */ +extern ClockP_Handle ClockP_create(ClockP_Fxn clockFxn, + ClockP_Params *params); + +/*! + * @brief Function to delete a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + * + * @return Status of the function. + * - ClockP_OK: Deleted the clock instance + * - ClockP_FAILURE: Timed out waiting to delete the clock object. + */ +extern ClockP_Status ClockP_delete(ClockP_Handle handle); + +/*! + * @brief Get CPU frequency in Hz + * + * @param freq Pointer to the FreqHz structure + */ +extern void ClockP_getCpuFreq(ClockP_FreqHz *freq); + +/*! + * @brief Get the system tick period in microseconds. + * + * @return The kernel's system tick period in microseconds. + */ +extern uint32_t ClockP_getSystemTickPeriod(); + +/*! + * @brief Get the current tick value + * + * The value returned will wrap back to zero after it reaches the max + * value that can be stored in 32 bits. + * + * @return Time in system clock ticks + */ +extern uint32_t ClockP_getSystemTicks(); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * - arg: 0 + * + * @param params Pointer to the instance configuration parameters. + */ +extern void ClockP_Params_init(ClockP_Params *params); + +/*! + * @brief Function to start a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + * + * @param timeout The timeout used for a one-shot clock object. The + * value of timeout must not be 0. + * + * @return Status of the functions + * - ClockP_OK: Scheduled the clock function successfully + * - ClockP_FAILURE: The API failed. + */ +extern ClockP_Status ClockP_start(ClockP_Handle handle, uint32_t timeout); + +/*! + * @brief Function to start a clock from an interrupt. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + * + * @param timeout The timeout used for a one-shot clock object. The + * value of timeout must not be 0. + * + * @return Status of the functions + * - ClockP_OK: Scheduled the clock function successfully + * - ClockP_FAILURE: The API failed. + */ +extern ClockP_Status ClockP_startFromISR(ClockP_Handle handle, uint32_t timeout); + +/*! + * @brief Function to stop a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + * + * It is ok to call ClockP_stop() for a clock that has not been started. + * + * @return Status of the functions + * - ClockP_OK: Stopped the clock function successfully + * - ClockP_FAILURE: The API failed. + */ +extern ClockP_Status ClockP_stop(ClockP_Handle handle); + +/*! + * @brief Function to stop a clock from an interrupt. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + * + * @return Status of the functions + * - ClockP_OK: Stopped the clock function successfully + * - ClockP_FAILURE: The API failed. + */ +extern ClockP_Status ClockP_stopFromISR(ClockP_Handle handle); + +extern ClockP_Status ClockP_timestamp(ClockP_Handle handle); + +/*! + * @brief Set delay in microseconds + * + * @param usec A duration in micro seconds + * + * @return ClockP_OK + */ +extern ClockP_Status ClockP_usleep(uint32_t usec); + +/*! + * @brief Set delay in seconds + * + * @param sec A duration in seconds + * + * @return ClockP_OK + */ +extern ClockP_Status ClockP_sleep(uint32_t sec); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_ClockP__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/ClockP_freertos.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/ClockP_freertos.c new file mode 100644 index 000000000..d73e90a74 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/ClockP_freertos.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== ClockP_freertos.c ======== + */ + +#include +#include +#include + +#include +#include +#include + +static TickType_t ticksToWait = portMAX_DELAY; + +void ClockP_callbackFxn(uintptr_t arg); + +typedef struct ClockP_FreeRTOSObj { + TimerHandle_t timer; + ClockP_Fxn fxn; + uintptr_t arg; +} ClockP_FreeRTOSObj; + +/* + * ======== ClockP_callbackFxn ======== + */ +void ClockP_callbackFxn(uintptr_t arg) +{ + TimerHandle_t handle = (TimerHandle_t)arg; + ClockP_FreeRTOSObj *obj; + + obj = (ClockP_FreeRTOSObj *)pvTimerGetTimerID(handle); + (obj->fxn)(obj->arg); +} + +/* + * ======== ClockP_create ======== + */ +ClockP_Handle ClockP_create(ClockP_Fxn clockFxn, ClockP_Params *params) +{ + ClockP_Params defaultParams; + ClockP_FreeRTOSObj *pObj; + TimerHandle_t handle = NULL; + + if (params == NULL) { + params = &defaultParams; + ClockP_Params_init(&defaultParams); + } + + if ((pObj = pvPortMalloc(sizeof(ClockP_FreeRTOSObj))) == NULL) { + return (NULL); + } + + handle = xTimerCreate(params->name, 1, 0, (void *)pObj, + (TimerCallbackFunction_t)ClockP_callbackFxn); + + if (handle == NULL) { + vPortFree(pObj); + return (NULL); + } + + pObj->timer = handle; + pObj->fxn = clockFxn; + pObj->arg = params->arg; + + return ((ClockP_Handle)pObj); +} + +/* + * ======== ClockP_delete ======== + */ +ClockP_Status ClockP_delete(ClockP_Handle handle) +{ + ClockP_FreeRTOSObj *pObj = (ClockP_FreeRTOSObj *)handle; + BaseType_t status; + + status = xTimerDelete((TimerHandle_t)pObj->timer, ticksToWait); + + if (status != pdPASS) { + return (ClockP_FAILURE); + } + + vPortFree(pObj); + + return (ClockP_OK); +} + +/* + * ======== ClockP_getCpuFreq ======== + */ +void ClockP_getCpuFreq(ClockP_FreqHz *freq) +{ + unsigned long configCpuFreq; + + /* + * configCPU_CLOCK_HZ is #define'd in the target's header file, + * eg, in FreeRTOS/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h. + * Sometimes configCPU_CLOCK_HZ is #define'd to a specific value, + * or to an extern uint32_t variable, eg: + * + * #define configCPU_CLOCK_HZ ( SystemFrequency ) // extern uint32_t + * + * #define configCPU_CLOCK_HZ ( ( unsigned long ) 8000000 ) + */ + + configCpuFreq = (unsigned long)configCPU_CLOCK_HZ; + freq->lo = (uint32_t)configCpuFreq; + freq->hi = 0; +// freq->hi = (uint32_t)(configCpuFreq >> 32); +} + +/* + * ======== ClockP_getSystemTickPeriod ======== + */ +uint32_t ClockP_getSystemTickPeriod() +{ + uint32_t tickPeriodUs; + + /* + * Tick period in microseconds. configTICK_RATE_HZ is defined in the + * application's FreeRTOSConfig.h, which is include by FreeRTOS.h + */ + tickPeriodUs = 1000000 / configTICK_RATE_HZ; + + return (tickPeriodUs); +} + +/* + * ======== ClockP_getSystemTicks ======== + * TODO determine if we ever call this from an ISR + */ +uint32_t ClockP_getSystemTicks() +{ + return ((uint32_t)xTaskGetTickCount()); +} + +/* + * ======== ClockP_Params_init ======== + */ +void ClockP_Params_init(ClockP_Params *params) +{ + params->name = NULL; + params->arg = (uintptr_t)0; +} + +/* + * ======== ClockP_start ======== + */ +ClockP_Status ClockP_start(ClockP_Handle handle, uint32_t timeout) +{ + ClockP_FreeRTOSObj *pObj = (ClockP_FreeRTOSObj *)handle; + BaseType_t status; + + status = xTimerChangePeriod(pObj->timer, (TickType_t)timeout, ticksToWait); + + if (status != pdPASS) { + return (ClockP_FAILURE); + } + status = xTimerStart(pObj->timer, ticksToWait); + + if (status != pdPASS) { + return (ClockP_FAILURE); + } + + return (ClockP_OK); +} + +/* + * ======== ClockP_startFromISR ======== + */ +ClockP_Status ClockP_startFromISR(ClockP_Handle handle, uint32_t timeout) +{ + ClockP_FreeRTOSObj *pObj = (ClockP_FreeRTOSObj *)handle; + BaseType_t xHigherPriorityTaskWoken; + BaseType_t status; + + status = xTimerChangePeriodFromISR(pObj->timer, (TickType_t)timeout, + &xHigherPriorityTaskWoken); + if (status != pdPASS) { + return (ClockP_FAILURE); + } + status = xTimerStartFromISR(pObj->timer, &xHigherPriorityTaskWoken); + + if (status != pdPASS) { + return (ClockP_FAILURE); + } + + return (ClockP_OK); +} + +/* + * ======== ClockP_stop ======== + */ +ClockP_Status ClockP_stop(ClockP_Handle handle) +{ + ClockP_FreeRTOSObj *pObj = (ClockP_FreeRTOSObj *)handle; + BaseType_t status; + + status = xTimerStop(pObj->timer, ticksToWait); + + if (status != pdPASS) { + return (ClockP_FAILURE); + } + return (ClockP_OK); +} + +/* + * ======== ClockP_stopFromISR ======== + */ +ClockP_Status ClockP_stopFromISR(ClockP_Handle handle) +{ + ClockP_FreeRTOSObj *pObj = (ClockP_FreeRTOSObj *)handle; + BaseType_t xHigherPriorityTaskWoken; + BaseType_t status; + + status = xTimerStopFromISR(pObj->timer, &xHigherPriorityTaskWoken); + + if (status != pdPASS) { + return (ClockP_FAILURE); + } + return (ClockP_OK); +} + +/* + * ======== ClockP_sleep ======== + */ +ClockP_Status ClockP_sleep(uint32_t sec) +{ + uint32_t msecs = sec * 1000; + TickType_t xDelay; + + /* Take the ceiling */ + xDelay = (msecs + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS; + + vTaskDelay(xDelay); + + return (ClockP_OK); +} + +/* + * ======== ClockP_usleep ======== + */ +ClockP_Status ClockP_usleep(uint32_t usec) +{ + uint32_t msecs = (usec + 999) / 1000; + TickType_t xDelay; + + /* Take the ceiling */ + xDelay = (msecs + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS; + + vTaskDelay(xDelay); + + return (ClockP_OK); +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/DebugP.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/DebugP.h new file mode 100644 index 000000000..51faa02c3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/DebugP.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file DebugP.h + * + * @brief Debug support + * + * The DebugP module allows application to do logging and assert checking. + * + * DebugP_assert calls can be added into code. If the code + * is compiled with the compiler define DebugP_ASSERT_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_ASSERT_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + * + * This module sits on top of the assert checking of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * Similarly, DebugP_logN calls can be added into code. If the code + * is compiled with the compiler define DebugP_LOG_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_LOG_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + + * This module sits on top of the logging of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * ============================================================================ + */ + +#ifndef ti_dpl_DebugP__include +#define ti_dpl_DebugP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif + +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +#if DebugP_ASSERT_ENABLED +extern void _DebugP_assert(int expression, const char *file, int line); +/*! + * @brief Assert checking function + * + * If the expression is evaluated to true, the API does nothing. + * If it is evaluated to false, the underlying RTOS port implementation + * handles the assert via its mechanisms. + * + * @param expression Expression to evaluate + */ +#define DebugP_assert(expression) (_DebugP_assert(expression, \ + __FILE__, __LINE__)) +#else +#define DebugP_assert(expression) +#endif + +#if DebugP_LOG_ENABLED +/*! + * @brief Debug log function with 0 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + */ +extern void DebugP_log0(const char *format); + +/*! + * @brief Debug log function with 1 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + */ +extern void DebugP_log1(const char *format, uintptr_t p1); + +/*! + * @brief Debug log function with 2 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + */ +extern void DebugP_log2(const char *format, uintptr_t p1, uintptr_t p2); + +/*! + * @brief Debug log function with 3 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + */ +extern void DebugP_log3(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3); + +/*! + * @brief Debug log function with 4 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + * @param p4 fourth parameter to format string + */ +extern void DebugP_log4(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3, uintptr_t p4); +#else +#define DebugP_log0(format) +#define DebugP_log1(format, p1) +#define DebugP_log2(format, p1, p2) +#define DebugP_log3(format, p1, p2, p3) +#define DebugP_log4(format, p1, p2, p3, p4) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_DebugP__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/DebugP_freertos.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/DebugP_freertos.c new file mode 100644 index 000000000..68fb306d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/DebugP_freertos.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== DebugP_freertos.c ======== + */ + +#include +#include +#include + +/* + * ======== _DebugP_assert ======== + */ +void _DebugP_assert(int expression, const char *file, int line) +{ +#if configASSERT_DEFINED + configASSERT(expression); +#endif +} + +/* + * ======== DebugP_log0 ======== + */ +void DebugP_log0(const char *format) +{ +// printf(format); +} + +/* + * ======== DebugP_log1 ======== + */ +void DebugP_log1(const char *format, uintptr_t p1) +{ +// printf(format, p1); +} + +/* + * ======== DebugP_log2 ======== + */ +void DebugP_log2(const char *format, uintptr_t p1, uintptr_t p2) +{ +// printf(format, p1, p2); +} +/* + * ======== DebugP_log3 ======== + */ +void DebugP_log3(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3) +{ +// printf(format, p1, p2, p3); +} +/* + * ======== DebugP_log4 ======== + */ +void DebugP_log4(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3, uintptr_t p4) +{ +// printf(format, p1, p2, p3, p4); +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/FreeRTOS_OSAL_issues.txt b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/FreeRTOS_OSAL_issues.txt new file mode 100644 index 000000000..0e74389ec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/FreeRTOS_OSAL_issues.txt @@ -0,0 +1,6 @@ +1. For UART drivers in blocking mode, the readCancel() and writeCancel() +post the UART object's readSem and writeSem. In FreeRTOS, there doesn't +seem to be a way to know if we're in ISR context or not. In ISR context, +SemOSAL_postFromISR() must be used instead of SemOSAL_post(). +So we'll assume writeCancel() and readCancel() are not being called from +ISR context and use SemOSAL_post(). diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/HwiP.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/HwiP.h new file mode 100644 index 000000000..780b0a72b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/HwiP.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file HwiP.h + * + * @brief Hardware Interrupt module for the RTOS Porting Interface + * + * The ::HwiP_disable/::HwiP_restore APIs can be called recursively. The order + * of the HwiP_restore calls, must be in reversed order. For example: + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_dpl_HwiP__include +#define ti_dpl_HwiP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Opaque client reference to an instance of a HwiP + * + * A HwiP_Handle returned from the ::HwiP_create represents that instance. + */ +typedef void *HwiP_Handle; + +/*! + * @brief Status codes for HwiP APIs + */ +typedef enum HwiP_Status { + HwiP_OK = 0, + HwiP_FAILURE = -1 +} HwiP_Status; + +/*! + * @brief Prototype for the entry function for a hardware interrupt + */ +typedef void (*HwiP_Fxn)(uintptr_t arg); + +/*! + * @brief Basic HwiP Parameters + * + * Structure that contains the parameters passed into ::HwiP_create + * when creating a HwiP instance. The ::HwiP_Params_init function should + * be used to initialize the fields to default values before the application sets + * the fields manually. The HwiP default parameters are noted in + * HwiP_Params_init. + */ +typedef struct HwiP_Params { + char *name; /*!< Name of the clock instance. Memory must + persist for the life of the clock instance. + This can be used for debugging purposes, or + set to NULL if not needed. */ + uintptr_t arg; /*!< Argument passed into the Hwi function. */ + uint32_t priority; /*!< Device specific priority. */ +} HwiP_Params; + +/*! + * @brief Function to clear a single interrupt + * + * @param interruptNum interrupt number to clear + */ +extern void HwiP_clearInterrupt(int interruptNum); + +/*! + * @brief Function to create an interrupt on CortexM devices + * + * @param interruptNum Interrupt Vector Id + * + * @param hwiFxn entry function of the hardware interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The HwiP default + * parameters are noted in ::HwiP_Params_init. + * + * @return A HwiP_Handle on success or a NULL on an error + */ +extern HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, + HwiP_Params *params); + +/*! + * @brief Function to delete an interrupt on CortexM devices + * + * @param handle returned from the HwiP_create call + * + * @return + */ +extern HwiP_Status HwiP_delete(HwiP_Handle handle); + +/*! + * @brief Function to disable interrupts to enter a critical region + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * @return A key that must be passed to HwiP_restore to re-enable interrupts. + */ +extern uintptr_t HwiP_disable(void); + +/*! + * @brief Function to disable a single interrupt + * + * @param interruptNum interrupt number to disable + */ +extern void HwiP_disableInterrupt(int interruptNum); + +/*! + * @brief Function to enable a single interrupt + * + * @param interruptNum interrupt number to enable + */ +extern void HwiP_enableInterrupt(int interruptNum); + +/*! + * @brief Function to return a status based on whether it is in an interrupt + * context. + * + * @return A status: indicating whether the function was called in an + * ISR (true) or at thread level (false). + */ +extern bool HwiP_inISR(void); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * - arg: 0 + * - priority: ~0 + * + * @param params Pointer to the instance configuration parameters. + */ +extern void HwiP_Params_init(HwiP_Params *params); + +/*! + * @brief Function to restore interrupts to exit a critical region + * + * @param key return from HwiP_disable + */ +extern void HwiP_restore(uintptr_t key); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_HwiP__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/HwiPCC32XX_freertos.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/HwiPCC32XX_freertos.c new file mode 100644 index 000000000..551507a27 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/HwiPCC32XX_freertos.c @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== HwiP_freertos.c ======== + * TODO is this the correct license? + * + * Writing an RTOS safe ISR for FreeRTOS is very dependent on the + * microcontroller and tool chain port of FreeRTOS being used. Refer to + * the documentation page and demo application for the RTOS port being used. + */ + +#include +#include +#include +#include +#include + +/* Driver lib includes */ +#include +#include +#include +#include + +#define MAX_INTERRUPTS 256 + + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK (0xFFUL) + +/* + * ======== HwiP_DispatchEntry ======== + */ +typedef struct HwiP_DispatchEntry { + HwiP_Fxn entry; + uintptr_t arg; +} HwiP_DispatchEntry; + +HwiP_DispatchEntry HwiP_dispatchTable[MAX_INTERRUPTS] = {{(HwiP_Fxn)0, 0}}; + +/* + * ======== HwiP_disable ======== + */ +uintptr_t HwiP_disable(void) +{ + uintptr_t key; + + /* + * If we're not in ISR context, use the FreeRTOS macro, since + * it handles nesting. + */ + if ((portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0) { + /* Cannot be called from an ISR! */ + portENTER_CRITICAL(); + key = 0; + } + else { +#ifdef __TI_COMPILER_VERSION__ + key = _set_interrupt_priority(configMAX_SYSCALL_INTERRUPT_PRIORITY); +#else +#if defined(__IAR_SYSTEMS_ICC__) + asm volatile ( +#else /* !__IAR_SYSTEMS_ICC__ */ + __asm__ __volatile__ ( +#endif + "mrs %0, basepri\n\t" + "msr basepri, %1" + : "=&r" (key) + : "r" (configMAX_SYSCALL_INTERRUPT_PRIORITY) + ); +#endif + } + + return (key); +} + +/* + * ======== HwiP_restore ======== + */ +void HwiP_restore(uintptr_t key) +{ + if ((portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0) { + /* Cannot be called from an ISR! */ + portEXIT_CRITICAL(); + } + else { +#ifdef __TI_COMPILER_VERSION__ + _set_interrupt_priority(key); +#else +#if defined(__IAR_SYSTEMS_ICC__) + asm volatile ( +#else /* !__IAR_SYSTEMS_ICC__ */ + __asm__ __volatile__ ( +#endif + "msr basepri, %0" + :: "r" (key) + ); +#endif + } +} + +#ifndef xdc_target__isaCompatible_28 + +typedef struct Hwi_NVIC { + uint32_t RES_00; + uint32_t ICTR; + uint32_t RES_08; + uint32_t RES_0C; + uint32_t STCSR; + uint32_t STRVR; + uint32_t STCVR; + uint32_t STCALIB; + uint32_t RES_20[56]; + uint32_t ISER[8]; + uint32_t RES_120[24]; + uint32_t ICER[8]; + uint32_t RES_1A0[24]; + uint32_t ISPR[8]; + uint32_t RES_220[24]; + uint32_t ICPR[8]; + uint32_t RES_2A0[24]; + uint32_t IABR[8]; + uint32_t RES_320[56]; + uint8_t IPR[240]; + uint32_t RES_4F0[516]; + uint32_t CPUIDBR; + uint32_t ICSR; + uint32_t VTOR; + uint32_t AIRCR; + uint32_t SCR; + uint32_t CCR; + uint8_t SHPR[12]; + uint32_t SHCSR; + uint8_t MMFSR; + uint8_t BFSR; + uint16_t UFSR; + uint32_t HFSR; + uint32_t DFSR; + uint32_t MMAR; + uint32_t BFAR; + uint32_t AFSR; + uint32_t PFR0; + uint32_t PFR1; + uint32_t DFR0; + uint32_t AFR0; + uint32_t MMFR0; + uint32_t MMFR1; + uint32_t MMFR2; + uint32_t MMFR3; + uint32_t ISAR0; + uint32_t ISAR1; + uint32_t ISAR2; + uint32_t ISAR3; + uint32_t ISAR4; + uint32_t RES_D74[5]; + uint32_t CPACR; + uint32_t RES_D8C[93]; + uint32_t STI; + uint32_t RES_F04[12]; + uint32_t FPCCR; + uint32_t FPCAR; + uint32_t FPDSCR; + uint32_t MVFR0; + uint32_t MVFR1; + uint32_t RES_F48[34]; + uint32_t PID4; + uint32_t PID5; + uint32_t PID6; + uint32_t PID7; + uint32_t PID0; + uint32_t PID1; + uint32_t PID2; + uint32_t PID3; + uint32_t CID0; + uint32_t CID1; + uint32_t CID2; + uint32_t CID3; +} Hwi_NVIC; + +/* + * ======== HwiP_clearInterrupt ======== + */ +void HwiP_clearInterrupt(int interruptNum) +{ + // TODO: Should driverlib functions be prefixed with MAP_? + IntPendClear((unsigned long)interruptNum); +} + +/* + * ======== HwiP_delete ======== + */ +HwiP_Status HwiP_delete(HwiP_Handle handle) +{ + IntDisable((int)handle); + IntUnregister((int)handle); + + return (HwiP_OK); +} + +/* + * ======== HwiP_disableInterrupt ======== + */ +void HwiP_disableInterrupt(int interruptNum) +{ + IntDisable(interruptNum); +} + +/* + * ======== HwiP_dispatch ======== + */ +void HwiP_dispatch(void) +{ + uint32_t intNum; + Hwi_NVIC *Hwi_nvic = (Hwi_NVIC *)0xE000E000; + HwiP_DispatchEntry hwi; + + /* Determine which interrupt has fired */ + intNum = (Hwi_nvic->ICSR & 0x000000ff); + hwi = HwiP_dispatchTable[intNum]; + if (hwi.entry) { + (hwi.entry)(hwi.arg); + taskYIELD(); + } +} + +/* + * ======== HwiP_enableInterrupt ======== + */ +void HwiP_enableInterrupt(int interruptNum) +{ + IntEnable(interruptNum); +} + +/* + * ======== HwiP_create ======== + */ +HwiP_Handle HwiP_create(int interruptNum, + HwiP_Fxn hwiFxn, + HwiP_Params *params) +{ + HwiP_Params defaultParams; + + if (params == NULL) { + params = &defaultParams; + HwiP_Params_init(&defaultParams); + } + + HwiP_dispatchTable[interruptNum].entry = hwiFxn; + HwiP_dispatchTable[interruptNum].arg = params->arg; + + // TODO: Should driverlib functions be prefixed with MAP_? + IntRegister(interruptNum, (void(*)(void))HwiP_dispatch); + IntPrioritySet(interruptNum, params->priority); + IntEnable(interruptNum); + + return ((HwiP_Handle)interruptNum); +} + +/* + * ======== HwiP_inISR ======== + */ +bool HwiP_inISR(void) +{ + bool stat; + + if ((portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0) { + /* Not currently in an ISR */ + stat = false; + } + else { + stat = true; + } + + return (stat); +} + +/* + * ======== HwiP_Params_init ======== + */ +void HwiP_Params_init(HwiP_Params *params) +{ + params->name = NULL; + params->arg = 0; + params->priority = ~0; +} + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/MutexP.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/MutexP.h new file mode 100644 index 000000000..5bf54f1f9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/MutexP.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file MutexP.h + * + * @brief Mutex module for the RTOS Porting Interface + * + * The MutexP module allows task to maintain critical region segments. The + * MutexP module has two main functions: ::MutexP_lock and ::MutexP_unlock. + * + * The MutexP module supports recursive calls to the MutexP_lock API by a + * single task. The same number of MutexP_unlock calls must be done for the + * mutex to be release. Note: the returned key must be provided in the LIFO + * order. For example: + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_lock(key2); + * MutexP_lock(key1); + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_dpl_MutexP__include +#define ti_dpl_MutexP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Status codes for MutexP APIs + */ +typedef enum MutexP_Status { + /*! API completed successfully */ + MutexP_OK = 0, + /*! API failed */ + MutexP_FAILURE = -1 +} MutexP_Status; + +/*! + * @brief Opaque client reference to an instance of a MutexP + * + * A MutexP_Handle returned from the ::MutexP_create represents that instance. + * and then is used in the other instance based functions (e.g. ::MutexP_lock, + * ::MutexP_unlock, etc.). + */ +typedef void *MutexP_Handle; + +/*! + * @brief Basic MutexP Parameters + * + * Structure that contains the parameters are passed into ::MutexP_create + * when creating a MutexP instance. The ::MutexP_Params_init function should + * be used to initialize the fields to default values before the application + * sets the fields manually. The MutexP default parameters are noted in + * ::MutexP_Params_init. + */ +typedef struct MutexP_Params { + char *name; /*!< Name of the mutex instance. Memory must persist + for the life of the mutex instance */ + void (*callback)(void); /*!< Callback while waiting for mutex unlock */ +} MutexP_Params; + + +/*! + * @brief Function to create a mutex. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The MutexP default + * parameters are noted in ::MutexP_Params_init. + * + * @return A MutexP_Handle on success or a NULL on an error + */ +extern MutexP_Handle MutexP_create(MutexP_Params *params); + +/*! + * @brief Function to delete a mutex. + * + * @param handle A MutexP_Handle returned from MutexP_create + * + * @return Status of the functions + * - MutexP_OK: Deleted the mutex instance + * - MutexP_FAILED: Failed to delete the mutex instance + */ +extern MutexP_Status MutexP_delete(MutexP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void MutexP_Params_init(MutexP_Params *params); + +/*! + * @brief Function to lock a mutex. + * + * This function can only be called from a Task. It cannot be called from + * an interrupt. The lock will block until the mutex is available. + * + * Users of a mutex should make every attempt to minimize the duration that + * that they have it locked. This is to minimize latency. It is recommended + * that the users of the mutex do not block while they have the mutex locked. + * + * This function unlocks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @return A key is returned. This key must be passed into ::MutexP_unlock. + */ +extern uintptr_t MutexP_lock(MutexP_Handle handle); + +/*! + * @brief Function to unlock a mutex + * + * This function unlocks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. The order of + * the keys must be reversed. For example + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_lock(key2); + * MutexP_lock(key1); + * @endcode + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @param key Return from ::MutexP_lock. + */ +extern void MutexP_unlock(MutexP_Handle handle, uintptr_t key); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_MutexP__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/MutexP_freertos.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/MutexP_freertos.c new file mode 100644 index 000000000..3c389e975 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/MutexP_freertos.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== MutexP_freertos.c ======== + */ + +#include + +#include +#include +#include + + +/* + * ======== MutexP_create ======== + */ +MutexP_Handle MutexP_create(MutexP_Params *params) +{ + SemaphoreHandle_t sem = NULL; + + /* + * NOTE: Documentation in semphr.h says that configUSE_RECURSIVE_MUTEXES + * must be set to 1 in FreeRTOSConfig.h for this to be available, but + * the xSemaphore recursive calls are inside a configUSE_RECURSIVE_MUTEXES + * block. + */ + sem = xSemaphoreCreateRecursiveMutex(); + + return ((MutexP_Handle)sem); +} + +/* + * ======== MutexP_delete ======== + */ +MutexP_Status MutexP_delete(MutexP_Handle handle) +{ + vSemaphoreDelete((SemaphoreHandle_t)handle); + + return (MutexP_OK); +} + +/* + * ======== MutexP_lock ======== + */ +uintptr_t MutexP_lock(MutexP_Handle handle) +{ + SemaphoreHandle_t xMutex = (SemaphoreHandle_t)handle; + + /* Retry every 10 ticks */ + while (xSemaphoreTakeRecursive(xMutex, (TickType_t)10) == pdFALSE) { + ; + } + + return (0); +} + +/* + * ======== MutexP_Params_init ======== + */ +void MutexP_Params_init(MutexP_Params *params) +{ + params->name = NULL; + params->callback = NULL; +} + +/* + * ======== MutexP_unlock ======== + */ +void MutexP_unlock(MutexP_Handle handle, uintptr_t key) +{ + SemaphoreHandle_t xMutex = (SemaphoreHandle_t)handle; + xSemaphoreGiveRecursive(xMutex); +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/PowerCC32XX_freertos.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/PowerCC32XX_freertos.c new file mode 100644 index 000000000..deffcf3b8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/PowerCC32XX_freertos.c @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== PowerCC32XX_freertos.c ======== + */ + +#include + +/* driverlib header files */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +/* bitmask of constraints that disallow LPDS */ +#define LPDS_DISALLOWED (1 << PowerCC32XX_DISALLOW_LPDS) + +/* macro to pick two matching count values */ +#define COUNT_WITHIN_TRESHOLD(a, b, c, th) \ + ((((b) - (a)) <= (th)) ? (b) : (c)) + +#define TRUE 1 +#define FALSE 0 + + +static volatile uint32_t idleTime = 0; + +void PowerCC32XX_sleepPolicy() +{ +#if (configUSE_TICKLESS_IDLE != 0) + int i = 0; + bool returnFromSleep = FALSE; + unsigned long constraintMask; + unsigned long long ullLowPowerTimeBeforeSleep, ullLowPowerTimeAfterSleep; + unsigned long long count[3]; + unsigned long long ullSleepTime; + unsigned long long time; + unsigned long long remain; + eSleepModeStatus eSleepStatus; + + /* + * Enter a critical section that will not effect interrupts + * bringing the MCU out of sleep mode. + */ + vPortEnterCritical(); + + /* query the declared constraints */ + constraintMask = Power_getConstraintMask(); + + /* check if we are allowed to go to LPDS */ + if ((constraintMask & LPDS_DISALLOWED) == 0) { + /* + * Read the current time from a time source that will remain + * operational while the microcontroller is in a low power state. + */ + /* + * Get the current RTC count, using the fast interface; to use the + * fast interface the count must be read three times, and then + * the value that matches on at least two of the reads is chosen + */ + for (i = 0; i < 3; i++) { + count[i] = MAP_PRCMSlowClkCtrFastGet(); + } + ullLowPowerTimeBeforeSleep = + COUNT_WITHIN_TRESHOLD(count[0], count[1], count[2], 1); + + /* Stop the timer that is generating the tick interrupt. */ + MAP_SysTickDisable(); + + /* Ensure it is still ok to enter the sleep mode. */ + eSleepStatus = eTaskConfirmSleepModeStatus(); + + if (eSleepStatus == eAbortSleep ) { + /* + * A task has been moved out of the Blocked state since this + * macro was executed, or a context siwth is being held pending. + * Do not enter a sleep state. Restart the tick and exit the + * critical section. + */ + MAP_SysTickEnable(); + vPortExitCritical(); + + returnFromSleep = FALSE; + } + else { + /* convert ticks to microseconds */ + time = idleTime * ClockP_getSystemTickPeriod(); + + /* check if can go to LPDS */ + if (time > Power_getTransitionLatency(PowerCC32XX_LPDS, + Power_TOTAL)) { + remain = ((time - PowerCC32XX_TOTALTIMELPDS) * 32768) / 1000000; + + /* set the LPDS wakeup time interval */ + MAP_PRCMLPDSIntervalSet(remain); + + /* enable the wake source to be timer */ + MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_TIMER); + + /* go to LPDS mode */ + Power_sleep(PowerCC32XX_LPDS); + + /* set 'returnFromSleep' to TRUE*/ + returnFromSleep = TRUE; + } + else { + MAP_SysTickEnable(); + vPortExitCritical(); + + returnFromSleep = FALSE; + } + } + } + else { + /* A constraint was set */ + vPortExitCritical(); + } + + if (returnFromSleep) { + /* + * Determine how long the microcontroller was actually in a low + * power state for, which will be less than xExpectedIdleTime if the + * microcontroller was brought out of low power mode by an interrupt + * other than that configured by the vSetWakeTimeInterrupt() call. + * Note that the scheduler is suspended before + * portSUPPRESS_TICKS_AND_SLEEP() is called, and resumed when + * portSUPPRESS_TICKS_AND_SLEEP() returns. Therefore no other + * tasks will execute until this function completes. + */ + for (i = 0; i < 3; i++) { + count[i] = MAP_PRCMSlowClkCtrFastGet(); + } + ullLowPowerTimeAfterSleep = + COUNT_WITHIN_TRESHOLD(count[0], count[1], count[2], 1); + + ullSleepTime = ullLowPowerTimeAfterSleep - ullLowPowerTimeBeforeSleep; + + ullSleepTime = ullSleepTime*1000; + ullSleepTime = ullSleepTime/32768; + + /* + * Correct the kernels tick count to account for the time the + * microcontroller spent in its low power state. + */ + vTaskStepTick((unsigned long)ullSleepTime); + + /* Restart the timer that is generating the tick interrupt. */ + MAP_SysTickEnable(); + + /* + * Exit the critical section - it might be possible to do this + * immediately after the prvSleep() calls. + */ + vPortExitCritical(); + } + else { + MAP_PRCMSleepEnter(); + } +#endif +} + +/* + * ======== PowerCC32XX_initPolicy ======== + */ +void PowerCC32XX_initPolicy() +{ +} + +/* Tickless Hook */ +void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) +{ +#if (configUSE_TICKLESS_IDLE != 0) + idleTime = xExpectedIdleTime; + Power_idleFunc(); +#endif +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SemaphoreP.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SemaphoreP.h new file mode 100644 index 000000000..ba44f4a66 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SemaphoreP.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SemaphoreP.h + * + * @brief Semaphore module for the RTOS Porting Interface + * + * Semaphores can be counting semaphores or binary semaphores. Counting + * semaphores keep track of the number of times the semaphore has been posted + * with post functions. This is useful, for example, if you have a group of + * resources that are shared between tasks. Such tasks might call pend() to see + * if a resource is available before using one. A count of zero for a counting + * semaphore denotes that it is not available. A positive count denotes + * how many times a SemaphoreP_pend can be called before it is blocked (or + * returns SemaphoreP_TIMEOUT). + * + * Binary semaphores can have only two states: available (count = 1) and + * unavailable (count = 0). They can be used to share a single resource + * between tasks. They can also be used for a basic signalling mechanism, where + * the semaphore can be posted multiple times. Binary semaphores do not keep + * track of the count; they simply track whether the semaphore has been posted + * or not. + * + * ============================================================================ + */ + +#ifndef ti_dpl_SemaphoreP__include +#define ti_dpl_SemaphoreP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Status codes for SemaphoreP APIs + */ +typedef enum SemaphoreP_Status { + /*! API completed successfully */ + SemaphoreP_OK = 0, + /*! API failed */ + SemaphoreP_FAILURE = -1, + /*! API failed because of a timeout */ + SemaphoreP_TIMEOUT = -2 +} SemaphoreP_Status; + +/*! + * @brief Wait forever define + */ +#define SemaphoreP_WAIT_FOREVER ~(0) + +/*! + * @brief No wait define + */ +#define SemaphoreP_NO_WAIT (0) + +/*! + * @brief Opaque client reference to an instance of a SemaphoreP + * + * A SemaphoreP_Handle returned from the ::SemaphoreP_create represents that + * instance and is used in the other instance based functions (e.g. + * ::SemaphoreP_post or ::SemaphoreP_pend, etc.). + */ +typedef void *SemaphoreP_Handle; + +/*! + * @brief Mode of the semaphore + */ +typedef enum SemaphoreP_Mode { + SemaphoreP_Mode_COUNTING = 0x0, + SemaphoreP_Mode_BINARY = 0x1 +} SemaphoreP_Mode; + +/*! + * @brief Basic SemaphoreP Parameters + * + * Structure that contains the parameters are passed into ::SemaphoreP_create + * when creating a SemaphoreP instance. The ::SemaphoreP_Params_init function + * should be used to initialize the fields to default values before the + * application sets the fields manually. The SemaphoreP default parameters are + * noted in SemaphoreP_Params_init. + */ +typedef struct SemaphoreP_Params { + char *name; /*!< Name of the semaphore instance. Memory must + persist for the life of the semaphore instance */ + SemaphoreP_Mode mode; /*!< Mode for the semaphore */ + uint32_t maxCount; /*!< The max count allowed for counting semaphore */ + void (*callback)(void); /*!< Callback while pending for semaphore post */ +} SemaphoreP_Params; + +/*! + * @brief Function to create a semaphore. + * + * @param count Initial count of the semaphore. For binary semaphores, + * only values of 0 or 1 are valid. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters (SemaphoreP default + * parameters as noted in ::SemaphoreP_Params_init. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_create(unsigned int count, + SemaphoreP_Params *params); + +/*! + * @brief Function to delete a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + * + * @return Status of the functions + * - SemaphoreP_OK: Deleted the semaphore instance + * - SemaphoreP_FAILED: Failed to delete the semaphore instance + */ +extern SemaphoreP_Status SemaphoreP_delete(SemaphoreP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - mode: SemaphoreP_Mode_COUNTING + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void SemaphoreP_Params_init(SemaphoreP_Params *params); + +/*! + * @brief Function to pend (wait) on a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + * + * @param timeout Timeout (in milliseconds) to wait for the semaphore to + * be posted (signalled). + * + * @return Status of the functions + * - SemaphoreP_OK: Obtain the semaphore + * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained. + * - SemaphoreP_FAILED: Non-time out failure. + */ +extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, + uint32_t timeout); + +/*! + * @brief Function to post (signal) a semaphore from task of ISR context. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + * + * @return Status of the functions + * - SemaphoreP_OK: Released the semaphore + * - SemaphoreP_FAILED: Failed to post the semaphore + */ +extern SemaphoreP_Status SemaphoreP_post(SemaphoreP_Handle handle); + +/*! + * @brief Function to post (signal) a semaphore from an ClockP function. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + * + * @return Status of the functions + * - SemaphoreP_OK: Released the semaphore + * - SemaphoreP_FAILED: Failed to post the semaphore + */ +extern SemaphoreP_Status SemaphoreP_postFromClock(SemaphoreP_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SemaphoreP__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SemaphoreP_freertos.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SemaphoreP_freertos.c new file mode 100644 index 000000000..d8c0db000 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SemaphoreP_freertos.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== SemaphoreP_freertos.c ======== + */ + +#include +#include + +#include +#include +#include + +/* + * ======== SemaphoreP_create ======== + */ +SemaphoreP_Handle SemaphoreP_create(unsigned int count, + SemaphoreP_Params *params) +{ + SemaphoreHandle_t sem = NULL; + SemaphoreP_Params semParams; + + if (params == NULL) { + params = &semParams; + SemaphoreP_Params_init(params); + } + + if (params->mode == SemaphoreP_Mode_COUNTING) { +#if (configUSE_COUNTING_SEMAPHORES == 1) + sem = xSemaphoreCreateCounting((UBaseType_t)params->maxCount, + (UBaseType_t)count); +#endif + } + else { + sem = xSemaphoreCreateBinary(); + if (count != 0) { + xSemaphoreGive(sem); + } + } + + return ((SemaphoreP_Handle)sem); +} + +/* + * ======== SemaphoreP_delete ======== + */ +SemaphoreP_Status SemaphoreP_delete(SemaphoreP_Handle handle) +{ + vSemaphoreDelete((SemaphoreHandle_t)handle); + return (SemaphoreP_OK); +} + +/* + * ======== SemaphoreP_Params_init ======== + */ +void SemaphoreP_Params_init(SemaphoreP_Params *params) +{ + params->mode = SemaphoreP_Mode_BINARY; + params->name = NULL; + params->maxCount = 1; + params->callback = NULL; +} + +/* + * ======== SemaphoreP_pend ======== + */ +SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout) +{ + BaseType_t status; + uint32_t ticks; + uint32_t tickRateMS; + + if (timeout == SemaphoreP_WAIT_FOREVER) { + ticks = portMAX_DELAY; + } + else { + tickRateMS = (configTICK_RATE_HZ / 1000); + /* + * Don't wait if tick rate resolution is greater than 1ms and + * prevent potential division by 0 when calculating the ticks to + * delay. + */ + if (tickRateMS == 0) { + ticks = 0; + } + else { + ticks = (timeout / tickRateMS); + } + } + + status = xSemaphoreTake((SemaphoreHandle_t)handle, ticks); + + if (status == pdTRUE) { + return (SemaphoreP_OK); + } + + return (SemaphoreP_TIMEOUT); +} + +/* + * ======== SemaphoreP_post ======== + */ +SemaphoreP_Status SemaphoreP_post(SemaphoreP_Handle handle) +{ + BaseType_t xHigherPriorityTaskWoken; + BaseType_t result; + SemaphoreP_Status status; + + if (!HwiP_inISR()) { + /* Not in ISR */ + xSemaphoreGive((SemaphoreHandle_t)handle); + status = SemaphoreP_OK; + } + else { + result = xSemaphoreGiveFromISR((SemaphoreHandle_t)handle, + &xHigherPriorityTaskWoken); + + if (result == pdTRUE) { + status = SemaphoreP_OK; + } + else { + /* The queue is full */ + status = SemaphoreP_FAILURE; + } + } + return (status); +} + +/* + * ======== SemaphoreP_postFromClock ======== + */ +SemaphoreP_Status SemaphoreP_postFromClock(SemaphoreP_Handle handle) +{ + return (SemaphoreP_post(handle)); +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SystemP.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SystemP.h new file mode 100644 index 000000000..b5aa4c1ae --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SystemP.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** =========================================================================== + * @file SystemP.h + * + * @brief System module for the RTOS Porting Interface + * + * Basic system services for supporting printf-like output. + * + * =========================================================================== + */ + +#ifndef ti_dpl_SystemP__include +#define ti_dpl_SystemP__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern int SystemP_snprintf(char *buf, size_t n, const char *format,...); +extern int SystemP_vsnprintf(char *buf, size_t n, const char *format, va_list va); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SemaphoreP__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SystemP_freertos.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SystemP_freertos.c new file mode 100644 index 000000000..47fc077a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/dpl/SystemP_freertos.c @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== SystemP_freertos.c ======== + */ +#include + +#include +#include +#include +#include +#include +#include + +/* ----------------------------------------------------------------------------- + * Constants and macros + * ----------------------------------------------------------------------------- + */ +#ifndef MIN +# define MIN(n, m) (((n) > (m)) ? (m) : (n)) +#endif + +/* + * ======== OUTMAX ======== + * The maximum length of the output of a base 8 number produced by formatNum + * plus 5 to accomodate the decimal point and 4 digits after the decimal + * point. + */ +#define OUTMAX ((32 + 2) / 3) + 5 +#define PTRZPAD 8 +#define MAXARGS 5 + +/* ---------------------------------------------------------------------------- + * Type definitions + * ---------------------------------------------------------------------------- + */ +/* ParseData */ +typedef struct ParseData { + int width; + bool lFlag; + bool lJust; + int precis; + int len; + int zpad; + char *end; + char *ptr; +} ParseData; + +/* + * Maximum sized (un)signed integer that we'll format. + */ +typedef uint32_t UNum; +typedef int32_t INum; +typedef UNum UIntMax; +typedef INum IntMax; + +static int doPrint(char *buf, size_t n, const char *fmt, va_list va); +static char *formatNum(char *ptr, UIntMax un, int zpad, int base); +static void putChar(char **bufp, char c, size_t *n); + +/* + * ======== SystemP_snprintf ======== + */ +int SystemP_snprintf(char *buf, size_t n, const char *format,...) +{ + va_list args; + int ret; + + va_start(args, format); + ret = doPrint(buf, n, format, args); + va_end(args); + + return (ret); +} + +/* + * ======== SystemP_snprintf_va ======== + */ +int SystemP_vsnprintf(char *buf, size_t n, const char *format, + va_list va) +{ + int ret; + + ret = doPrint(buf, n, format, va); + return (ret); +} + +/* + * ======== doPrint ======== + */ +static int doPrint(char *buf, size_t n, const char *fmt, va_list va) +{ + ParseData parse; + int base; + char c; + int res = 0; + char outbuf[OUTMAX]; + + if (fmt == (char *)NULL) { + return (res); + } + + while ((c = *fmt++) != '\0') { + if (c != '%') { + putChar(&buf, c, &n); + res++; + } + else { + c = *fmt++; + /* check for - flag (pad on right) */ + if (c == '-') { + parse.lJust = true; + c = *fmt++; + } + else { + parse.lJust = false; + } + /* check for leading 0 pad */ + if (c == '0') { + parse.zpad = 1; + c = *fmt++; + } + else { + parse.zpad = 0; + } + + /* allow optional field width/precision specification */ + parse.width = 0; + parse.precis = -1; + + /* note: dont use isdigit (very large for C30) */ + if (c == '*') { + /* Width is specified in argument, not in format string */ + parse.width = (int)va_arg(va, int); + + c = *fmt++; + if (parse.width < 0) { + parse.lJust = true; + parse.width = -parse.width; + } + } + else { + while (c >= '0' && c <= '9') { + parse.width = parse.width * 10 + c - '0'; + c = *fmt++; + } + } + + /* allow optional field precision specification */ + if (c == '.') { + parse.precis = 0; + c = *fmt++; + if (c == '*') { + /* Width specified in argument, not in format string */ + parse.precis = (int)va_arg(va, int); + + if (parse.precis < 0) { + parse.precis = 0; + } + c = *fmt++; + } + else { + while (c >= '0' && c <= '9') { + parse.precis = parse.precis * 10 + c - '0'; + c = *fmt++; + } + } + } + + /* setup for leading zero padding */ + if (parse.zpad) { + parse.zpad = parse.width; + } + + /* check for presence of l flag (e.g., %ld) */ + if (c == 'l' || c == 'L') { + parse.lFlag = true; + c = *fmt++; + } + else { + parse.lFlag = false; + } + + parse.ptr = outbuf; + parse.end = outbuf + OUTMAX; + parse.len = 0; + + if (c == 'd' || c == 'i') { + /* signed decimal */ + IntMax val = (IntMax)va_arg(va, int32_t); + + if (parse.precis > parse.zpad) { + parse.zpad = parse.precis; + } + parse.ptr = formatNum(parse.end, val, parse.zpad, -10); + parse.len = parse.end - parse.ptr; + } + /* use comma operator to optimize code generation! */ + else if (((base = 10), (c == 'u')) || /* unsigned decimal */ + ((base = 16), (c == 'x')) || /* unsigned hex */ + ((base = 8), (c == 'o'))) { /* unsigned octal */ + + UIntMax val = (UIntMax)va_arg(va, uint32_t) ; + + if (parse.precis > parse.zpad) { + parse.zpad = parse.precis; + } + parse.ptr = formatNum(parse.end, val, parse.zpad, base); + parse.len = parse.end - parse.ptr; + } + else if ((base = 16), (c == 'p')) { + parse.zpad = PTRZPAD; /* ptrs are 0 padded */ + parse.ptr = formatNum( + parse.end, + (UIntMax)va_arg(va, uint32_t), + parse.zpad, base); + *(--parse.ptr) = '@'; + parse.len = parse.end - parse.ptr; + } + else if (c == 'c') { + /* character */ + *parse.ptr = (char)va_arg(va, int); + parse.len = 1; + } + else if (c == 's') { + /* string */ + parse.ptr = (char *)va_arg(va, void *); + + /* substitute (null) for NULL pointer */ + if (parse.ptr == (char *)NULL) { + parse.ptr = "(null)"; + } + parse.len = strlen(parse.ptr); + if (parse.precis != -1 && parse.precis < parse.len) { + parse.len = parse.precis; + } + } + else if (c == 'f') { + double d, tmp; + bool negative = false; + UNum fract; + + d = va_arg(va, double); + + if (d < 0.0) { + d = -d; + negative = true; + parse.zpad--; + } + + /* + * Assumes four digits after decimal point. We are using a + * temporary double variable to force double-precision + * computations without using --fp_mode=strict flag. + * See the description of that flag in the compiler's doc + * for a further explanation. + */ + tmp = (d - (INum)d) * 1e4; + fract = (UNum)tmp; + + parse.ptr = formatNum(parse.end, fract, 4, 10); + *(--parse.ptr) = '.'; + + parse.len = parse.end - parse.ptr; + /* format integer part (right to left!) */ + parse.ptr = formatNum(parse.ptr, (INum)d, + parse.zpad - parse.len, 10); + if (negative) { + *(--parse.ptr) = '-'; + } + + parse.len = parse.end - parse.ptr; + } + + /* compute number of characters left in field */ + parse.width -= parse.len; + + if (!parse.lJust) { + /* pad with blanks on left */ + while (--parse.width >= 0) { + putChar(&buf, ' ', &n); + res++; + } + } + + /* output number, character or string */ + while (parse.len--) { + putChar(&buf, *parse.ptr++, &n); + res++; + } + /* pad with blanks on right */ + if (parse.lJust) { + while (--parse.width >= 0) { + putChar(&buf, ' ', &n); + res++; + } + } + } /* if */ + } /* while */ + + if (buf) { + *buf = '\0'; + } + + return (res); +} + + +/* + * ======== formatNum ======== + * Internal function + * + * Format unsigned long number in specified base, returning pointer to + * converted output. + * + * Note: ptr points PAST end of the buffer, and is decremented as digits + * are converted from right to left! + * + * Note: base is negative if n is signed else n unsigned! + * + * ptr - Pointer to the end of the working buffer where the string version + * of the number will be placed. + * un - The unsigned number to be formated + * base - The base to format the number into. TODO - signed? + */ +static char *formatNum(char *ptr, UIntMax un, int zpad, int base) +{ + int i = 0; + char sign = 0; + + UIntMax n; + n = un; + + if (base < 0) { + /* handle signed long case */ + base = -base; + if ((IntMax)n < 0) { + n = -(IntMax)n; + + /* account for sign '-': ok since zpad is signed */ + --zpad; + sign = '-'; + } + } + + /* compute digits in number from right to left */ + do { + *(--ptr) = "0123456789abcdef"[(int)(n % base)]; + n = n / base; + ++i; + } while (n); + + /* pad with leading 0s on left */ + while (i < zpad) { + *(--ptr) = '0'; + ++i; + } + + /* add sign indicator */ + if (sign) { + *(--ptr) = sign; + } + return (ptr); +} + +/* + * ======== putChar ======== + * Write character `c` to the buffer and the buffer pointer. + * + * Keeps track of the number of characters written into the buffer by + * modifying bufsize `n`. Atmost, `n` - 1 characters are written. + */ +static void putChar(char **bufp, char c, size_t *n) +{ + /* if the size == 1, don't write so we can '\0' terminate buffer */ + if ((*n) <= 1) { + return; + } + + /* decrement n to keep track of the number of chars written */ + (*n)--; + *((*bufp)++) = c; +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/gpio/GPIOCC32XX.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/gpio/GPIOCC32XX.c new file mode 100644 index 000000000..66c254662 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/gpio/GPIOCC32XX.c @@ -0,0 +1,691 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#if defined(__IAR_SYSTEMS_ICC__) +#include +#endif + +/* + * By default disable both asserts and log for this module. + * This must be done before DebugP.h is included. + */ +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +#include +#include +#include +#include +#include +#include + +/* driverlib header files */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Map GPIO_INT types to corresponding CC32XX interrupt options + */ +static const uint8_t interruptType[] = { + 0, /* Undefined interrupt type */ + GPIO_FALLING_EDGE, /* 1 = Interrupt on falling edge */ + GPIO_RISING_EDGE, /* 2 = Interrupt on rising edge */ + GPIO_BOTH_EDGES, /* 3 = Interrupt on both edges */ + GPIO_LOW_LEVEL, /* 4 = Interrupt on low level */ + GPIO_HIGH_LEVEL /* 5 = Interrupt on high level */ +}; + +/* + * Table of port interrupt vector numbers + * Used by setCallback() to create Hwis. + * Up to 4 port interrupts must be supported + */ +static const uint8_t portInterruptIds[] = { + INT_GPIOA0, INT_GPIOA1, + INT_GPIOA2, INT_GPIOA3 +}; + +/* Table of GPIO input types */ +const uint16_t inPinTypes [] = { + PIN_TYPE_STD, /* GPIO_CFG_IN_NOPULL */ + PIN_TYPE_STD_PU, /* GPIO_CFG_IN_PU */ + PIN_TYPE_STD_PD /* GPIO_CFG_IN_PD */ +}; + +/* Table of GPIO output types */ +const uint16_t outPinTypes [] = { + PIN_TYPE_STD, /* GPIO_CFG_OUT_STD */ + PIN_TYPE_OD, /* GPIO_CFG_OUT_OD_NOPULL */ + PIN_TYPE_OD_PU, /* GPIO_CFG_OUT_OD_PU */ + PIN_TYPE_OD_PD /* GPIO_CFG_OUT_OD_PD */ +}; + +/* Table of GPIO drive strengths */ +const uint16_t outPinStrengths [] = { + PIN_STRENGTH_2MA, /* GPIO_CFG_OUT_STR_LOW */ + PIN_STRENGTH_4MA, /* GPIO_CFG_OUT_STR_MED */ + PIN_STRENGTH_6MA /* GPIO_CFG_OUT_STR_HIGH */ +}; + +/* + * Table of port bases address. For use with most driverlib calls. + * Indexed by GPIO port number (0-3). + */ +static const uint32_t gpioBaseAddresses[] = { + GPIOA0_BASE, GPIOA1_BASE, + GPIOA2_BASE, GPIOA3_BASE +}; + +static const uint32_t powerResources[] = { + PowerCC32XX_PERIPH_GPIOA0, + PowerCC32XX_PERIPH_GPIOA1, + PowerCC32XX_PERIPH_GPIOA2, + PowerCC32XX_PERIPH_GPIOA3, +}; + +#define NUM_PORTS 4 +#define NUM_PINS_PER_PORT 8 +#define PORT_MASK 0x3 + +/* + * Extracts the GPIO interrupt type from the pinConfig. Value to index into the + * interruptType table. + */ +#define getIntTypeNumber(pinConfig) \ + ((pinConfig & GPIO_CFG_INT_MASK) >> GPIO_CFG_INT_LSB) + +/* Returns the GPIO port base address */ +#define getPortBase(port) (gpioBaseAddresses[(port) & PORT_MASK]) + +/* Returns the GPIO port number */ +#define getPort(port) (port & PORT_MASK) + +/* Returns the GPIO power resource ID */ +#define getPowerResource(port) (powerResources[port & PORT_MASK]) + +/* Returns GPIO number from the pinConfig */ +#define getGpioNumber(pinConfig) \ + (((pinConfig->port & PORT_MASK) * 8) + getPinNumber(pinConfig->pin)) + +/* Uninitialized callbackInfo pinIndex */ +#define CALLBACK_INDEX_NOT_CONFIGURED 0xFF + +/* + * Device specific interpretation of the GPIO_PinConfig content + */ +typedef struct PinConfig { + uint8_t pin; + uint8_t port; + uint16_t config; +} PinConfig; + +/* + * User defined pin indexes assigned to a port's 8 pins. + * Used by port interrupt function to locate callback assigned + * to a pin. + */ +typedef struct PortCallbackInfo { + /* + * the port's 8 corresponding + * user defined pinId indices + */ + uint8_t pinIndex[NUM_PINS_PER_PORT]; +} PortCallbackInfo; + +/* + * Table of portCallbackInfos. + * One for each port. + */ +static PortCallbackInfo gpioCallbackInfo[NUM_PORTS]; + +/* + * bit mask used to determine if a Hwi has been created/constructed + * for a port already. + * up to NUM_PORTS port interrupts must be supported + */ +static uint8_t portHwiCreatedBitMask = 0; + +/* + * Bit mask used to keep track of which of the GPIO objects in the config + * structure have interrupts enabled. This will be used to restore the + * interrupts after coming out of LPDS. + */ +static uint32_t configIntsEnabledMask = 0; + +#if DebugP_ASSERT_ENABLED +/* + * Internal boolean to confirm that GPIO_init() has been called. + */ +static bool initCalled = false; +#endif + +/* Notification for going into and waking up from LPDS */ +static Power_NotifyObj powerNotifyObj; + +extern const GPIOCC32XX_Config GPIOCC32XX_config; + +static int powerNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg); + +/* + * ======== getPinNumber ======== + * + * Internal function to efficiently find the index of the right most set bit. + */ +static inline uint32_t getPinNumber(uint32_t x) { +#if defined(__TI_COMPILER_VERSION__) + return (uint32_t)(__clz(__rbit(x)) & 0x7); +#elif defined(codered) || defined(__GNUC__) || defined(sourcerygxx) + return (uint32_t)(__builtin_ctz(x) & 0x7); +#elif defined(__IAR_SYSTEMS_ICC__) + return (uint32_t)(__CLZ(__RBIT(x)) & 0x7); +#elif defined(rvmdk) || defined(__ARMCC_VERSION) + return (uint32_t)(__clz(__rbit(x)) & 0x7); +#else + #error "Unsupported compiler used" +#endif +} + +/* + * ======== GPIO_clearInt ======== + */ +void GPIO_clearInt(uint_least8_t index) +{ + PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; + + DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); + + /* Clear GPIO interrupt flag */ + MAP_GPIOIntClear(getPortBase(config->port), config->pin); + + DebugP_log2("GPIO: port 0x%x, pin 0x%x interrupt flag cleared", + getPort(config->port), config->pin); +} + +/* + * ======== GPIO_disableInt ======== + */ +void GPIO_disableInt(uint_least8_t index) +{ + uintptr_t key; + PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; + + DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); + + /* Make atomic update */ + key = HwiP_disable(); + + /* Disable GPIO interrupt */ + MAP_GPIOIntDisable(getPortBase(config->port), config->pin); + + configIntsEnabledMask &= ~(1 << index); + + HwiP_restore(key); + + DebugP_log2("GPIO: port 0x%x, pin 0x%x interrupts disabled", + getPort(config->port), config->pin); +} + +/* + * ======== GPIO_enableInt ======== + */ +void GPIO_enableInt(uint_least8_t index) +{ + uintptr_t key; + PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; + + DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); + + /* Make atomic update */ + key = HwiP_disable(); + + /* Enable GPIO interrupt */ + MAP_GPIOIntEnable(getPortBase(config->port), config->pin); + + configIntsEnabledMask |= (1 << index); + + HwiP_restore(key); + + DebugP_log2("GPIO: port 0x%x, pin 0x%x interrupts enabled", + getPort(config->port), config->pin); +} + +/* + * ======== GPIO_getConfig ======== + */ +void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig) +{ + DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); + + *pinConfig = GPIOCC32XX_config.pinConfigs[index]; +} + +/* + * ======== GPIO_hwiIntFxn ======== + * Hwi function that processes GPIO interrupts. + */ +void GPIO_hwiIntFxn(uintptr_t portIndex) +{ + unsigned int bitNum; + unsigned int pinIndex; + uint32_t pins; + uint32_t portBase; + PortCallbackInfo *portCallbackInfo; + + portCallbackInfo = &gpioCallbackInfo[portIndex]; + portBase = getPortBase(portIndex); + + /* Find out which pins have their interrupt flags set */ + pins = MAP_GPIOIntStatus(portBase, 0xFF) & 0xFF; + + /* clear all the set bits at once */ + MAP_GPIOIntClear(portBase, pins); + + /* Match the interrupt to its corresponding callback function */ + while (pins) { + /* Gets the lowest order set bit number */ + bitNum = getPinNumber(pins); + pinIndex = portCallbackInfo->pinIndex[bitNum & 0x7]; + /* only call plugged callbacks */ + if (pinIndex != CALLBACK_INDEX_NOT_CONFIGURED) { + GPIOCC32XX_config.callbacks[pinIndex](pinIndex); + } + pins &= ~(1 << bitNum); + } +} + +/* + * ======== GPIO_init ======== + */ +void GPIO_init() +{ + unsigned int i, j; + +#if DebugP_ASSERT_ENABLED + initCalled = true; +#endif + for (i = 0; i < NUM_PORTS; i++) { + for (j = 0; j < NUM_PINS_PER_PORT; j++) { + gpioCallbackInfo[i].pinIndex[j] = CALLBACK_INDEX_NOT_CONFIGURED; + } + } + + /* + * Configure pins and create Hwis per static array content + */ + for (i = 0; i < GPIOCC32XX_config.numberOfPinConfigs; i++) { + if (!(GPIOCC32XX_config.pinConfigs[i] & GPIO_DO_NOT_CONFIG)) { + + GPIO_setConfig(i, GPIOCC32XX_config.pinConfigs[i]); + } + if (i < GPIOCC32XX_config.numberOfCallbacks) { + if (GPIOCC32XX_config.callbacks[i] != NULL) { + /* create Hwi as necessary */ + GPIO_setCallback(i, GPIOCC32XX_config.callbacks[i]); + } + } + } + + Power_registerNotify(&powerNotifyObj, + PowerCC32XX_ENTERING_LPDS | PowerCC32XX_AWAKE_LPDS, + powerNotifyFxn, (uintptr_t) NULL); +} + +/* + * ======== GPIO_read ======== + */ +uint_fast8_t GPIO_read(uint_least8_t index) +{ + unsigned int value; + + PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; + + DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); + + value = MAP_GPIOPinRead(getPortBase(config->port), config->pin); + + DebugP_log3("GPIO: port 0x%x, pin 0x%x read 0x%x", + getPort(config->port), config->pin, value); + + value = (value & config->pin) ? 1 : 0; + + return (value); +} + +/* + * ======== GPIO_setCallback ======== + */ +void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback) +{ + uint32_t pinNum; + uint32_t portIndex; + PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; + + DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfCallbacks); + + /* + * plug the pin index into the corresponding + * port's callbackInfo pinIndex entry + */ + pinNum = getPinNumber(config->pin); + portIndex = config->port & PORT_MASK; + + if (callback == NULL) { + gpioCallbackInfo[portIndex].pinIndex[pinNum] = + CALLBACK_INDEX_NOT_CONFIGURED; + } + else { + gpioCallbackInfo[portIndex].pinIndex[pinNum] = index; + } + + /* + * Only update callBackFunctions entry if different. + * This allows the callBackFunctions array to be in flash for static systems. + */ + if (GPIOCC32XX_config.callbacks[index] != callback) { + GPIOCC32XX_config.callbacks[index] = callback; + } +} + +/* + * ======== GPIO_setConfig ======== + */ +int_fast16_t GPIO_setConfig(uint_least8_t index, GPIO_PinConfig pinConfig) +{ + uintptr_t key; + uint32_t pin; + uint32_t pad; + uint32_t portBase; + uint32_t portIndex; + uint32_t portBitMask; + uint16_t direction; + uint16_t strength; + uint16_t pinType; + HwiP_Handle hwiHandle; + HwiP_Params hwiParams; + GPIO_PinConfig gpioPinConfig; + PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; + + DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); + + if (pinConfig & GPIO_DO_NOT_CONFIG) { + return (GPIO_STATUS_SUCCESS); + } + + portBase = getPortBase(config->port); + pin = config->pin; + pad = PinFromPadGet((unsigned long)getGpioNumber(config)); + + /* Make atomic update */ + key = HwiP_disable(); + + /* set the pad's pinType to GPIO */ + MAP_PinModeSet(pad, PIN_MODE_0); + + /* enable clocks for the GPIO port */ + Power_setDependency(getPowerResource(config->port)); + + HwiP_restore(key); + + if ((pinConfig & GPIO_CFG_IN_INT_ONLY) == 0) { + if (pinConfig & GPIO_CFG_INPUT) { + /* configure input */ + direction = GPIO_DIR_MODE_IN; + strength = PIN_STRENGTH_2MA; + pinType = inPinTypes[(pinConfig & GPIO_CFG_IN_TYPE_MASK) >> + GPIO_CFG_IN_TYPE_LSB]; + } + else { + /* configure output */ + direction = GPIO_DIR_MODE_OUT; + strength = + outPinStrengths[(pinConfig & GPIO_CFG_OUT_STRENGTH_MASK) >> + GPIO_CFG_OUT_STRENGTH_LSB]; + pinType = outPinTypes[(pinConfig & GPIO_CFG_OUT_TYPE_MASK) >> + GPIO_CFG_OUT_TYPE_LSB]; + } + + key = HwiP_disable(); + + /* Configure the GPIO pin */ + MAP_GPIODirModeSet(portBase, pin, direction); + MAP_PinConfigSet(pad, strength, pinType); + + /* Set output value */ + if (direction == GPIO_DIR_MODE_OUT) { + MAP_GPIOPinWrite(portBase, pin, + ((pinConfig & GPIO_CFG_OUT_HIGH) ? 0xFF : 0)); + } + + /* + * Update pinConfig with the latest GPIO configuration and + * clear the GPIO_DO_NOT_CONFIG bit if it was set. + */ + gpioPinConfig = GPIOCC32XX_config.pinConfigs[index]; + gpioPinConfig &= ~(GPIO_CFG_IO_MASK | GPIO_DO_NOT_CONFIG); + gpioPinConfig |= (pinConfig & GPIO_CFG_IO_MASK); + GPIOCC32XX_config.pinConfigs[index] = gpioPinConfig; + + HwiP_restore(key); + } + + /* Set type of interrupt and then clear it */ + if (pinConfig & GPIO_CFG_INT_MASK) { + portIndex = config->port & PORT_MASK; + portBitMask = 1 << portIndex; + + /* if Hwi has not already been created, do so */ + if ((portHwiCreatedBitMask & portBitMask) == 0) { + HwiP_Params_init(&hwiParams); + hwiParams.arg = (uintptr_t) portIndex; + hwiParams.priority = GPIOCC32XX_config.intPriority; + hwiHandle = HwiP_create(portInterruptIds[portIndex], GPIO_hwiIntFxn, + &hwiParams); + if (hwiHandle == NULL) { + /* Error creating Hwi */ + DebugP_log1("GPIO: Error constructing Hwi for GPIO Port %d", + getPort(config->port)); + return (GPIO_STATUS_ERROR); + } + } + + key = HwiP_disable(); + + /* Mark the Hwi as created */ + portHwiCreatedBitMask |= portBitMask; + + MAP_GPIOIntTypeSet(portBase, pin, + interruptType[getIntTypeNumber(pinConfig)]); + MAP_GPIOIntClear(portBase, pin); + + /* + * Update pinConfig with the latest interrupt configuration and + * clear the GPIO_DO_NOT_CONFIG bit if it was set. + */ + gpioPinConfig = GPIOCC32XX_config.pinConfigs[index]; + gpioPinConfig &= ~(GPIO_CFG_INT_MASK | GPIO_DO_NOT_CONFIG); + gpioPinConfig |= (pinConfig & GPIO_CFG_INT_MASK); + GPIOCC32XX_config.pinConfigs[index] = gpioPinConfig; + + HwiP_restore(key); + } + + return (GPIO_STATUS_SUCCESS); +} + +/* + * ======== GPIO_toggle ======== + */ +void GPIO_toggle(uint_least8_t index) +{ + uintptr_t key; + uint32_t value; + PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; + + DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); + DebugP_assert((GPIOCC32XX_config.pinConfigs[index] & GPIO_CFG_INPUT) == + GPIO_CFG_OUTPUT); + + /* Make atomic update */ + key = HwiP_disable(); + + value = MAP_GPIOPinRead(getPortBase(config->port), config->pin); + value ^= config->pin; + MAP_GPIOPinWrite(getPortBase(config->port), config->pin, value); + + /* Update config table entry with value written */ + GPIOCC32XX_config.pinConfigs[index] ^= GPIO_CFG_OUT_HIGH; + + HwiP_restore(key); + + DebugP_log2("GPIO: port 0x%x, pin 0x%x toggled", + getPort(config->port), config->pin); +} + +/* + * ======== GPIO_write ======== + */ +void GPIO_write(uint_least8_t index, unsigned int value) +{ + uintptr_t key; + uint32_t output; + PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; + + DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); + DebugP_assert((GPIOCC32XX_config.pinConfigs[index] & GPIO_CFG_INPUT) == + GPIO_CFG_OUTPUT); + + key = HwiP_disable(); + + /* Clear output from pinConfig */ + GPIOCC32XX_config.pinConfigs[index] &= ~GPIO_CFG_OUT_HIGH; + + if (value) { + output = config->pin; + + /* Set the pinConfig output bit to high */ + GPIOCC32XX_config.pinConfigs[index] |= GPIO_CFG_OUT_HIGH; + } + else { + output = value; + } + + MAP_GPIOPinWrite(getPortBase(config->port), config->pin, output); + + HwiP_restore(key); + + DebugP_log3("GPIO: port 0x%x, pin 0x%x wrote 0x%x", + getPort(config->port), config->pin, value); +} + +/* + * ======== powerNotifyFxn ======== + */ +static int powerNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg) +{ + unsigned int i; + uint32_t ulRegVal; + GPIO_PinConfig config; + uint32_t output; + uint32_t pad; + PinConfig *pinConfig; + PowerCC32XX_ParkState state; + + if (eventType == PowerCC32XX_AWAKE_LPDS) { + /* Take GPIO semaphore */ + ulRegVal = HWREG(0x400F703C); + ulRegVal = (ulRegVal & ~0x3FF) | 0x155; + HWREG(0x400F703C) = ulRegVal; + + for (i = 0; i < GPIOCC32XX_config.numberOfPinConfigs; i++) { + if (!(GPIOCC32XX_config.pinConfigs[i] & GPIO_DO_NOT_CONFIG)) { + config = GPIOCC32XX_config.pinConfigs[i]; + + GPIO_setConfig(i, config); + + if (configIntsEnabledMask & (1 << i)) { + GPIO_enableInt(i); + } + } + } + } + else { + /* Entering LPDS */ + /* + * For pins configured as GPIO output, if the GPIOCC32XX_USE_STATIC + * configuration flag is *not* set, get the current pin state, and + * then call to the Power manager to define the state to be held + * during LPDS. + * If GPIOCC32XX_USE_STATIC *is* defined, do nothing, and the pin + * will be parked in the state statically defined in + * PowerCC32XX_config.pinParkDefs[] in the board file. + */ + for (i = 0; i < GPIOCC32XX_config.numberOfPinConfigs; i++) { + if (GPIOCC32XX_config.pinConfigs[i] & GPIO_DO_NOT_CONFIG) { + continue; + } + + config = GPIOCC32XX_config.pinConfigs[i]; + + /* if OUTPUT, and GPIOCC32XX_USE_STATIC flag is not set */ + if ((!(config & GPIO_CFG_INPUT)) && + (!(config & GPIOCC32XX_USE_STATIC))) { + + pinConfig = (PinConfig *) &GPIOCC32XX_config.pinConfigs[i]; + + /* determine state to be held */ + pad = PinFromPadGet((unsigned long)getGpioNumber(pinConfig)); + output = config & GPIO_CFG_OUT_HIGH; + state = (PowerCC32XX_ParkState) ((output) ? 1 : 0); + + /* set the new park state */ + PowerCC32XX_setParkState((PowerCC32XX_Pin)pad, state); + } + } + } + + return (Power_NOTIFYDONE); +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/gpio/GPIOCC32XX.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/gpio/GPIOCC32XX.h new file mode 100644 index 000000000..2404c326b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/gpio/GPIOCC32XX.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! ============================================================================ + * @file GPIOCC32XX.h + * + * @brief GPIO driver implementation for CC32xx devices + * + * The GPIO header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref GPIO.h for a complete description of the GPIO + * driver APIs provided and examples of their use. + * + * ### CC32xx GPIO Driver Configuration # + * + * In order to use the GPIO APIs, the application is required + * to provide 3 structures in the Board.c file: + * + * 1. An array of @ref GPIO_PinConfig elements that defines the + * initial configuration of each pin used by the application. A + * pin is referenced in the application by its corresponding index in this + * array. The pin type (that is, INPUT/OUTPUT), its initial state (that is + * OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.) + * (see @ref GPIO_PinConfigSettings), and + * device specific pin identification (see @ref GPIOCC32XX_PinConfigIds) + * are configured in each element of this array. + * Below is an CC32XX device specific example of the GPIO_PinConfig array: + * @code + * // + * // Array of Pin configurations + * // NOTE: The order of the pin configurations must coincide with what was + * // defined in CC3220SF_LAUNCHXL.h + * // NOTE: Pins not used for interrupts should be placed at the end of the + * // array. Callback entries can be omitted from callbacks array to + * // reduce memory usage. + * // + * GPIO_PinConfig gpioPinConfigs[] = { + * // input pins with callbacks + * // CC3220SF_LAUNCHXL_GPIO_SW2 + * GPIOCC32XX_GPIO_22 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, + * // CC3220SF_LAUNCHXL_GPIO_SW3 + * GPIOCC32XX_GPIO_13 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, + * + * // output pins + * // CC3220SF_LAUNCHXL_GPIO_LED_D7 + * GPIOCC32XX_GPIO_09 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + * }; + * @endcode + * + * 2. An array of @ref GPIO_CallbackFxn elements that is used to store + * callback function pointers for GPIO pins configured with interrupts. + * The indexes for these array elements correspond to the pins defined + * in the @ref GPIO_PinConfig array. These function pointers can be defined + * statically by referencing the callback function name in the array + * element, or dynamically, by setting the array element to NULL and using + * GPIO_setCallback() at runtime to plug the callback entry. + * Pins not used for interrupts can be omitted from the callback array to + * reduce memory usage (if they are placed at the end of the @ref + * GPIO_PinConfig array). The callback function syntax should match the + * following: + * @code + * void (*GPIO_CallbackFxn)(unsigned int index); + * @endcode + * The index parameter is the same index that was passed to + * GPIO_setCallback(). This allows the same callback function to be used + * for multiple GPIO interrupts, by using the index to identify the GPIO + * that caused the interrupt. + * Below is a CC32XX device specific example of the @ref GPIO_CallbackFxn + * array: + * @code + * // + * // Array of callback function pointers + * // NOTE: The order of the pin configurations must coincide with what was + * // defined in CC3220SF_LAUNCHXL.h + * // NOTE: Pins not used for interrupts can be omitted from callbacks array to + * // reduce memory usage (if placed at end of gpioPinConfigs array). + * // + * GPIO_CallbackFxn gpioCallbackFunctions[] = { + * NULL, // CC3220SF_LAUNCHXL_GPIO_SW2 + * NULL // CC3220SF_LAUNCHXL_GPIO_SW3 + * }; + * @endcode + * + * 3. The device specific GPIOCC32XX_Config structure that tells the GPIO + * driver where the two aforementioned arrays are and the number of elements + * in each. The interrupt priority of all pins configured to generate + * interrupts is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + * Below is an example of an initialized GPIOCC32XX_Config + * structure: + * @code + * const GPIOCC32XX_Config GPIOCC32XX_config = { + * .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + * .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + * .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + * .intPriority = (~0) + * }; + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_GPIOCC32XX__include +#define ti_drivers_GPIOCC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/*! + * @brief GPIO device specific driver configuration structure + * + * The device specific GPIOCC32XX_Config structure that tells the GPIO + * driver where the two aforementioned arrays are and the number of elements + * in each. The interrupt priority of all pins configured to generate + * interrupts is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + * + * Below is an example of an initialized GPIOCC32XX_Config + * structure: + * @code + * const GPIOCC32XX_Config GPIOCC32XX_config = { + * .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + * .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + * .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + * .intPriority = (~0) + * }; + * @endcode + */ +typedef struct GPIOCC32XX_Config { + /*! Pointer to the board's GPIO_PinConfig array */ + GPIO_PinConfig *pinConfigs; + + /*! Pointer to the board's GPIO_CallbackFxn array */ + GPIO_CallbackFxn *callbacks; + + /*! Number of GPIO_PinConfigs defined */ + uint32_t numberOfPinConfigs; + + /*! Number of GPIO_Callbacks defined */ + uint32_t numberOfCallbacks; + + /*! + * Interrupt priority used for call back interrupts. + * + * intPriority is the interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's + * interrupt handler creation code, so you need to refer to the OS + * documentation for usage. For example, for SYS/BIOS applications, + * refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS + * usage of interrupt priorities. If the driver uses the ti.dpl + * interface instead of making OS calls directly, then the HwiP port + * handles the interrupt priority in an OS specific way. In the case + * of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). + * + * Setting ~0 will configure the lowest possible priority + */ + uint32_t intPriority; +} GPIOCC32XX_Config; + +/*! + * \defgroup GPIOCC32XX_PinConfigIds GPIO pin identification macros used to configure GPIO pins + * @{ + */ +/** + * @name Device specific GPIO port/pin identifiers to be used within the board's GPIO_PinConfig table. + * @{ +*/ +#define GPIOCC32XX_EMPTY_PIN 0x0000 /*!< @hideinitializer */ + +#define GPIOCC32XX_GPIO_00 0x0001 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_01 0x0002 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_02 0x0004 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_03 0x0008 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_04 0x0010 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_05 0x0020 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_06 0x0040 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_07 0x0080 /*!< @hideinitializer */ + +#define GPIOCC32XX_GPIO_08 0x0101 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_09 0x0102 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_10 0x0104 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_11 0x0108 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_12 0x0110 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_13 0x0120 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_14 0x0140 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_15 0x0180 /*!< @hideinitializer */ + +#define GPIOCC32XX_GPIO_16 0x0201 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_17 0x0202 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_18 0x0204 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_19 0x0208 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_20 0x0210 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_21 0x0220 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_22 0x0240 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_23 0x0280 /*!< @hideinitializer */ + +#define GPIOCC32XX_GPIO_24 0x0301 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_25 0x0302 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_26 0x0304 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_27 0x0308 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_28 0x0310 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_29 0x0320 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_30 0x0340 /*!< @hideinitializer */ +#define GPIOCC32XX_GPIO_31 0x0380 /*!< @hideinitializer */ +/** @} */ + +/** + * @name CC32xx device specific GPIO_PinConfig macros + * @{ + */ +#define GPIOCC32XX_USE_STATIC 0x8000 /*!< @hideinitializer use statically-defined parking state */ +/** @} */ + +/** @} end of GPIOCC32XX_PinConfigIds group */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_GPIOCC32XX__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/i2c/I2CCC32XX.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/i2c/I2CCC32XX.h new file mode 100644 index 000000000..5a7106545 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/i2c/I2CCC32XX.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file I2CCC32XX.h + * + * @brief I2C driver implementation for a CC32XX I2C controller. + * + * The I2C header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref I2C.h for a complete description of APIs and usage. + * + * ============================================================================ + */ + +#ifndef ti_drivers_i2c_I2CCC32XX__include +#define ti_drivers_i2c_I2CCC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include + +/* macros defining possible I2C signal pin mux options */ +#define I2CCC32XX_PIN_01_I2C_SCL 0x100 /*!< PIN 1 is used for I2C_SCL */ +#define I2CCC32XX_PIN_02_I2C_SDA 0x101 /*!< PIN 2 is used for I2C_SDA */ +#define I2CCC32XX_PIN_03_I2C_SCL 0x502 /*!< PIN 3 is used for I2C_SCL */ +#define I2CCC32XX_PIN_04_I2C_SDA 0x503 /*!< PIN 4 is used for I2C_SDA */ +#define I2CCC32XX_PIN_05_I2C_SCL 0x504 /*!< PIN 5 is used for I2C_SCL */ +#define I2CCC32XX_PIN_06_I2C_SDA 0x505 /*!< PIN 6 is used for I2C_SDA */ +#define I2CCC32XX_PIN_16_I2C_SCL 0x90F /*!< PIN 16 is used for I2C_SCL */ +#define I2CCC32XX_PIN_17_I2C_SDA 0x910 /*!< PIN 17 is used for I2C_SDA */ + +/** + * @addtogroup I2C_STATUS + * I2CCC32XX_STATUS_* macros are command codes only defined in the + * I2CCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add I2CCC32XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup I2C_CMD + * I2CCC32XX_CMD_* macros are command codes only defined in the + * I2CCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add I2CCC32XX_CMD_* macros here */ + +/** @}*/ + +/* I2C function table pointer */ +extern const I2C_FxnTable I2CCC32XX_fxnTable; + +/*! + * @cond NODOC + * I2CCC32XX mode + * + * This enum defines the state of the I2C driver's state machine. + */ +typedef enum I2CCC32XX_Mode { + /*! I2C is idle, and not performing a transaction */ + I2CCC32XX_IDLE_MODE = 0, + /*! I2C is currently performing a write operation */ + I2CCC32XX_WRITE_MODE, + /*! I2C is currently performing a read operation */ + I2CCC32XX_READ_MODE, + /*! I2C error has occurred */ + I2CCC32XX_ERROR = 0xFF +} I2CCC32XX_Mode; +/*! @endcond */ + +/*! + * @brief I2CCC32XX Hardware attributes + * + * The baseAddr and intNum fields define the base address and interrupt number + * of the I2C peripheral. These values are used by driverlib APIs and + * therefore must be populated by driverlib macro definitions. These + * definitions are found in the header files: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * intPriority is the I2C peripheral's interrupt priority. + * This driver uses the ti.dpl interface instead of making OS calls directly, + * and the corresponding HwiP port handles the interrupt priority in an + * OS-specific way. For example, in the case of the TI-RTOS kernel port, + * the intPriority is passed unmodified to Hwi_create() provided by the + * ti.sysbios.family.arm.m3.Hwi module; so the documentation for the + * ti.sysbios.family.arm.m3.Hwi module should be referenced for a description + * of usage of priority. + * + * clkPin and dataPin define the pin multiplexing to be used for the SCL and + * SDA pins, respectively. Macro values defined in this header file should + * be used for these fields. + * + * A sample structure is shown below: + * @code + * const I2CCC32XX_HWAttrsV1 i2cCC32XXHWAttrs[] = { + * { + * .baseAddr = I2CA0_BASE, + * .intNum = INT_I2CA0, + * .intPriority = (~0), + * .clkPin = I2CCC32XX_PIN_01_I2C_SCL, + * .dataPin = I2CCC32XX_PIN_02_I2C_SDA, + * } + * }; + * @endcode + */ +typedef struct I2CCC32XX_HWAttrsV1 { + /*! I2C Peripheral's base address */ + unsigned int baseAddr; + /*! I2C Peripheral's interrupt vector */ + unsigned int intNum; + /*! I2C Peripheral's interrupt priority */ + unsigned int intPriority; + /*! I2C clock pin configuration */ + uint16_t clkPin; + /*! I2C data pin configuration */ + uint16_t dataPin; +} I2CCC32XX_HWAttrsV1; + +/*! + * @cond NODOC + * I2CCC32XX Object. Applications must not access any member variables of + * this structure! + */ +typedef struct I2CCC32XX_Object { + SemaphoreP_Handle mutex; /* Grants exclusive access to I2C */ + SemaphoreP_Handle transferComplete; /* Signals I2C transfer completion */ + + HwiP_Handle hwiHandle; + + I2C_TransferMode transferMode; /* Blocking or Callback mode */ + I2C_CallbackFxn transferCallbackFxn; /* Callback function pointer */ + + volatile I2CCC32XX_Mode mode; /* Stores the I2C state */ + + I2C_Transaction *currentTransaction; /* Pointer to current transaction */ + + uint8_t *writeBufIdx; /* Internal inc. writeBuf index */ + size_t writeCountIdx; /* Internal dec. writeCounter */ + + uint8_t *readBufIdx; /* Internal inc. readBuf index */ + size_t readCountIdx; /* Internal dec. readCounter */ + + /* I2C transaction pointers for I2C_MODE_CALLBACK */ + I2C_Transaction *headPtr; /* Head ptr for queued transactions */ + I2C_Transaction *tailPtr; /* Tail ptr for queued transactions */ + + bool isOpen; /* Flag to indicate module is open */ + + Power_NotifyObj notifyObj; /* For notification of wake from LPDS */ + I2C_BitRate bitRate; /* I2C bus bit rate */ +} I2CCC32XX_Object; +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_i2c_I2CCC32XX__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/i2s/I2SCC32XXDMA.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/i2s/I2SCC32XXDMA.h new file mode 100644 index 000000000..44e17b94f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/i2s/I2SCC32XXDMA.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file I2SCC32XXDMA.h + * + * @brief I2S driver implementation for a CC32XX I2S controller + * + * The I2S header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref I2S.h for a complete description of APIs & example of use. + * + * ============================================================================ + */ + +#ifndef ti_drivers_i2s_I2SCC32XXDMA__include +#define ti_drivers_i2s_I2SCC32XXDMA__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include + +#define I2SCC32XXDMA_PIN_02_McAFSX 0x0d01 +#define I2SCC32XXDMA_PIN_03_McACLK 0x0302 +#define I2SCC32XXDMA_PIN_15_McAFSX 0x070e +#define I2SCC32XXDMA_PIN_17_McAFSX 0x0610 +#define I2SCC32XXDMA_PIN_21_McAFSX 0x0214 +#define I2SCC32XXDMA_PIN_45_McAXR0 0x062c +#define I2SCC32XXDMA_PIN_45_McAFSX 0x0c2c +#define I2SCC32XXDMA_PIN_50_McAXR0 0x0431 +#define I2SCC32XXDMA_PIN_50_McAXR1 0x0631 +#define I2SCC32XXDMA_PIN_52_McACLK 0x0233 +#define I2SCC32XXDMA_PIN_52_McAXR0 0x0433 +#define I2SCC32XXDMA_PIN_53_McACLK 0x0234 +#define I2SCC32XXDMA_PIN_53_McAFSX 0x0334 +#define I2SCC32XXDMA_PIN_60_McAXR1 0x063b +#define I2SCC32XXDMA_PIN_62_McACLKX 0x0d3d +#define I2SCC32XXDMA_PIN_63_McAFSX 0x073e +#define I2SCC32XXDMA_PIN_64_McAXR0 0x073f + +/** + * @addtogroup I2S_STATUS + * I2SCC32XXDMA_STATUS_* macros are command codes only defined in the + * I2SCC32XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add I2SCC32XXDMA_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup I2S_CMD + * I2SCC32XXDMA_CMD_* macros are command codes only defined in the + * I2SCC32XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +#define I2SCC32XXDMA_CMD_SET_ZEROBUF_LEN (I2S_CMD_RESERVED + 0) +#define I2SCC32XXDMA_CMD_SET_EMPTYBUF_LEN (I2S_CMD_RESERVED + 1) + +/** @}*/ + +/* BACKWARDS COMPATIBILITY */ +#define I2SCC32XXDMA_SET_ZEROBUF_LEN I2SCC32XXDMA_CMD_SET_ZEROBUF_LEN +#define I2SCC32XXDMA_SET_EMPTYBUF_LEN I2SCC32XXDMA_CMD_SET_EMPTYBUF_LEN +/* END BACKWARDS COMPATIBILITY */ + +/* Value for Invalid Index */ +#define I2SCC32XXDMA_INDEX_INVALID 0xFF + +/*Number of Serial data pins supported*/ +#define I2SCC32XXDMA_NUM_SERIAL_PINS 2 + +/*! + * @brief + * I2SCC32XXDMA data size is used to determine how to configure the + * DMA data transfers. This field is to be only used internally. + * + * I2SCC32XXDMA_16bit: txBuf and rxBuf are arrays of uint16_t elements + * I2SCC32XXDMA_32bit: txBuf and rxBuf are arrays of uint32_t elements + */ +typedef enum I2SCC32XXDMA_DataSize { + I2SCC32XXDMA_16bit = 0, + I2SCC32XXDMA_32bit = 1 +} I2SCC32XXDMA_DataSize; + + +/* I2S function table pointer */ +extern const I2S_FxnTable I2SCC32XXDMA_fxnTable; + + +/*! + * @brief I2SCC32XXDMA Hardware attributes + * + * These fields, with the exception of intPriority, + * are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC32XXWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * intPriority is the I2S peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * const I2SCC32XXDMA_HWAttrsV1 i2sCC32XXHWAttrs[] = { + * { + * .baseAddr = I2S_BASE, + * .intNum = INT_I2S, + * .intPriority = (~0), + * .rxChannelIndex = UDMA_CH4_I2S_RX, + * .txChannelIndex = UDMA_CH5_I2S_TX, + * .xr0Pin = I2SCC32XXDMA_PIN_64_McAXR0, + * .xr1Pin = I2SCC32XXDMA_PIN_50_McAXR1, + * .clkxPin = I2SCC32XXDMA_PIN_62_McACLKX, + * .clkPin = I2SCC32XXDMA_PIN_53_McACLK, + * .fsxPin = I2SCC32XXDMA_PIN_63_McAFSX, + * } + * }; + * @endcode + */ +typedef struct I2SCC32XXDMA_HWAttrsV1 { + /*! I2S Peripheral's base address */ + uint32_t baseAddr; + /*! I2S Peripheral's interrupt vector */ + uint32_t intNum; + /*! I2S Peripheral's interrupt priority */ + uint32_t intPriority; + /*! uDMA controlTable receive channel index */ + unsigned long rxChannelIndex; + /*! uDMA controlTable transmit channel index */ + unsigned long txChannelIndex; + /*! I2S audio port data 0 pin */ + uint16_t xr0Pin; + /*! I2S audio port data 1 pin */ + uint16_t xr1Pin; + /*! I2S audio port clock O pin */ + uint16_t clkxPin; + /*! I2S audio port data pin */ + uint16_t clkPin; + /*! I2S audio port frame sync */ + uint16_t fsxPin; +} I2SCC32XXDMA_HWAttrsV1; + +/*! + * @brief CC32XX Serial Pin Configuration + */ +typedef struct I2SCC32XXDMA_SerialPinConfig { + /*!< Pin number */ + unsigned char pinNumber; + + /*!< Mode the pin will operate(Rx/Tx) */ + I2S_PinMode pinMode; + + /*!< Pin configuration in inactive state */ + I2S_SerInActiveConfig inActiveConfig; + +} I2SCC32XXDMA_SerialPinConfig; + +/*! + * @brief CC32XX specific I2S Parameters + */ +typedef struct I2SCC32XXDMA_SerialPinParams { + + /*!< CC32XX Serial Pin Configuration */ + I2SCC32XXDMA_SerialPinConfig serialPinConfig[I2SCC32XXDMA_NUM_SERIAL_PINS]; + +} I2SCC32XXDMA_SerialPinParams; + +/*! + * @brief I2SCC32XXDMA Serial pin variables + * + * The application must not access any member variables of this structure! + */ +typedef struct I2SCC32XXDMA_SerialPinVars { + I2S_DataMode readWriteMode; + /* Pointer to read/write callback */ + I2S_Callback readWriteCallback; + /* Timeout for read/write semaphore */ + uint32_t readWriteTimeout; + +}I2SCC32XXDMA_SerialPinVars; + +/*! + * @brief I2SCC32XXDMA Object + * + * The application must not access any member variables of this structure! + */ +typedef struct I2SCC32XXDMA_Object { + /* I2S control variables */ + bool opened; /* Has the obj been opened */ + uint32_t operationMode; /* Mode of operation of I2S */ + + /* I2S serial pin variables */ + I2SCC32XXDMA_SerialPinVars serialPinVars[I2SCC32XXDMA_NUM_SERIAL_PINS]; + + uint16_t readIndex; /* read channel Index */ + uint16_t writeIndex; /* write channel Index */ + + I2SCC32XXDMA_DataSize dmaSize; /* Config DMA word size */ + + /* I2S OSAL objects */ + SemaphoreP_Handle writeSem; /* I2S write semaphore*/ + SemaphoreP_Handle readSem; /* I2S read semaphore */ + HwiP_Handle hwiHandle; + + /*!< Length of zero buffer to write in case of no data */ + unsigned long zeroWriteBufLength; + + /*!< Length of empty buffer to read in case of no data + requested */ + unsigned long emptyReadBufLength; + + /* Current Write buffer descriptor pointer */ + I2S_BufDesc *currentWriteBufDesc; + + /* Previous Write Buffer descriptor pointer */ + I2S_BufDesc *prevWriteBufDesc; + + /* Current Read buffer descriptor pointer */ + I2S_BufDesc *currentReadBufDesc; + + /* Previous Read Buffer descriptor pointer */ + I2S_BufDesc *prevReadBufDesc; + + /* UDMA */ + UDMACC32XX_Handle dmaHandle; + + /* Lists for issue-reclaim mode */ + List_List readActiveQueue; + List_List readDoneQueue; + List_List writeActiveQueue; + List_List writeDoneQueue; +} I2SCC32XXDMA_Object, *I2SCC32XXDMA_Handle; + +/*! + * @brief Function to initialize the I2S_Params struct to its defaults + * + * params->serialPinConfig[0].pinNumber = 0; + * params->serialPinConfig[0].pinMode = I2S_PINMODE_RX; + * params->serialPinConfig[0].inActiveConfig = I2S_SERCONFIG_INACT_LOW_LEVEL; + * + * params->serialPinConfig[1].pinNumber = 1; + * params->serialPinConfig[1].pinMode = I2S_PINMODE_TX; + * params->serialPinConfig[1].inActiveConfig = I2S_SERCONFIG_INACT_LOW_LEVEL; + * + * @param params Parameter structure to initialize + */ +extern void I2SCC32XXDMA_Params_init(I2SCC32XXDMA_SerialPinParams *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_i2s_I2SCC32XXDMA__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/power/PowerCC32XX.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/power/PowerCC32XX.c new file mode 100644 index 000000000..d572ca113 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/power/PowerCC32XX.c @@ -0,0 +1,1311 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC32XX.c ======== + */ + +#include + +/* + * By default disable both asserts and log for this module. + * This must be done before DebugP.h is included. + */ +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif +#include +#include + +#include + +#include +#include + +#if defined(__IAR_SYSTEMS_ICC__) +#include +#endif + +/* driverlib header files */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TRUE 1 +#define FALSE 0 +#define STATUS_BUSY 0x01 + +#define PowerCC32XX_SSPIReadStatusInstruction (0x05) +#define PowerCC32XX_SSPIPowerDownInstruction (0xB9) +#define PowerCC32XX_SSPISemaphoreTakeTries (4000000) + +#define SYNCBARRIER() { \ + __asm(" dsb \n" \ + " isb \n"); \ +} + +/* Externs */ +extern const PowerCC32XX_ConfigV1 PowerCC32XX_config; + +/* Module_State */ +PowerCC32XX_ModuleState PowerCC32XX_module = { + { NULL, NULL}, /* list */ + 0, /* constraintsMask */ + Power_ACTIVE, /* state */ + /* dbRecords */ + { + PRCM_CAMERA, /* PERIPH_CAMERA */ + PRCM_I2S, /* PERIPH_MCASP */ + PRCM_SDHOST, /* PERIPH_MMCHS */ + PRCM_GSPI, /* PERIPH_MCSPI_A1 */ + PRCM_LSPI, /* PERIPH_MCSPI_A2 */ + PRCM_UDMA, /* PERIPH_UDMA_A */ + PRCM_GPIOA0, /* PERIPH_GPIO_A */ + PRCM_GPIOA1, /* PERIPH_GPIO_B */ + PRCM_GPIOA2, /* PERIPH_GPIO_C */ + PRCM_GPIOA3, /* PERIPH_GPIO_D */ + PRCM_GPIOA4, /* PERIPH_GPIO_E */ + PRCM_WDT, /* PERIPH_WDOG_A */ + PRCM_UARTA0, /* PERIPH_UART_A0 */ + PRCM_UARTA1, /* PERIPH_UART_A1 */ + PRCM_TIMERA0, /* PERIPH_GPT_A0 */ + PRCM_TIMERA1, /* PERIPH_GPT_A1 */ + PRCM_TIMERA2, /* PERIPH_GPT_A2 */ + PRCM_TIMERA3, /* PERIPH_GPT_A3 */ + PRCM_DTHE, /* PERIPH_CRYPTO */ + PRCM_SSPI, /* PERIPH_MCSPI_S0 */ + PRCM_I2CA0 /* PERIPH_I2C */ + }, + /* enablePolicy */ + FALSE, + /* initialized */ + FALSE, + /* refCount */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + /* constraintCounts */ + { 0, 0 }, + /* policyFxn */ + NULL +}; + +/* context save variable */ +PowerCC32XX_SaveRegisters PowerCC32XX_contextSave; + +typedef void (*LPDSFunc)(void); + +/* enter LPDS is an assembly function */ +extern void PowerCC32XX_enterLPDS(LPDSFunc driverlibFunc); + +/* pin parking functions */ +void PowerCC32XX_parkPin(PowerCC32XX_Pin pin, PowerCC32XX_ParkState parkState, + uint32_t * previousState, uint16_t * previousDirection); +void PowerCC32XX_restoreParkedPin(PowerCC32XX_Pin pin, uint32_t type, + uint16_t direction); +void PowerCC32XX_shutdownSSPI(void); + +/* internal functions */ +static int_fast16_t notify(uint_fast16_t eventType); +static void restoreNVICRegs(void); +static void restorePeriphClocks(void); +static void saveNVICRegs(void); +static void parkPins(void); +static void restoreParkedPins(void); + +/* + * ======== Power_disablePolicy ======== + * Do not run the configured policy + */ +void Power_disablePolicy(void) +{ + PowerCC32XX_module.enablePolicy = FALSE; + + DebugP_log0("Power: disable policy"); +} + +/* + * ======== Power_enablePolicy ======== + * Run the configured policy + */ +void Power_enablePolicy(void) +{ + PowerCC32XX_module.enablePolicy = TRUE; + + DebugP_log0("Power: enable policy"); +} + +/* + * ======== Power_getConstraintMask ======== + * Get a bitmask indicating the constraints that have been registered with + * Power. + */ +uint_fast32_t Power_getConstraintMask(void) +{ + return (PowerCC32XX_module.constraintMask); +} + +/* + * ======== Power_getDependencyCount ======== + * Get the count of dependencies that are currently declared upon a resource. + */ +int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId) +{ + int_fast16_t status; + + if (resourceId >= PowerCC32XX_NUMRESOURCES) { + status = Power_EINVALIDINPUT; + } + else { + status = PowerCC32XX_module.refCount[resourceId]; + } + + return (status); +} + +/* + * ======== Power_getTransitionLatency ======== + * Get the transition latency for a sleep state. The latency is reported + * in units of microseconds. + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, + uint_fast16_t type) +{ + uint32_t latency = 0; + + if (type == Power_RESUME) { + latency = PowerCC32XX_RESUMETIMELPDS; + } + else { + latency = PowerCC32XX_TOTALTIMELPDS; + } + + return (latency); +} + +/* + * ======== Power_getTransitionState ======== + * Get the current sleep transition state. + */ +uint_fast16_t Power_getTransitionState(void) +{ + return (PowerCC32XX_module.state); +} + +/* + * ======== Power_idleFunc ======== + * Function needs to be plugged into the idle loop. + * It calls the configured policy function if the + * 'enablePolicy' flag is set. + */ +void Power_idleFunc() +{ + if (PowerCC32XX_module.enablePolicy) { + if (PowerCC32XX_module.policyFxn != NULL) { + DebugP_log1("Power: calling policy function (%p)", + (uintptr_t) PowerCC32XX_module.policyFxn); + (*(PowerCC32XX_module.policyFxn))(); + } + } +} + +/* + * ======== Power_init ======== + */ +int_fast16_t Power_init() +{ + /* if this function has already been called, just return */ + if (PowerCC32XX_module.initialized) { + return (Power_SOK); + } + + /* set module state field 'initialized' to true */ + PowerCC32XX_module.initialized = TRUE; + + /* set the module state enablePolicy field */ + PowerCC32XX_module.enablePolicy = PowerCC32XX_config.enablePolicy; + + /* call the config policy init function if its not null */ + if (PowerCC32XX_config.policyInitFxn != NULL) { + (*(PowerCC32XX_config.policyInitFxn))(); + } + + /* copy wakeup settings to module state */ + PowerCC32XX_module.wakeupConfig.enableGPIOWakeupLPDS = + PowerCC32XX_config.enableGPIOWakeupLPDS; + PowerCC32XX_module.wakeupConfig.enableGPIOWakeupShutdown = + PowerCC32XX_config.enableGPIOWakeupShutdown; + PowerCC32XX_module.wakeupConfig.enableNetworkWakeupLPDS = + PowerCC32XX_config.enableNetworkWakeupLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceLPDS = + PowerCC32XX_config.wakeupGPIOSourceLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeLPDS = + PowerCC32XX_config.wakeupGPIOTypeLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS = + PowerCC32XX_config.wakeupGPIOFxnLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg = + PowerCC32XX_config.wakeupGPIOFxnLPDSArg; + PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceShutdown = + PowerCC32XX_config.wakeupGPIOSourceShutdown; + PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeShutdown = + PowerCC32XX_config.wakeupGPIOTypeShutdown; + + /* now configure these wakeup settings in the device... */ + PowerCC32XX_configureWakeup(&PowerCC32XX_module.wakeupConfig); + + /* copy the Power policy function to module state */ + PowerCC32XX_module.policyFxn = PowerCC32XX_config.policyFxn; + + /* spin if too many pins were specified in the pin park array */ + if (PowerCC32XX_config.numPins > PowerCC32XX_NUMPINS) { + while(1){} + } + + return (Power_SOK); +} + +/* + * ======== Power_registerNotify ======== + * Register a function to be called on a specific power event. + */ +int_fast16_t Power_registerNotify(Power_NotifyObj * pNotifyObj, + uint_fast16_t eventTypes, Power_NotifyFxn notifyFxn, uintptr_t clientArg) +{ + int_fast16_t status = Power_SOK; + + /* check for NULL pointers */ + if ((pNotifyObj == NULL) || (notifyFxn == NULL)) { + status = Power_EINVALIDPOINTER; + } + + else { + /* fill in notify object elements */ + pNotifyObj->eventTypes = eventTypes; + pNotifyObj->notifyFxn = notifyFxn; + pNotifyObj->clientArg = clientArg; + + /* place notify object on event notification queue */ + List_put(&PowerCC32XX_module.notifyList, (List_Elem*)pNotifyObj); + } + + DebugP_log3( + "Power: register notify (%p), eventTypes (0x%x), notifyFxn (%p)", + (uintptr_t) pNotifyObj, eventTypes, (uintptr_t) notifyFxn); + + return (status); +} + +/* + * ======== Power_releaseConstraint ======== + * Release a previously declared constraint. + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) +{ + int_fast16_t status = Power_SOK; + uintptr_t key; + uint8_t count; + + /* first ensure constraintId is valid */ + if (constraintId >= PowerCC32XX_NUMCONSTRAINTS) { + status = Power_EINVALIDINPUT; + } + + /* if constraintId is OK ... */ + else { + + /* disable interrupts */ + key = HwiP_disable(); + + /* get the count of the constraint */ + count = PowerCC32XX_module.constraintCounts[constraintId]; + + /* ensure constraint count is not already zero */ + if (count == 0) { + status = Power_EFAIL; + } + + /* if not already zero ... */ + else { + /* decrement the count */ + count--; + + /* save the updated count */ + PowerCC32XX_module.constraintCounts[constraintId] = count; + + /* if constraint count reaches zero, remove constraint from mask */ + if (count == 0) { + PowerCC32XX_module.constraintMask &= ~(1 << constraintId); + } + } + + /* restore interrupts */ + HwiP_restore(key); + + DebugP_log1("Power: release constraint (%d)", constraintId); + } + + return (status); +} + +/* + * ======== Power_releaseDependency ======== + * Release a previously declared dependency. + */ +int_fast16_t Power_releaseDependency(uint_fast16_t resourceId) +{ + int_fast16_t status = Power_SOK; + uint8_t count; + uint32_t id; + uintptr_t key; + + /* first check that resourceId is valid */ + if (resourceId >= PowerCC32XX_NUMRESOURCES) { + status = Power_EINVALIDINPUT; + } + + /* if resourceId is OK ... */ + else { + + /* disable interrupts */ + key = HwiP_disable(); + + /* read the reference count */ + count = PowerCC32XX_module.refCount[resourceId]; + + /* ensure dependency count is not already zero */ + if (count == 0) { + status = Power_EFAIL; + } + + /* if not already zero ... */ + else { + + /* decrement the reference count */ + count--; + + /* if this was the last dependency being released.., */ + if (count == 0) { + /* deactivate this resource ... */ + id = PowerCC32XX_module.dbRecords[resourceId]; + + /* disable clk to peripheral */ + MAP_PRCMPeripheralClkDisable(id, + PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); + } + + /* save the updated count */ + PowerCC32XX_module.refCount[resourceId] = count; + } + + /* restore interrupts */ + HwiP_restore(key); + + DebugP_log1("Power: release dependency (%d)", resourceId); + } + + return (status); +} + +/* + * ======== Power_setConstraint ======== + * Declare an operational constraint. + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId) +{ + int_fast16_t status = Power_SOK; + uintptr_t key; + + /* ensure that constraintId is valid */ + if (constraintId >= PowerCC32XX_NUMCONSTRAINTS) { + status = Power_EINVALIDINPUT; + } + + else { + + /* disable interrupts */ + key = HwiP_disable(); + + /* set the specified constraint in the constraintMask */ + PowerCC32XX_module.constraintMask |= 1 << constraintId; + + /* increment the specified constraint count */ + PowerCC32XX_module.constraintCounts[constraintId]++; + + /* restore interrupts */ + HwiP_restore(key); + + DebugP_log1("Power: set constraint (%d)", constraintId); + } + + return (status); +} + +/* + * ======== Power_setDependency ======== + * Declare a dependency upon a resource. + */ +int_fast16_t Power_setDependency(uint_fast16_t resourceId) +{ + int_fast16_t status = Power_SOK; + uint8_t count; + uint32_t id; + uintptr_t key; + + /* ensure resourceId is valid */ + if (resourceId >= PowerCC32XX_NUMRESOURCES) { + status = Power_EINVALIDINPUT; + } + + /* resourceId is OK ... */ + else { + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and increment reference count */ + count = PowerCC32XX_module.refCount[resourceId]++; + + /* if resource was NOT activated previously ... */ + if (count == 0) { + /* now activate this resource ... */ + id = PowerCC32XX_module.dbRecords[resourceId]; + + /* enable the peripheral clock to the resource */ + MAP_PRCMPeripheralClkEnable(id, + PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); + + /* spin here until status returns TRUE */ + while(!MAP_PRCMPeripheralStatusGet(id)) { + } + } + + /* restore interrupts */ + HwiP_restore(key); + DebugP_log1("Power: set dependency (%d)", resourceId); + } + + return (status); +} + +/* + * ======== Power_setPolicy ======== + * Set the Power policy function + */ +void Power_setPolicy(Power_PolicyFxn policy) +{ + PowerCC32XX_module.policyFxn = policy; +} + +/* + * ======== Power_shutdown ======== + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, + uint_fast32_t shutdownTime) +{ + int_fast16_t status = Power_EFAIL; + uint32_t constraints; + uintptr_t hwiKey; + uint64_t counts; + + /* disable interrupts */ + hwiKey = HwiP_disable(); + + /* make sure shutdown request doesn't violate a constraint */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC32XX_DISALLOW_SHUTDOWN)) { + status = Power_ECHANGE_NOT_ALLOWED; + } + else { + if (PowerCC32XX_module.state == Power_ACTIVE) { + /* set new transition state to entering shutdown */ + PowerCC32XX_module.state = Power_ENTERING_SHUTDOWN; + + /* signal all clients registered for pre-shutdown notification */ + status = notify(PowerCC32XX_ENTERING_SHUTDOWN); + /* check for timeout or any other error */ + if (status != Power_SOK) { + PowerCC32XX_module.state = Power_ACTIVE; + HwiP_restore(hwiKey); + return (status); + } + /* shutdown the flash */ + PowerCC32XX_shutdownSSPI(); + /* if shutdown wakeup time was configured to be large enough */ + if (shutdownTime > (PowerCC32XX_TOTALTIMESHUTDOWN / 1000)) { + /* calculate the wakeup time for hibernate in RTC counts */ + counts = + (((uint64_t)(shutdownTime - + (PowerCC32XX_TOTALTIMESHUTDOWN / 1000)) + * 32768) / 1000); + + /* set the hibernate wakeup time */ + MAP_PRCMHibernateIntervalSet(counts); + + /* enable the wake source to be RTC */ + MAP_PRCMHibernateWakeupSourceEnable(PRCM_HIB_SLOW_CLK_CTR); + } + + /* enable IO retention */ + if (PowerCC32XX_config.ioRetentionShutdown) { + MAP_PRCMIORetentionEnable( + PowerCC32XX_config.ioRetentionShutdown); + } + + DebugP_log2( + "Power: entering shutdown state (%d), shutdownTime (%d)", + shutdownState, shutdownTime); + + /* enter hibernate - we should never return from here */ + MAP_PRCMHibernateEnter(); + } + else { + status = Power_EBUSY; + } + } + + /* set state to Power_ACTIVE */ + PowerCC32XX_module.state = Power_ACTIVE; + + /* re-enable interrupts */ + HwiP_restore(hwiKey); + + /* if get here, failed to shutdown, return error code */ + return (status); +} + +/* + * ======== Power_sleep ======== + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState) +{ + int_fast16_t status = Power_SOK; + uint32_t romMajorVer; + uint32_t romMinorVer; + uint32_t preEvent; + uint32_t postEvent; + bool earlyPG = true; + + /* first validate the sleep state */ + if (sleepState != PowerCC32XX_LPDS) { + status = Power_EINVALIDINPUT; + } + + else if (PowerCC32XX_module.state == Power_ACTIVE) { + + /* set transition state to entering sleep */ + PowerCC32XX_module.state = Power_ENTERING_SLEEP; + + /* setup sleep vars */ + preEvent = PowerCC32XX_ENTERING_LPDS; + postEvent = PowerCC32XX_AWAKE_LPDS; + + /* signal all clients registered for pre-sleep notification */ + status = notify(preEvent); + + /* check for timeout or any other error */ + if (status != Power_SOK) { + PowerCC32XX_module.state = Power_ACTIVE; + return (status); + } + + DebugP_log1("Power: sleep, sleepState (%d)", sleepState); + + /* invoke specific sequence to activate LPDS ...*/ + + /* enable RAM retention */ + MAP_PRCMSRAMRetentionEnable( + PowerCC32XX_config.ramRetentionMaskLPDS, + PRCM_SRAM_LPDS_RET); + + /* call the enter LPDS hook function if configured */ + if (PowerCC32XX_config.enterLPDSHookFxn != NULL) { + (*(PowerCC32XX_config.enterLPDSHookFxn))(); + } + + /* park pins, based upon board file definitions */ + if (PowerCC32XX_config.pinParkDefs != NULL) { + parkPins(); + } + + /* save the NVIC registers */ + saveNVICRegs(); + + /* check if PG >= 2.01 */ + romMajorVer = HWREG(0x00000400) & 0xFFFF; + romMinorVer = HWREG(0x00000400) >> 16; + if ((romMajorVer >= 3) || ((romMajorVer == 2) && (romMinorVer >= 1))) { + earlyPG = false; + } + + /* call sync barrier */ + SYNCBARRIER(); + + /* now enter LPDS - function does not return... */ + if (PowerCC32XX_config.keepDebugActiveDuringLPDS == TRUE) { + if (earlyPG) { + PowerCC32XX_enterLPDS(PRCMLPDSEnterKeepDebugIf); + } + else { + PowerCC32XX_enterLPDS(ROM_PRCMLPDSEnterKeepDebugIfDirect); + } + } + else { + if (earlyPG) { + PowerCC32XX_enterLPDS(PRCMLPDSEnter); + } + else { + PowerCC32XX_enterLPDS(ROM_PRCMLPDSEnterDirect); + } + } + + /* return here after reset, from Power_resumeLPDS() */ + + /* restore NVIC registers */ + restoreNVICRegs(); + + /* restore clock to those peripherals with dependecy set */ + restorePeriphClocks(); + + /* call PRCMCC3200MCUInit() for any necessary post-LPDS restore */ + MAP_PRCMCC3200MCUInit(); + + /* call the resume LPDS hook function if configured */ + if (PowerCC32XX_config.resumeLPDSHookFxn != NULL) { + (*(PowerCC32XX_config.resumeLPDSHookFxn))(); + } + + /* re-enable Slow Clock Counter Interrupt */ + MAP_PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR); + + /* set transition state to EXITING_SLEEP */ + PowerCC32XX_module.state = Power_EXITING_SLEEP; + + /* + * signal clients registered for post-sleep notification; for example, + * a driver that needs to reinitialize its peripheral state, that was + * lost during LPDS + */ + status = notify(postEvent); + + /* restore pins parked before LPDS to their previous states */ + if (PowerCC32XX_config.pinParkDefs != NULL) { + restoreParkedPins(); + } + + /* if wake source was GPIO, optionally call wakeup function */ + if (MAP_PRCMLPDSWakeupCauseGet() == PRCM_LPDS_GPIO) { + if (PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS != NULL) { + (*(PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS)) + (PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg); + } + } + + /* now clear the transition state before re-enabling scheduler */ + PowerCC32XX_module.state = Power_ACTIVE; + } + else { + status = Power_EBUSY; + } + + return (status); +} + +/* + * ======== Power_unregisterNotify ======== + * Unregister for a power notification. + * + */ +void Power_unregisterNotify(Power_NotifyObj * pNotifyObj) +{ + uintptr_t key; + + /* disable interrupts */ + key = HwiP_disable(); + + /* remove notify object from its event queue */ + List_remove(&PowerCC32XX_module.notifyList, (List_Elem *)pNotifyObj); + + /* re-enable interrupts */ + HwiP_restore(key); + + DebugP_log1("Power: unregister notify (%p)", (uintptr_t) pNotifyObj); +} + +/*********************** CC32XX-specific functions **************************/ + +/* + * ======== PowerCC32XX_configureWakeup ======== + * Configure LPDS and shutdown wakeups; copy settings into driver state + */ +void PowerCC32XX_configureWakeup(PowerCC32XX_Wakeup *wakeup) +{ + /* configure network (Host IRQ) as wakeup source for LPDS */ + if (wakeup->enableNetworkWakeupLPDS) { + MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_HOST_IRQ); + } + else { + MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_HOST_IRQ); + } + PowerCC32XX_module.wakeupConfig.enableNetworkWakeupLPDS = + wakeup->enableNetworkWakeupLPDS; + + /* configure GPIO as wakeup source for LPDS */ + if (wakeup->enableGPIOWakeupLPDS) { + MAP_PRCMLPDSWakeUpGPIOSelect( + wakeup->wakeupGPIOSourceLPDS, + wakeup->wakeupGPIOTypeLPDS); + MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_GPIO); + } + else { + MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_GPIO); + } + PowerCC32XX_module.wakeupConfig.enableGPIOWakeupLPDS = + wakeup->enableGPIOWakeupLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceLPDS = + wakeup->wakeupGPIOSourceLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeLPDS = + wakeup->wakeupGPIOTypeLPDS; + + /* configure GPIO as wakeup source for Shutdown */ + if (wakeup->enableGPIOWakeupShutdown) { + MAP_PRCMHibernateWakeUpGPIOSelect( + wakeup->wakeupGPIOSourceShutdown, + wakeup->wakeupGPIOTypeShutdown); + MAP_PRCMHibernateWakeupSourceEnable( + wakeup->wakeupGPIOSourceShutdown); + } + else { + MAP_PRCMHibernateWakeupSourceDisable( + wakeup->wakeupGPIOSourceShutdown); + } + PowerCC32XX_module.wakeupConfig.enableGPIOWakeupShutdown = + wakeup->enableGPIOWakeupShutdown; + PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceShutdown = + wakeup->wakeupGPIOSourceShutdown; + PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeShutdown = + wakeup->wakeupGPIOTypeShutdown; + + /* copy the LPDS GPIO wakeup function and arg to module state */ + PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS = + wakeup->wakeupGPIOFxnLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg = + wakeup->wakeupGPIOFxnLPDSArg; +} + +/* + * ======== PowerCC32XX_disableIORetention ======== + * Disable IO retention and unlock pins after exit from Shutdown + */ +void PowerCC32XX_disableIORetention(unsigned long groupFlags) +{ + MAP_PRCMIORetentionDisable(groupFlags); +} + +/* + * ======== PowerCC32XX_getWakeup ======== + * Get the current LPDS and shutdown wakeup configuration + */ +void PowerCC32XX_getWakeup(PowerCC32XX_Wakeup *wakeup) +{ + *wakeup = PowerCC32XX_module.wakeupConfig; +} + +/* + * ======== PowerCC32XX_parkPin ======== + * Park a device pin in preparation for LPDS + */ +void PowerCC32XX_parkPin(PowerCC32XX_Pin pin, PowerCC32XX_ParkState parkState, + uint32_t * previousType, uint16_t * previousDirection) +{ + unsigned long strength; + unsigned long type; + + /* get the current pin configuration */ + MAP_PinConfigGet(pin, &strength, &type); + + /* stash the current pin type */ + *previousType = type; + + /* get and stash the current pin direction */ + *previousDirection = (uint16_t)MAP_PinDirModeGet(pin); + + /* set pin type to the parking state */ + MAP_PinConfigSet(pin, strength, (unsigned long) parkState); + + /* set pin direction to input to HiZ the pin */ + MAP_PinDirModeSet(pin, PIN_DIR_MODE_IN); +} + +/* + * ======== PowerCC32XX_restoreParkedPin ======== + * Restore a pin that was previously parked with PowerCC32XX_parkPin + */ +void PowerCC32XX_restoreParkedPin(PowerCC32XX_Pin pin, uint32_t type, + uint16_t direction) +{ + unsigned long strength; + unsigned long currentType; + + /* get the current pin configuration */ + MAP_PinConfigGet(pin, &strength, ¤tType); + + /* restore the pin type */ + MAP_PinConfigSet(pin, strength, type); + + /* restore the pin direction */ + MAP_PinDirModeSet(pin, (unsigned long)direction); +} + +/* + * ======== PowerCC32XX_setParkState ======== + * Set a new LPDS park state for a pin + */ +void PowerCC32XX_setParkState(PowerCC32XX_Pin pin, uint32_t level) +{ + PowerCC32XX_ParkInfo parkInfo; + PowerCC32XX_ParkState state; + uint32_t i; + + DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); + + /* if ES2.00 or later, drive the pin */ + if((HWREG(0x00000400) & 0xFFFF) >= 2) { + state = (level) ? PowerCC32XX_DRIVE_HIGH : PowerCC32XX_DRIVE_LOW; + } + /* else, for earlier devices use the weak pull resistor */ + else { + state = (level) ? PowerCC32XX_WEAK_PULL_UP_STD : + PowerCC32XX_WEAK_PULL_DOWN_STD; + } + + /* step thru the park array until find the pin to be updated */ + for (i = 0; i < PowerCC32XX_config.numPins; i++) { + + parkInfo = PowerCC32XX_config.pinParkDefs[i]; + + /* if this is the pin to be updated... */ + if (parkInfo.pin == pin) { + parkInfo.parkState = state; + PowerCC32XX_config.pinParkDefs[i] = parkInfo; + break; + } + } +} +/* + * ======== PowerCC32XX_shutdownSSPI ======== + * Put SPI flash into Deep Power Down mode + */ +void PowerCC32XX_shutdownSSPI(void) +{ + unsigned long status = 0; + + /* Acquire SSPI HwSpinlock. */ + if (0 != MAP_HwSpinLockTryAcquire(HWSPINLOCK_SSPI, PowerCC32XX_SSPISemaphoreTakeTries)){ + return; + } + + /* Enable clock for SSPI module */ + MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK); + + /* Reset SSPI at PRCM level and wait for reset to complete */ + MAP_PRCMPeripheralReset(PRCM_SSPI); + while(MAP_PRCMPeripheralStatusGet(PRCM_SSPI)== false){ + } + + /* Reset SSPI at module level */ + MAP_SPIReset(SSPI_BASE); + + /* Configure SSPI module */ + MAP_SPIConfigSetExpClk(SSPI_BASE,PRCMPeripheralClockGet(PRCM_SSPI), + 20000000,SPI_MODE_MASTER,SPI_SUB_MODE_0, + (SPI_SW_CTRL_CS | + SPI_4PIN_MODE | + SPI_TURBO_OFF | + SPI_CS_ACTIVELOW | + SPI_WL_8)); + + /* Enable SSPI module */ + MAP_SPIEnable(SSPI_BASE); + + /* Enable chip select for the spi flash. */ + MAP_SPICSEnable(SSPI_BASE); + + /* Wait for spi flash. */ + do{ + /* Send status register read instruction and read back a dummy byte. */ + MAP_SPIDataPut(SSPI_BASE,PowerCC32XX_SSPIReadStatusInstruction); + MAP_SPIDataGet(SSPI_BASE,&status); + + /* Write a dummy byte then read back the actual status. */ + MAP_SPIDataPut(SSPI_BASE,0xFF); + MAP_SPIDataGet(SSPI_BASE,&status); + } while((status & 0xFF )== STATUS_BUSY); + + /* Disable chip select for the spi flash. */ + MAP_SPICSDisable(SSPI_BASE); + + /* Start another CS enable sequence for Power down command. */ + MAP_SPICSEnable(SSPI_BASE); + + /* Send Deep Power Down command to spi flash */ + MAP_SPIDataPut(SSPI_BASE,PowerCC32XX_SSPIPowerDownInstruction); + + /* Disable chip select for the spi flash. */ + MAP_SPICSDisable(SSPI_BASE); + + /* Release SSPI HwSpinlock. */ + MAP_HwSpinLockRelease(HWSPINLOCK_SSPI); + + return; +} + +/*************************internal functions ****************************/ + +/* + * ======== notify ======== + * Note: When this function is called hardware interrupts are disabled + */ +static int_fast16_t notify(uint_fast16_t eventType) +{ + int_fast16_t notifyStatus; + Power_NotifyFxn notifyFxn; + uintptr_t clientArg; + List_Elem *elem; + + /* if queue is empty, return immediately */ + if (!List_empty(&PowerCC32XX_module.notifyList)) { + /* point to first client notify object */ + elem = List_head(&PowerCC32XX_module.notifyList); + + /* walk the queue and notify each registered client of the event */ + do { + if (((Power_NotifyObj *)elem)->eventTypes & eventType) { + /* pull params from notify object */ + notifyFxn = ((Power_NotifyObj *)elem)->notifyFxn; + clientArg = ((Power_NotifyObj *)elem)->clientArg; + + /* call the client's notification function */ + notifyStatus = (int_fast16_t) (*(Power_NotifyFxn)notifyFxn)( + eventType, 0, clientArg); + + /* if client declared error stop all further notifications */ + if (notifyStatus != Power_NOTIFYDONE) { + return (Power_EFAIL); + } + } + + /* get next element in the notification queue */ + elem = List_next(elem); + + } while (elem != NULL); + } + + return (Power_SOK); +} + +/* + * ======== restoreNVICRegs ======== + * Restore the NVIC registers + */ +static void restoreNVICRegs(void) +{ + uint32_t i; + uint32_t *base_reg_addr; + + /* Restore the NVIC control registers */ + HWREG(NVIC_VTABLE) = PowerCC32XX_contextSave.nvicRegs.vectorTable; + HWREG(NVIC_ACTLR) = PowerCC32XX_contextSave.nvicRegs.auxCtrl; + HWREG(NVIC_APINT) = PowerCC32XX_contextSave.nvicRegs.appInt; + HWREG(NVIC_INT_CTRL) = PowerCC32XX_contextSave.nvicRegs.intCtrlState; + HWREG(NVIC_SYS_CTRL) = PowerCC32XX_contextSave.nvicRegs.sysCtrl; + HWREG(NVIC_CFG_CTRL) = PowerCC32XX_contextSave.nvicRegs.configCtrl; + HWREG(NVIC_SYS_PRI1) = PowerCC32XX_contextSave.nvicRegs.sysPri1; + HWREG(NVIC_SYS_PRI2) = PowerCC32XX_contextSave.nvicRegs.sysPri2; + HWREG(NVIC_SYS_PRI3) = PowerCC32XX_contextSave.nvicRegs.sysPri3; + HWREG(NVIC_SYS_HND_CTRL) = PowerCC32XX_contextSave.nvicRegs.sysHcrs; + + /* Systick registers */ + HWREG(NVIC_ST_CTRL) = PowerCC32XX_contextSave.nvicRegs.systickCtrl; + HWREG(NVIC_ST_RELOAD) = PowerCC32XX_contextSave.nvicRegs.systickReload; + HWREG(NVIC_ST_CAL) = PowerCC32XX_contextSave.nvicRegs.systickCalib; + + /* Restore the interrupt priority registers */ + base_reg_addr = (uint32_t *)NVIC_PRI0; + for(i = 0; i < PowerCC32XX_numNVICIntPriority; i++) { + base_reg_addr[i] = PowerCC32XX_contextSave.nvicRegs.intPriority[i]; + } + + /* Restore the interrupt enable registers */ + base_reg_addr = (uint32_t *)NVIC_EN0; + for(i = 0; i < PowerCC32XX_numNVICSetEnableRegs; i++) { + base_reg_addr[i] = PowerCC32XX_contextSave.nvicRegs.intSetEn[i]; + } + + /* Data and instruction sync barriers */ + SYNCBARRIER(); +} + +/* + * ======== restorePeriphClocks ======== + * Restores the peripheral clocks that had dependency set + */ +static void restorePeriphClocks(void) +{ + uint32_t dependCount; + uint32_t i; + + /* need to re-enable peripheral clocks to those with set dependency */ + for (i = 0; i < PowerCC32XX_NUMRESOURCES; i++) { + dependCount = Power_getDependencyCount(i); + if (dependCount > 0) { + MAP_PRCMPeripheralClkEnable(PowerCC32XX_module.dbRecords[i], + PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); + + while(!MAP_PRCMPeripheralStatusGet(PowerCC32XX_module.dbRecords[i])) { + } + } + } +} + +/* + * ======== saveNVICRegs ======== + * Save away the NVIC registers for LPDS mode. + */ +static void saveNVICRegs(void) +{ + uint32_t i; + uint32_t *base_reg_addr; + + /* Save the NVIC control registers */ + PowerCC32XX_contextSave.nvicRegs.vectorTable = HWREG(NVIC_VTABLE); + PowerCC32XX_contextSave.nvicRegs.auxCtrl = HWREG(NVIC_ACTLR); + PowerCC32XX_contextSave.nvicRegs.intCtrlState = HWREG(NVIC_INT_CTRL); + PowerCC32XX_contextSave.nvicRegs.appInt = HWREG(NVIC_APINT); + PowerCC32XX_contextSave.nvicRegs.sysCtrl = HWREG(NVIC_SYS_CTRL); + PowerCC32XX_contextSave.nvicRegs.configCtrl = HWREG(NVIC_CFG_CTRL); + PowerCC32XX_contextSave.nvicRegs.sysPri1 = HWREG(NVIC_SYS_PRI1); + PowerCC32XX_contextSave.nvicRegs.sysPri2 = HWREG(NVIC_SYS_PRI2); + PowerCC32XX_contextSave.nvicRegs.sysPri3 = HWREG(NVIC_SYS_PRI3); + PowerCC32XX_contextSave.nvicRegs.sysHcrs = HWREG(NVIC_SYS_HND_CTRL); + + /* Systick registers */ + PowerCC32XX_contextSave.nvicRegs.systickCtrl = HWREG(NVIC_ST_CTRL); + PowerCC32XX_contextSave.nvicRegs.systickReload = HWREG(NVIC_ST_RELOAD); + PowerCC32XX_contextSave.nvicRegs.systickCalib = HWREG(NVIC_ST_CAL); + + /* Save the interrupt enable registers */ + base_reg_addr = (uint32_t *)NVIC_EN0; + for (i = 0; i < PowerCC32XX_numNVICSetEnableRegs; i++) { + PowerCC32XX_contextSave.nvicRegs.intSetEn[i] = base_reg_addr[i]; + } + + /* Save the interrupt priority registers */ + base_reg_addr = (uint32_t *)NVIC_PRI0; + for (i = 0; i < PowerCC32XX_numNVICIntPriority; i++) { + PowerCC32XX_contextSave.nvicRegs.intPriority[i] = base_reg_addr[i]; + } +} + +/* + * ======== parkPins ======== + */ +static void parkPins(void) +{ + PowerCC32XX_ParkInfo parkInfo; + uint32_t antpadreg; + uint32_t i; + + DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); + + /* for each pin in the park array ... */ + for (i = 0; i < PowerCC32XX_config.numPins; i++) { + + parkInfo = PowerCC32XX_config.pinParkDefs[i]; + + /* skip this pin if "don't park" is specified */ + if (parkInfo.parkState == PowerCC32XX_DONT_PARK) { + continue; + } + + /* if this is a special antenna select pin, stash current pad state */ + if (parkInfo.pin == PowerCC32XX_PIN29) { + antpadreg = 0x4402E108; + PowerCC32XX_module.stateAntPin29 = (uint16_t) HWREG(antpadreg); + } + else if (parkInfo.pin == PowerCC32XX_PIN30) { + antpadreg = 0x4402E10C; + PowerCC32XX_module.stateAntPin30 = (uint16_t) HWREG(antpadreg); + } + else { + antpadreg = 0; + } + + /* if this is antenna select pin, park via direct writes to pad reg */ + if (antpadreg != 0) { + HWREG(antpadreg) &= 0xFFFFF0EF; /* first clear bits 4, 8-11 */ + if (parkInfo.parkState == PowerCC32XX_NO_PULL_HIZ) { + HWREG(antpadreg) |= 0x00000C00; + } + else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_UP_STD) { + HWREG(antpadreg) |= 0x00000D00; + } + else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_DOWN_STD) { + HWREG(antpadreg) |= 0x00000E00; + } + else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_UP_OPENDRAIN) { + HWREG(antpadreg) |= 0x00000D10; + } + else if (parkInfo.parkState == + PowerCC32XX_WEAK_PULL_DOWN_OPENDRAIN) { + HWREG(antpadreg) |= 0x00000E10; + } + } + + /* else, for all other pins */ + else { + + /* if pin is NOT to be driven, park it to the specified state... */ + if ((parkInfo.parkState != PowerCC32XX_DRIVE_LOW) && + (parkInfo.parkState != PowerCC32XX_DRIVE_HIGH)) { + + PowerCC32XX_parkPin( + (PowerCC32XX_Pin)parkInfo.pin, + (PowerCC32XX_ParkState)parkInfo.parkState, + &PowerCC32XX_module.pinType[i], + &PowerCC32XX_module.pinDir[i]); + } + + /* + * else, now check if the pin CAN be driven (pins 45, 53, and 55 + * can't be driven) + */ + else if ((parkInfo.pin != PowerCC32XX_PIN45) && + (parkInfo.pin != PowerCC32XX_PIN53) && + (parkInfo.pin != PowerCC32XX_PIN55)){ + + /* + * must ensure pin mode is zero; first get/stash current mode, + * then set mode to zero + */ + PowerCC32XX_module.pinMode[i] = + (uint8_t)MAP_PinModeGet(parkInfo.pin); + MAP_PinModeSet(parkInfo.pin, 0); + + /* if pin is to be driven low, set the lock level to 0 */ + if (parkInfo.parkState == PowerCC32XX_DRIVE_LOW) { + MAP_PinLockLevelSet((PowerCC32XX_Pin)parkInfo.pin, 0); + PowerCC32XX_module.pinLockMask |= 1 << + PinToPadGet(parkInfo.pin); + } + + /* else, pin to be driven high, set lock level to 1 */ + else { + MAP_PinLockLevelSet((PowerCC32XX_Pin)parkInfo.pin, 1); + PowerCC32XX_module.pinLockMask |= 1 << + PinToPadGet(parkInfo.pin); + } + } + } + } + + /* if any pins are to be driven, lock them now */ + if (PowerCC32XX_module.pinLockMask) { + MAP_PinLock(PowerCC32XX_module.pinLockMask); + } +} + +/* + * ======== restoreParkedPins ======== + */ +static void restoreParkedPins(void) +{ + PowerCC32XX_ParkInfo parkInfo; + uint32_t i; + + DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); + + /* first, unlock any locked pins (that were driven high or low) */ + if (PowerCC32XX_module.pinLockMask) { + MAP_PinUnlock(); + } + + /* now, for each pin in the park array ... */ + for (i = 0; i < PowerCC32XX_config.numPins; i++) { + + parkInfo = PowerCC32XX_config.pinParkDefs[i]; + + /* skip this pin if "don't park" is specified */ + if (parkInfo.parkState == PowerCC32XX_DONT_PARK) { + continue; + } + + /* if this is special antenna select pin: restore the saved pad state */ + if (parkInfo.pin == PowerCC32XX_PIN29) { + HWREG(0x4402E108) = ((HWREG(0x4402E108) & 0xFFFFF000) | + (PowerCC32XX_module.stateAntPin29 & 0x00000FFF)); + } + + else if (parkInfo.pin == PowerCC32XX_PIN30) { + HWREG(0x4402E10C) = ((HWREG(0x4402E10C) & 0xFFFFF000) | + (PowerCC32XX_module.stateAntPin30 & 0x00000FFF)); + } + + /* else if pin was driven during LPDS, restore the pin mode */ + else if ((parkInfo.parkState == PowerCC32XX_DRIVE_LOW) || + (parkInfo.parkState == PowerCC32XX_DRIVE_HIGH)) { + MAP_PinModeSet(parkInfo.pin, + (unsigned long)PowerCC32XX_module.pinMode[i]); + } + + /* else, restore all others */ + else { + /* if pin parked in a non-driven state, restore type & direction */ + if ((parkInfo.parkState != PowerCC32XX_DRIVE_LOW) && + (parkInfo.parkState != PowerCC32XX_DRIVE_HIGH)) { + + PowerCC32XX_restoreParkedPin( + (PowerCC32XX_Pin)parkInfo.pin, + PowerCC32XX_module.pinType[i], + PowerCC32XX_module.pinDir[i]); + } + } + } +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/power/PowerCC32XX.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/power/PowerCC32XX.h new file mode 100644 index 000000000..332e2fa34 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/power/PowerCC32XX.h @@ -0,0 +1,636 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PowerCC32XX.h + * + * @brief Power manager interface for the CC32XX + * + * The Power header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref Power.h for a complete description of APIs. + * + * ## Implementation # + * This module defines the power resources, constraints, events, sleep + * states and transition latencies for CC32XX. + * + * A reference power policy is provided which can transition the MCU from the + * active state to one of two sleep states: LPDS or Sleep. + * The policy looks at the estimated idle time remaining, and the active + * constraints, and determine which sleep state to transition to. The + * policy will give first preference to choosing LPDS, but if that is not + * appropriate (e.g., not enough idle time), it will choose Sleep. + * + * ============================================================================ + */ + +#ifndef ti_drivers_power_PowerCC32XX__include +#define ti_drivers_power_PowerCC32XX__include + +#include +#include +#include + +/* driverlib header files */ +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* latency values were measured with a logic analyzer, and rounded up */ + +/*! The latency to reserve for resuming from LPDS (usec) */ +#define PowerCC32XX_RESUMETIMELPDS 2500 + +/*! The total latency to reserve for entry to and exit from LPDS (usec) */ +#define PowerCC32XX_TOTALTIMELPDS 20000 + +/*! The total latency to reserve for entry to and exit from Shutdown (usec) */ +#define PowerCC32XX_TOTALTIMESHUTDOWN 500000 + +/* Power resources */ +#define PowerCC32XX_PERIPH_CAMERA 0 +/*!< Resource ID: Camera */ + +#define PowerCC32XX_PERIPH_I2S 1 +/*!< Resource ID: I2S */ + +#define PowerCC32XX_PERIPH_SDHOST 2 +/*!< Resource ID: SDHost */ + +#define PowerCC32XX_PERIPH_GSPI 3 +/*!< Resource ID: General Purpose SPI (GSPI) */ + +#define PowerCC32XX_PERIPH_LSPI 4 +/*!< Resource ID: LSPI */ + +#define PowerCC32XX_PERIPH_UDMA 5 +/*!< Resource ID: uDMA Controller */ + +#define PowerCC32XX_PERIPH_GPIOA0 6 +/*!< Resource ID: General Purpose I/O Port A0 */ + +#define PowerCC32XX_PERIPH_GPIOA1 7 +/*!< Resource ID: General Purpose I/O Port A1 */ + +#define PowerCC32XX_PERIPH_GPIOA2 8 +/*!< Resource ID: General Purpose I/O Port A2 */ + +#define PowerCC32XX_PERIPH_GPIOA3 9 +/*!< Resource ID: General Purpose I/O Port A3 */ + +#define PowerCC32XX_PERIPH_GPIOA4 10 +/*!< Resource ID: General Purpose I/O Port A4 */ + +#define PowerCC32XX_PERIPH_WDT 11 +/*!< Resource ID: Watchdog module */ + +#define PowerCC32XX_PERIPH_UARTA0 12 +/*!< Resource ID: UART 0 */ + +#define PowerCC32XX_PERIPH_UARTA1 13 +/*!< Resource ID: UART 1 */ + +#define PowerCC32XX_PERIPH_TIMERA0 14 +/*!< Resource ID: General Purpose Timer A0 */ + +#define PowerCC32XX_PERIPH_TIMERA1 15 +/*!< Resource ID: General Purpose Timer A1 */ + +#define PowerCC32XX_PERIPH_TIMERA2 16 +/*!< Resource ID: General Purpose Timer A2 */ + +#define PowerCC32XX_PERIPH_TIMERA3 17 +/*!< Resource ID: General Purpose Timer A3 */ + +#define PowerCC32XX_PERIPH_DTHE 18 +/*!< Resource ID: Cryptography Accelerator (DTHE) */ + +#define PowerCC32XX_PERIPH_SSPI 19 +/*!< Resource ID: Serial Flash SPI (SSPI) */ + +#define PowerCC32XX_PERIPH_I2CA0 20 +/*!< Resource ID: I2C */ + +/* \cond */ +#define PowerCC32XX_NUMRESOURCES 21 /* Number of resources in database */ +/* \endcond */ + +/* + * Power constraints on the CC32XX device + */ +#define PowerCC32XX_DISALLOW_LPDS 0 +/*!< Constraint: Disallow entry to Low Power Deep Sleep (LPDS) */ + +#define PowerCC32XX_DISALLOW_SHUTDOWN 1 +/*!< Constraint: Disallow entry to Shutdown */ + +/* \cond */ +#define PowerCC32XX_NUMCONSTRAINTS 2 /*!< number of constraints */ +/* \endcond */ + +/* + * Power events on the CC32XX device + * + * Each event must be a power of two, and the event IDs must be sequential + * without any gaps. + */ +#define PowerCC32XX_ENTERING_LPDS 0x1 +/*!< Power event: The device is entering the LPDS sleep state */ + +#define PowerCC32XX_ENTERING_SHUTDOWN 0x2 +/*!< Power event: The device is entering the Shutdown state */ + +#define PowerCC32XX_AWAKE_LPDS 0x4 +/*!< Power event: The device is waking from the LPDS sleep state */ + +/* \cond */ +#define PowerCC32XX_NUMEVENTS 3 /*!< number of events */ +/* \endcond */ + +/* Power sleep states */ +#define PowerCC32XX_LPDS 0x1 /*!< The LPDS sleep state */ + +/* \cond */ +/* Use by NVIC Register structure */ +#define PowerCC32XX_numNVICSetEnableRegs 6 +#define PowerCC32XX_numNVICIntPriority 49 +/* \endcond */ + +/* \cond */ +/* Number of pins that can be parked in LPDS */ +#define PowerCC32XX_NUMPINS 34 +/* \endcond */ + +/*! @brief Used to specify parking of a pin during LPDS */ +typedef struct PowerCC32XX_ParkInfo { + uint32_t pin; + /*!< The pin to be parked */ + uint32_t parkState; + /*!< The state to park the pin (an enumerated PowerCC32XX_ParkState) */ +} PowerCC32XX_ParkInfo; + +/*! @brief Power global configuration */ +typedef struct PowerCC32XX_ConfigV1 { + /*! Initialization function for the power policy */ + Power_PolicyInitFxn policyInitFxn; + /*! The power policy function */ + Power_PolicyFxn policyFxn; + /*! + * @brief Hook function called before entering LPDS + * + * This function is called after any notifications are complete, + * and before any pins are parked, just before entry to LPDS. + */ + void (*enterLPDSHookFxn)(void); + /*! + * @brief Hook function called when resuming from LPDS + * + * This function is called early in the wake sequence, before any + * notification functions are run. + */ + void (*resumeLPDSHookFxn)(void); + /*! Determines whether to run the power policy function */ + bool enablePolicy; + /*! Enable GPIO as a wakeup source for LPDS */ + bool enableGPIOWakeupLPDS; + /*! Enable GPIO as a wakeup source for shutdown */ + bool enableGPIOWakeupShutdown; + /*! Enable Network activity as a wakeup source for LPDS */ + bool enableNetworkWakeupLPDS; + /*! + * @brief The GPIO source for wakeup from LPDS + * + * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source + * for LPDS. The GPIO must be specified as one of the following (as + * defined in driverlib/prcm.h): PRCM_LPDS_GPIO2, PRCM_LPDS_GPIO4, + * PRCM_LPDS_GPIO11, PRCM_LPDS_GPIO13, PRCM_LPDS_GPIO17, PRCM_LPDS_GPIO24, + * PRCM_LPDS_GPIO26 + */ + uint32_t wakeupGPIOSourceLPDS; + /*! + * @brief The GPIO trigger type for wakeup from LPDS + * + * Value can be one of the following (defined in driverlib/prcm.h): + * PRCM_LPDS_LOW_LEVEL, PRCM_LPDS_HIGH_LEVEL, + * PRCM_LPDS_FALL_EDGE, PRCM_LPDS_RISE_EDGE + */ + uint32_t wakeupGPIOTypeLPDS; + /*! + * @brief Function to be called when the configured GPIO triggers wakeup + * from LPDS + * + * During LPDS the internal GPIO module is powered off, and special + * periphery logic is used instead to detect the trigger and wake the + * device. No GPIO interrupt service routine will be triggered in this + * case (even if an ISR is configured, and used normally to detect GPIO + * interrupts when not in LPDS). This function can be used in lieu of a + * GPIO ISR, to take specific action upon LPDS wakeup. + * + * A value of NULL indicates no GPIO wakeup function will be called. + * + * An argument for this wakeup function can be specified via + * wakeupGPIOFxnLPDSArg. + * + * Note that this wakeup function will be called as one of the last steps + * in Power_sleep(), after all notifications have been sent out, and after + * pins have been restored to their previous (non-parked) states. + */ + void (*wakeupGPIOFxnLPDS)(uint_least8_t argument); + /*! + * @brief The argument to be passed to wakeupGPIOFxnLPDS() + */ + uint_least8_t wakeupGPIOFxnLPDSArg; + /*! + * @brief The GPIO sources for wakeup from shutdown + * + * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source + * for Shutdown. The GPIO must be specified as one of the following (as + * defined in driverlib/prcm.h): PRCM_HIB_GPIO2, PRCM_HIB_GPIO4, + * PRCM_HIB_GPIO11, PRCM_HIB_GPIO13, PRCM_HIB_GPIO17, PRCM_HIB_GPIO24, + * PRCM_HIB_GPIO26 + */ + uint32_t wakeupGPIOSourceShutdown; + /*! + * @brief The GPIO trigger type for wakeup from shutdown + * + * Value can be one of the following (defined in driverlib/prcm.h): + * PRCM_HIB_LOW_LEVEL, PRCM_HIB_HIGH_LEVEL, + * PRCM_HIB_FALL_EDGE, PRCM_HIB_RISE_EDGE + */ + uint32_t wakeupGPIOTypeShutdown; + /*! + * @brief SRAM retention mask for LPDS + * + * Value can be a mask of the following (defined in driverlib/prcm.h): + * PRCM_SRAM_COL_1, PRCM_SRAM_COL_2, PRCM_SRAM_COL_3, + * PRCM_SRAM_COL_4 + */ + uint32_t ramRetentionMaskLPDS; + /*! + * @brief Keep debug interface active during LPDS + * + * This Boolean controls whether the debug interface will be left active + * when LPDS is entered. For best power savings this flag should be set + * to false. Setting the flag to true will enable better debug + * capability, but will prevent full LPDS, and will result in increased + * power consumption. + */ + bool keepDebugActiveDuringLPDS; + /*! + * @brief IO retention mask for Shutdown + * + * Value can be a mask of the following (defined in driverlib/prcm.h): + * PRCM_IO_RET_GRP_0, PRCM_IO_RET_GRP_1, PRCM_IO_RET_GRP_2 + * PRCM_IO_RET_GRP_3 + */ + uint32_t ioRetentionShutdown; + /*! + * @brief Pointer to an array of pins to be parked during LPDS + * + * A value of NULL will disable parking of any pins during LPDS + */ + PowerCC32XX_ParkInfo * pinParkDefs; + /*! + * @brief Number of pins to be parked during LPDS + */ + uint32_t numPins; +} PowerCC32XX_ConfigV1; + +/*! + * @cond NODOC + * NVIC registers that need to be saved before entering LPDS. + */ +typedef struct PowerCC32XX_NVICRegisters { + uint32_t vectorTable; + uint32_t auxCtrl; + uint32_t intCtrlState; + uint32_t appInt; + uint32_t sysCtrl; + uint32_t configCtrl; + uint32_t sysPri1; + uint32_t sysPri2; + uint32_t sysPri3; + uint32_t sysHcrs; + uint32_t systickCtrl; + uint32_t systickReload; + uint32_t systickCalib; + uint32_t intSetEn[PowerCC32XX_numNVICSetEnableRegs]; + uint32_t intPriority[PowerCC32XX_numNVICIntPriority]; +} PowerCC32XX_NVICRegisters; +/*! @endcond */ + +/*! + * @cond NODOC + * MCU core registers that need to be save before entering LPDS. + */ +typedef struct PowerCC32XX_MCURegisters { + uint32_t msp; + uint32_t psp; + uint32_t psr; + uint32_t primask; + uint32_t faultmask; + uint32_t basepri; + uint32_t control; +} PowerCC32XX_MCURegisters; +/*! @endcond */ + +/*! + * @cond NODOC + * Structure of context registers to save before entering LPDS. + */ +typedef struct PowerCC32XX_SaveRegisters { + PowerCC32XX_MCURegisters m4Regs; + PowerCC32XX_NVICRegisters nvicRegs; +} PowerCC32XX_SaveRegisters; +/*! @endcond */ + +/*! @brief Enumeration of states a pin can be parked in */ +typedef enum { + /*! No pull resistor, leave pin in a HIZ state */ + PowerCC32XX_NO_PULL_HIZ = PIN_TYPE_STD, + /*! Pull-up resistor for standard pin type */ + PowerCC32XX_WEAK_PULL_UP_STD = PIN_TYPE_STD_PU, + /*! Pull-down resistor for standard pin type */ + PowerCC32XX_WEAK_PULL_DOWN_STD = PIN_TYPE_STD_PD, + /*! Pull-up resistor for open drain pin type */ + PowerCC32XX_WEAK_PULL_UP_OPENDRAIN = PIN_TYPE_OD_PU, + /*! Pull-down resistor for open drain pin type */ + PowerCC32XX_WEAK_PULL_DOWN_OPENDRAIN = PIN_TYPE_OD_PD, + /*! Drive pin to a low logic state */ + PowerCC32XX_DRIVE_LOW, + /*! Drive pin to a high logic state */ + PowerCC32XX_DRIVE_HIGH, + /*! Take no action; do not park the pin */ + PowerCC32XX_DONT_PARK +} PowerCC32XX_ParkState; + +/*! @brief Enumeration of pins that can be parked */ +typedef enum { + /*! PIN_01 */ + PowerCC32XX_PIN01 = PIN_01, + /*! PIN_02 */ + PowerCC32XX_PIN02 = PIN_02, + /*! PIN_03 */ + PowerCC32XX_PIN03 = PIN_03, + /*! PIN_04 */ + PowerCC32XX_PIN04 = PIN_04, + /*! PIN_05 */ + PowerCC32XX_PIN05 = PIN_05, + /*! PIN_06 */ + PowerCC32XX_PIN06 = PIN_06, + /*! PIN_07 */ + PowerCC32XX_PIN07 = PIN_07, + /*! PIN_08 */ + PowerCC32XX_PIN08 = PIN_08, + /*! PIN_11 */ + PowerCC32XX_PIN11 = PIN_11, + /*! PIN_12 */ + PowerCC32XX_PIN12 = PIN_12, + /*! PIN_13 */ + PowerCC32XX_PIN13 = PIN_13, + /*! PIN_14 */ + PowerCC32XX_PIN14 = PIN_14, + /*! PIN_15 */ + PowerCC32XX_PIN15 = PIN_15, + /*! PIN_16 */ + PowerCC32XX_PIN16 = PIN_16, + /*! PIN_17 */ + PowerCC32XX_PIN17 = PIN_17, + /*! PIN_18 */ + PowerCC32XX_PIN18 = PIN_18, + /*! PIN_19 */ + PowerCC32XX_PIN19 = PIN_19, + /*! PIN_20 */ + PowerCC32XX_PIN20 = PIN_20, + /*! PIN_21 */ + PowerCC32XX_PIN21 = PIN_21, + /*! PIN_29 */ + PowerCC32XX_PIN29 = 0x1C, + /*! PIN_30 */ + PowerCC32XX_PIN30 = 0x1D, + /*! PIN_45 */ + PowerCC32XX_PIN45 = PIN_45, + /*! PIN_50 */ + PowerCC32XX_PIN50 = PIN_50, + /*! PIN_52 */ + PowerCC32XX_PIN52 = PIN_52, + /*! PIN_53 */ + PowerCC32XX_PIN53 = PIN_53, + /*! PIN_55 */ + PowerCC32XX_PIN55 = PIN_55, + /*! PIN_57 */ + PowerCC32XX_PIN57 = PIN_57, + /*! PIN_58 */ + PowerCC32XX_PIN58 = PIN_58, + /*! PIN_59 */ + PowerCC32XX_PIN59 = PIN_59, + /*! PIN_60 */ + PowerCC32XX_PIN60 = PIN_60, + /*! PIN_61 */ + PowerCC32XX_PIN61 = PIN_61, + /*! PIN_62 */ + PowerCC32XX_PIN62 = PIN_62, + /*! PIN_63 */ + PowerCC32XX_PIN63 = PIN_63, + /*! PIN_64 */ + PowerCC32XX_PIN64 = PIN_64 +} PowerCC32XX_Pin; + +/*! + * @brief Specify the wakeup sources for LPDS and Shutdown + * + * The wakeup sources for LPDS and Shutdown can be dynamically changed + * at runtime, via PowerCC32XX_configureWakeup(). The application + * should fill a structure of this type, and pass it as the parameter + * to PowerCC32XX_configureWakeup() to specify the new wakeup settings. + */ +typedef struct PowerCC32XX_Wakeup { + /*! Enable GPIO as a wakeup source for LPDS */ + bool enableGPIOWakeupLPDS; + /*! Enable GPIO as a wakeup source for shutdown */ + bool enableGPIOWakeupShutdown; + /*! Enable Network activity as a wakeup source for LPDS */ + bool enableNetworkWakeupLPDS; + /*! + * @brief The GPIO source for wakeup from LPDS + * + * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source + * for LPDS. The GPIO must be specified as one of the following (as + * defined in driverlib/prcm.h): PRCM_LPDS_GPIO2, PRCM_LPDS_GPIO4, + * PRCM_LPDS_GPIO11, PRCM_LPDS_GPIO13, PRCM_LPDS_GPIO17, PRCM_LPDS_GPIO24, + * PRCM_LPDS_GPIO26 + */ + uint32_t wakeupGPIOSourceLPDS; + /*! + * @brief The GPIO trigger type for wakeup from LPDS + * + * Value can be one of the following (defined in driverlib/prcm.h): + * PRCM_LPDS_LOW_LEVEL, PRCM_LPDS_HIGH_LEVEL, + * PRCM_LPDS_FALL_EDGE, PRCM_LPDS_RISE_EDGE + */ + uint32_t wakeupGPIOTypeLPDS; + /*! + * @brief Function to be called when the configured GPIO triggers wakeup + * from LPDS + * + * During LPDS the internal GPIO module is powered off, and special + * periphery logic is used instead to detect the trigger and wake the + * device. No GPIO interrupt service routine will be triggered in this + * case (even if an ISR is configured, and used normally to detect GPIO + * interrupts when not in LPDS). This function can be used in lieu of a + * GPIO ISR, to take specific action upon LPDS wakeup. + * + * A value of NULL indicates no GPIO wakeup function will be called. + * + * An argument for this wakeup function can be specified via + * wakeupGPIOFxnLPDSArg. + * + * Note that this wakeup function will be called as one of the last steps + * in Power_sleep(), after all notifications have been sent out, and after + * pins have been restored to their previous (non-parked) states. + */ + void (*wakeupGPIOFxnLPDS)(uint_least8_t argument); + /*! + * @brief The argument to be passed to wakeupGPIOFxnLPDS() + */ + uint_least8_t wakeupGPIOFxnLPDSArg; + /*! + * @brief The GPIO sources for wakeup from shutdown + * + * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source + * for Shutdown. The GPIO must be specified as one of the following (as + * defined in driverlib/prcm.h): PRCM_HIB_GPIO2, PRCM_HIB_GPIO4, + * PRCM_HIB_GPIO11, PRCM_HIB_GPIO13, PRCM_HIB_GPIO17, PRCM_HIB_GPIO24, + * PRCM_HIB_GPIO26 + */ + uint32_t wakeupGPIOSourceShutdown; + /*! + * @brief The GPIO trigger type for wakeup from shutdown + * + * Value can be one of the following (defined in driverlib/prcm.h): + * PRCM_HIB_LOW_LEVEL, PRCM_HIB_HIGH_LEVEL, + * PRCM_HIB_FALL_EDGE, PRCM_HIB_RISE_EDGE + */ + uint32_t wakeupGPIOTypeShutdown; +} PowerCC32XX_Wakeup; + +/*! + * @cond NODOC + * Internal structure defining Power module state. + */ +typedef struct PowerCC32XX_ModuleState { + List_List notifyList; + uint32_t constraintMask; + uint32_t state; + uint16_t dbRecords[PowerCC32XX_NUMRESOURCES]; + bool enablePolicy; + bool initialized; + uint8_t refCount[PowerCC32XX_NUMRESOURCES]; + uint8_t constraintCounts[PowerCC32XX_NUMCONSTRAINTS]; + Power_PolicyFxn policyFxn; + uint32_t pinType[PowerCC32XX_NUMPINS]; + uint16_t pinDir[PowerCC32XX_NUMPINS]; + uint8_t pinMode[PowerCC32XX_NUMPINS]; + uint16_t stateAntPin29; + uint16_t stateAntPin30; + uint32_t pinLockMask; + PowerCC32XX_Wakeup wakeupConfig; +} PowerCC32XX_ModuleState; +/*! @endcond */ + +/*! + * @brief Function configures wakeup for LPDS and shutdown + * + * This function allows the app to configure the GPIO source and + * type for waking up from LPDS and shutdown and the network host + * as a wakeup source for LPDS. This overwrites any previous + * wakeup settings. + * + * @param wakeup Settings applied to wakeup configuration + */ +void PowerCC32XX_configureWakeup(PowerCC32XX_Wakeup *wakeup); + +/*! OS-specific power policy initialization function */ +void PowerCC32XX_initPolicy(void); + +/*! + * @brief Function to get wakeup configuration settings + * + * This function allows an app to query the current LPDS and shutdown + * wakeup configuration settings. + * + * @param wakeup A PowerCC32XX_Wakeup structure to be written into + */ +void PowerCC32XX_getWakeup(PowerCC32XX_Wakeup *wakeup); + +/*! CC32XX-specific function to dynamically set the LPDS park state for a pin */ +void PowerCC32XX_setParkState(PowerCC32XX_Pin pin, uint32_t level); + +/*! + * @brief Function to disable IO retention and unlock pin groups following + * exit from Shutdown. + * + * PowerCC32XX_ConfigV1.ioRetentionShutdown can be used to specify locking and + * retention of pin groups during Shutdown. Upon exit from Shutdown, and + * when appropriate, an application can call this function, to + * correspondingly disable IO retention, and unlock the specified pin groups. + * + * @param groupFlags A logical OR of one or more of the following + * flags (defined in driverlib/prcm.h): + * PRCM_IO_RET_GRP_0 - all pins except sFlash and JTAG interface + * PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 + * PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 + * PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 + */ +void PowerCC32XX_disableIORetention(unsigned long groupFlags); + +/*! OS-specific power policy function */ +void PowerCC32XX_sleepPolicy(void); + +/* \cond */ +#define Power_getPerformanceLevel(void) 0 +#define Power_setPerformanceLevel(level) Power_EFAIL +/* \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_power_PowerCC32XX__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/pwm/PWMTimerCC32XX.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/pwm/PWMTimerCC32XX.h new file mode 100644 index 000000000..1982fa663 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/pwm/PWMTimerCC32XX.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! ============================================================================ + * @file PWMTimerCC32XX.h + * + * @brief PWM driver implementation using CC32XX General Purpose Timers. + * + * The PWM header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref PWM.h for a complete description of the PWM + * driver APIs provided and examples of their use. + * + * ## Overview # + * This driver configures a CC32XX General Purpose Timer (GPT) in PWM mode. + * When in PWM mode, each GPT is divided into 2 PWM outputs. This driver + * manages each output as an independent PWM instance. The timer is + * automatically configured in count-down mode using the system clock as + * the source. + * + * The timers operate at the system clock frequency (80 MHz). So each timer + * tick is 12.5 ns. The period and duty registers are 16 bits wide; thus + * 8-bit prescalars are used to extend period and duty registers. The + * maximum value supported is 16777215 timer counts ((2^24) - 1) or + * 209715 microseconds. Updates to a PWM's period or duty will occur + * instantaneously (GPT peripherals do not have shadow registers). + * + * Finally, when this driver is opened, it automatically changes the + * PWM pin's parking configuration (used when entering low power modes) to + * correspond with the PWM_IDLE_LEVEL set in the PWM_params. However, this + * setting is not reverted once the driver is closed, it is the users + * responsibility to change the parking configuration if necessary. + * + * ### CC32xx PWM Driver Configuration # + * + * In order to use the PWM APIs, the application is required + * to define 4 configuration items in the application Board.c file: + * + * 1. An array of PWMTimerCC32XX_Object elements, which will be used by + * by the driver to maintain instance state. + * Below is an example PWMTimerCC32XX_Object array appropriate for the CC3220SF Launchpad + * board: + * @code + * #include + * #include + * + * PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT]; + * @endcode + * + * 2. An array of PWMTimerCC32XX_HWAttrsV2 elements that defines which + * pin will be used by the corresponding PWM instance + * (see @ref pwmPinIdentifiersCC32XX). + * Below is an example PWMTimerCC32XX_HWAttrsV2 array appropriate for the CC3220SF Launchpad + * board: + * @code + * const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = { + * { + * .pwmPin = PWMTimerCC32XX_PIN_01 + * }, + * { + * .pwmPin = PWMTimerCC32XX_PIN_02 + * } + * }; + * @endcode + * + * 3. An array of @ref PWM_Config elements, one for each PWM instance. Each + * element of this array identifies the device-specific API function table, + * the device specific PWM object instance, and the device specific Hardware + * Attributes to be used for each PWM channel. + * Below is an example @ref PWM_Config array appropriate for the CC3220SF Launchpad + * board: + * @code + * const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = { + * { + * .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + * .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6], + * .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6] + * }, + * { + * .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + * .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7], + * .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7] + * } + * }; + * @endcode + * + * 4. A global variable, PWM_count, that informs the driver how many PWM + * instances are defined: + * @code + * const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT; + * @endcode + * + * ### Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The PWMTimerCC32XX driver explicitly sets a power constraint when the + * PWM is running to prevent LPDS and SHUTDOWN Power modes. + * The following statements are valid: + * - After PWM_open(): Clocks are enabled to the timer resource and the + * configured pwmPin. The device is still allowed + * to enter LPDS and SHUTDOWN. + * - After PWM_start(): LPDS and SHUTDOWN modes are disabled. The device + * can only go to Idle power mode since the + * high-frequency clock is needed for PWM operation: + * - After PWM_stop(): Conditions are equal as for after PWM_open + * - After PWM_close(): The underlying GPTimer is turned off, and the clocks + * to the timer and pin are disabled.. + * + * ============================================================================= + */ + +#ifndef ti_driver_pwm_PWMTimerCC32XX__include +#define ti_driver_pwm_PWMTimerCC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/*! \cond */ +/* + * PWMTimer port/pin defines for pin configuration. + * + * The timer id (0, 1, 2, or 3) is stored in bits 31 - 28 + * The timer half (0 = A, 1 = B) is stored in bits 27 - 24 + * The GPIO port (0, 1, 2, or 3) is stored in bits 23 - 20 + * The GPIO pin index within the port (0 - 7) is stored in bits 19 - 16 + * The pin mode is stored in bits 11 - 8 + * The pin number is stored in bits 7 - 0 + * + * + * 31 - 28 27 - 24 23 - 20 19 - 16 11 - 8 7 - 0 + * ----------------------------------------------------------------------- + * | Timer id | Timer half | GPIO port | GPIO pin index | pin mode | pin | + * ----------------------------------------------------------------------- + * + * The CC32XX has fixed GPIO assignments and pin modes for a given pin. + * A PWM pin mode for a given pin has a fixed timer/timer-half. + */ +#define PWMTimerCC32XX_T0A (0x00 << 24) +#define PWMTimerCC32XX_T0B (0x01 << 24) +#define PWMTimerCC32XX_T1A (0x10 << 24) +#define PWMTimerCC32XX_T1B (0x11 << 24) +#define PWMTimerCC32XX_T2A (0x20 << 24) +#define PWMTimerCC32XX_T2B (0x21 << 24) +#define PWMTimerCC32XX_T3A (0x30 << 24) +#define PWMTimerCC32XX_T3B (0x31 << 24) + +#define PWMTimerCC32XX_GPIO0 (0x00 << 16) +#define PWMTimerCC32XX_GPIO1 (0x01 << 16) +#define PWMTimerCC32XX_GPIO2 (0x02 << 16) +#define PWMTimerCC32XX_GPIO3 (0x03 << 16) +#define PWMTimerCC32XX_GPIO4 (0x04 << 16) +#define PWMTimerCC32XX_GPIO5 (0x05 << 16) +#define PWMTimerCC32XX_GPIO6 (0x06 << 16) +#define PWMTimerCC32XX_GPIO7 (0x07 << 16) +#define PWMTimerCC32XX_GPIO8 (0x10 << 16) +#define PWMTimerCC32XX_GPIO9 (0x11 << 16) +#define PWMTimerCC32XX_GPIO10 (0x12 << 16) +#define PWMTimerCC32XX_GPIO11 (0x13 << 16) +#define PWMTimerCC32XX_GPIO12 (0x14 << 16) +#define PWMTimerCC32XX_GPIO13 (0x15 << 16) +#define PWMTimerCC32XX_GPIO14 (0x16 << 16) +#define PWMTimerCC32XX_GPIO15 (0x17 << 16) +#define PWMTimerCC32XX_GPIO16 (0x20 << 16) +#define PWMTimerCC32XX_GPIO17 (0x21 << 16) +#define PWMTimerCC32XX_GPIO18 (0x22 << 16) +#define PWMTimerCC32XX_GPIO19 (0x23 << 16) +#define PWMTimerCC32XX_GPIO20 (0x24 << 16) +#define PWMTimerCC32XX_GPIO21 (0x25 << 16) +#define PWMTimerCC32XX_GPIO22 (0x26 << 16) +#define PWMTimerCC32XX_GPIO23 (0x27 << 16) +#define PWMTimerCC32XX_GPIO24 (0x30 << 16) +#define PWMTimerCC32XX_GPIO25 (0x31 << 16) +#define PWMTimerCC32XX_GPIO26 (0x32 << 16) +#define PWMTimerCC32XX_GPIO27 (0x33 << 16) +#define PWMTimerCC32XX_GPIO28 (0x34 << 16) +#define PWMTimerCC32XX_GPIO29 (0x35 << 16) +#define PWMTimerCC32XX_GPIO30 (0x36 << 16) +#define PWMTimerCC32XX_GPIO31 (0x37 << 16) + +#define PWMTimerCC32XX_GPIONONE (0xFF << 16) +/*! \endcond */ + +/*! + * \defgroup pwmPinIdentifiersCC32XX PWMTimerCC32XX_HWAttrs 'pwmPin' field options + * @{ + */ +/*! + * @name PIN 01, GPIO10, uses Timer3A for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_01 PWMTimerCC32XX_T3A | PWMTimerCC32XX_GPIO10 | 0x0300 /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 02, GPIO11, uses Timer3B for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_02 PWMTimerCC32XX_T3B | PWMTimerCC32XX_GPIO11 | 0x0301 /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 17, GPIO24, uses Timer0A for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_17 PWMTimerCC32XX_T0A | PWMTimerCC32XX_GPIO24 | 0x0510 /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 19, uses Timer1B for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_19 PWMTimerCC32XX_T1B | PWMTimerCC32XX_GPIO_NONE | 0x0812 /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 21, GPIO25, uses Timer1A for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_21 PWMTimerCC32XX_T1A | PWMTimerCC32XX_GPIO25 | 0x0914 /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 64, GPIO9, uses Timer2B for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_64 PWMTimerCC32XX_T2B | PWMTimerCC32XX_GPIO9 | 0x033F /*!< @hideinitializer */ +/*! @} */ +/*! @} */ + +/** + * @addtogroup PWM_STATUS + * PWMTimerCC32XX_STATUS_* macros are command codes only defined in the + * PWMTimerCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add PWMTimerCC32XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup PWM_CMD + * PWMTimerCC32XX_CMD_* macros are command codes only defined in the + * PWMTimerCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add PWMTimerCC32XX_CMD_* macros here */ + +/** @}*/ + +/* PWM function table pointer */ +extern const PWM_FxnTable PWMTimerCC32XX_fxnTable; + +/*! + * @brief PWMTimerCC32XX Hardware attributes + * + * The 'pwmPin' field identifies which physical pin to use for a + * particular PWM channel as well as the corresponding Timer resource used + * to source the PWM signal. The encoded pin identifier macros for + * initializing the 'pwmPin' field must be selected from the + * @ref pwmPinIdentifiersCC32XX macros. + * + * A sample structure is shown below: + * @code + * const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC32XXHWAttrs[] = { + * { + * .pwmPin = PWMTimerCC32XX_PIN_01, + * }, + * { + * .pwmPin = PWMTimerCC32XX_PIN_02, + * } + * }; + * @endcode + */ +typedef struct PWMTimerCC32XX_HWAttrsV2 { + uint32_t pwmPin; /*!< Pin to output PWM signal on + (see @ref pwmPinIdentifiersCC32XX) */ +} PWMTimerCC32XX_HWAttrsV2; + +/*! + * @brief PWMTimerCC32XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct PWMTimerCC32XX_Object { + Power_NotifyObj postNotify; + uint_fast16_t gpioPowerMgrId; /* Power Manager ID for pin in use */ + uint_fast16_t timerPowerMgrId; /* Power Manager ID for timer in use */ + uint32_t duty; /* Current duty cycle in Duty_Unites */ + uint32_t period; /* Current period PERIOD_Units */ + PWM_Duty_Units dutyUnits; /* Current duty cycle unit */ + PWM_Period_Units periodUnits; /* Current period unit */ + PWM_IdleLevel idleLevel; /* PWM idle level when stopped / not started */ + bool pwmStarted; /* Used to gate Power_set/releaseConstraint() calls */ + bool isOpen; /* open flag used to check if PWM is opened */ +} PWMTimerCC32XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_driver_pwm_PWMTimerCC32XX__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/sd/SDHostCC32XX.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/sd/SDHostCC32XX.h new file mode 100644 index 000000000..b93351262 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/sd/SDHostCC32XX.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** ============================================================================ + * @file SDHostCC32XX.h + * + * @brief SDHost driver implementation for CC32XX devices. + * + * The SDHost header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref SD.h for a complete description of APIs & example of use. + * + * This SDHost driver implementation is designed to operate on a CC32XX + * SD Host controller using a micro DMA controller. + * + * Note: The driver API's are not thread safe and must not be accessed through + * multiple threads without the use of mutexes. + * + * ## DMA buffer alignment # + * + * When performing disk operations with a word aligned buffer the driver will + * make transfers using the DMA controller. Alternatively, if the buffer is + * not aligned, the data will be copied to the internal SD Host controller + * buffer using a polling method. + * + * ## DMA Interrupts # + * + * When DMA is used, the micro DMA controller generates and IRQ on the + * perpheral's interrupt vector. This implementation automatically installs + * a DMA interrupt to service the assigned micro DMA channels. + * + * ## DMA accessible memory # + * + * When DMA is used, it is the responsibility of the application to ensure + * that read/write buffers reside in memory that is accessible by the DMA. + * + * ============================================================================ + */ + +#ifndef ti_drivers_sd_SDHostCC32XX__include +#define ti_drivers_sd_SDHostCC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include + +#define SDHostCC32XX_PIN_06_SDCARD_DATA 0x0805 +#define SDHostCC32XX_PIN_07_SDCARD_CLK 0x0806 +#define SDHostCC32XX_PIN_08_SDCARD_CMD 0x0807 +#define SDHostCC32XX_PIN_01_SDCARD_CLK 0x0600 +#define SDHostCC32XX_PIN_02_SDCARD_CMD 0x0601 +#define SDHostCC32XX_PIN_64_SDCARD_DATA 0x063f + +/* SDHost function table */ +extern const SD_FxnTable sdHostCC32XX_fxnTable; + +/*! + * @brief SDHostCC32XX Hardware attributes + * + * The SDHostCC32XX configuration structure is passed to the SDHostCC32XX + * driver implementation with hardware specifics regarding GPIO Pins and Ports + * to be used. + * + * The SDHostCC32XX driver uses this information to: + * - Configure and reconfigure specific ports/pins to initialize the SD Card + * for SD mode + * - Identify which GPIO port and pin is used for the SDHost clock, data and + * command lines + * + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC32xxWare these definitions are found in: + * - inc/hw_memmap.h + * - driverlib/pin.h + * + * @struct SDHostCC32XX_HWAttrs + * An example configuration structure could look as the following: + * @code + * const SDHostCC32XX_HWAttrsV1 sdhostCC32XXHWattrs[] = { + * { + * .clkRate = 8000000, + * .intPriority = ~0, + * .baseAddr = SDHOST_BASE, + * .rxChIdx = UDMA_CH23_SDHOST_RX, + * .txChIdx = UDMA_CH24_SDHOST_TX, + * .dataPin = SDHostCC32XX_PIN_06_SDCARD_DATA, + * .cmdPin = SDHostCC32XX_PIN_08_SDCARD_CMD, + * .clkPin = SDHostCC32XX_PIN_07_SDCARD_CLK, + * } + * }; + * @endcode + */ +typedef struct SDHostCC32XX_HWAttrsV1 { + /*!< SD interface clock rate */ + uint_fast32_t clkRate; + + /*!< Internal SDHost ISR command/transfer priorty */ + int_fast32_t intPriority; + + /*!< SDHost Peripheral base address */ + uint_fast32_t baseAddr; + + /*!< uDMA controlTable receive channel index */ + unsigned long rxChIdx; + + /*!< uDMA controlTable transmit channel index */ + unsigned long txChIdx; + + /*!< SD Host Data pin */ + uint32_t dataPin; + + /*!< SD Host CMD pin */ + uint32_t cmdPin; + + /*!< SD Host CLK pin */ + uint32_t clkPin; +} SDHostCC32XX_HWAttrsV1; + +/*! + * @brief SDHostCC32XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct SDHostCC32XX_Object { + /* Relative Card Address */ + uint_fast32_t rca; + /* Write data pointer */ + const uint_fast32_t *writeBuf; + /* Number of sectors written */ + volatile uint_fast32_t writeSecCount; + /* Read data pointer */ + uint_fast32_t *readBuf; + /* Number of sectors read */ + volatile uint_fast32_t readSecCount; + /* + * Semaphore to suspend thread execution when waiting for SD Commands + * or data transfers to complete. + */ + SemaphoreP_Handle cmdSem; + /* + * SD Card interrupt handle. + */ + HwiP_Handle hwiHandle; + /* Determined from base address */ + unsigned int powerMgrId; + /* LPDS wake-up notify object */ + Power_NotifyObj postNotify; + /* UDMA Handle */ + UDMACC32XX_Handle dmaHandle; + /* SD Card command state */ + volatile int_fast8_t stat; + /* State of the driver (open or closed) */ + bool isOpen; + /* SDCard Card Command Class(CCC) */ + SD_CardType cardType; +} SDHostCC32XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_sd_SDHostCC32XX__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/spi/SPICC32XXDMA.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/spi/SPICC32XXDMA.h new file mode 100644 index 000000000..6f69589b6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/spi/SPICC32XXDMA.h @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file SPICC32XXDMA.h + * + * @brief SPI driver implementation for a CC32XX SPI controller using the + * micro DMA controller. + * + * The SPI header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref SPI.h for a complete description of APIs & example of use. + * + * This SPI driver implementation is designed to operate on a CC32XX SPI + * controller using a micro DMA controller. + * + * ## SPI Chip Select # + * This SPI controller supports a hardware chip select pin. Refer to the + * device's user manual on how this hardware chip select pin behaves in regards + * to the SPI frame format. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Chip select typeSPI_MASTER modeSPI_SLAVE mode
Hardware chip selectNo action is needed by the application to select the peripheral.See the device documentation on it's chip select requirements.
Software chip selectThe application is responsible to ensure that correct SPI slave is + * selected before performing a SPI_transfer().See the device documentation on it's chip select requirements.
+ * + * ## DMA Interrupts # + * This driver is designed to operate with the micro DMA. The micro DMA + * generates an IRQ on the perpheral's interrupt vector. This implementation + * automatically installs a DMA aware hardware ISR to service the assigned + * micro DMA channels. + * + * ## SPI data frames # + * SPI data frames can be any size from 4-bits to 32-bits. The SPI data + * frame size is set in ::SPI_Params.dataSize passed to SPI_open. + * The SPICC32XXDMA driver implementation makes assumptions on the element + * size of the ::SPI_Transaction txBuf and rxBuf arrays, based on the data + * frame size. If the data frame size is less than or equal to 8 bits, + * txBuf and rxBuf are assumed to be arrays of 8-bit uint8_t elements. + * If the data frame size is greater than 8 bits, but less than or equal + * to 16 bits, txBuf and rxBuf are assumed to be arrays of 16-bit uint16_t + * elements. Otherwise, txBuf and rxBuf are assumed to point to 32-bit + * uint32_t elements. + * + * data frame size | buffer element size | + * -------------- | ------------------- | + * 4-8 bits | uint8_t | + * 9-16 bits | uint16_t | + * 16-32 bits | uint32_t | + * + * ## DMA transfer size limit # + * The micro DMA controller only supports data transfers of up to 1024 + * data frames. A data frame can be 4 to 32 bits in length. + * + * ## DMA accessible memory # + * As this driver uses uDMA to transfer data/from data buffers, it is the + * responsibility of the application to ensure that these buffers reside in + * memory that is accessible by the DMA. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_spi_SPICC32XXDMA__include +#define ti_drivers_spi_SPICC32XXDMA__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +/** + * @addtogroup SPI_STATUS + * SPICC32XXDMA_STATUS_* macros are command codes only defined in the + * SPICC32XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add SPICC32XXDMA_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup SPI_CMD + * SPICC32XXDMA_CMD_* macros are command codes only defined in the + * SPICC32XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add SPICC32XXDMA_CMD_* macros here */ + +/** @}*/ + +#define SPICC32XXDMA_PIN_05_CLK 0x0704 +#define SPICC32XXDMA_PIN_06_MISO 0x0705 +#define SPICC32XXDMA_PIN_07_MOSI 0x0706 +#define SPICC32XXDMA_PIN_08_CS 0x0707 +#define SPICC32XXDMA_PIN_45_CLK 0x072C +#define SPICC32XXDMA_PIN_50_CS 0x0931 +#define SPICC32XXDMA_PIN_52_MOSI 0x0833 +#define SPICC32XXDMA_PIN_53_MISO 0x0734 + +#define SPICC32XXDMA_PIN_NO_CONFIG 0xFFFF + + +typedef unsigned long SPIBaseAddrType; +typedef unsigned long SPIDataType; + +/* SPI function table pointer */ +extern const SPI_FxnTable SPICC32XXDMA_fxnTable; + +/*! + * @brief + * SPICC32XXDMA data frame size is used to determine how to configure the + * DMA data transfers. This field is to be only used internally. + * + * SPICC32XXDMA_8bit: txBuf and rxBuf are arrays of uint8_t elements + * SPICC32XXDMA_16bit: txBuf and rxBuf are arrays of uint16_t elements + * SPICC32XXDMA_32bit: txBuf and rxBuf are arrays of uint32_t elements + */ +typedef enum SPICC32XXDMA_FrameSize { + SPICC32XXDMA_8bit = 0, + SPICC32XXDMA_16bit = 1, + SPICC32XXDMA_32bit = 2 +} SPICC32XXDMA_FrameSize; + +/*! + * @brief SPICC32XXDMA Hardware attributes + * + * These fields, with the exception of intPriority, + * are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CCWare these definitions are found in: + * - driverlib/prcm.h + * - driverlib/spi.h + * - driverlib/udma.h + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * intPriority is the SPI peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * #if defined(__TI_COMPILER_VERSION__) + * #pragma DATA_ALIGN(scratchBuf, 32) + * #elif defined(__IAR_SYSTEMS_ICC__) + * #pragma data_alignment=32 + * #elif defined(__GNUC__) + * __attribute__ ((aligned (32))) + * #endif + * uint32_t scratchBuf; + * + * const SPICC32XXDMA_HWAttrsV1 SPICC32XXDMAHWAttrs[] = { + * { + * .baseAddr = GSPI_BASE, + * .intNum = INT_GSPI, + * .intPriority = (~0), + * .spiPRCM = PRCM_GSPI, + * .csControl = SPI_HW_CTRL_CS, + * .csPolarity = SPI_CS_ACTIVELOW, + * .pinMode = SPI_4PIN_MODE, + * .turboMode = SPI_TURBO_OFF, + * .scratchBufPtr = &scratchBuf, + * .defaultTxBufValue = 0, + * .rxChannelIndex = UDMA_CH6_GSPI_RX, + * .txChannelIndex = UDMA_CH7_GSPI_TX, + * .minDmaTransferSize = 100, + * .mosiPin = SPICC32XXDMA_PIN_07_MOSI, + * .misoPin = SPICC32XXDMA_PIN_06_MISO, + * .clkPin = SPICC32XXDMA_PIN_05_CLK, + * .csPin = SPICC32XXDMA_PIN_08_CS, + * }, + * ... + * }; + * @endcode + */ +typedef struct SPICC32XXDMA_HWAttrsV1 { + /*! SPICC32XXDMA Peripheral's base address */ + SPIBaseAddrType baseAddr; + + /*! SPICC32XXDMA Peripheral's interrupt vector */ + uint32_t intNum; + + /*! SPICC32XXDMA Peripheral's interrupt priority */ + uint32_t intPriority; + + /*! SPI PRCM peripheral number */ + uint32_t spiPRCM; + + /*! Specify if chip select line will be controlled by SW or HW */ + uint32_t csControl; + + uint32_t csPolarity; + + /*! Set peripheral to work in 3-pin or 4-pin mode */ + uint32_t pinMode; + + /*! Enable or disable SPI TURBO mode */ + uint32_t turboMode; + + /*! Address of a scratch buffer of size uint32_t */ + uint32_t *scratchBufPtr; + + /*! Default TX value if txBuf == NULL */ + unsigned long defaultTxBufValue; + + /*! uDMA RX channel index */ + uint32_t rxChannelIndex; + + /*! uDMA TX channel index */ + uint32_t txChannelIndex; + + /*! Minimum amout of data to start a uDMA transfer */ + uint32_t minDmaTransferSize; + + /*! GSPI MOSI pin assignment */ + uint16_t mosiPin; + + /*! GSPI MISO pin assignment */ + uint16_t misoPin; + + /*! GSPI CLK pin assignment */ + uint16_t clkPin; + + /*! GSPI CS pin assignment */ + uint16_t csPin; +} SPICC32XXDMA_HWAttrsV1; + +/*! + * @brief SPICC32XXDMA Object + * + * The application must not access any member variables of this structure! + */ +typedef struct SPICC32XXDMA_Object { + HwiP_Handle hwiHandle; + SemaphoreP_Handle transferComplete; + + Power_NotifyObj notifyObj; + unsigned int powerMgrId; + + uint32_t bitRate; /*!< SPI bit rate in Hz */ + uint32_t dataSize; /*!< SPI data frame size in bits */ + SPI_CallbackFxn transferCallbackFxn; + SPI_Transaction *transaction; + + void (*spiPollingFxn) (uint32_t baseAddr, void *rx, + void *tx, uint8_t rxInc, uint8_t txInc, + size_t count); + + uint8_t rxFifoTrigger; + uint8_t txFifoTrigger; + SPI_Mode spiMode; + SPI_TransferMode transferMode; + SPI_FrameFormat frameFormat; /*!< SPI frame format */ + SPICC32XXDMA_FrameSize frameSize; + + bool isOpen; + + /* UDMA */ + UDMACC32XX_Handle dmaHandle; +} SPICC32XXDMA_Object, *SPICC32XXDMA_Handle; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_spi_SPICC32XXDMA__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/uart/UARTCC32XX.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/uart/UARTCC32XX.h new file mode 100644 index 000000000..02cae9176 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/uart/UARTCC32XX.h @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UARTCC32XX.h + * + * @brief UART driver implementation for a CC32XX UART controller + * + * The UART header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref UART.h for a complete description of APIs & example of use. + * + * # Stack requirements # + * The UARTCC32XX driver is (ring) buffered driver, and stores data it may + * have already received in a user-supplied background buffer. + * @sa ::UARTCC32XX_HWAttrsV1 + * + * While permitted, it is STRONGLY suggested to avoid implementations where + * you call UART_read() within its own callback function (when in + * UART_MODE_CALLBACK). Doing so, will require additional (task and system) + * stack for each nested UART_read() call. + * + * Tool chain | Number of bytes per nested UART_read() call + * ---------- | ------------------------------------------------ + * GNU | 96 bytes + callback function stack requirements + * IAR | 40 bytes + callback function stack requirements + * TI | 80 bytes + callback function stack requirements + * + * It is important to note a potential worst case scenario: + * A full ring buffer with data; say 32 bytes + * The callback function calls UART_read() with a size of 1 (byte) + * No other variables are allocated in the callback function + * No other function calls are made in the callback function + * + * As a result, you need an additional task and system stack of: + * 32 bytes * (80 bytes for TI + 0 bytes by the callback function) = 2.5kB + * + * # Device Specific Pin Mode Macros # + * This header file contains pin mode definitions used to specify the + * UART TX and RX pin assignment in the UARTCC32XX_HWAttrsV1 structure. + * Please refer to the CC32XX Techincal Reference Manual for details on pin + * multiplexing. The bits in the pin mode macros are as follows: + * The lower 8 bits of the macro refer to the pin, offset by 1, to match + * driverlib pin defines. For example, UARTCC32XX_PIN_01_UART1_TX & 0xff = 0, + * which equals PIN_01 in driverlib pin.h. By matching the PIN_xx defines in + * driverlib pin.h, we can pass the pin directly to the driverlib functions. + * The upper 8 bits of the macro correspond to the pin mux confg mode + * value for the pin to operate in the UART mode. For example, pin 1 is + * configured with mode 7 to operate as UART1 TX. + * + * ============================================================================ + */ + +#ifndef ti_drivers_uart_UARTCC32XX__include +#define ti_drivers_uart_UARTCC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include + + +#define UARTCC32XX_PIN_01_UART1_TX 0x700 +#define UARTCC32XX_PIN_02_UART1_RX 0x701 +#define UARTCC32XX_PIN_03_UART0_TX 0x702 +#define UARTCC32XX_PIN_04_UART0_RX 0x703 +#define UARTCC32XX_PIN_07_UART1_TX 0x506 +#define UARTCC32XX_PIN_08_UART1_RX 0x507 +#define UARTCC32XX_PIN_16_UART1_TX 0x20F +#define UARTCC32XX_PIN_17_UART1_RX 0x210 +#define UARTCC32XX_PIN_45_UART0_RX 0x92C +#define UARTCC32XX_PIN_45_UART1_RX 0x22C +#define UARTCC32XX_PIN_53_UART0_TX 0x934 +#define UARTCC32XX_PIN_55_UART0_TX 0x336 +#define UARTCC32XX_PIN_55_UART1_TX 0x636 +#define UARTCC32XX_PIN_57_UART0_RX 0x338 +#define UARTCC32XX_PIN_57_UART1_RX 0x638 +#define UARTCC32XX_PIN_58_UART1_TX 0x639 +#define UARTCC32XX_PIN_59_UART1_RX 0x63A +#define UARTCC32XX_PIN_62_UART0_TX 0xB3D + + +/** + * @addtogroup UART_STATUS + * UARTCC32XX_STATUS_* macros are command codes only defined in the + * UARTCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add UARTCC32XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup UART_CMD + * UARTCC32XX_CMD_* macros are command codes only defined in the + * UARTCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by UART_control to determines + * whether the UART transmitter is busy or not + * + * With this command code, @b arg is a pointer to a @c bool. + * @b *arg contains @c true if the UART is transmitting, + * else @c false if all transmissions are complete. + */ +#define UARTCC32XX_CMD_IS_BUSY (UART_CMD_RESERVED + 0) + + +/*! + * @brief Command used by UART_control to determines + * if there are any characters in the receive FIFO + * + * With this command code, @b arg is a pointer to a @c bool. + * @b *arg contains @c true if there is data in the receive FIFO, + * or @c false if there is no data in the receive FIFO. + */ +#define UARTCC32XX_CMD_IS_RX_DATA_AVAILABLE (UART_CMD_RESERVED + 1) + + +/*! + * @brief Command used by UART_control to determines + * if there is any space in the transmit FIFO + * + * With this command code, @b arg is a pointer to a @c bool. + * @b *arg contains @c true if there is space available in the transmit FIFO, + * or @c false if there is no space available in the transmit FIFO. + */ +#define UARTCC32XX_CMD_IS_TX_SPACE_AVAILABLE (UART_CMD_RESERVED + 2) + + +/** @}*/ + +/* UART function table pointer */ +extern const UART_FxnTable UARTCC32XX_fxnTable; + +/*! + * @brief Complement set of read functions to be used by the UART ISR and + * UARTCC32XX_read(). Internal use only. + * + * These functions are solely intended for the UARTCC32XX driver, and should + * not be used by the application. + * The UARTCC32XX_FxnSet is a pair of complement functions that are design to + * operate with one another in a task context and in an ISR context. The + * readTaskFxn is called by UARTCC32XX_read() to drain a circular buffer, + * whereas the readIsrFxn is used by the UARTCC32XX_hwiIntFxn to fill up the + * circular buffer. + * + * readTaskFxn: Function called by UART read + * These variables are set and avilalable for use to the + * readTaskFxn. + * object->readBuf = buffer; //Pointer to a user buffer + * object->readSize = size; //Desired no. of bytes to read + * object->readCount = size; //Remaining no. of bytes to read + * + * readIsrFxn: The required ISR counterpart to readTaskFxn + */ +typedef struct UARTCC32XX_FxnSet { + bool (*readIsrFxn) (UART_Handle handle); + int (*readTaskFxn) (UART_Handle handle); +} UARTCC32XX_FxnSet; + +/*! + * @brief UARTCC32XX Hardware attributes + * + * The fields, baseAddr, intNum, and flowControl, are used by driverlib + * APIs and therefore must be populated by + * driverlib macro definitions. For CC32XXWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * - driverlib/uart.h + * + * intPriority is the UART peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * unsigned char uartCC32XXRingBuffer[2][32]; + * + * const UARTCC32XX_HWAttrsV1 uartCC32XXHWAttrs[] = { + * { + * .baseAddr = UARTA0_BASE, + * .intNum = INT_UARTA0, + * .intPriority = (~0), + * .flowControl = UART_FLOWCONTROL_NONE, + * .ringBufPtr = uartCC32XXRingBuffer[0], + * .ringBufSize = sizeof(uartCC32XXRingBuffer[0]), + * .rxPin = UARTCC32XX_PIN_57_UART0_RX, + * .txPin = UARTCC32XX_PIN_55_UART0_TX + * }, + * { + * .baseAddr = UARTA1_BASE, + * .intNum = INT_UARTA1, + * .intPriority = (~0), + * .flowControl = UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX, + * .ringBufPtr = uartCC32XXRingBuffer[1], + * .ringBufSize = sizeof(uartCC32XXRingBuffer[1]), + * .rxPin = UARTCC32XX_PIN_08_UART1_RX, + * .txPin = UARTCC32XX_PIN_07_UART1_TX + * }, + * }; + * @endcode + */ +typedef struct UARTCC32XX_HWAttrsV1 { + /*! UART Peripheral's base address */ + unsigned int baseAddr; + /*! UART Peripheral's interrupt vector */ + unsigned int intNum; + /*! UART Peripheral's interrupt priority */ + unsigned int intPriority; + /*! Hardware flow control setting defined by driverlib */ + uint32_t flowControl; + /*! Pointer to an application ring buffer */ + unsigned char *ringBufPtr; + /*! Size of ringBufPtr */ + size_t ringBufSize; + /*! UART RX pin assignment */ + uint16_t rxPin; + /*! UART TX pin assignment */ + uint16_t txPin; +} UARTCC32XX_HWAttrsV1; + +/*! + * @brief UARTCC32XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct UARTCC32XX_Object { + /* UART state variable */ + struct { + bool opened:1; /* Has the obj been opened */ + UART_Mode readMode:1; /* Mode for all read calls */ + UART_Mode writeMode:1; /* Mode for all write calls */ + UART_DataMode readDataMode:1; /* Type of data being read */ + UART_DataMode writeDataMode:1; /* Type of data being written */ + UART_ReturnMode readReturnMode:1; /* Receive return mode */ + UART_Echo readEcho:1; /* Echo received data back */ + /* + * Flag to determine if a timeout has occurred when the user called + * UART_read(). This flag is set by the timeoutClk clock object. + */ + bool bufTimeout:1; + /* + * Flag to determine when an ISR needs to perform a callback; in both + * UART_MODE_BLOCKING or UART_MODE_CALLBACK + */ + bool callCallback:1; + /* + * Flag to determine if the ISR is in control draining the ring buffer + * when in UART_MODE_CALLBACK + */ + bool drainByISR:1; + /* Flag to keep the state of the read Power constraints */ + bool rxEnabled:1; + /* Flag to keep the state of the write Power constraints */ + bool txEnabled:1; + } state; + + HwiP_Handle hwiHandle; /* Hwi handle for interrupts */ + ClockP_Handle timeoutClk; /* Clock object to for timeouts */ + uint32_t baudRate; /* Baud rate for UART */ + UART_LEN dataLength; /* Data length for UART */ + UART_STOP stopBits; /* Stop bits for UART */ + UART_PAR parityType; /* Parity bit type for UART */ + + /* UART read variables */ + RingBuf_Object ringBuffer; /* local circular buffer object */ + /* A complement pair of read functions for both the ISR and UART_read() */ + UARTCC32XX_FxnSet readFxns; + unsigned char *readBuf; /* Buffer data pointer */ + size_t readSize; /* Desired number of bytes to read */ + size_t readCount; /* Number of bytes left to read */ + SemaphoreP_Handle readSem; /* UART read semaphore */ + unsigned int readTimeout; /* Timeout for read semaphore */ + UART_Callback readCallback; /* Pointer to read callback */ + + /* UART write variables */ + const unsigned char *writeBuf; /* Buffer data pointer */ + size_t writeSize; /* Desired number of bytes to write*/ + size_t writeCount; /* Number of bytes left to write */ + SemaphoreP_Handle writeSem; /* UART write semaphore*/ + unsigned int writeTimeout; /* Timeout for write semaphore */ + UART_Callback writeCallback; /* Pointer to write callback */ + unsigned int writeEmptyClkTimeout; /* TX FIFO timeout tick count */ + + /* For Power management */ + ClockP_Handle txFifoEmptyClk; /* UART TX FIFO empty clock */ + Power_NotifyObj postNotify; /* LPDS wake-up notify object */ + unsigned int powerMgrId; /* Determined from base address */ +} UARTCC32XX_Object, *UARTCC32XX_Handle; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_uart_UARTCC32XX__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/uart/UARTCC32XXDMA.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/uart/UARTCC32XXDMA.h new file mode 100644 index 000000000..c185b92b3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/uart/UARTCC32XXDMA.h @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2014-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UARTCC32XXDMA.h + * + * @brief UART driver implementation for a CC32XX UART controller, using + * the micro DMA controller. + * + * The UART header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref UART.h for a complete description of APIs & example of use. + * + * + * # Device Specific Pin Mode Macros # + * This header file contains pin mode definitions used to specify the + * UART TX and RX pin assignment in the UARTCC32XXDMA_HWAttrsV1 structure. + * Please refer to the CC32XX Techincal Reference Manual for details on pin + * multiplexing. The bits in the pin mode macros are as follows: + * The lower 8 bits of the macro refer to the pin, offset by 1, to match + * driverlib pin defines. For example, + * UARTCC32XXDMA_PIN_01_UART1_TX & 0xff = 0, + * which equals PIN_01 in driverlib pin.h. By matching the PIN_xx defines in + * driverlib pin.h, we can pass the pin directly to the driverlib functions. + * The upper 8 bits of the macro correspond to the pin mux confg mode + * value for the pin to operate in the UART mode. For example, pin 1 is + * configured with mode 7 to operate as UART1 TX. + * + * ============================================================================ + */ + +#ifndef ti_drivers_uart_UARTCC32XXDMA__include +#define ti_drivers_uart_UARTCC32XXDMA__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include + +#include +#include +#include +#include + + +#define UARTCC32XXDMA_PIN_01_UART1_TX 0x700 +#define UARTCC32XXDMA_PIN_02_UART1_RX 0x701 +#define UARTCC32XXDMA_PIN_03_UART0_TX 0x702 +#define UARTCC32XXDMA_PIN_04_UART0_RX 0x703 +#define UARTCC32XXDMA_PIN_07_UART1_TX 0x506 +#define UARTCC32XXDMA_PIN_08_UART1_RX 0x507 +#define UARTCC32XXDMA_PIN_16_UART1_TX 0x20F +#define UARTCC32XXDMA_PIN_17_UART1_RX 0x210 +#define UARTCC32XXDMA_PIN_45_UART0_RX 0x92C +#define UARTCC32XXDMA_PIN_45_UART1_RX 0x22C +#define UARTCC32XXDMA_PIN_53_UART0_TX 0x934 +#define UARTCC32XXDMA_PIN_55_UART0_TX 0x336 +#define UARTCC32XXDMA_PIN_55_UART1_TX 0x636 +#define UARTCC32XXDMA_PIN_57_UART0_RX 0x338 +#define UARTCC32XXDMA_PIN_57_UART1_RX 0x638 +#define UARTCC32XXDMA_PIN_58_UART1_TX 0x639 +#define UARTCC32XXDMA_PIN_59_UART1_RX 0x63A +#define UARTCC32XXDMA_PIN_62_UART0_TX 0xB3D + + +/** + * @addtogroup UART_STATUS + * UARTCC32XXDMA_STATUS_* macros are command codes only defined in the + * UARTCC32XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add UARTCC32XXDMA_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup UART_CMD + * UARTCC32XXDMA_CMD_* macros are command codes only defined in the + * UARTCC32XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by UART_control to determines + * whether the UART transmitter is busy or not + * + * With this command code, @b arg is a pointer to a @c bool. + * @b *arg contains @c true if the UART is transmitting, + * else @c false if all transmissions are complete. + */ +#define UARTCC32XXDMA_CMD_IS_BUSY (UART_CMD_RESERVED + 0) + + +/*! + * @brief Command used by UART_control to determines + * if there are any characters in the receive FIFO + * + * With this command code, @b arg is a pointer to a @c bool. + * @b *arg contains @c true if there is data in the receive FIFO, + * or @c false if there is no data in the receive FIFO. + */ +#define UARTCC32XXDMA_CMD_IS_RX_DATA_AVAILABLE (UART_CMD_RESERVED + 1) + + +/*! + * @brief Command used by UART_control to determines + * if there is any space in the transmit FIFO + * + * With this command code, @b arg is a pointer to a @c bool. + * @b *arg contains @c true if there is space available in the transmit FIFO, + * or @c false if there is no space available in the transmit FIFO. + */ +#define UARTCC32XXDMA_CMD_IS_TX_SPACE_AVAILABLE (UART_CMD_RESERVED + 2) + + +/** @}*/ + +/* UART function table pointer */ +extern const UART_FxnTable UARTCC32XXDMA_fxnTable; + +/*! + * @brief UARTCC32XXDMA Hardware attributes + * + * These fields, with the exception of intPriority, + * are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC32XXWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * intPriority is the UART peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * const UARTCC32XXDMA_HWAttrsV1 uartCC32XXHWAttrs[] = { + * { + * .baseAddr = UARTA0_BASE, + * .intNum = INT_UARTA0, + * .intPriority = (~0), + * .rxChannelIndex = DMA_CH8_UARTA0_RX, + * .txChannelIndex = UDMA_CH9_UARTA0_TX, + * .rxPin = UARTCC32XXDMA_PIN_57_UART0_RX, + * .txPin = UARTCC32XXDMA_PIN_55_UART0_TX + * }, + * { + * .baseAddr = UARTA1_BASE, + * .intNum = INT_UARTA1, + * .intPriority = (~0), + * .rxChannelIndex = UDMA_CH10_UARTA1_RX, + * .txChannelIndex = UDMA_CH11_UARTA1_TX, + * .rxPin = UARTCC32XXDMA_PIN_08_UART1_RX, + * .txPin = UARTCC32XXDMA_PIN_07_UART1_TX + * }, + * }; + * @endcode + */ +typedef struct UARTCC32XXDMA_HWAttrsV1 { + /*! UART Peripheral's base address */ + unsigned int baseAddr; + /*! UART Peripheral's interrupt vector */ + unsigned int intNum; + /*! UART Peripheral's interrupt priority */ + unsigned int intPriority; + /*! uDMA controlTable receive channel index */ + unsigned long rxChannelIndex; + /*! uDMA controlTable transmit channel index */ + unsigned long txChannelIndex; + /*! UART RX pin assignment */ + uint16_t rxPin; + /*! UART TX pin assignment */ + uint16_t txPin; +} UARTCC32XXDMA_HWAttrsV1; + +/*! + * @brief UARTCC32XXDMA Object + * + * The application must not access any member variables of this structure! + */ +typedef struct UARTCC32XXDMA_Object { + /* UART control variables */ + bool opened; /* Has the obj been opened */ + UART_Mode readMode; /* Mode for all read calls */ + UART_Mode writeMode; /* Mode for all write calls */ + unsigned int readTimeout; /* Timeout for read semaphore */ + unsigned int writeTimeout; /* Timeout for write semaphore */ + UART_Callback readCallback; /* Pointer to read callback */ + UART_Callback writeCallback; /* Pointer to write callback */ + UART_ReturnMode readReturnMode; /* Receive return mode */ + UART_DataMode readDataMode; /* Type of data being read */ + UART_DataMode writeDataMode; /* Type of data being written */ + uint32_t baudRate; /* Baud rate for UART */ + UART_LEN dataLength; /* Data length for UART */ + UART_STOP stopBits; /* Stop bits for UART */ + UART_PAR parityType; /* Parity bit type for UART */ + UART_Echo readEcho; /* Echo received data back */ + + /* UART write variables */ + const void *writeBuf; /* Buffer data pointer */ + size_t writeCount; /* Number of Chars sent */ + size_t writeSize; /* Chars remaining in buffer */ + + /* UART receive variables */ + void *readBuf; /* Buffer data pointer */ + size_t readCount; /* Number of Chars read */ + size_t readSize; /* Chars remaining in buffer */ + + /* Semaphores for blocking mode */ + SemaphoreP_Handle writeSem; /* UART write semaphore */ + SemaphoreP_Handle readSem; /* UART read semaphore */ + + HwiP_Handle hwiHandle; + + /* For Power management */ + ClockP_Handle txFifoEmptyClk; /* UART TX FIFO empty clock */ + Power_NotifyObj postNotify; /* LPDS wake-up notify object */ + unsigned int powerMgrId; /* Determined from base address */ + + /* UDMA */ + UDMACC32XX_Handle dmaHandle; +} UARTCC32XXDMA_Object, *UARTCC32XXDMA_Handle; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_uart_UARTCC32XXDMA__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/List.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/List.c new file mode 100644 index 000000000..7c0e0f93d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/List.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== List.c ======== + */ +#include +#include + +#include +#include +#include + +/* + * ======== List_clearList ======== + */ +void List_clearList(List_List *list) +{ + list->head = list->tail = NULL; +} + +/* + * ======== List_empty ======== + */ +bool List_empty(List_List *list) +{ + return (list->head == NULL); +} + +/* + * ======== List_get ======== + */ +List_Elem *List_get(List_List *list) +{ + List_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = list->head; + + /* See if the List was empty */ + if (elem != NULL) { + list->head = elem->next; + if (elem->next != NULL) { + elem->next->prev = NULL; + } + else { + list->tail = NULL; + } + } + + HwiP_restore(key); + + return (elem); +} + +/* + * ======== List_head ======== + */ +List_Elem *List_head(List_List *list) +{ + return (list->head); +} + +/* + * ======== List_insert ======== + */ +void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem) +{ + newElem->next = curElem; + newElem->prev = curElem->prev; + if (curElem->prev != NULL) { + curElem->prev->next = newElem; + } + else { + list->head = newElem; + } + curElem->prev = newElem; +} + +/* + * ======== List_next ======== + */ +List_Elem *List_next(List_Elem *elem) +{ + return (elem->next); +} + +/* + * ======== List_prev ======== + */ +List_Elem *List_prev(List_Elem *elem) +{ + return (elem->prev); +} + +/* + * ======== List_put ======== + */ +void List_put(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = NULL; + elem->prev = list->tail; + if (list->tail != NULL) { + list->tail->next = elem; + } + else { + list->head = elem; + } + + list->tail = elem; + + HwiP_restore(key); +} + +/* + * ======== List_putHead ======== + */ +void List_putHead(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = list->head; + elem->prev = NULL; + if (list->head != NULL) { + list->head->prev = elem; + } + else { + list->tail = elem; + } + + list->head = elem; + + HwiP_restore(key); +} + +/* + * ======== List_remove ======== + */ +void List_remove(List_List *list, List_Elem *elem) +{ + /* Handle the case where the elem to remove is the last one */ + if (elem->next == NULL) { + list->tail = elem->prev; + } + else { + elem->next->prev = elem->prev; + } + + /* Handle the case where the elem to remove is the first one */ + if (elem->prev == NULL) { + list->head = elem->next; + } + else { + elem->prev->next = elem->next; + } +} + +/* + * ======== List_tail ======== + */ +List_Elem *List_tail(List_List *list) +{ + return (list->tail); +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/List.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/List.h new file mode 100644 index 000000000..03085e06c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/List.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file List.h + * + * @brief Linked List interface for use in drivers + * + * This module provides simple doubly-link list implementation. There are two + * main structures: + * - ::List_List: The structure that holds the start of a linked list. There + * is no API to create one. It is up to the driver to provide the structure + * itself. + * - ::List_Elem: The structure that must be in the structure that is placed + * onto a linked list. Generally it is the first field in the structure. For + * example: + * @code + * typedef struct MyStruct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * @endcode + * + * The following shows how to create a linked list with three elements. + * + * @code + * + denotes null-terminated + * _______ _______ _______ _______ + * |_______|----->|_______|----->|_______|--->|_______|--//---, + * ,----|_______| ,-|_______|<-----|_______|<---|_______|<-//-, + + * | List + elem elem elem | + * |_____________________________________________________________| + * @endcode + * + * The APIs ::List_get, ::List_put, and ::List_putHead are + * atomic. The other APIs are not necessarily atomic. In other words, when + * traversing a linked list, it is up to the application to provide + * thread-safety (e.g. HwiP_disable/restore or MutexP_pend/post). + * + * Initializing and adding an element to the tail and removing it + * @code + * typedef struct MyStruct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * + * List_List list; + * MyStruct foo; + * MyStruct *bar; + * + * List_clearList(&list); + * List_put(&list, (List_Elem *)&foo); + * bar = (MyStruct *)List_get(&list); + * @endcode + * + * The ::List_put and ::List_get APIs are used to maintain a first-in first-out + * (FIFO) linked list. + * + * The ::List_putHead and ::List_get APIs are used to maintain a last-in first-out + * (LIFO) linked list. + * + * Traversing a list from head to tail. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_head(&list); temp != NULL; temp = List_next(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * Traversing a list from tail to head. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_tail(&list); temp != NULL; temp = List_prev(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_utils_List__include +#define ti_drivers_utils_List__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef struct List_Elem { + struct List_Elem *next; + struct List_Elem *prev; +} List_Elem; + +typedef struct List_List { + List_Elem *head; + List_Elem *tail; +} List_List; + +/*! + * @brief Function to initialize the contents of a List_List + * + * @param list Pointer to a List_List structure that will be used to + * maintain a linked list + */ +extern void List_clearList(List_List *list); + +/*! + * @brief Function to test whether a linked list is empty + * + * @param list A pointer to a linked list + * + * @return true if empty, false if not empty + */ +extern bool List_empty(List_List *list); + +/*! + * @brief Function to atomically get the first elem in a linked list + * + * @param list A pointer to a linked list + * + * @return Pointer the first elem in the linked list or NULL if empty + */ +extern List_Elem *List_get(List_List *list); + +/*! + * @brief Function to return the head of a linked list + * + * This function does not remove the head, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the first elem in the linked list or NULL if empty + */ +extern List_Elem *List_head(List_List *list); + +/*! + * @brief Function to insert an elem into a linked list + * + * @param list A pointer to the linked list + * + * @param newElem New elem to insert + * + * @param curElem Elem to insert the newElem in front of. + * This value cannot be NULL. + */ +extern void List_insert(List_List *list, List_Elem *newElem, + List_Elem *curElem); + +/*! + * @brief Function to return the next elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * next one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the next elem in linked list or NULL if at the end + */ +extern List_Elem *List_next(List_Elem *elem); + +/*! + * @brief Function to return the prev elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * prev one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the prev elem in linked list or NULL if at the beginning + */ +extern List_Elem *List_prev(List_Elem *elem); + +/*! + * @brief Function to atomically put an elem onto the end of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the end of the linked list + */ +extern void List_put(List_List *list, List_Elem *elem); + +/*! + * @brief Function to atomically put an elem onto the head of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the beginning of the linked list + */ +extern void List_putHead(List_List *list, List_Elem *elem); + +/*! + * @brief Function to remove an elem from a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to be removed from a linked list + */ +extern void List_remove(List_List *list, List_Elem *elem); + +/*! + * @brief Function to return the tail of a linked list + * + * This function does not remove the tail, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the last elem in the linked list or NULL if empty + */ +extern List_Elem *List_tail(List_List *list); + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_List__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/RingBuf.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/RingBuf.c new file mode 100644 index 000000000..ace4f012c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/RingBuf.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +/* + * ======== RingBuf_construct ======== + */ +void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, + size_t bufSize) +{ + object->buffer = bufPtr; + object->length = bufSize; + object->count = 0; + object->head = bufSize - 1; + object->tail = 0; + object->maxCount = 0; +} + +/* + * ======== RingBuf_get ======== + */ +int RingBuf_get(RingBuf_Handle object, unsigned char *data) +{ + unsigned int key; + + key = HwiP_disable(); + + if (!object->count) { + HwiP_restore(key); + return -1; + } + + *data = object->buffer[object->tail]; + object->tail = (object->tail + 1) % object->length; + object->count--; + + HwiP_restore(key); + + return (object->count); +} + +/* + * ======== RingBuf_getCount ======== + */ +int RingBuf_getCount(RingBuf_Handle object) +{ + return (object->count); +} + +/* + * ======== RingBuf_isFull ======== + */ +bool RingBuf_isFull(RingBuf_Handle object) +{ + return (object->count == object->length); +} + +/* + * ======== RingBuf_getMaxCount ======== + */ +int RingBuf_getMaxCount(RingBuf_Handle object) +{ + return (object->maxCount); +} + +/* + * ======== RingBuf_peek ======== + */ +int RingBuf_peek(RingBuf_Handle object, unsigned char *data) +{ + unsigned int key; + int retCount; + + key = HwiP_disable(); + + *data = object->buffer[object->tail]; + retCount = object->count; + + HwiP_restore(key); + + return (retCount); +} + +/* + * ======== RingBuf_put ======== + */ +int RingBuf_put(RingBuf_Handle object, unsigned char data) +{ + unsigned int key; + unsigned int next; + + key = HwiP_disable(); + + if (object->count != object->length) { + next = (object->head + 1) % object->length; + object->buffer[next] = data; + object->head = next; + object->count++; + object->maxCount = (object->count > object->maxCount) ? + object->count : + object->maxCount; + } + else { + + HwiP_restore(key); + return (-1); + } + + HwiP_restore(key); + + return (object->count); +} diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/RingBuf.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/RingBuf.h new file mode 100644 index 000000000..29e8c8243 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/utils/RingBuf.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_uart_RingBuf__include +#define ti_drivers_uart_RingBuf__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef struct RingBuf_Object { + unsigned char *buffer; + size_t length; + size_t count; + size_t head; + size_t tail; + size_t maxCount; +} RingBuf_Object, *RingBuf_Handle; + +/*! + * @brief Initialize circular buffer + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param bufPtr Pointer to data buffer to be used for the circular buffer. + * The buffer is NOT stored in RingBuf_Object. + * + * @param bufSize The size of bufPtr in number of unsigned chars. + */ +void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, + size_t bufSize); + +/*! + * @brief Get an unsigned char from the end of the circular buffer and remove + * it. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from + * the front of the circular buffer. + * + * @return Number of unsigned chars on the buffer after taking it out + * of the circular buffer. If it returns -1, the circular + * buffer was already empty and data is invalid. + */ +int RingBuf_get(RingBuf_Handle object, unsigned char *data); + +/*! + * @brief Get the number of unsigned chars currently stored on the circular + * buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @return Number of unsigned chars on the circular buffer. + */ +int RingBuf_getCount(RingBuf_Handle object); + +/*! + * @brief Function to determine if the circular buffer is full or not. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @return true if circular buffer is full, else false. + */ +bool RingBuf_isFull(RingBuf_Handle object); + +/*! + * @brief A high-water mark indicating the largest number of unsigned chars + * stored on the circular buffer since it was constructed. + * + * @return Get the largest number of unsigned chars that were at one + * point in the circular buffer. + */ +int RingBuf_getMaxCount(RingBuf_Handle object); + +/*! + * @brief Get an unsigned char from the end of the circular buffer without + * removing it. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from + * the front of the circular buffer. This function does not + * remove the data from the circular buffer. Do not evaluate + * data if the count returned is equal to 0. + * + * @return Number of unsigned chars on the circular buffer. If the + * number != 0, then data will contain the unsigned char at the + * end of the circular buffer. + */ +int RingBuf_peek(RingBuf_Handle object, unsigned char *data); + +/*! + * @brief Put an unsigned char into the end of the circular buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data unsigned char to be placed at the end of the circular + * buffer. + * + * @return Number of unsigned chars on the buffer after it was added, + * or -1 if it's already full. + */ +int RingBuf_put(RingBuf_Handle object, unsigned char data); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_uart_RingBuf__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/watchdog/WatchdogCC32XX.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/watchdog/WatchdogCC32XX.h new file mode 100644 index 000000000..53b50e285 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/watchdog/WatchdogCC32XX.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file WatchdogCC32XX.h + * + * @brief Watchdog driver implementation for CC32XX + * + * The Watchdog header file for CC32XX should be included in an application + * as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref Watchdog.h for a complete description of APIs. + * + * This Watchdog driver implementation is designed to operate on a CC32XX + * device. Once opened, CC32XX Watchdog will count down from the reload + * value specified in the WatchdogCC32XX_HWAttrs. If it times out, the + * Watchdog interrupt flag will be set, and a user-provided callback function + * will be called. If the Watchdog Timer is allowed to time out again while + * the interrupt flag is still pending, a reset signal will be generated. + * To prevent a reset, Watchdog_clear() must be called to clear the interrupt + * flag. + * + * The reload value from which the Watchdog Timer counts down may be changed + * during runtime using Watchdog_setReload(). + * + * Watchdog_close() is not supported by this driver implementation. + * + * By default the Watchdog driver has resets turned on and this feature cannot + * be turned disabled. + * + * To have a user-defined function run at the warning interrupt, first define + * a void-type function that takes a Watchdog_Handle cast to a UArg as an + * argument. The callback and code to start the Watchdog timer are shown below. + * + * @code + * void watchdogCallback(UArg handle); + * + * ... + * + * Watchdog_Handle handle; + * Watchdog_Params params; + * uint32_t tickValue; + * + * Watchdog_Params_init(¶ms); + * params.callbackFxn = watchdogCallback; + * handle = Watchdog_open(Watchdog_configIndex, ¶ms); + * // Set timeout period to 100 ms + * tickValue = Watchdog_convertMsToTicks(handle, 100); + * Watchdog_setReload(handle, tickValue); + * + * ... + * + * void watchdogCallback(UArg handle) + * { + * // User-defined code here + * ... + * + * } + * @endcode + * ============================================================================ + */ + +#ifndef ti_drivers_watchdog_WatchdogCC32XX__include +#define ti_drivers_watchdog_WatchdogCC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @addtogroup Watchdog_STATUS + * WatchdogCC32XX_STATUS_* macros are command codes only defined in the + * WatchdogCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add WatchdogCC32XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup Watchdog_CMD + * WatchdogCC32XX_CMD_* macros are command codes only defined in the + * WatchdogCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by Watchdog_control to determines + * whether the watchdog timer is enabled + * + * With this command code, @b arg is a pointer to a @c bool. + * @b *arg contains @c true if the watchdog timer is enabled, + * else @c false if it is not. + */ +#define WatchdogCC32XX_CMD_IS_TIMER_ENABLE (Watchdog_CMD_RESERVED + 0) + + +/*! + * @brief Command used by Watchdog_control + * to gets the current watchdog timer value + * + * With this command code, @b arg is a pointer to an @a integer. + * @b *arg contains the current value of the watchdog timer. + */ +#define WatchdogCC32XX_CMD_GET_TIMER_VALUE (Watchdog_CMD_RESERVED + 1) + + +/*! + * @brief Command used by Watchdog_control to determines + * whether the watchdog timer is locked + * + * With this command code, @b arg is a pointer to a @c bool. + * @b *arg contains @c true if the watchdog timer is locked, + * else @c false if it is not. + */ +#define WatchdogCC32XX_CMD_IS_TIMER_LOCKED (Watchdog_CMD_RESERVED + 2) + + +/*! + * @brief Command used by Watchdog_control + * to gets the current watchdog timer reload value + * + * With this command code, @b arg is a pointer to an @a integer. + * @b *arg contains the current value loaded into the watchdog timer when + * the count reaches zero for the first time. + */ +#define WatchdogCC32XX_CMD_GET_TIMER_RELOAD_VALUE (Watchdog_CMD_RESERVED + 3) + + +/** @}*/ + +/*! @brief Watchdog function table for CC32XX */ +extern const Watchdog_FxnTable WatchdogCC32XX_fxnTable; + +/*! + * @brief Watchdog hardware attributes for CC32XX + * + * intPriority is the Watchdog timer's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + */ +typedef struct WatchdogCC32XX_HWAttrs { + unsigned int baseAddr; /*!< Base adddress for Watchdog */ + unsigned int intNum; /*!< WDT interrupt number */ + unsigned int intPriority; /*!< WDT interrupt priority */ + uint32_t reloadValue; /*!< Reload value for Watchdog */ +} WatchdogCC32XX_HWAttrs; + +/*! + * @brief Watchdog Object for CC32XX + * + * Not to be accessed by the user. + */ +typedef struct WatchdogCC32XX_Object { + bool isOpen; /* Flag for open/close status */ +} WatchdogCC32XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_watchdog_WatchdogCC32XX__include */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/startup_cc32xx_ccs.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/startup_cc32xx_ccs.c new file mode 100644 index 000000000..dc9fff532 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/startup_cc32xx_ccs.c @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void resetISR(void); +static void nmiISR(void); +static void faultISR(void); +static void defaultHandler(void); +static void busFaultHandler(void); + +//***************************************************************************** +// +// External declaration for the reset handler that is to be called when the +// processor is started +// +//***************************************************************************** +extern void _c_int00(void); +extern void vPortSVCHandler(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); + +//***************************************************************************** +// +// Linker variable that marks the top of the stack. +// +//***************************************************************************** +extern unsigned long __STACK_END; + +//***************************************************************************** +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000 or at the start of +// the program if located at a start address other than 0. +// +//***************************************************************************** +#pragma RETAIN(resetVectors) +#pragma DATA_SECTION(resetVectors, ".resetVecs") +void (* const resetVectors[16])(void) = +{ + (void (*)(void))((unsigned long)&__STACK_END), + // The initial stack pointer + resetISR, // The reset handler + nmiISR, // The NMI handler + faultISR, // The hard fault handler + defaultHandler, // The MPU fault handler + busFaultHandler, // The bus fault handler + defaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + vPortSVCHandler, // SVCall handler + defaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler // The SysTick handler +}; + + +#pragma DATA_SECTION(ramVectors, ".ramVecs") +static unsigned long ramVectors[256]; + +//***************************************************************************** +// +// Copy the first 16 vectors from the read-only/reset table to the runtime +// RAM table. Fill the remaining vectors with a stub. This vector table will +// be updated at runtime. +// +//***************************************************************************** +void initVectors(void) +{ + int i; + + /* Copy from reset vector table into RAM vector table */ + memcpy(ramVectors, resetVectors, 16*4); + + /* fill remaining vectors with default handler */ + for (i=16; i < 256; i++) { + ramVectors[i] = (unsigned long)defaultHandler; + } + + /* Set vector table base */ + MAP_IntVTableBaseSet((unsigned long)&ramVectors[0]); + + /* Enable Processor */ + MAP_IntMasterEnable(); + MAP_IntEnable(FAULT_SYSTICK); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void resetISR(void) +{ + /* + * Set stack pointer based on the stack value stored in the vector table. + * This is necessary to ensure that the application is using the correct + * stack when using a debugger since a reset within the debugger will + * load the stack pointer from the bootloader's vector table at address '0'. + */ + __asm(" .global resetVectorAddr\n" + " ldr r0, resetVectorAddr\n" + " ldr r0, [r0]\n" + " mov sp, r0\n" + " bl initVectors"); + + /* Jump to the CCS C Initialization Routine. */ + __asm(" .global _c_int00\n" + " b.w _c_int00"); + + _Pragma("diag_suppress 1119"); + __asm("resetVectorAddr: .word resetVectors"); + _Pragma("diag_default 1119"); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +nmiISR(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +faultISR(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** + +static void +busFaultHandler(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +defaultHandler(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} -- 2.39.5