From 6f94fa21cc7552dae9bf452e12eaa85c8897fcbb Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Wed, 21 Sep 2016 10:26:00 +0800 Subject: [PATCH] arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1 Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See Cc: Marek Vasut Cc: Dinh Nguyen --- board/is1/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h index 67ea1ec21e..8ce3c70e78 100644 --- a/board/is1/qts/sdram_config.h +++ b/board/is1/qts/sdram_config.h @@ -49,6 +49,9 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777 -- 2.39.5