From 704744f81bd478e9b1ef4fae9b14201f17bd8fe3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Apr 2018 10:46:49 +0200 Subject: [PATCH] arm64: zynqmp: Remove pinctrl settings This part hasn't been pushed to mainline yet that's why remove it. The patch can be reverted in future when this is pushed there. Reported-by: Alexander Graf Signed-off-by: Michal Simek Reviewed-by: Alexander Graf --- arch/arm/dts/zynqmp-zcu102-revA.dts | 288 ------------------- include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 30 -- 2 files changed, 318 deletions(-) delete mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 059d1ffe86..b7c638bc9e 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -13,7 +13,6 @@ #include "zynqmp-clk-ccf.dtsi" #include #include -#include #include / { @@ -70,8 +69,6 @@ &can1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_default>; }; &dcc { @@ -114,8 +111,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; @@ -126,8 +121,6 @@ &gpio { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_default>; }; &gpu { @@ -137,11 +130,6 @@ &i2c0 { status = "okay"; clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0_default>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -391,11 +379,6 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ @@ -545,269 +528,6 @@ }; }; -&pinctrl0 { - status = "okay"; - pinctrl_i2c0_default: i2c0-default { - mux { - groups = "i2c0_3_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_3_grp"; - bias-pull-up; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_i2c0_gpio: i2c0-gpio { - mux { - groups = "gpio0_14_grp", "gpio0_15_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_14_grp", "gpio0_15_grp"; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_i2c1_default: i2c1-default { - mux { - groups = "i2c1_4_grp"; - function = "i2c1"; - }; - - conf { - groups = "i2c1_4_grp"; - bias-pull-up; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - mux { - groups = "gpio0_16_grp", "gpio0_17_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_16_grp", "gpio0_17_grp"; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_uart0_default: uart0-default { - mux { - groups = "uart0_4_grp"; - function = "uart0"; - }; - - conf { - groups = "uart0_4_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO18"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO19"; - bias-disable; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_5_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_5_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO21"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO20"; - bias-disable; - }; - }; - - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", - "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - }; - - pinctrl_gem3_default: gem3-default { - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - - conf { - groups = "ethernet3_0_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", - "MIO75"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", - "MIO69"; - bias-disable; - low-power-enable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = ; - io-standard = ; - bias-disable; - }; - }; - - pinctrl_can1_default: can1-default { - mux { - function = "can1"; - groups = "can1_6_grp"; - }; - - conf { - groups = "can1_6_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO25"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO24"; - bias-disable; - }; - }; - - pinctrl_sdhci1_default: sdhci1-default { - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - - conf { - groups = "sdio1_0_grp"; - slew-rate = ; - io-standard = ; - bias-disable; - }; - - mux-cd { - groups = "sdio1_0_cd_grp"; - function = "sdio1_cd"; - }; - - conf-cd { - groups = "sdio1_0_cd_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = ; - io-standard = ; - }; - - mux-wp { - groups = "sdio1_0_wp_grp"; - function = "sdio1_wp"; - }; - - conf-wp { - groups = "sdio1_0_wp_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_gpio_default: gpio-default { - mux-sw { - function = "gpio0"; - groups = "gpio0_22_grp", "gpio0_23_grp"; - }; - - conf-sw { - groups = "gpio0_22_grp", "gpio0_23_grp"; - slew-rate = ; - io-standard = ; - }; - - mux-msp { - function = "gpio0"; - groups = "gpio0_13_grp", "gpio0_38_grp"; - }; - - conf-msp { - groups = "gpio0_13_grp", "gpio0_38_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-pull-up { - pins = "MIO22", "MIO23"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO13", "MIO38"; - bias-disable; - }; - }; -}; - &pcie { status = "okay"; }; @@ -864,8 +584,6 @@ /* SD1 with level shifter */ &sdhci1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ xlnx,mio_bank = <1>; }; @@ -876,21 +594,15 @@ &uart0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h deleted file mode 100644 index e1b81fe5ef..0000000000 --- a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * MIO pin configuration defines for Xilinx ZynqMP - * - * Copyright (C) 2017 Xilinx, Inc. - * Author: Chirag Parekh - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H -#define _DT_BINDINGS_PINCTRL_ZYNQMP_H - -/* Bit value for IO standards */ -#define IO_STANDARD_LVCMOS33 0 -#define IO_STANDARD_LVCMOS18 1 - -/* Bit values for Slew Rates */ -#define SLEW_RATE_FAST 0 -#define SLEW_RATE_SLOW 1 - -/* Bit values for Pin inputs */ -#define PIN_INPUT_TYPE_CMOS 0 -#define PIN_INPUT_TYPE_SCHMITT 1 - -#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ -- 2.39.5