From 72740904568414bb4a9192fe89034bae3b1a9e45 Mon Sep 17 00:00:00 2001 From: Matthias Welwarsky Date: Tue, 13 Mar 2018 17:03:38 +0100 Subject: [PATCH] tcl/board: add configuration for the avnet ultrazed-eg starter kit also contains target configuration for the Xilinx UltraScale+ platform Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/4467 Tested-by: jenkins Reviewed-by: Matthias Welwarsky --- tcl/board/avnet_ultrazed-eg.cfg | 16 ++++++ tcl/target/xilinx_ultrascale.cfg | 90 ++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 tcl/board/avnet_ultrazed-eg.cfg create mode 100644 tcl/target/xilinx_ultrascale.cfg diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg new file mode 100644 index 00000000..a0ac5c6a --- /dev/null +++ b/tcl/board/avnet_ultrazed-eg.cfg @@ -0,0 +1,16 @@ +# +# AVNET UltraZED EG StarterKit +# UlraScale-EG plus IO Carrier with on-board digilent smt2 +# +source [find interface/ftdi/digilent_jtag_smt2_nc.cfg] +# jtag transport only +transport select jtag +# reset lines are not wired +reset_config none + +# slow default clock +adapter_khz 1000 + +set CHIPNAME uscale + +source [find target/xilinx_ultrascale.cfg] diff --git a/tcl/target/xilinx_ultrascale.cfg b/tcl/target/xilinx_ultrascale.cfg new file mode 100644 index 00000000..9be198dc --- /dev/null +++ b/tcl/target/xilinx_ultrascale.cfg @@ -0,0 +1,90 @@ +# +# target configuration for +# Xilinx UltraScale+ +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME uscale +} + +# +# DAP tap +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID + +# +# PS tap +# +if { [info exists PS_TAPID] } { + set _PS_TAPID $PS_TAPID +} else { + set _PS_TAPID 0x04710093 +} + +set jtag_configured 0 + +jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID + +jtag configure $_CHIPNAME.ps -event setup { + global _CHIPNAME + global jtag_configured + + if { $jtag_configured == 0 } { + # add the DAP tap to the chain + # See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924 + irscan $_CHIPNAME.ps 0x824 + drscan $_CHIPNAME.ps 32 0x00000003 + runtest 100 + + # setup event will be re-entered through jtag arp_init + # break the recursion + set jtag_configured 1 + # re-initialized the jtag chain + jtag arp_init + } +} + +set _TARGETNAME $_CHIPNAME.a53 +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} +set _cores 4 + +for { set _core 0 } { $_core < $_cores } { incr _core } { + + cti create $_CTINAME.$_core -chain-position $_CHIPNAME.dap -ap-num 1 \ + -ctibase [lindex $CTIBASE $_core] + + set _command "target create $_TARGETNAME.$_core aarch64 -chain-position $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core" + + if { $_core != 0 } { + # non-boot core examination may fail + set _command "$_command -defer-examine" + set _smp_command "$_smp_command $_TARGETNAME.$_core" + } else { + # uncomment when "hawt" rtos is merged + #set _command "$_command -rtos hawt" + set _smp_command "target smp $_TARGETNAME.$_core" + } + + eval $_command +} + +eval $_smp_command +targets $_TARGETNAME.0 + +proc core_up { args } { + global _TARGETNAME + foreach { core } [set args] { + $_TARGETNAME.$core arp_examine + } +} -- 2.39.5