From 73aede596cea7adc8e76dfbf92662cfc2eb0de5c Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Thu, 24 May 2018 00:17:29 +0800 Subject: [PATCH] arm: socfpga: stratix10: Add timer support for Stratix10 SoC Add timer support for Stratix SoC Signed-off-by: Chin Liang See Signed-off-by: Ley Foon Tan Reviewed-by: Marek Vasut --- arch/arm/mach-socfpga/Makefile | 4 +++- arch/arm/mach-socfpga/timer_s10.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-socfpga/timer_s10.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 3131949d68..654999cdf6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,7 +9,6 @@ obj-y += board.o obj-y += clock_manager.o obj-y += misc.o obj-y += reset_manager.o -obj-y += timer.o ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += clock_manager_gen5.o @@ -17,6 +16,7 @@ obj-y += misc_gen5.o obj-y += reset_manager_gen5.o obj-y += scan_manager.o obj-y += system_manager_gen5.o +obj-y += timer.o obj-y += wrap_pll_config.o obj-y += fpga_manager.o endif @@ -26,6 +26,7 @@ obj-y += clock_manager_arria10.o obj-y += misc_arria10.o obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o +obj-y += timer.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 @@ -35,6 +36,7 @@ obj-y += misc_s10.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o +obj-y += timer_s10.o obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c new file mode 100644 index 0000000000..57237892c3 --- /dev/null +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017-2018 Intel Corporation + * + */ + +#include +#include +#include + +/* + * Timer initialization + */ +int timer_init(void) +{ + int enable = 0x3; /* timer enable + output signal masked */ + int loadval = ~0; + + /* enable system counter */ + writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS); + /* enable processor pysical counter */ + asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); + asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); + + return 0; +} -- 2.39.5