From 79d0f1345b8d68ff522f21451860c74c8f1018ca Mon Sep 17 00:00:00 2001 From: Jiri Kastner Date: Thu, 5 May 2016 11:35:10 +0200 Subject: [PATCH] arm_adi_v5: added partnumber for APQ8016 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit On APQ8016 was found a CoreSight component designed by Qualcomm, according to db410c HRM [1] it has a partnumber following this schema: [11:8] is 0x4 meaning Qualcomm designed Coresight component in QDSS. Reads as 0x4. [7:6] is Subsystem/core family ID (e.g. denote QDSS family or generation). [5:4] is Subsystem/core configuration options (e.g. denote cache options, etc.). [3:2] is Subsystem/core fuse options. [1:0] is Subsystem/core future use field Reads as 0x440. [1] - https://developer.qualcomm.com/download/sd410/hardware-register-description-qualcomm-snapdragon-410.pdf Change-Id: I9b4b41fd17c59d2f5ae35b53278d06d6087665f8 Signed-off-by: Jiri Kastner Signed-off-by: Andreas Färber Reviewed-on: http://openocd.zylin.com/3408 Tested-by: jenkins Reviewed-by: Freddie Chopin --- src/target/arm_adi_v5.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 8ab873bb..b92ecb30 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1040,6 +1040,7 @@ static const struct { { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", }, { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", }, { 0x0E5, 0x000, "SHARC+/Blackfin+", "", }, + { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", }, /* legacy comment: 0x113: what? */ { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */ { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */ -- 2.39.5