From 7ae5b45f75f0becea3bc8e165ddd19a84674fbed Mon Sep 17 00:00:00 2001 From: Evan Hunter Date: Fri, 17 Jul 2015 12:37:35 +0100 Subject: [PATCH] Documentation : Add missing commands for ARM-v7A & R Change-Id: I520fed122385d4d666bf91b754b1ac196b51d471 Signed-off-by: Evan Hunter Reviewed-on: http://openocd.zylin.com/2875 Reviewed-by: Matthias Welwarsky Reviewed-by: Freddie Chopin Tested-by: jenkins --- doc/openocd.texi | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/doc/openocd.texi b/doc/openocd.texi index 1248727d..eb4bd4ee 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -7568,6 +7568,54 @@ fix CSW_SPROT from register AP_REG_CSW on selected dap. Defaulting to 0. @end deffn +@deffn Command {dap ti_be_32_quirks} [@option{enable}] +Set/get quirks mode for TI TMS450/TMS570 processors +Disabled by default +@end deffn + + +@subsection ARMv7-A specific commands +@cindex Cortex-A + +@deffn Command {cortex_a cache_info} +display information about target caches +@end deffn + +@deffn Command {cortex_a dbginit} +Initialize core debug +Enables debug by unlocking the Software Lock and clearing sticky powerdown indications +@end deffn + +@deffn Command {cortex_a smp_off} +Disable SMP mode +@end deffn + +@deffn Command {cortex_a smp_on} +Enable SMP mode +@end deffn + +@deffn Command {cortex_a smp_gdb} [core_id] +Display/set the current core displayed in GDB +@end deffn + +@deffn Command {cortex_a maskisr} [@option{on}|@option{off}] +Selects whether interrupts will be processed when single stepping +@end deffn + +@deffn Command {cache_config l2x} [base way] +configure l2x cache +@end deffn + + +@subsection ARMv7-R specific commands +@cindex Cortex-R + +@deffn Command {cortex_r dbginit} +Initialize core debug +Enables debug by unlocking the Software Lock and clearing sticky powerdown indications +@end deffn + + @subsection ARMv7-M specific commands @cindex tracing @cindex SWO -- 2.39.5