From 7ba05378381e2a9138c42161ece86e3c5f2e380f Mon Sep 17 00:00:00 2001 From: Salvador Arroyo Date: Sun, 24 Aug 2014 19:34:08 +0200 Subject: [PATCH] Fix for BMIPS BMIPS always needs 2 additional instructions to reach the core. Seems there is a 2 instructions fifo between the tap and the core, or it behaves in this way. No idea of the purpose of this fifo, I can only guess. Of course function mips32_pracc_clean_text_jump() must add this additional instructions (NOPs). Only tested on bcm3348.. Change-Id: I3183d3ce865d469d7262ba4b15446e5743a5f1df Signed-off-by: Salvador Arroyo Reviewed-on: http://openocd.zylin.com/2270 Tested-by: jenkins Reviewed-by: Kent Brinkley Reviewed-by: Spencer Oliver --- src/target/mips32_pracc.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index e97626cb..c08e3249 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -160,19 +160,22 @@ int mips32_pracc_clean_text_jump(struct mips_ejtag *ejtag_info) return retval; } - if (ejtag_info->mode != 0) /* done, queued mode won't work with lexra cores */ + if (ejtag_info->mode != 0) /* async mode support only for MIPS ... */ return ERROR_OK; - retval = mips32_pracc_read_ctrl_addr(ejtag_info); - if (retval != ERROR_OK) - return retval; - - if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT) { /* LEXRA/BMIPS ?, shift out another NOP */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); - mips_ejtag_drscan_32_out(ejtag_info, MIPS32_NOP); - retval = mips32_pracc_finish(ejtag_info); + for (int i = 0; i != 2; i++) { + retval = mips32_pracc_read_ctrl_addr(ejtag_info); if (retval != ERROR_OK) return retval; + + if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT) { /* LEXRA/BMIPS ?, shift out another NOP, max 2 */ + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); + mips_ejtag_drscan_32_out(ejtag_info, MIPS32_NOP); + retval = mips32_pracc_finish(ejtag_info); + if (retval != ERROR_OK) + return retval; + } else + break; } return ERROR_OK; -- 2.39.5