XPS Project Report

From 85484f240b5e5ca1cf7ea419901dbad7aa3cfd52 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Sat, 27 Aug 2011 14:23:59 +0000 Subject: [PATCH] Remove some large files from the repository that don't need to be there. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1567 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../SDK/SDK_Export/hw/system.html | 12 - .../SDK/SDK_Export/hw/system_main.html | 5397 ---------------- .../SDK/SDK_Export/hw/system_mainNF.html | 5407 ----------------- .../SDK/SDK_Export/hw/system_toc.html | 73 - 4 files changed, 10889 deletions(-) delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html deleted file mode 100644 index 1dda8a75f..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html +++ /dev/null @@ -1,12 +0,0 @@ - - - - -XPS Project Report - -XPS Project Report - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html deleted file mode 100644 index 0864e1f1c..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html +++ /dev/null @@ -1,5397 +0,0 @@ - - - - -XPS Project Report - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Printable Version

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Overview

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Resources Used
1Â Â	MicroBlaze
2Â Â	AXI Interconnect
2Â Â	Local Memory Bus (LMB) 1.0
1Â Â	Block RAM (BRAM) Block
2Â Â	LMB BRAM Controller
1Â Â	AXI S6 Memory Controller(DDR/DDR2/DDR3)
1Â Â	Processor System Reset Module
1Â Â	Clock Generator
1Â Â	MicroBlaze Debug Module (MDM)
1Â Â	AXI UART (Lite)
2Â Â	AXI General Purpose IO
1Â Â	AXI 10/100 Ethernet MAC Lite
1Â Â	AXI Timer/Counter
1Â Â	AXI Interrupt Controller

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Specifics
Generated	Wed Jul 27 11:49:42 2011
EDK Version	13.1
Device Family	spartan6
Device	xc6slx45tfgg484-3

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Block Diagram	TOP

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BlockDiagram

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External Ports	TOP

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- These are the external ports defined in the MHS file. -

-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLKÂ Â indicates Clock ports, (SIGIS = CLK)Â
INTRÂ Â indicates Interrupt ports,(SIGIS = INTR)Â
RESETÂ Â indicates Reset ports, (SIGIS = RST)Â
BUF or REGÂ Â Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)Â -

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#	NAME		DIR	[LSB:MSB]	SIG		ATTRIBUTES
-SHARED -	RESET		I	1	RESET		Â RESETÂ
-Ethernet_Lite -	Ethernet_Lite_COL		I	1	Ethernet_Lite_COL
-Ethernet_Lite -	Ethernet_Lite_CRS		I	1	Ethernet_Lite_CRS
-Ethernet_Lite -	Ethernet_Lite_RXD		I	0:3	Ethernet_Lite_RXD
-Ethernet_Lite -	Ethernet_Lite_RX_CLK		I	1	Ethernet_Lite_RX_CLK
-Ethernet_Lite -	Ethernet_Lite_RX_DV		I	1	Ethernet_Lite_RX_DV
-Ethernet_Lite -	Ethernet_Lite_RX_ER		I	1	Ethernet_Lite_RX_ER
-Ethernet_Lite -	Ethernet_Lite_TX_CLK		I	1	Ethernet_Lite_TX_CLK
-Ethernet_Lite -	Ethernet_Lite_MDIO		IO	1	Ethernet_Lite_MDIO
-Ethernet_Lite -	Ethernet_Lite_MDC		O	1	Ethernet_Lite_MDC
-Ethernet_Lite -	Ethernet_Lite_PHY_RST_N		O	1	Ethernet_Lite_PHY_RST_N
-Ethernet_Lite -	Ethernet_Lite_TXD		O	0:3	Ethernet_Lite_TXD
-Ethernet_Lite -	Ethernet_Lite_TX_EN		O	1	Ethernet_Lite_TX_EN
-LEDs_4Bits -	LEDs_4Bits_TRI_O		O	3:0	LEDs_4Bits_TRI_O
-MCB_DDR3 -	mcbx_dram_dq		IO	0:15	mcbx_dram_dq
-MCB_DDR3 -	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
-MCB_DDR3 -	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
-MCB_DDR3 -	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
-MCB_DDR3 -	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
-MCB_DDR3 -	rzq		IO	1	rzq
-MCB_DDR3 -	zio		IO	1	zio
-MCB_DDR3 -	mcbx_dram_addr		O	0:12	mcbx_dram_addr
-MCB_DDR3 -	mcbx_dram_ba		O	0:2	mcbx_dram_ba
-MCB_DDR3 -	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
-MCB_DDR3 -	mcbx_dram_cke		O	1	mcbx_dram_cke
-MCB_DDR3 -	mcbx_dram_clk		O	1	mcbx_dram_clk
-MCB_DDR3 -	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
-MCB_DDR3 -	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
-MCB_DDR3 -	mcbx_dram_ldm		O	1	mcbx_dram_ldm
-MCB_DDR3 -	mcbx_dram_odt		O	1	mcbx_dram_odt
-MCB_DDR3 -	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
-MCB_DDR3 -	mcbx_dram_udm		O	1	mcbx_dram_udm
-MCB_DDR3 -	mcbx_dram_we_n		O	1	mcbx_dram_we_n
-Push_Buttons_4Bits -	Push_Buttons_4Bits_TRI_I		I	0:3	Push_Buttons_4Bits_TRI_I
-RS232_Uart_1 -	RS232_Uart_1_sin		I	1	RS232_Uart_1_sin
-RS232_Uart_1 -	RS232_Uart_1_sout		O	1	RS232_Uart_1_sout
-clock_generator_0 -	CLK_N		I	1	CLK		Â CLKÂ
-clock_generator_0 -	CLK_P		I	1	CLK		Â CLKÂ

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Processors	TOP

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-microblaze_0 - Â Â MicroBlaze
The MicroBlaze 32 bit soft processor

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IP Specs
Core	Version	Documentation
microblaze	8.10.a	IP

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microblaze_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	MB_RESET		I	1	proc_sys_reset_0_MB_Reset
1	CLK		I	1	clk_100_0000MHzPLL0
2	INTERRUPT		I	1	microblaze_0_interrupt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
M_AXI_DP	MASTER	AXI	axi4lite_0			7 Peripherals.
M_AXI_DC	MASTER	AXI	axi4_0			MCB_DDR3
M_AXI_IC	MASTER	AXI	axi4_0			MCB_DDR3
DLMB	MASTER	LMB	microblaze_0_dlmb			microblaze_0_d_bram_ctrl
ILMB	MASTER	LMB	microblaze_0_ilmb			microblaze_0_i_bram_ctrl
DEBUG	TARGET	XIL_MBDEBUG3	microblaze_0_debug			debug_module

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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Name	Value
C_SCO	0
C_FREQ	0
C_DATA_SIZE	32
C_DYNAMIC_BUS_SIZING	1
C_FAMILY	virtex5
C_INSTANCE	microblaze
C_FAULT_TOLERANT	0
C_ECC_USE_CE_EXCEPTION	0
C_ENDIANNESS	0
C_AREA_OPTIMIZED	0
C_OPTIMIZATION	0
C_INTERCONNECT	2
C_STREAM_INTERCONNECT	0
C_DPLB_DWIDTH	32
C_DPLB_NATIVE_DWIDTH	32
C_DPLB_BURST_EN	0
C_DPLB_P2P	0
C_IPLB_DWIDTH	32
C_IPLB_NATIVE_DWIDTH	32
C_IPLB_BURST_EN	0
C_IPLB_P2P	0
C_M_AXI_DP_SUPPORTS_THREADS	0
C_M_AXI_DP_THREAD_ID_WIDTH	1
C_M_AXI_DP_SUPPORTS_READ	1
C_M_AXI_DP_SUPPORTS_WRITE	1
C_M_AXI_DP_SUPPORTS_NARROW_BURST	0
C_M_AXI_DP_DATA_WIDTH	32
C_M_AXI_DP_ADDR_WIDTH	32
C_M_AXI_DP_PROTOCOL	AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS	0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING	1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING	1
C_M_AXI_IP_SUPPORTS_THREADS	0
C_M_AXI_IP_THREAD_ID_WIDTH	1
C_M_AXI_IP_SUPPORTS_READ	1
C_M_AXI_IP_SUPPORTS_WRITE	0
C_M_AXI_IP_SUPPORTS_NARROW_BURST	0
C_M_AXI_IP_DATA_WIDTH	32
C_M_AXI_IP_ADDR_WIDTH	32
C_M_AXI_IP_PROTOCOL	AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING	1
C_D_AXI	0
C_D_PLB	0
C_D_LMB	1
C_I_AXI	0
C_I_PLB	0
C_I_LMB	1
C_USE_MSR_INSTR	1
C_USE_PCMP_INSTR	1
C_USE_BARREL	1
C_USE_DIV	1
C_USE_HW_MUL	1
C_USE_FPU	1
C_UNALIGNED_EXCEPTIONS	1
C_ILL_OPCODE_EXCEPTION	1
C_M_AXI_I_BUS_EXCEPTION	1
C_M_AXI_D_BUS_EXCEPTION	1
C_IPLB_BUS_EXCEPTION	0
C_DPLB_BUS_EXCEPTION	0
C_DIV_ZERO_EXCEPTION	1
C_FPU_EXCEPTION	1
C_FSL_EXCEPTION	0
C_USE_STACK_PROTECTION	0
C_PVR	0
C_PVR_USER1	0x00
C_PVR_USER2	0x00000000
C_DEBUG_ENABLED	1
C_NUMBER_OF_PC_BRK	7
C_NUMBER_OF_RD_ADDR_BRK	2
C_NUMBER_OF_WR_ADDR_BRK	2
C_INTERRUPT_IS_EDGE	0
C_EDGE_IS_POSITIVE	1
C_RESET_MSR	0x00000000
C_OPCODE_0x0_ILLEGAL	1
C_FSL_LINKS	0
C_FSL_DATA_SIZE	32
C_USE_EXTENDED_FSL_INSTR	0
C_M0_AXIS_PROTOCOL	GENERIC
C_S0_AXIS_PROTOCOL	GENERIC
C_M1_AXIS_PROTOCOL	GENERIC
C_S1_AXIS_PROTOCOL	GENERIC
C_M2_AXIS_PROTOCOL	GENERIC
C_S2_AXIS_PROTOCOL	GENERIC
C_M3_AXIS_PROTOCOL	GENERIC
C_S3_AXIS_PROTOCOL	GENERIC
C_M4_AXIS_PROTOCOL	GENERIC
C_S4_AXIS_PROTOCOL	GENERIC
C_M5_AXIS_PROTOCOL	GENERIC
C_S5_AXIS_PROTOCOL	GENERIC
C_M6_AXIS_PROTOCOL	GENERIC
C_S6_AXIS_PROTOCOL	GENERIC
C_M7_AXIS_PROTOCOL	GENERIC
C_S7_AXIS_PROTOCOL	GENERIC
C_M8_AXIS_PROTOCOL	GENERIC
C_S8_AXIS_PROTOCOL	GENERIC
C_M9_AXIS_PROTOCOL	GENERIC
C_S9_AXIS_PROTOCOL	GENERIC
C_M10_AXIS_PROTOCOL	GENERIC
C_S10_AXIS_PROTOCOL	GENERIC
C_M11_AXIS_PROTOCOL	GENERIC
C_S11_AXIS_PROTOCOL	GENERIC
C_M12_AXIS_PROTOCOL	GENERIC
C_S12_AXIS_PROTOCOL	GENERIC
C_M13_AXIS_PROTOCOL	GENERIC
C_S13_AXIS_PROTOCOL	GENERIC
C_M14_AXIS_PROTOCOL	GENERIC
C_S14_AXIS_PROTOCOL	GENERIC
C_M15_AXIS_PROTOCOL	GENERIC
C_S15_AXIS_PROTOCOL	GENERIC
C_M0_AXIS_DATA_WIDTH	32
C_S0_AXIS_DATA_WIDTH	32
C_M1_AXIS_DATA_WIDTH	32
C_S1_AXIS_DATA_WIDTH	32
C_M2_AXIS_DATA_WIDTH	32
C_S2_AXIS_DATA_WIDTH	32

Â

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Name	Value
C_M3_AXIS_DATA_WIDTH	32
C_S3_AXIS_DATA_WIDTH	32
C_M4_AXIS_DATA_WIDTH	32
C_S4_AXIS_DATA_WIDTH	32
C_M5_AXIS_DATA_WIDTH	32
C_S5_AXIS_DATA_WIDTH	32
C_M6_AXIS_DATA_WIDTH	32
C_S6_AXIS_DATA_WIDTH	32
C_M7_AXIS_DATA_WIDTH	32
C_S7_AXIS_DATA_WIDTH	32
C_M8_AXIS_DATA_WIDTH	32
C_S8_AXIS_DATA_WIDTH	32
C_M9_AXIS_DATA_WIDTH	32
C_S9_AXIS_DATA_WIDTH	32
C_M10_AXIS_DATA_WIDTH	32
C_S10_AXIS_DATA_WIDTH	32
C_M11_AXIS_DATA_WIDTH	32
C_S11_AXIS_DATA_WIDTH	32
C_M12_AXIS_DATA_WIDTH	32
C_S12_AXIS_DATA_WIDTH	32
C_M13_AXIS_DATA_WIDTH	32
C_S13_AXIS_DATA_WIDTH	32
C_M14_AXIS_DATA_WIDTH	32
C_S14_AXIS_DATA_WIDTH	32
C_M15_AXIS_DATA_WIDTH	32
C_S15_AXIS_DATA_WIDTH	32
C_ICACHE_BASEADDR	0xC0000000
C_ICACHE_HIGHADDR	0xC7FFFFFF
C_USE_ICACHE	1
C_ALLOW_ICACHE_WR	1
C_ADDR_TAG_BITS	17
C_CACHE_BYTE_SIZE	16384
C_ICACHE_USE_FSL	1
C_ICACHE_LINE_LEN	4
C_ICACHE_ALWAYS_USED	1
C_ICACHE_INTERFACE	0
C_ICACHE_VICTIMS	0
C_ICACHE_STREAMS	0
C_ICACHE_FORCE_TAG_LUTRAM	0
C_ICACHE_DATA_WIDTH	0
C_M_AXI_IC_SUPPORTS_THREADS	0
C_M_AXI_IC_THREAD_ID_WIDTH	1
C_M_AXI_IC_SUPPORTS_READ	1
C_M_AXI_IC_SUPPORTS_WRITE	0
C_M_AXI_IC_SUPPORTS_NARROW_BURST	0
C_M_AXI_IC_DATA_WIDTH	32
C_M_AXI_IC_ADDR_WIDTH	32
C_M_AXI_IC_PROTOCOL	AXI4
C_M_AXI_IC_USER_VALUE	0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_IC_AWUSER_WIDTH	5
C_M_AXI_IC_ARUSER_WIDTH	5
C_M_AXI_IC_WUSER_WIDTH	1
C_M_AXI_IC_RUSER_WIDTH	1
C_M_AXI_IC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING	2
C_DCACHE_BASEADDR	0xC0000000
C_DCACHE_HIGHADDR	0xC7FFFFFF
C_USE_DCACHE	1
C_ALLOW_DCACHE_WR	1
C_DCACHE_ADDR_TAG	17
C_DCACHE_BYTE_SIZE	16384
C_DCACHE_USE_FSL	1
C_DCACHE_LINE_LEN	4
C_DCACHE_ALWAYS_USED	1
C_DCACHE_INTERFACE	0
C_DCACHE_USE_WRITEBACK	0
C_DCACHE_VICTIMS	0
C_DCACHE_FORCE_TAG_LUTRAM	0
C_DCACHE_DATA_WIDTH	0
C_M_AXI_DC_SUPPORTS_THREADS	0
C_M_AXI_DC_THREAD_ID_WIDTH	1
C_M_AXI_DC_SUPPORTS_READ	1
C_M_AXI_DC_SUPPORTS_WRITE	1
C_M_AXI_DC_SUPPORTS_NARROW_BURST	0
C_M_AXI_DC_DATA_WIDTH	32
C_M_AXI_DC_ADDR_WIDTH	32
C_M_AXI_DC_PROTOCOL	AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS	0
C_M_AXI_DC_USER_VALUE	0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_DC_AWUSER_WIDTH	5
C_M_AXI_DC_ARUSER_WIDTH	5
C_M_AXI_DC_WUSER_WIDTH	1
C_M_AXI_DC_RUSER_WIDTH	1
C_M_AXI_DC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING	2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING	32
C_USE_MMU	0
C_MMU_DTLB_SIZE	4
C_MMU_ITLB_SIZE	2
C_MMU_TLB_ACCESS	3
C_MMU_ZONES	16
C_MMU_PRIVILEGED_INSTR	0
C_USE_INTERRUPT	0
C_USE_EXT_BRK	0
C_USE_EXT_NM_BRK	0
C_USE_BRANCH_TARGET_CACHE	0
C_BRANCH_TARGET_CACHE_SIZE	0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DC_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DP_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_R_REGISTER	1
C_INTERCONNECT_M_AXI_DP_B_REGISTER	1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DC_R_REGISTER	1
C_INTERCONNECT_M_AXI_DC_B_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_IC_W_REGISTER	1
C_INTERCONNECT_M_AXI_IC_R_REGISTER	1
C_INTERCONNECT_M_AXI_IC_B_REGISTER	1
Â

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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Debuggers	TOP

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-debug_module - Â Â MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

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IP Specs
Core	Version	Documentation
mdm	2.00.b	IP

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debug_module IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Debug_SYS_Rst		O	1	proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
MBDEBUG_0	INITIATOR	XIL_MBDEBUG3	microblaze_0_debug			microblaze_0
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_JTAG_CHAIN	2
C_INTERCONNECT	2
C_BASEADDR	0x74800000
C_HIGHADDR	0x7480FFFF
C_SPLB_AWIDTH	32
C_SPLB_DWIDTH	32
C_SPLB_P2P	0
C_SPLB_MID_WIDTH	3
C_SPLB_NUM_MASTERS	8
C_SPLB_NATIVE_DWIDTH	32

Â

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_SPLB_SUPPORT_BURSTS	0
C_MB_DBG_PORTS	1
C_USE_UART	1
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Interrupt Controllers	TOP

-
- - -

- - - - - - - - - -

-microblaze_0_intc - Â Â AXI Interrupt Controller
intc core attached to the AXI

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_intc	1.01.a	IP

-

-

microblaze_0_intc IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	IRQ		O	1	microblaze_0_interrupt
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	INTR		I	1	Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.
-Interrupt Priorities
Priority	SIG			MODULE
0	Push_Buttons_4Bits_IP2INTC_Irpt			Push_Buttons_4Bits
1	Ethernet_Lite_IP2INTC_Irpt			Ethernet_Lite
2	axi_timer_0_Interrupt			axi_timer_0
3	RS232_Uart_1_Interrupt			RS232_Uart_1

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x41200000
C_HIGHADDR	0x4120FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_NUM_INTR_INPUTS	2
C_KIND_OF_INTR	0xFFFFFFFF
C_KIND_OF_EDGE	0xFFFFFFFF
C_KIND_OF_LVL	0xFFFFFFFF
C_HAS_IPR	1
C_HAS_SIE	1

Â

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_HAS_CIE	1
C_HAS_IVR	1
C_IRQ_IS_LEVEL	1
C_IRQ_ACTIVE	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
Â

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Busses	TOP

-
- - - - - - - - -

- - - - - - - - - -

-axi4_0 - Â Â AXI Interconnect
AXI4 Memory-Mapped Interconnect

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

-

-

axi4_0 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	interconnect_aclk		I	1	clk_100_0000MHzPLL0
1	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DC
microblaze_0					MASTER	M_AXI_IC
MCB_DDR3					SLAVE	S0_AXI

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

Â

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	1
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-axi4lite_0 - Â Â AXI Interconnect
AXI4 Memory-Mapped Interconnect

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

-

-

axi4lite_0 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
1	INTERCONNECT_ACLK		I	1	clk_50_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DP
debug_module					SLAVE	S_AXI
RS232_Uart_1					SLAVE	S_AXI
LEDs_4Bits					SLAVE	S_AXI
Push_Buttons_4Bits					SLAVE	S_AXI
Ethernet_Lite					SLAVE	S_AXI
axi_timer_0					SLAVE	S_AXI
microblaze_0_intc					SLAVE	S_AXI

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

Â

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	0
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-microblaze_0_dlmb - Â Â Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

-

-

microblaze_0_dlmb IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	DLMB
microblaze_0_d_bram_ctrl					SLAVE	SLMB

-

-

- - - - - - - - - - - - - - - - - - - - -

Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-microblaze_0_ilmb - Â Â Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

-

-

microblaze_0_ilmb IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	ILMB
microblaze_0_i_bram_ctrl					SLAVE	SLMB

-

-

- - - - - - - - - - - - - - - - - - - - -

Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

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-

- - -

Memorys	TOP

-
- - -

- - - - - - - - - -

-microblaze_0_bram_block - Â Â Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
bram_block	1.00.a	IP

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-

microblaze_0_bram_block IP Image

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Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
PORTA	TARGET	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_i_bram_ctrl
PORTB	TARGET	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_d_bram_ctrl

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Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_MEMSIZE		2048
C_PORT_DWIDTH		32
C_PORT_AWIDTH		32
C_NUM_WE		4
C_FAMILY		virtex2

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-

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-

- - -

Memory Controllers	TOP

-
- - - - - - -

- - - - - - - - - -

-MCB_DDR3 - Â Â AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_s6_ddrx	1.02.a	IP

-

-

MCB_DDR3 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	mcbx_dram_clk		O	1	mcbx_dram_clk
1	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
2	mcbx_dram_cke		O	1	mcbx_dram_cke
3	mcbx_dram_odt		O	1	mcbx_dram_odt
4	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
5	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
6	mcbx_dram_we_n		O	1	mcbx_dram_we_n
7	mcbx_dram_udm		O	1	mcbx_dram_udm
8	mcbx_dram_ldm		O	1	mcbx_dram_ldm
9	mcbx_dram_ba		O	1	mcbx_dram_ba
10	mcbx_dram_addr		O	1	mcbx_dram_addr
11	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
12	mcbx_dram_dq		IO	1	mcbx_dram_dq
13	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
14	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
15	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
16	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
17	rzq		IO	1	rzq
18	zio		IO	1	zio
19	s0_axi_aclk		I	1	clk_100_0000MHzPLL0
20	ui_clk		I	1	clk_100_0000MHzPLL0
21	sysclk_2x		I	1	clk_600_0000MHzPLL0_nobuf
22	sysclk_2x_180		I	1	clk_600_0000MHz180PLL0_nobuf
23	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
24	PLL_LOCK		I	1	proc_sys_reset_0_Dcm_locked
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S0_AXI	SLAVE	AXI	axi4_0			microblaze_0

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_MCB_LOC	MEMC3
C_MCB_RZQ_LOC	K7
C_MCB_ZIO_LOC	R7
C_MCB_PERFORMANCE	STANDARD
C_BYPASS_CORE_UCF	0
C_S0_AXI_BASEADDR	0xC0000000
C_S0_AXI_HIGHADDR	0xC7FFFFFF
C_S1_AXI_BASEADDR	0xFFFFFFFF
C_S1_AXI_HIGHADDR	0x00000000
C_S2_AXI_BASEADDR	0xFFFFFFFF
C_S2_AXI_HIGHADDR	0x00000000
C_S3_AXI_BASEADDR	0xFFFFFFFF
C_S3_AXI_HIGHADDR	0x00000000
C_S4_AXI_BASEADDR	0xFFFFFFFF
C_S4_AXI_HIGHADDR	0x00000000
C_S5_AXI_BASEADDR	0xFFFFFFFF
C_S5_AXI_HIGHADDR	0x00000000
C_MEM_TYPE	DDR3
C_MEM_PARTNO	MT41J64M16XX-187E
C_MEM_BASEPARTNO	NOT_SET
C_NUM_DQ_PINS	16
C_MEM_ADDR_WIDTH	13
C_MEM_BANKADDR_WIDTH	3
C_MEM_NUM_COL_BITS	10
C_MEM_TRAS	-1
C_MEM_TRCD	-1
C_MEM_TREFI	-1
C_MEM_TRFC	-1
C_MEM_TRP	-1
C_MEM_TWR	-1
C_MEM_TRTP	-1
C_MEM_TWTR	-1
C_PORT_CONFIG	B32_B32_B32_B32
C_SKIP_IN_TERM_CAL	0
C_SKIP_IN_TERM_CAL_VALUE	NONE
C_MEMCLK_PERIOD	0
C_MEM_ADDR_ORDER	ROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT	512
C_MEM_CAS_LATENCY	6
C_SIMULATION	FALSE
C_MEM_DDR1_2_ODS	FULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR2_RTT	150OHMS
C_MEM_DDR2_DIFF_DQS_EN	YES
C_MEM_DDR2_3_PA_SR	FULL
C_MEM_DDR2_3_HIGH_TEMP_SR	NORMAL
C_MEM_DDR3_CAS_WR_LATENCY	5
C_MEM_DDR3_CAS_LATENCY	6
C_MEM_DDR3_ODS	DIV6
C_MEM_DDR3_RTT	DIV4
C_MEM_DDR3_AUTO_SR	ENABLED
C_MEM_MOBILE_PA_SR	FULL
C_MEM_MDDR_ODS	FULL
C_ARB_ALGORITHM	0
C_ARB_NUM_TIME_SLOTS	12
C_ARB_TIME_SLOT_0	0b000000000001010011
C_ARB_TIME_SLOT_1	0b000000001010011000
C_ARB_TIME_SLOT_2	0b000000010011000001
C_ARB_TIME_SLOT_3	0b000000011000001010
C_ARB_TIME_SLOT_4	0b000000000001010011
C_ARB_TIME_SLOT_5	0b000000001010011000
C_ARB_TIME_SLOT_6	0b000000010011000001
C_ARB_TIME_SLOT_7	0b000000011000001010
C_ARB_TIME_SLOT_8	0b000000000001010011
C_ARB_TIME_SLOT_9	0b000000001010011000
C_ARB_TIME_SLOT_10	0b000000010011000001
C_ARB_TIME_SLOT_11	0b000000011000001010
C_S0_AXI_ENABLE	1
C_S0_AXI_PROTOCOL	AXI4
C_S0_AXI_ID_WIDTH	4
C_S0_AXI_ADDR_WIDTH	32
C_S0_AXI_DATA_WIDTH	32
C_S0_AXI_SUPPORTS_READ	1
C_S0_AXI_SUPPORTS_WRITE	1
C_S0_AXI_SUPPORTS_NARROW_BURST	1
C_S0_AXI_REG_EN0	0x00000
C_S0_AXI_REG_EN1	0x01000
C_S0_AXI_STRICT_COHERENCY	1
C_S0_AXI_ENABLE_AP	0

Â

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE	4
C_S1_AXI_ENABLE	0
C_S1_AXI_PROTOCOL	AXI4
C_S1_AXI_ID_WIDTH	4
C_S1_AXI_ADDR_WIDTH	32
C_S1_AXI_DATA_WIDTH	32
C_S1_AXI_SUPPORTS_READ	1
C_S1_AXI_SUPPORTS_WRITE	1
C_S1_AXI_SUPPORTS_NARROW_BURST	1
C_S1_AXI_REG_EN0	0x00000
C_S1_AXI_REG_EN1	0x01000
C_S1_AXI_STRICT_COHERENCY	1
C_S1_AXI_ENABLE_AP	0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE	4
C_S2_AXI_ENABLE	0
C_S2_AXI_PROTOCOL	AXI4
C_S2_AXI_ID_WIDTH	4
C_S2_AXI_ADDR_WIDTH	32
C_S2_AXI_DATA_WIDTH	32
C_S2_AXI_SUPPORTS_READ	1
C_S2_AXI_SUPPORTS_WRITE	1
C_S2_AXI_SUPPORTS_NARROW_BURST	1
C_S2_AXI_REG_EN0	0x00000
C_S2_AXI_REG_EN1	0x01000
C_S2_AXI_STRICT_COHERENCY	1
C_S2_AXI_ENABLE_AP	0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE	4
C_S3_AXI_ENABLE	0
C_S3_AXI_PROTOCOL	AXI4
C_S3_AXI_ID_WIDTH	4
C_S3_AXI_ADDR_WIDTH	32
C_S3_AXI_DATA_WIDTH	32
C_S3_AXI_SUPPORTS_READ	1
C_S3_AXI_SUPPORTS_WRITE	1
C_S3_AXI_SUPPORTS_NARROW_BURST	1
C_S3_AXI_REG_EN0	0x00000
C_S3_AXI_REG_EN1	0x01000
C_S3_AXI_STRICT_COHERENCY	1
C_S3_AXI_ENABLE_AP	0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE	4
C_S4_AXI_ENABLE	0
C_S4_AXI_PROTOCOL	AXI4
C_S4_AXI_ID_WIDTH	4
C_S4_AXI_ADDR_WIDTH	32
C_S4_AXI_DATA_WIDTH	32
C_S4_AXI_SUPPORTS_READ	1
C_S4_AXI_SUPPORTS_WRITE	1
C_S4_AXI_SUPPORTS_NARROW_BURST	1
C_S4_AXI_REG_EN0	0x00000
C_S4_AXI_REG_EN1	0x01000
C_S4_AXI_STRICT_COHERENCY	1
C_S4_AXI_ENABLE_AP	0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE	4
C_S5_AXI_ENABLE	0
C_S5_AXI_PROTOCOL	AXI4
C_S5_AXI_ID_WIDTH	4
C_S5_AXI_ADDR_WIDTH	32
C_S5_AXI_DATA_WIDTH	32
C_S5_AXI_SUPPORTS_READ	1
C_S5_AXI_SUPPORTS_WRITE	1
C_S5_AXI_SUPPORTS_NARROW_BURST	1
C_S5_AXI_REG_EN0	0x00000
C_S5_AXI_REG_EN1	0x01000
C_S5_AXI_STRICT_COHERENCY	1
C_S5_AXI_ENABLE_AP	0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE	4
C_MCB_USE_EXTERNAL_BUFPLL	0
C_SYS_RST_PRESENT	0
C_INTERCONNECT_S0_AXI_MASTERS	microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
C_INTERCONNECT_S0_AXI_AW_REGISTER	1
C_INTERCONNECT_S0_AXI_AR_REGISTER	1
C_INTERCONNECT_S0_AXI_W_REGISTER	1
C_INTERCONNECT_S0_AXI_R_REGISTER	1
C_INTERCONNECT_S0_AXI_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

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- - - - - - - - - -

-microblaze_0_d_bram_ctrl - Â Â LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

-

-

microblaze_0_d_bram_ctrl IP Image

- - - - - - - - - - - - - - - - - - - - - -

Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_dlmb			microblaze_0

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

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Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

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-

- - - - - - - - - -

-microblaze_0_i_bram_ctrl - Â Â LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

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microblaze_0_i_bram_ctrl IP Image

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Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_ilmb			microblaze_0

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

Â

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Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Peripherals	TOP

-
- - - - - - - - - - -

- - - - - - - - - -

-Ethernet_Lite - Â Â AXI 10/100 Ethernet MAC Lite
'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'

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- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_ethernetlite	1.00.a	IP

-

-

Ethernet_Lite IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	PHY_MDIO		IO	1	Ethernet_Lite_MDIO
1	PHY_MDC		O	1	Ethernet_Lite_MDC
2	PHY_tx_data		O	1	Ethernet_Lite_TXD
3	PHY_tx_en		O	1	Ethernet_Lite_TX_EN
4	PHY_tx_clk		I	1	Ethernet_Lite_TX_CLK
5	PHY_col		I	1	Ethernet_Lite_COL
6	PHY_rx_data		I	1	Ethernet_Lite_RXD
7	PHY_rx_er		I	1	Ethernet_Lite_RX_ER
8	PHY_rx_clk		I	1	Ethernet_Lite_RX_CLK
9	PHY_crs		I	1	Ethernet_Lite_CRS
10	PHY_dv		I	1	Ethernet_Lite_RX_DV
11	PHY_rst_n		O	1	Ethernet_Lite_PHY_RST_N
12	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
13	IP2INTC_Irpt		O	1	Ethernet_Lite_IP2INTC_Irpt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_BASEADDR	0x40E00000
C_HIGHADDR	0x40E0FFFF
C_S_AXI_ACLK_PERIOD_PS	10000
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_ID_WIDTH	1
C_INCLUDE_MDIO	1
C_INCLUDE_GLOBAL_BUFFERS	0
C_INCLUDE_INTERNAL_LOOPBACK	0
C_DUPLEX	1

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Name	Value
C_TX_PING_PONG	1
C_RX_PING_PONG	1
C_INCLUDE_PHY_CONSTRAINTS	1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE	1
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE	1
C_S_AXI_SUPPORTS_NARROW_BURST	0
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
Â

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-LEDs_4Bits - Â Â AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

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LEDs_4Bits IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_O		O	1	LEDs_4Bits_TRI_O
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40020000
C_HIGHADDR	0x4002FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	0
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	0
C_DOUT_DEFAULT	0x00000000

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Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-Push_Buttons_4Bits - Â Â AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

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Push_Buttons_4Bits IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_I		I	1	Push_Buttons_4Bits_TRI_I
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	IP2INTC_Irpt		O	1	Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40000000
C_HIGHADDR	0x4000FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	1
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	1
C_DOUT_DEFAULT	0x00000000

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Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-RS232_Uart_1 - Â Â AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

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IP Specs
Core	Version	Documentation
axi_uartlite	1.01.a	IP

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RS232_Uart_1 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	TX		O	1	RS232_Uart_1_sout
1	RX		I	1	RS232_Uart_1_sin
2	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
3	Interrupt		O	1	RS232_Uart_1_Interrupt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

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-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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Name	Value
C_FAMILY	virtex6
C_S_AXI_ACLK_FREQ_HZ	100000000
C_BASEADDR	0x40600000
C_HIGHADDR	0x4060FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_BAUDRATE	115200
C_DATA_BITS	8

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Name	Value
C_USE_PARITY	0
C_ODD_PARITY	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

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-axi_timer_0 - Â Â AXI Timer/Counter
Timer counter with AXI interface

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IP Specs
Core	Version	Documentation
axi_timer	1.01.a	IP

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axi_timer_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Interrupt		O	1	axi_timer_0_Interrupt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

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-

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_COUNT_WIDTH	32
C_ONE_TIMER_ONLY	0
C_TRIG0_ASSERT	1
C_TRIG1_ASSERT	1
C_GEN0_ASSERT	1
C_GEN1_ASSERT	1
C_BASEADDR	0x41C00000

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Name	Value
C_HIGHADDR	0x41C0FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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IP	TOP

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-clock_generator_0 - Â Â Clock Generator
Clock generator for processor system.

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IP Specs
Core	Version	Documentation
clock_generator	4.01.a	IP

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clock_generator_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	RST		I	1	RESET
1	CLKIN		I	1	CLK
2	CLKOUT2		O	1	clk_100_0000MHzPLL0
3	CLKOUT3		O	1	clk_50_0000MHzPLL0
4	CLKOUT0		O	1	clk_600_0000MHzPLL0_nobuf
5	CLKOUT1		O	1	clk_600_0000MHz180PLL0_nobuf
6	LOCKED		O	1	proc_sys_reset_0_Dcm_locked

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-

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_DEVICE	NOT_SET
C_PACKAGE	NOT_SET
C_SPEEDGRADE	NOT_SET
C_CLKIN_FREQ	200000000
C_CLKOUT0_FREQ	600000000
C_CLKOUT0_PHASE	0
C_CLKOUT0_GROUP	PLL0
C_CLKOUT0_BUF	FALSE
C_CLKOUT0_VARIABLE_PHASE	FALSE
C_CLKOUT1_FREQ	600000000
C_CLKOUT1_PHASE	180
C_CLKOUT1_GROUP	PLL0
C_CLKOUT1_BUF	FALSE
C_CLKOUT1_VARIABLE_PHASE	FALSE
C_CLKOUT2_FREQ	100000000
C_CLKOUT2_PHASE	0
C_CLKOUT2_GROUP	PLL0
C_CLKOUT2_BUF	TRUE
C_CLKOUT2_VARIABLE_PHASE	FALSE
C_CLKOUT3_FREQ	50000000
C_CLKOUT3_PHASE	0
C_CLKOUT3_GROUP	PLL0
C_CLKOUT3_BUF	TRUE
C_CLKOUT3_VARIABLE_PHASE	FALSE
C_CLKOUT4_FREQ	0
C_CLKOUT4_PHASE	0
C_CLKOUT4_GROUP	NONE
C_CLKOUT4_BUF	TRUE
C_CLKOUT4_VARIABLE_PHASE	FALSE
C_CLKOUT5_FREQ	0
C_CLKOUT5_PHASE	0
C_CLKOUT5_GROUP	NONE
C_CLKOUT5_BUF	TRUE
C_CLKOUT5_VARIABLE_PHASE	FALSE
C_CLKOUT6_FREQ	0
C_CLKOUT6_PHASE	0
C_CLKOUT6_GROUP	NONE
C_CLKOUT6_BUF	TRUE
C_CLKOUT6_VARIABLE_PHASE	FALSE
C_CLKOUT7_FREQ	0
C_CLKOUT7_PHASE	0
C_CLKOUT7_GROUP	NONE
C_CLKOUT7_BUF	TRUE
C_CLKOUT7_VARIABLE_PHASE	FALSE
C_CLKOUT8_FREQ	0
C_CLKOUT8_PHASE	0
C_CLKOUT8_GROUP	NONE

Â

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Name	Value
C_CLKOUT8_BUF	TRUE
C_CLKOUT8_VARIABLE_PHASE	FALSE
C_CLKOUT9_FREQ	0
C_CLKOUT9_PHASE	0
C_CLKOUT9_GROUP	NONE
C_CLKOUT9_BUF	TRUE
C_CLKOUT9_VARIABLE_PHASE	FALSE
C_CLKOUT10_FREQ	0
C_CLKOUT10_PHASE	0
C_CLKOUT10_GROUP	NONE
C_CLKOUT10_BUF	TRUE
C_CLKOUT10_VARIABLE_PHASE	FALSE
C_CLKOUT11_FREQ	0
C_CLKOUT11_PHASE	0
C_CLKOUT11_GROUP	NONE
C_CLKOUT11_BUF	TRUE
C_CLKOUT11_VARIABLE_PHASE	FALSE
C_CLKOUT12_FREQ	0
C_CLKOUT12_PHASE	0
C_CLKOUT12_GROUP	NONE
C_CLKOUT12_BUF	TRUE
C_CLKOUT12_VARIABLE_PHASE	FALSE
C_CLKOUT13_FREQ	0
C_CLKOUT13_PHASE	0
C_CLKOUT13_GROUP	NONE
C_CLKOUT13_BUF	TRUE
C_CLKOUT13_VARIABLE_PHASE	FALSE
C_CLKOUT14_FREQ	0
C_CLKOUT14_PHASE	0
C_CLKOUT14_GROUP	NONE
C_CLKOUT14_BUF	TRUE
C_CLKOUT14_VARIABLE_PHASE	FALSE
C_CLKOUT15_FREQ	0
C_CLKOUT15_PHASE	0
C_CLKOUT15_GROUP	NONE
C_CLKOUT15_BUF	TRUE
C_CLKOUT15_VARIABLE_PHASE	FALSE
C_CLKFBIN_FREQ	0
C_CLKFBIN_DESKEW	NONE
C_CLKFBOUT_FREQ	0
C_CLKFBOUT_PHASE	0
C_CLKFBOUT_GROUP	NONE
C_CLKFBOUT_BUF	TRUE
C_PSDONE_GROUP	NONE
C_EXT_RESET_HIGH	1
C_CLK_PRIMITIVE_FEEDBACK_BUF	FALSE
C_CLK_GEN	UPDATE
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-proc_sys_reset_0 - Â Â Processor System Reset Module
Reset management module

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IP Specs
Core	Version	Documentation
proc_sys_reset	3.00.a	IP

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proc_sys_reset_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	Ext_Reset_In		I	1	RESET
1	MB_Reset		O	1	proc_sys_reset_0_MB_Reset
2	Slowest_sync_clk		I	1	clk_50_0000MHzPLL0
3	Interconnect_aresetn		O	1	proc_sys_reset_0_Interconnect_aresetn
4	Dcm_locked		I	1	proc_sys_reset_0_Dcm_locked
5	MB_Debug_Sys_Rst		I	1	proc_sys_reset_0_MB_Debug_Sys_Rst
6	BUS_STRUCT_RESET		O	1	proc_sys_reset_0_BUS_STRUCT_RESET

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Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_SUBFAMILY		lx
C_EXT_RST_WIDTH		4
C_AUX_RST_WIDTH		4
C_EXT_RESET_HIGH		1
C_AUX_RESET_HIGH		1
C_NUM_BUS_RST		1
C_NUM_PERP_RST		1
C_NUM_INTERCONNECT_ARESETN		1
C_NUM_PERP_ARESETN		1
C_FAMILY		virtex5

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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Timing Information	TOP

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Post Synthesis Clock Limits
- No clocks could be identified in the design. Run platgen to generate synthesis information. -

-

- diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html deleted file mode 100644 index 01df645af..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html +++ /dev/null @@ -1,5407 +0,0 @@ - - - - -XPS Project Report - - - - - - - -

TABLE OF CONTENTS

-
Overview
Block Diagram
External Ports
Processor
Â Â Â microblaze_0
Debuggers
Â Â Â debug_module
Interrupt Controllers
Â Â Â microblaze_0_intc
Busses
Â Â Â axi4_0
Â Â Â axi4lite_0
Â Â Â microblaze_0_dlmb
Â Â Â microblaze_0_ilmb
Memory
Â Â Â microblaze_0_bram_block
Memory Controllers
Â Â Â MCB_DDR3
Â Â Â microblaze_0_d_bram_ctrl
Â Â Â microblaze_0_i_bram_ctrl
Peripherals
Â Â Â Ethernet_Lite
Â Â Â LEDs_4Bits
Â Â Â Push_Buttons_4Bits
Â Â Â RS232_Uart_1
Â Â Â axi_timer_0
IP
Â Â Â clock_generator_0
Â Â Â proc_sys_reset_0
Timing Information -

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Overview	TOC

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Resources Used
1Â Â	MicroBlaze
2Â Â	AXI Interconnect
2Â Â	Local Memory Bus (LMB) 1.0
1Â Â	Block RAM (BRAM) Block
2Â Â	LMB BRAM Controller
1Â Â	AXI S6 Memory Controller(DDR/DDR2/DDR3)
1Â Â	Processor System Reset Module
1Â Â	Clock Generator
1Â Â	MicroBlaze Debug Module (MDM)
1Â Â	AXI UART (Lite)
2Â Â	AXI General Purpose IO
1Â Â	AXI 10/100 Ethernet MAC Lite
1Â Â	AXI Timer/Counter
1Â Â	AXI Interrupt Controller

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Specifics
Generated	Wed Jul 27 11:49:42 2011
EDK Version	13.1
Device Family	spartan6
Device	xc6slx45tfgg484-3

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-
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Block Diagram	TOC

-

BlockDiagram

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External Ports	TOC

-
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- These are the external ports defined in the MHS file. -

-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLKÂ Â indicates Clock ports, (SIGIS = CLK)Â
INTRÂ Â indicates Interrupt ports,(SIGIS = INTR)Â
RESETÂ Â indicates Reset ports, (SIGIS = RST)Â
BUF or REGÂ Â Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)Â -

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#	NAME		DIR	[LSB:MSB]	SIG		ATTRIBUTES
-SHARED -	RESET		I	1	RESET		Â RESETÂ
-Ethernet_Lite -	Ethernet_Lite_COL		I	1	Ethernet_Lite_COL
-Ethernet_Lite -	Ethernet_Lite_CRS		I	1	Ethernet_Lite_CRS
-Ethernet_Lite -	Ethernet_Lite_RXD		I	0:3	Ethernet_Lite_RXD
-Ethernet_Lite -	Ethernet_Lite_RX_CLK		I	1	Ethernet_Lite_RX_CLK
-Ethernet_Lite -	Ethernet_Lite_RX_DV		I	1	Ethernet_Lite_RX_DV
-Ethernet_Lite -	Ethernet_Lite_RX_ER		I	1	Ethernet_Lite_RX_ER
-Ethernet_Lite -	Ethernet_Lite_TX_CLK		I	1	Ethernet_Lite_TX_CLK
-Ethernet_Lite -	Ethernet_Lite_MDIO		IO	1	Ethernet_Lite_MDIO
-Ethernet_Lite -	Ethernet_Lite_MDC		O	1	Ethernet_Lite_MDC
-Ethernet_Lite -	Ethernet_Lite_PHY_RST_N		O	1	Ethernet_Lite_PHY_RST_N
-Ethernet_Lite -	Ethernet_Lite_TXD		O	0:3	Ethernet_Lite_TXD
-Ethernet_Lite -	Ethernet_Lite_TX_EN		O	1	Ethernet_Lite_TX_EN
-LEDs_4Bits -	LEDs_4Bits_TRI_O		O	3:0	LEDs_4Bits_TRI_O
-MCB_DDR3 -	mcbx_dram_dq		IO	0:15	mcbx_dram_dq
-MCB_DDR3 -	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
-MCB_DDR3 -	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
-MCB_DDR3 -	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
-MCB_DDR3 -	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
-MCB_DDR3 -	rzq		IO	1	rzq
-MCB_DDR3 -	zio		IO	1	zio
-MCB_DDR3 -	mcbx_dram_addr		O	0:12	mcbx_dram_addr
-MCB_DDR3 -	mcbx_dram_ba		O	0:2	mcbx_dram_ba
-MCB_DDR3 -	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
-MCB_DDR3 -	mcbx_dram_cke		O	1	mcbx_dram_cke
-MCB_DDR3 -	mcbx_dram_clk		O	1	mcbx_dram_clk
-MCB_DDR3 -	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
-MCB_DDR3 -	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
-MCB_DDR3 -	mcbx_dram_ldm		O	1	mcbx_dram_ldm
-MCB_DDR3 -	mcbx_dram_odt		O	1	mcbx_dram_odt
-MCB_DDR3 -	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
-MCB_DDR3 -	mcbx_dram_udm		O	1	mcbx_dram_udm
-MCB_DDR3 -	mcbx_dram_we_n		O	1	mcbx_dram_we_n
-Push_Buttons_4Bits -	Push_Buttons_4Bits_TRI_I		I	0:3	Push_Buttons_4Bits_TRI_I
-RS232_Uart_1 -	RS232_Uart_1_sin		I	1	RS232_Uart_1_sin
-RS232_Uart_1 -	RS232_Uart_1_sout		O	1	RS232_Uart_1_sout
-clock_generator_0 -	CLK_N		I	1	CLK		Â CLKÂ
-clock_generator_0 -	CLK_P		I	1	CLK		Â CLKÂ

-

-

- - -

Processors	TOC

-
- - -

- - - - - - - - - -

-microblaze_0 - Â Â MicroBlaze
The MicroBlaze 32 bit soft processor

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
microblaze	8.10.a	IP

-

-

microblaze_0 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	MB_RESET		I	1	proc_sys_reset_0_MB_Reset
1	CLK		I	1	clk_100_0000MHzPLL0
2	INTERRUPT		I	1	microblaze_0_interrupt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
M_AXI_DP	MASTER	AXI	axi4lite_0			7 Peripherals.
M_AXI_DC	MASTER	AXI	axi4_0			MCB_DDR3
M_AXI_IC	MASTER	AXI	axi4_0			MCB_DDR3
DLMB	MASTER	LMB	microblaze_0_dlmb			microblaze_0_d_bram_ctrl
ILMB	MASTER	LMB	microblaze_0_ilmb			microblaze_0_i_bram_ctrl
DEBUG	TARGET	XIL_MBDEBUG3	microblaze_0_debug			debug_module

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_SCO	0
C_FREQ	0
C_DATA_SIZE	32
C_DYNAMIC_BUS_SIZING	1
C_FAMILY	virtex5
C_INSTANCE	microblaze
C_FAULT_TOLERANT	0
C_ECC_USE_CE_EXCEPTION	0
C_ENDIANNESS	0
C_AREA_OPTIMIZED	0
C_OPTIMIZATION	0
C_INTERCONNECT	2
C_STREAM_INTERCONNECT	0
C_DPLB_DWIDTH	32
C_DPLB_NATIVE_DWIDTH	32
C_DPLB_BURST_EN	0
C_DPLB_P2P	0
C_IPLB_DWIDTH	32
C_IPLB_NATIVE_DWIDTH	32
C_IPLB_BURST_EN	0
C_IPLB_P2P	0
C_M_AXI_DP_SUPPORTS_THREADS	0
C_M_AXI_DP_THREAD_ID_WIDTH	1
C_M_AXI_DP_SUPPORTS_READ	1
C_M_AXI_DP_SUPPORTS_WRITE	1
C_M_AXI_DP_SUPPORTS_NARROW_BURST	0
C_M_AXI_DP_DATA_WIDTH	32
C_M_AXI_DP_ADDR_WIDTH	32
C_M_AXI_DP_PROTOCOL	AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS	0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING	1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING	1
C_M_AXI_IP_SUPPORTS_THREADS	0
C_M_AXI_IP_THREAD_ID_WIDTH	1
C_M_AXI_IP_SUPPORTS_READ	1
C_M_AXI_IP_SUPPORTS_WRITE	0
C_M_AXI_IP_SUPPORTS_NARROW_BURST	0
C_M_AXI_IP_DATA_WIDTH	32
C_M_AXI_IP_ADDR_WIDTH	32
C_M_AXI_IP_PROTOCOL	AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING	1
C_D_AXI	0
C_D_PLB	0
C_D_LMB	1
C_I_AXI	0
C_I_PLB	0
C_I_LMB	1
C_USE_MSR_INSTR	1
C_USE_PCMP_INSTR	1
C_USE_BARREL	1
C_USE_DIV	1
C_USE_HW_MUL	1
C_USE_FPU	1
C_UNALIGNED_EXCEPTIONS	1
C_ILL_OPCODE_EXCEPTION	1
C_M_AXI_I_BUS_EXCEPTION	1
C_M_AXI_D_BUS_EXCEPTION	1
C_IPLB_BUS_EXCEPTION	0
C_DPLB_BUS_EXCEPTION	0
C_DIV_ZERO_EXCEPTION	1
C_FPU_EXCEPTION	1
C_FSL_EXCEPTION	0
C_USE_STACK_PROTECTION	0
C_PVR	0
C_PVR_USER1	0x00
C_PVR_USER2	0x00000000
C_DEBUG_ENABLED	1
C_NUMBER_OF_PC_BRK	7
C_NUMBER_OF_RD_ADDR_BRK	2
C_NUMBER_OF_WR_ADDR_BRK	2
C_INTERRUPT_IS_EDGE	0
C_EDGE_IS_POSITIVE	1
C_RESET_MSR	0x00000000
C_OPCODE_0x0_ILLEGAL	1
C_FSL_LINKS	0
C_FSL_DATA_SIZE	32
C_USE_EXTENDED_FSL_INSTR	0
C_M0_AXIS_PROTOCOL	GENERIC
C_S0_AXIS_PROTOCOL	GENERIC
C_M1_AXIS_PROTOCOL	GENERIC
C_S1_AXIS_PROTOCOL	GENERIC
C_M2_AXIS_PROTOCOL	GENERIC
C_S2_AXIS_PROTOCOL	GENERIC
C_M3_AXIS_PROTOCOL	GENERIC
C_S3_AXIS_PROTOCOL	GENERIC
C_M4_AXIS_PROTOCOL	GENERIC
C_S4_AXIS_PROTOCOL	GENERIC
C_M5_AXIS_PROTOCOL	GENERIC
C_S5_AXIS_PROTOCOL	GENERIC
C_M6_AXIS_PROTOCOL	GENERIC
C_S6_AXIS_PROTOCOL	GENERIC
C_M7_AXIS_PROTOCOL	GENERIC
C_S7_AXIS_PROTOCOL	GENERIC
C_M8_AXIS_PROTOCOL	GENERIC
C_S8_AXIS_PROTOCOL	GENERIC
C_M9_AXIS_PROTOCOL	GENERIC
C_S9_AXIS_PROTOCOL	GENERIC
C_M10_AXIS_PROTOCOL	GENERIC
C_S10_AXIS_PROTOCOL	GENERIC
C_M11_AXIS_PROTOCOL	GENERIC
C_S11_AXIS_PROTOCOL	GENERIC
C_M12_AXIS_PROTOCOL	GENERIC
C_S12_AXIS_PROTOCOL	GENERIC
C_M13_AXIS_PROTOCOL	GENERIC
C_S13_AXIS_PROTOCOL	GENERIC
C_M14_AXIS_PROTOCOL	GENERIC
C_S14_AXIS_PROTOCOL	GENERIC
C_M15_AXIS_PROTOCOL	GENERIC
C_S15_AXIS_PROTOCOL	GENERIC
C_M0_AXIS_DATA_WIDTH	32
C_S0_AXIS_DATA_WIDTH	32
C_M1_AXIS_DATA_WIDTH	32
C_S1_AXIS_DATA_WIDTH	32
C_M2_AXIS_DATA_WIDTH	32
C_S2_AXIS_DATA_WIDTH	32

Â

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_M3_AXIS_DATA_WIDTH	32
C_S3_AXIS_DATA_WIDTH	32
C_M4_AXIS_DATA_WIDTH	32
C_S4_AXIS_DATA_WIDTH	32
C_M5_AXIS_DATA_WIDTH	32
C_S5_AXIS_DATA_WIDTH	32
C_M6_AXIS_DATA_WIDTH	32
C_S6_AXIS_DATA_WIDTH	32
C_M7_AXIS_DATA_WIDTH	32
C_S7_AXIS_DATA_WIDTH	32
C_M8_AXIS_DATA_WIDTH	32
C_S8_AXIS_DATA_WIDTH	32
C_M9_AXIS_DATA_WIDTH	32
C_S9_AXIS_DATA_WIDTH	32
C_M10_AXIS_DATA_WIDTH	32
C_S10_AXIS_DATA_WIDTH	32
C_M11_AXIS_DATA_WIDTH	32
C_S11_AXIS_DATA_WIDTH	32
C_M12_AXIS_DATA_WIDTH	32
C_S12_AXIS_DATA_WIDTH	32
C_M13_AXIS_DATA_WIDTH	32
C_S13_AXIS_DATA_WIDTH	32
C_M14_AXIS_DATA_WIDTH	32
C_S14_AXIS_DATA_WIDTH	32
C_M15_AXIS_DATA_WIDTH	32
C_S15_AXIS_DATA_WIDTH	32
C_ICACHE_BASEADDR	0xC0000000
C_ICACHE_HIGHADDR	0xC7FFFFFF
C_USE_ICACHE	1
C_ALLOW_ICACHE_WR	1
C_ADDR_TAG_BITS	17
C_CACHE_BYTE_SIZE	16384
C_ICACHE_USE_FSL	1
C_ICACHE_LINE_LEN	4
C_ICACHE_ALWAYS_USED	1
C_ICACHE_INTERFACE	0
C_ICACHE_VICTIMS	0
C_ICACHE_STREAMS	0
C_ICACHE_FORCE_TAG_LUTRAM	0
C_ICACHE_DATA_WIDTH	0
C_M_AXI_IC_SUPPORTS_THREADS	0
C_M_AXI_IC_THREAD_ID_WIDTH	1
C_M_AXI_IC_SUPPORTS_READ	1
C_M_AXI_IC_SUPPORTS_WRITE	0
C_M_AXI_IC_SUPPORTS_NARROW_BURST	0
C_M_AXI_IC_DATA_WIDTH	32
C_M_AXI_IC_ADDR_WIDTH	32
C_M_AXI_IC_PROTOCOL	AXI4
C_M_AXI_IC_USER_VALUE	0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_IC_AWUSER_WIDTH	5
C_M_AXI_IC_ARUSER_WIDTH	5
C_M_AXI_IC_WUSER_WIDTH	1
C_M_AXI_IC_RUSER_WIDTH	1
C_M_AXI_IC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING	2
C_DCACHE_BASEADDR	0xC0000000
C_DCACHE_HIGHADDR	0xC7FFFFFF
C_USE_DCACHE	1
C_ALLOW_DCACHE_WR	1
C_DCACHE_ADDR_TAG	17
C_DCACHE_BYTE_SIZE	16384
C_DCACHE_USE_FSL	1
C_DCACHE_LINE_LEN	4
C_DCACHE_ALWAYS_USED	1
C_DCACHE_INTERFACE	0
C_DCACHE_USE_WRITEBACK	0
C_DCACHE_VICTIMS	0
C_DCACHE_FORCE_TAG_LUTRAM	0
C_DCACHE_DATA_WIDTH	0
C_M_AXI_DC_SUPPORTS_THREADS	0
C_M_AXI_DC_THREAD_ID_WIDTH	1
C_M_AXI_DC_SUPPORTS_READ	1
C_M_AXI_DC_SUPPORTS_WRITE	1
C_M_AXI_DC_SUPPORTS_NARROW_BURST	0
C_M_AXI_DC_DATA_WIDTH	32
C_M_AXI_DC_ADDR_WIDTH	32
C_M_AXI_DC_PROTOCOL	AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS	0
C_M_AXI_DC_USER_VALUE	0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_DC_AWUSER_WIDTH	5
C_M_AXI_DC_ARUSER_WIDTH	5
C_M_AXI_DC_WUSER_WIDTH	1
C_M_AXI_DC_RUSER_WIDTH	1
C_M_AXI_DC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING	2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING	32
C_USE_MMU	0
C_MMU_DTLB_SIZE	4
C_MMU_ITLB_SIZE	2
C_MMU_TLB_ACCESS	3
C_MMU_ZONES	16
C_MMU_PRIVILEGED_INSTR	0
C_USE_INTERRUPT	0
C_USE_EXT_BRK	0
C_USE_EXT_NM_BRK	0
C_USE_BRANCH_TARGET_CACHE	0
C_BRANCH_TARGET_CACHE_SIZE	0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DC_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DP_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_R_REGISTER	1
C_INTERCONNECT_M_AXI_DP_B_REGISTER	1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DC_R_REGISTER	1
C_INTERCONNECT_M_AXI_DC_B_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_IC_W_REGISTER	1
C_INTERCONNECT_M_AXI_IC_R_REGISTER	1
C_INTERCONNECT_M_AXI_IC_B_REGISTER	1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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Debuggers	TOC

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- - - - - - - - - -

-debug_module - Â Â MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

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IP Specs
Core	Version	Documentation
mdm	2.00.b	IP

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debug_module IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Debug_SYS_Rst		O	1	proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
MBDEBUG_0	INITIATOR	XIL_MBDEBUG3	microblaze_0_debug			microblaze_0
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_FAMILY	virtex6
C_JTAG_CHAIN	2
C_INTERCONNECT	2
C_BASEADDR	0x74800000
C_HIGHADDR	0x7480FFFF
C_SPLB_AWIDTH	32
C_SPLB_DWIDTH	32
C_SPLB_P2P	0
C_SPLB_MID_WIDTH	3
C_SPLB_NUM_MASTERS	8
C_SPLB_NATIVE_DWIDTH	32

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Name	Value
C_SPLB_SUPPORT_BURSTS	0
C_MB_DBG_PORTS	1
C_USE_UART	1
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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Interrupt Controllers	TOC

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-microblaze_0_intc - Â Â AXI Interrupt Controller
intc core attached to the AXI

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IP Specs
Core	Version	Documentation
axi_intc	1.01.a	IP

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microblaze_0_intc IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	IRQ		O	1	microblaze_0_interrupt
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	INTR		I	1	Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.
-Interrupt Priorities
Priority	SIG			MODULE
0	Push_Buttons_4Bits_IP2INTC_Irpt			Push_Buttons_4Bits
1	Ethernet_Lite_IP2INTC_Irpt			Ethernet_Lite
2	axi_timer_0_Interrupt			axi_timer_0
3	RS232_Uart_1_Interrupt			RS232_Uart_1

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x41200000
C_HIGHADDR	0x4120FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_NUM_INTR_INPUTS	2
C_KIND_OF_INTR	0xFFFFFFFF
C_KIND_OF_EDGE	0xFFFFFFFF
C_KIND_OF_LVL	0xFFFFFFFF
C_HAS_IPR	1
C_HAS_SIE	1

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Name	Value
C_HAS_CIE	1
C_HAS_IVR	1
C_IRQ_IS_LEVEL	1
C_IRQ_ACTIVE	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
Â

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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Busses	TOC

-
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- - - - - - - - - -

-axi4_0 - Â Â AXI Interconnect
AXI4 Memory-Mapped Interconnect

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IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

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axi4_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	interconnect_aclk		I	1	clk_100_0000MHzPLL0
1	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DC
microblaze_0					MASTER	M_AXI_IC
MCB_DDR3					SLAVE	S0_AXI

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

Â

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	1
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-axi4lite_0 - Â Â AXI Interconnect
AXI4 Memory-Mapped Interconnect

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

-

-

axi4lite_0 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
1	INTERCONNECT_ACLK		I	1	clk_50_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DP
debug_module					SLAVE	S_AXI
RS232_Uart_1					SLAVE	S_AXI
LEDs_4Bits					SLAVE	S_AXI
Push_Buttons_4Bits					SLAVE	S_AXI
Ethernet_Lite					SLAVE	S_AXI
axi_timer_0					SLAVE	S_AXI
microblaze_0_intc					SLAVE	S_AXI

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

Â

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	0
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-microblaze_0_dlmb - Â Â Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

-

-

microblaze_0_dlmb IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	DLMB
microblaze_0_d_bram_ctrl					SLAVE	SLMB

-

-

- - - - - - - - - - - - - - - - - - - - -

Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-microblaze_0_ilmb - Â Â Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

-

-

microblaze_0_ilmb IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	ILMB
microblaze_0_i_bram_ctrl					SLAVE	SLMB

-

-

- - - - - - - - - - - - - - - - - - - - -

Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Memorys	TOC

-
- - -

- - - - - - - - - -

-microblaze_0_bram_block - Â Â Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
bram_block	1.00.a	IP

-

-

microblaze_0_bram_block IP Image

- - - - - - - - - - - - - - - - - - - - - -

Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
PORTA	TARGET	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_i_bram_ctrl
PORTB	TARGET	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_d_bram_ctrl

-

-

- - - - - - - - - - - - - - - - - - - - - - - -

Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_MEMSIZE		2048
C_PORT_DWIDTH		32
C_PORT_AWIDTH		32
C_NUM_WE		4
C_FAMILY		virtex2

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Memory Controllers	TOC

-
- - - - - - -

- - - - - - - - - -

-MCB_DDR3 - Â Â AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_s6_ddrx	1.02.a	IP

-

-

MCB_DDR3 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	mcbx_dram_clk		O	1	mcbx_dram_clk
1	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
2	mcbx_dram_cke		O	1	mcbx_dram_cke
3	mcbx_dram_odt		O	1	mcbx_dram_odt
4	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
5	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
6	mcbx_dram_we_n		O	1	mcbx_dram_we_n
7	mcbx_dram_udm		O	1	mcbx_dram_udm
8	mcbx_dram_ldm		O	1	mcbx_dram_ldm
9	mcbx_dram_ba		O	1	mcbx_dram_ba
10	mcbx_dram_addr		O	1	mcbx_dram_addr
11	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
12	mcbx_dram_dq		IO	1	mcbx_dram_dq
13	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
14	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
15	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
16	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
17	rzq		IO	1	rzq
18	zio		IO	1	zio
19	s0_axi_aclk		I	1	clk_100_0000MHzPLL0
20	ui_clk		I	1	clk_100_0000MHzPLL0
21	sysclk_2x		I	1	clk_600_0000MHzPLL0_nobuf
22	sysclk_2x_180		I	1	clk_600_0000MHz180PLL0_nobuf
23	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
24	PLL_LOCK		I	1	proc_sys_reset_0_Dcm_locked
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S0_AXI	SLAVE	AXI	axi4_0			microblaze_0

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_MCB_LOC	MEMC3
C_MCB_RZQ_LOC	K7
C_MCB_ZIO_LOC	R7
C_MCB_PERFORMANCE	STANDARD
C_BYPASS_CORE_UCF	0
C_S0_AXI_BASEADDR	0xC0000000
C_S0_AXI_HIGHADDR	0xC7FFFFFF
C_S1_AXI_BASEADDR	0xFFFFFFFF
C_S1_AXI_HIGHADDR	0x00000000
C_S2_AXI_BASEADDR	0xFFFFFFFF
C_S2_AXI_HIGHADDR	0x00000000
C_S3_AXI_BASEADDR	0xFFFFFFFF
C_S3_AXI_HIGHADDR	0x00000000
C_S4_AXI_BASEADDR	0xFFFFFFFF
C_S4_AXI_HIGHADDR	0x00000000
C_S5_AXI_BASEADDR	0xFFFFFFFF
C_S5_AXI_HIGHADDR	0x00000000
C_MEM_TYPE	DDR3
C_MEM_PARTNO	MT41J64M16XX-187E
C_MEM_BASEPARTNO	NOT_SET
C_NUM_DQ_PINS	16
C_MEM_ADDR_WIDTH	13
C_MEM_BANKADDR_WIDTH	3
C_MEM_NUM_COL_BITS	10
C_MEM_TRAS	-1
C_MEM_TRCD	-1
C_MEM_TREFI	-1
C_MEM_TRFC	-1
C_MEM_TRP	-1
C_MEM_TWR	-1
C_MEM_TRTP	-1
C_MEM_TWTR	-1
C_PORT_CONFIG	B32_B32_B32_B32
C_SKIP_IN_TERM_CAL	0
C_SKIP_IN_TERM_CAL_VALUE	NONE
C_MEMCLK_PERIOD	0
C_MEM_ADDR_ORDER	ROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT	512
C_MEM_CAS_LATENCY	6
C_SIMULATION	FALSE
C_MEM_DDR1_2_ODS	FULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR2_RTT	150OHMS
C_MEM_DDR2_DIFF_DQS_EN	YES
C_MEM_DDR2_3_PA_SR	FULL
C_MEM_DDR2_3_HIGH_TEMP_SR	NORMAL
C_MEM_DDR3_CAS_WR_LATENCY	5
C_MEM_DDR3_CAS_LATENCY	6
C_MEM_DDR3_ODS	DIV6
C_MEM_DDR3_RTT	DIV4
C_MEM_DDR3_AUTO_SR	ENABLED
C_MEM_MOBILE_PA_SR	FULL
C_MEM_MDDR_ODS	FULL
C_ARB_ALGORITHM	0
C_ARB_NUM_TIME_SLOTS	12
C_ARB_TIME_SLOT_0	0b000000000001010011
C_ARB_TIME_SLOT_1	0b000000001010011000
C_ARB_TIME_SLOT_2	0b000000010011000001
C_ARB_TIME_SLOT_3	0b000000011000001010
C_ARB_TIME_SLOT_4	0b000000000001010011
C_ARB_TIME_SLOT_5	0b000000001010011000
C_ARB_TIME_SLOT_6	0b000000010011000001
C_ARB_TIME_SLOT_7	0b000000011000001010
C_ARB_TIME_SLOT_8	0b000000000001010011
C_ARB_TIME_SLOT_9	0b000000001010011000
C_ARB_TIME_SLOT_10	0b000000010011000001
C_ARB_TIME_SLOT_11	0b000000011000001010
C_S0_AXI_ENABLE	1
C_S0_AXI_PROTOCOL	AXI4
C_S0_AXI_ID_WIDTH	4
C_S0_AXI_ADDR_WIDTH	32
C_S0_AXI_DATA_WIDTH	32
C_S0_AXI_SUPPORTS_READ	1
C_S0_AXI_SUPPORTS_WRITE	1
C_S0_AXI_SUPPORTS_NARROW_BURST	1
C_S0_AXI_REG_EN0	0x00000
C_S0_AXI_REG_EN1	0x01000
C_S0_AXI_STRICT_COHERENCY	1
C_S0_AXI_ENABLE_AP	0

Â

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Name	Value
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE	4
C_S1_AXI_ENABLE	0
C_S1_AXI_PROTOCOL	AXI4
C_S1_AXI_ID_WIDTH	4
C_S1_AXI_ADDR_WIDTH	32
C_S1_AXI_DATA_WIDTH	32
C_S1_AXI_SUPPORTS_READ	1
C_S1_AXI_SUPPORTS_WRITE	1
C_S1_AXI_SUPPORTS_NARROW_BURST	1
C_S1_AXI_REG_EN0	0x00000
C_S1_AXI_REG_EN1	0x01000
C_S1_AXI_STRICT_COHERENCY	1
C_S1_AXI_ENABLE_AP	0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE	4
C_S2_AXI_ENABLE	0
C_S2_AXI_PROTOCOL	AXI4
C_S2_AXI_ID_WIDTH	4
C_S2_AXI_ADDR_WIDTH	32
C_S2_AXI_DATA_WIDTH	32
C_S2_AXI_SUPPORTS_READ	1
C_S2_AXI_SUPPORTS_WRITE	1
C_S2_AXI_SUPPORTS_NARROW_BURST	1
C_S2_AXI_REG_EN0	0x00000
C_S2_AXI_REG_EN1	0x01000
C_S2_AXI_STRICT_COHERENCY	1
C_S2_AXI_ENABLE_AP	0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE	4
C_S3_AXI_ENABLE	0
C_S3_AXI_PROTOCOL	AXI4
C_S3_AXI_ID_WIDTH	4
C_S3_AXI_ADDR_WIDTH	32
C_S3_AXI_DATA_WIDTH	32
C_S3_AXI_SUPPORTS_READ	1
C_S3_AXI_SUPPORTS_WRITE	1
C_S3_AXI_SUPPORTS_NARROW_BURST	1
C_S3_AXI_REG_EN0	0x00000
C_S3_AXI_REG_EN1	0x01000
C_S3_AXI_STRICT_COHERENCY	1
C_S3_AXI_ENABLE_AP	0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE	4
C_S4_AXI_ENABLE	0
C_S4_AXI_PROTOCOL	AXI4
C_S4_AXI_ID_WIDTH	4
C_S4_AXI_ADDR_WIDTH	32
C_S4_AXI_DATA_WIDTH	32
C_S4_AXI_SUPPORTS_READ	1
C_S4_AXI_SUPPORTS_WRITE	1
C_S4_AXI_SUPPORTS_NARROW_BURST	1
C_S4_AXI_REG_EN0	0x00000
C_S4_AXI_REG_EN1	0x01000
C_S4_AXI_STRICT_COHERENCY	1
C_S4_AXI_ENABLE_AP	0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE	4
C_S5_AXI_ENABLE	0
C_S5_AXI_PROTOCOL	AXI4
C_S5_AXI_ID_WIDTH	4
C_S5_AXI_ADDR_WIDTH	32
C_S5_AXI_DATA_WIDTH	32
C_S5_AXI_SUPPORTS_READ	1
C_S5_AXI_SUPPORTS_WRITE	1
C_S5_AXI_SUPPORTS_NARROW_BURST	1
C_S5_AXI_REG_EN0	0x00000
C_S5_AXI_REG_EN1	0x01000
C_S5_AXI_STRICT_COHERENCY	1
C_S5_AXI_ENABLE_AP	0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE	4
C_MCB_USE_EXTERNAL_BUFPLL	0
C_SYS_RST_PRESENT	0
C_INTERCONNECT_S0_AXI_MASTERS	microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
C_INTERCONNECT_S0_AXI_AW_REGISTER	1
C_INTERCONNECT_S0_AXI_AR_REGISTER	1
C_INTERCONNECT_S0_AXI_W_REGISTER	1
C_INTERCONNECT_S0_AXI_R_REGISTER	1
C_INTERCONNECT_S0_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-microblaze_0_d_bram_ctrl - Â Â LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

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IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

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microblaze_0_d_bram_ctrl IP Image

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Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_dlmb			microblaze_0

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

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Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

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- - - - - - - - - -

-microblaze_0_i_bram_ctrl - Â Â LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

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IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

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microblaze_0_i_bram_ctrl IP Image

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Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_ilmb			microblaze_0

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

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Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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Peripherals	TOC

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-Ethernet_Lite - Â Â AXI 10/100 Ethernet MAC Lite
'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'

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IP Specs
Core	Version	Documentation
axi_ethernetlite	1.00.a	IP

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Ethernet_Lite IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	PHY_MDIO		IO	1	Ethernet_Lite_MDIO
1	PHY_MDC		O	1	Ethernet_Lite_MDC
2	PHY_tx_data		O	1	Ethernet_Lite_TXD
3	PHY_tx_en		O	1	Ethernet_Lite_TX_EN
4	PHY_tx_clk		I	1	Ethernet_Lite_TX_CLK
5	PHY_col		I	1	Ethernet_Lite_COL
6	PHY_rx_data		I	1	Ethernet_Lite_RXD
7	PHY_rx_er		I	1	Ethernet_Lite_RX_ER
8	PHY_rx_clk		I	1	Ethernet_Lite_RX_CLK
9	PHY_crs		I	1	Ethernet_Lite_CRS
10	PHY_dv		I	1	Ethernet_Lite_RX_DV
11	PHY_rst_n		O	1	Ethernet_Lite_PHY_RST_N
12	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
13	IP2INTC_Irpt		O	1	Ethernet_Lite_IP2INTC_Irpt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_BASEADDR	0x40E00000
C_HIGHADDR	0x40E0FFFF
C_S_AXI_ACLK_PERIOD_PS	10000
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_ID_WIDTH	1
C_INCLUDE_MDIO	1
C_INCLUDE_GLOBAL_BUFFERS	0
C_INCLUDE_INTERNAL_LOOPBACK	0
C_DUPLEX	1

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Name	Value
C_TX_PING_PONG	1
C_RX_PING_PONG	1
C_INCLUDE_PHY_CONSTRAINTS	1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE	1
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE	1
C_S_AXI_SUPPORTS_NARROW_BURST	0
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
Â

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-LEDs_4Bits - Â Â AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

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LEDs_4Bits IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_O		O	1	LEDs_4Bits_TRI_O
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

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-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40020000
C_HIGHADDR	0x4002FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	0
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	0
C_DOUT_DEFAULT	0x00000000

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Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
Â

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-

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-Push_Buttons_4Bits - Â Â AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

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Push_Buttons_4Bits IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_I		I	1	Push_Buttons_4Bits_TRI_I
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	IP2INTC_Irpt		O	1	Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

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-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40000000
C_HIGHADDR	0x4000FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	1
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	1
C_DOUT_DEFAULT	0x00000000

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Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
Â

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

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-

- - - - - - - - - -

-RS232_Uart_1 - Â Â AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

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IP Specs
Core	Version	Documentation
axi_uartlite	1.01.a	IP

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RS232_Uart_1 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	TX		O	1	RS232_Uart_1_sout
1	RX		I	1	RS232_Uart_1_sin
2	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
3	Interrupt		O	1	RS232_Uart_1_Interrupt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_S_AXI_ACLK_FREQ_HZ	100000000
C_BASEADDR	0x40600000
C_HIGHADDR	0x4060FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_BAUDRATE	115200
C_DATA_BITS	8

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Name	Value
C_USE_PARITY	0
C_ODD_PARITY	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-axi_timer_0 - Â Â AXI Timer/Counter
Timer counter with AXI interface

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IP Specs
Core	Version	Documentation
axi_timer	1.01.a	IP

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axi_timer_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Interrupt		O	1	axi_timer_0_Interrupt
Bus Interfaces
Â NAMEÂ	Â TYPEÂ	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_COUNT_WIDTH	32
C_ONE_TIMER_ONLY	0
C_TRIG0_ASSERT	1
C_TRIG1_ASSERT	1
C_GEN0_ASSERT	1
C_GEN1_ASSERT	1
C_BASEADDR	0x41C00000

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Name	Value
C_HIGHADDR	0x41C0FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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IP	TOC

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-clock_generator_0 - Â Â Clock Generator
Clock generator for processor system.

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IP Specs
Core	Version	Documentation
clock_generator	4.01.a	IP

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clock_generator_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	RST		I	1	RESET
1	CLKIN		I	1	CLK
2	CLKOUT2		O	1	clk_100_0000MHzPLL0
3	CLKOUT3		O	1	clk_50_0000MHzPLL0
4	CLKOUT0		O	1	clk_600_0000MHzPLL0_nobuf
5	CLKOUT1		O	1	clk_600_0000MHz180PLL0_nobuf
6	LOCKED		O	1	proc_sys_reset_0_Dcm_locked

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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Name	Value
C_FAMILY	virtex6
C_DEVICE	NOT_SET
C_PACKAGE	NOT_SET
C_SPEEDGRADE	NOT_SET
C_CLKIN_FREQ	200000000
C_CLKOUT0_FREQ	600000000
C_CLKOUT0_PHASE	0
C_CLKOUT0_GROUP	PLL0
C_CLKOUT0_BUF	FALSE
C_CLKOUT0_VARIABLE_PHASE	FALSE
C_CLKOUT1_FREQ	600000000
C_CLKOUT1_PHASE	180
C_CLKOUT1_GROUP	PLL0
C_CLKOUT1_BUF	FALSE
C_CLKOUT1_VARIABLE_PHASE	FALSE
C_CLKOUT2_FREQ	100000000
C_CLKOUT2_PHASE	0
C_CLKOUT2_GROUP	PLL0
C_CLKOUT2_BUF	TRUE
C_CLKOUT2_VARIABLE_PHASE	FALSE
C_CLKOUT3_FREQ	50000000
C_CLKOUT3_PHASE	0
C_CLKOUT3_GROUP	PLL0
C_CLKOUT3_BUF	TRUE
C_CLKOUT3_VARIABLE_PHASE	FALSE
C_CLKOUT4_FREQ	0
C_CLKOUT4_PHASE	0
C_CLKOUT4_GROUP	NONE
C_CLKOUT4_BUF	TRUE
C_CLKOUT4_VARIABLE_PHASE	FALSE
C_CLKOUT5_FREQ	0
C_CLKOUT5_PHASE	0
C_CLKOUT5_GROUP	NONE
C_CLKOUT5_BUF	TRUE
C_CLKOUT5_VARIABLE_PHASE	FALSE
C_CLKOUT6_FREQ	0
C_CLKOUT6_PHASE	0
C_CLKOUT6_GROUP	NONE
C_CLKOUT6_BUF	TRUE
C_CLKOUT6_VARIABLE_PHASE	FALSE
C_CLKOUT7_FREQ	0
C_CLKOUT7_PHASE	0
C_CLKOUT7_GROUP	NONE
C_CLKOUT7_BUF	TRUE
C_CLKOUT7_VARIABLE_PHASE	FALSE
C_CLKOUT8_FREQ	0
C_CLKOUT8_PHASE	0
C_CLKOUT8_GROUP	NONE

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Name	Value
C_CLKOUT8_BUF	TRUE
C_CLKOUT8_VARIABLE_PHASE	FALSE
C_CLKOUT9_FREQ	0
C_CLKOUT9_PHASE	0
C_CLKOUT9_GROUP	NONE
C_CLKOUT9_BUF	TRUE
C_CLKOUT9_VARIABLE_PHASE	FALSE
C_CLKOUT10_FREQ	0
C_CLKOUT10_PHASE	0
C_CLKOUT10_GROUP	NONE
C_CLKOUT10_BUF	TRUE
C_CLKOUT10_VARIABLE_PHASE	FALSE
C_CLKOUT11_FREQ	0
C_CLKOUT11_PHASE	0
C_CLKOUT11_GROUP	NONE
C_CLKOUT11_BUF	TRUE
C_CLKOUT11_VARIABLE_PHASE	FALSE
C_CLKOUT12_FREQ	0
C_CLKOUT12_PHASE	0
C_CLKOUT12_GROUP	NONE
C_CLKOUT12_BUF	TRUE
C_CLKOUT12_VARIABLE_PHASE	FALSE
C_CLKOUT13_FREQ	0
C_CLKOUT13_PHASE	0
C_CLKOUT13_GROUP	NONE
C_CLKOUT13_BUF	TRUE
C_CLKOUT13_VARIABLE_PHASE	FALSE
C_CLKOUT14_FREQ	0
C_CLKOUT14_PHASE	0
C_CLKOUT14_GROUP	NONE
C_CLKOUT14_BUF	TRUE
C_CLKOUT14_VARIABLE_PHASE	FALSE
C_CLKOUT15_FREQ	0
C_CLKOUT15_PHASE	0
C_CLKOUT15_GROUP	NONE
C_CLKOUT15_BUF	TRUE
C_CLKOUT15_VARIABLE_PHASE	FALSE
C_CLKFBIN_FREQ	0
C_CLKFBIN_DESKEW	NONE
C_CLKFBOUT_FREQ	0
C_CLKFBOUT_PHASE	0
C_CLKFBOUT_GROUP	NONE
C_CLKFBOUT_BUF	TRUE
C_PSDONE_GROUP	NONE
C_EXT_RESET_HIGH	1
C_CLK_PRIMITIVE_FEEDBACK_BUF	FALSE
C_CLK_GEN	UPDATE
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-proc_sys_reset_0 - Â Â Processor System Reset Module
Reset management module

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IP Specs
Core	Version	Documentation
proc_sys_reset	3.00.a	IP

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proc_sys_reset_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	Ext_Reset_In		I	1	RESET
1	MB_Reset		O	1	proc_sys_reset_0_MB_Reset
2	Slowest_sync_clk		I	1	clk_50_0000MHzPLL0
3	Interconnect_aresetn		O	1	proc_sys_reset_0_Interconnect_aresetn
4	Dcm_locked		I	1	proc_sys_reset_0_Dcm_locked
5	MB_Debug_Sys_Rst		I	1	proc_sys_reset_0_MB_Debug_Sys_Rst
6	BUS_STRUCT_RESET		O	1	proc_sys_reset_0_BUS_STRUCT_RESET

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Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_SUBFAMILY		lx
C_EXT_RST_WIDTH		4
C_AUX_RST_WIDTH		4
C_EXT_RESET_HIGH		1
C_AUX_RESET_HIGH		1
C_NUM_BUS_RST		1
C_NUM_PERP_RST		1
C_NUM_INTERCONNECT_ARESETN		1
C_NUM_PERP_ARESETN		1
C_FAMILY		virtex5

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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Timing Information	TOC

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Post Synthesis Clock Limits
- No clocks could be identified in the design. Run platgen to generate synthesis information. -

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- - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html deleted file mode 100644 index 25287d5b0..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html +++ /dev/null @@ -1,73 +0,0 @@ - - - - -Table of Contents - - - - -

-Overview
Block Diagram
External Ports

-

Â Processor -

-Â Â Â microblaze_0

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Â Debuggers -

-Â Â Â debug_module

-

Â Interrupt Controllers -

-Â Â Â microblaze_0_intc

-

Â Busses -

-Â Â Â axi4_0
Â Â Â axi4lite_0
Â Â Â microblaze_0_dlmb
Â Â Â microblaze_0_ilmb

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Â Memory -

-Â Â Â microblaze_0_bram_block

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Â Memory Controllers -

-Â Â Â MCB_DDR3
Â Â Â microblaze_0_d_bram_ctrl
Â Â Â microblaze_0_i_bram_ctrl

-

Â Peripherals -

-Â Â Â Ethernet_Lite
Â Â Â LEDs_4Bits
Â Â Â Push_Buttons_4Bits
Â Â Â RS232_Uart_1
Â Â Â axi_timer_0

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Â IP -

-Â Â Â clock_generator_0
Â Â Â proc_sys_reset_0
Timing Information
-

- -- 2.39.5