From 85484f240b5e5ca1cf7ea419901dbad7aa3cfd52 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Sat, 27 Aug 2011 14:23:59 +0000 Subject: [PATCH] Remove some large files from the repository that don't need to be there. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1567 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../SDK/SDK_Export/hw/system.html | 12 - .../SDK/SDK_Export/hw/system_main.html | 5397 ---------------- .../SDK/SDK_Export/hw/system_mainNF.html | 5407 ----------------- .../SDK/SDK_Export/hw/system_toc.html | 73 - 4 files changed, 10889 deletions(-) delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html deleted file mode 100644 index 1dda8a75f..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html +++ /dev/null @@ -1,12 +0,0 @@ - - - - -XPS Project Report - -XPS Project Report - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html deleted file mode 100644 index 0864e1f1c..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html +++ /dev/null @@ -1,5397 +0,0 @@ - - - - -XPS Project Report - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Printable Version
-
Overview
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Resources Used
1  MicroBlaze
2  AXI Interconnect
2  Local Memory Bus (LMB) 1.0
1  Block RAM (BRAM) Block
2  LMB BRAM Controller
1  AXI S6 Memory Controller(DDR/DDR2/DDR3)
1  Processor System Reset Module
1  Clock Generator
1  MicroBlaze Debug Module (MDM)
1  AXI UART (Lite)
2  AXI General Purpose IO
1  AXI 10/100 Ethernet MAC Lite
1  AXI Timer/Counter
1  AXI Interrupt Controller
- - - - - - - - - - - - - - -
Specifics
GeneratedWed Jul 27 11:49:42 2011
EDK Version13.1
Device Familyspartan6
Devicexc6slx45tfgg484-3
-
-
- - -
Block DiagramTOP
-
BlockDiagram -
- - - -
External PortsTOP
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- - - - - - -
- These are the external ports defined in the MHS file. -
-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
-SHARED -RESETI1RESET RESET 
-Ethernet_Lite -Ethernet_Lite_COLI1Ethernet_Lite_COL
-Ethernet_Lite -Ethernet_Lite_CRSI1Ethernet_Lite_CRS
-Ethernet_Lite -Ethernet_Lite_RXDI0:3Ethernet_Lite_RXD
-Ethernet_Lite -Ethernet_Lite_RX_CLKI1Ethernet_Lite_RX_CLK
-Ethernet_Lite -Ethernet_Lite_RX_DVI1Ethernet_Lite_RX_DV
-Ethernet_Lite -Ethernet_Lite_RX_ERI1Ethernet_Lite_RX_ER
-Ethernet_Lite -Ethernet_Lite_TX_CLKI1Ethernet_Lite_TX_CLK
-Ethernet_Lite -Ethernet_Lite_MDIOIO1Ethernet_Lite_MDIO
-Ethernet_Lite -Ethernet_Lite_MDCO1Ethernet_Lite_MDC
-Ethernet_Lite -Ethernet_Lite_PHY_RST_NO1Ethernet_Lite_PHY_RST_N
-Ethernet_Lite -Ethernet_Lite_TXDO0:3Ethernet_Lite_TXD
-Ethernet_Lite -Ethernet_Lite_TX_ENO1Ethernet_Lite_TX_EN
-LEDs_4Bits -LEDs_4Bits_TRI_OO3:0LEDs_4Bits_TRI_O
-MCB_DDR3 -mcbx_dram_dqIO0:15mcbx_dram_dq
-MCB_DDR3 -mcbx_dram_dqsIO1mcbx_dram_dqs
-MCB_DDR3 -mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
-MCB_DDR3 -mcbx_dram_udqsIO1mcbx_dram_udqs
-MCB_DDR3 -mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
-MCB_DDR3 -rzqIO1rzq
-MCB_DDR3 -zioIO1zio
-MCB_DDR3 -mcbx_dram_addrO0:12mcbx_dram_addr
-MCB_DDR3 -mcbx_dram_baO0:2mcbx_dram_ba
-MCB_DDR3 -mcbx_dram_cas_nO1mcbx_dram_cas_n
-MCB_DDR3 -mcbx_dram_ckeO1mcbx_dram_cke
-MCB_DDR3 -mcbx_dram_clkO1mcbx_dram_clk
-MCB_DDR3 -mcbx_dram_clk_nO1mcbx_dram_clk_n
-MCB_DDR3 -mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
-MCB_DDR3 -mcbx_dram_ldmO1mcbx_dram_ldm
-MCB_DDR3 -mcbx_dram_odtO1mcbx_dram_odt
-MCB_DDR3 -mcbx_dram_ras_nO1mcbx_dram_ras_n
-MCB_DDR3 -mcbx_dram_udmO1mcbx_dram_udm
-MCB_DDR3 -mcbx_dram_we_nO1mcbx_dram_we_n
-Push_Buttons_4Bits -Push_Buttons_4Bits_TRI_II0:3Push_Buttons_4Bits_TRI_I
-RS232_Uart_1 -RS232_Uart_1_sinI1RS232_Uart_1_sin
-RS232_Uart_1 -RS232_Uart_1_soutO1RS232_Uart_1_sout
-clock_generator_0 -CLK_NI1CLK CLK 
-clock_generator_0 -CLK_PI1CLK CLK 
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ProcessorsTOP
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-microblaze_0 -   MicroBlaze
The MicroBlaze 32 bit soft processor

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IP Specs
CoreVersionDocumentation
microblaze8.10.aIP
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microblaze_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0MB_RESETI1proc_sys_reset_0_MB_Reset
1CLKI1clk_100_0000MHzPLL0
2INTERRUPTI1microblaze_0_interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXI_DPMASTERAXIaxi4lite_07 Peripherals.
M_AXI_DCMASTERAXIaxi4_0MCB_DDR3
M_AXI_ICMASTERAXIaxi4_0MCB_DDR3
DLMBMASTERLMBmicroblaze_0_dlmbmicroblaze_0_d_bram_ctrl
ILMBMASTERLMBmicroblaze_0_ilmbmicroblaze_0_i_bram_ctrl
DEBUGTARGETXIL_MBDEBUG3microblaze_0_debugdebug_module
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SCO0
C_FREQ0
C_DATA_SIZE32
C_DYNAMIC_BUS_SIZING1
C_FAMILYvirtex5
C_INSTANCEmicroblaze
C_FAULT_TOLERANT0
C_ECC_USE_CE_EXCEPTION0
C_ENDIANNESS0
C_AREA_OPTIMIZED0
C_OPTIMIZATION0
C_INTERCONNECT2
C_STREAM_INTERCONNECT0
C_DPLB_DWIDTH32
C_DPLB_NATIVE_DWIDTH32
C_DPLB_BURST_EN0
C_DPLB_P2P0
C_IPLB_DWIDTH32
C_IPLB_NATIVE_DWIDTH32
C_IPLB_BURST_EN0
C_IPLB_P2P0
C_M_AXI_DP_SUPPORTS_THREADS0
C_M_AXI_DP_THREAD_ID_WIDTH1
C_M_AXI_DP_SUPPORTS_READ1
C_M_AXI_DP_SUPPORTS_WRITE1
C_M_AXI_DP_SUPPORTS_NARROW_BURST0
C_M_AXI_DP_DATA_WIDTH32
C_M_AXI_DP_ADDR_WIDTH32
C_M_AXI_DP_PROTOCOLAXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING1
C_M_AXI_IP_SUPPORTS_THREADS0
C_M_AXI_IP_THREAD_ID_WIDTH1
C_M_AXI_IP_SUPPORTS_READ1
C_M_AXI_IP_SUPPORTS_WRITE0
C_M_AXI_IP_SUPPORTS_NARROW_BURST0
C_M_AXI_IP_DATA_WIDTH32
C_M_AXI_IP_ADDR_WIDTH32
C_M_AXI_IP_PROTOCOLAXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING1
C_D_AXI0
C_D_PLB0
C_D_LMB1
C_I_AXI0
C_I_PLB0
C_I_LMB1
C_USE_MSR_INSTR1
C_USE_PCMP_INSTR1
C_USE_BARREL1
C_USE_DIV1
C_USE_HW_MUL1
C_USE_FPU1
C_UNALIGNED_EXCEPTIONS1
C_ILL_OPCODE_EXCEPTION1
C_M_AXI_I_BUS_EXCEPTION1
C_M_AXI_D_BUS_EXCEPTION1
C_IPLB_BUS_EXCEPTION0
C_DPLB_BUS_EXCEPTION0
C_DIV_ZERO_EXCEPTION1
C_FPU_EXCEPTION1
C_FSL_EXCEPTION0
C_USE_STACK_PROTECTION0
C_PVR0
C_PVR_USER10x00
C_PVR_USER20x00000000
C_DEBUG_ENABLED1
C_NUMBER_OF_PC_BRK7
C_NUMBER_OF_RD_ADDR_BRK2
C_NUMBER_OF_WR_ADDR_BRK2
C_INTERRUPT_IS_EDGE0
C_EDGE_IS_POSITIVE1
C_RESET_MSR0x00000000
C_OPCODE_0x0_ILLEGAL1
C_FSL_LINKS0
C_FSL_DATA_SIZE32
C_USE_EXTENDED_FSL_INSTR0
C_M0_AXIS_PROTOCOLGENERIC
C_S0_AXIS_PROTOCOLGENERIC
C_M1_AXIS_PROTOCOLGENERIC
C_S1_AXIS_PROTOCOLGENERIC
C_M2_AXIS_PROTOCOLGENERIC
C_S2_AXIS_PROTOCOLGENERIC
C_M3_AXIS_PROTOCOLGENERIC
C_S3_AXIS_PROTOCOLGENERIC
C_M4_AXIS_PROTOCOLGENERIC
C_S4_AXIS_PROTOCOLGENERIC
C_M5_AXIS_PROTOCOLGENERIC
C_S5_AXIS_PROTOCOLGENERIC
C_M6_AXIS_PROTOCOLGENERIC
C_S6_AXIS_PROTOCOLGENERIC
C_M7_AXIS_PROTOCOLGENERIC
C_S7_AXIS_PROTOCOLGENERIC
C_M8_AXIS_PROTOCOLGENERIC
C_S8_AXIS_PROTOCOLGENERIC
C_M9_AXIS_PROTOCOLGENERIC
C_S9_AXIS_PROTOCOLGENERIC
C_M10_AXIS_PROTOCOLGENERIC
C_S10_AXIS_PROTOCOLGENERIC
C_M11_AXIS_PROTOCOLGENERIC
C_S11_AXIS_PROTOCOLGENERIC
C_M12_AXIS_PROTOCOLGENERIC
C_S12_AXIS_PROTOCOLGENERIC
C_M13_AXIS_PROTOCOLGENERIC
C_S13_AXIS_PROTOCOLGENERIC
C_M14_AXIS_PROTOCOLGENERIC
C_S14_AXIS_PROTOCOLGENERIC
C_M15_AXIS_PROTOCOLGENERIC
C_S15_AXIS_PROTOCOLGENERIC
C_M0_AXIS_DATA_WIDTH32
C_S0_AXIS_DATA_WIDTH32
C_M1_AXIS_DATA_WIDTH32
C_S1_AXIS_DATA_WIDTH32
C_M2_AXIS_DATA_WIDTH32
C_S2_AXIS_DATA_WIDTH32
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_M3_AXIS_DATA_WIDTH32
C_S3_AXIS_DATA_WIDTH32
C_M4_AXIS_DATA_WIDTH32
C_S4_AXIS_DATA_WIDTH32
C_M5_AXIS_DATA_WIDTH32
C_S5_AXIS_DATA_WIDTH32
C_M6_AXIS_DATA_WIDTH32
C_S6_AXIS_DATA_WIDTH32
C_M7_AXIS_DATA_WIDTH32
C_S7_AXIS_DATA_WIDTH32
C_M8_AXIS_DATA_WIDTH32
C_S8_AXIS_DATA_WIDTH32
C_M9_AXIS_DATA_WIDTH32
C_S9_AXIS_DATA_WIDTH32
C_M10_AXIS_DATA_WIDTH32
C_S10_AXIS_DATA_WIDTH32
C_M11_AXIS_DATA_WIDTH32
C_S11_AXIS_DATA_WIDTH32
C_M12_AXIS_DATA_WIDTH32
C_S12_AXIS_DATA_WIDTH32
C_M13_AXIS_DATA_WIDTH32
C_S13_AXIS_DATA_WIDTH32
C_M14_AXIS_DATA_WIDTH32
C_S14_AXIS_DATA_WIDTH32
C_M15_AXIS_DATA_WIDTH32
C_S15_AXIS_DATA_WIDTH32
C_ICACHE_BASEADDR0xC0000000
C_ICACHE_HIGHADDR0xC7FFFFFF
C_USE_ICACHE1
C_ALLOW_ICACHE_WR1
C_ADDR_TAG_BITS17
C_CACHE_BYTE_SIZE16384
C_ICACHE_USE_FSL1
C_ICACHE_LINE_LEN4
C_ICACHE_ALWAYS_USED1
C_ICACHE_INTERFACE0
C_ICACHE_VICTIMS0
C_ICACHE_STREAMS0
C_ICACHE_FORCE_TAG_LUTRAM0
C_ICACHE_DATA_WIDTH0
C_M_AXI_IC_SUPPORTS_THREADS0
C_M_AXI_IC_THREAD_ID_WIDTH1
C_M_AXI_IC_SUPPORTS_READ1
C_M_AXI_IC_SUPPORTS_WRITE0
C_M_AXI_IC_SUPPORTS_NARROW_BURST0
C_M_AXI_IC_DATA_WIDTH32
C_M_AXI_IC_ADDR_WIDTH32
C_M_AXI_IC_PROTOCOLAXI4
C_M_AXI_IC_USER_VALUE0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS1
C_M_AXI_IC_AWUSER_WIDTH5
C_M_AXI_IC_ARUSER_WIDTH5
C_M_AXI_IC_WUSER_WIDTH1
C_M_AXI_IC_RUSER_WIDTH1
C_M_AXI_IC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING2
C_DCACHE_BASEADDR0xC0000000
C_DCACHE_HIGHADDR0xC7FFFFFF
C_USE_DCACHE1
C_ALLOW_DCACHE_WR1
C_DCACHE_ADDR_TAG17
C_DCACHE_BYTE_SIZE16384
C_DCACHE_USE_FSL1
C_DCACHE_LINE_LEN4
C_DCACHE_ALWAYS_USED1
C_DCACHE_INTERFACE0
C_DCACHE_USE_WRITEBACK0
C_DCACHE_VICTIMS0
C_DCACHE_FORCE_TAG_LUTRAM0
C_DCACHE_DATA_WIDTH0
C_M_AXI_DC_SUPPORTS_THREADS0
C_M_AXI_DC_THREAD_ID_WIDTH1
C_M_AXI_DC_SUPPORTS_READ1
C_M_AXI_DC_SUPPORTS_WRITE1
C_M_AXI_DC_SUPPORTS_NARROW_BURST0
C_M_AXI_DC_DATA_WIDTH32
C_M_AXI_DC_ADDR_WIDTH32
C_M_AXI_DC_PROTOCOLAXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS0
C_M_AXI_DC_USER_VALUE0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS1
C_M_AXI_DC_AWUSER_WIDTH5
C_M_AXI_DC_ARUSER_WIDTH5
C_M_AXI_DC_WUSER_WIDTH1
C_M_AXI_DC_RUSER_WIDTH1
C_M_AXI_DC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING32
C_USE_MMU0
C_MMU_DTLB_SIZE4
C_MMU_ITLB_SIZE2
C_MMU_TLB_ACCESS3
C_MMU_ZONES16
C_MMU_PRIVILEGED_INSTR0
C_USE_INTERRUPT0
C_USE_EXT_BRK0
C_USE_EXT_NM_BRK0
C_USE_BRANCH_TARGET_CACHE0
C_BRANCH_TARGET_CACHE_SIZE0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER1
C_INTERCONNECT_M_AXI_DC_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER1
C_INTERCONNECT_M_AXI_DP_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_R_REGISTER1
C_INTERCONNECT_M_AXI_DP_B_REGISTER1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER1
C_INTERCONNECT_M_AXI_DC_R_REGISTER1
C_INTERCONNECT_M_AXI_DC_B_REGISTER1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER1
C_INTERCONNECT_M_AXI_IC_W_REGISTER1
C_INTERCONNECT_M_AXI_IC_R_REGISTER1
C_INTERCONNECT_M_AXI_IC_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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DebuggersTOP
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- - -
- - - - - - - - - -
-debug_module -   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

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IP Specs
CoreVersionDocumentation
mdm2.00.bIP
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-
debug_module IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1Debug_SYS_RstO1proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
MBDEBUG_0INITIATORXIL_MBDEBUG3microblaze_0_debugmicroblaze_0
S_AXISLAVEAXIaxi4lite_07 Peripherals.
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-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_JTAG_CHAIN2
C_INTERCONNECT2
C_BASEADDR0x74800000
C_HIGHADDR0x7480FFFF
C_SPLB_AWIDTH32
C_SPLB_DWIDTH32
C_SPLB_P2P0
C_SPLB_MID_WIDTH3
C_SPLB_NUM_MASTERS8
C_SPLB_NATIVE_DWIDTH32
 
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NameValue
C_SPLB_SUPPORT_BURSTS0
C_MB_DBG_PORTS1
C_USE_UART1
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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Interrupt ControllersTOP
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-microblaze_0_intc -   AXI Interrupt Controller
intc core attached to the AXI

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- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_intc1.01.aIP
-

-
microblaze_0_intc IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0IRQO1microblaze_0_interrupt
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2INTRI1Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-Interrupt Priorities
PrioritySIGMODULE
0Push_Buttons_4Bits_IP2INTC_IrptPush_Buttons_4Bits
1Ethernet_Lite_IP2INTC_IrptEthernet_Lite
2axi_timer_0_Interruptaxi_timer_0
3RS232_Uart_1_InterruptRS232_Uart_1
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_BASEADDR0x41200000
C_HIGHADDR0x4120FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_NUM_INTR_INPUTS2
C_KIND_OF_INTR0xFFFFFFFF
C_KIND_OF_EDGE0xFFFFFFFF
C_KIND_OF_LVL0xFFFFFFFF
C_HAS_IPR1
C_HAS_SIE1
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_HAS_CIE1
C_HAS_IVR1
C_IRQ_IS_LEVEL1
C_IRQ_ACTIVE1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
BussesTOP
-
- - - - - - - - -
- - - - - - - - - -
-axi4_0 -   AXI Interconnect
AXI4 Memory-Mapped Interconnect

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
-

-
axi4_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0interconnect_aclkI1clk_100_0000MHzPLL0
1INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DC
microblaze_0MASTERM_AXI_IC
MCB_DDR3SLAVES0_AXI
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE1
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-axi4lite_0 -   AXI Interconnect
AXI4 Memory-Mapped Interconnect

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
-

-
axi4lite_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
1INTERCONNECT_ACLKI1clk_50_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DP
debug_moduleSLAVES_AXI
RS232_Uart_1SLAVES_AXI
LEDs_4BitsSLAVES_AXI
Push_Buttons_4BitsSLAVES_AXI
Ethernet_LiteSLAVES_AXI
axi_timer_0SLAVES_AXI
microblaze_0_intcSLAVES_AXI
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE0
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_dlmb -   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
-

-
microblaze_0_dlmb IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERDLMB
microblaze_0_d_bram_ctrlSLAVESLMB
-

-
- - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_ilmb -   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
-

-
microblaze_0_ilmb IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERILMB
microblaze_0_i_bram_ctrlSLAVESLMB
-

-
- - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
MemorysTOP
-
- - -
- - - - - - - - - -
-microblaze_0_bram_block -   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
bram_block1.00.aIP
-

-
microblaze_0_bram_block IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
PORTATARGETXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_i_bram_ctrl
PORTBTARGETXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_d_bram_ctrl
-

-
- - - - - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_MEMSIZE2048
C_PORT_DWIDTH32
C_PORT_AWIDTH32
C_NUM_WE4
C_FAMILYvirtex2
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
Memory ControllersTOP
-
- - - - - - -
- - - - - - - - - -
-MCB_DDR3 -   AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_s6_ddrx1.02.aIP
-

-
MCB_DDR3 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0mcbx_dram_clkO1mcbx_dram_clk
1mcbx_dram_clk_nO1mcbx_dram_clk_n
2mcbx_dram_ckeO1mcbx_dram_cke
3mcbx_dram_odtO1mcbx_dram_odt
4mcbx_dram_ras_nO1mcbx_dram_ras_n
5mcbx_dram_cas_nO1mcbx_dram_cas_n
6mcbx_dram_we_nO1mcbx_dram_we_n
7mcbx_dram_udmO1mcbx_dram_udm
8mcbx_dram_ldmO1mcbx_dram_ldm
9mcbx_dram_baO1mcbx_dram_ba
10mcbx_dram_addrO1mcbx_dram_addr
11mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
12mcbx_dram_dqIO1mcbx_dram_dq
13mcbx_dram_dqsIO1mcbx_dram_dqs
14mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
15mcbx_dram_udqsIO1mcbx_dram_udqs
16mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
17rzqIO1rzq
18zioIO1zio
19s0_axi_aclkI1clk_100_0000MHzPLL0
20ui_clkI1clk_100_0000MHzPLL0
21sysclk_2xI1clk_600_0000MHzPLL0_nobuf
22sysclk_2x_180I1clk_600_0000MHz180PLL0_nobuf
23SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
24PLL_LOCKI1proc_sys_reset_0_Dcm_locked
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S0_AXISLAVEAXIaxi4_0microblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_MCB_LOCMEMC3
C_MCB_RZQ_LOCK7
C_MCB_ZIO_LOCR7
C_MCB_PERFORMANCESTANDARD
C_BYPASS_CORE_UCF0
C_S0_AXI_BASEADDR0xC0000000
C_S0_AXI_HIGHADDR0xC7FFFFFF
C_S1_AXI_BASEADDR0xFFFFFFFF
C_S1_AXI_HIGHADDR0x00000000
C_S2_AXI_BASEADDR0xFFFFFFFF
C_S2_AXI_HIGHADDR0x00000000
C_S3_AXI_BASEADDR0xFFFFFFFF
C_S3_AXI_HIGHADDR0x00000000
C_S4_AXI_BASEADDR0xFFFFFFFF
C_S4_AXI_HIGHADDR0x00000000
C_S5_AXI_BASEADDR0xFFFFFFFF
C_S5_AXI_HIGHADDR0x00000000
C_MEM_TYPEDDR3
C_MEM_PARTNOMT41J64M16XX-187E
C_MEM_BASEPARTNONOT_SET
C_NUM_DQ_PINS16
C_MEM_ADDR_WIDTH13
C_MEM_BANKADDR_WIDTH3
C_MEM_NUM_COL_BITS10
C_MEM_TRAS-1
C_MEM_TRCD-1
C_MEM_TREFI-1
C_MEM_TRFC-1
C_MEM_TRP-1
C_MEM_TWR-1
C_MEM_TRTP-1
C_MEM_TWTR-1
C_PORT_CONFIGB32_B32_B32_B32
C_SKIP_IN_TERM_CAL0
C_SKIP_IN_TERM_CAL_VALUENONE
C_MEMCLK_PERIOD0
C_MEM_ADDR_ORDERROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT512
C_MEM_CAS_LATENCY6
C_SIMULATIONFALSE
C_MEM_DDR1_2_ODSFULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR2_RTT150OHMS
C_MEM_DDR2_DIFF_DQS_ENYES
C_MEM_DDR2_3_PA_SRFULL
C_MEM_DDR2_3_HIGH_TEMP_SRNORMAL
C_MEM_DDR3_CAS_WR_LATENCY5
C_MEM_DDR3_CAS_LATENCY6
C_MEM_DDR3_ODSDIV6
C_MEM_DDR3_RTTDIV4
C_MEM_DDR3_AUTO_SRENABLED
C_MEM_MOBILE_PA_SRFULL
C_MEM_MDDR_ODSFULL
C_ARB_ALGORITHM0
C_ARB_NUM_TIME_SLOTS12
C_ARB_TIME_SLOT_00b000000000001010011
C_ARB_TIME_SLOT_10b000000001010011000
C_ARB_TIME_SLOT_20b000000010011000001
C_ARB_TIME_SLOT_30b000000011000001010
C_ARB_TIME_SLOT_40b000000000001010011
C_ARB_TIME_SLOT_50b000000001010011000
C_ARB_TIME_SLOT_60b000000010011000001
C_ARB_TIME_SLOT_70b000000011000001010
C_ARB_TIME_SLOT_80b000000000001010011
C_ARB_TIME_SLOT_90b000000001010011000
C_ARB_TIME_SLOT_100b000000010011000001
C_ARB_TIME_SLOT_110b000000011000001010
C_S0_AXI_ENABLE1
C_S0_AXI_PROTOCOLAXI4
C_S0_AXI_ID_WIDTH4
C_S0_AXI_ADDR_WIDTH32
C_S0_AXI_DATA_WIDTH32
C_S0_AXI_SUPPORTS_READ1
C_S0_AXI_SUPPORTS_WRITE1
C_S0_AXI_SUPPORTS_NARROW_BURST1
C_S0_AXI_REG_EN00x00000
C_S0_AXI_REG_EN10x01000
C_S0_AXI_STRICT_COHERENCY1
C_S0_AXI_ENABLE_AP0
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE4
C_S1_AXI_ENABLE0
C_S1_AXI_PROTOCOLAXI4
C_S1_AXI_ID_WIDTH4
C_S1_AXI_ADDR_WIDTH32
C_S1_AXI_DATA_WIDTH32
C_S1_AXI_SUPPORTS_READ1
C_S1_AXI_SUPPORTS_WRITE1
C_S1_AXI_SUPPORTS_NARROW_BURST1
C_S1_AXI_REG_EN00x00000
C_S1_AXI_REG_EN10x01000
C_S1_AXI_STRICT_COHERENCY1
C_S1_AXI_ENABLE_AP0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE4
C_S2_AXI_ENABLE0
C_S2_AXI_PROTOCOLAXI4
C_S2_AXI_ID_WIDTH4
C_S2_AXI_ADDR_WIDTH32
C_S2_AXI_DATA_WIDTH32
C_S2_AXI_SUPPORTS_READ1
C_S2_AXI_SUPPORTS_WRITE1
C_S2_AXI_SUPPORTS_NARROW_BURST1
C_S2_AXI_REG_EN00x00000
C_S2_AXI_REG_EN10x01000
C_S2_AXI_STRICT_COHERENCY1
C_S2_AXI_ENABLE_AP0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE4
C_S3_AXI_ENABLE0
C_S3_AXI_PROTOCOLAXI4
C_S3_AXI_ID_WIDTH4
C_S3_AXI_ADDR_WIDTH32
C_S3_AXI_DATA_WIDTH32
C_S3_AXI_SUPPORTS_READ1
C_S3_AXI_SUPPORTS_WRITE1
C_S3_AXI_SUPPORTS_NARROW_BURST1
C_S3_AXI_REG_EN00x00000
C_S3_AXI_REG_EN10x01000
C_S3_AXI_STRICT_COHERENCY1
C_S3_AXI_ENABLE_AP0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE4
C_S4_AXI_ENABLE0
C_S4_AXI_PROTOCOLAXI4
C_S4_AXI_ID_WIDTH4
C_S4_AXI_ADDR_WIDTH32
C_S4_AXI_DATA_WIDTH32
C_S4_AXI_SUPPORTS_READ1
C_S4_AXI_SUPPORTS_WRITE1
C_S4_AXI_SUPPORTS_NARROW_BURST1
C_S4_AXI_REG_EN00x00000
C_S4_AXI_REG_EN10x01000
C_S4_AXI_STRICT_COHERENCY1
C_S4_AXI_ENABLE_AP0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE4
C_S5_AXI_ENABLE0
C_S5_AXI_PROTOCOLAXI4
C_S5_AXI_ID_WIDTH4
C_S5_AXI_ADDR_WIDTH32
C_S5_AXI_DATA_WIDTH32
C_S5_AXI_SUPPORTS_READ1
C_S5_AXI_SUPPORTS_WRITE1
C_S5_AXI_SUPPORTS_NARROW_BURST1
C_S5_AXI_REG_EN00x00000
C_S5_AXI_REG_EN10x01000
C_S5_AXI_STRICT_COHERENCY1
C_S5_AXI_ENABLE_AP0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE4
C_MCB_USE_EXTERNAL_BUFPLL0
C_SYS_RST_PRESENT0
C_INTERCONNECT_S0_AXI_MASTERSmicroblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
C_INTERCONNECT_S0_AXI_AW_REGISTER1
C_INTERCONNECT_S0_AXI_AR_REGISTER1
C_INTERCONNECT_S0_AXI_W_REGISTER1
C_INTERCONNECT_S0_AXI_R_REGISTER1
C_INTERCONNECT_S0_AXI_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_d_bram_ctrl -   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
-

-
microblaze_0_d_bram_ctrl IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_dlmbmicroblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_i_bram_ctrl -   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
-

-
microblaze_0_i_bram_ctrl IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_ilmbmicroblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
PeripheralsTOP
-
- - - - - - - - - - -
- - - - - - - - - -
-Ethernet_Lite -   AXI 10/100 Ethernet MAC Lite
'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_ethernetlite1.00.aIP
-

-
Ethernet_Lite IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0PHY_MDIOIO1Ethernet_Lite_MDIO
1PHY_MDCO1Ethernet_Lite_MDC
2PHY_tx_dataO1Ethernet_Lite_TXD
3PHY_tx_enO1Ethernet_Lite_TX_EN
4PHY_tx_clkI1Ethernet_Lite_TX_CLK
5PHY_colI1Ethernet_Lite_COL
6PHY_rx_dataI1Ethernet_Lite_RXD
7PHY_rx_erI1Ethernet_Lite_RX_ER
8PHY_rx_clkI1Ethernet_Lite_RX_CLK
9PHY_crsI1Ethernet_Lite_CRS
10PHY_dvI1Ethernet_Lite_RX_DV
11PHY_rst_nO1Ethernet_Lite_PHY_RST_N
12S_AXI_ACLKI1clk_50_0000MHzPLL0
13IP2INTC_IrptO1Ethernet_Lite_IP2INTC_Irpt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_FAMILYvirtex6
C_BASEADDR0x40E00000
C_HIGHADDR0x40E0FFFF
C_S_AXI_ACLK_PERIOD_PS10000
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_ID_WIDTH1
C_INCLUDE_MDIO1
C_INCLUDE_GLOBAL_BUFFERS0
C_INCLUDE_INTERNAL_LOOPBACK0
C_DUPLEX1
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_TX_PING_PONG1
C_RX_PING_PONG1
C_INCLUDE_PHY_CONSTRAINTS1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE1
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE1
C_S_AXI_SUPPORTS_NARROW_BURST0
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-LEDs_4Bits -   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
-

-
LEDs_4Bits IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_OO1LEDs_4Bits_TRI_O
1S_AXI_ACLKI1clk_50_0000MHzPLL0
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_BASEADDR0x40020000
C_HIGHADDR0x4002FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS0
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT0
C_DOUT_DEFAULT0x00000000
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-Push_Buttons_4Bits -   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
-

-
Push_Buttons_4Bits IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_II1Push_Buttons_4Bits_TRI_I
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2IP2INTC_IrptO1Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_BASEADDR0x40000000
C_HIGHADDR0x4000FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS1
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT1
C_DOUT_DEFAULT0x00000000
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-RS232_Uart_1 -   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

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IP Specs
CoreVersionDocumentation
axi_uartlite1.01.aIP
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-
RS232_Uart_1 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0TXO1RS232_Uart_1_sout
1RXI1RS232_Uart_1_sin
2S_AXI_ACLKI1clk_50_0000MHzPLL0
3InterruptO1RS232_Uart_1_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
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-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
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NameValue
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x40600000
C_HIGHADDR0x4060FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_BAUDRATE115200
C_DATA_BITS8
 
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NameValue
C_USE_PARITY0
C_ODD_PARITY1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-axi_timer_0 -   AXI Timer/Counter
Timer counter with AXI interface

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IP Specs
CoreVersionDocumentation
axi_timer1.01.aIP
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axi_timer_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1InterruptO1axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
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NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_FAMILYvirtex6
C_COUNT_WIDTH32
C_ONE_TIMER_ONLY0
C_TRIG0_ASSERT1
C_TRIG1_ASSERT1
C_GEN0_ASSERT1
C_GEN1_ASSERT1
C_BASEADDR0x41C00000
 
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NameValue
C_HIGHADDR0x41C0FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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IPTOP
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-clock_generator_0 -   Clock Generator
Clock generator for processor system.

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IP Specs
CoreVersionDocumentation
clock_generator4.01.aIP
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-
clock_generator_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0RSTI1RESET
1CLKINI1CLK
2CLKOUT2O1clk_100_0000MHzPLL0
3CLKOUT3O1clk_50_0000MHzPLL0
4CLKOUT0O1clk_600_0000MHzPLL0_nobuf
5CLKOUT1O1clk_600_0000MHz180PLL0_nobuf
6LOCKEDO1proc_sys_reset_0_Dcm_locked
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_DEVICENOT_SET
C_PACKAGENOT_SET
C_SPEEDGRADENOT_SET
C_CLKIN_FREQ200000000
C_CLKOUT0_FREQ600000000
C_CLKOUT0_PHASE0
C_CLKOUT0_GROUPPLL0
C_CLKOUT0_BUFFALSE
C_CLKOUT0_VARIABLE_PHASEFALSE
C_CLKOUT1_FREQ600000000
C_CLKOUT1_PHASE180
C_CLKOUT1_GROUPPLL0
C_CLKOUT1_BUFFALSE
C_CLKOUT1_VARIABLE_PHASEFALSE
C_CLKOUT2_FREQ100000000
C_CLKOUT2_PHASE0
C_CLKOUT2_GROUPPLL0
C_CLKOUT2_BUFTRUE
C_CLKOUT2_VARIABLE_PHASEFALSE
C_CLKOUT3_FREQ50000000
C_CLKOUT3_PHASE0
C_CLKOUT3_GROUPPLL0
C_CLKOUT3_BUFTRUE
C_CLKOUT3_VARIABLE_PHASEFALSE
C_CLKOUT4_FREQ0
C_CLKOUT4_PHASE0
C_CLKOUT4_GROUPNONE
C_CLKOUT4_BUFTRUE
C_CLKOUT4_VARIABLE_PHASEFALSE
C_CLKOUT5_FREQ0
C_CLKOUT5_PHASE0
C_CLKOUT5_GROUPNONE
C_CLKOUT5_BUFTRUE
C_CLKOUT5_VARIABLE_PHASEFALSE
C_CLKOUT6_FREQ0
C_CLKOUT6_PHASE0
C_CLKOUT6_GROUPNONE
C_CLKOUT6_BUFTRUE
C_CLKOUT6_VARIABLE_PHASEFALSE
C_CLKOUT7_FREQ0
C_CLKOUT7_PHASE0
C_CLKOUT7_GROUPNONE
C_CLKOUT7_BUFTRUE
C_CLKOUT7_VARIABLE_PHASEFALSE
C_CLKOUT8_FREQ0
C_CLKOUT8_PHASE0
C_CLKOUT8_GROUPNONE
 
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NameValue
C_CLKOUT8_BUFTRUE
C_CLKOUT8_VARIABLE_PHASEFALSE
C_CLKOUT9_FREQ0
C_CLKOUT9_PHASE0
C_CLKOUT9_GROUPNONE
C_CLKOUT9_BUFTRUE
C_CLKOUT9_VARIABLE_PHASEFALSE
C_CLKOUT10_FREQ0
C_CLKOUT10_PHASE0
C_CLKOUT10_GROUPNONE
C_CLKOUT10_BUFTRUE
C_CLKOUT10_VARIABLE_PHASEFALSE
C_CLKOUT11_FREQ0
C_CLKOUT11_PHASE0
C_CLKOUT11_GROUPNONE
C_CLKOUT11_BUFTRUE
C_CLKOUT11_VARIABLE_PHASEFALSE
C_CLKOUT12_FREQ0
C_CLKOUT12_PHASE0
C_CLKOUT12_GROUPNONE
C_CLKOUT12_BUFTRUE
C_CLKOUT12_VARIABLE_PHASEFALSE
C_CLKOUT13_FREQ0
C_CLKOUT13_PHASE0
C_CLKOUT13_GROUPNONE
C_CLKOUT13_BUFTRUE
C_CLKOUT13_VARIABLE_PHASEFALSE
C_CLKOUT14_FREQ0
C_CLKOUT14_PHASE0
C_CLKOUT14_GROUPNONE
C_CLKOUT14_BUFTRUE
C_CLKOUT14_VARIABLE_PHASEFALSE
C_CLKOUT15_FREQ0
C_CLKOUT15_PHASE0
C_CLKOUT15_GROUPNONE
C_CLKOUT15_BUFTRUE
C_CLKOUT15_VARIABLE_PHASEFALSE
C_CLKFBIN_FREQ0
C_CLKFBIN_DESKEWNONE
C_CLKFBOUT_FREQ0
C_CLKFBOUT_PHASE0
C_CLKFBOUT_GROUPNONE
C_CLKFBOUT_BUFTRUE
C_PSDONE_GROUPNONE
C_EXT_RESET_HIGH1
C_CLK_PRIMITIVE_FEEDBACK_BUFFALSE
C_CLK_GENUPDATE
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-proc_sys_reset_0 -   Processor System Reset Module
Reset management module

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IP Specs
CoreVersionDocumentation
proc_sys_reset3.00.aIP
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-
proc_sys_reset_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0Ext_Reset_InI1RESET
1MB_ResetO1proc_sys_reset_0_MB_Reset
2Slowest_sync_clkI1clk_50_0000MHzPLL0
3Interconnect_aresetnO1proc_sys_reset_0_Interconnect_aresetn
4Dcm_lockedI1proc_sys_reset_0_Dcm_locked
5MB_Debug_Sys_RstI1proc_sys_reset_0_MB_Debug_Sys_Rst
6BUS_STRUCT_RESETO1proc_sys_reset_0_BUS_STRUCT_RESET
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_SUBFAMILYlx
C_EXT_RST_WIDTH4
C_AUX_RST_WIDTH4
C_EXT_RESET_HIGH1
C_AUX_RESET_HIGH1
C_NUM_BUS_RST1
C_NUM_PERP_RST1
C_NUM_INTERCONNECT_ARESETN1
C_NUM_PERP_ARESETN1
C_FAMILYvirtex5
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-

-
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-

- - -
Timing InformationTOP
-

- - - -
Post Synthesis Clock Limits
- No clocks could be identified in the design. Run platgen to generate synthesis information. -
-
- diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html deleted file mode 100644 index 01df645af..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html +++ /dev/null @@ -1,5407 +0,0 @@ - - - - -XPS Project Report - - - - - - - -
TABLE OF CONTENTS
-
Overview
Block Diagram
External Ports
Processor
   microblaze_0
Debuggers
   debug_module
Interrupt Controllers
   microblaze_0_intc
Busses
   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb
Memory
   microblaze_0_bram_block
Memory Controllers
   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl
Peripherals
   Ethernet_Lite
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0
IP
   clock_generator_0
   proc_sys_reset_0
Timing Information -
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OverviewTOC
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Resources Used
1  MicroBlaze
2  AXI Interconnect
2  Local Memory Bus (LMB) 1.0
1  Block RAM (BRAM) Block
2  LMB BRAM Controller
1  AXI S6 Memory Controller(DDR/DDR2/DDR3)
1  Processor System Reset Module
1  Clock Generator
1  MicroBlaze Debug Module (MDM)
1  AXI UART (Lite)
2  AXI General Purpose IO
1  AXI 10/100 Ethernet MAC Lite
1  AXI Timer/Counter
1  AXI Interrupt Controller
- - - - - - - - - - - - - - -
Specifics
GeneratedWed Jul 27 11:49:42 2011
EDK Version13.1
Device Familyspartan6
Devicexc6slx45tfgg484-3
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Block DiagramTOC
-
BlockDiagram -
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External PortsTOC
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- - - - - - -
- These are the external ports defined in the MHS file. -
-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
-SHARED -RESETI1RESET RESET 
-Ethernet_Lite -Ethernet_Lite_COLI1Ethernet_Lite_COL
-Ethernet_Lite -Ethernet_Lite_CRSI1Ethernet_Lite_CRS
-Ethernet_Lite -Ethernet_Lite_RXDI0:3Ethernet_Lite_RXD
-Ethernet_Lite -Ethernet_Lite_RX_CLKI1Ethernet_Lite_RX_CLK
-Ethernet_Lite -Ethernet_Lite_RX_DVI1Ethernet_Lite_RX_DV
-Ethernet_Lite -Ethernet_Lite_RX_ERI1Ethernet_Lite_RX_ER
-Ethernet_Lite -Ethernet_Lite_TX_CLKI1Ethernet_Lite_TX_CLK
-Ethernet_Lite -Ethernet_Lite_MDIOIO1Ethernet_Lite_MDIO
-Ethernet_Lite -Ethernet_Lite_MDCO1Ethernet_Lite_MDC
-Ethernet_Lite -Ethernet_Lite_PHY_RST_NO1Ethernet_Lite_PHY_RST_N
-Ethernet_Lite -Ethernet_Lite_TXDO0:3Ethernet_Lite_TXD
-Ethernet_Lite -Ethernet_Lite_TX_ENO1Ethernet_Lite_TX_EN
-LEDs_4Bits -LEDs_4Bits_TRI_OO3:0LEDs_4Bits_TRI_O
-MCB_DDR3 -mcbx_dram_dqIO0:15mcbx_dram_dq
-MCB_DDR3 -mcbx_dram_dqsIO1mcbx_dram_dqs
-MCB_DDR3 -mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
-MCB_DDR3 -mcbx_dram_udqsIO1mcbx_dram_udqs
-MCB_DDR3 -mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
-MCB_DDR3 -rzqIO1rzq
-MCB_DDR3 -zioIO1zio
-MCB_DDR3 -mcbx_dram_addrO0:12mcbx_dram_addr
-MCB_DDR3 -mcbx_dram_baO0:2mcbx_dram_ba
-MCB_DDR3 -mcbx_dram_cas_nO1mcbx_dram_cas_n
-MCB_DDR3 -mcbx_dram_ckeO1mcbx_dram_cke
-MCB_DDR3 -mcbx_dram_clkO1mcbx_dram_clk
-MCB_DDR3 -mcbx_dram_clk_nO1mcbx_dram_clk_n
-MCB_DDR3 -mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
-MCB_DDR3 -mcbx_dram_ldmO1mcbx_dram_ldm
-MCB_DDR3 -mcbx_dram_odtO1mcbx_dram_odt
-MCB_DDR3 -mcbx_dram_ras_nO1mcbx_dram_ras_n
-MCB_DDR3 -mcbx_dram_udmO1mcbx_dram_udm
-MCB_DDR3 -mcbx_dram_we_nO1mcbx_dram_we_n
-Push_Buttons_4Bits -Push_Buttons_4Bits_TRI_II0:3Push_Buttons_4Bits_TRI_I
-RS232_Uart_1 -RS232_Uart_1_sinI1RS232_Uart_1_sin
-RS232_Uart_1 -RS232_Uart_1_soutO1RS232_Uart_1_sout
-clock_generator_0 -CLK_NI1CLK CLK 
-clock_generator_0 -CLK_PI1CLK CLK 
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ProcessorsTOC
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-microblaze_0 -   MicroBlaze
The MicroBlaze 32 bit soft processor

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IP Specs
CoreVersionDocumentation
microblaze8.10.aIP
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microblaze_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0MB_RESETI1proc_sys_reset_0_MB_Reset
1CLKI1clk_100_0000MHzPLL0
2INTERRUPTI1microblaze_0_interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXI_DPMASTERAXIaxi4lite_07 Peripherals.
M_AXI_DCMASTERAXIaxi4_0MCB_DDR3
M_AXI_ICMASTERAXIaxi4_0MCB_DDR3
DLMBMASTERLMBmicroblaze_0_dlmbmicroblaze_0_d_bram_ctrl
ILMBMASTERLMBmicroblaze_0_ilmbmicroblaze_0_i_bram_ctrl
DEBUGTARGETXIL_MBDEBUG3microblaze_0_debugdebug_module
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SCO0
C_FREQ0
C_DATA_SIZE32
C_DYNAMIC_BUS_SIZING1
C_FAMILYvirtex5
C_INSTANCEmicroblaze
C_FAULT_TOLERANT0
C_ECC_USE_CE_EXCEPTION0
C_ENDIANNESS0
C_AREA_OPTIMIZED0
C_OPTIMIZATION0
C_INTERCONNECT2
C_STREAM_INTERCONNECT0
C_DPLB_DWIDTH32
C_DPLB_NATIVE_DWIDTH32
C_DPLB_BURST_EN0
C_DPLB_P2P0
C_IPLB_DWIDTH32
C_IPLB_NATIVE_DWIDTH32
C_IPLB_BURST_EN0
C_IPLB_P2P0
C_M_AXI_DP_SUPPORTS_THREADS0
C_M_AXI_DP_THREAD_ID_WIDTH1
C_M_AXI_DP_SUPPORTS_READ1
C_M_AXI_DP_SUPPORTS_WRITE1
C_M_AXI_DP_SUPPORTS_NARROW_BURST0
C_M_AXI_DP_DATA_WIDTH32
C_M_AXI_DP_ADDR_WIDTH32
C_M_AXI_DP_PROTOCOLAXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING1
C_M_AXI_IP_SUPPORTS_THREADS0
C_M_AXI_IP_THREAD_ID_WIDTH1
C_M_AXI_IP_SUPPORTS_READ1
C_M_AXI_IP_SUPPORTS_WRITE0
C_M_AXI_IP_SUPPORTS_NARROW_BURST0
C_M_AXI_IP_DATA_WIDTH32
C_M_AXI_IP_ADDR_WIDTH32
C_M_AXI_IP_PROTOCOLAXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING1
C_D_AXI0
C_D_PLB0
C_D_LMB1
C_I_AXI0
C_I_PLB0
C_I_LMB1
C_USE_MSR_INSTR1
C_USE_PCMP_INSTR1
C_USE_BARREL1
C_USE_DIV1
C_USE_HW_MUL1
C_USE_FPU1
C_UNALIGNED_EXCEPTIONS1
C_ILL_OPCODE_EXCEPTION1
C_M_AXI_I_BUS_EXCEPTION1
C_M_AXI_D_BUS_EXCEPTION1
C_IPLB_BUS_EXCEPTION0
C_DPLB_BUS_EXCEPTION0
C_DIV_ZERO_EXCEPTION1
C_FPU_EXCEPTION1
C_FSL_EXCEPTION0
C_USE_STACK_PROTECTION0
C_PVR0
C_PVR_USER10x00
C_PVR_USER20x00000000
C_DEBUG_ENABLED1
C_NUMBER_OF_PC_BRK7
C_NUMBER_OF_RD_ADDR_BRK2
C_NUMBER_OF_WR_ADDR_BRK2
C_INTERRUPT_IS_EDGE0
C_EDGE_IS_POSITIVE1
C_RESET_MSR0x00000000
C_OPCODE_0x0_ILLEGAL1
C_FSL_LINKS0
C_FSL_DATA_SIZE32
C_USE_EXTENDED_FSL_INSTR0
C_M0_AXIS_PROTOCOLGENERIC
C_S0_AXIS_PROTOCOLGENERIC
C_M1_AXIS_PROTOCOLGENERIC
C_S1_AXIS_PROTOCOLGENERIC
C_M2_AXIS_PROTOCOLGENERIC
C_S2_AXIS_PROTOCOLGENERIC
C_M3_AXIS_PROTOCOLGENERIC
C_S3_AXIS_PROTOCOLGENERIC
C_M4_AXIS_PROTOCOLGENERIC
C_S4_AXIS_PROTOCOLGENERIC
C_M5_AXIS_PROTOCOLGENERIC
C_S5_AXIS_PROTOCOLGENERIC
C_M6_AXIS_PROTOCOLGENERIC
C_S6_AXIS_PROTOCOLGENERIC
C_M7_AXIS_PROTOCOLGENERIC
C_S7_AXIS_PROTOCOLGENERIC
C_M8_AXIS_PROTOCOLGENERIC
C_S8_AXIS_PROTOCOLGENERIC
C_M9_AXIS_PROTOCOLGENERIC
C_S9_AXIS_PROTOCOLGENERIC
C_M10_AXIS_PROTOCOLGENERIC
C_S10_AXIS_PROTOCOLGENERIC
C_M11_AXIS_PROTOCOLGENERIC
C_S11_AXIS_PROTOCOLGENERIC
C_M12_AXIS_PROTOCOLGENERIC
C_S12_AXIS_PROTOCOLGENERIC
C_M13_AXIS_PROTOCOLGENERIC
C_S13_AXIS_PROTOCOLGENERIC
C_M14_AXIS_PROTOCOLGENERIC
C_S14_AXIS_PROTOCOLGENERIC
C_M15_AXIS_PROTOCOLGENERIC
C_S15_AXIS_PROTOCOLGENERIC
C_M0_AXIS_DATA_WIDTH32
C_S0_AXIS_DATA_WIDTH32
C_M1_AXIS_DATA_WIDTH32
C_S1_AXIS_DATA_WIDTH32
C_M2_AXIS_DATA_WIDTH32
C_S2_AXIS_DATA_WIDTH32
 
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NameValue
C_M3_AXIS_DATA_WIDTH32
C_S3_AXIS_DATA_WIDTH32
C_M4_AXIS_DATA_WIDTH32
C_S4_AXIS_DATA_WIDTH32
C_M5_AXIS_DATA_WIDTH32
C_S5_AXIS_DATA_WIDTH32
C_M6_AXIS_DATA_WIDTH32
C_S6_AXIS_DATA_WIDTH32
C_M7_AXIS_DATA_WIDTH32
C_S7_AXIS_DATA_WIDTH32
C_M8_AXIS_DATA_WIDTH32
C_S8_AXIS_DATA_WIDTH32
C_M9_AXIS_DATA_WIDTH32
C_S9_AXIS_DATA_WIDTH32
C_M10_AXIS_DATA_WIDTH32
C_S10_AXIS_DATA_WIDTH32
C_M11_AXIS_DATA_WIDTH32
C_S11_AXIS_DATA_WIDTH32
C_M12_AXIS_DATA_WIDTH32
C_S12_AXIS_DATA_WIDTH32
C_M13_AXIS_DATA_WIDTH32
C_S13_AXIS_DATA_WIDTH32
C_M14_AXIS_DATA_WIDTH32
C_S14_AXIS_DATA_WIDTH32
C_M15_AXIS_DATA_WIDTH32
C_S15_AXIS_DATA_WIDTH32
C_ICACHE_BASEADDR0xC0000000
C_ICACHE_HIGHADDR0xC7FFFFFF
C_USE_ICACHE1
C_ALLOW_ICACHE_WR1
C_ADDR_TAG_BITS17
C_CACHE_BYTE_SIZE16384
C_ICACHE_USE_FSL1
C_ICACHE_LINE_LEN4
C_ICACHE_ALWAYS_USED1
C_ICACHE_INTERFACE0
C_ICACHE_VICTIMS0
C_ICACHE_STREAMS0
C_ICACHE_FORCE_TAG_LUTRAM0
C_ICACHE_DATA_WIDTH0
C_M_AXI_IC_SUPPORTS_THREADS0
C_M_AXI_IC_THREAD_ID_WIDTH1
C_M_AXI_IC_SUPPORTS_READ1
C_M_AXI_IC_SUPPORTS_WRITE0
C_M_AXI_IC_SUPPORTS_NARROW_BURST0
C_M_AXI_IC_DATA_WIDTH32
C_M_AXI_IC_ADDR_WIDTH32
C_M_AXI_IC_PROTOCOLAXI4
C_M_AXI_IC_USER_VALUE0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS1
C_M_AXI_IC_AWUSER_WIDTH5
C_M_AXI_IC_ARUSER_WIDTH5
C_M_AXI_IC_WUSER_WIDTH1
C_M_AXI_IC_RUSER_WIDTH1
C_M_AXI_IC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING2
C_DCACHE_BASEADDR0xC0000000
C_DCACHE_HIGHADDR0xC7FFFFFF
C_USE_DCACHE1
C_ALLOW_DCACHE_WR1
C_DCACHE_ADDR_TAG17
C_DCACHE_BYTE_SIZE16384
C_DCACHE_USE_FSL1
C_DCACHE_LINE_LEN4
C_DCACHE_ALWAYS_USED1
C_DCACHE_INTERFACE0
C_DCACHE_USE_WRITEBACK0
C_DCACHE_VICTIMS0
C_DCACHE_FORCE_TAG_LUTRAM0
C_DCACHE_DATA_WIDTH0
C_M_AXI_DC_SUPPORTS_THREADS0
C_M_AXI_DC_THREAD_ID_WIDTH1
C_M_AXI_DC_SUPPORTS_READ1
C_M_AXI_DC_SUPPORTS_WRITE1
C_M_AXI_DC_SUPPORTS_NARROW_BURST0
C_M_AXI_DC_DATA_WIDTH32
C_M_AXI_DC_ADDR_WIDTH32
C_M_AXI_DC_PROTOCOLAXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS0
C_M_AXI_DC_USER_VALUE0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS1
C_M_AXI_DC_AWUSER_WIDTH5
C_M_AXI_DC_ARUSER_WIDTH5
C_M_AXI_DC_WUSER_WIDTH1
C_M_AXI_DC_RUSER_WIDTH1
C_M_AXI_DC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING32
C_USE_MMU0
C_MMU_DTLB_SIZE4
C_MMU_ITLB_SIZE2
C_MMU_TLB_ACCESS3
C_MMU_ZONES16
C_MMU_PRIVILEGED_INSTR0
C_USE_INTERRUPT0
C_USE_EXT_BRK0
C_USE_EXT_NM_BRK0
C_USE_BRANCH_TARGET_CACHE0
C_BRANCH_TARGET_CACHE_SIZE0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER1
C_INTERCONNECT_M_AXI_DC_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER1
C_INTERCONNECT_M_AXI_DP_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_R_REGISTER1
C_INTERCONNECT_M_AXI_DP_B_REGISTER1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER1
C_INTERCONNECT_M_AXI_DC_R_REGISTER1
C_INTERCONNECT_M_AXI_DC_B_REGISTER1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER1
C_INTERCONNECT_M_AXI_IC_W_REGISTER1
C_INTERCONNECT_M_AXI_IC_R_REGISTER1
C_INTERCONNECT_M_AXI_IC_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-

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DebuggersTOC
-
- - -
- - - - - - - - - -
-debug_module -   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
mdm2.00.bIP
-

-
debug_module IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1Debug_SYS_RstO1proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
MBDEBUG_0INITIATORXIL_MBDEBUG3microblaze_0_debugmicroblaze_0
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_JTAG_CHAIN2
C_INTERCONNECT2
C_BASEADDR0x74800000
C_HIGHADDR0x7480FFFF
C_SPLB_AWIDTH32
C_SPLB_DWIDTH32
C_SPLB_P2P0
C_SPLB_MID_WIDTH3
C_SPLB_NUM_MASTERS8
C_SPLB_NATIVE_DWIDTH32
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SPLB_SUPPORT_BURSTS0
C_MB_DBG_PORTS1
C_USE_UART1
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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Interrupt ControllersTOC
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- - - - - - - - - -
-microblaze_0_intc -   AXI Interrupt Controller
intc core attached to the AXI

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_intc1.01.aIP
-

-
microblaze_0_intc IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0IRQO1microblaze_0_interrupt
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2INTRI1Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-Interrupt Priorities
PrioritySIGMODULE
0Push_Buttons_4Bits_IP2INTC_IrptPush_Buttons_4Bits
1Ethernet_Lite_IP2INTC_IrptEthernet_Lite
2axi_timer_0_Interruptaxi_timer_0
3RS232_Uart_1_InterruptRS232_Uart_1
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_BASEADDR0x41200000
C_HIGHADDR0x4120FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_NUM_INTR_INPUTS2
C_KIND_OF_INTR0xFFFFFFFF
C_KIND_OF_EDGE0xFFFFFFFF
C_KIND_OF_LVL0xFFFFFFFF
C_HAS_IPR1
C_HAS_SIE1
 
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NameValue
C_HAS_CIE1
C_HAS_IVR1
C_IRQ_IS_LEVEL1
C_IRQ_ACTIVE1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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BussesTOC
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-axi4_0 -   AXI Interconnect
AXI4 Memory-Mapped Interconnect

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
-

-
axi4_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0interconnect_aclkI1clk_100_0000MHzPLL0
1INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DC
microblaze_0MASTERM_AXI_IC
MCB_DDR3SLAVES0_AXI
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE1
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-axi4lite_0 -   AXI Interconnect
AXI4 Memory-Mapped Interconnect

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
-

-
axi4lite_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
1INTERCONNECT_ACLKI1clk_50_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DP
debug_moduleSLAVES_AXI
RS232_Uart_1SLAVES_AXI
LEDs_4BitsSLAVES_AXI
Push_Buttons_4BitsSLAVES_AXI
Ethernet_LiteSLAVES_AXI
axi_timer_0SLAVES_AXI
microblaze_0_intcSLAVES_AXI
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE0
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_dlmb -   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
-

-
microblaze_0_dlmb IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERDLMB
microblaze_0_d_bram_ctrlSLAVESLMB
-

-
- - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_ilmb -   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
-

-
microblaze_0_ilmb IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERILMB
microblaze_0_i_bram_ctrlSLAVESLMB
-

-
- - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
MemorysTOC
-
- - -
- - - - - - - - - -
-microblaze_0_bram_block -   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
bram_block1.00.aIP
-

-
microblaze_0_bram_block IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
PORTATARGETXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_i_bram_ctrl
PORTBTARGETXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_d_bram_ctrl
-

-
- - - - - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_MEMSIZE2048
C_PORT_DWIDTH32
C_PORT_AWIDTH32
C_NUM_WE4
C_FAMILYvirtex2
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
Memory ControllersTOC
-
- - - - - - -
- - - - - - - - - -
-MCB_DDR3 -   AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_s6_ddrx1.02.aIP
-

-
MCB_DDR3 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0mcbx_dram_clkO1mcbx_dram_clk
1mcbx_dram_clk_nO1mcbx_dram_clk_n
2mcbx_dram_ckeO1mcbx_dram_cke
3mcbx_dram_odtO1mcbx_dram_odt
4mcbx_dram_ras_nO1mcbx_dram_ras_n
5mcbx_dram_cas_nO1mcbx_dram_cas_n
6mcbx_dram_we_nO1mcbx_dram_we_n
7mcbx_dram_udmO1mcbx_dram_udm
8mcbx_dram_ldmO1mcbx_dram_ldm
9mcbx_dram_baO1mcbx_dram_ba
10mcbx_dram_addrO1mcbx_dram_addr
11mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
12mcbx_dram_dqIO1mcbx_dram_dq
13mcbx_dram_dqsIO1mcbx_dram_dqs
14mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
15mcbx_dram_udqsIO1mcbx_dram_udqs
16mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
17rzqIO1rzq
18zioIO1zio
19s0_axi_aclkI1clk_100_0000MHzPLL0
20ui_clkI1clk_100_0000MHzPLL0
21sysclk_2xI1clk_600_0000MHzPLL0_nobuf
22sysclk_2x_180I1clk_600_0000MHz180PLL0_nobuf
23SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
24PLL_LOCKI1proc_sys_reset_0_Dcm_locked
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S0_AXISLAVEAXIaxi4_0microblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_MCB_LOCMEMC3
C_MCB_RZQ_LOCK7
C_MCB_ZIO_LOCR7
C_MCB_PERFORMANCESTANDARD
C_BYPASS_CORE_UCF0
C_S0_AXI_BASEADDR0xC0000000
C_S0_AXI_HIGHADDR0xC7FFFFFF
C_S1_AXI_BASEADDR0xFFFFFFFF
C_S1_AXI_HIGHADDR0x00000000
C_S2_AXI_BASEADDR0xFFFFFFFF
C_S2_AXI_HIGHADDR0x00000000
C_S3_AXI_BASEADDR0xFFFFFFFF
C_S3_AXI_HIGHADDR0x00000000
C_S4_AXI_BASEADDR0xFFFFFFFF
C_S4_AXI_HIGHADDR0x00000000
C_S5_AXI_BASEADDR0xFFFFFFFF
C_S5_AXI_HIGHADDR0x00000000
C_MEM_TYPEDDR3
C_MEM_PARTNOMT41J64M16XX-187E
C_MEM_BASEPARTNONOT_SET
C_NUM_DQ_PINS16
C_MEM_ADDR_WIDTH13
C_MEM_BANKADDR_WIDTH3
C_MEM_NUM_COL_BITS10
C_MEM_TRAS-1
C_MEM_TRCD-1
C_MEM_TREFI-1
C_MEM_TRFC-1
C_MEM_TRP-1
C_MEM_TWR-1
C_MEM_TRTP-1
C_MEM_TWTR-1
C_PORT_CONFIGB32_B32_B32_B32
C_SKIP_IN_TERM_CAL0
C_SKIP_IN_TERM_CAL_VALUENONE
C_MEMCLK_PERIOD0
C_MEM_ADDR_ORDERROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT512
C_MEM_CAS_LATENCY6
C_SIMULATIONFALSE
C_MEM_DDR1_2_ODSFULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR2_RTT150OHMS
C_MEM_DDR2_DIFF_DQS_ENYES
C_MEM_DDR2_3_PA_SRFULL
C_MEM_DDR2_3_HIGH_TEMP_SRNORMAL
C_MEM_DDR3_CAS_WR_LATENCY5
C_MEM_DDR3_CAS_LATENCY6
C_MEM_DDR3_ODSDIV6
C_MEM_DDR3_RTTDIV4
C_MEM_DDR3_AUTO_SRENABLED
C_MEM_MOBILE_PA_SRFULL
C_MEM_MDDR_ODSFULL
C_ARB_ALGORITHM0
C_ARB_NUM_TIME_SLOTS12
C_ARB_TIME_SLOT_00b000000000001010011
C_ARB_TIME_SLOT_10b000000001010011000
C_ARB_TIME_SLOT_20b000000010011000001
C_ARB_TIME_SLOT_30b000000011000001010
C_ARB_TIME_SLOT_40b000000000001010011
C_ARB_TIME_SLOT_50b000000001010011000
C_ARB_TIME_SLOT_60b000000010011000001
C_ARB_TIME_SLOT_70b000000011000001010
C_ARB_TIME_SLOT_80b000000000001010011
C_ARB_TIME_SLOT_90b000000001010011000
C_ARB_TIME_SLOT_100b000000010011000001
C_ARB_TIME_SLOT_110b000000011000001010
C_S0_AXI_ENABLE1
C_S0_AXI_PROTOCOLAXI4
C_S0_AXI_ID_WIDTH4
C_S0_AXI_ADDR_WIDTH32
C_S0_AXI_DATA_WIDTH32
C_S0_AXI_SUPPORTS_READ1
C_S0_AXI_SUPPORTS_WRITE1
C_S0_AXI_SUPPORTS_NARROW_BURST1
C_S0_AXI_REG_EN00x00000
C_S0_AXI_REG_EN10x01000
C_S0_AXI_STRICT_COHERENCY1
C_S0_AXI_ENABLE_AP0
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE4
C_S1_AXI_ENABLE0
C_S1_AXI_PROTOCOLAXI4
C_S1_AXI_ID_WIDTH4
C_S1_AXI_ADDR_WIDTH32
C_S1_AXI_DATA_WIDTH32
C_S1_AXI_SUPPORTS_READ1
C_S1_AXI_SUPPORTS_WRITE1
C_S1_AXI_SUPPORTS_NARROW_BURST1
C_S1_AXI_REG_EN00x00000
C_S1_AXI_REG_EN10x01000
C_S1_AXI_STRICT_COHERENCY1
C_S1_AXI_ENABLE_AP0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE4
C_S2_AXI_ENABLE0
C_S2_AXI_PROTOCOLAXI4
C_S2_AXI_ID_WIDTH4
C_S2_AXI_ADDR_WIDTH32
C_S2_AXI_DATA_WIDTH32
C_S2_AXI_SUPPORTS_READ1
C_S2_AXI_SUPPORTS_WRITE1
C_S2_AXI_SUPPORTS_NARROW_BURST1
C_S2_AXI_REG_EN00x00000
C_S2_AXI_REG_EN10x01000
C_S2_AXI_STRICT_COHERENCY1
C_S2_AXI_ENABLE_AP0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE4
C_S3_AXI_ENABLE0
C_S3_AXI_PROTOCOLAXI4
C_S3_AXI_ID_WIDTH4
C_S3_AXI_ADDR_WIDTH32
C_S3_AXI_DATA_WIDTH32
C_S3_AXI_SUPPORTS_READ1
C_S3_AXI_SUPPORTS_WRITE1
C_S3_AXI_SUPPORTS_NARROW_BURST1
C_S3_AXI_REG_EN00x00000
C_S3_AXI_REG_EN10x01000
C_S3_AXI_STRICT_COHERENCY1
C_S3_AXI_ENABLE_AP0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE4
C_S4_AXI_ENABLE0
C_S4_AXI_PROTOCOLAXI4
C_S4_AXI_ID_WIDTH4
C_S4_AXI_ADDR_WIDTH32
C_S4_AXI_DATA_WIDTH32
C_S4_AXI_SUPPORTS_READ1
C_S4_AXI_SUPPORTS_WRITE1
C_S4_AXI_SUPPORTS_NARROW_BURST1
C_S4_AXI_REG_EN00x00000
C_S4_AXI_REG_EN10x01000
C_S4_AXI_STRICT_COHERENCY1
C_S4_AXI_ENABLE_AP0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE4
C_S5_AXI_ENABLE0
C_S5_AXI_PROTOCOLAXI4
C_S5_AXI_ID_WIDTH4
C_S5_AXI_ADDR_WIDTH32
C_S5_AXI_DATA_WIDTH32
C_S5_AXI_SUPPORTS_READ1
C_S5_AXI_SUPPORTS_WRITE1
C_S5_AXI_SUPPORTS_NARROW_BURST1
C_S5_AXI_REG_EN00x00000
C_S5_AXI_REG_EN10x01000
C_S5_AXI_STRICT_COHERENCY1
C_S5_AXI_ENABLE_AP0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE4
C_MCB_USE_EXTERNAL_BUFPLL0
C_SYS_RST_PRESENT0
C_INTERCONNECT_S0_AXI_MASTERSmicroblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
C_INTERCONNECT_S0_AXI_AW_REGISTER1
C_INTERCONNECT_S0_AXI_AR_REGISTER1
C_INTERCONNECT_S0_AXI_W_REGISTER1
C_INTERCONNECT_S0_AXI_R_REGISTER1
C_INTERCONNECT_S0_AXI_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_d_bram_ctrl -   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
-

-
microblaze_0_d_bram_ctrl IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_dlmbmicroblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-
- - - - - - - - - -
-microblaze_0_i_bram_ctrl -   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
-

-
microblaze_0_i_bram_ctrl IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_ilmbmicroblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
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NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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PeripheralsTOC
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-Ethernet_Lite -   AXI 10/100 Ethernet MAC Lite
'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_ethernetlite1.00.aIP
-

-
Ethernet_Lite IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0PHY_MDIOIO1Ethernet_Lite_MDIO
1PHY_MDCO1Ethernet_Lite_MDC
2PHY_tx_dataO1Ethernet_Lite_TXD
3PHY_tx_enO1Ethernet_Lite_TX_EN
4PHY_tx_clkI1Ethernet_Lite_TX_CLK
5PHY_colI1Ethernet_Lite_COL
6PHY_rx_dataI1Ethernet_Lite_RXD
7PHY_rx_erI1Ethernet_Lite_RX_ER
8PHY_rx_clkI1Ethernet_Lite_RX_CLK
9PHY_crsI1Ethernet_Lite_CRS
10PHY_dvI1Ethernet_Lite_RX_DV
11PHY_rst_nO1Ethernet_Lite_PHY_RST_N
12S_AXI_ACLKI1clk_50_0000MHzPLL0
13IP2INTC_IrptO1Ethernet_Lite_IP2INTC_Irpt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_FAMILYvirtex6
C_BASEADDR0x40E00000
C_HIGHADDR0x40E0FFFF
C_S_AXI_ACLK_PERIOD_PS10000
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_ID_WIDTH1
C_INCLUDE_MDIO1
C_INCLUDE_GLOBAL_BUFFERS0
C_INCLUDE_INTERNAL_LOOPBACK0
C_DUPLEX1
 
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NameValue
C_TX_PING_PONG1
C_RX_PING_PONG1
C_INCLUDE_PHY_CONSTRAINTS1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE1
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE1
C_S_AXI_SUPPORTS_NARROW_BURST0
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-
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-LEDs_4Bits -   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
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-
LEDs_4Bits IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_OO1LEDs_4Bits_TRI_O
1S_AXI_ACLKI1clk_50_0000MHzPLL0
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
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-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
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NameValue
C_FAMILYvirtex6
C_BASEADDR0x40020000
C_HIGHADDR0x4002FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS0
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT0
C_DOUT_DEFAULT0x00000000
 
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NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-
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-Push_Buttons_4Bits -   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
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-
Push_Buttons_4Bits IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_II1Push_Buttons_4Bits_TRI_I
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2IP2INTC_IrptO1Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_BASEADDR0x40000000
C_HIGHADDR0x4000FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS1
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT1
C_DOUT_DEFAULT0x00000000
 
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NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-RS232_Uart_1 -   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

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- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_uartlite1.01.aIP
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-
RS232_Uart_1 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0TXO1RS232_Uart_1_sout
1RXI1RS232_Uart_1_sin
2S_AXI_ACLKI1clk_50_0000MHzPLL0
3InterruptO1RS232_Uart_1_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x40600000
C_HIGHADDR0x4060FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_BAUDRATE115200
C_DATA_BITS8
 
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NameValue
C_USE_PARITY0
C_ODD_PARITY1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-axi_timer_0 -   AXI Timer/Counter
Timer counter with AXI interface

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_timer1.01.aIP
-

-
axi_timer_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1InterruptO1axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_07 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_FAMILYvirtex6
C_COUNT_WIDTH32
C_ONE_TIMER_ONLY0
C_TRIG0_ASSERT1
C_TRIG1_ASSERT1
C_GEN0_ASSERT1
C_GEN1_ASSERT1
C_BASEADDR0x41C00000
 
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NameValue
C_HIGHADDR0x41C0FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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IPTOC
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-clock_generator_0 -   Clock Generator
Clock generator for processor system.

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IP Specs
CoreVersionDocumentation
clock_generator4.01.aIP
-

-
clock_generator_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0RSTI1RESET
1CLKINI1CLK
2CLKOUT2O1clk_100_0000MHzPLL0
3CLKOUT3O1clk_50_0000MHzPLL0
4CLKOUT0O1clk_600_0000MHzPLL0_nobuf
5CLKOUT1O1clk_600_0000MHz180PLL0_nobuf
6LOCKEDO1proc_sys_reset_0_Dcm_locked
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-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_DEVICENOT_SET
C_PACKAGENOT_SET
C_SPEEDGRADENOT_SET
C_CLKIN_FREQ200000000
C_CLKOUT0_FREQ600000000
C_CLKOUT0_PHASE0
C_CLKOUT0_GROUPPLL0
C_CLKOUT0_BUFFALSE
C_CLKOUT0_VARIABLE_PHASEFALSE
C_CLKOUT1_FREQ600000000
C_CLKOUT1_PHASE180
C_CLKOUT1_GROUPPLL0
C_CLKOUT1_BUFFALSE
C_CLKOUT1_VARIABLE_PHASEFALSE
C_CLKOUT2_FREQ100000000
C_CLKOUT2_PHASE0
C_CLKOUT2_GROUPPLL0
C_CLKOUT2_BUFTRUE
C_CLKOUT2_VARIABLE_PHASEFALSE
C_CLKOUT3_FREQ50000000
C_CLKOUT3_PHASE0
C_CLKOUT3_GROUPPLL0
C_CLKOUT3_BUFTRUE
C_CLKOUT3_VARIABLE_PHASEFALSE
C_CLKOUT4_FREQ0
C_CLKOUT4_PHASE0
C_CLKOUT4_GROUPNONE
C_CLKOUT4_BUFTRUE
C_CLKOUT4_VARIABLE_PHASEFALSE
C_CLKOUT5_FREQ0
C_CLKOUT5_PHASE0
C_CLKOUT5_GROUPNONE
C_CLKOUT5_BUFTRUE
C_CLKOUT5_VARIABLE_PHASEFALSE
C_CLKOUT6_FREQ0
C_CLKOUT6_PHASE0
C_CLKOUT6_GROUPNONE
C_CLKOUT6_BUFTRUE
C_CLKOUT6_VARIABLE_PHASEFALSE
C_CLKOUT7_FREQ0
C_CLKOUT7_PHASE0
C_CLKOUT7_GROUPNONE
C_CLKOUT7_BUFTRUE
C_CLKOUT7_VARIABLE_PHASEFALSE
C_CLKOUT8_FREQ0
C_CLKOUT8_PHASE0
C_CLKOUT8_GROUPNONE
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_CLKOUT8_BUFTRUE
C_CLKOUT8_VARIABLE_PHASEFALSE
C_CLKOUT9_FREQ0
C_CLKOUT9_PHASE0
C_CLKOUT9_GROUPNONE
C_CLKOUT9_BUFTRUE
C_CLKOUT9_VARIABLE_PHASEFALSE
C_CLKOUT10_FREQ0
C_CLKOUT10_PHASE0
C_CLKOUT10_GROUPNONE
C_CLKOUT10_BUFTRUE
C_CLKOUT10_VARIABLE_PHASEFALSE
C_CLKOUT11_FREQ0
C_CLKOUT11_PHASE0
C_CLKOUT11_GROUPNONE
C_CLKOUT11_BUFTRUE
C_CLKOUT11_VARIABLE_PHASEFALSE
C_CLKOUT12_FREQ0
C_CLKOUT12_PHASE0
C_CLKOUT12_GROUPNONE
C_CLKOUT12_BUFTRUE
C_CLKOUT12_VARIABLE_PHASEFALSE
C_CLKOUT13_FREQ0
C_CLKOUT13_PHASE0
C_CLKOUT13_GROUPNONE
C_CLKOUT13_BUFTRUE
C_CLKOUT13_VARIABLE_PHASEFALSE
C_CLKOUT14_FREQ0
C_CLKOUT14_PHASE0
C_CLKOUT14_GROUPNONE
C_CLKOUT14_BUFTRUE
C_CLKOUT14_VARIABLE_PHASEFALSE
C_CLKOUT15_FREQ0
C_CLKOUT15_PHASE0
C_CLKOUT15_GROUPNONE
C_CLKOUT15_BUFTRUE
C_CLKOUT15_VARIABLE_PHASEFALSE
C_CLKFBIN_FREQ0
C_CLKFBIN_DESKEWNONE
C_CLKFBOUT_FREQ0
C_CLKFBOUT_PHASE0
C_CLKFBOUT_GROUPNONE
C_CLKFBOUT_BUFTRUE
C_PSDONE_GROUPNONE
C_EXT_RESET_HIGH1
C_CLK_PRIMITIVE_FEEDBACK_BUFFALSE
C_CLK_GENUPDATE
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-proc_sys_reset_0 -   Processor System Reset Module
Reset management module

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- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
proc_sys_reset3.00.aIP
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-
proc_sys_reset_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0Ext_Reset_InI1RESET
1MB_ResetO1proc_sys_reset_0_MB_Reset
2Slowest_sync_clkI1clk_50_0000MHzPLL0
3Interconnect_aresetnO1proc_sys_reset_0_Interconnect_aresetn
4Dcm_lockedI1proc_sys_reset_0_Dcm_locked
5MB_Debug_Sys_RstI1proc_sys_reset_0_MB_Debug_Sys_Rst
6BUS_STRUCT_RESETO1proc_sys_reset_0_BUS_STRUCT_RESET
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_SUBFAMILYlx
C_EXT_RST_WIDTH4
C_AUX_RST_WIDTH4
C_EXT_RESET_HIGH1
C_AUX_RESET_HIGH1
C_NUM_BUS_RST1
C_NUM_PERP_RST1
C_NUM_INTERCONNECT_ARESETN1
C_NUM_PERP_ARESETN1
C_FAMILYvirtex5
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
Timing InformationTOC
-

- - - -
Post Synthesis Clock Limits
- No clocks could be identified in the design. Run platgen to generate synthesis information. -
-
- - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html deleted file mode 100644 index 25287d5b0..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html +++ /dev/null @@ -1,73 +0,0 @@ - - - - -Table of Contents - - - - -
-Overview
Block Diagram
External Ports
- Processor -
-   microblaze_0
- Debuggers -
-   debug_module
- Interrupt Controllers -
-   microblaze_0_intc
- Busses -
-   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb
- Memory -
-   microblaze_0_bram_block
- Memory Controllers -
-   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl
- Peripherals -
-   Ethernet_Lite
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0
- IP -
-   clock_generator_0
   proc_sys_reset_0
Timing Information
-
- -- 2.39.5