From 882ecfa390516791d5e04db2d7c5ed602441755a Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 1 Nov 2011 20:00:27 +0000 Subject: [PATCH] net, davinci_emac: make clock divider in MDIO control register configurable Define CONFIG_SYS_EMAC_TI_CLKDIV for setting the clkdiv value in the MDIO control register. Signed-off-by: Heiko Schocher cc: Sandeep Paulraj cc: Wolfgang Denk Signed-off-by: Sandeep Paulraj --- drivers/net/davinci_emac.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index a9004805dc..fa31159a0e 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -53,6 +53,11 @@ unsigned int emac_dbg = 0; #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ #endif +#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) +#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ + EMAC_MDIO_CLOCK_FREQ) - 1) +#endif + static void davinci_eth_mdio_enable(void); static int gen_init_phy(int phy_addr); @@ -131,7 +136,7 @@ static void davinci_eth_mdio_enable(void) { u_int32_t clkdiv; - clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | @@ -473,7 +478,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) #endif /* Init MDIO & get link state */ - clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, &adap_mdio->CONTROL); -- 2.39.5