From 899fa289d186bbe97c02e7b2e6a03152cb7c8850 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Wed, 20 Apr 2011 18:29:28 +0000 Subject: [PATCH] git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1372 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../MicroSemi_Code/CMSIS_IAR/a2fxxxm3.h | 1102 ++++++++++ .../MicroSemi_Code/CMSIS_IAR/core_cm3.c | 784 +++++++ .../MicroSemi_Code/CMSIS_IAR/core_cm3.h | 1818 +++++++++++++++++ .../MicroSemi_Code/CMSIS_IAR/mss_assert.h | 48 + .../CMSIS_IAR/startup_iar/startup_a2fxxxm3.s | 973 +++++++++ .../CMSIS_IAR/system_a2fxxxm3.c | 199 ++ .../CMSIS_IAR/system_a2fxxxm3.h | 49 + 7 files changed, 4973 insertions(+) create mode 100644 Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/a2fxxxm3.h create mode 100644 Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/core_cm3.c create mode 100644 Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/core_cm3.h create mode 100644 Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/mss_assert.h create mode 100644 Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/startup_iar/startup_a2fxxxm3.s create mode 100644 Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/system_a2fxxxm3.c create mode 100644 Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/system_a2fxxxm3.h diff --git a/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/a2fxxxm3.h b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/a2fxxxm3.h new file mode 100644 index 000000000..ab389e05d --- /dev/null +++ b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/a2fxxxm3.h @@ -0,0 +1,1102 @@ +/******************************************************************************* + * (c) Copyright 2009 Actel Corporation. All rights reserved. + * + * SmartFusion A2FxxxM3 Cortex Microcontroller Software Interface - Peripheral + * Access Layer. + * + * This file describes the interrupt assignment and peripheral registers for + * the SmartFusion A2FxxxM3 familly of devices. + * + * SVN $Revision: 2331 $ + * SVN $Date: 2010-02-26 12:02:06 +0000 (Fri, 26 Feb 2010) $ + */ +#ifndef __A2FXXXM3_H__ +#define __A2FXXXM3_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers *********************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 2 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** SmartFusion specific Interrupt Numbers *********************************************************/ + WdogWakeup_IRQn = 0, /*!< WatchDog wakeup interrupt */ + BrownOut_1_5V_IRQn = 1, /*!< Supply dropped below 1.5V */ + BrownOut_3_3V_IRQn = 2, /*!< Supply dropped below 1.5V */ + RTC_Match_IRQn = 3, /*!< RTC match interrupt */ + RTCIF_Pub_IRQn = 4, /*!< RTC interface push button interrupt */ + EthernetMAC_IRQn = 5, /*!< Ethernet MAC interrupt */ + IAP_IRQn = 6, /*!< In Application Programming (IAP) interrupt */ + ENVM0_IRQn = 7, /*!< eNVM0 operation completion interrupt */ + ENVM1_IRQn = 8, /*!< eNVM1 operation completion interrupt */ + DMA_IRQn = 9, /*!< Peripheral DMA interrupt */ + UART0_IRQn = 10, /*!< UART0 interrupt */ + UART1_IRQn = 11, /*!< UART1 interrupt */ + SPI0_IRQn = 12, /*!< SPI0 interrupt */ + SPI1_IRQn = 13, /*!< SP1 interrupt */ + I2C0_IRQn = 14, /*!< I2C0 interrupt */ + I2C0_SMBAlert_IRQn = 15, /*!< I2C0 SMBus Alert interrupt */ + I2C0_SMBus_IRQn = 16, /*!< I2C0 SMBus Suspend interrupt */ + I2C1_IRQn = 17, /*!< I2C1 interrupt */ + I2C1_SMBAlert_IRQn = 18, /*!< I2C1 SMBus Alert interrupt */ + I2C1_SMBus_IRQn = 19, /*!< I2C1 SMBus Suspend interrupt */ + Timer1_IRQn = 20, /*!< Timer1 interrupt */ + Timer2_IRQn = 21, /*!< Timer2 interrupt */ + PLL_Lock_IRQn = 22, /*!< PLL lock interrupt */ + PLL_LockLost_IRQn = 23, /*!< PLL loss of lock interrupt */ + CommError_IRQn = 24, /*!< Communications Matrix error interrupt */ + Fabric_IRQn = 31, /*!< FPGA fabric interrupt */ + GPIO0_IRQn = 32, /*!< GPIO 0 interrupt */ + GPIO1_IRQn = 33, /*!< GPIO 1 interrupt */ + GPIO2_IRQn = 34, /*!< GPIO 2 interrupt */ + GPIO3_IRQn = 35, /*!< GPIO 3 interrupt */ + GPIO4_IRQn = 36, /*!< GPIO 4 interrupt */ + GPIO5_IRQn = 37, /*!< GPIO 5 interrupt */ + GPIO6_IRQn = 38, /*!< GPIO 6 interrupt */ + GPIO7_IRQn = 39, /*!< GPIO 7 interrupt */ + GPIO8_IRQn = 40, /*!< GPIO 8 interrupt */ + GPIO9_IRQn = 41, /*!< GPIO 9 interrupt */ + GPIO10_IRQn = 42, /*!< GPIO 10 interrupt */ + GPIO11_IRQn = 43, /*!< GPIO 11 interrupt */ + GPIO12_IRQn = 44, /*!< GPIO 12 interrupt */ + GPIO13_IRQn = 45, /*!< GPIO 13 interrupt */ + GPIO14_IRQn = 46, /*!< GPIO 14 interrupt */ + GPIO15_IRQn = 47, /*!< GPIO 15 interrupt */ + GPIO16_IRQn = 48, /*!< GPIO 16 interrupt */ + GPIO17_IRQn = 49, /*!< GPIO 17 interrupt */ + GPIO18_IRQn = 50, /*!< GPIO 18 interrupt */ + GPIO19_IRQn = 51, /*!< GPIO 19 interrupt */ + GPIO20_IRQn = 52, /*!< GPIO 20 interrupt */ + GPIO21_IRQn = 53, /*!< GPIO 21 interrupt */ + GPIO22_IRQn = 54, /*!< GPIO 22 interrupt */ + GPIO23_IRQn = 55, /*!< GPIO 23 interrupt */ + GPIO24_IRQn = 56, /*!< GPIO 24 interrupt */ + GPIO25_IRQn = 57, /*!< GPIO 25 interrupt */ + GPIO26_IRQn = 58, /*!< GPIO 26 interrupt */ + GPIO27_IRQn = 59, /*!< GPIO 27 interrupt */ + GPIO28_IRQn = 60, /*!< GPIO 28 interrupt */ + GPIO29_IRQn = 61, /*!< GPIO 29 interrupt */ + GPIO30_IRQn = 62, /*!< GPIO 30 interrupt */ + GPIO31_IRQn = 63, /*!< GPIO 31 interrupt */ + ACE_PC0_Flag0_IRQn = 64, /*!< ACE SSE program counter 0 flag 0 interrupt */ + ACE_PC0_Flag1_IRQn = 65, /*!< ACE SSE program counter 0 flag 1 interrupt */ + ACE_PC0_Flag2_IRQn = 66, /*!< ACE SSE program counter 0 flag 2 interrupt */ + ACE_PC0_Flag3_IRQn = 67, /*!< ACE SSE program counter 0 flag 3 interrupt */ + ACE_PC1_Flag0_IRQn = 68, /*!< ACE SSE program counter 1 flag 0 interrupt */ + ACE_PC1_Flag1_IRQn = 69, /*!< ACE SSE program counter 1 flag 1 interrupt */ + ACE_PC1_Flag2_IRQn = 70, /*!< ACE SSE program counter 1 flag 2 interrupt */ + ACE_PC1_Flag3_IRQn = 71, /*!< ACE SSE program counter 1 flag 3 interrupt */ + ACE_PC2_Flag0_IRQn = 72, /*!< ACE SSE program counter 2 flag 0 interrupt */ + ACE_PC2_Flag1_IRQn = 73, /*!< ACE SSE program counter 2 flag 1 interrupt */ + ACE_PC2_Flag2_IRQn = 74, /*!< ACE SSE program counter 2 flag 2 interrupt */ + ACE_PC2_Flag3_IRQn = 75, /*!< ACE SSE program counter 2 flag 3 interrupt */ + ACE_ADC0_DataValid_IRQn = 76, /*!< ACE ADC0 data valid interrupt */ + ACE_ADC1_DataValid_IRQn = 77, /*!< ACE ADC1 data valid interrupt */ + ACE_ADC2_DataValid_IRQn = 78, /*!< ACE ADC2 data valid interrupt */ + ACE_ADC0_CalDone_IRQn = 79, /*!< ACE ADC0 calibration done interrupt */ + ACE_ADC1_CalDone_IRQn = 80, /*!< ACE ADC1 calibration done interrupt */ + ACE_ADC2_CalDone_IRQn = 81, /*!< ACE ADC2 calibration done interrupt */ + ACE_ADC0_CalStart_IRQn = 82, /*!< ACE ADC0 calibration start interrupt */ + ACE_ADC1_CalStart_IRQn = 83, /*!< ACE ADC1 calibration start interrupt */ + ACE_ADC2_CalStart_IRQn = 84, /*!< ACE ADC2 calibration start interrupt */ + ACE_Comp0_Fall_IRQn = 85, /*!< ACE comparator 0 falling under reference interrupt */ + ACE_Comp1_Fall_IRQn = 86, /*!< ACE comparator 1 falling under reference interrupt */ + ACE_Comp2_Fall_IRQn = 87, /*!< ACE comparator 2 falling under reference interrupt */ + ACE_Comp3_Fall_IRQn = 88, /*!< ACE comparator 3 falling under reference interrupt */ + ACE_Comp4_Fall_IRQn = 89, /*!< ACE comparator 4 falling under reference interrupt */ + ACE_Comp5_Fall_IRQn = 90, /*!< ACE comparator 5 falling under reference interrupt */ + ACE_Comp6_Fall_IRQn = 91, /*!< ACE comparator 6 falling under reference interrupt */ + ACE_Comp7_Fall_IRQn = 92, /*!< ACE comparator 7 falling under reference interrupt */ + ACE_Comp8_Fall_IRQn = 93, /*!< ACE comparator 8 falling under reference interrupt */ + ACE_Comp9_Fall_IRQn = 94, /*!< ACE comparator 9 falling under reference interrupt */ + ACE_Comp10_Fall_IRQn = 95, /*!< ACE comparator 10 falling under reference interrupt */ + ACE_Comp11_Fall_IRQn = 96, /*!< ACE comparator 11 falling under reference interrupt */ + ACE_Comp0_Rise_IRQn = 97, /*!< ACE comparator 0 rising over reference interrupt */ + ACE_Comp1_Rise_IRQn = 98, /*!< ACE comparator 1 rising over reference interrupt */ + ACE_Comp2_Rise_IRQn = 99, /*!< ACE comparator 2 rising over reference interrupt */ + ACE_Comp3_Rise_IRQn = 100, /*!< ACE comparator 3 rising over reference interrupt */ + ACE_Comp4_Rise_IRQn = 101, /*!< ACE comparator 4 rising over reference interrupt */ + ACE_Comp5_Rise_IRQn = 102, /*!< ACE comparator 5 rising over reference interrupt */ + ACE_Comp6_Rise_IRQn = 103, /*!< ACE comparator 6 rising over reference interrupt */ + ACE_Comp7_Rise_IRQn = 104, /*!< ACE comparator 7 rising over reference interrupt */ + ACE_Comp8_Rise_IRQn = 105, /*!< ACE comparator 8 rising over reference interrupt */ + ACE_Comp9_Rise_IRQn = 106, /*!< ACE comparator 9 rising over reference interrupt */ + ACE_Comp10_Rise_IRQn = 107, /*!< ACE comparator 10 rising over reference interrupt */ + ACE_Comp11_Rise_IRQn = 108, /*!< ACE comparator 11 rising over reference interrupt */ + ACE_ADC0_FifoFull_IRQn = 109, /*!< ACE ADC0 FIFO full interrupt */ + ACE_ADC0_FifoAFull_IRQn = 110, /*!< ACE ADC0 FIFO almost full interrupt */ + ACE_ADC0_FifoEmpty_IRQn = 111, /*!< ACE ADC0 FIFO empty interrupt */ + ACE_ADC1_FifoFull_IRQn = 112, /*!< ACE ADC1 FIFO full interrupt */ + ACE_ADC1_FifoAFull_IRQn = 113, /*!< ACE ADC1 FIFO almost full interrupt */ + ACE_ADC1_FifoEmpty_IRQn = 114, /*!< ACE ADC1 FIFO empty interrupt */ + ACE_ADC2_FifoFull_IRQn = 115, /*!< ACE ADC2 FIFO full interrupt */ + ACE_ADC2_FifoAFull_IRQn = 116, /*!< ACE ADC2 FIFO almost full interrupt */ + ACE_ADC2_FifoEmpty_IRQn = 117, /*!< ACE ADC2 FIFO empty interrupt */ + ACE_PPE_Flag0_IRQn = 118, /*!< ACE post processing engine flag 0 interrupt */ + ACE_PPE_Flag1_IRQn = 119, /*!< ACE post processing engine flag 1 interrupt */ + ACE_PPE_Flag2_IRQn = 120, /*!< ACE post processing engine flag 2 interrupt */ + ACE_PPE_Flag3_IRQn = 121, /*!< ACE post processing engine flag 3 interrupt */ + ACE_PPE_Flag4_IRQn = 122, /*!< ACE post processing engine flag 4 interrupt */ + ACE_PPE_Flag5_IRQn = 123, /*!< ACE post processing engine flag 5 interrupt */ + ACE_PPE_Flag6_IRQn = 124, /*!< ACE post processing engine flag 6 interrupt */ + ACE_PPE_Flag7_IRQn = 125, /*!< ACE post processing engine flag 7 interrupt */ + ACE_PPE_Flag8_IRQn = 126, /*!< ACE post processing engine flag 8 interrupt */ + ACE_PPE_Flag9_IRQn = 127, /*!< ACE post processing engine flag 9 interrupt */ + ACE_PPE_Flag10_IRQn = 128, /*!< ACE post processing engine flag 10 interrupt */ + ACE_PPE_Flag11_IRQn = 129, /*!< ACE post processing engine flag 11 interrupt */ + ACE_PPE_Flag12_IRQn = 130, /*!< ACE post processing engine flag 12 interrupt */ + ACE_PPE_Flag13_IRQn = 131, /*!< ACE post processing engine flag 13 interrupt */ + ACE_PPE_Flag14_IRQn = 132, /*!< ACE post processing engine flag 14 interrupt */ + ACE_PPE_Flag15_IRQn = 133, /*!< ACE post processing engine flag 15 interrupt */ + ACE_PPE_Flag16_IRQn = 134, /*!< ACE post processing engine flag 16 interrupt */ + ACE_PPE_Flag17_IRQn = 135, /*!< ACE post processing engine flag 17 interrupt */ + ACE_PPE_Flag18_IRQn = 136, /*!< ACE post processing engine flag 18 interrupt */ + ACE_PPE_Flag19_IRQn = 137, /*!< ACE post processing engine flag 19 interrupt */ + ACE_PPE_Flag20_IRQn = 138, /*!< ACE post processing engine flag 20 interrupt */ + ACE_PPE_Flag21_IRQn = 139, /*!< ACE post processing engine flag 21 interrupt */ + ACE_PPE_Flag22_IRQn = 140, /*!< ACE post processing engine flag 22 interrupt */ + ACE_PPE_Flag23_IRQn = 141, /*!< ACE post processing engine flag 23 interrupt */ + ACE_PPE_Flag24_IRQn = 142, /*!< ACE post processing engine flag 24 interrupt */ + ACE_PPE_Flag25_IRQn = 143, /*!< ACE post processing engine flag 25 interrupt */ + ACE_PPE_Flag26_IRQn = 144, /*!< ACE post processing engine flag 26 interrupt */ + ACE_PPE_Flag27_IRQn = 145, /*!< ACE post processing engine flag 27 interrupt */ + ACE_PPE_Flag28_IRQn = 146, /*!< ACE post processing engine flag 28 interrupt */ + ACE_PPE_Flag29_IRQn = 147, /*!< ACE post processing engine flag 29 interrupt */ + ACE_PPE_Flag30_IRQn = 148, /*!< ACE post processing engine flag 30 interrupt */ + ACE_PPE_Flag31_IRQn = 149 /*!< ACE post processing engine flag 31 interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< SmartFusion includes a MPU */ +#define __NVIC_PRIO_BITS 5 /*!< SmartFusion uses 5 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_a2fxxxm3.h" /* SmartFusion System */ + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +#if defined ( __CC_ARM ) + /* Enable anonymous unions when building using Keil-MDK */ + #pragma anon_unions +#endif +/*----------------------------------------------------------------------------*/ +/*----------------------------------- UART -----------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + union + { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLR; + uint32_t RESERVED0; + }; + + union + { + __IO uint8_t DMR; + __IO uint8_t IER; + uint32_t RESERVED1; + }; + + union + { + __IO uint8_t IIR; + __IO uint8_t FCR; + uint32_t RESERVED2; + }; + + __IO uint8_t LCR; + uint8_t RESERVED3; + uint16_t RESERVED4; + __IO uint8_t MCR; + uint8_t RESERVED5; + uint16_t RESERVED6; + __I uint8_t LSR; + uint8_t RESERVED7; + uint16_t RESERVED8; + __I uint8_t MSR; + uint8_t RESERVED9; + uint16_t RESERVED10; + __IO uint8_t SR; + uint8_t RESERVED11; + uint16_t RESERVED12; +} UART_TypeDef; + +/*------------------------------------------------------------------------------ + * + */ +typedef struct +{ + uint32_t RESERVED0[32]; + + __IO uint32_t IER_ERBFI; + __IO uint32_t IER_ETBEI; + __IO uint32_t IER_ELSI; + __IO uint32_t IER_EDSSI; + + uint32_t RESERVED1[28]; + + __IO uint32_t FCR_ENABLE; + __IO uint32_t FCR_CLEAR_RX_FIFO; + __IO uint32_t FCR_CLEAR_TX_FIFO; + __IO uint32_t FCR_RXRDY_TXRDYN_EN; + __IO uint32_t FCR_RESERVED0; + __IO uint32_t FCR_RESERVED1; + __IO uint32_t FCR_RX_TRIG0; + __IO uint32_t FCR_RX_TRIG1; + + uint32_t RESERVED2[24]; + + __IO uint32_t LCR_WLS0; + __IO uint32_t LCR_WLS1; + __IO uint32_t LCR_STB; + __IO uint32_t LCR_PEN; + __IO uint32_t LCR_EPS; + __IO uint32_t LCR_SP; + __IO uint32_t LCR_SB; + __IO uint32_t LCR_DLAB; + + uint32_t RESERVED3[24]; + + __IO uint32_t MCR_DTR; + __IO uint32_t MCR_RTS; + __IO uint32_t MCR_OUT1; + __IO uint32_t MCR_OUT2; + __IO uint32_t MCR_LOOP; + + uint32_t RESERVED4[27]; + + __I uint32_t LSR_DR; + __I uint32_t LSR_OE; + __I uint32_t LSR_PE; + __I uint32_t LSR_FE; + __I uint32_t LSR_BI; + __I uint32_t LSR_THRE; + __I uint32_t LSR_TEMT; + __I uint32_t LSR_FIER; + + uint32_t RESERVED5[24]; + + __I uint32_t MSR_DCTS; + __I uint32_t MSR_DDSR; + __I uint32_t MSR_TERI; + __I uint32_t MSR_DDCD; + __I uint32_t MSR_CTS; + __I uint32_t MSR_DSR; + __I uint32_t MSR_RI; + __I uint32_t MSR_DCD; + +} UART_BitBand_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*----------------------------------- I2C ------------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint8_t CTRL; + uint8_t RESERVED0; + uint16_t RESERVED1; + uint8_t STATUS; + uint8_t RESERVED2; + uint16_t RESERVED3; + __IO uint8_t DATA; + uint8_t RESERVED4; + uint16_t RESERVED5; + __IO uint8_t ADDR; + uint8_t RESERVED6; + uint16_t RESERVED7; + __IO uint8_t SMBUS; + uint8_t RESERVED8; + uint16_t RESERVED9; + __IO uint8_t FREQ; + uint8_t RESERVED10; + uint16_t RESERVED11; + __IO uint8_t GLITCHREG; + uint8_t RESERVED12; + uint16_t RESERVED13; +} I2C_TypeDef; + +/*------------------------------------------------------------------------------ + * + */ +typedef struct +{ + uint32_t CTRL_CR0; + uint32_t CTRL_CR1; + uint32_t CTRL_AA; + uint32_t CTRL_SI; + uint32_t CTRL_STO; + uint32_t CTRL_STA; + uint32_t CTRL_ENS1; + uint32_t CTRL_CR2; + uint32_t RESERVED0[56]; + uint32_t DATA_DIR; + uint32_t RESERVED1[31]; + uint32_t ADDR_GC; +} I2C_BitBand_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*----------------------------------- SPI ------------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t CONTROL; + __IO uint32_t TXRXDF_SIZE; + __I uint32_t STATUS; + __O uint32_t INT_CLEAR; + __I uint32_t RX_DATA; + __O uint32_t TX_DATA; + __IO uint32_t CLK_GEN; + __IO uint32_t SLAVE_SELECT; + __I uint32_t MIS; + __I uint32_t RIS; +} SPI_TypeDef; + +typedef struct +{ + __IO uint32_t CTRL_ENABLE; + __IO uint32_t CTRL_MASTER; + __IO uint32_t CTRL_MODE[2]; + __IO uint32_t CTRL_RX_INT_EN; + __IO uint32_t CTRL_TX_INT_EN; + __IO uint32_t CTRL_RX_OVERFLOW_INT_EN; + __IO uint32_t CTRL_TX_UNDERRUN_INT_EN; + __IO uint32_t CTRL_TXRXDFCOUNT[16]; + __IO uint32_t CTRL_SPO; + __IO uint32_t CTRL_SPH; + __IO uint32_t CTRL_RESERVED[6]; + + __IO uint32_t TXRXDF_SIZE[32]; + + __I uint32_t STATUS_TX_DONE; + __I uint32_t STATUS_RX_RDY; + __I uint32_t STATUS_RX_CH_OV; + __I uint32_t STATUS_TX_CH_UV; + __I uint32_t STATUS_RX_FIFO_FULL; + __I uint32_t STATUS_RX_FIFO_FULL_NEXT; + __I uint32_t STATUS_RX_FIFO_EMPTY; + __I uint32_t STATUS_RX_FIFO_EMPTY_NEXT; + __I uint32_t STATUS_TX_FIFO_FULL; + __I uint32_t STATUS_TX_FIFO_FULL_NEXT; + __I uint32_t STATUS_TX_FIFO_EMPTY; + __I uint32_t STATUS_TX_FIFO_EMPTY_NEXT; + __I uint32_t STATUS_RESERVED[20]; + + __O uint32_t INT_CLEAR_TX_DONE; + __O uint32_t INT_CLEAR_RX_RDY; + __O uint32_t INT_CLEAR_RX_OVER; + __O uint32_t INT_CLEAR_TX_UNDER; + __O uint32_t INT_CLEAR[28]; + + __I uint32_t RX_DATA[32]; + __O uint32_t TX_DATA[32]; + __IO uint32_t CLK_GEN[32]; + __IO uint32_t SLAVE_SELECT[32]; + __I uint32_t MIS_TX_DONE; + __I uint32_t MIS_RX_RDY; + __I uint32_t MIS_RX_OVER; + __I uint32_t MIS_TX_UNDER; + __I uint32_t MIS[28]; + __I uint32_t RIS[32]; +} SPI_BitBand_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*----------------------------------- GPIO -----------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t GPIO_0_CFG; + __IO uint32_t GPIO_1_CFG; + __IO uint32_t GPIO_2_CFG; + __IO uint32_t GPIO_3_CFG; + __IO uint32_t GPIO_4_CFG; + __IO uint32_t GPIO_5_CFG; + __IO uint32_t GPIO_6_CFG; + __IO uint32_t GPIO_7_CFG; + __IO uint32_t GPIO_8_CFG; + __IO uint32_t GPIO_9_CFG; + __IO uint32_t GPIO_10_CFG; + __IO uint32_t GPIO_11_CFG; + __IO uint32_t GPIO_12_CFG; + __IO uint32_t GPIO_13_CFG; + __IO uint32_t GPIO_14_CFG; + __IO uint32_t GPIO_15_CFG; + __IO uint32_t GPIO_16_CFG; + __IO uint32_t GPIO_17_CFG; + __IO uint32_t GPIO_18_CFG; + __IO uint32_t GPIO_19_CFG; + __IO uint32_t GPIO_20_CFG; + __IO uint32_t GPIO_21_CFG; + __IO uint32_t GPIO_22_CFG; + __IO uint32_t GPIO_23_CFG; + __IO uint32_t GPIO_24_CFG; + __IO uint32_t GPIO_25_CFG; + __IO uint32_t GPIO_26_CFG; + __IO uint32_t GPIO_27_CFG; + __IO uint32_t GPIO_28_CFG; + __IO uint32_t GPIO_29_CFG; + __IO uint32_t GPIO_30_CFG; + __IO uint32_t GPIO_31_CFG; + __IO uint32_t GPIO_IRQ; + __I uint32_t GPIO_IN; + __IO uint32_t GPIO_OUT; +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t GPIO_0_CFG[32]; + __IO uint32_t GPIO_1_CFG[32]; + __IO uint32_t GPIO_2_CFG[32]; + __IO uint32_t GPIO_3_CFG[32]; + __IO uint32_t GPIO_4_CFG[32]; + __IO uint32_t GPIO_5_CFG[32]; + __IO uint32_t GPIO_6_CFG[32]; + __IO uint32_t GPIO_7_CFG[32]; + __IO uint32_t GPIO_8_CFG[32]; + __IO uint32_t GPIO_9_CFG[32]; + __IO uint32_t GPIO_10_CFG[32]; + __IO uint32_t GPIO_11_CFG[32]; + __IO uint32_t GPIO_12_CFG[32]; + __IO uint32_t GPIO_13_CFG[32]; + __IO uint32_t GPIO_14_CFG[32]; + __IO uint32_t GPIO_15_CFG[32]; + __IO uint32_t GPIO_16_CFG[32]; + __IO uint32_t GPIO_17_CFG[32]; + __IO uint32_t GPIO_18_CFG[32]; + __IO uint32_t GPIO_19_CFG[32]; + __IO uint32_t GPIO_20_CFG[32]; + __IO uint32_t GPIO_21_CFG[32]; + __IO uint32_t GPIO_22_CFG[32]; + __IO uint32_t GPIO_23_CFG[32]; + __IO uint32_t GPIO_24_CFG[32]; + __IO uint32_t GPIO_25_CFG[32]; + __IO uint32_t GPIO_26_CFG[32]; + __IO uint32_t GPIO_27_CFG[32]; + __IO uint32_t GPIO_28_CFG[32]; + __IO uint32_t GPIO_29_CFG[32]; + __IO uint32_t GPIO_30_CFG[32]; + __IO uint32_t GPIO_31_CFG[32]; + __IO uint32_t GPIO_IRQ[32]; + __I uint32_t GPIO_IN[32]; + __IO uint32_t GPIO_OUT[32]; +} GPIO_BitBand_TypeDef; + + +/*----------------------------------------------------------------------------*/ +/*----------------------------------- RTC ------------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t COUNTER0_REG; + __IO uint32_t COUNTER1_REG; + __IO uint32_t COUNTER2_REG; + __IO uint32_t COUNTER3_REG; + __IO uint32_t COUNTER4_REG; + + __IO uint32_t RESERVED0[3]; + + __IO uint32_t MATCHREG0_REG; + __IO uint32_t MATCHREG1_REG; + __IO uint32_t MATCHREG2_REG; + __IO uint32_t MATCHREG3_REG; + __IO uint32_t MATCHREG4_REG; + + __IO uint32_t RESERVED1[3]; + + __IO uint32_t MATCHBITS0_REG; + __IO uint32_t MATCHBITS1_REG; + __IO uint32_t MATCHBITS2_REG; + __IO uint32_t MATCHBITS3_REG; + __IO uint32_t MATCHBITS4_REG; + + __IO uint32_t RESERVED2[3]; + + __IO uint32_t CTRL_STAT_REG; +} RTC_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*---------------------------------- Timer -----------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __I uint32_t TIM1_VAL; + __IO uint32_t TIM1_LOADVAL; + __IO uint32_t TIM1_BGLOADVAL; + __IO uint32_t TIM1_CTRL; + __IO uint32_t TIM1_RIS; + __I uint32_t TIM1_MIS; + + __I uint32_t TIM2_VAL; + __IO uint32_t TIM2_LOADVAL; + __IO uint32_t TIM2_BGLOADVAL; + __IO uint32_t TIM2_CTRL; + __IO uint32_t TIM2_RIS; + __I uint32_t TIM2_MIS; + + __I uint32_t TIM64_VAL_U; + __I uint32_t TIM64_VAL_L; + __IO uint32_t TIM64_LOADVAL_U; + __IO uint32_t TIM64_LOADVAL_L; + __IO uint32_t TIM64_BGLOADVAL_U; + __IO uint32_t TIM64_BGLOADVAL_L; + __IO uint32_t TIM64_CTRL; + __IO uint32_t TIM64_RIS; + __I uint32_t TIM64_MIS; + __IO uint32_t TIM64_MODE; +} TIMER_TypeDef; + +/*------------------------------------------------------------------------------ + * Timer bit band + */ +typedef struct +{ + __I uint32_t TIM1_VALUE_BIT[32]; + __IO uint32_t TIM1_LOADVAL[32]; + __IO uint32_t TIM1_BGLOADVAL[32]; + + __IO uint32_t TIM1ENABLE; + __IO uint32_t TIM1MODE; + __IO uint32_t TIM1INTEN; + __IO uint32_t TIM1_CTRL_RESERVED[29]; + __IO uint32_t TIM1_RIS[32]; + __I uint32_t TIM1_MIS[32]; + + __I uint32_t TIM2_VALUE[32]; + __IO uint32_t TIM2_LOADVAL[32]; + __IO uint32_t TIM2_BGLOADVAL[32]; + + __IO uint32_t TIM2ENABLE; + __IO uint32_t TIM2MODE; + __IO uint32_t TIM2INTEN; + __IO uint32_t TIM2_CTRL[29]; + __IO uint32_t TIM2_RIS[32]; + __I uint32_t TIM2_MIS[32]; + + __I uint32_t TIM64VALUEU[32]; + __I uint32_t TIM64VALUEL[32]; + __IO uint32_t TIM64LOADVALUEU[32]; + __IO uint32_t TIM64LOADVALUEL[32]; + __IO uint32_t TIM64BGLOADVALUEU[32]; + __IO uint32_t TIM64BGLOADVALUEL[32]; + __IO uint32_t TIM64ENABLE; + __IO uint32_t TIM64MODE; + __IO uint32_t TIM64INTEN; + __IO uint32_t TIM64_CTRL[29]; + __IO uint32_t TIM64_RIS[32]; + __I uint32_t TIM64_MIS[32]; + __IO uint32_t TIM64_MODE[32]; +} TIMER_BitBand_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*--------------------------------- Watchdog ---------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __I uint32_t WDOGVALUE; + __IO uint32_t WDOGLOAD; + __IO uint32_t WDOGMVRP; + __O uint32_t WDOGREFRESH; + __IO uint32_t WDOGENABLE; + __IO uint32_t WDOGCONTROL; + __I uint32_t WDOGSTATUS; + __IO uint32_t WDOGRIS; + __I uint32_t WDOGMIS; +} WATCHDOG_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Real Time Clock ------------------------------*/ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Peripherals DMA ------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t CRTL; + __IO uint32_t STATUS; + __IO uint32_t BUFFER_A_SRC_ADDR; + __IO uint32_t BUFFER_A_DEST_ADDR; + __IO uint32_t BUFFER_A_TRANSFER_COUNT; + __IO uint32_t BUFFER_B_SRC_ADDR; + __IO uint32_t BUFFER_B_DEST_ADDR; + __IO uint32_t BUFFER_B_TRANSFER_COUNT; +} PDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t RATIO_HIGH_LOW; + __IO uint32_t BUFFER_STATUS; + uint32_t RESERVED[6]; + PDMA_Channel_TypeDef CHANNEL[8]; +} PDMA_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*------------------------------ Ethernet MAC --------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t CSR0; + uint32_t RESERVED0; + __IO uint32_t CSR1; + uint32_t RESERVED1; + __IO uint32_t CSR2; + uint32_t RESERVED2; + __IO uint32_t CSR3; + uint32_t RESERVED3; + __IO uint32_t CSR4; + uint32_t RESERVED4; + __IO uint32_t CSR5; + uint32_t RESERVED5; + __IO uint32_t CSR6; + uint32_t RESERVED6; + __IO uint32_t CSR7; + uint32_t RESERVED7; + __IO uint32_t CSR8; + uint32_t RESERVED8; + __IO uint32_t CSR9; + uint32_t RESERVED9; + uint32_t RESERVED10; + uint32_t RESERVED11; + __IO uint32_t CSR11; +} MAC_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*---------------------- Analog Conversion Engine (ACE) ----------------------*/ +/*----------------------------------------------------------------------------*/ +/* Analog quad configuration */ +typedef struct +{ + __IO uint8_t b0; + uint8_t reserved0_0; + uint16_t reserved0_1; + __IO uint8_t b1; + uint8_t reserved1_0; + uint16_t reserved1_1; + __IO uint8_t b2; + uint8_t reserved2_0; + uint16_t reserved2_1; + __IO uint8_t b3; + uint8_t reserved3_0; + uint16_t reserved3_1; + __IO uint8_t b4; + uint8_t reserved4_0; + uint16_t reserved4_1; + __IO uint8_t b5; + uint8_t reserved5_0; + uint16_t reserved5_1; + __IO uint8_t b6; + uint8_t reserved6_0; + uint16_t reserved6_1; + __IO uint8_t b7; + uint8_t reserved7_0; + uint16_t reserved7_1; + __IO uint8_t b8; + uint8_t reserved8_0; + uint16_t reserved8_1; + __IO uint8_t b9; + uint8_t reserved9_0; + uint16_t reserved9_1; + __IO uint8_t b10; + uint8_t reserved10_0; + uint16_t reserved10_1; + __IO uint8_t b11; + uint8_t reserved11_0; + uint16_t reserved11_1; +} AQ_config_t; + +/* ACE memory map layout */ +typedef struct +{ + __O uint32_t NOP; + __IO uint32_t SSE_TS_CTRL; + __IO uint32_t ADC_SYNC_CONV; + __IO uint32_t ANA_COMM_CTRL; + __IO uint32_t DAC_SYNC_CTRL; + __IO uint32_t PDMA_REQUEST; + uint32_t RESERVED0[10]; + __O uint32_t PC0_LO; + __O uint32_t PC0_HI; + __IO uint32_t PC0_CTRL; + __IO uint32_t PC0_DLY; + __IO uint32_t ADC0_CONV_CTRL; + __IO uint32_t ADC0_STC; + __IO uint32_t ADC0_TVC; + __IO uint32_t ADC0_MISC_CTRL; + __IO uint32_t DAC0_CTRL; + __IO uint32_t DAC0_BYTE0; + __IO uint32_t DAC0_BYTE1; + __IO uint32_t DAC0_BYTE2; + __IO uint32_t LC0; + __O uint32_t LC0_JMP_LO; + __O uint32_t LC0_JMP_HI; + __O uint32_t PC0_FLAGS; + __O uint32_t PC1_LO; + __O uint32_t PC1_HI; + __IO uint32_t PC1_CTRL; + __IO uint32_t PC1_DLY; + __IO uint32_t ADC1_CONV_CTRL; + __IO uint32_t ADC1_STC; + __IO uint32_t ADC1_TVC; + __IO uint32_t ADC1_MISC_CTRL; + __IO uint32_t DAC1_CTRL; + __IO uint32_t DAC1_BYTE0; + __IO uint32_t DAC1_BYTE1; + __IO uint32_t DAC1_BYTE2; + __IO uint32_t LC1; + __O uint32_t LC1_JMP_LO; + __O uint32_t LC1_JMP_HI; + __O uint32_t PC1_FLAGS; + __O uint32_t PC2_LO; + __O uint32_t PC2_HI; + __IO uint32_t PC2_CTRL; + __IO uint32_t PC2_DLY; + __IO uint32_t ADC2_CONV_CTRL; + __IO uint32_t ADC2_STC; + __IO uint32_t ADC2_TVC; + __IO uint32_t ADC2_MISC_CTRL; + __IO uint32_t DAC2_CTRL; + __IO uint32_t DAC2_BYTE0; + __IO uint32_t DAC2_BYTE1; + __IO uint32_t DAC2_BYTE2; + __IO uint32_t LC2; + __O uint32_t LC2_JMP_LO; + __O uint32_t LC2_JMP_HI; + __O uint32_t PC2_FLAGS; + uint32_t RESERVED1; + uint32_t RESERVED2; + __IO uint32_t SSE_RAM_LO_IDATA; + __IO uint32_t SSE_RAM_HI_IDATA; + uint32_t RESERVED3[61]; + AQ_config_t ACB_DATA[6]; + uint32_t RESERVED4[59]; + __IO uint32_t SSE_PC0; + __IO uint32_t SSE_PC1; + __IO uint32_t SSE_PC2; + uint32_t RESERVED5[57]; + __IO uint32_t SSE_DAC0_BYTES01; + __IO uint32_t SSE_DAC1_BYTES01; + __IO uint32_t SSE_DAC2_BYTES01; + uint32_t RESERVED6[61]; + __O uint32_t SSE_ADC0_RESULTS; + __O uint32_t SSE_ADC1_RESULTS; + __O uint32_t SSE_ADC2_RESULTS; + uint32_t RESERVED7[61]; + __O uint32_t SSE_PDMA_DATAIN; + uint32_t RESERVED8[63]; + __IO uint32_t SSE_RAM_DATA[512]; + __I uint32_t ADC0_STATUS; + __I uint32_t ADC1_STATUS; + __I uint32_t ADC2_STATUS; + __I uint32_t COMPARATOR_STATUS; + uint32_t RESERVED9[124]; + __IO uint32_t SSE_IRQ_EN; + __I uint32_t SSE_IRQ; + __O uint32_t SSE_IRQ_CLR; + __IO uint32_t COMP_IRQ_EN; + __I uint32_t COMP_IRQ; + __O uint32_t COMP_IRQ_CLR; + __IO uint32_t PPE_FIFO_IRQ_EN; + __I uint32_t PPE_FIFO_IRQ; + __O uint32_t PPE_FIFO_IRQ_CLR; + __IO uint32_t PPE_FLAGS0_IRQ_EN; + __I uint32_t PPE_FLAGS0_IRQ; + __O uint32_t PPE_FLAGS0_IRQ_CLR; + __IO uint32_t PPE_FLAGS1_IRQ_EN; + __I uint32_t PPE_FLAGS1_IRQ; + __O uint32_t PPE_FLAGS1_IRQ_CLR; + __IO uint32_t PPE_FLAGS2_IRQ_EN; + __I uint32_t PPE_FLAGS2_IRQ; + __O uint32_t PPE_FLAGS2_IRQ_CLR; + __IO uint32_t PPE_FLAGS3_IRQ_EN; + __I uint32_t PPE_FLAGS3_IRQ; + __O uint32_t PPE_FLAGS3_IRQ_CLR; + __IO uint32_t PPE_SFFLAGS_IRQ_EN; + __I uint32_t PPE_SFFLAGS_IRQ; + __O uint32_t PPE_SFFLAGS_IRQ_CLR; + __IO uint32_t FPGA_FLAGS_SEL; + uint32_t RESERVED10[39]; + __IO uint32_t PPE_PDMA_CTRL; + __I uint32_t PDMA_STATUS; + __IO uint32_t PPE_PDMA_DATAOUT; + uint32_t RESERVED11[61]; + __I uint32_t PPE_NOP; + __IO uint32_t PPE_CTRL; + __IO uint32_t PPE_PC_ETC; + __IO uint32_t PPE_SF; + __IO uint32_t PPE_SCRATCH; + uint32_t RESERVED12; + __IO uint32_t ALU_CTRL; + __I uint32_t ALU_STATUS; + __IO uint32_t ALU_A; + uint32_t RESERVED50; + __IO uint32_t ALU_B; + uint32_t RESERVED53; + __IO uint32_t ALU_C; + uint32_t RESERVED51; + __IO uint32_t ALU_D; + uint32_t RESERVED52; + __IO uint32_t ALU_E; + uint32_t RESERVED54; + __IO uint32_t PPE_FPTR; + uint32_t RESERVED55; + __IO uint32_t PPE_FLAGS0; + __IO uint32_t PPE_FLAGS1; + __IO uint32_t PPE_FLAGS2; + __IO uint32_t PPE_FLAGS3; + __IO uint32_t PPE_SFFLAGS; + uint32_t RESERVED13[11]; + __IO uint32_t ADC0_FIFO_CTRL; + __I uint32_t ADC0_FIFO_STATUS; + __IO uint32_t ADC0_FIFO_DATA; + __IO uint32_t ADC1_FIFO_CTRL; + __I uint32_t ADC1_FIFO_STATUS; + __IO uint32_t ADC1_FIFO_DATA; + __IO uint32_t ADC2_FIFO_CTRL; + __I uint32_t ADC2_FIFO_STATUS; + __IO uint32_t ADC2_FIFO_DATA; + uint32_t RESERVED14[19]; + __I uint32_t ADC0_FIFO_DATA_PEEK; + __I uint32_t ADC0_FIFO_DATA0; + __I uint32_t ADC0_FIFO_DATA1; + __I uint32_t ADC0_FIFO_DATA2; + __I uint32_t ADC0_FIFO_DATA3; + __I uint32_t ADC1_FIFO_DATA_PEEK; + __I uint32_t ADC1_FIFO_DATA0; + __I uint32_t ADC1_FIFO_DATA1; + __I uint32_t ADC1_FIFO_DATA2; + __I uint32_t ADC1_FIFO_DATA3; + __I uint32_t ADC2_FIFO_DATA_PEEK; + __I uint32_t ADC2_FIFO_DATA0; + __I uint32_t ADC2_FIFO_DATA1; + __I uint32_t ADC2_FIFO_DATA2; + __I uint32_t ADC2_FIFO_DATA3; + uint32_t RESERVED15[177]; + __IO uint32_t PPE_RAM_DATA[512]; +} ACE_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*------------------------ In Application Programming ------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IAP_IR; + __IO uint32_t IAP_DR2; + __IO uint32_t IAP_DR3; + __IO uint32_t IAP_DR5; + __IO uint32_t IAP_DR26; + __IO uint32_t IAP_DR32; + __IO uint32_t IAP_DR; + __IO uint32_t IAP_DR_LENGTH; + __IO uint32_t IAP_TAP_NEW_STATE; + __IO uint32_t IAP_TAP_CONTROL; + __I uint32_t IAP_STATUS; +} IAP_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*---------------------- eNVM Special Function Registers ---------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t STATUS; + __IO uint32_t CONTROL; + __IO uint32_t ENABLE; + uint32_t RESERVED0; + __IO uint32_t CONFIG_0; + __IO uint32_t CONFIG_1; + __IO uint32_t PAGE_STATUS_0; + __IO uint32_t PAGE_STATUS_1; + __IO uint32_t SEGMENT; + __IO uint32_t ENVM_SELECT; +} NVM_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*---------------------- eNVM Special Function Registers ---------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t MSSIRQ_EN0; + __IO uint32_t MSSIRQ_EN1; + __IO uint32_t MSSIRQ_EN2; + __IO uint32_t MSSIRQ_EN3; + __IO uint32_t MSSIRQ_EN4; + __IO uint32_t MSSIRQ_EN5; + __IO uint32_t MSSIRQ_EN6; + __IO uint32_t MSSIRQ_EN7; + __I uint32_t MSSIRQ_SRC0; + __I uint32_t MSSIRQ_SRC1; + __I uint32_t MSSIRQ_SRC2; + __I uint32_t MSSIRQ_SRC3; + __I uint32_t MSSIRQ_SRC4; + __I uint32_t MSSIRQ_SRC5; + __I uint32_t MSSIRQ_SRC6; + __I uint32_t MSSIRQ_SRC7; + __IO uint32_t FIIC_MR; +} MSS_IRQ_CTRL_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*------------------------------ System Registers ----------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t ESRAM_CR; + __IO uint32_t ENVM_CR; + __IO uint32_t ENVM_REMAP_SYS_CR; + __IO uint32_t ENVM_REMAP_FAB_CR; + __IO uint32_t FAB_PROT_SIZE_CR; + __IO uint32_t FAB_PROT_BASE_CR; + __IO uint32_t AHB_MATRIX_CR; + __IO uint32_t MSS_SR; + __IO uint32_t CLR_MSS_SR; + __IO uint32_t EFROM_CR; + __IO uint32_t IAP_CR; + __IO uint32_t SOFT_IRQ_CR; + __IO uint32_t SOFT_RST_CR; + __IO uint32_t DEVICE_SR; + __IO uint32_t SYSTICK_CR; + __IO uint32_t EMC_MUX_CR; + __IO uint32_t EMC_CS_0_CR; + __IO uint32_t EMC_CS_1_CR; + __IO uint32_t MSS_CLK_CR; + __IO uint32_t MSS_CCC_DIV_CR; + __IO uint32_t MSS_CCC_MUX_CR; + __IO uint32_t MSS_CCC_PLL_CR; + __IO uint32_t MSS_CCC_DLY_CR; + __IO uint32_t MSS_CCC_SR; + __IO uint32_t MSS_RCOSC_CR; + __IO uint32_t VRPSM_CR; + __IO uint32_t RESERVED; + __IO uint32_t FAB_IF_CR; + __IO uint32_t FAB_APB_HIWORD_DR; + __IO uint32_t LOOPBACK_CR; + __IO uint32_t MSS_IO_BANK_CR; + __IO uint32_t GPIN_SOURCE_CR; + __IO uint32_t TEST_SR; + __IO uint32_t RED_REP_ADDR0; + __I uint32_t RED_REP_LOW_LOCS0; + __I uint32_t RED_REP_HIGH_LOCS0; + __IO uint32_t RED_REP_ADDR1; + __I uint32_t RED_REP_LOW_LOCS1; + __I uint32_t RED_REP_HIGH_LOCS1; + __IO uint32_t FABRIC_CR; + uint32_t RESERVED1[24]; + __IO uint32_t IOMUX_CR[83]; +} SYSREG_TypeDef; + +#define SYSREG_ENVM_SOFTRESET_MASK (uint32_t)0x00000001 +#define SYSREG_ESRAM0_SOFTRESET_MASK (uint32_t)0x00000002 +#define SYSREG_ESRAM1_SOFTRESET_MASK (uint32_t)0x00000004 +#define SYSREG_EMC_SOFTRESET_MASK (uint32_t)0x00000008 +#define SYSREG_MAC_SOFTRESET_MASK (uint32_t)0x00000010 +#define SYSREG_PDMA_SOFTRESET_MASK (uint32_t)0x00000020 +#define SYSREG_TIMER_SOFTRESET_MASK (uint32_t)0x00000040 +#define SYSREG_UART0_SOFTRESET_MASK (uint32_t)0x00000080 +#define SYSREG_UART1_SOFTRESET_MASK (uint32_t)0x00000100 +#define SYSREG_SPI0_SOFTRESET_MASK (uint32_t)0x00000200 +#define SYSREG_SPI1_SOFTRESET_MASK (uint32_t)0x00000400 +#define SYSREG_I2C0_SOFTRESET_MASK (uint32_t)0x00000800 +#define SYSREG_I2C1_SOFTRESET_MASK (uint32_t)0x00001000 +#define SYSREG_ACE_SOFTRESET_MASK (uint32_t)0x00002000 +#define SYSREG_GPIO_SOFTRESET_MASK (uint32_t)0x00004000 +#define SYSREG_IAP_SOFTRESET_MASK (uint32_t)0x00008000 +#define SYSREG_EXT_SOFTRESET_MASK (uint32_t)0x00010000 +#define SYSREG_FPGA_SOFTRESET_MASK (uint32_t)0x00020000 +#define SYSREG_F2M_RESET_ENABLE_MASK (uint32_t)0x00040000 +#define SYSREG_PADRESET_ENABLE_MASK (uint32_t)0x00080000 + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +#define UART0_BASE 0x40000000U +#define SPI0_BASE 0x40001000U +#define I2C0_BASE 0x40002000U +#define MAC_BASE 0x40003000U +#define PDMA_BASE 0x40004000U +#define TIMER_BASE 0x40005000U +#define WATCHDOG_BASE 0x40006000U +#define H2F_IRQ_CTRL_BASE 0x40007000U +#define UART1_BASE 0x40010000U +#define SPI1_BASE 0x40011000U +#define I2C1_BASE 0x40012000U +#define GPIO_BASE 0x40013000U +#define RTC_BASE 0x40014100U +#define FROM_BASE 0x40015000U +#define IAP_BASE 0x40016000U +#define ACE_BASE 0x40020000U +#define FPGA_FABRIC_RAM_BASE 0x40040000U +#define FPGA_FABRIC_BASE 0x40050000U +#define ENVM_BASE 0x60000000U +#define ENVM_REGS_BASE 0x60100000U +#define SYSREG_BASE 0xE0042000U + +/******************************************************************************/ +/* bitband address calcualtion macro */ +/******************************************************************************/ +#define BITBAND_ADDRESS(X) ((X & 0xF0000000U) + 0x02000000U + ((X & 0xFFFFFU) << 5)) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART0_BITBAND ((UART_BitBand_TypeDef *) BITBAND_ADDRESS(UART0_BASE)) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI0_BITBAND ((SPI_BitBand_TypeDef *) BITBAND_ADDRESS(SPI0_BASE)) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C0_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C0_BASE)) +#define MAC ((MAC_TypeDef *) MAC_BASE) +#define PDMA ((PDMA_TypeDef *) PDMA_BASE) +#define TIMER ((TIMER_TypeDef *) TIMER_BASE) +#define TIMER_BITBAND ((TIMER_BitBand_TypeDef *) BITBAND_ADDRESS(TIMER_BASE)) +#define WATCHDOG ((WATCHDOG_TypeDef *) WATCHDOG_BASE) +#define MSS_IRQ_CTRL ((MSS_IRQ_CTRL_TypeDef *) H2F_IRQ_CTRL_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART1_BITBAND ((UART_BitBand_TypeDef *) BITBAND_ADDRESS(UART1_BASE)) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI1_BITBAND ((SPI_BitBand_TypeDef *) BITBAND_ADDRESS(SPI1_BASE)) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C1_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C1_BASE)) +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) +#define GPIO_BITBAND ((GPIO_BitBand_TypeDef *) BITBAND_ADDRESS(GPIO_BASE)) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define FROM ((void *) FROM_BASE) +#define IAP ((IAP_TypeDef *) IAP_BASE) +#define ACE ((ACE_TypeDef *) ACE_BASE) +#define FPGA_FABRIC_RAM ((void *) FPGA_FABRIC_RAM_BASE) +#define FPGA_FABRIC ((void *) FPGA_FABRIC_BASE) +#define ENVM ((void *) ENVM_BASE) +#define ENVM_REGS ((NVM_TypeDef *) ENVM_REGS_BASE) +#define SYSREG ((SYSREG_TypeDef *) SYSREG_BASE) + +#ifdef __cplusplus +} +#endif + +#endif /* __A2FXXXM3_H__ */ + diff --git a/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/core_cm3.c b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/core_cm3.c new file mode 100644 index 000000000..56fddc52b --- /dev/null +++ b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/core_cm3.c @@ -0,0 +1,784 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/core_cm3.h b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/core_cm3.h new file mode 100644 index 000000000..e0565d7d4 --- /dev/null +++ b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP(void) { __ASM volatile ("nop"); } +static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } +static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } +static __INLINE void __SEV(void) { __ASM volatile ("sev"); } +static __INLINE void __ISB(void) { __ASM volatile ("isb"); } +static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } +static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } +static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/mss_assert.h b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/mss_assert.h new file mode 100644 index 000000000..4725d2132 --- /dev/null +++ b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/mss_assert.h @@ -0,0 +1,48 @@ +/******************************************************************************* + * (c) Copyright 2009 Actel Corporation. All rights reserved. + * + * Assertion implementation. + * + * This file provides the implementation of the ASSERT macro. This file can be + * modified to cater for project specific requirements regarding the way + * assertions are handled. + * + * SVN $Revision: 1676 $ + * SVN $Date: 2009-12-02 16:47:03 +0000 (Wed, 02 Dec 2009) $ + */ +#ifndef __MSS_ASSERT_H_ +#define __MSS_ASSERT_H_ + +#include + +#if defined ( __GNUC__ ) + +#if defined(NDEBUG) + +#define ASSERT(CHECK) + +#else /* NDEBUG */ +/* + * SoftConsole assertion handling + */ +#define ASSERT(CHECK) \ + do { \ + if (!(CHECK)) \ + { \ + __asm volatile ("BKPT\n\t"); \ + } \ + } while (0); + +#endif /* NDEBUG */ + +#else +/* + * IAR Embedded Workbench or Keil assertion handling. + * Call C library assert function which should result in error message + * displayed in debugger. + */ +#define ASSERT(X) assert(X) + +#endif + +#endif /* __MSS_ASSERT_H_ */ diff --git a/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/startup_iar/startup_a2fxxxm3.s b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/startup_iar/startup_a2fxxxm3.s new file mode 100644 index 000000000..0aa80dffa --- /dev/null +++ b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/startup_iar/startup_a2fxxxm3.s @@ -0,0 +1,973 @@ +/******************************************************************************* + * (c) Copyright 2009 Actel Corporation. All rights reserved. + * + * Startup code for SmartFusion A2FM3Fxxx + * + * SVN $Revision: 2068 $ + * SVN $Date: 2010-01-27 17:27:41 +0000 (Wed, 27 Jan 2010) $ + */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start +; EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WdogWakeup_IRQHandler + DCD BrownOut_1_5V_IRQHandler + DCD BrownOut_3_3V_IRQHandler + DCD RTC_Match_IRQHandler + DCD RTCIF_Pub_IRQHandler + DCD EthernetMAC_IRQHandler + DCD IAP_IRQHandler + DCD ENVM0_IRQHandler + DCD ENVM1_IRQHandler + DCD DMA_IRQHandler + DCD UART0_IRQHandler + DCD UART1_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD I2C0_IRQHandler + DCD I2C0_SMBAlert_IRQHandler + DCD I2C0_SMBus_IRQHandler + DCD I2C1_IRQHandler + DCD I2C1_SMBAlert_IRQHandler + DCD I2C1_SMBus_IRQHandler + DCD Timer1_IRQHandler + DCD Timer2_IRQHandler + DCD PLL_Lock_IRQHandler + DCD PLL_LockLost_IRQHandler + DCD CommError_IRQHandler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD Fabric_IRQHandler + DCD GPIO0_IRQHandler + DCD GPIO1_IRQHandler + DCD GPIO2_IRQHandler + DCD GPIO3_IRQHandler + DCD GPIO4_IRQHandler + DCD GPIO5_IRQHandler + DCD GPIO6_IRQHandler + DCD GPIO7_IRQHandler + DCD GPIO8_IRQHandler + DCD GPIO9_IRQHandler + DCD GPIO10_IRQHandler + DCD GPIO11_IRQHandler + DCD GPIO12_IRQHandler + DCD GPIO13_IRQHandler + DCD GPIO14_IRQHandler + DCD GPIO15_IRQHandler + DCD GPIO16_IRQHandler + DCD GPIO17_IRQHandler + DCD GPIO18_IRQHandler + DCD GPIO19_IRQHandler + DCD GPIO20_IRQHandler + DCD GPIO21_IRQHandler + DCD GPIO22_IRQHandler + DCD GPIO23_IRQHandler + DCD GPIO24_IRQHandler + DCD GPIO25_IRQHandler + DCD GPIO26_IRQHandler + DCD GPIO27_IRQHandler + DCD GPIO28_IRQHandler + DCD GPIO29_IRQHandler + DCD GPIO30_IRQHandler + DCD GPIO31_IRQHandler + DCD ACE_PC0_Flag0_IRQHandler + DCD ACE_PC0_Flag1_IRQHandler + DCD ACE_PC0_Flag2_IRQHandler + DCD ACE_PC0_Flag3_IRQHandler + DCD ACE_PC1_Flag0_IRQHandler + DCD ACE_PC1_Flag1_IRQHandler + DCD ACE_PC1_Flag2_IRQHandler + DCD ACE_PC1_Flag3_IRQHandler + DCD ACE_PC2_Flag0_IRQHandler + DCD ACE_PC2_Flag1_IRQHandler + DCD ACE_PC2_Flag2_IRQHandler + DCD ACE_PC2_Flag3_IRQHandler + DCD ACE_ADC0_DataValid_IRQHandler + DCD ACE_ADC1_DataValid_IRQHandler + DCD ACE_ADC2_DataValid_IRQHandler + DCD ACE_ADC0_CalDone_IRQHandler + DCD ACE_ADC1_CalDone_IRQHandler + DCD ACE_ADC2_CalDone_IRQHandler + DCD ACE_ADC0_CalStart_IRQHandler + DCD ACE_ADC1_CalStart_IRQHandler + DCD ACE_ADC2_CalStart_IRQHandler + DCD ACE_Comp0_Fall_IRQHandler + DCD ACE_Comp1_Fall_IRQHandler + DCD ACE_Comp2_Fall_IRQHandler + DCD ACE_Comp3_Fall_IRQHandler + DCD ACE_Comp4_Fall_IRQHandler + DCD ACE_Comp5_Fall_IRQHandler + DCD ACE_Comp6_Fall_IRQHandler + DCD ACE_Comp7_Fall_IRQHandler + DCD ACE_Comp8_Fall_IRQHandler + DCD ACE_Comp9_Fall_IRQHandler + DCD ACE_Comp10_Fall_IRQHandler + DCD ACE_Comp11_Fall_IRQHandler + DCD ACE_Comp0_Rise_IRQHandler + DCD ACE_Comp1_Rise_IRQHandler + DCD ACE_Comp2_Rise_IRQHandler + DCD ACE_Comp3_Rise_IRQHandler + DCD ACE_Comp4_Rise_IRQHandler + DCD ACE_Comp5_Rise_IRQHandler + DCD ACE_Comp6_Rise_IRQHandler + DCD ACE_Comp7_Rise_IRQHandler + DCD ACE_Comp8_Rise_IRQHandler + DCD ACE_Comp9_Rise_IRQHandler + DCD ACE_Comp10_Rise_IRQHandler + DCD ACE_Comp11_Rise_IRQHandler + DCD ACE_ADC0_FifoFull_IRQHandler + DCD ACE_ADC0_FifoAFull_IRQHandler + DCD ACE_ADC0_FifoEmpty_IRQHandler + DCD ACE_ADC1_FifoFull_IRQHandler + DCD ACE_ADC1_FifoAFull_IRQHandler + DCD ACE_ADC1_FifoEmpty_IRQHandler + DCD ACE_ADC2_FifoFull_IRQHandler + DCD ACE_ADC2_FifoAFull_IRQHandler + DCD ACE_ADC2_FifoEmpty_IRQHandler + DCD ACE_PPE_Flag0_IRQHandler + DCD ACE_PPE_Flag1_IRQHandler + DCD ACE_PPE_Flag2_IRQHandler + DCD ACE_PPE_Flag3_IRQHandler + DCD ACE_PPE_Flag4_IRQHandler + DCD ACE_PPE_Flag5_IRQHandler + DCD ACE_PPE_Flag6_IRQHandler + DCD ACE_PPE_Flag7_IRQHandler + DCD ACE_PPE_Flag8_IRQHandler + DCD ACE_PPE_Flag9_IRQHandler + DCD ACE_PPE_Flag10_IRQHandler + DCD ACE_PPE_Flag11_IRQHandler + DCD ACE_PPE_Flag12_IRQHandler + DCD ACE_PPE_Flag13_IRQHandler + DCD ACE_PPE_Flag14_IRQHandler + DCD ACE_PPE_Flag15_IRQHandler + DCD ACE_PPE_Flag16_IRQHandler + DCD ACE_PPE_Flag17_IRQHandler + DCD ACE_PPE_Flag18_IRQHandler + DCD ACE_PPE_Flag19_IRQHandler + DCD ACE_PPE_Flag20_IRQHandler + DCD ACE_PPE_Flag21_IRQHandler + DCD ACE_PPE_Flag22_IRQHandler + DCD ACE_PPE_Flag23_IRQHandler + DCD ACE_PPE_Flag24_IRQHandler + DCD ACE_PPE_Flag25_IRQHandler + DCD ACE_PPE_Flag26_IRQHandler + DCD ACE_PPE_Flag27_IRQHandler + DCD ACE_PPE_Flag28_IRQHandler + DCD ACE_PPE_Flag29_IRQHandler + DCD ACE_PPE_Flag30_IRQHandler + DCD ACE_PPE_Flag31_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler +; LDR R0, =SystemInit +; BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WdogWakeup_IRQHandler + SECTION .text:CODE:REORDER(1) +WdogWakeup_IRQHandler + B WdogWakeup_IRQHandler + + PUBWEAK BrownOut_1_5V_IRQHandler + SECTION .text:CODE:REORDER(1) +BrownOut_1_5V_IRQHandler + B BrownOut_1_5V_IRQHandler + + PUBWEAK BrownOut_3_3V_IRQHandler + SECTION .text:CODE:REORDER(1) +BrownOut_3_3V_IRQHandler + B BrownOut_3_3V_IRQHandler + + PUBWEAK RTC_Match_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Match_IRQHandler + B RTC_Match_IRQHandler + + PUBWEAK RTCIF_Pub_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCIF_Pub_IRQHandler + B RTCIF_Pub_IRQHandler + + PUBWEAK EthernetMAC_IRQHandler + SECTION .text:CODE:REORDER(1) +EthernetMAC_IRQHandler + B EthernetMAC_IRQHandler + + PUBWEAK IAP_IRQHandler + SECTION .text:CODE:REORDER(1) +IAP_IRQHandler + B IAP_IRQHandler + + PUBWEAK ENVM0_IRQHandler + SECTION .text:CODE:REORDER(1) +ENVM0_IRQHandler + B ENVM0_IRQHandler + + PUBWEAK ENVM1_IRQHandler + SECTION .text:CODE:REORDER(1) +ENVM1_IRQHandler + B ENVM1_IRQHandler + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK I2C0_SMBAlert_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C0_SMBAlert_IRQHandler + B I2C0_SMBAlert_IRQHandler + + PUBWEAK I2C0_SMBus_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C0_SMBus_IRQHandler + B I2C0_SMBus_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C1_SMBAlert_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_SMBAlert_IRQHandler + B I2C1_SMBAlert_IRQHandler + + PUBWEAK I2C1_SMBus_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_SMBus_IRQHandler + B I2C1_SMBus_IRQHandler + + PUBWEAK Timer1_IRQHandler + SECTION .text:CODE:REORDER(1) +Timer1_IRQHandler + B Timer1_IRQHandler + + PUBWEAK Timer2_IRQHandler + SECTION .text:CODE:REORDER(1) +Timer2_IRQHandler + B Timer2_IRQHandler + + PUBWEAK PLL_Lock_IRQHandler + SECTION .text:CODE:REORDER(1) +PLL_Lock_IRQHandler + B PLL_Lock_IRQHandler + + PUBWEAK PLL_LockLost_IRQHandler + SECTION .text:CODE:REORDER(1) +PLL_LockLost_IRQHandler + B PLL_LockLost_IRQHandler + + PUBWEAK CommError_IRQHandler + SECTION .text:CODE:REORDER(1) +CommError_IRQHandler + B CommError_IRQHandler + + PUBWEAK Fabric_IRQHandler + SECTION .text:CODE:REORDER(1) +Fabric_IRQHandler + B Fabric_IRQHandler + + PUBWEAK GPIO0_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO0_IRQHandler + B GPIO0_IRQHandler + + PUBWEAK GPIO1_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO1_IRQHandler + B GPIO1_IRQHandler + + PUBWEAK GPIO2_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO2_IRQHandler + B GPIO2_IRQHandler + + PUBWEAK GPIO3_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO3_IRQHandler + B GPIO3_IRQHandler + + PUBWEAK GPIO4_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO4_IRQHandler + B GPIO4_IRQHandler + + PUBWEAK GPIO5_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO5_IRQHandler + B GPIO5_IRQHandler + + PUBWEAK GPIO6_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO6_IRQHandler + B GPIO6_IRQHandler + + PUBWEAK GPIO7_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO7_IRQHandler + B GPIO7_IRQHandler + + PUBWEAK GPIO8_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO8_IRQHandler + B GPIO8_IRQHandler + + PUBWEAK GPIO9_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO9_IRQHandler + B GPIO9_IRQHandler + + PUBWEAK GPIO10_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO10_IRQHandler + B GPIO10_IRQHandler + + PUBWEAK GPIO11_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO11_IRQHandler + B GPIO11_IRQHandler + + PUBWEAK GPIO12_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO12_IRQHandler + B GPIO12_IRQHandler + + PUBWEAK GPIO13_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO13_IRQHandler + B GPIO13_IRQHandler + + PUBWEAK GPIO14_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO14_IRQHandler + B GPIO14_IRQHandler + + PUBWEAK GPIO15_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO15_IRQHandler + B GPIO15_IRQHandler + + PUBWEAK GPIO16_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO16_IRQHandler + B GPIO16_IRQHandler + + PUBWEAK GPIO17_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO17_IRQHandler + B GPIO17_IRQHandler + + PUBWEAK GPIO18_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO18_IRQHandler + B GPIO18_IRQHandler + + PUBWEAK GPIO19_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO19_IRQHandler + B GPIO19_IRQHandler + + PUBWEAK GPIO20_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO20_IRQHandler + B GPIO20_IRQHandler + + PUBWEAK GPIO21_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO21_IRQHandler + B GPIO21_IRQHandler + + PUBWEAK GPIO22_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO22_IRQHandler + B GPIO22_IRQHandler + + PUBWEAK GPIO23_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO23_IRQHandler + B GPIO23_IRQHandler + + PUBWEAK GPIO24_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO24_IRQHandler + B GPIO24_IRQHandler + + PUBWEAK GPIO25_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO25_IRQHandler + B GPIO25_IRQHandler + + PUBWEAK GPIO26_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO26_IRQHandler + B GPIO26_IRQHandler + + PUBWEAK GPIO27_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO27_IRQHandler + B GPIO27_IRQHandler + + PUBWEAK GPIO28_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO28_IRQHandler + B GPIO28_IRQHandler + + PUBWEAK GPIO29_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO29_IRQHandler + B GPIO29_IRQHandler + + PUBWEAK GPIO30_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO30_IRQHandler + B GPIO30_IRQHandler + + PUBWEAK GPIO31_IRQHandler + SECTION .text:CODE:REORDER(1) +GPIO31_IRQHandler + B GPIO31_IRQHandler + + PUBWEAK ACE_PC0_Flag0_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC0_Flag0_IRQHandler + B ACE_PC0_Flag0_IRQHandler + + PUBWEAK ACE_PC0_Flag1_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC0_Flag1_IRQHandler + B ACE_PC0_Flag1_IRQHandler + + PUBWEAK ACE_PC0_Flag2_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC0_Flag2_IRQHandler + B ACE_PC0_Flag2_IRQHandler + + PUBWEAK ACE_PC0_Flag3_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC0_Flag3_IRQHandler + B ACE_PC0_Flag3_IRQHandler + + PUBWEAK ACE_PC1_Flag0_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC1_Flag0_IRQHandler + B ACE_PC1_Flag0_IRQHandler + + PUBWEAK ACE_PC1_Flag1_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC1_Flag1_IRQHandler + B ACE_PC1_Flag1_IRQHandler + + PUBWEAK ACE_PC1_Flag2_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC1_Flag2_IRQHandler + B ACE_PC1_Flag2_IRQHandler + + PUBWEAK ACE_PC1_Flag3_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC1_Flag3_IRQHandler + B ACE_PC1_Flag3_IRQHandler + + PUBWEAK ACE_PC2_Flag0_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC2_Flag0_IRQHandler + B ACE_PC2_Flag0_IRQHandler + + PUBWEAK ACE_PC2_Flag1_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC2_Flag1_IRQHandler + B ACE_PC2_Flag1_IRQHandler + + PUBWEAK ACE_PC2_Flag2_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC2_Flag2_IRQHandler + B ACE_PC2_Flag2_IRQHandler + + PUBWEAK ACE_PC2_Flag3_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PC2_Flag3_IRQHandler + B ACE_PC2_Flag3_IRQHandler + + PUBWEAK ACE_ADC0_DataValid_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC0_DataValid_IRQHandler + B ACE_ADC0_DataValid_IRQHandler + + PUBWEAK ACE_ADC1_DataValid_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC1_DataValid_IRQHandler + B ACE_ADC1_DataValid_IRQHandler + + PUBWEAK ACE_ADC2_DataValid_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC2_DataValid_IRQHandler + B ACE_ADC2_DataValid_IRQHandler + + PUBWEAK ACE_ADC0_CalDone_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC0_CalDone_IRQHandler + B ACE_ADC0_CalDone_IRQHandler + + PUBWEAK ACE_ADC1_CalDone_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC1_CalDone_IRQHandler + B ACE_ADC1_CalDone_IRQHandler + + PUBWEAK ACE_ADC2_CalDone_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC2_CalDone_IRQHandler + B ACE_ADC2_CalDone_IRQHandler + + PUBWEAK ACE_ADC0_CalStart_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC0_CalStart_IRQHandler + B ACE_ADC0_CalStart_IRQHandler + + PUBWEAK ACE_ADC1_CalStart_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC1_CalStart_IRQHandler + B ACE_ADC1_CalStart_IRQHandler + + PUBWEAK ACE_ADC2_CalStart_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC2_CalStart_IRQHandler + B ACE_ADC2_CalStart_IRQHandler + + PUBWEAK ACE_Comp0_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp0_Fall_IRQHandler + B ACE_Comp0_Fall_IRQHandler + + PUBWEAK ACE_Comp1_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp1_Fall_IRQHandler + B ACE_Comp1_Fall_IRQHandler + + PUBWEAK ACE_Comp2_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp2_Fall_IRQHandler + B ACE_Comp2_Fall_IRQHandler + + PUBWEAK ACE_Comp3_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp3_Fall_IRQHandler + B ACE_Comp3_Fall_IRQHandler + + PUBWEAK ACE_Comp4_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp4_Fall_IRQHandler + B ACE_Comp4_Fall_IRQHandler + + PUBWEAK ACE_Comp5_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp5_Fall_IRQHandler + B ACE_Comp5_Fall_IRQHandler + + PUBWEAK ACE_Comp6_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp6_Fall_IRQHandler + B ACE_Comp6_Fall_IRQHandler + + PUBWEAK ACE_Comp7_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp7_Fall_IRQHandler + B ACE_Comp7_Fall_IRQHandler + + PUBWEAK ACE_Comp8_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp8_Fall_IRQHandler + B ACE_Comp8_Fall_IRQHandler + + PUBWEAK ACE_Comp9_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp9_Fall_IRQHandler + B ACE_Comp9_Fall_IRQHandler + + PUBWEAK ACE_Comp10_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp10_Fall_IRQHandler + B ACE_Comp10_Fall_IRQHandler + + PUBWEAK ACE_Comp11_Fall_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp11_Fall_IRQHandler + B ACE_Comp11_Fall_IRQHandler + + PUBWEAK ACE_Comp0_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp0_Rise_IRQHandler + B ACE_Comp0_Rise_IRQHandler + + PUBWEAK ACE_Comp1_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp1_Rise_IRQHandler + B ACE_Comp1_Rise_IRQHandler + + PUBWEAK ACE_Comp2_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp2_Rise_IRQHandler + B ACE_Comp2_Rise_IRQHandler + + PUBWEAK ACE_Comp3_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp3_Rise_IRQHandler + B ACE_Comp3_Rise_IRQHandler + + PUBWEAK ACE_Comp4_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp4_Rise_IRQHandler + B ACE_Comp4_Rise_IRQHandler + + PUBWEAK ACE_Comp5_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp5_Rise_IRQHandler + B ACE_Comp5_Rise_IRQHandler + + PUBWEAK ACE_Comp6_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp6_Rise_IRQHandler + B ACE_Comp6_Rise_IRQHandler + + PUBWEAK ACE_Comp7_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp7_Rise_IRQHandler + B ACE_Comp7_Rise_IRQHandler + + PUBWEAK ACE_Comp8_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp8_Rise_IRQHandler + B ACE_Comp8_Rise_IRQHandler + + PUBWEAK ACE_Comp9_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp9_Rise_IRQHandler + B ACE_Comp9_Rise_IRQHandler + + PUBWEAK ACE_Comp10_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp10_Rise_IRQHandler + B ACE_Comp10_Rise_IRQHandler + + PUBWEAK ACE_Comp11_Rise_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_Comp11_Rise_IRQHandler + B ACE_Comp11_Rise_IRQHandler + + PUBWEAK ACE_ADC0_FifoFull_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC0_FifoFull_IRQHandler + B ACE_ADC0_FifoFull_IRQHandler + + PUBWEAK ACE_ADC0_FifoAFull_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC0_FifoAFull_IRQHandler + B ACE_ADC0_FifoAFull_IRQHandler + + PUBWEAK ACE_ADC0_FifoEmpty_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC0_FifoEmpty_IRQHandler + B ACE_ADC0_FifoEmpty_IRQHandler + + PUBWEAK ACE_ADC1_FifoFull_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC1_FifoFull_IRQHandler + B ACE_ADC1_FifoFull_IRQHandler + + PUBWEAK ACE_ADC1_FifoAFull_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC1_FifoAFull_IRQHandler + B ACE_ADC1_FifoAFull_IRQHandler + + PUBWEAK ACE_ADC1_FifoEmpty_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC1_FifoEmpty_IRQHandler + B ACE_ADC1_FifoEmpty_IRQHandler + + PUBWEAK ACE_ADC2_FifoFull_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC2_FifoFull_IRQHandler + B ACE_ADC2_FifoFull_IRQHandler + + PUBWEAK ACE_ADC2_FifoAFull_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC2_FifoAFull_IRQHandler + B ACE_ADC2_FifoAFull_IRQHandler + + PUBWEAK ACE_ADC2_FifoEmpty_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_ADC2_FifoEmpty_IRQHandler + B ACE_ADC2_FifoEmpty_IRQHandler + + PUBWEAK ACE_PPE_Flag0_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag0_IRQHandler + B ACE_PPE_Flag0_IRQHandler + + PUBWEAK ACE_PPE_Flag1_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag1_IRQHandler + B ACE_PPE_Flag1_IRQHandler + + PUBWEAK ACE_PPE_Flag2_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag2_IRQHandler + B ACE_PPE_Flag2_IRQHandler + + PUBWEAK ACE_PPE_Flag3_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag3_IRQHandler + B ACE_PPE_Flag3_IRQHandler + + PUBWEAK ACE_PPE_Flag4_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag4_IRQHandler + B ACE_PPE_Flag4_IRQHandler + + PUBWEAK ACE_PPE_Flag5_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag5_IRQHandler + B ACE_PPE_Flag5_IRQHandler + + PUBWEAK ACE_PPE_Flag6_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag6_IRQHandler + B ACE_PPE_Flag6_IRQHandler + + PUBWEAK ACE_PPE_Flag7_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag7_IRQHandler + B ACE_PPE_Flag7_IRQHandler + + PUBWEAK ACE_PPE_Flag8_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag8_IRQHandler + B ACE_PPE_Flag8_IRQHandler + + PUBWEAK ACE_PPE_Flag9_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag9_IRQHandler + B ACE_PPE_Flag9_IRQHandler + + PUBWEAK ACE_PPE_Flag10_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag10_IRQHandler + B ACE_PPE_Flag10_IRQHandler + + PUBWEAK ACE_PPE_Flag11_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag11_IRQHandler + B ACE_PPE_Flag11_IRQHandler + + PUBWEAK ACE_PPE_Flag12_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag12_IRQHandler + B ACE_PPE_Flag12_IRQHandler + + PUBWEAK ACE_PPE_Flag13_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag13_IRQHandler + B ACE_PPE_Flag13_IRQHandler + + PUBWEAK ACE_PPE_Flag14_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag14_IRQHandler + B ACE_PPE_Flag14_IRQHandler + + PUBWEAK ACE_PPE_Flag15_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag15_IRQHandler + B ACE_PPE_Flag15_IRQHandler + + PUBWEAK ACE_PPE_Flag16_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag16_IRQHandler + B ACE_PPE_Flag16_IRQHandler + + PUBWEAK ACE_PPE_Flag17_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag17_IRQHandler + B ACE_PPE_Flag17_IRQHandler + + PUBWEAK ACE_PPE_Flag18_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag18_IRQHandler + B ACE_PPE_Flag18_IRQHandler + + PUBWEAK ACE_PPE_Flag19_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag19_IRQHandler + B ACE_PPE_Flag19_IRQHandler + + PUBWEAK ACE_PPE_Flag20_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag20_IRQHandler + B ACE_PPE_Flag20_IRQHandler + + PUBWEAK ACE_PPE_Flag21_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag21_IRQHandler + B ACE_PPE_Flag21_IRQHandler + + PUBWEAK ACE_PPE_Flag22_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag22_IRQHandler + B ACE_PPE_Flag22_IRQHandler + + PUBWEAK ACE_PPE_Flag23_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag23_IRQHandler + B ACE_PPE_Flag23_IRQHandler + + PUBWEAK ACE_PPE_Flag24_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag24_IRQHandler + B ACE_PPE_Flag24_IRQHandler + + PUBWEAK ACE_PPE_Flag25_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag25_IRQHandler + B ACE_PPE_Flag25_IRQHandler + + PUBWEAK ACE_PPE_Flag26_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag26_IRQHandler + B ACE_PPE_Flag26_IRQHandler + + PUBWEAK ACE_PPE_Flag27_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag27_IRQHandler + B ACE_PPE_Flag27_IRQHandler + + PUBWEAK ACE_PPE_Flag28_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag28_IRQHandler + B ACE_PPE_Flag28_IRQHandler + + PUBWEAK ACE_PPE_Flag29_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag29_IRQHandler + B ACE_PPE_Flag29_IRQHandler + + PUBWEAK ACE_PPE_Flag30_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag30_IRQHandler + B ACE_PPE_Flag30_IRQHandler + + PUBWEAK ACE_PPE_Flag31_IRQHandler + SECTION .text:CODE:REORDER(1) +ACE_PPE_Flag31_IRQHandler + B ACE_PPE_Flag31_IRQHandler + + END diff --git a/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/system_a2fxxxm3.c b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/system_a2fxxxm3.c new file mode 100644 index 000000000..1b3798f3e --- /dev/null +++ b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/system_a2fxxxm3.c @@ -0,0 +1,199 @@ +/******************************************************************************* + * (c) Copyright 2009 Actel Corporation. All rights reserved. + * + * SmartFusion A2FxxxM3 CMSIS system initialization. + * + * SVN $Revision: 2069 $ + * SVN $Date: 2010-01-28 00:23:48 +0000 (Thu, 28 Jan 2010) $ + */ +#include "a2fxxxm3.h" +#include "mss_assert.h" + +/* System frequency (FCLK) coming out of reset is 25MHz. */ +#define RESET_SYSCLCK_FREQ 25000000uL + +/* + * SmartFusion Microcontroller Subsystem FLCK frequency. + * The value of SMARTFUSION_FCLK_FREQ is used to report the system's clock + * frequency in system's which either do not use the Actel System Boot or + * a version of the Actel System Boot older than 1.3.1. In eitehr of these cases + * SMARTFUSION_FCLK_FREQ should be defined in the projects settings to reflect + * the FCLK frequency selected in the Libero MSS configurator. + * Systems using the Actel System Boot version 1.3.1 or later do not require this + * define since the system's frequency is retrieved from eNVM spare pages where + * the MSS Configurator stored the frequency selected during hardware design/configuration. + */ +#ifdef SMARTFUSION_FCLK_FREQ +#define SMARTFUSION_FCLK_FREQ_DEFINED 1 +#else +#define SMARTFUSION_FCLK_FREQ_DEFINED 0 +#define SMARTFUSION_FCLK_FREQ RESET_SYSCLCK_FREQ +#endif + +/* Divider values for APB0, APB1 and ACE clocks. */ +#define RESET_PCLK0_DIV 4uL +#define RESET_PCLK1_DIV 4uL +#define RESET_ACE_DIV 4uL +#define RESET_FPGA_CLK_DIV 4uL + +/* System register clock control mask and shift for PCLK dividers. */ +#define PCLK_DIV_MASK 0x00000003uL +#define PCLK0_DIV_SHIFT 2uL +#define PCLK1_DIV_SHIFT 4uL +#define ACE_DIV_SHIFT 6uL + +/* System register MSS_CCC_DIV_CR mask and shift for GLB (FPGA fabric clock). */ +#define OBDIV_SHIFT 8uL +#define OBDIV_MASK 0x0000001FuL +#define OBDIVHALF_SHIFT 13uL +#define OBDIVHALF_MASK 0x00000001uL + +/* + * Actel system boot version defines used to extract the system clock from eNVM + * spare pages. + * These defines allow detecting the presence of Actel system boot in eNVM spare + * pages and the version of that system boot executable and associated + * configuration data. + */ +#define SYSBOOT_KEY_ADDR (uint32_t *)0x6008081C +#define SYSBOOT_KEY_VALUE 0x4C544341uL +#define SYSBOOT_VERSION_ADDR (uint32_t *)0x60080840 +#define SYSBOOT_1_3_FCLK_ADDR (uint32_t *)0x6008162C +#define SYSBOOT_2_x_FCLK_ADDR (uint32_t *)0x60081EAC + +/* + * The system boot version is stored in the least significant 24 bits of a word. + * The FCLK is stored in eNVM from version 1.3.1 of the system boot. We expect + * that the major version number of the system boot version will change if the + * system boot configuration data layout needs to change. + */ +#define SYSBOOT_VERSION_MASK 0x00FFFFFFuL +#define MIN_SYSBOOT_VERSION 0x00010301uL +#define SYSBOOT_VERSION_2_X 0x00020000uL +#define MAX_SYSBOOT_VERSION 0x00030000uL + +/* Standard CMSIS global variables. */ +uint32_t SystemFrequency = SMARTFUSION_FCLK_FREQ; /*!< System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = SMARTFUSION_FCLK_FREQ; /*!< System Clock Frequency (Core Clock) */ + +/* SmartFusion specific clocks. */ +uint32_t g_FrequencyPCLK0 = (SMARTFUSION_FCLK_FREQ / RESET_PCLK0_DIV); /*!< Clock frequency of APB bus 0. */ +uint32_t g_FrequencyPCLK1 = (SMARTFUSION_FCLK_FREQ / RESET_PCLK1_DIV); /*!< Clock frequency of APB bus 1. */ +uint32_t g_FrequencyACE = (SMARTFUSION_FCLK_FREQ / RESET_ACE_DIV); /*!< Clock frequency of Analog Compute Engine. */ +uint32_t g_FrequencyFPGA = (SMARTFUSION_FCLK_FREQ / RESET_FPGA_CLK_DIV); /*!< Clock frequecny of FPGA fabric */ + +/* Local functions */ +static uint32_t GetSystemClock( void ); + +/***************************************************************************//** + * See system_a2fm3fxxx.h for details. + */ +void SystemInit(void) +{ +} + +/***************************************************************************//** + * + */ +void SystemCoreClockUpdate (void) +{ + uint32_t PclkDiv0; + uint32_t PclkDiv1; + uint32_t AceDiv; + uint32_t FabDiv; + + const uint32_t pclk_div_lut[4] = { 1uL, 2uL, 4uL, 1uL }; + + /* Read PCLK dividers from system registers. Multiply the value read from + * system register by two to get actual divider value. */ + PclkDiv0 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK0_DIV_SHIFT) & PCLK_DIV_MASK)]; + PclkDiv1 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK1_DIV_SHIFT) & PCLK_DIV_MASK)]; + AceDiv = pclk_div_lut[((SYSREG->MSS_CLK_CR >> ACE_DIV_SHIFT) & PCLK_DIV_MASK)]; + { + /* Compute the FPGA fabric frequency divider. */ + uint32_t obdiv; + uint32_t obdivhalf; + + obdiv = (SYSREG->MSS_CCC_DIV_CR >> OBDIV_SHIFT) & OBDIV_MASK; + obdivhalf = (SYSREG->MSS_CCC_DIV_CR >> OBDIVHALF_SHIFT) & OBDIVHALF_MASK; + FabDiv = obdiv + 1uL; + if ( obdivhalf != 0uL ) + { + FabDiv = FabDiv * 2uL; + } + } + + /* Retrieve FCLK from eNVM spare pages if Actel system boot programmed as part of the system. */ + + /* Read system clock from eNVM spare pages. */ + SystemCoreClock = GetSystemClock(); + g_FrequencyPCLK0 = SystemCoreClock / PclkDiv0; + g_FrequencyPCLK1 = SystemCoreClock / PclkDiv1; + g_FrequencyACE = SystemCoreClock / AceDiv; + g_FrequencyFPGA = SystemCoreClock / FabDiv; + + /* Keep SystemFrequency as well as SystemCoreClock for legacy reasons. */ + SystemFrequency = SystemCoreClock; +} + +/***************************************************************************//** + * Retrieve the system clock frequency from eNVM spare page if available. + * Returns the frequency defined through SMARTFUSION_FCLK_FREQ if FCLK cannot be + * retrieved from eNVM spare pages. + * The FCLK frequency value selected in the MSS Configurator software tool is + * stored in eNVM spare pages as part of the Actel system boot configuration data. + */ +uint32_t GetSystemClock( void ) +{ + uint32_t fclk = 0uL; + + uint32_t * p_sysboot_key = SYSBOOT_KEY_ADDR; + + if ( SYSBOOT_KEY_VALUE == *p_sysboot_key ) + { + /* Actel system boot programmed, check if it has the FCLK value stored. */ + uint32_t *p_sysboot_version = SYSBOOT_VERSION_ADDR; + uint32_t sysboot_version = *p_sysboot_version; + + sysboot_version &= SYSBOOT_VERSION_MASK; + + if ( sysboot_version >= MIN_SYSBOOT_VERSION ) + { + /* Handle change of eNVM location of FCLK between 1.3.x and 2.x.x versions of the system boot. */ + if ( sysboot_version < SYSBOOT_VERSION_2_X ) + { + /* Read FCLK value from MSS configurator generated configuration + * data stored in eNVM spare pages as part of system boot version 1.3.x + * configuration tables. */ + uint32_t *p_fclk = SYSBOOT_1_3_FCLK_ADDR; + fclk = *p_fclk; + } + else if ( sysboot_version < MAX_SYSBOOT_VERSION ) + { + /* Read FCLK value from MSS configurator generated configuration + * data stored in eNVM spare pages as part of system boot version 2.x.x + * configuration tables. */ + uint32_t *p_fclk = SYSBOOT_2_x_FCLK_ADDR; + fclk = *p_fclk; + } + else + { + fclk = 0uL; + } + } + } + + if ( 0uL == fclk ) + { + /* + * Could not retrieve FCLK from system boot configuration data. Fall back + * to using SMARTFUSION_FCLK_FREQ which must then be defined as part of + * project settings. + */ + ASSERT( SMARTFUSION_FCLK_FREQ_DEFINED ); + fclk = SMARTFUSION_FCLK_FREQ; + } + + return fclk; +} + diff --git a/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/system_a2fxxxm3.h b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/system_a2fxxxm3.h new file mode 100644 index 000000000..6ae0ad5b7 --- /dev/null +++ b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS_IAR/system_a2fxxxm3.h @@ -0,0 +1,49 @@ +/******************************************************************************* + * (c) Copyright 2009 Actel Corporation. All rights reserved. + * + * SmartFusion A2FxxxM3 CMSIS system initialization. + * + * SVN $Revision: 2064 $ + * SVN $Date: 2010-01-27 15:05:58 +0000 (Wed, 27 Jan 2010) $ + */ + +#ifndef __SYSTEM_A2FM3FXX_H__ +#define __SYSTEM_A2FM3FXX_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Standard CMSIS global variables. */ +extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/* SmartFusion specific clocks. */ +extern uint32_t g_FrequencyPCLK0; /*!< Clock frequency of APB bus 0. */ +extern uint32_t g_FrequencyPCLK1; /*!< Clock frequency of APB bus 1. */ +extern uint32_t g_FrequencyACE; /*!< Clock frequency of Analog Compute Engine. */ +extern uint32_t g_FrequencyFPGA; /*!< Clock frequecny of FPGA fabric */ + +/***************************************************************************//** + * The SystemInit() is a standard CMSIS function called during system startup. + * It is meant to perform low level hardware setup such as configuring PLLs. In + * the case of SmartFusion these hardware setup operations are performed by the + * chip boot which executed before the application started. Therefore this + * function does not need to perform any hardware setup. + */ +void SystemInit(void); + +/***************************************************************************//** + * The SystemCoreClockUpdate() is a standard CMSIS function which can be called + * by the application in order to ensure that the SystemCoreClock global + * variable contains the up to date Cortex-M3 core frequency. Calling this + * function also updates the global variables containing the frequencies of the + * APB busses connecting the peripherals and the ACE frequency. + */ +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif -- 2.39.5