From 8b3d91fbd307203a04432bd051a00b4d0674f3d2 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Sat, 27 Aug 2011 11:55:55 +0000 Subject: [PATCH] Update platform studio project for MicroBlaze with full Ethernet. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1562 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../SDK/SDK_Export/hw/system.bit | Bin 0 -> 1484497 bytes .../SDK/SDK_Export/hw/system.html | 12 + .../SDK/SDK_Export/hw/system.xml | 6926 +++++++++++++++++ .../SDK/SDK_Export/hw/system_bd.bmm | 32 + .../SDK/SDK_Export/hw/system_main.html | 5984 ++++++++++++++ .../SDK/SDK_Export/hw/system_mainNF.html | 5994 ++++++++++++++ .../SDK/SDK_Export/hw/system_toc.html | 73 + .../__xps/MCB_DDR3/param_input.xml | 2 +- .../__xps/MCB_DDR3/tcl.log | 34 +- .../__xps/ise/system.xreport | 4 +- .../PlatformStudioProject/__xps/system.xml | 227 +- .../PlatformStudioProject/etc/system.filters | 7 +- .../PlatformStudioProject/etc/system.gui | 33 +- .../implementation/system_summary.html | 80 +- .../PlatformStudioProject/system.mhs | 12 +- 15 files changed, 19223 insertions(+), 197 deletions(-) create mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.bit create mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.html create mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.xml create mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm create mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html create mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html create mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.bit 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Bus Structure Reset Registered Outputs + + + Number of Peripheral Reset Registered Outputs + + + Number of Active Low Interconnect Reset Registered Outputs + + + Number of Active Low Peripheral Reset Registered Outputs + + + Device Family + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Clock Generator + Clock generator for processor system. + + + + + + + Family + + + Device + + + Package + + + Speed Grade + + + Input Clock Frequency (Hz) + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Varaible Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Varaible Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Clock Deskew + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase Shift + + + + Clock Primitive Feedback Buffer + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + MicroBlaze Debug Module (MDM) + Debug module for MicroBlaze Soft Processor. + + + + + + + Device Family + + + Specifies the JTAG user-defined register used + + + Specifies the Bus Interface for the JTAG UART + + + Base Address + + + High Address + + + PLB Address Bus Width + + + PLB Data Bus Width + + + PLB Slave Uses P2P Topology + + + Master ID Bus Width of PLB + + + Number of PLB Masters + + + Native Data Bus Width of PLB Slave + + + PLB Slave is Capable of Bursts + + + Number of MicroBlaze debug ports + + + Enable JTAG UART + + + AXI Address Width + + + AXI Data Width + + + AXI4LITE protocal + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI UART (Lite) + Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI. + + + + + + + Device Family + + + AXI Clock Frequency + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + UART Lite Baud Rate + Baud Rate + + + Number of Data Bits in a Serial Frame + Data Bits + + + Use Parity + + + Parity Type + + + AXI4LITE protocol + + + + + + + + + + Serial Data Out + + + Serial Data In + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI General Purpose IO + General Purpose Input/Output (GPIO) core for the AXI bus. + + + + + + + Device Family + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + GPIO Data Channel Width + GPIO Data Width + + + GPIO2 Data Channel Width + + + Channel 1 is Input Only + + + Channel 2 is Input Only + + + GPIO Supports Interrupts + + + Channel 1 Data Out Default Value + + + Channel 1 Tri-state Default Value + + + Enable Channel 2 + + + Channel 2 Data Out Default Value + + + Channel 2 Tri-state Default Value + + + AXI4LITE protocol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GPIO1 Data IO + + + GPIO2 Data IO + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI General Purpose IO + General Purpose Input/Output (GPIO) core for the AXI bus. + + + + + + + Device Family + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + GPIO Data Channel Width + GPIO Data Width + + + GPIO2 Data Channel Width + + + Channel 1 is Input Only + + + Channel 2 is Input Only + + + GPIO Supports Interrupts + + + Channel 1 Data Out Default Value + + + Channel 1 Tri-state Default Value + + + Enable Channel 2 + + + Channel 2 Data Out Default Value + + + Channel 2 Tri-state Default Value + + + AXI4LITE protocol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GPIO1 Data IO + + + GPIO2 Data IO + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI S6 Memory Controller(DDR/DDR2/DDR3) + Spartan-6 memory controller + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Ethernet + AXI Ethernet MAC + + + + + + + AXI Protocol + + + AXI Stream Bus Width + + + AXI Stream Bus Width + + + AXI Stream Bus Width + + + AXI Stream Bus Width + + + AXI Stream Protocol + + + AXI Stream Protocol + + + AXI Stream Protocol + + + AXI Stream Protocol + + + AXI Stream Protocol + + + AXI Stream Protocol + + + Device Family + + + AXI Clock Freq in HZ + + + Base Address + + + High Address + + + AXI Address Width + + + AXI Data Width + + + AXI ID Width + + + Spartan 6 Transceiver Side + + + PHY Address + + + Include IO and BUFG as Needed for the PHY Interface Selected + + + Type of TEMAC + + + Physical Interface Type + + + Enable Half Duplex mode + + + TX Memory Depth + + + RX Memory Depth + + + Enable TX Checksum Offload + + + Enable RX Checksum Offload + + + Transmit VLAN translation + + + Receive VLAN translation + + + Transmit VLAN tagging + + + Receive VLAN tagging + + + Transmit VLAN stripping + + + Receive VLAN stripping + + + Receive Extended Multicast Address Filtering + + + Statistics Counters + + + Audio Video Bridging (AVB) - license required + + + Simulation Mode + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI DMA Engine + AXI MemoryMap to/from AXI Stream Direct Memory Access Engine + + + + + + + AXI Lite Address Width + + + AXI Lite Data Width + + + Delay Timer Counter Resolution + + + Primary clock Is Asynchronous + + + Include Scatter Gather Descriptor Queuing + + + Include AXI Status and Control Streams + + + Use Status Stream App Length + + + Buffer Length Field Width + + + AXI SG Address Width + + + AXI SG Data Width + + + AXI Control Stream Width + + + AXI Status Stream Width + + + Include MM2S Channel + + + Include MM2S Data Realignment Engine + + + Maximum Memory Map Burst Size for MM2S + + + MM2S Address Width + + + MM2S Memory Map Data Width + + + MM2S Stream Data Width + + + Include S2MM Channel + + + Include S2MM Data Realignment Engine + + + Maximum Memory Map Burst Size for S2MM (data beats) + + + S2MM Address Width + + + S2MM Memory Map Data Width + + + S2MM Stream Data Width + + + Device Family + + + Base Address + + + High Address + + + AXI Lite Clock Frequency + + + AXI Scatter Gather Clock Frequency + + + AXI MM2S Clock Frequency + + + AXI S2MM Clock Frequency + + + AXI Lite Protocol + + + AXI Lite Supports Read Access + + + AXI Lite Supports Write Access + + + AXI SG Protocol + + + AXI SG Support Threads + + + Base Address + + + AXI SG Supports Narrow Bursts + + + AXI SG Generates Read Accesses + + + AXI SG Generates Write Accesses + + + AXI MM2S Protocol + + + AXI MM2S Support Threads + + + AXI MM2S Thread ID Width + + + AXI MM2S Supports Narrow Bursts + + + AXI MM2S Generates Read Accesses + + + AXI MM2S Generates Write Accesses + + + AXI MM2S Interface Read Issuing + + + AXI MM2S Interface Read FIFO Depth + + + AXI S2MM Protocol + + + AXI S2MM Support Threads + + + AXI S2MM Thread ID Width + + + AXI S2MM Supports Narrow Bursts + + + AXI S2MM Generates Write Accesses + + + AXI S2MM Generates Read Accesses + + + AXI S2MM Interface Write Issuing + + + AXI S2MM Interface Write FIFO Depth + + + AXI MM2S Stream Interface Protocol + + + AXI S2MM Stream Interface Protocol + + + AXI MM2S Control Stream Interface Protocol + + + AXI S2MM Status Stream Interface Protocol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Interrupt Controller + intc core attached to the AXI + + + + + + + Device Family + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + Number of Interrupt Inputs + + + Type of Interrupt for Each Input + + + Type of Each Edge Senstive Interrupt + + + Type of Each Level Sensitive Interrupt + + + Support IPR + + + Support SIE + + + Support CIE + + + Support IVR + + + IRQ Output Use Level + + + The Sense of IRQ Output + + + AXI4LITE protocol + + + + + + + + + + Interrupt Request Output + + + + + + + + + + + + Interrupt Inputs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Timer/Counter + Timer counter with AXI interface + + + + + + + AXI4LITE protocol + + + Device Family + + + The Width of Counter in Timer + Count Width + + + Only One Timer is present + + + TRIG0 Active Level + + + TRIG1 Active Level + + + GEN0 Active Level + + + GEN1 Active Level + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + + + + + Capture Trig 0 + + + Capture Trig 1 + + + Generate Out 0 + + + Generate Out 1 + + + Pulse Width Modulation 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm new file mode 100644 index 000000000..7a8633606 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm @@ -0,0 +1,32 @@ +// BMM LOC annotation file. +// +// Release 13.1 - Data2MEM O.40d, build 1.9 Aug 19, 2010 +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. + + +/////////////////////////////////////////////////////////////////////////////// +// +// Processor 'microblaze_0', ID 100, memory map. +// +/////////////////////////////////////////////////////////////////////////////// + +ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100 + + + /////////////////////////////////////////////////////////////////////////////// + // + // Processor 'microblaze_0' address space 'microblaze_0_bram_block_combined' 0x00000000:0x00001FFF (8 KBytes). + // + /////////////////////////////////////////////////////////////////////////////// + + ADDRESS_SPACE microblaze_0_bram_block_combined RAMB16 [0x00000000:0x00001FFF] + BUS_BLOCK + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X0Y24; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X0Y26; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X0Y22; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X0Y28; + END_BUS_BLOCK; + END_ADDRESS_SPACE; + +END_ADDRESS_MAP; + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html new file mode 100644 index 000000000..fc27d4cf6 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html @@ -0,0 +1,5984 @@ + + + + +XPS Project Report + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Printable Version
+
Overview
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Resources Used
1  MicroBlaze
2  AXI Interconnect
2  Local Memory Bus (LMB) 1.0
1  Block RAM (BRAM) Block
2  LMB BRAM Controller
1  AXI S6 Memory Controller(DDR/DDR2/DDR3)
1  Processor System Reset Module
1  Clock Generator
1  MicroBlaze Debug Module (MDM)
1  AXI UART (Lite)
2  AXI General Purpose IO
1  AXI Ethernet
1  AXI DMA Engine
1  AXI Interrupt Controller
1  AXI Timer/Counter
 + + + + + + + + + + + + + + +
Specifics
GeneratedSat Aug 27 12:49:18 2011
EDK Version13.1
Device Familyspartan6
Devicexc6slx45tfgg484-3
+
+
+ + +
Block DiagramTOP
+
BlockDiagram +
+ + + +
External PortsTOP
+
+ + + + + + +
+ These are the external ports defined in the MHS file. +
+Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+SHARED +RESETI1RESET RESET 
+ETHERNET +ETHERNET_MII_TX_CLKI1ETHERNET_MII_TX_CLK
+ETHERNET +ETHERNET_RXDI0:7ETHERNET_RXD
+ETHERNET +ETHERNET_RX_CLKI1ETHERNET_RX_CLK
+ETHERNET +ETHERNET_RX_DVI1ETHERNET_RX_DV
+ETHERNET +ETHERNET_RX_ERI1ETHERNET_RX_ER
+ETHERNET +ETHERNET_MDIOIO1ETHERNET_MDIO
+ETHERNET +ETHERNET_MDCO1ETHERNET_MDC
+ETHERNET +ETHERNET_PHY_RST_NO1ETHERNET_PHY_RST_N
+ETHERNET +ETHERNET_TXDO0:7ETHERNET_TXD
+ETHERNET +ETHERNET_TX_CLKO1ETHERNET_TX_CLK
+ETHERNET +ETHERNET_TX_ENO1ETHERNET_TX_EN
+ETHERNET +ETHERNET_TX_ERO1ETHERNET_TX_ER
+LEDs_4Bits +LEDs_4Bits_TRI_OO0:3LEDs_4Bits_TRI_O
+MCB_DDR3 +mcbx_dram_dqIO0:15mcbx_dram_dq
+MCB_DDR3 +mcbx_dram_dqsIO1mcbx_dram_dqs
+MCB_DDR3 +mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
+MCB_DDR3 +mcbx_dram_udqsIO1mcbx_dram_udqs
+MCB_DDR3 +mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
+MCB_DDR3 +rzqIO1rzq
+MCB_DDR3 +zioIO1zio
+MCB_DDR3 +mcbx_dram_addrO0:12mcbx_dram_addr
+MCB_DDR3 +mcbx_dram_baO0:2mcbx_dram_ba
+MCB_DDR3 +mcbx_dram_cas_nO1mcbx_dram_cas_n
+MCB_DDR3 +mcbx_dram_ckeO1mcbx_dram_cke
+MCB_DDR3 +mcbx_dram_clkO1mcbx_dram_clk
+MCB_DDR3 +mcbx_dram_clk_nO1mcbx_dram_clk_n
+MCB_DDR3 +mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
+MCB_DDR3 +mcbx_dram_ldmO1mcbx_dram_ldm
+MCB_DDR3 +mcbx_dram_odtO1mcbx_dram_odt
+MCB_DDR3 +mcbx_dram_ras_nO1mcbx_dram_ras_n
+MCB_DDR3 +mcbx_dram_udmO1mcbx_dram_udm
+MCB_DDR3 +mcbx_dram_we_nO1mcbx_dram_we_n
+Push_Buttons_4Bits +Push_Buttons_4Bits_TRI_II0:3Push_Buttons_4Bits_TRI_I
+RS232_Uart_1 +RS232_Uart_1_sinI1RS232_Uart_1_sin
+RS232_Uart_1 +RS232_Uart_1_soutO1RS232_Uart_1_sout
+clock_generator_0 +CLK_NI1CLK CLK 
+clock_generator_0 +CLK_PI1CLK CLK 
+
+

+ + +
ProcessorsTOP
+
+ + +
+ + + + + + + + + +
+microblaze_0 +   MicroBlaze
The MicroBlaze 32 bit soft processor

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
microblaze8.10.aIP
+

+
microblaze_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0MB_RESETI1proc_sys_reset_0_MB_Reset
1CLKI1clk_100_0000MHzPLL0
2INTERRUPTI1microblaze_0_interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXI_DPMASTERAXIaxi4lite_08 Peripherals.
DLMBMASTERLMBmicroblaze_0_dlmbmicroblaze_0_d_bram_ctrl
ILMBMASTERLMBmicroblaze_0_ilmbmicroblaze_0_i_bram_ctrl
DEBUGTARGETXIL_MBDEBUG3microblaze_0_debugdebug_module
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_SCO0
C_FREQ0
C_DATA_SIZE32
C_DYNAMIC_BUS_SIZING1
C_FAMILYvirtex5
C_INSTANCEmicroblaze
C_FAULT_TOLERANT0
C_ECC_USE_CE_EXCEPTION0
C_ENDIANNESS0
C_AREA_OPTIMIZED0
C_OPTIMIZATION0
C_INTERCONNECT2
C_STREAM_INTERCONNECT0
C_DPLB_DWIDTH32
C_DPLB_NATIVE_DWIDTH32
C_DPLB_BURST_EN0
C_DPLB_P2P0
C_IPLB_DWIDTH32
C_IPLB_NATIVE_DWIDTH32
C_IPLB_BURST_EN0
C_IPLB_P2P0
C_M_AXI_DP_SUPPORTS_THREADS0
C_M_AXI_DP_THREAD_ID_WIDTH1
C_M_AXI_DP_SUPPORTS_READ1
C_M_AXI_DP_SUPPORTS_WRITE1
C_M_AXI_DP_SUPPORTS_NARROW_BURST0
C_M_AXI_DP_DATA_WIDTH32
C_M_AXI_DP_ADDR_WIDTH32
C_M_AXI_DP_PROTOCOLAXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING1
C_M_AXI_IP_SUPPORTS_THREADS0
C_M_AXI_IP_THREAD_ID_WIDTH1
C_M_AXI_IP_SUPPORTS_READ1
C_M_AXI_IP_SUPPORTS_WRITE0
C_M_AXI_IP_SUPPORTS_NARROW_BURST0
C_M_AXI_IP_DATA_WIDTH32
C_M_AXI_IP_ADDR_WIDTH32
C_M_AXI_IP_PROTOCOLAXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING1
C_D_AXI0
C_D_PLB0
C_D_LMB1
C_I_AXI0
C_I_PLB0
C_I_LMB1
C_USE_MSR_INSTR1
C_USE_PCMP_INSTR1
C_USE_BARREL1
C_USE_DIV0
C_USE_HW_MUL1
C_USE_FPU0
C_UNALIGNED_EXCEPTIONS0
C_ILL_OPCODE_EXCEPTION0
C_M_AXI_I_BUS_EXCEPTION0
C_M_AXI_D_BUS_EXCEPTION0
C_IPLB_BUS_EXCEPTION0
C_DPLB_BUS_EXCEPTION0
C_DIV_ZERO_EXCEPTION0
C_FPU_EXCEPTION0
C_FSL_EXCEPTION0
C_USE_STACK_PROTECTION0
C_PVR0
C_PVR_USER10x00
C_PVR_USER20x00000000
C_DEBUG_ENABLED1
C_NUMBER_OF_PC_BRK7
C_NUMBER_OF_RD_ADDR_BRK2
C_NUMBER_OF_WR_ADDR_BRK2
C_INTERRUPT_IS_EDGE0
C_EDGE_IS_POSITIVE1
C_RESET_MSR0x00000000
C_OPCODE_0x0_ILLEGAL0
C_FSL_LINKS0
C_FSL_DATA_SIZE32
C_USE_EXTENDED_FSL_INSTR0
C_M0_AXIS_PROTOCOLGENERIC
C_S0_AXIS_PROTOCOLGENERIC
C_M1_AXIS_PROTOCOLGENERIC
C_S1_AXIS_PROTOCOLGENERIC
C_M2_AXIS_PROTOCOLGENERIC
C_S2_AXIS_PROTOCOLGENERIC
C_M3_AXIS_PROTOCOLGENERIC
C_S3_AXIS_PROTOCOLGENERIC
C_M4_AXIS_PROTOCOLGENERIC
C_S4_AXIS_PROTOCOLGENERIC
C_M5_AXIS_PROTOCOLGENERIC
C_S5_AXIS_PROTOCOLGENERIC
C_M6_AXIS_PROTOCOLGENERIC
C_S6_AXIS_PROTOCOLGENERIC
C_M7_AXIS_PROTOCOLGENERIC
C_S7_AXIS_PROTOCOLGENERIC
C_M8_AXIS_PROTOCOLGENERIC
C_S8_AXIS_PROTOCOLGENERIC
C_M9_AXIS_PROTOCOLGENERIC
C_S9_AXIS_PROTOCOLGENERIC
C_M10_AXIS_PROTOCOLGENERIC
C_S10_AXIS_PROTOCOLGENERIC
C_M11_AXIS_PROTOCOLGENERIC
C_S11_AXIS_PROTOCOLGENERIC
C_M12_AXIS_PROTOCOLGENERIC
C_S12_AXIS_PROTOCOLGENERIC
C_M13_AXIS_PROTOCOLGENERIC
C_S13_AXIS_PROTOCOLGENERIC
C_M14_AXIS_PROTOCOLGENERIC
C_S14_AXIS_PROTOCOLGENERIC
C_M15_AXIS_PROTOCOLGENERIC
C_S15_AXIS_PROTOCOLGENERIC
C_M0_AXIS_DATA_WIDTH32
C_S0_AXIS_DATA_WIDTH32
C_M1_AXIS_DATA_WIDTH32
C_S1_AXIS_DATA_WIDTH32
C_M2_AXIS_DATA_WIDTH32
C_S2_AXIS_DATA_WIDTH32
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_M3_AXIS_DATA_WIDTH32
C_S3_AXIS_DATA_WIDTH32
C_M4_AXIS_DATA_WIDTH32
C_S4_AXIS_DATA_WIDTH32
C_M5_AXIS_DATA_WIDTH32
C_S5_AXIS_DATA_WIDTH32
C_M6_AXIS_DATA_WIDTH32
C_S6_AXIS_DATA_WIDTH32
C_M7_AXIS_DATA_WIDTH32
C_S7_AXIS_DATA_WIDTH32
C_M8_AXIS_DATA_WIDTH32
C_S8_AXIS_DATA_WIDTH32
C_M9_AXIS_DATA_WIDTH32
C_S9_AXIS_DATA_WIDTH32
C_M10_AXIS_DATA_WIDTH32
C_S10_AXIS_DATA_WIDTH32
C_M11_AXIS_DATA_WIDTH32
C_S11_AXIS_DATA_WIDTH32
C_M12_AXIS_DATA_WIDTH32
C_S12_AXIS_DATA_WIDTH32
C_M13_AXIS_DATA_WIDTH32
C_S13_AXIS_DATA_WIDTH32
C_M14_AXIS_DATA_WIDTH32
C_S14_AXIS_DATA_WIDTH32
C_M15_AXIS_DATA_WIDTH32
C_S15_AXIS_DATA_WIDTH32
C_ICACHE_BASEADDR0xC0000000
C_ICACHE_HIGHADDR0xC7FFFFFF
C_USE_ICACHE0
C_ALLOW_ICACHE_WR1
C_ADDR_TAG_BITS17
C_CACHE_BYTE_SIZE8192
C_ICACHE_USE_FSL1
C_ICACHE_LINE_LEN4
C_ICACHE_ALWAYS_USED1
C_ICACHE_INTERFACE0
C_ICACHE_VICTIMS0
C_ICACHE_STREAMS0
C_ICACHE_FORCE_TAG_LUTRAM0
C_ICACHE_DATA_WIDTH0
C_M_AXI_IC_SUPPORTS_THREADS0
C_M_AXI_IC_THREAD_ID_WIDTH1
C_M_AXI_IC_SUPPORTS_READ1
C_M_AXI_IC_SUPPORTS_WRITE0
C_M_AXI_IC_SUPPORTS_NARROW_BURST0
C_M_AXI_IC_DATA_WIDTH32
C_M_AXI_IC_ADDR_WIDTH32
C_M_AXI_IC_PROTOCOLAXI4
C_M_AXI_IC_USER_VALUE0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS1
C_M_AXI_IC_AWUSER_WIDTH5
C_M_AXI_IC_ARUSER_WIDTH5
C_M_AXI_IC_WUSER_WIDTH1
C_M_AXI_IC_RUSER_WIDTH1
C_M_AXI_IC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING2
C_DCACHE_BASEADDR0xC0000000
C_DCACHE_HIGHADDR0xC7FFFFFF
C_USE_DCACHE0
C_ALLOW_DCACHE_WR1
C_DCACHE_ADDR_TAG17
C_DCACHE_BYTE_SIZE8192
C_DCACHE_USE_FSL1
C_DCACHE_LINE_LEN4
C_DCACHE_ALWAYS_USED1
C_DCACHE_INTERFACE0
C_DCACHE_USE_WRITEBACK0
C_DCACHE_VICTIMS0
C_DCACHE_FORCE_TAG_LUTRAM0
C_DCACHE_DATA_WIDTH0
C_M_AXI_DC_SUPPORTS_THREADS0
C_M_AXI_DC_THREAD_ID_WIDTH1
C_M_AXI_DC_SUPPORTS_READ1
C_M_AXI_DC_SUPPORTS_WRITE1
C_M_AXI_DC_SUPPORTS_NARROW_BURST0
C_M_AXI_DC_DATA_WIDTH32
C_M_AXI_DC_ADDR_WIDTH32
C_M_AXI_DC_PROTOCOLAXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS0
C_M_AXI_DC_USER_VALUE0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS1
C_M_AXI_DC_AWUSER_WIDTH5
C_M_AXI_DC_ARUSER_WIDTH5
C_M_AXI_DC_WUSER_WIDTH1
C_M_AXI_DC_RUSER_WIDTH1
C_M_AXI_DC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING32
C_USE_MMU0
C_MMU_DTLB_SIZE4
C_MMU_ITLB_SIZE2
C_MMU_TLB_ACCESS3
C_MMU_ZONES16
C_MMU_PRIVILEGED_INSTR0
C_USE_INTERRUPT0
C_USE_EXT_BRK0
C_USE_EXT_NM_BRK0
C_USE_BRANCH_TARGET_CACHE0
C_BRANCH_TARGET_CACHE_SIZE0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER1
C_INTERCONNECT_M_AXI_DC_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER1
C_INTERCONNECT_M_AXI_DP_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_R_REGISTER1
C_INTERCONNECT_M_AXI_DP_B_REGISTER1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER1
C_INTERCONNECT_M_AXI_DC_R_REGISTER1
C_INTERCONNECT_M_AXI_DC_B_REGISTER1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER1
C_INTERCONNECT_M_AXI_IC_W_REGISTER1
C_INTERCONNECT_M_AXI_IC_R_REGISTER1
C_INTERCONNECT_M_AXI_IC_B_REGISTER1
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
DebuggersTOP
+
+ + +
+ + + + + + + + + +
+debug_module +   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
mdm2.00.bIP
+

+
debug_module IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1Debug_SYS_RstO1proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
MBDEBUG_0INITIATORXIL_MBDEBUG3microblaze_0_debugmicroblaze_0
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_JTAG_CHAIN2
C_INTERCONNECT2
C_BASEADDR0x74800000
C_HIGHADDR0x748FFFFF
C_SPLB_AWIDTH32
C_SPLB_DWIDTH32
C_SPLB_P2P0
C_SPLB_MID_WIDTH3
C_SPLB_NUM_MASTERS8
C_SPLB_NATIVE_DWIDTH32
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_SPLB_SUPPORT_BURSTS0
C_MB_DBG_PORTS1
C_USE_UART1
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
Interrupt ControllersTOP
+
+ + +
+ + + + + + + + + +
+microblaze_0_intc +   AXI Interrupt Controller
intc core attached to the AXI

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_intc1.01.aIP
+

+
microblaze_0_intc IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0IRQO1microblaze_0_interrupt
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2INTRI1ETHERNET_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut & Push_Buttons_4Bits_IP2INTC_Irpt & RS232_Uart_1_Interrupt & axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+Interrupt Priorities
PrioritySIGMODULE
0ETHERNET_INTERRUPTETHERNET
1ETHERNET_dma_mm2s_introutETHERNET_dma
2ETHERNET_dma_s2mm_introutETHERNET_dma
3Push_Buttons_4Bits_IP2INTC_IrptPush_Buttons_4Bits
4RS232_Uart_1_InterruptRS232_Uart_1
5axi_timer_0_Interruptaxi_timer_0
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_BASEADDR0x41200000
C_HIGHADDR0x4120FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_NUM_INTR_INPUTS2
C_KIND_OF_INTR0xFFFFFFFF
C_KIND_OF_EDGE0xFFFFFFFF
C_KIND_OF_LVL0xFFFFFFFF
C_HAS_IPR1
C_HAS_SIE1
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_HAS_CIE1
C_HAS_IVR1
C_IRQ_IS_LEVEL1
C_IRQ_ACTIVE1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
BussesTOP
+
+ + + + + + + + +
+ + + + + + + + + +
+axi4_0 +   AXI Interconnect
AXI4 Memory-Mapped Interconnect

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
+

+
axi4_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0interconnect_aclkI1clk_100_0000MHzPLL0
1INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
ETHERNET_dmaMASTERM_AXI_SG
ETHERNET_dmaMASTERM_AXI_MM2S
ETHERNET_dmaMASTERM_AXI_S2MM
MCB_DDR3SLAVES0_AXI
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE1
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+axi4lite_0 +   AXI Interconnect
AXI4 Memory-Mapped Interconnect

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
+

+
axi4lite_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
1INTERCONNECT_ACLKI1clk_50_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DP
debug_moduleSLAVES_AXI
RS232_Uart_1SLAVES_AXI
LEDs_4BitsSLAVES_AXI
Push_Buttons_4BitsSLAVES_AXI
ETHERNETSLAVES_AXI
ETHERNET_dmaSLAVES_AXI_LITE
microblaze_0_intcSLAVES_AXI
axi_timer_0SLAVES_AXI
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE0
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+microblaze_0_dlmb +   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
+

+
microblaze_0_dlmb IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERDLMB
microblaze_0_d_bram_ctrlSLAVESLMB
+

+
+ + + + + + + + + + + + + + + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+microblaze_0_ilmb +   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
+

+
microblaze_0_ilmb IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERILMB
microblaze_0_i_bram_ctrlSLAVESLMB
+

+
+ + + + + + + + + + + + + + + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
MemorysTOP
+
+ + +
+ + + + + + + + + +
+microblaze_0_bram_block +   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
bram_block1.00.aIP
+

+
microblaze_0_bram_block IP Image + + + + + + + + + + + + + + + + + + + + + +
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
PORTATARGETXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_i_bram_ctrl
PORTBTARGETXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_d_bram_ctrl
+

+
+ + + + + + + + + + + + + + + + + + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
NameValue
C_MEMSIZE2048
C_PORT_DWIDTH32
C_PORT_AWIDTH32
C_NUM_WE4
C_FAMILYvirtex2
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
Memory ControllersTOP
+
+ + + + + + +
+ + + + + + + + + +
+MCB_DDR3 +   AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_s6_ddrx1.02.aIP
+

+
MCB_DDR3 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0mcbx_dram_clkO1mcbx_dram_clk
1mcbx_dram_clk_nO1mcbx_dram_clk_n
2mcbx_dram_ckeO1mcbx_dram_cke
3mcbx_dram_odtO1mcbx_dram_odt
4mcbx_dram_ras_nO1mcbx_dram_ras_n
5mcbx_dram_cas_nO1mcbx_dram_cas_n
6mcbx_dram_we_nO1mcbx_dram_we_n
7mcbx_dram_udmO1mcbx_dram_udm
8mcbx_dram_ldmO1mcbx_dram_ldm
9mcbx_dram_baO1mcbx_dram_ba
10mcbx_dram_addrO1mcbx_dram_addr
11mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
12mcbx_dram_dqIO1mcbx_dram_dq
13mcbx_dram_dqsIO1mcbx_dram_dqs
14mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
15mcbx_dram_udqsIO1mcbx_dram_udqs
16mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
17rzqIO1rzq
18zioIO1zio
19s0_axi_aclkI1clk_100_0000MHzPLL0
20ui_clkI1clk_100_0000MHzPLL0
21sysclk_2xI1clk_600_0000MHzPLL0_nobuf
22sysclk_2x_180I1clk_600_0000MHz180PLL0_nobuf
23SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
24PLL_LOCKI1proc_sys_reset_0_Dcm_locked
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S0_AXISLAVEAXIaxi4_0ETHERNET_dma
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_MCB_LOCMEMC3
C_MCB_RZQ_LOCK7
C_MCB_ZIO_LOCR7
C_MCB_PERFORMANCESTANDARD
C_BYPASS_CORE_UCF0
C_S0_AXI_BASEADDR0x80000000
C_S0_AXI_HIGHADDR0x87FFFFFF
C_S1_AXI_BASEADDR0xFFFFFFFF
C_S1_AXI_HIGHADDR0x00000000
C_S2_AXI_BASEADDR0xFFFFFFFF
C_S2_AXI_HIGHADDR0x00000000
C_S3_AXI_BASEADDR0xFFFFFFFF
C_S3_AXI_HIGHADDR0x00000000
C_S4_AXI_BASEADDR0xFFFFFFFF
C_S4_AXI_HIGHADDR0x00000000
C_S5_AXI_BASEADDR0xFFFFFFFF
C_S5_AXI_HIGHADDR0x00000000
C_MEM_TYPEDDR3
C_MEM_PARTNOMT41J64M16XX-187E
C_MEM_BASEPARTNONOT_SET
C_NUM_DQ_PINS16
C_MEM_ADDR_WIDTH13
C_MEM_BANKADDR_WIDTH3
C_MEM_NUM_COL_BITS10
C_MEM_TRAS-1
C_MEM_TRCD-1
C_MEM_TREFI-1
C_MEM_TRFC-1
C_MEM_TRP-1
C_MEM_TWR-1
C_MEM_TRTP-1
C_MEM_TWTR-1
C_PORT_CONFIGB32_B32_B32_B32
C_SKIP_IN_TERM_CAL0
C_SKIP_IN_TERM_CAL_VALUENONE
C_MEMCLK_PERIOD0
C_MEM_ADDR_ORDERROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT512
C_MEM_CAS_LATENCY6
C_SIMULATIONFALSE
C_MEM_DDR1_2_ODSFULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR2_RTT150OHMS
C_MEM_DDR2_DIFF_DQS_ENYES
C_MEM_DDR2_3_PA_SRFULL
C_MEM_DDR2_3_HIGH_TEMP_SRNORMAL
C_MEM_DDR3_CAS_WR_LATENCY5
C_MEM_DDR3_CAS_LATENCY6
C_MEM_DDR3_ODSDIV6
C_MEM_DDR3_RTTDIV4
C_MEM_DDR3_AUTO_SRENABLED
C_MEM_MOBILE_PA_SRFULL
C_MEM_MDDR_ODSFULL
C_ARB_ALGORITHM0
C_ARB_NUM_TIME_SLOTS12
C_ARB_TIME_SLOT_00b000000000001010011
C_ARB_TIME_SLOT_10b000000001010011000
C_ARB_TIME_SLOT_20b000000010011000001
C_ARB_TIME_SLOT_30b000000011000001010
C_ARB_TIME_SLOT_40b000000000001010011
C_ARB_TIME_SLOT_50b000000001010011000
C_ARB_TIME_SLOT_60b000000010011000001
C_ARB_TIME_SLOT_70b000000011000001010
C_ARB_TIME_SLOT_80b000000000001010011
C_ARB_TIME_SLOT_90b000000001010011000
C_ARB_TIME_SLOT_100b000000010011000001
C_ARB_TIME_SLOT_110b000000011000001010
C_S0_AXI_ENABLE1
C_S0_AXI_PROTOCOLAXI4
C_S0_AXI_ID_WIDTH4
C_S0_AXI_ADDR_WIDTH32
C_S0_AXI_DATA_WIDTH32
C_S0_AXI_SUPPORTS_READ1
C_S0_AXI_SUPPORTS_WRITE1
C_S0_AXI_SUPPORTS_NARROW_BURST1
C_S0_AXI_REG_EN00x00000
C_S0_AXI_REG_EN10x01000
C_S0_AXI_STRICT_COHERENCY0
C_S0_AXI_ENABLE_AP0
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE4
C_S1_AXI_ENABLE0
C_S1_AXI_PROTOCOLAXI4
C_S1_AXI_ID_WIDTH4
C_S1_AXI_ADDR_WIDTH32
C_S1_AXI_DATA_WIDTH32
C_S1_AXI_SUPPORTS_READ1
C_S1_AXI_SUPPORTS_WRITE1
C_S1_AXI_SUPPORTS_NARROW_BURST1
C_S1_AXI_REG_EN00x00000
C_S1_AXI_REG_EN10x01000
C_S1_AXI_STRICT_COHERENCY1
C_S1_AXI_ENABLE_AP0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE4
C_S2_AXI_ENABLE0
C_S2_AXI_PROTOCOLAXI4
C_S2_AXI_ID_WIDTH4
C_S2_AXI_ADDR_WIDTH32
C_S2_AXI_DATA_WIDTH32
C_S2_AXI_SUPPORTS_READ1
C_S2_AXI_SUPPORTS_WRITE1
C_S2_AXI_SUPPORTS_NARROW_BURST1
C_S2_AXI_REG_EN00x00000
C_S2_AXI_REG_EN10x01000
C_S2_AXI_STRICT_COHERENCY1
C_S2_AXI_ENABLE_AP0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE4
C_S3_AXI_ENABLE0
C_S3_AXI_PROTOCOLAXI4
C_S3_AXI_ID_WIDTH4
C_S3_AXI_ADDR_WIDTH32
C_S3_AXI_DATA_WIDTH32
C_S3_AXI_SUPPORTS_READ1
C_S3_AXI_SUPPORTS_WRITE1
C_S3_AXI_SUPPORTS_NARROW_BURST1
C_S3_AXI_REG_EN00x00000
C_S3_AXI_REG_EN10x01000
C_S3_AXI_STRICT_COHERENCY1
C_S3_AXI_ENABLE_AP0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE4
C_S4_AXI_ENABLE0
C_S4_AXI_PROTOCOLAXI4
C_S4_AXI_ID_WIDTH4
C_S4_AXI_ADDR_WIDTH32
C_S4_AXI_DATA_WIDTH32
C_S4_AXI_SUPPORTS_READ1
C_S4_AXI_SUPPORTS_WRITE1
C_S4_AXI_SUPPORTS_NARROW_BURST1
C_S4_AXI_REG_EN00x00000
C_S4_AXI_REG_EN10x01000
C_S4_AXI_STRICT_COHERENCY1
C_S4_AXI_ENABLE_AP0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE4
C_S5_AXI_ENABLE0
C_S5_AXI_PROTOCOLAXI4
C_S5_AXI_ID_WIDTH4
C_S5_AXI_ADDR_WIDTH32
C_S5_AXI_DATA_WIDTH32
C_S5_AXI_SUPPORTS_READ1
C_S5_AXI_SUPPORTS_WRITE1
C_S5_AXI_SUPPORTS_NARROW_BURST1
C_S5_AXI_REG_EN00x00000
C_S5_AXI_REG_EN10x01000
C_S5_AXI_STRICT_COHERENCY1
C_S5_AXI_ENABLE_AP0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE4
C_MCB_USE_EXTERNAL_BUFPLL0
C_SYS_RST_PRESENT0
C_INTERCONNECT_S0_AXI_MASTERSETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
C_INTERCONNECT_S0_AXI_AW_REGISTER1
C_INTERCONNECT_S0_AXI_AR_REGISTER1
C_INTERCONNECT_S0_AXI_W_REGISTER1
C_INTERCONNECT_S0_AXI_R_REGISTER1
C_INTERCONNECT_S0_AXI_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+microblaze_0_d_bram_ctrl +   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
+

+
microblaze_0_d_bram_ctrl IP Image + + + + + + + + + + + + + + + + + + + + + +
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_dlmbmicroblaze_0
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+microblaze_0_i_bram_ctrl +   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
+

+
microblaze_0_i_bram_ctrl IP Image + + + + + + + + + + + + + + + + + + + + + +
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_ilmbmicroblaze_0
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
PeripheralsTOP
+
+ + + + + + + + + + + + +
+ + + + + + + + + +
+ETHERNET +   AXI Ethernet
AXI Ethernet MAC

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_ethernet2.01.aIP
+

+
ETHERNET IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0MDIOIO1ETHERNET_MDIO
1MDCO1ETHERNET_MDC
2GMII_TX_ERO1ETHERNET_TX_ER
3GMII_TXDO1ETHERNET_TXD
4GMII_TX_ENO1ETHERNET_TX_EN
5MII_TX_CLKI1ETHERNET_MII_TX_CLK
6GMII_TX_CLKO1ETHERNET_TX_CLK
7GMII_RXDI1ETHERNET_RXD
8GMII_RX_ERI1ETHERNET_RX_ER
9GMII_RX_CLKI1ETHERNET_RX_CLK
10GMII_RX_DVI1ETHERNET_RX_DV
11PHY_RST_NO1ETHERNET_PHY_RST_N
12S_AXI_ACLKI1clk_50_0000MHzPLL0
13GTX_CLKI1clk_125_0000MHz
14REF_CLKI1clk_200_0000MHzPLL0
15AXI_STR_TXD_ACLKI1clk_100_0000MHzPLL0
16AXI_STR_TXC_ACLKI1clk_100_0000MHzPLL0
17AXI_STR_RXD_ACLKI1clk_100_0000MHzPLL0
18AXI_STR_RXS_ACLKI1clk_100_0000MHzPLL0
19AXI_STR_TXD_ARESETNI1AXI_STR_TXD_ARESETN
20AXI_STR_TXC_ARESETNI1AXI_STR_TXC_ARESETN
21AXI_STR_RXD_ARESETNI1AXI_STR_RXD_ARESETN
22AXI_STR_RXS_ARESETNI1AXI_STR_RXS_ARESETN
23INTERRUPTO1ETHERNET_INTERRUPT
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
AXI_STR_RXSINITIATORAXISETHERNET_dma_rxsETHERNET_dma
AXI_STR_RXDINITIATORAXISETHERNET_dma_rxdETHERNET_dma
S_AXISLAVEAXIaxi4lite_08 Peripherals.
AXI_STR_TXDTARGETAXISETHERNET_dma_txdETHERNET_dma
AXI_STR_TXCTARGETAXISETHERNET_dma_txcETHERNET_dma
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_AXI_STR_TXC_TDATA_WIDTH32
C_AXI_STR_TXD_TDATA_WIDTH32
C_AXI_STR_RXS_TDATA_WIDTH32
C_AXI_STR_RXD_TDATA_WIDTH32
C_AXI_STR_TXC_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_TXD_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_AXI_STR_RXS_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_RXD_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_AXI_STR_AVBTX_PROTOCOLXIL_AXI_STREAM_ETH_AVB_TX
C_AXI_STR_AVBRX_PROTOCOLXIL_AXI_STREAM_ETH_AVB_RX
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x41240000
C_HIGHADDR0x4127FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_ID_WIDTH4
C_TRANSA
C_PHYADDR0B00001
C_INCLUDE_IO1
C_TYPE1
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_PHY_TYPE1
C_HALFDUP0
C_TXMEM4096
C_RXMEM4096
C_TXCSUM0
C_RXCSUM0
C_TXVLAN_TRAN0
C_RXVLAN_TRAN0
C_TXVLAN_TAG0
C_RXVLAN_TAG0
C_TXVLAN_STRP0
C_RXVLAN_STRP0
C_MCAST_EXTEND0
C_STATS0
C_AVB0
C_SIMULATION0
C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC0
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+ETHERNET_dma +   AXI DMA Engine
AXI MemoryMap to/from AXI Stream Direct Memory Access Engine

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_dma3.00.aIP
+

+
ETHERNET_dma IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0s_axi_lite_aclkI1clk_100_0000MHzPLL0
1m_axi_sg_aclkI1clk_100_0000MHzPLL0
2m_axi_mm2s_aclkI1clk_100_0000MHzPLL0
3m_axi_s2mm_aclkI1clk_100_0000MHzPLL0
4mm2s_prmry_reset_out_nO1AXI_STR_TXD_ARESETN
5mm2s_cntrl_reset_out_nO1AXI_STR_TXC_ARESETN
6s2mm_prmry_reset_out_nO1AXI_STR_RXD_ARESETN
7s2mm_sts_reset_out_nO1AXI_STR_RXS_ARESETN
8mm2s_introutO1ETHERNET_dma_mm2s_introut
9s2mm_introutO1ETHERNET_dma_s2mm_introut
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXIS_MM2SINITIATORAXISETHERNET_dma_txdETHERNET
M_AXIS_CNTRLINITIATORAXISETHERNET_dma_txcETHERNET
M_AXI_SGMASTERAXIaxi4_0MCB_DDR3
M_AXI_MM2SMASTERAXIaxi4_0MCB_DDR3
M_AXI_S2MMMASTERAXIaxi4_0MCB_DDR3
S_AXI_LITESLAVEAXIaxi4lite_08 Peripherals.
S_AXIS_STSTARGETAXISETHERNET_dma_rxsETHERNET
S_AXIS_S2MMTARGETAXISETHERNET_dma_rxdETHERNET
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_LITE_ADDR_WIDTH32
C_S_AXI_LITE_DATA_WIDTH32
C_DLYTMR_RESOLUTION1250
C_PRMRY_IS_ACLK_ASYNC0
C_SG_INCLUDE_DESC_QUEUE1
C_SG_INCLUDE_STSCNTRL_STRM1
C_SG_USE_STSAPP_LENGTH1
C_SG_LENGTH_WIDTH16
C_M_AXI_SG_ADDR_WIDTH32
C_M_AXI_SG_DATA_WIDTH32
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH32
C_S_AXIS_S2MM_STS_TDATA_WIDTH32
C_INCLUDE_MM2S1
C_INCLUDE_MM2S_DRE1
C_MM2S_BURST_SIZE16
C_M_AXI_MM2S_ADDR_WIDTH32
C_M_AXI_MM2S_DATA_WIDTH32
C_M_AXIS_MM2S_TDATA_WIDTH32
C_INCLUDE_S2MM1
C_INCLUDE_S2MM_DRE1
C_S2MM_BURST_SIZE16
C_M_AXI_S2MM_ADDR_WIDTH32
C_M_AXI_S2MM_DATA_WIDTH32
C_S_AXIS_S2MM_TDATA_WIDTH32
C_FAMILYvirtex6
C_BASEADDR0x41E00000
C_HIGHADDR0x41E0FFFF
C_S_AXI_LITE_ACLK_FREQ_HZ100000000
C_M_AXI_SG_ACLK_FREQ_HZ100000000
C_M_AXI_MM2S_ACLK_FREQ_HZ100000000
C_M_AXI_S2MM_ACLK_FREQ_HZ100000000
C_S_AXI_LITE_PROTOCOLAXI4LITE
C_S_AXI_LITE_SUPPORTS_READ1
C_S_AXI_LITE_SUPPORTS_WRITE1
C_M_AXI_SG_PROTOCOLAXI4
C_M_AXI_SG_SUPPORTS_THREADS0
C_M_AXI_SG_THREAD_ID_WIDTH1
C_M_AXI_SG_SUPPORTS_NARROW_BURST0
C_M_AXI_SG_SUPPORTS_READ1
C_M_AXI_SG_SUPPORTS_WRITE1
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_M_AXI_MM2S_PROTOCOLAXI4
C_M_AXI_MM2S_SUPPORTS_THREADS0
C_M_AXI_MM2S_THREAD_ID_WIDTH1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST0
C_M_AXI_MM2S_SUPPORTS_READ1
C_M_AXI_MM2S_SUPPORTS_WRITE0
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING4
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH512
C_M_AXI_S2MM_PROTOCOLAXI4
C_M_AXI_S2MM_SUPPORTS_THREADS0
C_M_AXI_S2MM_THREAD_ID_WIDTH1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST0
C_M_AXI_S2MM_SUPPORTS_WRITE1
C_M_AXI_S2MM_SUPPORTS_READ0
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING4
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH512
C_M_AXIS_MM2S_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_S_AXIS_S2MM_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_M_AXIS_CNTRL_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_S_AXIS_STS_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_INTERCONNECT_S_AXI_LITE_AW_REGISTER1
C_INTERCONNECT_S_AXI_LITE_AR_REGISTER1
C_INTERCONNECT_S_AXI_LITE_W_REGISTER1
C_INTERCONNECT_S_AXI_LITE_R_REGISTER1
C_INTERCONNECT_S_AXI_LITE_B_REGISTER1
C_INTERCONNECT_M_AXI_SG_AW_REGISTER1
C_INTERCONNECT_M_AXI_SG_AR_REGISTER1
C_INTERCONNECT_M_AXI_SG_W_REGISTER1
C_INTERCONNECT_M_AXI_SG_R_REGISTER1
C_INTERCONNECT_M_AXI_SG_B_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_W_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_R_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_B_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_W_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_R_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+LEDs_4Bits +   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
+

+
LEDs_4Bits IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_OO1LEDs_4Bits_TRI_O
1S_AXI_ACLKI1clk_50_0000MHzPLL0
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_BASEADDR0x40020000
C_HIGHADDR0x4002FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS0
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT0
C_DOUT_DEFAULT0x00000000
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+Push_Buttons_4Bits +   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
+

+
Push_Buttons_4Bits IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_II1Push_Buttons_4Bits_TRI_I
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2IP2INTC_IrptO1Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_BASEADDR0x40000000
C_HIGHADDR0x4000FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS1
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT1
C_DOUT_DEFAULT0x00000000
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+RS232_Uart_1 +   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_uartlite1.01.aIP
+

+
RS232_Uart_1 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0TXO1RS232_Uart_1_sout
1RXI1RS232_Uart_1_sin
2S_AXI_ACLKI1clk_50_0000MHzPLL0
3InterruptO1RS232_Uart_1_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x40600000
C_HIGHADDR0x4060FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_BAUDRATE115200
C_DATA_BITS8
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_USE_PARITY0
C_ODD_PARITY1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+axi_timer_0 +   AXI Timer/Counter
Timer counter with AXI interface

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_timer1.01.aIP
+

+
axi_timer_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1InterruptO1axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_FAMILYvirtex6
C_COUNT_WIDTH32
C_ONE_TIMER_ONLY0
C_TRIG0_ASSERT1
C_TRIG1_ASSERT1
 
 + + + + + + + + + + + + + + + + + + + + +
NameValue
C_GEN0_ASSERT1
C_GEN1_ASSERT1
C_BASEADDR0x41C00000
C_HIGHADDR0x41C0FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
IPTOP
+
+ + + + +
+ + + + + + + + + +
+clock_generator_0 +   Clock Generator
Clock generator for processor system.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
clock_generator4.01.aIP
+

+
clock_generator_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0RSTI1RESET
1CLKINI1CLK
2CLKOUT2O1clk_100_0000MHzPLL0
3CLKOUT5O1clk_50_0000MHzPLL0
4CLKOUT3O1clk_125_0000MHz
5CLKOUT4O1clk_200_0000MHzPLL0
6CLKOUT0O1clk_600_0000MHzPLL0_nobuf
7CLKOUT1O1clk_600_0000MHz180PLL0_nobuf
8LOCKEDO1proc_sys_reset_0_Dcm_locked
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_DEVICENOT_SET
C_PACKAGENOT_SET
C_SPEEDGRADENOT_SET
C_CLKIN_FREQ200000000
C_CLKOUT0_FREQ600000000
C_CLKOUT0_PHASE0
C_CLKOUT0_GROUPPLL0
C_CLKOUT0_BUFFALSE
C_CLKOUT0_VARIABLE_PHASEFALSE
C_CLKOUT1_FREQ600000000
C_CLKOUT1_PHASE180
C_CLKOUT1_GROUPPLL0
C_CLKOUT1_BUFFALSE
C_CLKOUT1_VARIABLE_PHASEFALSE
C_CLKOUT2_FREQ100000000
C_CLKOUT2_PHASE0
C_CLKOUT2_GROUPPLL0
C_CLKOUT2_BUFTRUE
C_CLKOUT2_VARIABLE_PHASEFALSE
C_CLKOUT3_FREQ125000000
C_CLKOUT3_PHASE0
C_CLKOUT3_GROUPNONE
C_CLKOUT3_BUFTRUE
C_CLKOUT3_VARIABLE_PHASEFALSE
C_CLKOUT4_FREQ200000000
C_CLKOUT4_PHASE0
C_CLKOUT4_GROUPPLL0
C_CLKOUT4_BUFTRUE
C_CLKOUT4_VARIABLE_PHASEFALSE
C_CLKOUT5_FREQ50000000
C_CLKOUT5_PHASE0
C_CLKOUT5_GROUPPLL0
C_CLKOUT5_BUFTRUE
C_CLKOUT5_VARIABLE_PHASEFALSE
C_CLKOUT6_FREQ0
C_CLKOUT6_PHASE0
C_CLKOUT6_GROUPNONE
C_CLKOUT6_BUFTRUE
C_CLKOUT6_VARIABLE_PHASEFALSE
C_CLKOUT7_FREQ0
C_CLKOUT7_PHASE0
C_CLKOUT7_GROUPNONE
C_CLKOUT7_BUFTRUE
C_CLKOUT7_VARIABLE_PHASEFALSE
C_CLKOUT8_FREQ0
C_CLKOUT8_PHASE0
C_CLKOUT8_GROUPNONE
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_CLKOUT8_BUFTRUE
C_CLKOUT8_VARIABLE_PHASEFALSE
C_CLKOUT9_FREQ0
C_CLKOUT9_PHASE0
C_CLKOUT9_GROUPNONE
C_CLKOUT9_BUFTRUE
C_CLKOUT9_VARIABLE_PHASEFALSE
C_CLKOUT10_FREQ0
C_CLKOUT10_PHASE0
C_CLKOUT10_GROUPNONE
C_CLKOUT10_BUFTRUE
C_CLKOUT10_VARIABLE_PHASEFALSE
C_CLKOUT11_FREQ0
C_CLKOUT11_PHASE0
C_CLKOUT11_GROUPNONE
C_CLKOUT11_BUFTRUE
C_CLKOUT11_VARIABLE_PHASEFALSE
C_CLKOUT12_FREQ0
C_CLKOUT12_PHASE0
C_CLKOUT12_GROUPNONE
C_CLKOUT12_BUFTRUE
C_CLKOUT12_VARIABLE_PHASEFALSE
C_CLKOUT13_FREQ0
C_CLKOUT13_PHASE0
C_CLKOUT13_GROUPNONE
C_CLKOUT13_BUFTRUE
C_CLKOUT13_VARIABLE_PHASEFALSE
C_CLKOUT14_FREQ0
C_CLKOUT14_PHASE0
C_CLKOUT14_GROUPNONE
C_CLKOUT14_BUFTRUE
C_CLKOUT14_VARIABLE_PHASEFALSE
C_CLKOUT15_FREQ0
C_CLKOUT15_PHASE0
C_CLKOUT15_GROUPNONE
C_CLKOUT15_BUFTRUE
C_CLKOUT15_VARIABLE_PHASEFALSE
C_CLKFBIN_FREQ0
C_CLKFBIN_DESKEWNONE
C_CLKFBOUT_FREQ0
C_CLKFBOUT_PHASE0
C_CLKFBOUT_GROUPNONE
C_CLKFBOUT_BUFTRUE
C_PSDONE_GROUPNONE
C_EXT_RESET_HIGH1
C_CLK_PRIMITIVE_FEEDBACK_BUFFALSE
C_CLK_GENUPDATE
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+proc_sys_reset_0 +   Processor System Reset Module
Reset management module

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
proc_sys_reset3.00.aIP
+

+
proc_sys_reset_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0Ext_Reset_InI1RESET
1MB_ResetO1proc_sys_reset_0_MB_Reset
2Slowest_sync_clkI1clk_50_0000MHzPLL0
3Interconnect_aresetnO1proc_sys_reset_0_Interconnect_aresetn
4Dcm_lockedI1proc_sys_reset_0_Dcm_locked
5MB_Debug_Sys_RstI1proc_sys_reset_0_MB_Debug_Sys_Rst
6BUS_STRUCT_RESETO1proc_sys_reset_0_BUS_STRUCT_RESET
+

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
NameValue
C_SUBFAMILYlx
C_EXT_RST_WIDTH4
C_AUX_RST_WIDTH4
C_EXT_RESET_HIGH1
C_AUX_RESET_HIGH1
C_NUM_BUS_RST1
C_NUM_PERP_RST1
C_NUM_INTERCONNECT_ARESETN1
C_NUM_PERP_ARESETN1
C_FAMILYvirtex5
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
Timing InformationTOP
+

+ + + +
Post Synthesis Clock Limits
+ No clocks could be identified in the design. Run platgen to generate synthesis information. +
+
+ diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html new file mode 100644 index 000000000..6cc23975e --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html @@ -0,0 +1,5994 @@ + + + + +XPS Project Report + + + + + + + +
TABLE OF CONTENTS
+
Overview
Block Diagram
External Ports
Processor
   microblaze_0
Debuggers
   debug_module
Interrupt Controllers
   microblaze_0_intc
Busses
   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb
Memory
   microblaze_0_bram_block
Memory Controllers
   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl
Peripherals
   ETHERNET
   ETHERNET_dma
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0
IP
   clock_generator_0
   proc_sys_reset_0
Timing Information +
+ + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
OverviewTOC
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Resources Used
1  MicroBlaze
2  AXI Interconnect
2  Local Memory Bus (LMB) 1.0
1  Block RAM (BRAM) Block
2  LMB BRAM Controller
1  AXI S6 Memory Controller(DDR/DDR2/DDR3)
1  Processor System Reset Module
1  Clock Generator
1  MicroBlaze Debug Module (MDM)
1  AXI UART (Lite)
2  AXI General Purpose IO
1  AXI Ethernet
1  AXI DMA Engine
1  AXI Interrupt Controller
1  AXI Timer/Counter
 + + + + + + + + + + + + + + +
Specifics
GeneratedSat Aug 27 12:49:18 2011
EDK Version13.1
Device Familyspartan6
Devicexc6slx45tfgg484-3
+
+
+ + +
Block DiagramTOC
+
BlockDiagram +
+ + + +
External PortsTOC
+
+ + + + + + +
+ These are the external ports defined in the MHS file. +
+Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+SHARED +RESETI1RESET RESET 
+ETHERNET +ETHERNET_MII_TX_CLKI1ETHERNET_MII_TX_CLK
+ETHERNET +ETHERNET_RXDI0:7ETHERNET_RXD
+ETHERNET +ETHERNET_RX_CLKI1ETHERNET_RX_CLK
+ETHERNET +ETHERNET_RX_DVI1ETHERNET_RX_DV
+ETHERNET +ETHERNET_RX_ERI1ETHERNET_RX_ER
+ETHERNET +ETHERNET_MDIOIO1ETHERNET_MDIO
+ETHERNET +ETHERNET_MDCO1ETHERNET_MDC
+ETHERNET +ETHERNET_PHY_RST_NO1ETHERNET_PHY_RST_N
+ETHERNET +ETHERNET_TXDO0:7ETHERNET_TXD
+ETHERNET +ETHERNET_TX_CLKO1ETHERNET_TX_CLK
+ETHERNET +ETHERNET_TX_ENO1ETHERNET_TX_EN
+ETHERNET +ETHERNET_TX_ERO1ETHERNET_TX_ER
+LEDs_4Bits +LEDs_4Bits_TRI_OO0:3LEDs_4Bits_TRI_O
+MCB_DDR3 +mcbx_dram_dqIO0:15mcbx_dram_dq
+MCB_DDR3 +mcbx_dram_dqsIO1mcbx_dram_dqs
+MCB_DDR3 +mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
+MCB_DDR3 +mcbx_dram_udqsIO1mcbx_dram_udqs
+MCB_DDR3 +mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
+MCB_DDR3 +rzqIO1rzq
+MCB_DDR3 +zioIO1zio
+MCB_DDR3 +mcbx_dram_addrO0:12mcbx_dram_addr
+MCB_DDR3 +mcbx_dram_baO0:2mcbx_dram_ba
+MCB_DDR3 +mcbx_dram_cas_nO1mcbx_dram_cas_n
+MCB_DDR3 +mcbx_dram_ckeO1mcbx_dram_cke
+MCB_DDR3 +mcbx_dram_clkO1mcbx_dram_clk
+MCB_DDR3 +mcbx_dram_clk_nO1mcbx_dram_clk_n
+MCB_DDR3 +mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
+MCB_DDR3 +mcbx_dram_ldmO1mcbx_dram_ldm
+MCB_DDR3 +mcbx_dram_odtO1mcbx_dram_odt
+MCB_DDR3 +mcbx_dram_ras_nO1mcbx_dram_ras_n
+MCB_DDR3 +mcbx_dram_udmO1mcbx_dram_udm
+MCB_DDR3 +mcbx_dram_we_nO1mcbx_dram_we_n
+Push_Buttons_4Bits +Push_Buttons_4Bits_TRI_II0:3Push_Buttons_4Bits_TRI_I
+RS232_Uart_1 +RS232_Uart_1_sinI1RS232_Uart_1_sin
+RS232_Uart_1 +RS232_Uart_1_soutO1RS232_Uart_1_sout
+clock_generator_0 +CLK_NI1CLK CLK 
+clock_generator_0 +CLK_PI1CLK CLK 
+
+

+ + +
ProcessorsTOC
+
+ + +
+ + + + + + + + + +
+microblaze_0 +   MicroBlaze
The MicroBlaze 32 bit soft processor

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
microblaze8.10.aIP
+

+
microblaze_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0MB_RESETI1proc_sys_reset_0_MB_Reset
1CLKI1clk_100_0000MHzPLL0
2INTERRUPTI1microblaze_0_interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXI_DPMASTERAXIaxi4lite_08 Peripherals.
DLMBMASTERLMBmicroblaze_0_dlmbmicroblaze_0_d_bram_ctrl
ILMBMASTERLMBmicroblaze_0_ilmbmicroblaze_0_i_bram_ctrl
DEBUGTARGETXIL_MBDEBUG3microblaze_0_debugdebug_module
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_SCO0
C_FREQ0
C_DATA_SIZE32
C_DYNAMIC_BUS_SIZING1
C_FAMILYvirtex5
C_INSTANCEmicroblaze
C_FAULT_TOLERANT0
C_ECC_USE_CE_EXCEPTION0
C_ENDIANNESS0
C_AREA_OPTIMIZED0
C_OPTIMIZATION0
C_INTERCONNECT2
C_STREAM_INTERCONNECT0
C_DPLB_DWIDTH32
C_DPLB_NATIVE_DWIDTH32
C_DPLB_BURST_EN0
C_DPLB_P2P0
C_IPLB_DWIDTH32
C_IPLB_NATIVE_DWIDTH32
C_IPLB_BURST_EN0
C_IPLB_P2P0
C_M_AXI_DP_SUPPORTS_THREADS0
C_M_AXI_DP_THREAD_ID_WIDTH1
C_M_AXI_DP_SUPPORTS_READ1
C_M_AXI_DP_SUPPORTS_WRITE1
C_M_AXI_DP_SUPPORTS_NARROW_BURST0
C_M_AXI_DP_DATA_WIDTH32
C_M_AXI_DP_ADDR_WIDTH32
C_M_AXI_DP_PROTOCOLAXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING1
C_M_AXI_IP_SUPPORTS_THREADS0
C_M_AXI_IP_THREAD_ID_WIDTH1
C_M_AXI_IP_SUPPORTS_READ1
C_M_AXI_IP_SUPPORTS_WRITE0
C_M_AXI_IP_SUPPORTS_NARROW_BURST0
C_M_AXI_IP_DATA_WIDTH32
C_M_AXI_IP_ADDR_WIDTH32
C_M_AXI_IP_PROTOCOLAXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING1
C_D_AXI0
C_D_PLB0
C_D_LMB1
C_I_AXI0
C_I_PLB0
C_I_LMB1
C_USE_MSR_INSTR1
C_USE_PCMP_INSTR1
C_USE_BARREL1
C_USE_DIV0
C_USE_HW_MUL1
C_USE_FPU0
C_UNALIGNED_EXCEPTIONS0
C_ILL_OPCODE_EXCEPTION0
C_M_AXI_I_BUS_EXCEPTION0
C_M_AXI_D_BUS_EXCEPTION0
C_IPLB_BUS_EXCEPTION0
C_DPLB_BUS_EXCEPTION0
C_DIV_ZERO_EXCEPTION0
C_FPU_EXCEPTION0
C_FSL_EXCEPTION0
C_USE_STACK_PROTECTION0
C_PVR0
C_PVR_USER10x00
C_PVR_USER20x00000000
C_DEBUG_ENABLED1
C_NUMBER_OF_PC_BRK7
C_NUMBER_OF_RD_ADDR_BRK2
C_NUMBER_OF_WR_ADDR_BRK2
C_INTERRUPT_IS_EDGE0
C_EDGE_IS_POSITIVE1
C_RESET_MSR0x00000000
C_OPCODE_0x0_ILLEGAL0
C_FSL_LINKS0
C_FSL_DATA_SIZE32
C_USE_EXTENDED_FSL_INSTR0
C_M0_AXIS_PROTOCOLGENERIC
C_S0_AXIS_PROTOCOLGENERIC
C_M1_AXIS_PROTOCOLGENERIC
C_S1_AXIS_PROTOCOLGENERIC
C_M2_AXIS_PROTOCOLGENERIC
C_S2_AXIS_PROTOCOLGENERIC
C_M3_AXIS_PROTOCOLGENERIC
C_S3_AXIS_PROTOCOLGENERIC
C_M4_AXIS_PROTOCOLGENERIC
C_S4_AXIS_PROTOCOLGENERIC
C_M5_AXIS_PROTOCOLGENERIC
C_S5_AXIS_PROTOCOLGENERIC
C_M6_AXIS_PROTOCOLGENERIC
C_S6_AXIS_PROTOCOLGENERIC
C_M7_AXIS_PROTOCOLGENERIC
C_S7_AXIS_PROTOCOLGENERIC
C_M8_AXIS_PROTOCOLGENERIC
C_S8_AXIS_PROTOCOLGENERIC
C_M9_AXIS_PROTOCOLGENERIC
C_S9_AXIS_PROTOCOLGENERIC
C_M10_AXIS_PROTOCOLGENERIC
C_S10_AXIS_PROTOCOLGENERIC
C_M11_AXIS_PROTOCOLGENERIC
C_S11_AXIS_PROTOCOLGENERIC
C_M12_AXIS_PROTOCOLGENERIC
C_S12_AXIS_PROTOCOLGENERIC
C_M13_AXIS_PROTOCOLGENERIC
C_S13_AXIS_PROTOCOLGENERIC
C_M14_AXIS_PROTOCOLGENERIC
C_S14_AXIS_PROTOCOLGENERIC
C_M15_AXIS_PROTOCOLGENERIC
C_S15_AXIS_PROTOCOLGENERIC
C_M0_AXIS_DATA_WIDTH32
C_S0_AXIS_DATA_WIDTH32
C_M1_AXIS_DATA_WIDTH32
C_S1_AXIS_DATA_WIDTH32
C_M2_AXIS_DATA_WIDTH32
C_S2_AXIS_DATA_WIDTH32
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_M3_AXIS_DATA_WIDTH32
C_S3_AXIS_DATA_WIDTH32
C_M4_AXIS_DATA_WIDTH32
C_S4_AXIS_DATA_WIDTH32
C_M5_AXIS_DATA_WIDTH32
C_S5_AXIS_DATA_WIDTH32
C_M6_AXIS_DATA_WIDTH32
C_S6_AXIS_DATA_WIDTH32
C_M7_AXIS_DATA_WIDTH32
C_S7_AXIS_DATA_WIDTH32
C_M8_AXIS_DATA_WIDTH32
C_S8_AXIS_DATA_WIDTH32
C_M9_AXIS_DATA_WIDTH32
C_S9_AXIS_DATA_WIDTH32
C_M10_AXIS_DATA_WIDTH32
C_S10_AXIS_DATA_WIDTH32
C_M11_AXIS_DATA_WIDTH32
C_S11_AXIS_DATA_WIDTH32
C_M12_AXIS_DATA_WIDTH32
C_S12_AXIS_DATA_WIDTH32
C_M13_AXIS_DATA_WIDTH32
C_S13_AXIS_DATA_WIDTH32
C_M14_AXIS_DATA_WIDTH32
C_S14_AXIS_DATA_WIDTH32
C_M15_AXIS_DATA_WIDTH32
C_S15_AXIS_DATA_WIDTH32
C_ICACHE_BASEADDR0xC0000000
C_ICACHE_HIGHADDR0xC7FFFFFF
C_USE_ICACHE0
C_ALLOW_ICACHE_WR1
C_ADDR_TAG_BITS17
C_CACHE_BYTE_SIZE8192
C_ICACHE_USE_FSL1
C_ICACHE_LINE_LEN4
C_ICACHE_ALWAYS_USED1
C_ICACHE_INTERFACE0
C_ICACHE_VICTIMS0
C_ICACHE_STREAMS0
C_ICACHE_FORCE_TAG_LUTRAM0
C_ICACHE_DATA_WIDTH0
C_M_AXI_IC_SUPPORTS_THREADS0
C_M_AXI_IC_THREAD_ID_WIDTH1
C_M_AXI_IC_SUPPORTS_READ1
C_M_AXI_IC_SUPPORTS_WRITE0
C_M_AXI_IC_SUPPORTS_NARROW_BURST0
C_M_AXI_IC_DATA_WIDTH32
C_M_AXI_IC_ADDR_WIDTH32
C_M_AXI_IC_PROTOCOLAXI4
C_M_AXI_IC_USER_VALUE0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS1
C_M_AXI_IC_AWUSER_WIDTH5
C_M_AXI_IC_ARUSER_WIDTH5
C_M_AXI_IC_WUSER_WIDTH1
C_M_AXI_IC_RUSER_WIDTH1
C_M_AXI_IC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING2
C_DCACHE_BASEADDR0xC0000000
C_DCACHE_HIGHADDR0xC7FFFFFF
C_USE_DCACHE0
C_ALLOW_DCACHE_WR1
C_DCACHE_ADDR_TAG17
C_DCACHE_BYTE_SIZE8192
C_DCACHE_USE_FSL1
C_DCACHE_LINE_LEN4
C_DCACHE_ALWAYS_USED1
C_DCACHE_INTERFACE0
C_DCACHE_USE_WRITEBACK0
C_DCACHE_VICTIMS0
C_DCACHE_FORCE_TAG_LUTRAM0
C_DCACHE_DATA_WIDTH0
C_M_AXI_DC_SUPPORTS_THREADS0
C_M_AXI_DC_THREAD_ID_WIDTH1
C_M_AXI_DC_SUPPORTS_READ1
C_M_AXI_DC_SUPPORTS_WRITE1
C_M_AXI_DC_SUPPORTS_NARROW_BURST0
C_M_AXI_DC_DATA_WIDTH32
C_M_AXI_DC_ADDR_WIDTH32
C_M_AXI_DC_PROTOCOLAXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS0
C_M_AXI_DC_USER_VALUE0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS1
C_M_AXI_DC_AWUSER_WIDTH5
C_M_AXI_DC_ARUSER_WIDTH5
C_M_AXI_DC_WUSER_WIDTH1
C_M_AXI_DC_RUSER_WIDTH1
C_M_AXI_DC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING32
C_USE_MMU0
C_MMU_DTLB_SIZE4
C_MMU_ITLB_SIZE2
C_MMU_TLB_ACCESS3
C_MMU_ZONES16
C_MMU_PRIVILEGED_INSTR0
C_USE_INTERRUPT0
C_USE_EXT_BRK0
C_USE_EXT_NM_BRK0
C_USE_BRANCH_TARGET_CACHE0
C_BRANCH_TARGET_CACHE_SIZE0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER1
C_INTERCONNECT_M_AXI_DC_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER1
C_INTERCONNECT_M_AXI_DP_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_R_REGISTER1
C_INTERCONNECT_M_AXI_DP_B_REGISTER1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER1
C_INTERCONNECT_M_AXI_DC_R_REGISTER1
C_INTERCONNECT_M_AXI_DC_B_REGISTER1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER1
C_INTERCONNECT_M_AXI_IC_W_REGISTER1
C_INTERCONNECT_M_AXI_IC_R_REGISTER1
C_INTERCONNECT_M_AXI_IC_B_REGISTER1
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
DebuggersTOC
+
+ + +
+ + + + + + + + + +
+debug_module +   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
mdm2.00.bIP
+

+
debug_module IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1Debug_SYS_RstO1proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
MBDEBUG_0INITIATORXIL_MBDEBUG3microblaze_0_debugmicroblaze_0
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_JTAG_CHAIN2
C_INTERCONNECT2
C_BASEADDR0x74800000
C_HIGHADDR0x748FFFFF
C_SPLB_AWIDTH32
C_SPLB_DWIDTH32
C_SPLB_P2P0
C_SPLB_MID_WIDTH3
C_SPLB_NUM_MASTERS8
C_SPLB_NATIVE_DWIDTH32
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_SPLB_SUPPORT_BURSTS0
C_MB_DBG_PORTS1
C_USE_UART1
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
Interrupt ControllersTOC
+
+ + +
+ + + + + + + + + +
+microblaze_0_intc +   AXI Interrupt Controller
intc core attached to the AXI

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_intc1.01.aIP
+

+
microblaze_0_intc IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0IRQO1microblaze_0_interrupt
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2INTRI1ETHERNET_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut & Push_Buttons_4Bits_IP2INTC_Irpt & RS232_Uart_1_Interrupt & axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+Interrupt Priorities
PrioritySIGMODULE
0ETHERNET_INTERRUPTETHERNET
1ETHERNET_dma_mm2s_introutETHERNET_dma
2ETHERNET_dma_s2mm_introutETHERNET_dma
3Push_Buttons_4Bits_IP2INTC_IrptPush_Buttons_4Bits
4RS232_Uart_1_InterruptRS232_Uart_1
5axi_timer_0_Interruptaxi_timer_0
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_BASEADDR0x41200000
C_HIGHADDR0x4120FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_NUM_INTR_INPUTS2
C_KIND_OF_INTR0xFFFFFFFF
C_KIND_OF_EDGE0xFFFFFFFF
C_KIND_OF_LVL0xFFFFFFFF
C_HAS_IPR1
C_HAS_SIE1
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_HAS_CIE1
C_HAS_IVR1
C_IRQ_IS_LEVEL1
C_IRQ_ACTIVE1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
BussesTOC
+
+ + + + + + + + +
+ + + + + + + + + +
+axi4_0 +   AXI Interconnect
AXI4 Memory-Mapped Interconnect

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
+

+
axi4_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0interconnect_aclkI1clk_100_0000MHzPLL0
1INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
ETHERNET_dmaMASTERM_AXI_SG
ETHERNET_dmaMASTERM_AXI_MM2S
ETHERNET_dmaMASTERM_AXI_S2MM
MCB_DDR3SLAVES0_AXI
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE1
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+axi4lite_0 +   AXI Interconnect
AXI4 Memory-Mapped Interconnect

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
+

+
axi4lite_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
1INTERCONNECT_ACLKI1clk_50_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DP
debug_moduleSLAVES_AXI
RS232_Uart_1SLAVES_AXI
LEDs_4BitsSLAVES_AXI
Push_Buttons_4BitsSLAVES_AXI
ETHERNETSLAVES_AXI
ETHERNET_dmaSLAVES_AXI_LITE
microblaze_0_intcSLAVES_AXI
axi_timer_0SLAVES_AXI
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE0
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+microblaze_0_dlmb +   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
+

+
microblaze_0_dlmb IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERDLMB
microblaze_0_d_bram_ctrlSLAVESLMB
+

+
+ + + + + + + + + + + + + + + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+microblaze_0_ilmb +   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
+

+
microblaze_0_ilmb IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERILMB
microblaze_0_i_bram_ctrlSLAVESLMB
+

+
+ + + + + + + + + + + + + + + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
MemorysTOC
+
+ + +
+ + + + + + + + + +
+microblaze_0_bram_block +   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
bram_block1.00.aIP
+

+
microblaze_0_bram_block IP Image + + + + + + + + + + + + + + + + + + + + + +
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
PORTATARGETXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_i_bram_ctrl
PORTBTARGETXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_d_bram_ctrl
+

+
+ + + + + + + + + + + + + + + + + + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
NameValue
C_MEMSIZE2048
C_PORT_DWIDTH32
C_PORT_AWIDTH32
C_NUM_WE4
C_FAMILYvirtex2
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
Memory ControllersTOC
+
+ + + + + + +
+ + + + + + + + + +
+MCB_DDR3 +   AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_s6_ddrx1.02.aIP
+

+
MCB_DDR3 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0mcbx_dram_clkO1mcbx_dram_clk
1mcbx_dram_clk_nO1mcbx_dram_clk_n
2mcbx_dram_ckeO1mcbx_dram_cke
3mcbx_dram_odtO1mcbx_dram_odt
4mcbx_dram_ras_nO1mcbx_dram_ras_n
5mcbx_dram_cas_nO1mcbx_dram_cas_n
6mcbx_dram_we_nO1mcbx_dram_we_n
7mcbx_dram_udmO1mcbx_dram_udm
8mcbx_dram_ldmO1mcbx_dram_ldm
9mcbx_dram_baO1mcbx_dram_ba
10mcbx_dram_addrO1mcbx_dram_addr
11mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
12mcbx_dram_dqIO1mcbx_dram_dq
13mcbx_dram_dqsIO1mcbx_dram_dqs
14mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
15mcbx_dram_udqsIO1mcbx_dram_udqs
16mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
17rzqIO1rzq
18zioIO1zio
19s0_axi_aclkI1clk_100_0000MHzPLL0
20ui_clkI1clk_100_0000MHzPLL0
21sysclk_2xI1clk_600_0000MHzPLL0_nobuf
22sysclk_2x_180I1clk_600_0000MHz180PLL0_nobuf
23SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
24PLL_LOCKI1proc_sys_reset_0_Dcm_locked
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S0_AXISLAVEAXIaxi4_0ETHERNET_dma
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_MCB_LOCMEMC3
C_MCB_RZQ_LOCK7
C_MCB_ZIO_LOCR7
C_MCB_PERFORMANCESTANDARD
C_BYPASS_CORE_UCF0
C_S0_AXI_BASEADDR0x80000000
C_S0_AXI_HIGHADDR0x87FFFFFF
C_S1_AXI_BASEADDR0xFFFFFFFF
C_S1_AXI_HIGHADDR0x00000000
C_S2_AXI_BASEADDR0xFFFFFFFF
C_S2_AXI_HIGHADDR0x00000000
C_S3_AXI_BASEADDR0xFFFFFFFF
C_S3_AXI_HIGHADDR0x00000000
C_S4_AXI_BASEADDR0xFFFFFFFF
C_S4_AXI_HIGHADDR0x00000000
C_S5_AXI_BASEADDR0xFFFFFFFF
C_S5_AXI_HIGHADDR0x00000000
C_MEM_TYPEDDR3
C_MEM_PARTNOMT41J64M16XX-187E
C_MEM_BASEPARTNONOT_SET
C_NUM_DQ_PINS16
C_MEM_ADDR_WIDTH13
C_MEM_BANKADDR_WIDTH3
C_MEM_NUM_COL_BITS10
C_MEM_TRAS-1
C_MEM_TRCD-1
C_MEM_TREFI-1
C_MEM_TRFC-1
C_MEM_TRP-1
C_MEM_TWR-1
C_MEM_TRTP-1
C_MEM_TWTR-1
C_PORT_CONFIGB32_B32_B32_B32
C_SKIP_IN_TERM_CAL0
C_SKIP_IN_TERM_CAL_VALUENONE
C_MEMCLK_PERIOD0
C_MEM_ADDR_ORDERROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT512
C_MEM_CAS_LATENCY6
C_SIMULATIONFALSE
C_MEM_DDR1_2_ODSFULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR2_RTT150OHMS
C_MEM_DDR2_DIFF_DQS_ENYES
C_MEM_DDR2_3_PA_SRFULL
C_MEM_DDR2_3_HIGH_TEMP_SRNORMAL
C_MEM_DDR3_CAS_WR_LATENCY5
C_MEM_DDR3_CAS_LATENCY6
C_MEM_DDR3_ODSDIV6
C_MEM_DDR3_RTTDIV4
C_MEM_DDR3_AUTO_SRENABLED
C_MEM_MOBILE_PA_SRFULL
C_MEM_MDDR_ODSFULL
C_ARB_ALGORITHM0
C_ARB_NUM_TIME_SLOTS12
C_ARB_TIME_SLOT_00b000000000001010011
C_ARB_TIME_SLOT_10b000000001010011000
C_ARB_TIME_SLOT_20b000000010011000001
C_ARB_TIME_SLOT_30b000000011000001010
C_ARB_TIME_SLOT_40b000000000001010011
C_ARB_TIME_SLOT_50b000000001010011000
C_ARB_TIME_SLOT_60b000000010011000001
C_ARB_TIME_SLOT_70b000000011000001010
C_ARB_TIME_SLOT_80b000000000001010011
C_ARB_TIME_SLOT_90b000000001010011000
C_ARB_TIME_SLOT_100b000000010011000001
C_ARB_TIME_SLOT_110b000000011000001010
C_S0_AXI_ENABLE1
C_S0_AXI_PROTOCOLAXI4
C_S0_AXI_ID_WIDTH4
C_S0_AXI_ADDR_WIDTH32
C_S0_AXI_DATA_WIDTH32
C_S0_AXI_SUPPORTS_READ1
C_S0_AXI_SUPPORTS_WRITE1
C_S0_AXI_SUPPORTS_NARROW_BURST1
C_S0_AXI_REG_EN00x00000
C_S0_AXI_REG_EN10x01000
C_S0_AXI_STRICT_COHERENCY0
C_S0_AXI_ENABLE_AP0
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE4
C_S1_AXI_ENABLE0
C_S1_AXI_PROTOCOLAXI4
C_S1_AXI_ID_WIDTH4
C_S1_AXI_ADDR_WIDTH32
C_S1_AXI_DATA_WIDTH32
C_S1_AXI_SUPPORTS_READ1
C_S1_AXI_SUPPORTS_WRITE1
C_S1_AXI_SUPPORTS_NARROW_BURST1
C_S1_AXI_REG_EN00x00000
C_S1_AXI_REG_EN10x01000
C_S1_AXI_STRICT_COHERENCY1
C_S1_AXI_ENABLE_AP0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE4
C_S2_AXI_ENABLE0
C_S2_AXI_PROTOCOLAXI4
C_S2_AXI_ID_WIDTH4
C_S2_AXI_ADDR_WIDTH32
C_S2_AXI_DATA_WIDTH32
C_S2_AXI_SUPPORTS_READ1
C_S2_AXI_SUPPORTS_WRITE1
C_S2_AXI_SUPPORTS_NARROW_BURST1
C_S2_AXI_REG_EN00x00000
C_S2_AXI_REG_EN10x01000
C_S2_AXI_STRICT_COHERENCY1
C_S2_AXI_ENABLE_AP0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE4
C_S3_AXI_ENABLE0
C_S3_AXI_PROTOCOLAXI4
C_S3_AXI_ID_WIDTH4
C_S3_AXI_ADDR_WIDTH32
C_S3_AXI_DATA_WIDTH32
C_S3_AXI_SUPPORTS_READ1
C_S3_AXI_SUPPORTS_WRITE1
C_S3_AXI_SUPPORTS_NARROW_BURST1
C_S3_AXI_REG_EN00x00000
C_S3_AXI_REG_EN10x01000
C_S3_AXI_STRICT_COHERENCY1
C_S3_AXI_ENABLE_AP0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE4
C_S4_AXI_ENABLE0
C_S4_AXI_PROTOCOLAXI4
C_S4_AXI_ID_WIDTH4
C_S4_AXI_ADDR_WIDTH32
C_S4_AXI_DATA_WIDTH32
C_S4_AXI_SUPPORTS_READ1
C_S4_AXI_SUPPORTS_WRITE1
C_S4_AXI_SUPPORTS_NARROW_BURST1
C_S4_AXI_REG_EN00x00000
C_S4_AXI_REG_EN10x01000
C_S4_AXI_STRICT_COHERENCY1
C_S4_AXI_ENABLE_AP0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE4
C_S5_AXI_ENABLE0
C_S5_AXI_PROTOCOLAXI4
C_S5_AXI_ID_WIDTH4
C_S5_AXI_ADDR_WIDTH32
C_S5_AXI_DATA_WIDTH32
C_S5_AXI_SUPPORTS_READ1
C_S5_AXI_SUPPORTS_WRITE1
C_S5_AXI_SUPPORTS_NARROW_BURST1
C_S5_AXI_REG_EN00x00000
C_S5_AXI_REG_EN10x01000
C_S5_AXI_STRICT_COHERENCY1
C_S5_AXI_ENABLE_AP0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE4
C_MCB_USE_EXTERNAL_BUFPLL0
C_SYS_RST_PRESENT0
C_INTERCONNECT_S0_AXI_MASTERSETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
C_INTERCONNECT_S0_AXI_AW_REGISTER1
C_INTERCONNECT_S0_AXI_AR_REGISTER1
C_INTERCONNECT_S0_AXI_W_REGISTER1
C_INTERCONNECT_S0_AXI_R_REGISTER1
C_INTERCONNECT_S0_AXI_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+microblaze_0_d_bram_ctrl +   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
+

+
microblaze_0_d_bram_ctrl IP Image + + + + + + + + + + + + + + + + + + + + + +
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_dlmbmicroblaze_0
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+microblaze_0_i_bram_ctrl +   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
+

+
microblaze_0_i_bram_ctrl IP Image + + + + + + + + + + + + + + + + + + + + + +
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_ilmbmicroblaze_0
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
PeripheralsTOC
+
+ + + + + + + + + + + + +
+ + + + + + + + + +
+ETHERNET +   AXI Ethernet
AXI Ethernet MAC

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_ethernet2.01.aIP
+

+
ETHERNET IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0MDIOIO1ETHERNET_MDIO
1MDCO1ETHERNET_MDC
2GMII_TX_ERO1ETHERNET_TX_ER
3GMII_TXDO1ETHERNET_TXD
4GMII_TX_ENO1ETHERNET_TX_EN
5MII_TX_CLKI1ETHERNET_MII_TX_CLK
6GMII_TX_CLKO1ETHERNET_TX_CLK
7GMII_RXDI1ETHERNET_RXD
8GMII_RX_ERI1ETHERNET_RX_ER
9GMII_RX_CLKI1ETHERNET_RX_CLK
10GMII_RX_DVI1ETHERNET_RX_DV
11PHY_RST_NO1ETHERNET_PHY_RST_N
12S_AXI_ACLKI1clk_50_0000MHzPLL0
13GTX_CLKI1clk_125_0000MHz
14REF_CLKI1clk_200_0000MHzPLL0
15AXI_STR_TXD_ACLKI1clk_100_0000MHzPLL0
16AXI_STR_TXC_ACLKI1clk_100_0000MHzPLL0
17AXI_STR_RXD_ACLKI1clk_100_0000MHzPLL0
18AXI_STR_RXS_ACLKI1clk_100_0000MHzPLL0
19AXI_STR_TXD_ARESETNI1AXI_STR_TXD_ARESETN
20AXI_STR_TXC_ARESETNI1AXI_STR_TXC_ARESETN
21AXI_STR_RXD_ARESETNI1AXI_STR_RXD_ARESETN
22AXI_STR_RXS_ARESETNI1AXI_STR_RXS_ARESETN
23INTERRUPTO1ETHERNET_INTERRUPT
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
AXI_STR_RXSINITIATORAXISETHERNET_dma_rxsETHERNET_dma
AXI_STR_RXDINITIATORAXISETHERNET_dma_rxdETHERNET_dma
S_AXISLAVEAXIaxi4lite_08 Peripherals.
AXI_STR_TXDTARGETAXISETHERNET_dma_txdETHERNET_dma
AXI_STR_TXCTARGETAXISETHERNET_dma_txcETHERNET_dma
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_AXI_STR_TXC_TDATA_WIDTH32
C_AXI_STR_TXD_TDATA_WIDTH32
C_AXI_STR_RXS_TDATA_WIDTH32
C_AXI_STR_RXD_TDATA_WIDTH32
C_AXI_STR_TXC_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_TXD_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_AXI_STR_RXS_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_RXD_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_AXI_STR_AVBTX_PROTOCOLXIL_AXI_STREAM_ETH_AVB_TX
C_AXI_STR_AVBRX_PROTOCOLXIL_AXI_STREAM_ETH_AVB_RX
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x41240000
C_HIGHADDR0x4127FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_ID_WIDTH4
C_TRANSA
C_PHYADDR0B00001
C_INCLUDE_IO1
C_TYPE1
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_PHY_TYPE1
C_HALFDUP0
C_TXMEM4096
C_RXMEM4096
C_TXCSUM0
C_RXCSUM0
C_TXVLAN_TRAN0
C_RXVLAN_TRAN0
C_TXVLAN_TAG0
C_RXVLAN_TAG0
C_TXVLAN_STRP0
C_RXVLAN_STRP0
C_MCAST_EXTEND0
C_STATS0
C_AVB0
C_SIMULATION0
C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC0
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+ETHERNET_dma +   AXI DMA Engine
AXI MemoryMap to/from AXI Stream Direct Memory Access Engine

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_dma3.00.aIP
+

+
ETHERNET_dma IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0s_axi_lite_aclkI1clk_100_0000MHzPLL0
1m_axi_sg_aclkI1clk_100_0000MHzPLL0
2m_axi_mm2s_aclkI1clk_100_0000MHzPLL0
3m_axi_s2mm_aclkI1clk_100_0000MHzPLL0
4mm2s_prmry_reset_out_nO1AXI_STR_TXD_ARESETN
5mm2s_cntrl_reset_out_nO1AXI_STR_TXC_ARESETN
6s2mm_prmry_reset_out_nO1AXI_STR_RXD_ARESETN
7s2mm_sts_reset_out_nO1AXI_STR_RXS_ARESETN
8mm2s_introutO1ETHERNET_dma_mm2s_introut
9s2mm_introutO1ETHERNET_dma_s2mm_introut
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXIS_MM2SINITIATORAXISETHERNET_dma_txdETHERNET
M_AXIS_CNTRLINITIATORAXISETHERNET_dma_txcETHERNET
M_AXI_SGMASTERAXIaxi4_0MCB_DDR3
M_AXI_MM2SMASTERAXIaxi4_0MCB_DDR3
M_AXI_S2MMMASTERAXIaxi4_0MCB_DDR3
S_AXI_LITESLAVEAXIaxi4lite_08 Peripherals.
S_AXIS_STSTARGETAXISETHERNET_dma_rxsETHERNET
S_AXIS_S2MMTARGETAXISETHERNET_dma_rxdETHERNET
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_LITE_ADDR_WIDTH32
C_S_AXI_LITE_DATA_WIDTH32
C_DLYTMR_RESOLUTION1250
C_PRMRY_IS_ACLK_ASYNC0
C_SG_INCLUDE_DESC_QUEUE1
C_SG_INCLUDE_STSCNTRL_STRM1
C_SG_USE_STSAPP_LENGTH1
C_SG_LENGTH_WIDTH16
C_M_AXI_SG_ADDR_WIDTH32
C_M_AXI_SG_DATA_WIDTH32
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH32
C_S_AXIS_S2MM_STS_TDATA_WIDTH32
C_INCLUDE_MM2S1
C_INCLUDE_MM2S_DRE1
C_MM2S_BURST_SIZE16
C_M_AXI_MM2S_ADDR_WIDTH32
C_M_AXI_MM2S_DATA_WIDTH32
C_M_AXIS_MM2S_TDATA_WIDTH32
C_INCLUDE_S2MM1
C_INCLUDE_S2MM_DRE1
C_S2MM_BURST_SIZE16
C_M_AXI_S2MM_ADDR_WIDTH32
C_M_AXI_S2MM_DATA_WIDTH32
C_S_AXIS_S2MM_TDATA_WIDTH32
C_FAMILYvirtex6
C_BASEADDR0x41E00000
C_HIGHADDR0x41E0FFFF
C_S_AXI_LITE_ACLK_FREQ_HZ100000000
C_M_AXI_SG_ACLK_FREQ_HZ100000000
C_M_AXI_MM2S_ACLK_FREQ_HZ100000000
C_M_AXI_S2MM_ACLK_FREQ_HZ100000000
C_S_AXI_LITE_PROTOCOLAXI4LITE
C_S_AXI_LITE_SUPPORTS_READ1
C_S_AXI_LITE_SUPPORTS_WRITE1
C_M_AXI_SG_PROTOCOLAXI4
C_M_AXI_SG_SUPPORTS_THREADS0
C_M_AXI_SG_THREAD_ID_WIDTH1
C_M_AXI_SG_SUPPORTS_NARROW_BURST0
C_M_AXI_SG_SUPPORTS_READ1
C_M_AXI_SG_SUPPORTS_WRITE1
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_M_AXI_MM2S_PROTOCOLAXI4
C_M_AXI_MM2S_SUPPORTS_THREADS0
C_M_AXI_MM2S_THREAD_ID_WIDTH1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST0
C_M_AXI_MM2S_SUPPORTS_READ1
C_M_AXI_MM2S_SUPPORTS_WRITE0
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING4
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH512
C_M_AXI_S2MM_PROTOCOLAXI4
C_M_AXI_S2MM_SUPPORTS_THREADS0
C_M_AXI_S2MM_THREAD_ID_WIDTH1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST0
C_M_AXI_S2MM_SUPPORTS_WRITE1
C_M_AXI_S2MM_SUPPORTS_READ0
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING4
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH512
C_M_AXIS_MM2S_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_S_AXIS_S2MM_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_M_AXIS_CNTRL_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_S_AXIS_STS_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_INTERCONNECT_S_AXI_LITE_AW_REGISTER1
C_INTERCONNECT_S_AXI_LITE_AR_REGISTER1
C_INTERCONNECT_S_AXI_LITE_W_REGISTER1
C_INTERCONNECT_S_AXI_LITE_R_REGISTER1
C_INTERCONNECT_S_AXI_LITE_B_REGISTER1
C_INTERCONNECT_M_AXI_SG_AW_REGISTER1
C_INTERCONNECT_M_AXI_SG_AR_REGISTER1
C_INTERCONNECT_M_AXI_SG_W_REGISTER1
C_INTERCONNECT_M_AXI_SG_R_REGISTER1
C_INTERCONNECT_M_AXI_SG_B_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_W_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_R_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_B_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_W_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_R_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+LEDs_4Bits +   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
+

+
LEDs_4Bits IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_OO1LEDs_4Bits_TRI_O
1S_AXI_ACLKI1clk_50_0000MHzPLL0
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_BASEADDR0x40020000
C_HIGHADDR0x4002FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS0
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT0
C_DOUT_DEFAULT0x00000000
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+Push_Buttons_4Bits +   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
+

+
Push_Buttons_4Bits IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_II1Push_Buttons_4Bits_TRI_I
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2IP2INTC_IrptO1Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_BASEADDR0x40000000
C_HIGHADDR0x4000FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS1
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT1
C_DOUT_DEFAULT0x00000000
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+RS232_Uart_1 +   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_uartlite1.01.aIP
+

+
RS232_Uart_1 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0TXO1RS232_Uart_1_sout
1RXI1RS232_Uart_1_sin
2S_AXI_ACLKI1clk_50_0000MHzPLL0
3InterruptO1RS232_Uart_1_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x40600000
C_HIGHADDR0x4060FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_BAUDRATE115200
C_DATA_BITS8
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_USE_PARITY0
C_ODD_PARITY1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+axi_timer_0 +   AXI Timer/Counter
Timer counter with AXI interface

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
axi_timer1.01.aIP
+

+
axi_timer_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1InterruptO1axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + +
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_FAMILYvirtex6
C_COUNT_WIDTH32
C_ONE_TIMER_ONLY0
C_TRIG0_ASSERT1
C_TRIG1_ASSERT1
 
 + + + + + + + + + + + + + + + + + + + + +
NameValue
C_GEN0_ASSERT1
C_GEN1_ASSERT1
C_BASEADDR0x41C00000
C_HIGHADDR0x41C0FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
IPTOC
+
+ + + + +
+ + + + + + + + + +
+clock_generator_0 +   Clock Generator
Clock generator for processor system.

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
clock_generator4.01.aIP
+

+
clock_generator_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0RSTI1RESET
1CLKINI1CLK
2CLKOUT2O1clk_100_0000MHzPLL0
3CLKOUT5O1clk_50_0000MHzPLL0
4CLKOUT3O1clk_125_0000MHz
5CLKOUT4O1clk_200_0000MHzPLL0
6CLKOUT0O1clk_600_0000MHzPLL0_nobuf
7CLKOUT1O1clk_600_0000MHz180PLL0_nobuf
8LOCKEDO1proc_sys_reset_0_Dcm_locked
+

+
+ + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_FAMILYvirtex6
C_DEVICENOT_SET
C_PACKAGENOT_SET
C_SPEEDGRADENOT_SET
C_CLKIN_FREQ200000000
C_CLKOUT0_FREQ600000000
C_CLKOUT0_PHASE0
C_CLKOUT0_GROUPPLL0
C_CLKOUT0_BUFFALSE
C_CLKOUT0_VARIABLE_PHASEFALSE
C_CLKOUT1_FREQ600000000
C_CLKOUT1_PHASE180
C_CLKOUT1_GROUPPLL0
C_CLKOUT1_BUFFALSE
C_CLKOUT1_VARIABLE_PHASEFALSE
C_CLKOUT2_FREQ100000000
C_CLKOUT2_PHASE0
C_CLKOUT2_GROUPPLL0
C_CLKOUT2_BUFTRUE
C_CLKOUT2_VARIABLE_PHASEFALSE
C_CLKOUT3_FREQ125000000
C_CLKOUT3_PHASE0
C_CLKOUT3_GROUPNONE
C_CLKOUT3_BUFTRUE
C_CLKOUT3_VARIABLE_PHASEFALSE
C_CLKOUT4_FREQ200000000
C_CLKOUT4_PHASE0
C_CLKOUT4_GROUPPLL0
C_CLKOUT4_BUFTRUE
C_CLKOUT4_VARIABLE_PHASEFALSE
C_CLKOUT5_FREQ50000000
C_CLKOUT5_PHASE0
C_CLKOUT5_GROUPPLL0
C_CLKOUT5_BUFTRUE
C_CLKOUT5_VARIABLE_PHASEFALSE
C_CLKOUT6_FREQ0
C_CLKOUT6_PHASE0
C_CLKOUT6_GROUPNONE
C_CLKOUT6_BUFTRUE
C_CLKOUT6_VARIABLE_PHASEFALSE
C_CLKOUT7_FREQ0
C_CLKOUT7_PHASE0
C_CLKOUT7_GROUPNONE
C_CLKOUT7_BUFTRUE
C_CLKOUT7_VARIABLE_PHASEFALSE
C_CLKOUT8_FREQ0
C_CLKOUT8_PHASE0
C_CLKOUT8_GROUPNONE
 
 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
C_CLKOUT8_BUFTRUE
C_CLKOUT8_VARIABLE_PHASEFALSE
C_CLKOUT9_FREQ0
C_CLKOUT9_PHASE0
C_CLKOUT9_GROUPNONE
C_CLKOUT9_BUFTRUE
C_CLKOUT9_VARIABLE_PHASEFALSE
C_CLKOUT10_FREQ0
C_CLKOUT10_PHASE0
C_CLKOUT10_GROUPNONE
C_CLKOUT10_BUFTRUE
C_CLKOUT10_VARIABLE_PHASEFALSE
C_CLKOUT11_FREQ0
C_CLKOUT11_PHASE0
C_CLKOUT11_GROUPNONE
C_CLKOUT11_BUFTRUE
C_CLKOUT11_VARIABLE_PHASEFALSE
C_CLKOUT12_FREQ0
C_CLKOUT12_PHASE0
C_CLKOUT12_GROUPNONE
C_CLKOUT12_BUFTRUE
C_CLKOUT12_VARIABLE_PHASEFALSE
C_CLKOUT13_FREQ0
C_CLKOUT13_PHASE0
C_CLKOUT13_GROUPNONE
C_CLKOUT13_BUFTRUE
C_CLKOUT13_VARIABLE_PHASEFALSE
C_CLKOUT14_FREQ0
C_CLKOUT14_PHASE0
C_CLKOUT14_GROUPNONE
C_CLKOUT14_BUFTRUE
C_CLKOUT14_VARIABLE_PHASEFALSE
C_CLKOUT15_FREQ0
C_CLKOUT15_PHASE0
C_CLKOUT15_GROUPNONE
C_CLKOUT15_BUFTRUE
C_CLKOUT15_VARIABLE_PHASEFALSE
C_CLKFBIN_FREQ0
C_CLKFBIN_DESKEWNONE
C_CLKFBOUT_FREQ0
C_CLKFBOUT_PHASE0
C_CLKFBOUT_GROUPNONE
C_CLKFBOUT_BUFTRUE
C_PSDONE_GROUPNONE
C_EXT_RESET_HIGH1
C_CLK_PRIMITIVE_FEEDBACK_BUFFALSE
C_CLK_GENUPDATE
 
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+ + + + + + + + + +
+proc_sys_reset_0 +   Processor System Reset Module
Reset management module

+
+ + + + + + + + + + +
IP Specs
CoreVersionDocumentation
proc_sys_reset3.00.aIP
+

+
proc_sys_reset_0 IP Image + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#NAMEDIR[LSB:MSB]SIGNAL
0Ext_Reset_InI1RESET
1MB_ResetO1proc_sys_reset_0_MB_Reset
2Slowest_sync_clkI1clk_50_0000MHzPLL0
3Interconnect_aresetnO1proc_sys_reset_0_Interconnect_aresetn
4Dcm_lockedI1proc_sys_reset_0_Dcm_locked
5MB_Debug_Sys_RstI1proc_sys_reset_0_MB_Debug_Sys_Rst
6BUS_STRUCT_RESETO1proc_sys_reset_0_BUS_STRUCT_RESET
+

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Parameters
+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +
NameValue
C_SUBFAMILYlx
C_EXT_RST_WIDTH4
C_AUX_RST_WIDTH4
C_EXT_RESET_HIGH1
C_AUX_RESET_HIGH1
C_NUM_BUS_RST1
C_NUM_PERP_RST1
C_NUM_INTERCONNECT_ARESETN1
C_NUM_PERP_ARESETN1
C_FAMILYvirtex5
+ + + + +
Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +
+
+

+
+
+

+ + +
Timing InformationTOC
+

+ + + +
Post Synthesis Clock Limits
+ No clocks could be identified in the design. Run platgen to generate synthesis information. +
+
+ + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html new file mode 100644 index 000000000..88f408ceb --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html @@ -0,0 +1,73 @@ + + + + +Table of Contents + + + + +
+Overview
Block Diagram
External Ports
+ Processor +
+   microblaze_0
+ Debuggers +
+   debug_module
+ Interrupt Controllers +
+   microblaze_0_intc
+ Busses +
+   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb
+ Memory +
+   microblaze_0_bram_block
+ Memory Controllers +
+   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl
+ Peripherals +
+   ETHERNET
   ETHERNET_dma
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0
+ IP +
+   clock_generator_0
   proc_sys_reset_0
Timing Information
+
+ diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml index 2424c8119..7e444c01f 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml @@ -589,7 +589,7 @@ C_S0_AXI_STRICT_COHERENCY - "1" + "0" C_S0_AXI_SUPPORTS_NARROW_BURST diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log index 250c330b7..937512d97 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log @@ -1,6 +1,6 @@ ========================================================================= -Time: Fri Aug 26 20:58:58 GMT Daylight Time 2011 -Running: run_batch_mode 74543544 +Time: Sat Aug 27 12:49:03 GMT Daylight Time 2011 +Running: run_batch_mode 96333944 {COLLECTING: INSTANCE MCB_DDR3 } {COLLECTING: C_INTERCONNECT_S0_AXI_MASTERS ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM OPTIONAL string none ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} {COLLECTING: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } @@ -109,13 +109,13 @@ Running: run_batch_mode 74543544 {COLLECTING: C_S4_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } {COLLECTING: C_S5_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } {COLLECTING: C_S5_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_MEM_TYPE DDR3 OPTIONAL STRING DDR3 DDR3} +{COLLECTING: C_MEM_TYPE DDR3 OPTIONAL STRING DDR3 } {COLLECTING: C_MEM_PARTNO MT41J64M16XX-187E REQUIRE STRING NOT_SET MT41J64M16XX-187E} {COLLECTING: C_MEM_BASEPARTNO NOT_SET OPTIONAL STRING NOT_SET } {COLLECTING: C_NUM_DQ_PINS 16 OPTIONAL_UPDATE INTEGER 16 } {COLLECTING: C_MEM_ADDR_WIDTH 13 OPTIONAL_UPDATE INTEGER 13 } -{COLLECTING: C_MEM_BANKADDR_WIDTH 3 OPTIONAL_UPDATE INTEGER 3 3} -{COLLECTING: C_MEM_NUM_COL_BITS 10 OPTIONAL_UPDATE INTEGER 10 10} +{COLLECTING: C_MEM_BANKADDR_WIDTH 3 OPTIONAL_UPDATE INTEGER 3 } +{COLLECTING: C_MEM_NUM_COL_BITS 10 OPTIONAL_UPDATE INTEGER 10 } {COLLECTING: C_MEM_TRAS -1 OPTIONAL_UPDATE INTEGER -1 } {COLLECTING: C_MEM_TRCD -1 OPTIONAL_UPDATE INTEGER -1 } {COLLECTING: C_MEM_TREFI -1 OPTIONAL_UPDATE INTEGER -1 } @@ -125,7 +125,7 @@ Running: run_batch_mode 74543544 {COLLECTING: C_MEM_TRTP -1 OPTIONAL_UPDATE INTEGER -1 } {COLLECTING: C_MEM_TWTR -1 OPTIONAL_UPDATE INTEGER -1 } {COLLECTING: C_PORT_CONFIG B32_B32_B32_B32 OPTIONAL STRING B32_B32_B32_B32 } -{COLLECTING: C_SKIP_IN_TERM_CAL 0 OPTIONAL INTEGER 0 0} +{COLLECTING: C_SKIP_IN_TERM_CAL 0 OPTIONAL INTEGER 0 } {COLLECTING: C_SKIP_IN_TERM_CAL_VALUE NONE OPTIONAL STRING NONE } {COLLECTING: C_MEMCLK_PERIOD 0 OPTIONAL_UPDATE INTEGER 0 } {COLLECTING: C_MEM_ADDR_ORDER ROW_BANK_COLUMN OPTIONAL STRING ROW_BANK_COLUMN } @@ -160,7 +160,7 @@ Running: run_batch_mode 74543544 {COLLECTING: C_ARB_TIME_SLOT_9 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } {COLLECTING: C_ARB_TIME_SLOT_10 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } {COLLECTING: C_ARB_TIME_SLOT_11 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } -{COLLECTING: C_S0_AXI_ENABLE 1 OPTIONAL INTEGER 1 1} +{COLLECTING: C_S0_AXI_ENABLE 1 OPTIONAL INTEGER 1 } {COLLECTING: C_S0_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } {COLLECTING: C_S0_AXI_ID_WIDTH 2 UPDATE INTEGER 4 } {COLLECTING: C_S0_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } @@ -170,7 +170,7 @@ Running: run_batch_mode 74543544 {COLLECTING: C_S0_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } {COLLECTING: C_S0_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } {COLLECTING: C_S0_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S0_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S0_AXI_STRICT_COHERENCY 0 OPTIONAL_UPDATE INTEGER 1 0} {COLLECTING: C_S0_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } {COLLECTING: C_S1_AXI_ENABLE 0 OPTIONAL INTEGER 0 } {COLLECTING: C_S1_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } @@ -379,7 +379,7 @@ Running: run_batch_mode 74543544 {SENDING PARAMETER: C_S0_AXI_PROTOCOL : AXI4 STRING CONSTANT} {SENDING PARAMETER: C_S0_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} {SENDING PARAMETER: C_S0_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S0_AXI_STRICT_COHERENCY : 0 INTEGER OPTIONAL_UPDATE} {SENDING PARAMETER: C_S0_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} {SENDING PARAMETER: C_S0_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} {SENDING PARAMETER: C_S0_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} @@ -479,14 +479,14 @@ Running: run_batch_mode 74543544 {SET: IGNORE C_MEM_DDR2_DIFF_DQS_EN = YES (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_S2_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_S0_AXI_DATA_WIDTH = 32 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: CHECK C_MEM_NUM_COL_BITS = 10 (BATCH:OPTIONAL_UPDATE:CHECK:MHS:MPDVAL)} +{SET: CHECK C_MEM_NUM_COL_BITS = 10 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} {SET: IGNORE C_MEM_DDR3_RTT = DIV4 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: UPDREM C_MEM_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)} {SET: UPDATE C_MEM_TRFC = 160000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} {SET: IGNORE C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} {SET: UPDATE C_S3_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} {SET: IGNORE C_S0_AXI_SUPPORTS_NARROW_BURST = Auto (BATCH:OPTIONAL_UPDATE::MPD:DEFVAL)} -{SET: UPDREM C_S0_AXI_STRICT_COHERENCY = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} +{SET: IGNORE C_S0_AXI_STRICT_COHERENCY = 0 (BATCH:OPTIONAL_UPDATE::MHS:COMPVAL)} {SET: IGNORE C_ARB_TIME_SLOT_10 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} {SET: IGNORE C_INTERCONNECT_S0_AXI_SECURE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_ARB_TIME_SLOT_11 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} @@ -497,14 +497,14 @@ Running: run_batch_mode 74543544 {SET: UPDATE C_MEM_TREFI = 7800000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} {SET: IGNORE C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_ENABLE = 1 (BATCH:OPTIONAL::MHS:MPDVAL)} +{SET: IGNORE C_S0_AXI_ENABLE = 1 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_MEM_MOBILE_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_SKIP_IN_TERM_CAL = 0 (BATCH:OPTIONAL::MHS:MPDVAL)} +{SET: IGNORE C_SKIP_IN_TERM_CAL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_MEM_DDR2_3_HIGH_TEMP_SR = NORMAL (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: UPDREM C_S0_AXI_SUPPORTS_READ = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} {SET: IGNORE C_S0_AXI_HIGHADDR = 0x87ffffff (BATCH:OPTIONAL::MHS:COMPVAL)} {SET: IGNORE C_MEM_DDR1_2_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_TYPE = DDR3 (BATCH:OPTIONAL::MHS:MPDVAL)} +{SET: IGNORE C_MEM_TYPE = DDR3 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: CHECK C_MEM_ADDR_WIDTH = 13 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} {SET: UPDATE C_S5_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} {SET: UPDATE C_S4_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} @@ -521,7 +521,7 @@ Running: run_batch_mode 74543544 {SET: IGNORE C_INTERCONNECT_S0_AXI_W_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} {SET: IGNORE C_MEM_DDR2_RTT = 150OHMS (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_MCB_PERFORMANCE = STANDARD (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: CHECK C_MEM_BANKADDR_WIDTH = 3 (BATCH:OPTIONAL_UPDATE:CHECK:MHS:MPDVAL)} +{SET: CHECK C_MEM_BANKADDR_WIDTH = 3 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} {SET: IGNORE C_INTERCONNECT_S0_AXI_B_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} {SET: IGNORE C_SIMULATION = FALSE (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: UPDATE C_S1_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} @@ -561,7 +561,3 @@ Running: run_batch_mode 74543544 {SET: IGNORE C_MEM_PARTNO = MT41J64M16XX-187E (BATCH:REQUIRE::MHS:COMPVAL)} {SET: CHECK C_NUM_DQ_PINS = 16 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} RETURN: 0 -========================================================================= -Time: Fri Aug 26 20:59:03 GMT Daylight Time 2011 -Running: generate_corelevel_constraints 74543544 -RETURN: diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport index 475832950..452c0cddf 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport @@ -1,9 +1,9 @@

- 2011-08-26T20:58:42 + 2011-08-27T11:01:38 system - 2011-08-26T20:58:42 + 2011-08-27T11:01:38 C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport filter.filter C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml index 63bbe247f..e70dd10d5 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml @@ -1,47 +1,7 @@ - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -50,7 +10,6 @@ - @@ -271,6 +230,7 @@ + AXI Interconnect @@ -278,7 +238,6 @@ - @@ -293,7 +252,7 @@ - + @@ -499,6 +458,7 @@ + MicroBlaze @@ -506,7 +466,6 @@ - @@ -2519,18 +2478,21 @@ + + + - + - + - + @@ -2583,9 +2545,7 @@ - - - + Local Memory Bus (LMB) 1.0 @@ -2593,7 +2553,6 @@ - @@ -2631,6 +2590,7 @@ + Local Memory Bus (LMB) 1.0 @@ -2638,7 +2598,6 @@ - @@ -2676,6 +2635,7 @@ + LMB BRAM Controller @@ -2683,10 +2643,9 @@ - - + @@ -2898,7 +2857,7 @@ - + @@ -2914,6 +2873,7 @@ + LMB BRAM Controller @@ -2921,10 +2881,9 @@ - - + @@ -3136,7 +3095,7 @@ - + @@ -3152,6 +3111,7 @@ + Block RAM (BRAM) Block @@ -3159,9 +3119,8 @@ - - + @@ -3207,6 +3166,7 @@ + Processor System Reset Module @@ -3214,7 +3174,6 @@ - @@ -3276,6 +3235,7 @@ + Clock Generator @@ -3283,7 +3243,6 @@ - @@ -3409,6 +3368,7 @@ + MicroBlaze Debug Module (MDM) @@ -3416,13 +3376,12 @@ - - + @@ -3768,13 +3727,14 @@ - + + AXI UART (Lite) @@ -3782,7 +3742,6 @@ - @@ -3862,6 +3821,9 @@ + + + @@ -3869,9 +3831,7 @@ - - - + AXI General Purpose IO @@ -3879,7 +3839,6 @@ - @@ -3983,6 +3942,7 @@ + AXI General Purpose IO @@ -3990,7 +3950,6 @@ - @@ -4087,6 +4046,9 @@ + + + @@ -4094,9 +4056,7 @@ - - - + AXI S6 Memory Controller(DDR/DDR2/DDR3) @@ -4104,15 +4064,14 @@ - - - + + @@ -4123,13 +4082,13 @@ - - + + - - + + @@ -4139,7 +4098,7 @@ - + @@ -4174,7 +4133,7 @@ - + @@ -4184,7 +4143,7 @@ - + @@ -4260,12 +4219,12 @@ - - - - - - + + + + + + @@ -4857,6 +4816,7 @@ + AXI Ethernet @@ -4864,7 +4824,6 @@ - @@ -5177,6 +5136,9 @@ + + + @@ -5184,9 +5146,7 @@ - - - + AXI DMA Engine @@ -5194,7 +5154,6 @@ - @@ -5530,6 +5489,10 @@ + + + + @@ -5537,10 +5500,7 @@ - - - - + AXI Interrupt Controller @@ -5548,7 +5508,6 @@ - @@ -5632,13 +5591,6 @@ - - - - - - - @@ -5648,6 +5600,14 @@ + + + + + + + + AXI Timer/Counter @@ -5655,7 +5615,6 @@ - @@ -5733,6 +5692,9 @@ + + + @@ -5740,10 +5702,49 @@ - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters index d4000c0c3..42835f226 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters @@ -1,10 +1,11 @@ + - + @@ -93,8 +94,8 @@ - - + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui index 0f1452183..f9ab6d94b 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui @@ -6,16 +6,18 @@ - + - + - + - + + + @@ -96,6 +98,7 @@ + @@ -109,16 +112,17 @@ - - + + - + - + + @@ -189,12 +193,19 @@ - + + - - + + + + + + + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html index c14fba7dd..7ac689bd4 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html @@ -2,7 +2,7 @@ - + @@ -19,7 +19,7 @@ No Errors - +
Project Status (08/27/2011 - 07:43:24)
Project Status (08/27/2011 - 12:37:45)
Project File: system.xmp
Product Version:EDK 13.1
  • Warnings:
238 Warnings (237 new)238 Warnings (0 new)
@@ -29,16 +29,23 @@ No Errors XPS Reports [-] Report NameGenerated ErrorsWarningsInfos -Platgen Log FileFri 26. Aug 21:18:30 2011019 Warnings (19 new)35 Infos (35 new) +Platgen Log FileSat 27. Aug 12:17:02 2011019 Warnings (18 new)34 Infos (32 new) Libgen Log File     Simgen Log File     BitInit Log File     -System Log FileFri 26. Aug 21:36:10 2011    +System Log FileSat 27. Aug 12:34:09 2011     
- + + + + + + + + @@ -55,20 +62,13 @@ No Errors - - - - - - - @@ -109,31 +109,31 @@ No Errors - + - + - + - + - + @@ -223,13 +223,13 @@ No Errors - + - + @@ -247,33 +247,33 @@ No Errors - + - + - + - - - + + + - - + + - - - + + + @@ -307,9 +307,9 @@ No Errors - + - + @@ -511,7 +511,7 @@ No Errors - + @@ -548,18 +548,18 @@ No Errors - - - - - + + + + +
XPS Synthesis Summary (estimated values) [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
systemFri 26. Aug 21:19:20 20111469614249420
systemSat 27. Aug 12:17:50 20111469614247140
mcb_ddr3_wrapperSat 27. Aug 12:16:50 2011373690 0
debug_module_wrapperSat 27. Aug 12:16:27 2011131142 0
clock_generator_0_wrapperSat 27. Aug 12:16:17 2011 1 0
microblaze_0_bram_block_wrapperSat 27. Aug 12:16:12 2011  40
microblaze_0_d_bram_ctrl_wrapperSat 27. Aug 12:16:06 201126 0
microblaze_0_i_bram_ctrl_wrapperSat 27. Aug 12:16:01 201126 0
axi4lite_0_wrapperSat 27. Aug 12:15:55 201129051827 0
axi_timer_0_wrapperFri 26. Aug 21:17:55 2011260272 0
microblaze_0_intc_wrapperFri 26. Aug 21:17:45 201186115 0
ethernet_dma_wrapperFri 26. Aug 21:17:37 201137283798 0
ethernet_wrapper_blk_mem_gen_v5_2_1_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:07:03 2011  20
ethernet_wrapper_blk_mem_gen_v5_2_4_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:06:36 2011  10
ethernet_wrapper_blk_mem_gen_v5_2_3_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:06:10 201124920
mcb_ddr3_wrapperFri 26. Aug 21:04:44 2011373691 0
push_buttons_4bits_wrapperFri 26. Aug 21:04:24 20117285 0
leds_4bits_wrapperFri 26. Aug 21:04:14 20113341 0
rs232_uart_1_wrapperFri 26. Aug 21:04:05 201184102 0
debug_module_wrapperFri 26. Aug 21:03:57 2011131142 0
clock_generator_0_wrapperFri 26. Aug 21:03:48 2011 1 0
proc_sys_reset_0_wrapperFri 26. Aug 21:03:43 20116955 0
microblaze_0_bram_block_wrapperFri 26. Aug 21:03:37 2011  320
microblaze_0_d_bram_ctrl_wrapperFri 26. Aug 21:03:30 201126 0
microblaze_0_i_bram_ctrl_wrapperFri 26. Aug 21:03:25 201126 0
microblaze_0_dlmb_wrapperFri 26. Aug 21:03:19 201111 0
microblaze_0_ilmb_wrapperFri 26. Aug 21:03:15 201111 0
microblaze_0_wrapperFri 26. Aug 21:03:10 201113011703 0
axi4lite_0_wrapperFri 26. Aug 21:02:41 201129051828 0
axi4_0_wrapperFri 26. Aug 21:02:14 201114881083 0
axi4_0_wrapper_FIFO_GENERATOR_V8_1_2_fifo_generator_v8_1_xst_1Fri 26. Aug 21:01:57 2011909720
axi4_0_wrapper_FIFO_GENERATOR_V8_1_1_fifo_generator_v8_1_xst_1Fri 26. Aug 21:00:49 2011899610
 
Number of Slice LUTs10,97310,940 27,288 40%  
    Number used as logic9,6419,639 27,288 35%  
        Number using O6 output only6,8876,889      
        Number using O5 output only261260      
        Number using O5 and O62,4932,490        
    Number used exclusively as route-thrus639608      
        Number with same-slice register load597566        
Number of occupied Slices4,5204,589 6,82266%67%  
Number of LUT Flip Flop pairs used13,73113,843      
    Number with an unused Flip Flop3,68613,73126%3,76513,84327%  
    Number with an unused LUT2,75813,7312,90313,843 20%  
    Number of fully used LUT-FF pairs7,28713,73153%7,17513,84351%  
    Number of unique control sets  
Number of RAMB16BWERs4012 11634%10%  
Number of RAMB8BWERs  
Average Fanout of Non-Clock Nets3.953.89      
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Translation ReportCurrentFri 26. Aug 21:20:32 2011087 Warnings (86 new)13 Infos (13 new)
Map ReportCurrentFri 26. Aug 21:30:17 2011050 Warnings (50 new)1134 Infos (1134 new)
Place and Route ReportCurrentFri 26. Aug 21:33:52 2011051 Warnings (51 new)3 Infos (3 new)
Post-PAR Static Timing ReportCurrentFri 26. Aug 21:34:50 201103 Warnings (3 new)3 Infos (3 new)
Bitgen ReportCurrentFri 26. Aug 21:36:07 2011047 Warnings (47 new)0
Translation ReportCurrentSat 27. Aug 12:19:05 2011087 Warnings (0 new)13 Infos (8 new)
Map ReportCurrentSat 27. Aug 12:28:13 2011050 Warnings (0 new)1134 Infos (0 new)
Place and Route ReportCurrentSat 27. Aug 12:31:43 2011051 Warnings (0 new)3 Infos (0 new)
Post-PAR Static Timing ReportCurrentSat 27. Aug 12:32:50 201103 Warnings (0 new)3 Infos (0 new)
Bitgen ReportCurrentSat 27. Aug 12:34:09 2011047 Warnings (0 new)0
 
- +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentFri 26. Aug 21:36:10 2011
WebTalk Log FileCurrentSat 27. Aug 12:34:09 2011
-
Date Generated: 08/27/2011 - 07:43:25
+
Date Generated: 08/27/2011 - 12:37:46
\ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs index 37a4f5b4c..8baa228ea 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs @@ -126,7 +126,7 @@ BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_i_bram_ctrl PARAMETER HW_VER = 3.00.a PARAMETER C_BASEADDR = 0x00000000 - PARAMETER C_HIGHADDR = 0x0000ffff + PARAMETER C_HIGHADDR = 0x00001FFF BUS_INTERFACE SLMB = microblaze_0_ilmb BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block END @@ -135,7 +135,7 @@ BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_d_bram_ctrl PARAMETER HW_VER = 3.00.a PARAMETER C_BASEADDR = 0x00000000 - PARAMETER C_HIGHADDR = 0x0000ffff + PARAMETER C_HIGHADDR = 0x00001FFF BUS_INTERFACE SLMB = microblaze_0_dlmb BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block END @@ -201,7 +201,7 @@ BEGIN mdm PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 PARAMETER C_BASEADDR = 0x74800000 - PARAMETER C_HIGHADDR = 0x7480ffff + PARAMETER C_HIGHADDR = 0x748FFFFF BUS_INTERFACE S_AXI = axi4lite_0 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug PORT S_AXI_ACLK = clk_50_0000MHzPLL0 @@ -273,12 +273,7 @@ BEGIN axi_s6_ddrx PARAMETER HW_VER = 1.02.a PARAMETER C_MCB_RZQ_LOC = K7 PARAMETER C_MCB_ZIO_LOC = R7 - PARAMETER C_MEM_TYPE = DDR3 PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E - PARAMETER C_MEM_BANKADDR_WIDTH = 3 - PARAMETER C_MEM_NUM_COL_BITS = 10 - PARAMETER C_SKIP_IN_TERM_CAL = 0 - PARAMETER C_S0_AXI_ENABLE = 1 PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 @@ -287,6 +282,7 @@ BEGIN axi_s6_ddrx PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 1 PARAMETER C_S0_AXI_BASEADDR = 0x80000000 PARAMETER C_S0_AXI_HIGHADDR = 0x87ffffff + PARAMETER C_S0_AXI_STRICT_COHERENCY = 0 BUS_INTERFACE S0_AXI = axi4_0 PORT mcbx_dram_clk = mcbx_dram_clk PORT mcbx_dram_clk_n = mcbx_dram_clk_n -- 2.39.5

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