From 8ef583a0351590a91394499eb5ca2ab8a703d959 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 23 Dec 2010 15:40:12 -0500 Subject: [PATCH] miiphy: convert to linux/mii.h The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger --- arch/arm/cpu/arm920t/at91rm9200/lxt972.c | 14 ++-- arch/arm/cpu/arm926ejs/davinci/lxt972.c | 14 ++-- arch/arm/cpu/ixp/npe/miiphy.c | 16 ++--- arch/arm/cpu/ixp/npe/npe.c | 8 +-- arch/powerpc/cpu/mpc8xx/fec.c | 4 +- arch/powerpc/cpu/ppc4xx/miiphy.c | 72 +++++++++---------- board/Marvell/rd6281a/rd6281a.c | 4 +- board/actux1/actux1.c | 4 +- board/csb272/csb272.c | 6 +- board/csb472/csb472.c | 6 +- board/evb64260/eth.c | 16 ++--- board/freescale/mpc8260ads/mpc8260ads.c | 12 ++-- board/freescale/mpc8560ads/mpc8560ads.c | 6 +- board/manroland/uc100/uc100.c | 4 +- board/netphone/netphone.c | 8 +-- board/netta/netta.c | 8 +-- board/netta2/netta2.c | 8 +-- board/prodrive/p3mx/mv_eth.c | 30 ++++---- board/sbc8560/sbc8560.c | 6 +- board/stx/stxgp3/stxgp3.c | 6 +- board/stx/stxssa/stxssa.c | 6 +- board/stx/stxxtc/stxxtc.c | 6 +- board/tqc/tqm8xx/tqm8xx.c | 6 +- common/cmd_mii.c | 29 ++++---- common/miiphyutil.c | 50 ++++++------- drivers/net/4xx_enet.c | 10 +-- drivers/net/altera_tse.c | 14 ++-- drivers/net/altera_tse.h | 2 - drivers/net/davinci_emac.c | 16 ++--- drivers/net/designware.c | 54 +++++++------- drivers/net/eepro100.c | 2 +- drivers/net/fec_mxc.c | 20 +++--- drivers/net/fsl_mcdmafec.c | 2 +- drivers/net/inca-ip_sw.c | 6 +- drivers/net/mcffec.c | 2 +- drivers/net/mcfmii.c | 14 ++-- drivers/net/ns7520_eth.c | 36 +++++----- drivers/net/ns9750_eth.c | 51 +++++++------- drivers/net/phy/mv88e61xx.c | 2 +- drivers/net/smc911x.c | 12 ++-- drivers/net/tsec.c | 50 ++++++------- drivers/qe/uec_phy.c | 68 +++++++++--------- drivers/qe/uec_phy.h | 18 ----- include/miiphy.h | 89 +++--------------------- include/tsec.h | 2 - 45 files changed, 361 insertions(+), 458 deletions(-) diff --git a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c index 260d393cf0..f02cfddddd 100644 --- a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c +++ b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c @@ -52,8 +52,8 @@ unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac) unsigned short Id1, Id2; at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1); - at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2); + at91rm9200_EmacReadPhy(p_mac, MII_PHYSID1, &Id1); + at91rm9200_EmacReadPhy(p_mac, MII_PHYSID2, &Id2); at91rm9200_EmacDisableMDIO (p_mac); if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0)) @@ -170,18 +170,18 @@ UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) unsigned short value; /* Set lxt972 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, PHY_BMCR, &value)) + if (!at91rm9200_EmacReadPhy (p_mac, MII_BMCR, &value)) return FALSE; /* Restart Auto_negotiation */ - value |= PHY_BMCR_RST_NEG; - if (!at91rm9200_EmacWritePhy (p_mac, PHY_BMCR, &value)) + value |= BMCR_ANRESTART; + if (!at91rm9200_EmacWritePhy (p_mac, MII_BMCR, &value)) return FALSE; /*check AutoNegotiate complete */ udelay (10000); - at91rm9200_EmacReadPhy(p_mac, PHY_BMSR, &value); - if (!(value & PHY_BMSR_AUTN_COMP)) + at91rm9200_EmacReadPhy(p_mac, MII_BMSR, &value); + if (!(value & BMSR_ANEGCOMPLETE)) return FALSE; return (lxt972_GetLinkSpeed (p_mac)); diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c index ce3e41c551..733d413729 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c +++ b/arch/arm/cpu/arm926ejs/davinci/lxt972.c @@ -39,9 +39,9 @@ int lxt972_is_phy_connected(int phy_addr) { u_int16_t id1, id2; - if (!davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &id1)) + if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1)) return(0); - if (!davinci_eth_phy_read(phy_addr, PHY_PHYIDR2, &id2)) + if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2)) return(0); if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) @@ -105,19 +105,19 @@ int lxt972_auto_negotiate(int phy_addr) { u_int16_t tmp; - if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) + if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) return(0); /* Restart Auto_negotiation */ - tmp |= PHY_BMCR_RST_NEG; - davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp); + tmp |= BMCR_ANRESTART; + davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); /*check AutoNegotiate complete */ udelay (10000); - if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) + if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) return(0); - if (!(tmp & PHY_BMSR_AUTN_COMP)) + if (!(tmp & BMSR_ANEGCOMPLETE)) return(0); return (lxt972_get_link_speed(phy_addr)); diff --git a/arch/arm/cpu/ixp/npe/miiphy.c b/arch/arm/cpu/ixp/npe/miiphy.c index 4b0201a357..a04779ab46 100644 --- a/arch/arm/cpu/ixp/npe/miiphy.c +++ b/arch/arm/cpu/ixp/npe/miiphy.c @@ -85,16 +85,16 @@ int phy_setup_aneg (char *devname, unsigned char addr) unsigned short ctl, adv; /* Setup standard advertise */ - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &ctl); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, ctl); + miiphy_read (devname, addr, MII_BMCR, &ctl); + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, ctl); return 0; } diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c index 2e6868960a..857bcadc0b 100644 --- a/arch/arm/cpu/ixp/npe/npe.c +++ b/arch/arm/cpu/ixp/npe/npe.c @@ -359,15 +359,15 @@ static int npe_init(struct eth_device *dev, bd_t * bis) debug("%s: 1\n", __FUNCTION__); - miiphy_read (dev->name, p_npe->phy_no, PHY_BMSR, ®_short); + miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, ®_short); /* * Wait if PHY is capable of autonegotiation and autonegotiation is not complete */ - if ((reg_short & PHY_BMSR_AUTN_ABLE) && !(reg_short & PHY_BMSR_AUTN_COMP)) { + if ((reg_short & BMSR_ANEGCAPABLE) && !(reg_short & BMSR_ANEGCOMPLETE)) { puts ("Waiting for PHY auto negotiation to complete"); i = 0; - while (!(reg_short & PHY_BMSR_AUTN_COMP)) { + while (!(reg_short & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -378,7 +378,7 @@ static int npe_init(struct eth_device *dev, bd_t * bis) if ((i++ % 1000) == 0) { putc ('.'); - miiphy_read (dev->name, p_npe->phy_no, PHY_BMSR, ®_short); + miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, ®_short); } udelay (1000); /* 1 ms */ } diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index d4abeb1b2f..a2d2bd6d8d 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -888,14 +888,14 @@ static int mii_discover_phy(struct eth_device *dev) udelay(10000); /* wait 10ms */ } for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2)); #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type ", phytype, pass); #endif if (phytype != 0xffff) { phyaddr = phyno; phytype |= mii_send(mk_mii_read(phyno, - PHY_PHYIDR1)) << 16; + MII_PHYSID1)) << 16; #ifdef ET_DEBUG printf("PHY @ 0x%x pass %d type ",phyno,pass); diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 3b28122014..206c476648 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -89,60 +89,60 @@ int phy_setup_aneg (char *devname, unsigned char addr) u16 exsr = 0x0000; #endif - miiphy_read (devname, addr, PHY_BMSR, &bmsr); + miiphy_read (devname, addr, MII_BMSR, &bmsr); #if defined(CONFIG_PHY_GIGE) - if (bmsr & PHY_BMSR_EXT_STAT) - miiphy_read (devname, addr, PHY_EXSR, &exsr); + if (bmsr & BMSR_ESTATEN) + miiphy_read (devname, addr, MII_ESTATUS, &exsr); - if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) { + if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) { /* 1000BASE-X */ u16 anar = 0x0000; - if (exsr & PHY_EXSR_1000XF) - anar |= PHY_X_ANLPAR_FD; + if (exsr & ESTATUS_1000XF) + anar |= ADVERTISE_1000XFULL); - if (exsr & PHY_EXSR_1000XH) - anar |= PHY_X_ANLPAR_HD; + if (exsr & ESTATUS_1000XH) + anar |= ADVERTISE_1000XHALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); } else #endif { u16 anar, btcr; - miiphy_read (devname, addr, PHY_ANAR, &anar); - anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10); + miiphy_read (devname, addr, MII_ADVERTISE, &anar); + anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL | + LPA_100HALF | LPA_10FULL | LPA_10HALF); - miiphy_read (devname, addr, PHY_1000BTCR, &btcr); + miiphy_read (devname, addr, MII_CTRL1000, &btcr); btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); - if (bmsr & PHY_BMSR_100T4) - anar |= PHY_ANLPAR_T4; + if (bmsr & BMSR_100BASE4) + anar |= LPA_100BASE4; - if (bmsr & PHY_BMSR_100TXF) - anar |= PHY_ANLPAR_TXFD; + if (bmsr & BMSR_100FULL) + anar |= LPA_100FULL; - if (bmsr & PHY_BMSR_100TXH) - anar |= PHY_ANLPAR_TX; + if (bmsr & BMSR_100HALF) + anar |= LPA_100HALF; - if (bmsr & PHY_BMSR_10TF) - anar |= PHY_ANLPAR_10FD; + if (bmsr & BMSR_10FULL) + anar |= LPA_10FULL; - if (bmsr & PHY_BMSR_10TH) - anar |= PHY_ANLPAR_10; + if (bmsr & BMSR_10HALF) + anar |= LPA_10HALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); #if defined(CONFIG_PHY_GIGE) - if (exsr & PHY_EXSR_1000TF) + if (exsr & ESTATUS_1000_TFULL) btcr |= PHY_1000BTCR_1000FD; - if (exsr & PHY_EXSR_1000TH) + if (exsr & ESTATUS_1000_THALF) btcr |= PHY_1000BTCR_1000HD; - miiphy_write (devname, addr, PHY_1000BTCR, btcr); + miiphy_write (devname, addr, MII_CTRL1000, btcr); #endif } @@ -152,21 +152,21 @@ int phy_setup_aneg (char *devname, unsigned char addr) */ u16 adv; - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF | + LPA_10FULL | LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); - miiphy_read (devname, addr, PHY_1000BTCR, &adv); + miiphy_read (devname, addr, MII_CTRL1000, &adv); adv |= (0x0300); - miiphy_write (devname, addr, PHY_1000BTCR, adv); + miiphy_write (devname, addr, MII_CTRL1000, adv); #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &bmcr); - bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, bmcr); + miiphy_read (devname, addr, MII_BMCR, &bmcr); + bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, bmcr); return 0; } diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index e69e035308..ecdea82d90 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -139,11 +139,11 @@ void mv_phy_88e1116_init(char *name) miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); /* reset the phy */ - if (miiphy_read (name, devadr, PHY_BMCR, ®) != 0) { + if (miiphy_read (name, devadr, MII_BMCR, ®) != 0) { printf("Err..(%s) PHY status read failed\n", __FUNCTION__); return; } - if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) { + if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) { printf("Err..(%s) PHY reset failed\n", __FUNCTION__); return; } diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c index 399be23e1e..e73aff8ced 100644 --- a/board/actux1/actux1.c +++ b/board/actux1/actux1.c @@ -140,8 +140,8 @@ void reset_phy (void) /* initialize the PHY */ miiphy_reset ("NPE0", CONFIG_PHY_ADDR); - miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR1, &id1); - miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR2, &id2); + miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); + miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); id2 &= 0xFFF0; /* mask out revision bits */ diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index e248aa752a..8b36127e90 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -176,11 +176,11 @@ int last_stage_init(void) miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08); return 0; /* success */ diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 25709f2a43..eac440848a 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -144,11 +144,11 @@ int last_stage_init(void) miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08); return 0; /* success */ } diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index a96e65590f..352505a51f 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -422,24 +422,24 @@ gt6426x_dump_mii(bd_t *bis, unsigned short phy) static void check_phy_state(struct eth_dev_s *p) { - int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR); + int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR); int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); - if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) { - int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) & - miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR); + if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) { + int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) & + miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA); int want; - if (nego & PHY_ANLPAR_TXFD) { + if (nego & LPA_100FULL) { want = 0x3; printf("MII: 100Base-TX, Full Duplex\n"); - } else if (nego & PHY_ANLPAR_TX) { + } else if (nego & LPA_100HALF) { want = 0x1; printf("MII: 100Base-TX, Half Duplex\n"); - } else if (nego & PHY_ANLPAR_10FD) { + } else if (nego & LPA_10FULL) { want = 0x2; printf("MII: 10Base-T, Full Duplex\n"); - } else if (nego & PHY_ANLPAR_10) { + } else if (nego & LPA_10HALF) { want = 0x0; printf("MII: 10Base-T, Half Duplex\n"); } else { diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c index be55626104..8f617ca932 100644 --- a/board/freescale/mpc8260ads/mpc8260ads.c +++ b/board/freescale/mpc8260ads/mpc8260ads.c @@ -243,8 +243,8 @@ void reset_phy (void) * Enable autonegotiation. */ bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610); - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #else /* * Ethernet PHY is configured (by means of configuration pins) @@ -254,13 +254,13 @@ void reset_phy (void) */ /* Advertise all capabilities */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_ANAR, 0x01E1); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1); /* Do not bypass Rx/Tx (de)scrambler */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_DCR, 0x0000); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER, 0x0000); - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ #endif /* CONFIG_MII */ } diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 1761431e33..2ae0459fec 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -239,10 +239,10 @@ void reset_phy (void) miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, 0x02, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_MII */ } diff --git a/board/manroland/uc100/uc100.c b/board/manroland/uc100/uc100.c index bdee4de366..959b2adf90 100644 --- a/board/manroland/uc100/uc100.c +++ b/board/manroland/uc100/uc100.c @@ -261,10 +261,10 @@ int misc_init_r (void) mii_init(); /* disable auto-negotiation, 100mbit, full-duplex */ - fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100); + fec8xx_miiphy_write(NULL, 0, MII_BMCR, 0x2100); /* set LED's to Link, Transmit, Receive */ - fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122); + fec8xx_miiphy_write(NULL, 0, MII_NWAYTEST, 0x4122); return 0; } diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index ce5f05169d..7fea71bd4d 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -488,13 +488,13 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); + fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); if (v == 0xFFFF) continue; - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); udelay(10000); - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, - PHY_BMCR_RESET | PHY_BMCR_AUTON); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE); udelay(10000); } } diff --git a/board/netta/netta.c b/board/netta/netta.c index 5c935f47a2..d15dc9b5b2 100644 --- a/board/netta/netta.c +++ b/board/netta/netta.c @@ -436,13 +436,13 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); + fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); if (v == 0xFFFF) continue; - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); udelay(10000); - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, - PHY_BMCR_RESET | PHY_BMCR_AUTON); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE); udelay(10000); } } diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index 3b0191dd78..ff713d9bba 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -486,13 +486,13 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); + fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); if (v == 0xFFFF) continue; - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); udelay(10000); - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, - PHY_BMCR_RESET | PHY_BMCR_AUTON); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE); udelay(10000); } } diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c index 567ae99d06..fac7633b77 100644 --- a/board/prodrive/p3mx/mv_eth.c +++ b/board/prodrive/p3mx/mv_eth.c @@ -586,16 +586,16 @@ static int mv64460_eth_real_open (struct eth_device *dev) } #endif /* defined(CONFIG_PHY_RESET) */ - miiphy_read (dev->name, reg, PHY_BMSR, ®_short); + miiphy_read (dev->name, reg, MII_BMSR, ®_short); /* * Wait if PHY is capable of autonegotiation and autonegotiation is not complete */ - if ((reg_short & PHY_BMSR_AUTN_ABLE) - && !(reg_short & PHY_BMSR_AUTN_COMP)) { + if ((reg_short & BMSR_ANEGCAPABLE) + && !(reg_short & BMSR_ANEGCOMPLETE)) { puts ("Waiting for PHY auto negotiation to complete"); i = 0; - while (!(reg_short & PHY_BMSR_AUTN_COMP)) { + while (!(reg_short & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -608,7 +608,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) putc ('.'); } udelay (1000); /* 1 ms */ - miiphy_read (dev->name, reg, PHY_BMSR, ®_short); + miiphy_read (dev->name, reg, MII_BMSR, ®_short); } puts (" done\n"); @@ -2241,20 +2241,20 @@ int phy_setup_aneg (char *devname, unsigned char addr) unsigned short ctl, adv; /* Setup standard advertise */ - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); - miiphy_read (devname, addr, PHY_1000BTCR, &adv); + miiphy_read (devname, addr, MII_CTRL1000, &adv); adv |= (0x0300); - miiphy_write (devname, addr, PHY_1000BTCR, adv); + miiphy_write (devname, addr, MII_CTRL1000, adv); /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &ctl); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, ctl); + miiphy_read (devname, addr, MII_BMCR, &ctl); + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, ctl); return 0; } diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 77abde5d41..7bf81799e5 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -228,10 +228,10 @@ void reset_phy (void) miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, 0x02, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_MII */ } diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index 25d5211700..1ed340efe7 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -242,10 +242,10 @@ reset_phy(void) miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, 0x02, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_MII */ #endif } diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 1e0acab546..6cd28a34b9 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -241,10 +241,10 @@ reset_phy(void) miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, 0x02, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_MII */ #endif } diff --git a/board/stx/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c index 6693a7051b..4afbbf5099 100644 --- a/board/stx/stxxtc/stxxtc.c +++ b/board/stx/stxxtc/stxxtc.c @@ -481,12 +481,12 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - miiphy_read("FEC", phyno, PHY_PHYIDR1, &v); + miiphy_read("FEC", phyno, MII_PHYSID1, &v); if (v == 0xFFFF) continue; - miiphy_write("FEC", phyno, PHY_BMCR, PHY_BMCR_POWD); + miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN); udelay(10000); - miiphy_write("FEC", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); + miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); udelay(10000); } } diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 940cc8ff71..6576e0288a 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -722,15 +722,15 @@ int last_stage_init(void) return 0; for (i = 0; i < 2; i++) { - ret = miiphy_read("FEC", phy[i], PHY_BMCR, ®); + ret = miiphy_read("FEC", phy[i], MII_BMCR, ®); if (ret) { printf("Cannot read BMCR on PHY %d\n", phy[i]); return 0; } /* Auto-negotiation off, hard set full duplex, 100Mbps */ ret = miiphy_write("FEC", phy[i], - PHY_BMCR, (reg | PHY_BMCR_100MB | - PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON); + MII_BMCR, (reg | BMCR_SPEED100 | + BMCR_FULLDPLX) & ~BMCR_ANENABLE); if (ret) { printf("Cannot write BMCR on PHY %d\n", phy[i]); return 0; diff --git a/common/cmd_mii.c b/common/cmd_mii.c index 3fb0795c3f..23b723eb23 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -35,12 +35,12 @@ typedef struct _MII_reg_desc_t { } MII_reg_desc_t; static const MII_reg_desc_t reg_0_5_desc_tbl[] = { - { 0, "PHY control register" }, - { 1, "PHY status register" }, - { 2, "PHY ID 1 register" }, - { 3, "PHY ID 2 register" }, - { 4, "Autonegotiation advertisement register" }, - { 5, "Autonegotiation partner abilities register" }, + { MII_BMCR, "PHY control register" }, + { MII_BMSR, "PHY status register" }, + { MII_PHYSID1, "PHY ID 1 register" }, + { MII_PHYSID2, "PHY ID 2 register" }, + { MII_ADVERTISE, "Autonegotiation advertisement register" }, + { MII_LPA, "Autonegotiation partner abilities register" }, }; typedef struct _MII_field_desc_t { @@ -212,20 +212,19 @@ static int special_field( const MII_field_desc_t *pdesc, ushort regval) { - if ((regno == 0) && (pdesc->lo == 6)) { - ushort speed_bits = regval & PHY_BMCR_SPEED_MASK; + if ((regno == MII_BMCR) && (pdesc->lo == 6)) { + ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100); printf("%2u,%2u = b%u%u speed selection = %s Mbps", 6, 13, (regval >> 6) & 1, (regval >> 13) & 1, - speed_bits == PHY_BMCR_1000_MBPS ? "1000" : - speed_bits == PHY_BMCR_100_MBPS ? "100" : - speed_bits == PHY_BMCR_10_MBPS ? "10" : - "???"); + speed_bits == BMCR_SPEED1000 ? "1000" : + speed_bits == BMCR_SPEED100 ? "100" : + "10"); return 1; } - else if ((regno == 0) && (pdesc->lo == 8)) { + else if ((regno == MII_BMCR) && (pdesc->lo == 8)) { printf("%2u = %5u duplex = %s", pdesc->lo, (regval >> pdesc->lo) & 1, @@ -233,7 +232,7 @@ static int special_field( return 1; } - else if ((regno == 4) && (pdesc->lo == 0)) { + else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) { ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; printf("%2u-%2u = %5u selector = %s", pdesc->hi, pdesc->lo, sel_bits, @@ -245,7 +244,7 @@ static int special_field( return 1; } - else if ((regno == 5) && (pdesc->lo == 0)) { + else if ((regno == MII_LPA) && (pdesc->lo == 0)) { ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; printf("%2u-%2u = %u selector = %s", pdesc->hi, pdesc->lo, sel_bits, diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 9cf845f605..e282096a13 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -253,20 +253,20 @@ int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui, unsigned int reg = 0; unsigned short tmp; - if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) { + if (miiphy_read (devname, addr, MII_PHYSID2, &tmp) != 0) { debug ("PHY ID register 2 read failed\n"); return (-1); } reg = tmp; - debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg); + debug ("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg); if (reg == 0xFFFF) { /* No physical device present at this address */ return (-1); } - if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) { + if (miiphy_read (devname, addr, MII_PHYSID1, &tmp) != 0) { debug ("PHY ID register 1 read failed\n"); return (-1); } @@ -290,11 +290,11 @@ int miiphy_reset(const char *devname, unsigned char addr) unsigned short reg; int timeout = 500; - if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { + if (miiphy_read (devname, addr, MII_BMCR, ®) != 0) { debug ("PHY status read failed\n"); return (-1); } - if (miiphy_write (devname, addr, PHY_BMCR, reg | PHY_BMCR_RESET) != 0) { + if (miiphy_write (devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { debug ("PHY reset failed\n"); return (-1); } @@ -308,7 +308,7 @@ int miiphy_reset(const char *devname, unsigned char addr) */ reg = 0x8000; while (((reg & 0x8000) != 0) && timeout--) { - if (miiphy_read(devname, addr, PHY_BMCR, ®) != 0) { + if (miiphy_read(devname, addr, MII_BMCR, ®) != 0) { debug("PHY status read failed\n"); return -1; } @@ -345,7 +345,7 @@ int miiphy_speed(const char *devname, unsigned char addr) * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. */ /* Check for 1000BASE-T. */ - if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) { + if (miiphy_read (devname, addr, MII_STAT1000, &btsr)) { printf ("PHY 1000BT status"); goto miiphy_read_failed; } @@ -356,21 +356,21 @@ int miiphy_speed(const char *devname, unsigned char addr) #endif /* CONFIG_PHY_GIGE */ /* Check Basic Management Control Register first. */ - if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) { + if (miiphy_read (devname, addr, MII_BMCR, &bmcr)) { printf ("PHY speed"); goto miiphy_read_failed; } /* Check if auto-negotiation is on. */ - if (bmcr & PHY_BMCR_AUTON) { + if (bmcr & BMCR_ANENABLE) { /* Get auto-negotiation results. */ - if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { + if (miiphy_read (devname, addr, MII_LPA, &anlpar)) { printf ("PHY AN speed"); goto miiphy_read_failed; } - return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET; + return (anlpar & LPA_100) ? _100BASET : _10BASET; } /* Get speed from basic control settings. */ - return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET; + return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET; miiphy_read_failed: printf (" read failed, assuming 10BASE-T\n"); @@ -391,7 +391,7 @@ int miiphy_duplex(const char *devname, unsigned char addr) /* Check for 1000BASE-X. */ if (miiphy_is_1000base_x (devname, addr)) { /* 1000BASE-X */ - if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { + if (miiphy_read (devname, addr, MII_LPA, &anlpar)) { printf ("1000BASE-X PHY AN duplex"); goto miiphy_read_failed; } @@ -400,7 +400,7 @@ int miiphy_duplex(const char *devname, unsigned char addr) * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. */ /* Check for 1000BASE-T. */ - if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) { + if (miiphy_read (devname, addr, MII_STAT1000, &btsr)) { printf ("PHY 1000BT status"); goto miiphy_read_failed; } @@ -414,22 +414,22 @@ int miiphy_duplex(const char *devname, unsigned char addr) #endif /* CONFIG_PHY_GIGE */ /* Check Basic Management Control Register first. */ - if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) { + if (miiphy_read (devname, addr, MII_BMCR, &bmcr)) { puts ("PHY duplex"); goto miiphy_read_failed; } /* Check if auto-negotiation is on. */ - if (bmcr & PHY_BMCR_AUTON) { + if (bmcr & BMCR_ANENABLE) { /* Get auto-negotiation results. */ - if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { + if (miiphy_read (devname, addr, MII_LPA, &anlpar)) { puts ("PHY AN duplex"); goto miiphy_read_failed; } - return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ? + return (anlpar & (LPA_10FULL | LPA_100FULL)) ? FULL : HALF; } /* Get speed from basic control settings. */ - return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF; + return (bmcr & BMCR_FULLDPLX) ? FULL : HALF; miiphy_read_failed: printf (" read failed, assuming half duplex\n"); @@ -446,12 +446,12 @@ int miiphy_is_1000base_x(const char *devname, unsigned char addr) #if defined(CONFIG_PHY_GIGE) u16 exsr; - if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) { + if (miiphy_read (devname, addr, MII_ESTATUS, &exsr)) { printf ("PHY extended status read failed, assuming no " "1000BASE-X\n"); return 0; } - return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)); + return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)); #else return 0; #endif @@ -467,14 +467,14 @@ int miiphy_link(const char *devname, unsigned char addr) unsigned short reg; /* dummy read; needed to latch some phys */ - (void)miiphy_read (devname, addr, PHY_BMSR, ®); - if (miiphy_read (devname, addr, PHY_BMSR, ®)) { - puts ("PHY_BMSR read failed, assuming no link\n"); + (void)miiphy_read (devname, addr, MII_BMSR, ®); + if (miiphy_read (devname, addr, MII_BMSR, ®)) { + puts ("MII_BMSR read failed, assuming no link\n"); return (0); } /* Determine if a link is active */ - if ((reg & PHY_BMSR_LS) != 0) { + if ((reg & BMSR_LSTATUS) != 0) { return (1); } else { return (0); diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 45ff4f333b..b1763b18bb 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -1185,16 +1185,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #endif /* defined(CONFIG_PHY_RESET) */ - miiphy_read (dev->name, reg, PHY_BMSR, ®_short); + miiphy_read (dev->name, reg, MII_BMSR, ®_short); /* * Wait if PHY is capable of autonegotiation and autonegotiation is not complete */ - if ((reg_short & PHY_BMSR_AUTN_ABLE) - && !(reg_short & PHY_BMSR_AUTN_COMP)) { + if ((reg_short & BMSR_ANEGCAPABLE) + && !(reg_short & BMSR_ANEGCOMPLETE)) { puts ("Waiting for PHY auto negotiation to complete"); i = 0; - while (!(reg_short & PHY_BMSR_AUTN_COMP)) { + while (!(reg_short & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -1207,7 +1207,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) putc ('.'); } udelay (1000); /* 1 ms */ - miiphy_read (dev->name, reg, PHY_BMSR, ®_short); + miiphy_read (dev->name, reg, MII_BMSR, ®_short); } puts (" done\n"); udelay (500000); /* another 500 ms (results in faster booting) */ diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index d45aab1306..54a944bfc4 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -475,12 +475,12 @@ static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv) */ mii_reg = tse_mdio_read(priv, MIIM_STATUS); - if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) - && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE) + && !(mii_reg & BMSR_ANEGCOMPLETE)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); - while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { + while (!(mii_reg & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -643,13 +643,13 @@ static struct phy_info phy_info_generic = { "Unknown/Generic PHY", 32, (struct phy_cmd[]){ /* config */ - {PHY_BMCR, PHY_BMCR_RESET, NULL}, - {PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG, NULL}, + {MII_BMCR, BMCR_RESET, NULL}, + {MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL}, {miim_end,} }, (struct phy_cmd[]){ /* startup */ - {PHY_BMSR, miim_read, NULL}, - {PHY_BMSR, miim_read, &mii_parse_sr}, + {MII_BMSR, miim_read, NULL}, + {MII_BMSR, miim_read, &mii_parse_sr}, {miim_end,} }, (struct phy_cmd[]){ /* shutdown */ diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h index c1cb79e88a..8880bfc0f8 100644 --- a/drivers/net/altera_tse.h +++ b/drivers/net/altera_tse.h @@ -41,8 +41,6 @@ #define MIIM_STATUS 0x1 #define MIIM_STATUS_AN_DONE 0x00000020 #define MIIM_STATUS_LINK 0x0004 -#define PHY_BMSR_AUTN_ABLE 0x0008 -#define PHY_BMSR_AUTN_COMP 0x0020 #define MIIM_PHYIR1 0x2 #define MIIM_PHYIR2 0x3 diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 43a3d79dc5..56cd2aaf49 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -236,7 +236,7 @@ static int gen_is_phy_connected(int phy_addr) { u_int16_t dummy; - return(davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); + return(davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy)); } static int gen_get_link_speed(int phy_addr) @@ -280,19 +280,19 @@ static int gen_auto_negotiate(int phy_addr) { u_int16_t tmp; - if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) + if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) return(0); /* Restart Auto_negotiation */ - tmp |= PHY_BMCR_AUTON; - davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp); + tmp |= BMCR_ANENABLE; + davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); /*check AutoNegotiate complete */ udelay (10000); - if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) + if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) return(0); - if (!(tmp & PHY_BMSR_AUTN_COMP)) + if (!(tmp & BMSR_ANEGCOMPLETE)) return(0); return(gen_get_link_speed(phy_addr)); @@ -694,14 +694,14 @@ int davinci_emac_initialize(void) return(0); /* Get PHY ID and initialize phy_ops for a detected PHY */ - if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { + if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID1, &tmp)) { active_phy_addr = 0xff; return(0); } phy_id = (tmp << 16) & 0xffff0000; - if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { + if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID2, &tmp)) { active_phy_addr = 0xff; return(0); } diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 2f923f26f9..3f5eeb73c5 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -318,19 +318,19 @@ static int find_phy(struct eth_device *dev) u16 ctrl, oldctrl; do { - eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); - oldctrl = ctrl & PHY_BMCR_AUTON; + eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); + oldctrl = ctrl & BMCR_ANENABLE; - ctrl ^= PHY_BMCR_AUTON; - eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); - eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); - ctrl &= PHY_BMCR_AUTON; + ctrl ^= BMCR_ANENABLE; + eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); + eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); + ctrl &= BMCR_ANENABLE; if (ctrl == oldctrl) { phy_addr++; } else { - ctrl ^= PHY_BMCR_AUTON; - eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + ctrl ^= BMCR_ANENABLE; + eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); return phy_addr; } @@ -347,10 +347,10 @@ static int dw_reset_phy(struct eth_device *dev) int timeout = CONFIG_PHYRESET_TIMEOUT; u32 phy_addr = priv->address; - eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET); + eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); do { - eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); - if (!(ctrl & PHY_BMCR_RESET)) + eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); + if (!(ctrl & BMCR_RESET)) break; udelay(1000); } while (timeout--); @@ -386,33 +386,33 @@ static int configure_phy(struct eth_device *dev) return -1; #if defined(CONFIG_DW_AUTONEG) - bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \ - PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS; + bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100 | \ + BMCR_FULLDPLX | BMCR_SPEED1000; #else - bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX; + bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; #if defined(CONFIG_DW_SPEED10M) - bmcr &= ~PHY_BMCR_100MB; + bmcr &= ~BMCR_SPEED100; #endif #if defined(CONFIG_DW_DUPLEXHALF) - bmcr &= ~PHY_BMCR_DPLX; + bmcr &= ~BMCR_FULLDPLX; #endif #endif - if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0) + if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) return -1; /* Read the phy status register and populate priv structure */ #if defined(CONFIG_DW_AUTONEG) timeout = CONFIG_AUTONEG_TIMEOUT; do { - eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr); - if (bmsr & PHY_BMSR_AUTN_COMP) + eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); + if (bmsr & BMSR_ANEGCOMPLETE) break; udelay(1000); } while (timeout--); - eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar); - eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr); + eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar); + eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr); if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { priv->speed = SPEED_1000M; @@ -421,28 +421,28 @@ static int configure_phy(struct eth_device *dev) else priv->duplex = HALF_DUPLEX; } else { - if (anlpar & PHY_ANLPAR_100) + if (anlpar & LPA_100) priv->speed = SPEED_100M; else priv->speed = SPEED_10M; - if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + if (anlpar & (LPA_10FULL | LPA_100FULL)) priv->duplex = FULL_DUPLEX; else priv->duplex = HALF_DUPLEX; } #else - if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0) + if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0) return -1; - if (ctrl & PHY_BMCR_DPLX) + if (ctrl & BMCR_FULLDPLX) priv->duplex = FULL_DUPLEX; else priv->duplex = HALF_DUPLEX; - if (ctrl & PHY_BMCR_1000_MBPS) + if (ctrl & BMCR_SPEED1000) priv->speed = SPEED_1000M; - else if (ctrl & PHY_BMCR_100_MBPS) + else if (ctrl & BMCR_SPEED100) priv->speed = SPEED_100M; else priv->speed = SPEED_10M; diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index ae0e0d4582..86709a7f0a 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -335,7 +335,7 @@ static struct eth_device* verify_phyaddr (const char *devname, } /* read id2 register */ - if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) { + if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) { printf("%s: mii read timeout!\n", devname); return NULL; } diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 0d0f392d1e..c4389629a9 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -163,20 +163,20 @@ static int miiphy_restart_aneg(struct eth_device *dev) * Reset PHY, then delay 300ns */ #ifdef CONFIG_MX27 - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF); + miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_DCOUNTER, 0x00FF); #endif - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, - PHY_BMCR_RESET); + miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, + BMCR_RESET); udelay(1000); /* * Set the auto-negotiation advertisement register bits */ - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3); - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_ADVERTISE, + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF | PHY_ANLPAR_PSB_802_3); + miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); return 0; } @@ -197,12 +197,12 @@ static int miiphy_wait_aneg(struct eth_device *dev) } if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR, - PHY_BMSR, &status)) { + MII_BMSR, &status)) { printf("%s: Autonegotiation failed. status: 0x%04x\n", dev->name, status); return -1; } - } while (!(status & PHY_BMSR_LS)); + } while (!(status & BMSR_LSTATUS)); return 0; } diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 35a6dfbe94..5330dbc79f 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -200,7 +200,7 @@ static int fec_send(struct eth_device *dev, volatile void *packet, int length) cbd_t *pTbd, *pUsedTbd; u16 phyStatus; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); /* process all the consumed TBDs */ while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) { diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c index 492f5ce8f8..bd3360cad7 100644 --- a/drivers/net/inca-ip_sw.c +++ b/drivers/net/inca-ip_sw.c @@ -756,7 +756,7 @@ static int inca_amdix(void) (0x1 << 31) | /* RA */ (0x0 << 30) | /* Read */ (0x6 << 21) | /* LAN */ - (6 << 16)); /* PHY_ANER */ + (6 << 16)); /* MII_EXPANSION */ do { SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6); } while (phyReg6 & (1 << 31)); @@ -769,7 +769,7 @@ static int inca_amdix(void) (0x1 << 31) | /* RA */ (0x0 << 30) | /* Read */ (0x6 << 21) | /* LAN */ - (4 << 16)); /* PHY_ANAR */ + (4 << 16)); /* MII_ADVERTISE */ do { SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4); } while (phyReg4 & (1 << 31)); @@ -782,7 +782,7 @@ static int inca_amdix(void) (0x1 << 31) | /* RA */ (0x0 << 30) | /* Read */ (0x6 << 21) | /* LAN */ - (5 << 16)); /* PHY_ANLPAR */ + (5 << 16)); /* MII_LPA */ do { SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5); } while (phyReg5 & (1 << 31)); diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 64be5de52f..a08ff278bf 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -141,7 +141,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) int j, rc; u16 phyStatus; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); /* section 16.9.23.3 * Wait for ready diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 401182d426..f959c00ca7 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -171,7 +171,7 @@ int mii_discover_phy(struct eth_device *dev) for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); + phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1)); #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type\n", phytype, pass); #endif @@ -180,7 +180,7 @@ int mii_discover_phy(struct eth_device *dev) phyaddr = phyno; phytype <<= 16; phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + mii_send(mk_mii_read(phyno, MII_PHYSID2)); #ifdef ET_DEBUG printf("PHY @ 0x%x pass %d\n", phyno, pass); @@ -256,18 +256,18 @@ void __mii_init(void) status = 0; i++; /* Read PHY control register */ - miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &status); + miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status); /* If phy set to autonegotiate, wait for autonegotiation done, * if phy is not autonegotiating, just wait for link up. */ - if ((status & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { - linkgood = (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS); + if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) { + linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS); } else { - linkgood = PHY_BMSR_LS; + linkgood = BMSR_LSTATUS; } /* Read PHY status register */ - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &status); + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status); if ((status & linkgood) == linkgood) break; diff --git a/drivers/net/ns7520_eth.c b/drivers/net/ns7520_eth.c index bfa651b7bf..de82b0487a 100644 --- a/drivers/net/ns7520_eth.c +++ b/drivers/net/ns7520_eth.c @@ -387,8 +387,8 @@ static int ns7520_eth_reset(void) ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); /* reset PHY */ - ns7520_mii_write(PHY_BMCR, PHY_BMCR_RESET); - ns7520_mii_write(PHY_BMCR, 0); + ns7520_mii_write(MII_BMCR, BMCR_RESET); + ns7520_mii_write(MII_BMCR, 0); udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */ @@ -438,23 +438,23 @@ static void ns7520_link_auto_negotiate(void) /* run auto-negotation */ /* define what we are capable of */ - ns7520_mii_write(PHY_ANAR, - PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | - PHY_ANLPAR_10 | + ns7520_mii_write(MII_ADVERTISE, + LPA_100FULL | + LPA_100HALF | + LPA_10FULL | + LPA_10HALF | PHY_ANLPAR_PSB_802_3); /* start auto-negotiation */ - ns7520_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + ns7520_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); /* wait for completion */ ulStartJiffies = get_timer(0); while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) { - uiStatus = ns7520_mii_read(PHY_BMSR); + uiStatus = ns7520_mii_read(MII_BMSR); if ((uiStatus & - (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) == - (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) { + (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) == + (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) { /* lucky we are, auto-negotiation succeeded */ ns7520_link_print_changed(); ns7520_link_update_egcr(); @@ -515,13 +515,13 @@ static void ns7520_link_print_changed(void) DEBUG_FN(DEBUG_LINK); - uiControl = ns7520_mii_read(PHY_BMCR); + uiControl = ns7520_mii_read(MII_BMCR); - if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { - /* PHY_BMSR_LS is only set on autonegotiation */ - uiStatus = ns7520_mii_read(PHY_BMSR); + if ((uiControl & BMCR_ANENABLE) == BMCR_ANENABLE) { + /* BMSR_LSTATUS is only set on autonegotiation */ + uiStatus = ns7520_mii_read(MII_BMSR); - if (!(uiStatus & PHY_BMSR_LS)) { + if (!(uiStatus & BMSR_LSTATUS)) { printk(KERN_WARNING NS7520_DRIVER_NAME ": link down\n"); /* @TODO Linux: carrier_off */ @@ -582,12 +582,12 @@ static char ns7520_mii_identify_phy(void) DEBUG_FN(DEBUG_MII); - phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_PHYIDR1); + phyDetected = (PhyType) uiID1 = ns7520_mii_read(MII_PHYSID1); switch (phyDetected) { case PHY_LXT971A: szName = "LXT971A"; - uiID2 = ns7520_mii_read(PHY_PHYIDR2); + uiID2 = ns7520_mii_read(MII_PHYSID2); nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; cRes = 1; break; diff --git a/drivers/net/ns9750_eth.c b/drivers/net/ns9750_eth.c index d4901b4118..9899563c47 100644 --- a/drivers/net/ns9750_eth.c +++ b/drivers/net/ns9750_eth.c @@ -399,8 +399,8 @@ static int ns9750_eth_reset (void) ns9750_mii_get_clock_divisor (nPhyMaxMdioClock); /* reset PHY */ - ns9750_mii_write(PHY_BMCR, PHY_BMCR_RESET); - ns9750_mii_write(PHY_BMCR, 0); + ns9750_mii_write(MII_BMCR, BMCR_RESET); + ns9750_mii_write(MII_BMCR, 0); /* @TODO check time */ udelay (3000); /* [2] p.70 says at least 300us reset recovery time. But @@ -455,26 +455,25 @@ static void ns9750_link_force (void) DEBUG_FN (DEBUG_LINK); - uiControl = ns9750_mii_read(PHY_BMCR); - uiControl &= ~(PHY_BMCR_SPEED_MASK | - PHY_BMCR_AUTON | PHY_BMCR_DPLX); + uiControl = ns9750_mii_read(MII_BMCR); + uiControl &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | + BMCR_ANENABLE | BMCR_FULLDPLX); uiLastLinkStatus = 0; if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) == FS_EEPROM_AUTONEG_SPEED_100) { - uiControl |= PHY_BMCR_100MB; + uiControl |= BMCR_SPEED100; uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX; - } else - uiControl |= PHY_BMCR_10_MBPS; + } if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) == FS_EEPROM_AUTONEG_DUPLEX_FULL) { - uiControl |= PHY_BMCR_DPLX; + uiControl |= BMCR_FULLDPLX; uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE; } - ns9750_mii_write(PHY_BMCR, uiControl); + ns9750_mii_write(MII_BMCR, uiControl); ns9750_link_print_changed (); ns9750_link_update_egcr (); @@ -495,23 +494,23 @@ static void ns9750_link_auto_negotiate (void) /* run auto-negotation */ /* define what we are capable of */ - ns9750_mii_write(PHY_ANAR, - PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | - PHY_ANLPAR_10 | + ns9750_mii_write(MII_ADVERTISE, + LPA_100FULL | + LPA_100HALF | + LPA_10FULL | + LPA_10HALF | PHY_ANLPAR_PSB_802_3); /* start auto-negotiation */ - ns9750_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + ns9750_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); /* wait for completion */ ulStartJiffies = get_ticks (); while (get_ticks () < ulStartJiffies + NS9750_MII_NEG_DELAY) { - uiStatus = ns9750_mii_read(PHY_BMSR); + uiStatus = ns9750_mii_read(MII_BMSR); if ((uiStatus & - (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) == - (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) { + (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) == + (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) { /* lucky we are, auto-negotiation succeeded */ ns9750_link_print_changed (); ns9750_link_update_egcr (); @@ -569,13 +568,13 @@ static void ns9750_link_print_changed (void) DEBUG_FN (DEBUG_LINK); - uiControl = ns9750_mii_read(PHY_BMCR); + uiControl = ns9750_mii_read(MII_BMCR); - if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { - /* PHY_BMSR_LS is only set on autonegotiation */ - uiStatus = ns9750_mii_read(PHY_BMSR); + if ((uiControl & BMCR_ANENABLE) == BMCR_ANENABLE) { + /* BMSR_LSTATUS is only set on autonegotiation */ + uiStatus = ns9750_mii_read(MII_BMSR); - if (!(uiStatus & PHY_BMSR_LS)) { + if (!(uiStatus & BMSR_LSTATUS)) { printk (KERN_WARNING NS9750_DRIVER_NAME ": link down\n"); /* @TODO Linux: carrier_off */ @@ -634,12 +633,12 @@ static char ns9750_mii_identify_phy (void) DEBUG_FN (DEBUG_MII); - phyDetected = (PhyType) uiID1 = ns9750_mii_read(PHY_PHYIDR1); + phyDetected = (PhyType) uiID1 = ns9750_mii_read(MII_PHYSID1); switch (phyDetected) { case PHY_LXT971A: szName = "LXT971A"; - uiID2 = ns9750_mii_read(PHY_PHYIDR2); + uiID2 = ns9750_mii_read(MII_PHYSID2); nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; cRes = 1; break; diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 2d1de02917..483a920fca 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -354,7 +354,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) printf("Invalid cpu port config, using default port5\n"); } - RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, ®); + RD_PHY(name, MV88E61XX_PRT_OFST, MII_PHYSID2, ®); switch (reg &= 0xfff0) { case 0x1610: idstr = "88E6161"; diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 3da4c35fc2..aeafeba44c 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -103,11 +103,11 @@ static void smc911x_phy_configure(struct eth_device *dev) smc911x_phy_reset(dev); - smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_RESET); + smc911x_miiphy_write(dev, 1, MII_BMCR, BMCR_RESET); mdelay(1); - smc911x_miiphy_write(dev, 1, PHY_ANAR, 0x01e1); - smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_AUTON | - PHY_BMCR_RST_NEG); + smc911x_miiphy_write(dev, 1, MII_ADVERTISE, 0x01e1); + smc911x_miiphy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | + BMCR_ANRESTART); timeout = 5000; do { @@ -115,9 +115,9 @@ static void smc911x_phy_configure(struct eth_device *dev) if ((timeout--) == 0) goto err_out; - if (smc911x_miiphy_read(dev, 1, PHY_BMSR, &status) != 0) + if (smc911x_miiphy_read(dev, 1, MII_BMSR, &status) != 0) goto err_out; - } while (!(status & PHY_BMSR_LS)); + } while (!(status & BMSR_LSTATUS)); printf(DRIVERNAME ": phy initialized\n"); diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 77908d1e12..9c8fe62441 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -377,11 +377,11 @@ static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) * (ie - we're capable and it's not done) */ mii_reg = read_phy_reg(priv, MIIM_STATUS); - if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); - while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { + while (!(mii_reg & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -427,17 +427,17 @@ static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) { /* We're using autonegotiation */ - if (mii_reg & PHY_BMSR_AUTN_ABLE) { + if (mii_reg & BMSR_ANEGCAPABLE) { uint lpa = 0; uint gblpa = 0; /* Check for gigabit capability */ - if (mii_reg & PHY_BMSR_EXT) { + if (mii_reg & BMSR_ERCAP) { /* We want a list of states supported by * both PHYs in the link */ - gblpa = read_phy_reg(priv, PHY_1000BTSR); - gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; + gblpa = read_phy_reg(priv, MII_STAT1000); + gblpa &= read_phy_reg(priv, MII_CTRL1000) << 2; } /* Set the baseline so we only have to set them @@ -457,29 +457,29 @@ static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) return 0; } - lpa = read_phy_reg(priv, PHY_ANAR); - lpa &= read_phy_reg(priv, PHY_ANLPAR); + lpa = read_phy_reg(priv, MII_ADVERTISE); + lpa &= read_phy_reg(priv, MII_LPA); - if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { + if (lpa & (LPA_100FULL | LPA_100HALF)) { priv->speed = 100; - if (lpa & PHY_ANLPAR_TXFD) + if (lpa & LPA_100FULL) priv->duplexity = 1; - } else if (lpa & PHY_ANLPAR_10FD) + } else if (lpa & LPA_10FULL) priv->duplexity = 1; } else { - uint bmcr = read_phy_reg(priv, PHY_BMCR); + uint bmcr = read_phy_reg(priv, MII_BMCR); priv->speed = 10; priv->duplexity = 0; - if (bmcr & PHY_BMCR_DPLX) + if (bmcr & BMCR_FULLDPLX) priv->duplexity = 1; - if (bmcr & PHY_BMCR_1000_MBPS) + if (bmcr & BMCR_SPEED1000) priv->speed = 1000; - else if (bmcr & PHY_BMCR_100_MBPS) + else if (bmcr & BMCR_SPEED100) priv->speed = 100; } @@ -1645,14 +1645,14 @@ static struct phy_info phy_info_ksz804 = { "Micrel KSZ804 PHY", 4, (struct phy_cmd[]) { /* config */ - {PHY_BMCR, PHY_BMCR_RESET, NULL}, - {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, + {MII_BMCR, BMCR_RESET, NULL}, + {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL}, {miim_end,} }, (struct phy_cmd[]) { /* startup */ - {PHY_BMSR, miim_read, NULL}, - {PHY_BMSR, miim_read, &mii_parse_sr}, - {PHY_BMSR, miim_read, &mii_parse_link}, + {MII_BMSR, miim_read, NULL}, + {MII_BMSR, miim_read, &mii_parse_sr}, + {MII_BMSR, miim_read, &mii_parse_link}, {miim_end,} }, (struct phy_cmd[]) { /* shutdown */ @@ -1666,14 +1666,14 @@ static struct phy_info phy_info_generic = { "Unknown/Generic PHY", 32, (struct phy_cmd[]) { /* config */ - {PHY_BMCR, PHY_BMCR_RESET, NULL}, - {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, + {MII_BMCR, BMCR_RESET, NULL}, + {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL}, {miim_end,} }, (struct phy_cmd[]) { /* startup */ - {PHY_BMSR, miim_read, NULL}, - {PHY_BMSR, miim_read, &mii_parse_sr}, - {PHY_BMSR, miim_read, &mii_parse_link}, + {MII_BMSR, miim_read, NULL}, + {MII_BMSR, miim_read, &mii_parse_sr}, + {MII_BMSR, miim_read, &mii_parse_link}, {miim_end,} }, (struct phy_cmd[]) { /* shutdown */ diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 35f2368a80..465a497136 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -242,7 +242,7 @@ static void config_genmii_advert (struct uec_mii_info *mii_info) advertise = mii_info->advertising; /* Setup standard advertisement */ - adv = phy_read (mii_info, PHY_ANAR); + adv = phy_read (mii_info, MII_ADVERTISE); adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); if (advertise & ADVERTISED_10baseT_Half) adv |= ADVERTISE_10HALF; @@ -252,7 +252,7 @@ static void config_genmii_advert (struct uec_mii_info *mii_info) adv |= ADVERTISE_100HALF; if (advertise & ADVERTISED_100baseT_Full) adv |= ADVERTISE_100FULL; - phy_write (mii_info, PHY_ANAR, adv); + phy_write (mii_info, MII_ADVERTISE, adv); } static void genmii_setup_forced (struct uec_mii_info *mii_info) @@ -260,24 +260,24 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info) u16 ctrl; u32 features = mii_info->phyinfo->features; - ctrl = phy_read (mii_info, PHY_BMCR); + ctrl = phy_read (mii_info, MII_BMCR); - ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS | - PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON); - ctrl |= PHY_BMCR_RESET; + ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | + BMCR_SPEED1000 | BMCR_ANENABLE); + ctrl |= BMCR_RESET; switch (mii_info->speed) { case SPEED_1000: if (features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)) { - ctrl |= PHY_BMCR_1000_MBPS; + ctrl |= BMCR_SPEED1000; break; } mii_info->speed = SPEED_100; case SPEED_100: if (features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)) { - ctrl |= PHY_BMCR_100_MBPS; + ctrl |= BMCR_SPEED100; break; } mii_info->speed = SPEED_10; @@ -290,7 +290,7 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info) break; } - phy_write (mii_info, PHY_BMCR, ctrl); + phy_write (mii_info, MII_BMCR, ctrl); } /* Enable and Restart Autonegotiation */ @@ -298,9 +298,9 @@ static void genmii_restart_aneg (struct uec_mii_info *mii_info) { u16 ctl; - ctl = phy_read (mii_info, PHY_BMCR); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - phy_write (mii_info, PHY_BMCR, ctl); + ctl = phy_read (mii_info, MII_BMCR); + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + phy_write (mii_info, MII_BMCR, ctl); } static int gbit_config_aneg (struct uec_mii_info *mii_info) @@ -335,7 +335,7 @@ static int marvell_config_aneg (struct uec_mii_info *mii_info) /* The Marvell PHY has an errata which requires * that certain registers get written in order * to restart autonegotiation */ - phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET); + phy_write (mii_info, MII_BMCR, BMCR_RESET); phy_write (mii_info, 0x1d, 0x1f); phy_write (mii_info, 0x1e, 0x200c); @@ -373,18 +373,18 @@ static int genmii_update_link (struct uec_mii_info *mii_info) u16 status; /* Status is read once to clear old link state */ - phy_read (mii_info, PHY_BMSR); + phy_read (mii_info, MII_BMSR); /* * Wait if the link is up, and autonegotiation is in progress * (ie - we're capable and it's not done) */ - status = phy_read(mii_info, PHY_BMSR); - if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE) - && !(status & PHY_BMSR_AUTN_COMP)) { + status = phy_read(mii_info, MII_BMSR); + if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE) + && !(status & BMSR_ANEGCOMPLETE)) { int i = 0; - while (!(status & PHY_BMSR_AUTN_COMP)) { + while (!(status & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -395,11 +395,11 @@ static int genmii_update_link (struct uec_mii_info *mii_info) i++; udelay(1000); /* 1 ms */ - status = phy_read(mii_info, PHY_BMSR); + status = phy_read(mii_info, MII_BMSR); } mii_info->link = 1; } else { - if (status & PHY_BMSR_LS) + if (status & BMSR_LSTATUS) mii_info->link = 1; else mii_info->link = 0; @@ -429,13 +429,13 @@ static int genmii_read_status (struct uec_mii_info *mii_info) else mii_info->duplex = DUPLEX_HALF; } else { - status = phy_read(mii_info, PHY_ANLPAR); + status = phy_read(mii_info, MII_LPA); - if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + if (status & (LPA_10FULL | LPA_100FULL)) mii_info->duplex = DUPLEX_FULL; else mii_info->duplex = DUPLEX_HALF; - if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) + if (status & (LPA_100FULL | LPA_100HALF)) mii_info->speed = SPEED_100; else mii_info->speed = SPEED_10; @@ -463,8 +463,8 @@ static int bcm_init(struct uec_mii_info *mii_info) /* Wait for aneg to complete. */ do - val = phy_read(mii_info, PHY_BMSR); - while (--cnt && !(val & PHY_BMSR_AUTN_COMP)); + val = phy_read(mii_info, MII_BMSR); + while (--cnt && !(val & BMSR_ANEGCOMPLETE)); /* Set RDX clk delay. */ phy_write(mii_info, 0x18, 0x7 | (7 << 12)); @@ -511,7 +511,7 @@ static int marvell_init(struct uec_mii_info *mii_info) temp |= MII_M1111_HWCFG_MODE_RGMII; phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp); - phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); + phy_write(mii_info, MII_BMCR, BMCR_RESET); } return 0; @@ -582,11 +582,11 @@ static int marvell_config_intr (struct uec_mii_info *mii_info) static int dm9161_init (struct uec_mii_info *mii_info) { /* Reset the PHY */ - phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) | - PHY_BMCR_RESET); + phy_write (mii_info, MII_BMCR, phy_read (mii_info, MII_BMCR) | + BMCR_RESET); /* PHY and MAC connect */ - phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) & - ~PHY_BMCR_ISO); + phy_write (mii_info, MII_BMCR, phy_read (mii_info, MII_BMCR) & + ~BMCR_ISOLATE); phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); @@ -825,11 +825,11 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) struct phy_info *theInfo = NULL; /* Grab the bits from PHYIR1, and put them in the upper half */ - phy_reg = phy_read (mii_info, PHY_PHYIDR1); + phy_reg = phy_read (mii_info, MII_PHYSID1); phy_ID = (phy_reg & 0xffff) << 16; /* Grab the bits from PHYIR2, and put them in the lower half */ - phy_reg = phy_read (mii_info, PHY_PHYIDR2); + phy_reg = phy_read (mii_info, MII_PHYSID2); phy_ID |= (phy_reg & 0xffff); /* loop through all the known PHY types, and find one that */ @@ -900,8 +900,8 @@ void marvell_phy_interface_mode (struct eth_device *dev, /* handle 88e1111 rev.B2 erratum 5.6 */ if (mii_info->autoneg) { - status = phy_read (mii_info, PHY_BMCR); - phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON); + status = phy_read (mii_info, MII_BMCR); + phy_write (mii_info, MII_BMCR, status | BMCR_ANENABLE); } /* now the B2 will correctly report autoneg completion status */ } diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index 7ac1ff9329..929d9bdd7d 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -169,24 +169,6 @@ #define ADVERTISED_BNC (1 << 11) #define ADVERTISED_10000baseT_Full (1 << 12) -/* Advertisement control register. */ -#define ADVERTISE_SLCT 0x001f /* Selector bits */ -#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ -#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ -#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ -#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ -#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ -#define ADVERTISE_RESV 0x1c00 /* Unused... */ -#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ - -#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) -#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) - /* Taken from mii_if_info and sungem_phy.h */ struct uec_mii_info { /* Information about the PHY type */ diff --git a/include/miiphy.h b/include/miiphy.h index 2f7d915526..42dc12715c 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -34,6 +34,7 @@ #ifndef _miiphy_h_ #define _miiphy_h_ +#include #include int miiphy_read (const char *devname, unsigned char addr, unsigned char reg, @@ -100,89 +101,17 @@ int bb_miiphy_write (const char *devname, unsigned char addr, #define FULL 44 /* phy register offsets */ -#define PHY_BMCR 0x00 -#define PHY_BMSR 0x01 -#define PHY_PHYIDR1 0x02 -#define PHY_PHYIDR2 0x03 -#define PHY_ANAR 0x04 -#define PHY_ANLPAR 0x05 -#define PHY_ANER 0x06 -#define PHY_ANNPTR 0x07 -#define PHY_ANLPNP 0x08 -#define PHY_1000BTCR 0x09 -#define PHY_1000BTSR 0x0A -#define PHY_EXSR 0x0F -#define PHY_PHYSTS 0x10 -#define PHY_MIPSCR 0x11 -#define PHY_MIPGSR 0x12 -#define PHY_DCR 0x13 -#define PHY_FCSCR 0x14 -#define PHY_RECR 0x15 -#define PHY_PCSR 0x16 -#define PHY_LBR 0x17 -#define PHY_10BTSCR 0x18 -#define PHY_PHYCTRL 0x19 - -/* PHY BMCR */ -#define PHY_BMCR_RESET 0x8000 -#define PHY_BMCR_LOOP 0x4000 -#define PHY_BMCR_100MB 0x2000 -#define PHY_BMCR_AUTON 0x1000 -#define PHY_BMCR_POWD 0x0800 -#define PHY_BMCR_ISO 0x0400 -#define PHY_BMCR_RST_NEG 0x0200 -#define PHY_BMCR_DPLX 0x0100 -#define PHY_BMCR_COL_TST 0x0080 - -#define PHY_BMCR_SPEED_MASK 0x2040 -#define PHY_BMCR_1000_MBPS 0x0040 -#define PHY_BMCR_100_MBPS 0x2000 -#define PHY_BMCR_10_MBPS 0x0000 - -/* phy BMSR */ -#define PHY_BMSR_100T4 0x8000 -#define PHY_BMSR_100TXF 0x4000 -#define PHY_BMSR_100TXH 0x2000 -#define PHY_BMSR_10TF 0x1000 -#define PHY_BMSR_10TH 0x0800 -#define PHY_BMSR_EXT_STAT 0x0100 -#define PHY_BMSR_PRE_SUP 0x0040 -#define PHY_BMSR_AUTN_COMP 0x0020 -#define PHY_BMSR_RF 0x0010 -#define PHY_BMSR_AUTN_ABLE 0x0008 -#define PHY_BMSR_LS 0x0004 -#define PHY_BMSR_JD 0x0002 -#define PHY_BMSR_EXT 0x0001 - -/*phy ANLPAR */ -#define PHY_ANLPAR_NP 0x8000 -#define PHY_ANLPAR_ACK 0x4000 -#define PHY_ANLPAR_RF 0x2000 -#define PHY_ANLPAR_ASYMP 0x0800 -#define PHY_ANLPAR_PAUSE 0x0400 -#define PHY_ANLPAR_T4 0x0200 -#define PHY_ANLPAR_TXFD 0x0100 -#define PHY_ANLPAR_TX 0x0080 -#define PHY_ANLPAR_10FD 0x0040 -#define PHY_ANLPAR_10 0x0020 -#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ -/* phy ANLPAR 1000BASE-X */ -#define PHY_X_ANLPAR_NP 0x8000 -#define PHY_X_ANLPAR_ACK 0x4000 -#define PHY_X_ANLPAR_RF_MASK 0x3000 -#define PHY_X_ANLPAR_PAUSE_MASK 0x0180 -#define PHY_X_ANLPAR_HD 0x0040 -#define PHY_X_ANLPAR_FD 0x0020 - -#define PHY_ANLPAR_PSB_MASK 0x001f +#define MII_MIPSCR 0x11 + +/* MII_LPA */ #define PHY_ANLPAR_PSB_802_3 0x0001 #define PHY_ANLPAR_PSB_802_9 0x0002 -/* phy 1000BTCR */ +/* MII_CTRL1000 masks */ #define PHY_1000BTCR_1000FD 0x0200 #define PHY_1000BTCR_1000HD 0x0100 -/* phy 1000BTSR */ +/* MII_STAT1000 masks */ #define PHY_1000BTSR_MSCF 0x8000 #define PHY_1000BTSR_MSCR 0x4000 #define PHY_1000BTSR_LRS 0x2000 @@ -191,9 +120,7 @@ int bb_miiphy_write (const char *devname, unsigned char addr, #define PHY_1000BTSR_1000HD 0x0400 /* phy EXSR */ -#define PHY_EXSR_1000XF 0x8000 -#define PHY_EXSR_1000XH 0x4000 -#define PHY_EXSR_1000TF 0x2000 -#define PHY_EXSR_1000TH 0x1000 +#define ESTATUS_1000XF 0x8000 +#define ESTATUS_1000XH 0x4000 #endif diff --git a/include/tsec.h b/include/tsec.h index 1e903659eb..d56ec2cd0c 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -124,8 +124,6 @@ #define MIIM_STATUS 0x1 #define MIIM_STATUS_AN_DONE 0x00000020 #define MIIM_STATUS_LINK 0x0004 -#define PHY_BMSR_AUTN_ABLE 0x0008 -#define PHY_BMSR_AUTN_COMP 0x0020 #define MIIM_PHYIR1 0x2 #define MIIM_PHYIR2 0x3 -- 2.39.5