From 920638fa5e781de91bb70fb516219c8cd4136407 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 3 Jun 2015 14:43:23 +0530 Subject: [PATCH] ARM: DRA7-evm: Enable HW leveling Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/omap5/sdram.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 2e2385286c..942a80a8b4 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -149,15 +149,15 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00910091, .emif_ddr_ext_phy_ctrl_3 = 0x00950095, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -174,15 +174,15 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00910091, .emif_ddr_ext_phy_ctrl_3 = 0x00950095, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -453,6 +453,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 }; @@ -488,6 +493,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 }; -- 2.39.5