From 935b402eaec0f78ffdafd614aa8176a777d8b6d9 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 18 Oct 2013 11:47:23 +0200 Subject: [PATCH] fsl/mpc85xx: define common serdes_clock_to_string function This allows to share some common code for the boards that use a corenet base SoC. Two different versions of the function are available in fsl_corenet_serdes.c and fsl_corenet2_serdes.c files. Signed-off-by: Valentin Longchamp [York Sun: fix t1040qds.c] Acked-by: York Sun --- .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 21 +++++++++++++++++++ arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 17 +++++++++++++++ arch/powerpc/include/asm/fsl_serdes.h | 1 + board/freescale/b4860qds/b4860qds.c | 16 -------------- board/freescale/corenet_ds/corenet_ds.c | 14 ------------- board/freescale/p2041rdb/p2041rdb.c | 14 ------------- board/freescale/t1040qds/t1040qds.c | 14 ------------- board/freescale/t4qds/t4240qds.c | 16 -------------- 8 files changed, 39 insertions(+), 74 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 39d9409d64..25db899e5f 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -201,3 +201,24 @@ void fsl_serdes_init(void) #endif } + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: +#if defined(CONFIG_T4240QDS) + return "???"; +#else + return "122.88"; +#endif + } +} + diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 680b5222bc..ba22f90a6f 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -858,3 +858,20 @@ void fsl_serdes_init(void) } #endif } + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: + return "150"; + } +} + diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 1106d28058..cce892ce90 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -86,6 +86,7 @@ enum srds { int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); +const char *serdes_clock_to_string(u32 clock); #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index f74651c520..f6b012dbbc 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -457,22 +457,6 @@ static int serdes_refclock(u8 sw, u8 sdclk) return ret; } -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - case SRDS_PLLCR0_RFCK_SEL_161_13: - return "161.13"; - default: - return "122.88"; - } -} - #define NUM_SRDS_BANKS 2 int misc_init_r(void) diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 60e2100af3..9212372fee 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -127,20 +127,6 @@ int board_early_init_r(void) return 0; } -static const char *serdes_clock_to_string(u32 clock) -{ - switch(clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - default: - return "150"; - } -} - #define NUM_SRDS_BANKS 3 int misc_init_r(void) diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 60694a6723..8554512df6 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -155,20 +155,6 @@ unsigned long get_board_sys_clk(unsigned long dummy) } } -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - default: - return "150"; - } -} - #define NUM_SRDS_BANKS 2 int misc_init_r(void) diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 5abb18a260..2aa176c7a2 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -160,20 +160,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - default: - return "Unknown frequency"; - } -} - #define NUM_SRDS_BANKS 2 int misc_init_r(void) { diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 0c1a4fbd9f..79b770b488 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -608,22 +608,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - case SRDS_PLLCR0_RFCK_SEL_161_13: - return "161.1328125"; - default: - return "???"; - } -} - int misc_init_r(void) { u8 sw; -- 2.39.5