From 9868a36dfb8de4bb98b48e4f4eb912312d67279e Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Thu, 12 Nov 2009 11:02:17 -0500 Subject: [PATCH] TI Davinci timer.c: Remove volatiles and memory mapped structures Remove volatiles and memory mapped structure accesses and replace with readl and writel macro usage. Signed-off-by: Nick Thompson --- cpu/arm926ejs/davinci/timer.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c index 80751add84..7c2c208253 100644 --- a/cpu/arm926ejs/davinci/timer.c +++ b/cpu/arm926ejs/davinci/timer.c @@ -38,8 +38,9 @@ */ #include +#include -typedef volatile struct { +struct davinci_timer { u_int32_t pid12; u_int32_t emumgt; u_int32_t na1; @@ -51,9 +52,10 @@ typedef volatile struct { u_int32_t tcr; u_int32_t tgcr; u_int32_t wdtcr; -} davinci_timer; +}; -davinci_timer *timer = (davinci_timer *)CONFIG_SYS_TIMERBASE; +static struct davinci_timer * const timer = + (struct davinci_timer *)CONFIG_SYS_TIMERBASE; #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) #define TIM_CLK_DIV 16 @@ -64,30 +66,30 @@ static ulong lastinc; int timer_init(void) { /* We are using timer34 in unchained 32-bit mode, full speed */ - timer->tcr = 0x0; - timer->tgcr = 0x0; - timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8); - timer->tim34 = 0x0; - timer->prd34 = TIMER_LOAD_VAL; + writel(0x0, &timer->tcr); + writel(0x0, &timer->tgcr); + writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr); + writel(0x0, &timer->tim34); + writel(TIMER_LOAD_VAL, &timer->prd34); lastinc = 0; timestamp = 0; - timer->tcr = 2 << 22; + writel(2 << 22, &timer->tcr); return(0); } void reset_timer(void) { - timer->tcr = 0x0; - timer->tim34 = 0; + writel(0x0, &timer->tcr); + writel(0x0, &timer->tim34); lastinc = 0; timestamp = 0; - timer->tcr = 2 << 22; + writel(2 << 22, &timer->tcr); } static ulong get_timer_raw(void) { - ulong now = timer->tim34; + ulong now = readl(&timer->tim34); if (now >= lastinc) { /* normal mode */ -- 2.39.5