From 9984fa215eca9d0ab1a993439b9a1e767ebe32fb Mon Sep 17 00:00:00 2001 From: richardbarry Date: Tue, 10 Sep 2013 13:01:48 +0000 Subject: [PATCH] Update Keil XMC1000 to later version. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2035 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../Keil_Specific/system_XMC1100.c | 55 +++++++++++++---- .../Keil_Specific/system_XMC1200.c | 57 ++++++++++++++---- .../Keil_Specific/system_XMC1300.c | 59 ++++++++++++++----- .../RTOSDemo.uvopt | 46 +++++++-------- .../main.c | 2 +- .../settings/RTOSDemo.wsdt | 8 +-- 6 files changed, 160 insertions(+), 67 deletions(-) diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1100.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1100.c index 99884b3e9..95d7a36bd 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1100.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1100.c @@ -2,8 +2,8 @@ * @file system_XMC1100.c * @brief Device specific initialization for the XMC1100-Series according * to CMSIS - * @version V1.2 - * @date 13 Dec 2012 + * @version V1.4 + * @date 01 Feb 2013 * * @note * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. @@ -28,6 +28,8 @@ /* * *************************** Change history ******************************** * V1.2, 13 Dec 2012, PKB : Created change history table + * V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation + * V1.3, 01 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK */ #include "system_XMC1100.h" @@ -41,14 +43,23 @@ extern uint32_t AllowClkInitByStartup(void); /*---------------------------------------------------------------------------- Clock Global defines *----------------------------------------------------------------------------*/ -#define DCO_DCLK 64000000UL - +#define DCO_DCLK 64000000UL +#define DCO_DCLK_MULTIPLIER 16384000UL +#define DCO_DCLK_DIVIDER 9UL +#define MCLK_MHZ 32000000UL +#define KHZ_MULTIPLIER 1000UL +#define FRACBITS 8UL /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ +/*!< System Clock Frequency (Core Clock) (MCLK on TIMM1) */ uint32_t SystemCoreClock; +/*---------------------------------------------------------------------------- + Fixed point math definitions + *----------------------------------------------------------------------------*/ +typedef int32_t Q_24_8; +typedef int32_t Q_15_0; /** * @brief Setup the microcontroller system. @@ -57,6 +68,7 @@ uint32_t SystemCoreClock; */ void SystemInit(void) { + /* * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE * Clock app. @@ -80,20 +92,39 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - uint32_t IDIV, CLKCR; + uint32_t IDIV, FDIV, CLKCR, Clock; - CLKCR = SCU_CLOCK -> CLKCR; - - IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; + CLKCR = SCU_CLK -> CLKCR; + IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos; + FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos; if(IDIV) { - SystemCoreClock = DCO_DCLK / (2 * IDIV ); + /* Divider is enabled and used */ + if(0 == FDIV) + { + /* No fractional divider, so MCLK = DCO_Clk / (2 * IDIV) */ + Clock = MCLK_MHZ / IDIV; + } + else + { + /* Both integer and fractional divider must be considered */ + /* 1. IDIV + FDIV/256 */ + Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV; + + /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */ + Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum; + Clock = ((uint32_t)ClockVal) * KHZ_MULTIPLIER; + Clock = Clock >> DCO_DCLK_DIVIDER; + } } else { - /* Divider bypassed */ - SystemCoreClock = DCO_DCLK; + /* Divider bypassed. Simply divide DCO_DCLK by 2 */ + Clock = MCLK_MHZ; } + + /* Finally with the math class over, update SystemCoreClock */ + SystemCoreClock = Clock; } diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1200.c index 5b06bc4c1..9d559e7e9 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1200.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1200.c @@ -2,8 +2,8 @@ * @file system_XMC1200.c * @brief Device specific initialization for the XMC1200-Series according * to CMSIS - * @version V1.2 - * @date 13 Dec 2012 + * @version V1.4 + * @date 01 Feb 2013 * * @note * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. @@ -28,9 +28,11 @@ /* * *************************** Change history ******************************** * V1.2, 13 Dec 2012, PKB : Created change history table + * V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation + * V1.4, 01 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK */ -#include "System_XMC1200.h" +#include "system_XMC1200.h" #include /*--------------------------------------------------------------------------- @@ -41,14 +43,23 @@ extern uint32_t AllowClkInitByStartup(void); /*---------------------------------------------------------------------------- Clock Global defines *----------------------------------------------------------------------------*/ -#define DCO_DCLK 64000000UL - +#define DCO_DCLK 64000000UL +#define DCO_DCLK_MULTIPLIER 16384000UL +#define DCO_DCLK_DIVIDER 9UL +#define MCLK_MHZ 32000000UL +#define KHZ_MULTIPLIER 1000UL +#define FRACBITS 8UL /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ +/*!< System Clock Frequency (Core Clock) (MCLK on TIMM1) */ uint32_t SystemCoreClock; +/*---------------------------------------------------------------------------- + Fixed point math definitions + *----------------------------------------------------------------------------*/ +typedef int32_t Q_24_8; +typedef int32_t Q_15_0; /** * @brief Setup the microcontroller system. @@ -57,6 +68,7 @@ uint32_t SystemCoreClock; */ void SystemInit(void) { + /* * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE * Clock app. @@ -80,20 +92,39 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - uint32_t IDIV, CLKCR; + uint32_t IDIV, FDIV, CLKCR, Clock; - CLKCR = SCU_CLOCK -> CLKCR; - - IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; + CLKCR = SCU_CLK -> CLKCR; + IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos; + FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos; if(IDIV) { - SystemCoreClock = DCO_DCLK / (2 * IDIV ); + /* Divider is enabled and used */ + if(0 == FDIV) + { + /* No fractional divider, so MCLK = DCO_Clk / (2 * IDIV) */ + Clock = MCLK_MHZ / IDIV; + } + else + { + /* Both integer and fractional divider must be considered */ + /* 1. IDIV + FDIV/256 */ + Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV; + + /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */ + Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum; + Clock = ((uint32_t)ClockVal) * KHZ_MULTIPLIER; + Clock = Clock >> DCO_DCLK_DIVIDER; + } } else { - /* Divider bypassed */ - SystemCoreClock = DCO_DCLK; + /* Divider bypassed. Simply divide DCO_DCLK by 2 */ + Clock = MCLK_MHZ; } + + /* Finally with the math class over, update SystemCoreClock */ + SystemCoreClock = Clock; } diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1300.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1300.c index c83e3fec6..44d0adc21 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1300.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1300.c @@ -2,8 +2,8 @@ * @file system_XMC1300.c * @brief Device specific initialization for the XMC1300-Series according * to CMSIS - * @version V1.2 - * @date 13 Dec 2012 + * @version V1.4 + * @date 01 Feb 2013 * * @note * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. @@ -26,8 +26,10 @@ * ******************************************************************************/ /* - * ************************** Change history ********************************* - * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_ + * *************************** Change history ******************************** + * V1.2, 13 Dec 2012, PKB : Created change history table + * V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation + * V1.4, 02 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK */ #include "system_XMC1300.h" @@ -41,14 +43,23 @@ extern uint32_t AllowClkInitByStartup(void); /*---------------------------------------------------------------------------- Clock Global defines *----------------------------------------------------------------------------*/ -#define DCO_DCLK 64000000UL - +#define DCO_DCLK 64000000UL +#define DCO_DCLK_MULTIPLIER 16384000UL +#define DCO_DCLK_DIVIDER 9UL +#define MCLK_MHZ 32000000UL +#define KHZ_MULTIPLIER 1000UL +#define FRACBITS 8UL /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ +/*!< System Clock Frequency (Core Clock) (MCLK on TIMM1) */ uint32_t SystemCoreClock; +/*---------------------------------------------------------------------------- + Fixed point math definitions + *----------------------------------------------------------------------------*/ +typedef int32_t Q_24_8; +typedef int32_t Q_15_0; /** * @brief Setup the microcontroller system. @@ -57,6 +68,7 @@ uint32_t SystemCoreClock; */ void SystemInit(void) { + /* * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE * Clock app. @@ -80,20 +92,39 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - uint32_t IDIV, CLKCR; + uint32_t IDIV, FDIV, CLKCR, Clock; - CLKCR = SCU_CLOCK -> CLKCR; - - IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; + CLKCR = SCU_CLK -> CLKCR; + IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos; + FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos; if(IDIV) { - SystemCoreClock = DCO_DCLK / (2 * IDIV ); + /* Divider is enabled and used */ + if(0 == FDIV) + { + /* No fractional divider, so MCLK = DCO_Clk / (2 * IDIV) */ + Clock = MCLK_MHZ / IDIV; + } + else + { + /* Both integer and fractional divider must be considered */ + /* 1. IDIV + FDIV/256 */ + Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV; + + /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */ + Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum; + Clock = ((uint32_t)ClockVal) * KHZ_MULTIPLIER; + Clock = Clock >> DCO_DCLK_DIVIDER; + } } else { - /* Divider bypassed */ - SystemCoreClock = DCO_DCLK; + /* Divider bypassed. Simply divide DCO_DCLK by 2 */ + Clock = MCLK_MHZ; } + + /* Finally with the math class over, update SystemCoreClock */ + SystemCoreClock = Clock; } diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvopt index 56256eee2..efd8fb8b6 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvopt +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvopt @@ -73,7 +73,7 @@ 1 0 - 1 + 0 255 @@ -150,7 +150,7 @@ 0 DLGUARM - / + 0 @@ -345,7 +345,7 @@ 0 DLGUARM - / + 0 @@ -497,7 +497,7 @@ 1 0 - 0 + 1 255 @@ -574,7 +574,7 @@ 0 DLGUARM - + / 0 @@ -703,8 +703,8 @@ 0 0 0 - 0 - 0 + 1 + 1 0 .\Keil_Specific\system_XMC1300.c system_XMC1300.c @@ -789,10 +789,10 @@ 1 0 0 - 26 + 0 0 - 0 - 0 + 1028 + 1036 0 ..\..\Source\queue.c queue.c @@ -807,8 +807,8 @@ 0 0 0 - 2152 - 2153 + 0 + 0 0 ..\..\Source\tasks.c tasks.c @@ -823,8 +823,8 @@ 0 0 0 - 0 - 0 + 253 + 261 0 ..\..\Source\portable\RVDS\ARM_CM0\port.c port.c @@ -861,10 +861,10 @@ 1 0 0 - 0 + 45 0 - 57 - 122 + 63 + 96 0 .\main.c main.c @@ -959,8 +959,8 @@ 0 15 0 - 38 - 74 + 0 + 0 0 .\ParTest_XMC1100.c ParTest_XMC1100.c @@ -975,8 +975,8 @@ 0 15 0 - 44 - 74 + 0 + 0 0 .\ParTest_XMC1300.c ParTest_XMC1300.c @@ -999,8 +999,8 @@ 0 0 0 - 0 - 0 + 411 + 419 0 ..\Common\Minimal\dynamic.c dynamic.c diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c index c4d6fcc20..d762e22f2 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c @@ -93,7 +93,7 @@ /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.wsdt index 3bb336da8..0c08a5408 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.wsdt +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.wsdt @@ -25,7 +25,7 @@ - + TabID-23707-15152 @@ -37,7 +37,7 @@ - 0 + 0 TabID-19002-15240 @@ -47,7 +47,7 @@ TabID-13685-21727Debug LogDebug-Log - 0 + 0 @@ -60,7 +60,7 @@ - iaridepm.enu1-2-2740435-2-2200200119048203666260119755601-2-21981682-2-216842001002381203666119048203666 + iaridepm.enu1-2-2740435-2-2200200119048203666260119755601-2-21981682-2-216842001002381203666119048203666 -- 2.39.2