From 9d063f686ddb3582d0cc5a9a6c9abcff0bb537cf Mon Sep 17 00:00:00 2001 From: richardbarry Date: Tue, 21 Jul 2009 19:35:59 +0000 Subject: [PATCH] Correct interrupt priority assignment. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@822 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h | 4 +++- Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c | 2 +- Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h | 3 +++ Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c | 2 +- 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h index 1458e9e73..2ce1eaab7 100644 --- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h +++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h @@ -132,7 +132,9 @@ to exclude the API function. */ /* Priority 5, or 160 as only the top three bits are implemented. */ #define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 5 << (8 - configPRIO_BITS) ) - +/* Priorities passed to NVIC_SetPriority() do not require shifting as the +function does the shifting itself. */ +#define configEMAC_INTERRUPT_PRIORITY 5 diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c index 6f56b92cd..71ad5ce3d 100644 --- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c +++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c @@ -142,7 +142,7 @@ extern void ( vEMAC_ISR_Wrapper )( void ); /* Set the interrupt priority to the max permissible to cause some interrupt nesting. */ - NVIC_SetPriority( ENET_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY ); + NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY ); /* Enable the interrupt. */ NVIC_EnableIRQ( ENET_IRQn ); diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h b/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h index 1458e9e73..f63270552 100644 --- a/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h +++ b/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h @@ -132,6 +132,9 @@ to exclude the API function. */ /* Priority 5, or 160 as only the top three bits are implemented. */ #define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 5 << (8 - configPRIO_BITS) ) +/* Priorities passed to NVIC_SetPriority() do not require shifting as the +function does the shifting itself. */ +#define configEMAC_INTERRUPT_PRIORITY 5 diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c index ea9e43e35..deab7e8f8 100644 --- a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c +++ b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c @@ -142,7 +142,7 @@ extern void ( vEMAC_ISR_Wrapper )( void ); /* Set the interrupt priority to the max permissible to cause some interrupt nesting. */ - NVIC_SetPriority( ENET_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY ); + NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY ); /* Enable the interrupt. */ NVIC_EnableIRQ( ENET_IRQn ); -- 2.39.2