From a07422c26cb0a659c7615d6c0aa2cf09d8a48829 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C3=98yvind=20Harboe?= Date: Sun, 25 Oct 2009 18:29:17 +0100 Subject: [PATCH] fix syntax of mww phys. --- tcl/board/atmel_at91sam9260-ek.cfg | 2 +- tcl/board/mini2440.cfg | 60 +++++++++++++++--------------- tcl/board/olimex_sam9_l9260.cfg | 2 +- tcl/board/unknown_at91sam9260.cfg | 2 +- tcl/target/davinci.cfg | 22 +++++------ 5 files changed, 44 insertions(+), 44 deletions(-) diff --git a/tcl/board/atmel_at91sam9260-ek.cfg b/tcl/board/atmel_at91sam9260-ek.cfg index 06a54e23..e74ccf46 100644 --- a/tcl/board/atmel_at91sam9260-ek.cfg +++ b/tcl/board/atmel_at91sam9260-ek.cfg @@ -24,7 +24,7 @@ $_TARGETNAME configure -event reset-start { jtag_rclk 5 halt # RSTC_MR : enable user reset, MMU may be enabled... use physical address - arm926ejs mww phys 0xfffffd08 0xa5000501 + mww phys 0xfffffd08 0xa5000501 } $_TARGETNAME configure -event reset-init { diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 29819501..90acafa0 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -177,10 +177,10 @@ proc init_2440 { } { # usb clock are off 12mHz xtal #----------------------------------------------- - arm920t mww phys 0x4C000014 0x00000005 # Clock Divider control Reg - arm920t mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register - arm920t mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg - arm920t mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg + mww phys 0x4C000014 0x00000005 # Clock Divider control Reg + mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register + mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg + mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg #----------------------------------------------- # Configure Memory controller @@ -188,45 +188,45 @@ proc init_2440 { } { # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7 #----------------------------------------------- - arm920t mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width - arm920t mww phys 0x48000010 0x00001112 # BANKCON4 - ? - arm920t mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM - arm920t mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM - arm920t mww phys 0x48000024 0x008E04EB # REFRESH - DRAM - arm920t mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM - arm920t mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM - arm920t mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM + mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width + mww phys 0x48000010 0x00001112 # BANKCON4 - ? + mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM + mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM + mww phys 0x48000024 0x008E04EB # REFRESH - DRAM + mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM + mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM + mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM #----------------------------------------------- # Now port configuration for enables for memory # and other stuff. #----------------------------------------------- - arm920t mww phys 0x56000000 0x007FFFFF # GPACON + mww phys 0x56000000 0x007FFFFF # GPACON - arm920t mww phys 0x56000010 0x00295559 # GPBCON - arm920t mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE) - arm920t mww phys 0x56000014 0x000007C2 # GPBDAT + mww phys 0x56000010 0x00295559 # GPBCON + mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE) + mww phys 0x56000014 0x000007C2 # GPBDAT - arm920t mww phys 0x56000020 0xAAAAA6AA # GPCCON - arm920t mww phys 0x56000028 0x0000FFFF # GPCUP - arm920t mww phys 0x56000024 0x00000020 # GPCDAT + mww phys 0x56000020 0xAAAAA6AA # GPCCON + mww phys 0x56000028 0x0000FFFF # GPCUP + mww phys 0x56000024 0x00000020 # GPCDAT - arm920t mww phys 0x56000030 0xAAAAAAAA # GPDCON - arm920t mww phys 0x56000038 0x0000FFFF # GPDUP + mww phys 0x56000030 0xAAAAAAAA # GPDCON + mww phys 0x56000038 0x0000FFFF # GPDUP - arm920t mww phys 0x56000040 0xAAAAAAAA # GPECON - arm920t mww phys 0x56000048 0x0000FFFF # GPEUP + mww phys 0x56000040 0xAAAAAAAA # GPECON + mww phys 0x56000048 0x0000FFFF # GPEUP - arm920t mww phys 0x56000050 0x00001555 # GPFCON - arm920t mww phys 0x56000058 0x0000007F # GPFUP - arm920t mww phys 0x56000054 0x00000000 # GPFDAT + mww phys 0x56000050 0x00001555 # GPFCON + mww phys 0x56000058 0x0000007F # GPFUP + mww phys 0x56000054 0x00000000 # GPFDAT - arm920t mww phys 0x56000060 0x00150114 # GPGCON - arm920t mww phys 0x56000068 0x0000007F # GPGUP + mww phys 0x56000060 0x00150114 # GPGCON + mww phys 0x56000068 0x0000007F # GPGUP - arm920t mww phys 0x56000070 0x0015AAAA # GPHCON - arm920t mww phys 0x56000078 0x000003FF # GPGUP + mww phys 0x56000070 0x0015AAAA # GPHCON + mww phys 0x56000078 0x000003FF # GPGUP } diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg index 935d7cd5..5c4714e1 100644 --- a/tcl/board/olimex_sam9_l9260.cfg +++ b/tcl/board/olimex_sam9_l9260.cfg @@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start { # RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may # be enabled... use physical address. - arm926ejs mww phys 0xfffffd08 0xa5000501 + mww phys 0xfffffd08 0xa5000501 } $_TARGETNAME configure -event reset-init { diff --git a/tcl/board/unknown_at91sam9260.cfg b/tcl/board/unknown_at91sam9260.cfg index 7286a967..2abd367f 100644 --- a/tcl/board/unknown_at91sam9260.cfg +++ b/tcl/board/unknown_at91sam9260.cfg @@ -18,7 +18,7 @@ $_TARGETNAME configure -event reset-start { jtag_rclk 3 halt # RSTC_MR : enable user reset, MMU may be enabled... use physical address - arm926ejs mww phys 0xfffffd08 0xa5000501 + mww phys 0xfffffd08 0xa5000501 } diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index c14c98ea..ee840c8d 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -204,34 +204,34 @@ proc davinci_wdog_reset {} { # # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt - arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr $timer2_phys + 0x28] 0x00004000 # # Part II -- in case watchdog hasn't been set up # # TCR: disable, force internal clock source - arm926ejs mww phys [expr $timer2_phys + 0x20] 0 + mww phys [expr $timer2_phys + 0x20] 0 # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state) - arm926ejs mww phys [expr $timer2_phys + 0x24] 0 - arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b + mww phys [expr $timer2_phys + 0x24] 0 + mww phys [expr $timer2_phys + 0x24] 0x110b # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers # so watchdog triggers ASAP - arm926ejs mww phys [expr $timer2_phys + 0x10] 0 - arm926ejs mww phys [expr $timer2_phys + 0x14] 0 - arm926ejs mww phys [expr $timer2_phys + 0x18] 0 - arm926ejs mww phys [expr $timer2_phys + 0x1c] 0 + mww phys [expr $timer2_phys + 0x10] 0 + mww phys [expr $timer2_phys + 0x14] 0 + mww phys [expr $timer2_phys + 0x18] 0 + mww phys [expr $timer2_phys + 0x1c] 0 # WDTCR: put into pre-active state, then active - arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000 - arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000 + mww phys [expr $timer2_phys + 0x28] 0xa5c64000 + mww phys [expr $timer2_phys + 0x28] 0xda7e4000 # # Part III -- it's ready to rumble # # WDTCR: write invalid WDKEY to trigger reset - arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr $timer2_phys + 0x28] 0x00004000 } -- 2.39.5