From aaf87f03ad709ff9f00819ef1eb001e878ad0a54 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 13 Oct 2015 11:01:27 -0300 Subject: [PATCH] pci: pcie_imx: Fix hang on mx6qp PCI driver currently hangs on mx6qp. Toggle the reset bit with the appropriate timings to fix the issue. Based on the FSL kernel driver implementation. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- arch/arm/include/asm/arch-mx6/iomux.h | 2 ++ drivers/pci/pcie_imx.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index 9b3a91f076..907cb408ff 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -18,6 +18,8 @@ #define IOMUXC_GPR1_REF_SSP_EN (1 << 16) #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) +#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29) + /* * IOMUXC_GPR5 bit fields */ diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 1568f20c1a..f1e189edd5 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -19,6 +19,7 @@ #include #include #include +#include #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 @@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, static int imx6_pcie_assert_core_reset(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (is_mx6dqp()) + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); + #if defined(CONFIG_MX6SX) struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; @@ -536,6 +541,9 @@ static int imx6_pcie_deassert_core_reset(void) enable_pcie_clock(); + if (is_mx6dqp()) + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); + /* * Wait for the clock to settle a bit, when the clock are sourced * from the CPU, we need about 30 ms to settle. -- 2.39.5