From af2536088e2feae2cf1274f48376e3310e0f709e Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Fri, 18 May 2012 06:04:17 +0000 Subject: [PATCH] powerpc/p1022ds: add support for SPI and SD boot Add TLB mappings, board target options, and configuration items need for SPI/SD boot. Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them. Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B. Signed-off-by: Matthew McClintock Signed-off-by: Jerry Huang Signed-off-by: Jiang Yutang Signed-off-by: Andy Fleming --- board/freescale/p1022ds/p1022ds.c | 4 +++ board/freescale/p1022ds/tlb.c | 14 +++++++++ boards.cfg | 4 +++ include/configs/P1022DS.h | 51 +++++++++++++++++++++++++++++-- 4 files changed, 70 insertions(+), 3 deletions(-) diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 56dfcce410..25fdc2a740 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -39,6 +39,10 @@ int board_early_init_f(void) /* Set pmuxcr to allow both i2c1 and i2c2 */ setbits_be32(&gur->pmuxcr, 0x1000); +#ifdef CONFIG_SYS_RAMBOOT + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); +#endif /* Read back the register to synchronize the write. */ in_be32(&gur->pmuxcr); diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index e6201127a9..71e71f7070 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -71,6 +71,20 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1), + +#ifdef CONFIG_SYS_RAMBOOT + /* *I*G - eSDHC/eSPI/NAND boot */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), + + /* map the second 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_1G, 1), +#endif +# }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 1af87c0f0c..05987632f4 100644 --- a/boards.cfg +++ b/boards.cfg @@ -731,6 +731,10 @@ P1021RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freesca P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale +P1022DS_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:SPIFLASH +P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SPIFLASH +P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD +P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SDCARD P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 50d3f8d703..86217a46db 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -18,6 +18,22 @@ #define CONFIG_PHYS_64BIT #endif +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ @@ -402,11 +418,40 @@ /* * Environment */ +#ifdef CONFIG_SYS_RAMBOOT +#ifdef CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_NAND_U_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_LOADS_ECHO #define CONFIG_SYS_LOADS_BAUD_CHANGE -- 2.39.5