From bcd5c10086f198bfc1643aabd22e9a82802545e2 Mon Sep 17 00:00:00 2001
From: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Wed, 1 Oct 2014 09:30:35 +0000
Subject: [PATCH] Demo project only:  Cyclone V SoC now running from external
 RAM.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2308 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---
 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject |  2 +-
 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c    | 14 +++++++++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject
index 612e1a4a7..d94e97779 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject
+++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject
@@ -41,7 +41,7 @@
 							</tool>
 							<tool id="cdt.managedbuild.tool.gnu.cross.c.linker.451869963" name="Cross GCC Linker" superClass="cdt.managedbuild.tool.gnu.cross.c.linker">
 								<option id="gnu.c.link.option.other.1746198439" name="Other options (-Xlinker [option])" superClass="gnu.c.link.option.other" valueType="stringList">
-									<listOptionValue builtIn="false" value="-TcycloneV-dk-oc-ram.ld"/>
+									<listOptionValue builtIn="false" value="-TcycloneV-dk-ram.ld"/>
 									<listOptionValue builtIn="false" value="--defsym=__cs3_isr_irq=FreeRTOS_IRQ_Handler"/>
 									<listOptionValue builtIn="false" value="--defsym=__cs3_isr_swi=FreeRTOS_SWI_Handler"/>
 									<listOptionValue builtIn="false" value="-Map=RTOSDemo.map"/>
diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c
index f2345e7e1..e7000fcab 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c
@@ -29,9 +29,21 @@ int main( void )
 
 static void prvSetupHardware( void )
 {
+extern uint8_t __cs3_interrupt_vector;
+uint32_t ulSCTLR, ulVectorTable = ( uint32_t ) &__cs3_interrupt_vector;
+const uint32_t ulVBit = 13U;
+
 	alt_int_global_init();
+
+	/* Clear SCTLR.V for low vectors and map the vector table to the beginning
+	of the code. */
+	__asm( "MRC p15, 0, %0, c1, c0, 0" : "=r" ( ulSCTLR ) );
+	ulSCTLR &= ~( 1 << ulVBit );
+	__asm( "MCR p15, 0, %0, c1, c0, 0" : : "r" ( ulSCTLR ) );
+	__asm( "MCR p15, 0, %0, c12, c0, 0" : : "r" ( ulVectorTable ) );
+
 	cache_init();
-	//_RB_mmu_init();
+	mmu_init();
 }
 /*-----------------------------------------------------------*/
 
-- 
2.39.5