From c57e42575c8aec2d7ba8758ce073f277645c6dfa Mon Sep 17 00:00:00 2001 From: richardbarry Date: Sat, 21 Jun 2008 17:35:41 +0000 Subject: [PATCH] Correct PLL setting for the defined configCPU_CLOCK_HZ setting. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@399 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- Demo/ARM7_LPC2129_IAR/main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Demo/ARM7_LPC2129_IAR/main.c b/Demo/ARM7_LPC2129_IAR/main.c index 0d941447f..4c7a22fe2 100644 --- a/Demo/ARM7_LPC2129_IAR/main.c +++ b/Demo/ARM7_LPC2129_IAR/main.c @@ -112,7 +112,7 @@ #define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) /* Constants to setup the PLL. */ -#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_MUL_5 ( ( unsigned portCHAR ) 0x0004 ) #define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) #define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) #define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) @@ -188,8 +188,8 @@ void main( void ) static void prvSetupHardware( void ) { - /* Setup the PLL to multiply the XTAL input by 4. */ - PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + /* Setup the PLL to multiply the XTAL input by 5. */ + PLLCFG = ( mainPLL_MUL_5 | mainPLL_DIV_1 ); /* Activate the PLL by turning it on then feeding the correct sequence of bytes. */ -- 2.39.5