From c57fc28947e248fb03c49a28b467686299895055 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 31 Oct 2008 05:07:04 -0500 Subject: [PATCH] NAND: Add NAND support for MPC8536DS board This patch defines 1M TLB&LAW size for NAND on MPC8536DS, assigns 0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file. It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image. Singed-off-by: Jason Jin Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- board/freescale/mpc8536ds/law.c | 1 + board/freescale/mpc8536ds/tlb.c | 5 +++ include/configs/MPC8536DS.h | 56 +++++++++++++++++++++++++++++++-- 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 8013d416e6..0861fa7080 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -38,6 +38,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index ebf41ce4fd..c81a959220 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -66,6 +66,11 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1M, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index c4389cc446..fff888abc6 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -155,8 +155,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable * * Localbus non-cacheable - * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable + * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable @@ -243,6 +244,57 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ + CONFIG_SYS_NAND_BASE + 0x40000, \ + CONFIG_SYS_NAND_BASE + 0x80000, \ + CONFIG_SYS_NAND_BASE + 0xC0000} +#define CONFIG_SYS_MAX_NAND_DEVICE 4 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ + | (2< 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -- 2.39.5