From c8c778882570c36ff51b83b9c7d1e575566bc4ce Mon Sep 17 00:00:00 2001
From: Oleksij Rempel <o.rempel@pengutronix.de>
Date: Thu, 28 Jun 2018 12:18:07 +0200
Subject: [PATCH] target|board: Add Intel (Altera) Arria 10 target and related
 board

Target information about this SoC can be found here:
https://www.altera.com/products/fpga/arria-series/arria-10/overview.html

Achilles Instant-Development Kit Arria 10 SoC SoM:
https://www.reflexces.com/products-solutions/development-kits/arria-10/achilles-instant-development-kit-arria-10-soc-som

Change-Id: Id78c741be6a8b7d3a70f37d41088e47ee61b437a
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/4583
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
---
 .../reflexces_achilles_i-dev_kit_arria10.cfg  | 13 +++++
 tcl/target/altera_fpgasoc_arria10.cfg         | 56 +++++++++++++++++++
 2 files changed, 69 insertions(+)
 create mode 100644 tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg
 create mode 100644 tcl/target/altera_fpgasoc_arria10.cfg

diff --git a/tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg b/tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg
new file mode 100644
index 00000000..a6e80650
--- /dev/null
+++ b/tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg
@@ -0,0 +1,13 @@
+# Achilles Instant-Development Kit Arria 10 SoC SoM
+# https://www.reflexces.com/products-solutions/achilles-instant-development-kit-arria-10-soc-som
+#
+
+if { [info exists USE_EXTERNAL_DEBUGGER] } {
+	echo "Using external debugger"
+} else {
+	source [find interface/altera-usb-blaster2.cfg]
+	usb_blaster_device_desc "Arria10 IDK"
+}
+
+source [find fpga/altera-10m50.cfg]
+source [find target/altera_fpgasoc_arria10.cfg]
diff --git a/tcl/target/altera_fpgasoc_arria10.cfg b/tcl/target/altera_fpgasoc_arria10.cfg
new file mode 100644
index 00000000..c9c5ab66
--- /dev/null
+++ b/tcl/target/altera_fpgasoc_arria10.cfg
@@ -0,0 +1,56 @@
+# Intel (Altera) Arria10 FPGA SoC
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME arria10
+}
+
+# ARM CoreSight Debug Access Port (dap HPS)
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID
+
+# Subsidiary TAP: fpga (tap)
+# See Intel Arria 10 Handbook
+# https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
+# Intel Arria 10 GX 160  0x02ee20dd
+# Intel Arria 10 GX 220  0x02e220dd
+# Intel Arria 10 GX 270  0x02ee30dd
+# Intel Arria 10 GX 320  0x02e230dd
+# Intel Arria 10 GX 480  0x02e240dd
+# Intel Arria 10 GX 570  0x02ee50dd
+# Intel Arria 10 GX 660  0x02e250dd
+# Intel Arria 10 GX 900  0x02ee60dd
+# Intel Arria 10 GX 1150 0x02e660dd
+# Intel Arria 10 GT 900  0x02e260dd
+# Intel Arria 10 GT 1150 0x02e060dd
+# Intel Arria 10 SX 160  0x02e620dd
+# Intel Arria 10 SX 220  0x02e020dd
+# Intel Arria 10 SX 270  0x02e630dd
+# Intel Arria 10 SX 320  0x02e030dd
+# Intel Arria 10 SX 480  0x02e040dd
+# Intel Arria 10 SX 570  0x02e650dd
+# Intel Arria 10 SX 660  0x02e050dd
+jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \
+	-expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \
+	-expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \
+	-expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \
+	-expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \
+	-expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \
+	-expected-id 0x02e050dd
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+#
+# Cortex-A9 target
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0
+target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \
+	-defer-examine
+target smp $_TARGETNAME.0 $_TARGETNAME.1
-- 
2.39.5