From c9c94d5d7e8ca6a9578732cecc15710bad0cb319 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:09:33 +0200 Subject: [PATCH] mips: bmips: add bcm6345-gpio driver support for BCM63268 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This SoC has one gpio bank divided into two 32 bit registers, with a total of 52 GPIOs. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm63268.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 3d810473ec..3eda77db5a 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -63,6 +63,25 @@ mask = <0x1>; }; + gpio1: gpio-controller@100000c0 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c0 0x4>, <0x100000c8 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <20>; + + status = "disabled"; + }; + + gpio0: gpio-controller@100000c4 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c4 0x4>, <0x100000cc 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + uart0: serial@10000180 { compatible = "brcm,bcm6345-uart"; reg = <0x10000180 0x18>; -- 2.39.5