From cf96848bc76c7d680100e914b088ca34ed4e04e0 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 4 Aug 2015 22:12:32 -0500 Subject: [PATCH] ddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKS MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Fix build error for socfpga_cyclone5_defconfig: board/altera/socfpga/wrap_sdram_config.c:245:26: error: ‘RW_MGR_MEM_NUMBER_OF_RANKS’ undeclared here (not in a function) make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1 Signed-off-by: Dinh Nguyen --- board/altera/socfpga/qts/sequencer_defines.h | 1 + 1 file changed, 1 insertion(+) diff --git a/board/altera/socfpga/qts/sequencer_defines.h b/board/altera/socfpga/qts/sequencer_defines.h index 32f13ac9f8..bfe5b2719f 100644 --- a/board/altera/socfpga/qts/sequencer_defines.h +++ b/board/altera/socfpga/qts/sequencer_defines.h @@ -103,6 +103,7 @@ #define RW_MGR_MEM_IF_READ_DQS_WIDTH 5 #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5 #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 #define RW_MGR_MEM_ODT_WIDTH 1 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 -- 2.39.5